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scripts/templates/body-jekyll-release-post-part-1-liquid.md

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@@ -119,9 +119,32 @@ xpm uninstall --global @xpack-dev-tools/riscv-none-elf-gcc
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## Compliance
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The xPack GNU RISC-V Embedded GCC generally follows the official
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GNU GCC [releases](https://gcc.gnu.org/releases.html)),
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with as little differences as possible.
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The xPack GNU RISC-V Embedded GCC use the official sources,
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with no functional changes:
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- GCC 12.1.0
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- binutils 2.38
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- gdb 12.1
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- newlib 4.2.0.20211231
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- python 3.10.4
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## ISA updates
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Compared to previous releases, starting from 12.x, the compiler
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implements the new RISC-V ISA, which introduces an incompatibility issue,
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and builds might throw error messages like _unrecognized opcode `csrr`_.
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The reason is that csr read/write (`csrr*`/`csrw*`)
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instructions and `fence.i` instruction were separated from the `I`
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extension, becoming two standalone extensions: `Zicsr` and `Zifencei`.
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The solution is to add `_zicsr` and/or `_zifencei` to the
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`-march` option, e.g. `-march=rv32imac` becomes
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`-march=rv32imac_zicsr_zifencei`.
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In Eclipse, until the GUI will be updated, select the *Toolchain Default*
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for _Architecture_ and
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enter the new string separately as _Other target flags_.
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## Supported libraries
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