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lines changed Original file line number Diff line number Diff line change @@ -119,9 +119,32 @@ xpm uninstall --global @xpack-dev-tools/riscv-none-elf-gcc
119119
120120## Compliance
121121
122- The xPack GNU RISC-V Embedded GCC generally follows the official
123- GNU GCC [ releases] ( https://gcc.gnu.org/releases.html ) ),
124- with as little differences as possible.
122+ The xPack GNU RISC-V Embedded GCC use the official sources,
123+ with no functional changes:
124+
125+ - GCC 12.1.0
126+ - binutils 2.38
127+ - gdb 12.1
128+ - newlib 4.2.0.20211231
129+ - python 3.10.4
130+
131+ ## ISA updates
132+
133+ Compared to previous releases, starting from 12.x, the compiler
134+ implements the new RISC-V ISA, which introduces an incompatibility issue,
135+ and builds might throw error messages like _ unrecognized opcode ` csrr ` _ .
136+
137+ The reason is that csr read/write (` csrr* ` /` csrw* ` )
138+ instructions and ` fence.i ` instruction were separated from the ` I `
139+ extension, becoming two standalone extensions: ` Zicsr ` and ` Zifencei ` .
140+
141+ The solution is to add ` _zicsr ` and/or ` _zifencei ` to the
142+ ` -march ` option, e.g. ` -march=rv32imac ` becomes
143+ ` -march=rv32imac_zicsr_zifencei ` .
144+
145+ In Eclipse, until the GUI will be updated, select the * Toolchain Default*
146+ for _ Architecture_ and
147+ enter the new string separately as _ Other target flags_ .
125148
126149## Supported libraries
127150
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