Fix RISCV build

Author: serge-sans-paille

include/xsimd/arch/xsimd_rvv.hpp

@@ -513,7 +513,7 @@ namespace xsimd
                 return __riscv_vset(tmp, 1, hi);
             }
 
-            template <class T, size_t W, std::enable_if_t<W<types::detail::rvv_width_m1, int>::type = 0> D_INLINE rvv_reg_t<T, W * 2> rvvabut(rvv_reg_t<T, W> const& lo, rvv_reg_t<T, W> const& hi) noexcept
+            template <class T, size_t W, std::enable_if_t<W<types::detail::rvv_width_m1, int> = 0> XSIMD_INLINE rvv_reg_t<T, W * 2> rvvabut(rvv_reg_t<T, W> const& lo, rvv_reg_t<T, W> const& hi) noexcept
             {
                 return __riscv_vslideup(lo, hi, lo.vl, lo.vl * 2);
             }
@@ -538,7 +538,7 @@ namespace xsimd
                 typename rvv_reg_t<T, W>::register_type tmp = vv;
                 return tmp;
             }
-            template <class T, size_t W, std::enable_if_t<W<types::detail::rvv_width_m1, int>::type = 0> reg_t<T, W> rvvget_hi(rvv_reg_t<T, W * 2> const& vv) noexcept
+            template <class T, size_t W, std::enable_if_t<W<types::detail::rvv_width_m1, int> = 0> rvv_reg_t<T, W> rvvget_hi(rvv_reg_t<T, W * 2> const& vv) noexcept
             {
                 return __riscv_vslidedown(vv, vv.vl / 2, vv.vl);
             }

include/xsimd/types/xsimd_rvv_register.hpp

@@ -219,6 +219,25 @@ namespace xsimd
                 type get() const { return value; }
                 void set(type v) { value = v; }
             };
+
+            template <size_t div>
+            struct semitype;
+            template <>
+            struct semitype<2>
+            {
+                using type = vuint8mf2_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF2)));
+            };
+            template <>
+            struct semitype<4>
+            {
+                using type = vuint8mf4_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF4)));
+            };
+            template <>
+            struct semitype<8>
+            {
+                using type = vuint8mf8_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF8)));
+            };
+
             //
             // But sometimes we want our storage type to be less than a whole
             // register, while presenting as a whole register to the outside
@@ -233,23 +252,6 @@ namespace xsimd
                 using super = rvv_type_info<T, rvv_width_m1>;
                 static constexpr size_t width = rvv_width_m1 / divisor;
                 using typename super::type;
-                template <size_t div>
-                struct semitype;
-                template <>
-                struct semitype<2>
-                {
-                    using type = vuint8mf2_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF2)));
-                };
-                template <>
-                struct semitype<4>
-                {
-                    using type = vuint8mf4_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF4)));
-                };
-                template <>
-                struct semitype<8>
-                {
-                    using type = vuint8mf8_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF8)));
-                };
                 using fixed_type = typename semitype<divisor>::type;
                 using super::as_bytes;
                 using super::bitcast;