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serge-sans-pailleserge-sans-paille
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-47
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3 files changed

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-47
lines changed

‎include/xsimd/arch/xsimd_altivec.hpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -430,7 +430,7 @@ namespace xsimd
430430
template <class A, class T, size_t I, class = typename std::enable_if<std::is_scalar<T>::value, void>::type>
431431
XSIMD_INLINE batch<T, A> insert(batch<T, A> const& self, T val, index<I> pos, requires_arch<altivec>) noexcept
432432
{
433-
return vec_insert(val, self.data, pos);
433+
return vec_insert(val, self.data, I);
434434
}
435435

436436
// isnan

‎test/CMakeLists.txt‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -141,10 +141,10 @@ set(XSIMD_TESTS
141141
test_bitwise_cast.cpp
142142
test_batch_constant.cpp
143143
# test_batch_manip.cpp
144-
# test_complex_exponential.cpp
145-
# test_complex_hyperbolic.cpp
146-
# test_complex_power.cpp
147-
# test_complex_trigonometric.cpp
144+
test_complex_exponential.cpp
145+
test_complex_hyperbolic.cpp
146+
test_complex_power.cpp
147+
test_complex_trigonometric.cpp
148148
# test_conversion.cpp
149149
# test_custom_default_arch.cpp
150150
# test_error_gamma.cpp

‎test/test_bitwise_cast.cpp‎

Lines changed: 66 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -21,46 +21,67 @@ struct bitwise_cast_test
2121
static constexpr size_t N = CP::size;
2222

2323
using int32_batch = xsimd::batch<int32_t>;
24-
using int64_batch = xsimd::batch<int64_t>;
2524
using float_batch = xsimd::batch<float>;
26-
using double_batch = xsimd::batch<double>;
2725

2826
using int32_vector = std::vector<int32_t, xsimd::default_allocator<int32_t>>;
29-
using int64_vector = std::vector<int64_t, xsimd::default_allocator<int64_t>>;
3027
using float_vector = std::vector<float, xsimd::default_allocator<float>>;
31-
using double_vector = std::vector<double, xsimd::default_allocator<double>>;
3228

3329
int32_vector ftoi32_res;
34-
int32_vector dtoi32_res;
35-
int64_vector ftoi64_res;
36-
int64_vector dtoi64_res;
3730
float_vector i32tof_res;
31+
32+
#ifndef XSIMD_WITH_ALTIVEC
33+
using int64_batch = xsimd::batch<int64_t>;
34+
using double_batch = xsimd::batch<double>;
35+
36+
using int64_vector = std::vector<int64_t, xsimd::default_allocator<int64_t>>;
37+
using double_vector = std::vector<double, xsimd::default_allocator<double>>;
38+
39+
int32_vector dtoi32_res;
3840
float_vector i64tof_res;
3941
float_vector dtof_res;
42+
int64_vector ftoi64_res;
43+
int64_vector dtoi64_res;
4044
double_vector i32tod_res;
4145
double_vector i64tod_res;
4246
double_vector ftod_res;
47+
#endif
4348

4449
bitwise_cast_test()
4550
: ftoi32_res(2 * N)
46-
, dtoi32_res(2 * N)
47-
, ftoi64_res(N)
48-
, dtoi64_res(N)
4951
, i32tof_res(2 * N)
52+
#ifndef XSIMD_WITH_ALTIVEC
53+
, dtoi32_res(2 * N)
5054
, i64tof_res(2 * N)
5155
, dtof_res(2 * N)
56+
, ftoi64_res(N)
57+
, dtoi64_res(N)
5258
, i32tod_res(N)
5359
, i64tod_res(N)
5460
, ftod_res(N)
61+
#endif
5562
{
5663
{
5764
int32_batch input = i32_input();
5865
bitcast b;
5966
b.i32[0] = input.get(0);
6067
b.i32[1] = input.get(1);
6168
std::fill(i32tof_res.begin(), i32tof_res.end(), b.f[0]);
69+
#ifndef XSIMD_WITH_ALTIVEC
6270
std::fill(i32tod_res.begin(), i32tod_res.end(), b.d);
71+
#endif
72+
}
73+
{
74+
float_batch input = f_input();
75+
bitcast b;
76+
b.f[0] = input.get(0);
77+
b.f[1] = input.get(1);
78+
std::fill(ftoi32_res.begin(), ftoi32_res.end(), b.i32[0]);
79+
#ifndef XSIMD_WITH_ALTIVEC
80+
std::fill(ftoi64_res.begin(), ftoi64_res.end(), b.i64);
81+
std::fill(ftod_res.begin(), ftod_res.end(), b.d);
82+
#endif
6383
}
84+
#ifndef XSIMD_WITH_ALTIVEC
6485
{
6586
int64_batch input = i64_input();
6687
bitcast b;
@@ -72,15 +93,6 @@ struct bitwise_cast_test
7293
i64tof_res[2 * i + 1] = b.f[1];
7394
}
7495
}
75-
{
76-
float_batch input = f_input();
77-
bitcast b;
78-
b.f[0] = input.get(0);
79-
b.f[1] = input.get(1);
80-
std::fill(ftoi32_res.begin(), ftoi32_res.end(), b.i32[0]);
81-
std::fill(ftoi64_res.begin(), ftoi64_res.end(), b.i64);
82-
std::fill(ftod_res.begin(), ftod_res.end(), b.d);
83-
}
8496
{
8597
double_batch input = d_input();
8698
bitcast b;
@@ -95,6 +107,7 @@ struct bitwise_cast_test
95107
dtof_res[2 * i + 1] = b.f[1];
96108
}
97109
}
110+
#endif
98111
}
99112

100113
void test_to_int32()
@@ -106,29 +119,14 @@ struct bitwise_cast_test
106119
INFO("to_int32(float)");
107120
CHECK_VECTOR_EQ(i32vres, ftoi32_res);
108121
}
122+
#ifndef XSIMD_WITH_ALTIVEC
109123
{
110124
int32_batch i32bres = xsimd::bitwise_cast<int32_t>(d_input());
111125
i32bres.store_aligned(i32vres.data());
112126
INFO("to_int32(double)");
113127
CHECK_VECTOR_EQ(i32vres, dtoi32_res);
114128
}
115-
}
116-
117-
void test_to_int64()
118-
{
119-
int64_vector i64vres(int64_batch::size);
120-
{
121-
int64_batch i64bres = xsimd::bitwise_cast<int64_t>(f_input());
122-
i64bres.store_aligned(i64vres.data());
123-
INFO("to_int64(float)");
124-
CHECK_VECTOR_EQ(i64vres, ftoi64_res);
125-
}
126-
{
127-
int64_batch i64bres = xsimd::bitwise_cast<int64_t>(d_input());
128-
i64bres.store_aligned(i64vres.data());
129-
INFO("to_int64(double)");
130-
CHECK_VECTOR_EQ(i64vres, dtoi64_res);
131-
}
129+
#endif
132130
}
133131

134132
void test_to_float()
@@ -140,6 +138,7 @@ struct bitwise_cast_test
140138
INFO("to_float(int32_t)");
141139
CHECK_VECTOR_EQ(fvres, i32tof_res);
142140
}
141+
#ifndef XSIMD_WITH_ALTIVEC
143142
{
144143
float_batch fbres = xsimd::bitwise_cast<float>(i64_input());
145144
fbres.store_aligned(fvres.data());
@@ -152,6 +151,26 @@ struct bitwise_cast_test
152151
INFO("to_float(double)");
153152
CHECK_VECTOR_EQ(fvres, dtof_res);
154153
}
154+
#endif
155+
}
156+
157+
#ifndef XSIMD_WITH_ALTIVEC
158+
159+
void test_to_int64()
160+
{
161+
int64_vector i64vres(int64_batch::size);
162+
{
163+
int64_batch i64bres = xsimd::bitwise_cast<int64_t>(f_input());
164+
i64bres.store_aligned(i64vres.data());
165+
INFO("to_int64(float)");
166+
CHECK_VECTOR_EQ(i64vres, ftoi64_res);
167+
}
168+
{
169+
int64_batch i64bres = xsimd::bitwise_cast<int64_t>(d_input());
170+
i64bres.store_aligned(i64vres.data());
171+
INFO("to_int64(double)");
172+
CHECK_VECTOR_EQ(i64vres, dtoi64_res);
173+
}
155174
}
156175

157176
void test_to_double()
@@ -176,27 +195,30 @@ struct bitwise_cast_test
176195
CHECK_VECTOR_EQ(dvres, ftod_res);
177196
}
178197
}
198+
#endif
179199

180200
private:
181201
int32_batch i32_input() const
182202
{
183203
return int32_batch(2);
184204
}
185205

186-
int64_batch i64_input() const
206+
float_batch f_input() const
187207
{
188-
return int64_batch(2);
208+
return float_batch(3.);
189209
}
190210

191-
float_batch f_input() const
211+
#ifndef XSIMD_WITH_ALTIVEC
212+
int64_batch i64_input() const
192213
{
193-
return float_batch(3.);
214+
return int64_batch(2);
194215
}
195216

196217
double_batch d_input() const
197218
{
198219
return double_batch(2.5e17);
199220
}
221+
#endif
200222

201223
union bitcast
202224
{
@@ -212,11 +234,13 @@ TEST_CASE_TEMPLATE("[bitwise cast]", B, CONVERSION_TYPES)
212234
bitwise_cast_test<B> Test;
213235
SUBCASE("to_int32") { Test.test_to_int32(); }
214236

215-
SUBCASE("to_int64") { Test.test_to_int64(); }
216-
217237
SUBCASE("to_float") { Test.test_to_float(); }
218238

239+
#ifndef XSIMD_WITH_ALTIVEC
240+
SUBCASE("to_int64") { Test.test_to_int64(); }
241+
219242
SUBCASE("to_double") { Test.test_to_double(); }
243+
#endif
220244
}
221245
#endif
222246
#endif

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