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JohanMabilleJohanMabille
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Merge pull request #979 from rivosinc/upstream-rvv
Add RISC-V Vector support.
2 parents be56a35 + dc9fbff commit 997d9d9

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+2017
-7
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14 files changed

+2017
-7
lines changed

‎.github/toolchains/clang-riscv64-linux-gnu.cmake‎

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set(CMAKE_SYSTEM_PROCESSOR riscv64)
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set(triple riscv64-linux-gnu)
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include(${CMAKE_CURRENT_LIST_DIR}/clang.cmake)

‎.github/toolchains/gcc-riscv64-linux-gnu.cmake‎

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set(CMAKE_SYSTEM_PROCESSOR riscv64)
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set(triple riscv64-linux-gnu)
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include(${CMAKE_CURRENT_LIST_DIR}/gcc.cmake)

‎.github/workflows/cross-rvv.yml‎

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name: RISC-V RVV cross-compilation build
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on: [push, pull_request]
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concurrency:
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group: ${{ github.workflow }}-${{ github.job }}-${{ github.ref }}
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cancel-in-progress: true
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env:
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LLVM_VERSION: "17"
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GCC_VERSION: "12"
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jobs:
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build:
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runs-on: ubuntu-22.04
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name: 'RISC-V RVV${{ matrix.vector_bits }}'
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strategy:
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matrix:
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vector_bits:
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- 128
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- 256
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- 512
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steps:
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- name: Setup GCC
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run: |
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sudo apt-get -y -qq update
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sudo apt-get -y -qq --no-install-suggests --no-install-recommends install gcc-${GCC_VERSION}-riscv64-linux-gnu g++-${GCC_VERSION}-riscv64-linux-gnu
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sudo update-alternatives --install /usr/bin/riscv64-linux-gnu-gcc riscv64-linux-gnu-gcc /usr/bin/riscv64-linux-gnu-gcc-${GCC_VERSION} 20
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sudo update-alternatives --install /usr/bin/riscv64-linux-gnu-g++ riscv64-linux-gnu-g++ /usr/bin/riscv64-linux-gnu-g++-${GCC_VERSION} 20
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- name: Setup LLVM
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run: |
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# Install latest LLVM stable
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curl -o llvm.sh https://apt.llvm.org/llvm.sh
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chmod u+x llvm.sh
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sudo ./llvm.sh ${LLVM_VERSION}
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sudo ln -srf $(which clang-${LLVM_VERSION}) /usr/bin/clang
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sudo ln -srf $(which clang++-${LLVM_VERSION}) /usr/bin/clang++
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rm llvm.sh
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- name: Setup QEMU
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uses: docker/[email protected]
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with:
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platforms: riscv64
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- name: Setup Ninja
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run: |
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sudo apt-get -y -qq install ninja-build
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- name: Checkout xsimd
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uses: actions/checkout@v3
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- name: Setup
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run: >
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cmake -S . -B _build
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-GNinja
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-DBUILD_TESTS=ON
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-DDOWNLOAD_DOCTEST=ON
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-DCMAKE_BUILD_TYPE=Release
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-DTARGET_ARCH=generic
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-DCMAKE_C_FLAGS="-march=rv64gcv_zvl${{ matrix.vector_bits }}b_zba_zbb_zbs -mrvv-vector-bits=zvl"
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-DCMAKE_CXX_FLAGS="-march=rv64gcv_zvl${{ matrix.vector_bits }}b_zba_zbb_zbs -mrvv-vector-bits=zvl"
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-DCMAKE_TOOLCHAIN_FILE=${{ github.workspace }}/.github/toolchains/clang-riscv64-linux-gnu.cmake
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- name: Build
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run: cmake --build _build
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- name: Testing xsimd
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run: >
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QEMU_CPU="rv64,zba=true,zbb=true,zbs=true,v=true,vlen=${{ matrix.vector_bits }},elen=64,vext_spec=v1.0"
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QEMU_LD_PREFIX="/usr/riscv64-linux-gnu"
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./test/test_xsimd
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working-directory: ${{ github.workspace }}/_build

‎CMakeLists.txt‎

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@@ -42,6 +42,7 @@ ${XSIMD_INCLUDE_DIR}/xsimd/arch/xsimd_generic.hpp
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${XSIMD_INCLUDE_DIR}/xsimd/arch/xsimd_isa.hpp
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${XSIMD_INCLUDE_DIR}/xsimd/arch/xsimd_neon.hpp
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${XSIMD_INCLUDE_DIR}/xsimd/arch/xsimd_neon64.hpp
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${XSIMD_INCLUDE_DIR}/xsimd/arch/xsimd_rvv.hpp
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${XSIMD_INCLUDE_DIR}/xsimd/arch/xsimd_scalar.hpp
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${XSIMD_INCLUDE_DIR}/xsimd/arch/xsimd_sse2.hpp
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${XSIMD_INCLUDE_DIR}/xsimd/arch/xsimd_sse3.hpp
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${XSIMD_INCLUDE_DIR}/xsimd/types/xsimd_fma4_register.hpp
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${XSIMD_INCLUDE_DIR}/xsimd/types/xsimd_generic_arch.hpp
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${XSIMD_INCLUDE_DIR}/xsimd/types/xsimd_register.hpp
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${XSIMD_INCLUDE_DIR}/xsimd/types/xsimd_rvv_register.hpp
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${XSIMD_INCLUDE_DIR}/xsimd/types/xsimd_sse2_register.hpp
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${XSIMD_INCLUDE_DIR}/xsimd/types/xsimd_sse3_register.hpp
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${XSIMD_INCLUDE_DIR}/xsimd/types/xsimd_sse4_1_register.hpp

‎docs/Doxyfile‎

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@@ -21,6 +21,7 @@ INPUT = ../include/xsimd/types/xsimd_api.hpp \
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../include/xsimd/types/xsimd_fma4_register.hpp \
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../include/xsimd/types/xsimd_neon64_register.hpp \
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../include/xsimd/types/xsimd_neon_register.hpp \
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../include/xsimd/types/xsimd_rvv_register.hpp \
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../include/xsimd/types/xsimd_sse2_register.hpp \
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../include/xsimd/types/xsimd_sse3_register.hpp \
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../include/xsimd/types/xsimd_sse4_1_register.hpp \

‎include/xsimd/arch/xsimd_isa.hpp‎

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#include "./xsimd_sve.hpp"
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#endif
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#if XSIMD_WITH_RVV
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#include "./xsimd_rvv.hpp"
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#endif
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#if XSIMD_WITH_WASM
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#include "./xsimd_wasm.hpp"
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#endif

‎include/xsimd/arch/xsimd_rvv.hpp‎

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‎include/xsimd/config/xsimd_arch.hpp‎

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};
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using all_x86_architectures = arch_list<avx512bw, avx512dq, avx512cd, avx512f, fma3<avx2>, avx2, fma3<avx>, avx, fma4, fma3<sse4_2>, sse4_2, sse4_1, /*sse4a,*/ ssse3, sse3, sse2>;
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using all_sve_architectures = arch_list<detail::sve<512>, detail::sve<256>, detail::sve<128>>;
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using all_rvv_architectures = arch_list<detail::rvv<512>, detail::rvv<256>, detail::rvv<128>>;
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using all_arm_architectures = typename detail::join<all_sve_architectures, arch_list<neon64, neon>>::type;
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using all_riscv_architectures = all_rvv_architectures;
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using all_wasm_architectures = arch_list<wasm>;
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using all_architectures = typename detail::join<all_arm_architectures, all_x86_architectures, all_wasm_architectures>::type;
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using all_architectures = typename detail::join<all_arm_architectures, all_x86_architectures, all_riscv_architectures, all_wasm_architectures>::type;
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using supported_architectures = typename detail::supported<all_architectures>::type;
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using x86_arch = typename detail::supported<all_x86_architectures>::type::best;
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using arm_arch = typename detail::supported<all_arm_architectures>::type::best;
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using riscv_arch = typename detail::supported<all_riscv_architectures>::type::best;
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using best_arch = typename supported_architectures::best;
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#ifdef XSIMD_DEFAULT_ARCH

‎include/xsimd/config/xsimd_config.hpp‎

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#define XSIMD_SVE_BITS 0
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#endif
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/**
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* @ingroup xsimd_config_macro
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*
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* Set to 1 if RVV is available and bit width is pre-set at compile-time, to 0 otherwise.
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*/
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#if defined(__riscv_vector) && defined(__riscv_v_fixed_vlen) && __riscv_v_fixed_vlen > 0
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#define XSIMD_WITH_RVV 1
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#define XSIMD_RVV_BITS __riscv_v_fixed_vlen
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#else
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#define XSIMD_WITH_RVV 0
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#define XSIMD_RVV_BITS 0
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#endif
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/**
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* @ingroup xsimd_config_macro
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*
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#endif
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#if !XSIMD_WITH_SSE2 && !XSIMD_WITH_SSE3 && !XSIMD_WITH_SSSE3 && !XSIMD_WITH_SSE4_1 && !XSIMD_WITH_SSE4_2 && !XSIMD_WITH_AVX && !XSIMD_WITH_AVX2 && !XSIMD_WITH_FMA3_SSE && !XSIMD_WITH_FMA4 && !XSIMD_WITH_FMA3_AVX && !XSIMD_WITH_FMA3_AVX2 && !XSIMD_WITH_AVX512F && !XSIMD_WITH_AVX512CD && !XSIMD_WITH_AVX512DQ && !XSIMD_WITH_AVX512BW && !XSIMD_WITH_NEON && !XSIMD_WITH_NEON64 && !XSIMD_WITH_SVE && !XSIMD_WITH_WASM
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#if !XSIMD_WITH_SSE2 && !XSIMD_WITH_SSE3 && !XSIMD_WITH_SSSE3 && !XSIMD_WITH_SSE4_1 && !XSIMD_WITH_SSE4_2 && !XSIMD_WITH_AVX && !XSIMD_WITH_AVX2 && !XSIMD_WITH_FMA3_SSE && !XSIMD_WITH_FMA4 && !XSIMD_WITH_FMA3_AVX && !XSIMD_WITH_FMA3_AVX2 && !XSIMD_WITH_AVX512F && !XSIMD_WITH_AVX512CD && !XSIMD_WITH_AVX512DQ && !XSIMD_WITH_AVX512BW && !XSIMD_WITH_NEON && !XSIMD_WITH_NEON64 && !XSIMD_WITH_SVE && !XSIMD_WITH_RVV && !XSIMD_WITH_WASM
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#endif
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#endif

‎include/xsimd/config/xsimd_cpuid.hpp‎

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#include <algorithm>
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#include <cstring>
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#if defined(__linux__) && (defined(__ARM_NEON) || defined(_M_ARM))
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#if defined(__linux__) && (defined(__ARM_NEON) || defined(_M_ARM) || defined(__riscv_vector))
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#include <asm/hwcap.h>
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#include <sys/auxv.h>
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#endif
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unsigned neon : 1;
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unsigned neon64 : 1;
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unsigned sve : 1;
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unsigned rvv : 1;
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// version number of the best arch available
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unsigned best;
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#endif
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best = sve::version() * sve;
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#elif defined(__riscv_vector) && defined(__riscv_v_fixed_vlen) && __riscv_v_fixed_vlen > 0
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#if defined(__linux__) && (!defined(__ANDROID_API__) || __ANDROID_API__ >= 18)
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#ifndef HWCAP_V
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#define HWCAP_V (1 << ('V' - 'A'))
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#endif
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rvv = bool(getauxval(AT_HWCAP) & HWCAP_V);
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#else
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rvv = 0;
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#endif
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best = ::xsimd::rvv::version() * rvv;
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#elif defined(__x86_64__) || defined(__i386__) || defined(_M_AMD64) || defined(_M_IX86)
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auto get_cpuid = [](int reg[4], int func_id) noexcept
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{

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