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ARM: make FastISel & GISel pass -1 to ADJCALLSTACKUP to signal no callee pop.
The interface for these instructions changed with support for mandatory tail calls, and now -1 indicates the CalleePopAmount argument is not valid. Unfortunately I didn't realise FastISel or GISel did calls at the time so didn't update them. (cherry picked from commit 0b5b35f)
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6 files changed

+46
-27
lines changed

6 files changed

+46
-27
lines changed

‎llvm/lib/Target/ARM/ARMCallLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -525,7 +525,7 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &
525525

526526
MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)
527527
.addImm(ArgAssigner.StackOffset)
528-
.addImm(0)
528+
.addImm(-1ULL)
529529
.add(predOps(ARMCC::AL));
530530

531531
return true;

‎llvm/lib/Target/ARM/ARMFastISel.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2022,7 +2022,7 @@ bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
20222022
unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
20232023
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
20242024
TII.get(AdjStackUp))
2025-
.addImm(NumBytes).addImm(0));
2025+
.addImm(NumBytes).addImm(-1ULL));
20262026

20272027
// Now the return value.
20282028
if (RetVT != MVT::isVoid) {

‎llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -11,31 +11,31 @@ define arm_aapcscc void @test_indirect_call(void() *%fptr) {
1111
; NOV4T: [[COPY:%[0-9]+]]:tgpr(p0) = COPY $r0
1212
; NOV4T: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
1313
; NOV4T: BMOVPCRX_CALL [[COPY]](p0), csr_aapcs, implicit-def $lr, implicit $sp
14-
; NOV4T: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
14+
; NOV4T: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
1515
; NOV4T: MOVPCLR 14 /* CC::al */, $noreg
1616
; V4T-LABEL: name: test_indirect_call
1717
; V4T: bb.1.entry:
1818
; V4T: liveins: $r0
1919
; V4T: [[COPY:%[0-9]+]]:tgpr(p0) = COPY $r0
2020
; V4T: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
2121
; V4T: BX_CALL [[COPY]](p0), csr_aapcs, implicit-def $lr, implicit $sp
22-
; V4T: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
22+
; V4T: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
2323
; V4T: BX_RET 14 /* CC::al */, $noreg
2424
; V5T-LABEL: name: test_indirect_call
2525
; V5T: bb.1.entry:
2626
; V5T: liveins: $r0
2727
; V5T: [[COPY:%[0-9]+]]:gpr(p0) = COPY $r0
2828
; V5T: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
2929
; V5T: BLX [[COPY]](p0), csr_aapcs, implicit-def $lr, implicit $sp
30-
; V5T: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
30+
; V5T: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
3131
; V5T: BX_RET 14 /* CC::al */, $noreg
3232
; THUMB-LABEL: name: test_indirect_call
3333
; THUMB: bb.1.entry:
3434
; THUMB: liveins: $r0
3535
; THUMB: [[COPY:%[0-9]+]]:gpr(p0) = COPY $r0
3636
; THUMB: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
3737
; THUMB: tBLXr 14 /* CC::al */, $noreg, [[COPY]](p0), csr_aapcs, implicit-def $lr, implicit $sp
38-
; THUMB: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
38+
; THUMB: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
3939
; THUMB: tBX_RET 14 /* CC::al */, $noreg
4040
entry:
4141
notail call arm_aapcscc void %fptr()
@@ -49,25 +49,25 @@ define arm_aapcscc void @test_direct_call() {
4949
; NOV4T: bb.1.entry:
5050
; NOV4T: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
5151
; NOV4T: BL @call_target, csr_aapcs, implicit-def $lr, implicit $sp
52-
; NOV4T: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
52+
; NOV4T: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
5353
; NOV4T: MOVPCLR 14 /* CC::al */, $noreg
5454
; V4T-LABEL: name: test_direct_call
5555
; V4T: bb.1.entry:
5656
; V4T: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
5757
; V4T: BL @call_target, csr_aapcs, implicit-def $lr, implicit $sp
58-
; V4T: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
58+
; V4T: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
5959
; V4T: BX_RET 14 /* CC::al */, $noreg
6060
; V5T-LABEL: name: test_direct_call
6161
; V5T: bb.1.entry:
6262
; V5T: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
6363
; V5T: BL @call_target, csr_aapcs, implicit-def $lr, implicit $sp
64-
; V5T: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
64+
; V5T: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
6565
; V5T: BX_RET 14 /* CC::al */, $noreg
6666
; THUMB-LABEL: name: test_direct_call
6767
; THUMB: bb.1.entry:
6868
; THUMB: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
6969
; THUMB: tBL 14 /* CC::al */, $noreg, @call_target, csr_aapcs, implicit-def $lr, implicit $sp
70-
; THUMB: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
70+
; THUMB: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
7171
; THUMB: tBX_RET 14 /* CC::al */, $noreg
7272
entry:
7373
notail call arm_aapcscc void @call_target()

‎llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) {
1414
; ARM: BL @simple_reg_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0
1515
; THUMB: tBL 14 /* CC::al */, $noreg, @simple_reg_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0
1616
; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY $r0
17-
; CHECK: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
17+
; CHECK: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
1818
; CHECK: $r0 = COPY [[RVREG]]
1919
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0
2020
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
@@ -45,7 +45,7 @@ define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) {
4545
; ARM: BL @simple_stack_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
4646
; THUMB: tBL 14 /* CC::al */, $noreg, @simple_stack_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
4747
; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY $r0
48-
; CHECK: ADJCALLSTACKUP 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
48+
; CHECK: ADJCALLSTACKUP 8, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
4949
; CHECK: $r0 = COPY [[RVREG]]
5050
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0
5151
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
@@ -103,7 +103,7 @@ define arm_aapcscc signext i16 @test_call_ext_params(i8 %a, i16 %b, i1 %c) {
103103
; CHECK: [[R0VREG:%[0-9]+]]:_(s32) = COPY $r0
104104
; CHECK: [[R0VREG_ASSERT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[R0VREG]], 16
105105
; CHECK: [[RVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R0VREG_ASSERT]]
106-
; CHECK: ADJCALLSTACKUP 20, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
106+
; CHECK: ADJCALLSTACKUP 20, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
107107
; CHECK: [[RExtVREG:%[0-9]+]]:_(s32) = G_SEXT [[RVREG]]
108108
; CHECK: $r0 = COPY [[RExtVREG]]
109109
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0
@@ -125,7 +125,7 @@ define arm_aapcs_vfpcc double @test_call_vfpcc_fp_params(double %a, float %b) {
125125
; ARM: BL @vfpcc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $d1, implicit-def $d0
126126
; THUMB: tBL 14 /* CC::al */, $noreg, @vfpcc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $d1, implicit-def $d0
127127
; CHECK: [[RVREG:%[0-9]+]]:_(s64) = COPY $d0
128-
; CHECK: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
128+
; CHECK: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
129129
; CHECK: $d0 = COPY [[RVREG]]
130130
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $d0
131131
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $d0
@@ -164,7 +164,7 @@ define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) {
164164
; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r1
165165
; LITTLE: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32)
166166
; BIG: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R1]](s32)
167-
; CHECK: ADJCALLSTACKUP 16, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
167+
; CHECK: ADJCALLSTACKUP 16, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
168168
; CHECK: [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RVREG]](s64)
169169
; LITTLE-DAG: $r0 = COPY [[R1]]
170170
; LITTLE-DAG: $r1 = COPY [[R2]]
@@ -187,7 +187,7 @@ define arm_aapcs_vfpcc float @test_call_different_call_conv(float %x) {
187187
; ARM: BL @different_call_conv_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit-def $r0
188188
; THUMB: tBL 14 /* CC::al */, $noreg, @different_call_conv_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit-def $r0
189189
; CHECK: [[R:%[0-9]+]]:_(s32) = COPY $r0
190-
; CHECK: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
190+
; CHECK: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
191191
; CHECK: $s0 = COPY [[R]]
192192
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $s0
193193
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $s0
@@ -211,7 +211,7 @@ define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) {
211211
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
212212
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
213213
; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2
214-
; CHECK: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
214+
; CHECK: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
215215
; FIXME: This doesn't seem correct with regard to the AAPCS docs (which say
216216
; that composite types larger than 4 bytes should be passed through memory),
217217
; but it's what DAGISel does. We should fix it in the common code for both.
@@ -241,7 +241,7 @@ define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %ar
241241
; CHECK: $r3 = COPY [[R3]]
242242
; ARM: BL @multiple_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3
243243
; THUMB: tBL 14 /* CC::al */, $noreg, @multiple_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3
244-
; CHECK: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
244+
; CHECK: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
245245
; ARM: BX_RET 14 /* CC::al */, $noreg
246246
; THUMB: tBX_RET 14 /* CC::al */, $noreg
247247
entry:
@@ -284,7 +284,7 @@ define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) {
284284
; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store (s32)
285285
; ARM: BL @large_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3
286286
; THUMB: tBL 14 /* CC::al */, $noreg, @large_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3
287-
; CHECK: ADJCALLSTACKUP 64, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
287+
; CHECK: ADJCALLSTACKUP 64, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
288288
; ARM: BX_RET 14 /* CC::al */, $noreg
289289
; THUMB: tBX_RET 14 /* CC::al */, $noreg
290290
entry:
@@ -328,7 +328,7 @@ define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) {
328328
; THUMB: tBL 14 /* CC::al */, $noreg, @fp_arrays_aapcs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
329329
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
330330
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
331-
; CHECK: ADJCALLSTACKUP 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
331+
; CHECK: ADJCALLSTACKUP 8, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
332332
; CHECK: $r0 = COPY [[R0]]
333333
; CHECK: $r1 = COPY [[R1]]
334334
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
@@ -391,7 +391,7 @@ define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3
391391
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $s1
392392
; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $s2
393393
; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $s3
394-
; CHECK: ADJCALLSTACKUP 32, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
394+
; CHECK: ADJCALLSTACKUP 32, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
395395
; CHECK: $s0 = COPY [[R0]]
396396
; CHECK: $s1 = COPY [[R1]]
397397
; CHECK: $s2 = COPY [[R2]]
@@ -440,7 +440,7 @@ define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) {
440440
; THUMB: tBL 14 /* CC::al */, $noreg, @tough_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
441441
; CHECK: [[R0:%[0-9]+]]:_(p0) = COPY $r0
442442
; CHECK: [[R1:%[0-9]+]]:_(p0) = COPY $r1
443-
; CHECK: ADJCALLSTACKUP 80, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
443+
; CHECK: ADJCALLSTACKUP 80, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
444444
; CHECK: $r0 = COPY [[R0]]
445445
; CHECK: $r1 = COPY [[R1]]
446446
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
@@ -464,7 +464,7 @@ define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) {
464464
; THUMB: tBL 14 /* CC::al */, $noreg, @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
465465
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
466466
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
467-
; CHECK: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
467+
; CHECK: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
468468
; CHECK: $r0 = COPY [[R0]](s32)
469469
; CHECK: $r1 = COPY [[R1]](s32)
470470
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1

‎llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ define arm_aapcscc i32 @test_call_to_varargs_with_ints(i32 *%a, i32 %b) {
2323
; ARM: BL @int_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
2424
; THUMB: tBL 14 /* CC::al */, $noreg, @int_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
2525
; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0
26-
; CHECK: ADJCALLSTACKUP 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
26+
; CHECK: ADJCALLSTACKUP 8, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
2727
; CHECK: $r0 = COPY [[RVREG]]
2828
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0
2929
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
@@ -50,7 +50,7 @@ define arm_aapcs_vfpcc float @test_call_to_varargs_with_floats(float %a, double
5050
; ARM: BL @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
5151
; THUMB: tBL 14 /* CC::al */, $noreg, @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
5252
; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0
53-
; CHECK: ADJCALLSTACKUP 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
53+
; CHECK: ADJCALLSTACKUP 8, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
5454
; CHECK: $s0 = COPY [[RVREG]]
5555
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $s0
5656
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $s0
@@ -71,7 +71,7 @@ define arm_aapcs_vfpcc float @test_call_to_varargs_with_floats_fixed_args_only(f
7171
; ARM: BL @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
7272
; THUMB: tBL 14 /* CC::al */, $noreg, @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
7373
; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0
74-
; CHECK: ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
74+
; CHECK: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
7575
; CHECK: $s0 = COPY [[RVREG]]
7676
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $s0
7777
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $s0
@@ -97,7 +97,7 @@ define arm_aapcs_vfpcc float @test_indirect_call_to_varargs(float (float, double
9797
; ARM: BLX [[FPTRVREG]](p0), csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
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; THUMB: tBLXr 14 /* CC::al */, $noreg, [[FPTRVREG]](p0), csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
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; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0
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; CHECK: ADJCALLSTACKUP 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
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; CHECK: ADJCALLSTACKUP 8, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[RVREG]]
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; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $s0
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; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $s0

‎llvm/test/CodeGen/ARM/fast-call-frame-restore.ll‎

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Original file line numberDiff line numberDiff line change
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; RUN: llc -mtriple=armv7-linux-gnueabi %s -o - | FileCheck %s
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declare void @bar(i8*, i32, i32, i32, i32)
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define void @foo(i32 %amt) optnone noinline {
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br label %next
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next:
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%mem = alloca i8;, i32 %amt
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br label %next1
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next1:
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call void @bar(i8* %mem, i32 undef, i32 undef, i32 undef, i32 undef)
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; CHECK: sub sp, sp, #8
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; CHECK: bl bar
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; CHECK: add sp, sp, #8
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ret void
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}

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