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fix d8200 with split binary, correct modbus addresses (#36)
* fix d8200 with split binary, correct modbus addresses * slow down * [pre-commit.ci] auto fixes from pre-commit.com hooks for more information, see https://pre-commit.ci --------- Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>
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CHANGELOG.md

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@@ -5,6 +5,11 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/).
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## [Unreleased]
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## [2024.2.0]
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### fixed
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- d8200 uses split binary, not twos-complement
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## [2023.11.0]
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### Added

yaqd_omega/_omega_d8200.py

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__all__ = ["OmegaPlatinum"]
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import asyncio
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from typing import Dict, Any, List
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import struct
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stop_bit_options = {"one": 1, "one_and_half": 1.5, "two": 2}
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CHANNEL_REGISTERS = dict()
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CHANNEL_REGISTERS[0] = 49
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CHANNEL_REGISTERS[1] = 50
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CHANNEL_REGISTERS[2] = 51
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CHANNEL_REGISTERS[3] = 52
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CHANNEL_REGISTERS[4] = 53
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CHANNEL_REGISTERS[5] = 54
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CHANNEL_REGISTERS[6] = 55
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# https://assets.omega.com/manuals/M5442.pdf
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# as far as I can tell, the registers in this manual are wrong
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# subtract 40,000 decimal from all registers
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class OmegaD8200(UsesUart, UsesSerial, IsSensor, IsDaemon):
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_kind = "omega-d8200"
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@@ -55,12 +43,13 @@ async def _update_measurements(self):
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while True:
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await asyncio.sleep(0.5)
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out = dict()
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for index in range(7):
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register = CHANNEL_REGISTERS[index]
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raw = self.client.read_register(register, functioncode=3)
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current = (raw * (0.040 / 2**16)) + 0.020
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out[f"channel{index}"] = current
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self._measurement_id += 1
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out["measurement_id"] = self._measurement_id
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await asyncio.sleep(0)
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rawl = self.client.read_registers(48, 7, functioncode=3)
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# data is stored as offset binary
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# by xoring into 0x80_00, I can convert into twos complement shorts
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shortl = [i ^ 0x80_00 for i in rawl]
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intl = [struct.unpack(">h", b.to_bytes(2, "big"))[0] for b in shortl]
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for i, integer in enumerate(intl):
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out[f"channel{i}"] = integer * (0.04 / 2**16)
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out["measurement_id"] = self._measurement_id
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self._measurement_id += 1
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self._measured = out

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