Merge pull request #1 from yezzfusl/test

Initial setup and implementation of CAN protocol stack.

Author: yezzfusl

src/can_protocol/can_controller.vhd

@@ -0,0 +1,104 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity can_controller is
+    Port ( 
+        clk : in STD_LOGIC;
+        rst : in STD_LOGIC;
+        rx : in STD_LOGIC;
+        tx : out STD_LOGIC;
+        data_in : in STD_LOGIC_VECTOR(63 downto 0);
+        data_out : out STD_LOGIC_VECTOR(63 downto 0);
+        data_valid : out STD_LOGIC
+    );
+end can_controller;
+
+architecture Behavioral of can_controller is
+    type can_state_type is (IDLE, ARBITRATION, CONTROL, DATA, CRC, ACK, EOF);
+    signal state : can_state_type := IDLE;
+    signal bit_counter : integer range 0 to 127 := 0;
+    signal crc : STD_LOGIC_VECTOR(14 downto 0) := (others => '0');
+    
+    -- CAN frame components
+    signal arbitration_field : STD_LOGIC_VECTOR(11 downto 0);
+    signal control_field : STD_LOGIC_VECTOR(5 downto 0);
+    signal data_field : STD_LOGIC_VECTOR(63 downto 0);
+    
+begin
+    process(clk, rst)
+    begin
+        if rst = '1' then
+            state <= IDLE;
+            bit_counter <= 0;
+            crc <= (others => '0');
+            tx <= '1';
+            data_valid <= '0';
+        elsif rising_edge(clk) then
+            case state is
+                when IDLE =>
+                    if rx = '0' then  -- Start of Frame detected
+                        state <= ARBITRATION;
+                        bit_counter <= 0;
+                    end if;
+                
+                when ARBITRATION =>
+                    if bit_counter < 11 then
+                        arbitration_field(11 - bit_counter) <= rx;
+                        bit_counter <= bit_counter + 1;
+                    else
+                        state <= CONTROL;
+                        bit_counter <= 0;
+                    end if;
+                
+                when CONTROL =>
+                    if bit_counter < 6 then
+                        control_field(5 - bit_counter) <= rx;
+                        bit_counter <= bit_counter + 1;
+                    else
+                        state <= DATA;
+                        bit_counter <= 0;
+                    end if;
+                
+                when DATA =>
+                    if bit_counter < 64 then
+                        data_field(63 - bit_counter) <= rx;
+                        bit_counter <= bit_counter + 1;
+                    else
+                        state <= CRC;
+                        bit_counter <= 0;
+                    end if;
+                
+                when CRC =>
+                    if bit_counter < 15 then
+                        crc(14 - bit_counter) <= rx;
+                        bit_counter <= bit_counter + 1;
+                    else
+                        state <= ACK;
+                        bit_counter <= 0;
+                    end if;
+                
+                when ACK =>
+                    if bit_counter = 0 then
+                        tx <= '0';  -- Send ACK
+                        bit_counter <= bit_counter + 1;
+                    elsif bit_counter = 1 then
+                        tx <= '1';  -- ACK delimiter
+                        bit_counter <= 0;
+                        state <= EOF;
+                    end if;
+                
+                when EOF =>
+                    if bit_counter < 7 then
+                        bit_counter <= bit_counter + 1;
+                    else
+                        state <= IDLE;
+                        bit_counter <= 0;
+                        data_out <= data_field;
+                        data_valid <= '1';
+                    end if;
+            end case;
+        end if;
+    end process;
+
+end Behavioral;

src/can_protocol/can_transceiver.vhd

@@ -0,0 +1,39 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity can_transceiver is
+    Port ( 
+        clk : in STD_LOGIC;
+        rst : in STD_LOGIC;
+        tx_in : in STD_LOGIC;
+        rx_out : out STD_LOGIC;
+        can_high : inout STD_LOGIC;
+        can_low : inout STD_LOGIC
+    );
+end can_transceiver;
+
+architecture Behavioral of can_transceiver is
+    signal differential : STD_LOGIC;
+begin
+    -- Transmit logic
+    process(clk, rst)
+    begin
+        if rst = '1' then
+            can_high <= 'Z';
+            can_low <= 'Z';
+        elsif rising_edge(clk) then
+            if tx_in = '0' then
+                can_high <= '1';
+                can_low <= '0';
+            else
+                can_high <= 'Z';
+                can_low <= 'Z';
+            end if;
+        end if;
+    end process;
+
+    -- Receive logic
+    differential <= can_high xor can_low;
+    rx_out <= differential;
+
+end Behavioral;

src/common/clock_generator.vhd

@@ -0,0 +1,34 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity clock_generator is
+    Port ( 
+        clk_in : in STD_LOGIC;
+        rst : in STD_LOGIC;
+        clk_out : out STD_LOGIC
+    );
+end clock_generator;
+
+architecture Behavioral of clock_generator is
+    signal counter : unsigned(7 downto 0) := (others => '0');
+    signal clk_internal : STD_LOGIC := '0';
+begin
+    process(clk_in, rst)
+    begin
+        if rst = '1' then
+            counter <= (others => '0');
+            clk_internal <= '0';
+        elsif rising_edge(clk_in) then
+            if counter = 49 then  -- Divide by 50 for 1MHz CAN clock (assuming 50MHz input)
+                counter <= (others => '0');
+                clk_internal <= not clk_internal;
+            else
+                counter <= counter + 1;
+            end if;
+        end if;
+    end process;
+
+    clk_out <= clk_internal;
+
+end Behavioral;

src/common/reset_controller.vhd

@@ -0,0 +1,24 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity reset_controller is
+    Port ( 
+        clk : in STD_LOGIC;
+        ext_rst : in STD_LOGIC;
+        rst_out : out STD_LOGIC
+    );
+end reset_controller;
+
+architecture Behavioral of reset_controller is
+    signal reset_shift_reg : STD_LOGIC_VECTOR(3 downto 0) := (others => '1');
+begin
+    process(clk)
+    begin
+        if rising_edge(clk) then
+            reset_shift_reg <= reset_shift_reg(2 downto 0) & ext_rst;
+        end if;
+    end process;
+
+    rst_out <= '1' when reset_shift_reg = "1111" else '0';
+
+end Behavioral;

src/top_level.vhd

@@ -0,0 +1,96 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity top_level is
+    Port ( 
+        clk_50m : in STD_LOGIC;
+        ext_rst : in STD_LOGIC;
+        can_rx : in STD_LOGIC;
+        can_tx : out STD_LOGIC;
+        data_in : in STD_LOGIC_VECTOR(63 downto 0);
+        data_out : out STD_LOGIC_VECTOR(63 downto 0);
+        data_valid : out STD_LOGIC
+    );
+end top_level;
+
+architecture Behavioral of top_level is
+    signal clk_1m : STD_LOGIC;
+    signal rst : STD_LOGIC;
+    signal can_rx_internal, can_tx_internal : STD_LOGIC;
+
+    component clock_generator
+        Port ( 
+            clk_in : in STD_LOGIC;
+            rst : in STD_LOGIC;
+            clk_out : out STD_LOGIC
+        );
+    end component;
+
+    component reset_controller
+        Port ( 
+            clk : in STD_LOGIC;
+            ext_rst : in STD_LOGIC;
+            rst_out : out STD_LOGIC
+        );
+    end component;
+
+    component can_controller
+        Port ( 
+            clk : in STD_LOGIC;
+            rst : in STD_LOGIC;
+            rx : in STD_LOGIC;
+            tx : out STD_LOGIC;
+            data_in : in STD_LOGIC_VECTOR(63 downto 0);
+            data_out : out STD_LOGIC_VECTOR(63 downto 0);
+            data_valid : out STD_LOGIC
+        );
+    end component;
+
+    component can_transceiver
+        Port ( 
+            clk : in STD_LOGIC;
+            rst : in STD_LOGIC;
+            tx_in : in STD_LOGIC;
+            rx_out : out STD_LOGIC;
+            can_high : inout STD_LOGIC;
+            can_low : inout STD_LOGIC
+        );
+    end component;
+
+begin
+    clock_gen: clock_generator
+        port map (
+            clk_in => clk_50m,
+            rst => rst,
+            clk_out => clk_1m
+        );
+
+    reset_ctrl: reset_controller
+        port map (
+            clk => clk_50m,
+            ext_rst => ext_rst,
+            rst_out => rst
+        );
+
+    can_ctrl: can_controller
+        port map (
+            clk => clk_1m,
+            rst => rst,
+            rx => can_rx_internal,
+            tx => can_tx_internal,
+            data_in => data_in,
+            data_out => data_out,
+            data_valid => data_valid
+        );
+
+    can_xcvr: can_transceiver
+        port map (
+            clk => clk_1m,
+            rst => rst,
+            tx_in => can_tx_internal,
+            rx_out => can_rx_internal,
+            can_high => can_rx,
+            can_low => can_tx
+        );
+
+end Behavioral;