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davemgreendavemgreen
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[AArch64] Clean up abd lowering. NFC
The neon ABD intrinsics are lowering to ISD::ABDS/ISD::ABDU nodes in SDAG. This adds the same for GISel so that we can remove the AArch64sabd/AArch64uabd PatFrags, reducing the number of patterns needed. Some very basic legalization info is added for G_ABD nodes.
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‎llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,8 @@ def : GINodeEquiv<G_XOR, xor>;
7878
def : GINodeEquiv<G_SHL, shl>;
7979
def : GINodeEquiv<G_LSHR, srl>;
8080
def : GINodeEquiv<G_ASHR, sra>;
81+
def : GINodeEquiv<G_ABDS, abds>;
82+
def : GINodeEquiv<G_ABDU, abdu>;
8183
def : GINodeEquiv<G_SADDSAT, saddsat>;
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def : GINodeEquiv<G_UADDSAT, uaddsat>;
8385
def : GINodeEquiv<G_SSUBSAT, ssubsat>;

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 8 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1053,13 +1053,6 @@ def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>;
10531053
def AArch64uaddlv : SDNode<"AArch64ISD::UADDLV", SDT_AArch64uaddlp>;
10541054
def AArch64saddlv : SDNode<"AArch64ISD::SADDLV", SDT_AArch64uaddlp>;
10551055

1056-
def AArch64uabd : PatFrags<(ops node:$lhs, node:$rhs),
1057-
[(abdu node:$lhs, node:$rhs),
1058-
(int_aarch64_neon_uabd node:$lhs, node:$rhs)]>;
1059-
def AArch64sabd : PatFrags<(ops node:$lhs, node:$rhs),
1060-
[(abds node:$lhs, node:$rhs),
1061-
(int_aarch64_neon_sabd node:$lhs, node:$rhs)]>;
1062-
10631056
// Add Pairwise of two vectors
10641057
def AArch64addp_n : SDNode<"AArch64ISD::ADDP", SDT_AArch64Zip>;
10651058
// Add Long Pairwise
@@ -5667,8 +5660,7 @@ let Predicates = [HasFullFP16] in {
56675660
// Advanced SIMD two vector instructions.
56685661
//===----------------------------------------------------------------------===//
56695662

5670-
defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
5671-
AArch64uabd>;
5663+
defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl", abdu>;
56725664
// Match UABDL in log2-shuffle patterns.
56735665
def : Pat<(abs (v8i16 (sub (zext (v8i8 V64:$opA)),
56745666
(zext (v8i8 V64:$opB))))),
@@ -6018,8 +6010,8 @@ defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls", null_frag>;
60186010
defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
60196011
defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
60206012
defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
6021-
TriOpFrag<(add node:$LHS, (AArch64sabd node:$MHS, node:$RHS))> >;
6022-
defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", AArch64sabd>;
6013+
TriOpFrag<(add node:$LHS, (abds node:$MHS, node:$RHS))> >;
6014+
defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", abds>;
60236015
defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", avgfloors>;
60246016
defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
60256017
defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
@@ -6037,8 +6029,8 @@ defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
60376029
defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
60386030
defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
60396031
defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
6040-
TriOpFrag<(add node:$LHS, (AArch64uabd node:$MHS, node:$RHS))> >;
6041-
defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", AArch64uabd>;
6032+
TriOpFrag<(add node:$LHS, (abdu node:$MHS, node:$RHS))> >;
6033+
defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", abdu>;
60426034
defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", avgflooru>;
60436035
defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
60446036
defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
@@ -6759,10 +6751,8 @@ defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>
67596751
defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
67606752
defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
67616753
defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull", AArch64pmull>;
6762-
defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
6763-
AArch64sabd>;
6764-
defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
6765-
AArch64sabd>;
6754+
defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal", abds>;
6755+
defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl", abds>;
67666756
defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
67676757
BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
67686758
defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
@@ -6780,8 +6770,7 @@ defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
67806770
BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
67816771
defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
67826772
BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
6783-
defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
6784-
AArch64uabd>;
6773+
defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal", abdu>;
67856774
defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
67866775
BinOpFrag<(add (zanyext node:$LHS), (zanyext node:$RHS))>>;
67876776
defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -287,6 +287,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
287287
.moreElementsToNextPow2(0)
288288
.lower();
289289

290+
getActionDefinitionsBuilder({G_ABDS, G_ABDU})
291+
.legalFor({v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
292+
.lower();
293+
290294
getActionDefinitionsBuilder(
291295
{G_SADDE, G_SSUBE, G_UADDE, G_USUBE, G_SADDO, G_SSUBO, G_UADDO, G_USUBO})
292296
.legalFor({{s32, s32}, {s64, s32}})
@@ -1794,6 +1798,10 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
17941798
return LowerBinOp(AArch64::G_SMULL);
17951799
case Intrinsic::aarch64_neon_umull:
17961800
return LowerBinOp(AArch64::G_UMULL);
1801+
case Intrinsic::aarch64_neon_sabd:
1802+
return LowerBinOp(TargetOpcode::G_ABDS);
1803+
case Intrinsic::aarch64_neon_uabd:
1804+
return LowerBinOp(TargetOpcode::G_ABDU);
17971805
case Intrinsic::aarch64_neon_abs: {
17981806
// Lower the intrinsic to G_ABS.
17991807
MIB.buildInstr(TargetOpcode::G_ABS, {MI.getOperand(0)}, {MI.getOperand(2)});

‎llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -71,12 +71,13 @@
7171
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
7272
#
7373
# DEBUG-NEXT: G_ABDS (opcode 65): 1 type index, 0 imm indices
74-
# DEBUG-NEXT:.. type index coverage check SKIPPED: no rules defined
75-
# DEBUG-NEXT:.. imm index coverage check SKIPPED: no rules defined
74+
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
75+
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
7676
#
77-
# DEBUG-NEXT:G_ABDU (opcode 66): 1 type index, 0 imm indices
78-
# DEBUG-NEXT:.. type index coverage check SKIPPED: no rules defined
79-
# DEBUG-NEXT:.. imm index coverage check SKIPPED: no rules defined
77+
# DEBUG-NEXT: G_ABDU (opcode 66): 1 type index, 0 imm indices
78+
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
79+
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
80+
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
8081
#
8182
# DEBUG-NEXT: G_IMPLICIT_DEF (opcode {{[0-9]+}}): 1 type index, 0 imm indices
8283
# DEBUG-NEXT: .. the first uncovered type index: {{[0-9]+}}, OK

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