[RISCV][GlobalIsel] Remove redundant sext.w for ADDIW (llvm#159597)

This is the minimal case generated by clang at `-O0`; I'm not sure if
writing the test this way is appropriate.

Author: sunshaoce

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

@@ -226,6 +226,8 @@ bool RISCVInstructionSelector::hasAllNBitUsers(const MachineInstr &MI,
     case RISCV::ADDW:
     case RISCV::ADDIW:
     case RISCV::SUBW:
+    case RISCV::FCVT_D_W:
+    case RISCV::FCVT_S_W:
       if (Bits >= 32)
         break;
       return false;

llvm/lib/Target/RISCV/RISCVGISel.td

@@ -143,6 +143,9 @@ def : Pat<(anyext (i32 GPR:$src)), (COPY GPR:$src)>;
 def : Pat<(sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
 def : Pat<(i32 (trunc GPR:$src)), (COPY GPR:$src)>;
 
+def : Pat<(sext_inreg (i64 (add GPR:$rs1, simm12:$imm)), i32),
+          (ADDIW GPR:$rs1, simm12:$imm)>;
+
 // Use sext if the sign bit of the input is 0.
 def : Pat<(zext_is_sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
 }

llvm/test/CodeGen/RISCV/GlobalISel/addiw-sext-inreg.ll

@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV64I
+
+define i32 @addiw_sext_inreg(i32 noundef signext %A) #0 {
+; RV64I-LABEL: addiw_sext_inreg:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    addiw a0, a0, 123
+; RV64I-NEXT:    ret
+entry:
+  %add = add nsw i32 123, %A
+  ret i32 %add
+}
+
+attributes #0 = { noinline nounwind optnone }