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[ARM] Auto-decode pred operands of Thumb instructions (llvm#156540)
Most predicable Thumb instructions do not encode the predicate operand, but rather take it from an enclosing IT block. Add `bits<0> p` to the encoding of these instructions to make the predicate operand decodable by the generated code. The previous approach was to analyze an instruction after it has been decoded and add missing predicate operand if necessary. The post-decoding pass is still required to check predicate applicability and advance IT block state, but it no longer modifies a decoded instruction. Some of the custom decoder methods have become redundant and can be removed in the future, delegating the decoding task to TableGen-erated decoder. Pull Request: llvm#156540
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-76
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8 files changed

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‎llvm/lib/Target/ARM/ARMInstrCDE.td‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,7 @@ class CDE_CX1_Instr<string iname, CX_Params params>
115115
!con(params.Iops1, (ins imm_13b:$imm), params.PredOp),
116116
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $imm"),
117117
params.Cstr> {
118+
bits<0> p;
118119
bits<13> imm;
119120
bits<4> Rd;
120121

@@ -131,6 +132,7 @@ class CDE_CX2_Instr<string iname, CX_Params params>
131132
!con(params.Iops2, (ins imm_9b:$imm), params.PredOp),
132133
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $imm"),
133134
params.Cstr> {
135+
bits<0> p;
134136
bits<9> imm;
135137
bits<4> Rd;
136138
bits<4> Rn;
@@ -149,6 +151,7 @@ class CDE_CX3_Instr<string iname, CX_Params params>
149151
!con(params.Iops3, (ins imm_6b:$imm), params.PredOp),
150152
!strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $Rm, $imm"),
151153
params.Cstr> {
154+
bits<0> p;
152155
bits<6> imm;
153156
bits<4> Rd;
154157
bits<4> Rn;

‎llvm/lib/Target/ARM/ARMInstrFormats.td‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1220,6 +1220,7 @@ class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
12201220
string opc, string asm, string cstr, list<dag> pattern>
12211221
: InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
12221222
bits<0> s;
1223+
bits<0> p;
12231224
let OutOperandList = !con(oops, (outs s_cc_out:$s));
12241225
let InOperandList = !con(iops, (ins pred:$p));
12251226
let AsmString = !strconcat(opc, "${s}${p}", asm);
@@ -1244,6 +1245,7 @@ class Thumb1pI<dag oops, dag iops, AddrMode am, int sz,
12441245
InstrItinClass itin,
12451246
string opc, string asm, string cstr, list<dag> pattern>
12461247
: InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1248+
bits<0> p;
12471249
let OutOperandList = oops;
12481250
let InOperandList = !con(iops, (ins pred:$p));
12491251
let AsmString = !strconcat(opc, "${p}", asm);
@@ -1343,6 +1345,7 @@ class Thumb2I<dag oops, dag iops, AddrMode am, int sz,
13431345
InstrItinClass itin,
13441346
string opc, string asm, string cstr, list<dag> pattern>
13451347
: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1348+
bits<0> p;
13461349
let OutOperandList = oops;
13471350
let InOperandList = !con(iops, (ins pred:$p));
13481351
let AsmString = !strconcat(opc, "${p}", asm);
@@ -1361,6 +1364,7 @@ class Thumb2sI<dag oops, dag iops, AddrMode am, int sz,
13611364
InstrItinClass itin,
13621365
string opc, string asm, string cstr, list<dag> pattern>
13631366
: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1367+
bits<0> p;
13641368
bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
13651369
let Inst{20} = s;
13661370

@@ -2221,6 +2225,7 @@ class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
22212225
InstrItinClass itin, string opc, string dt, string asm, string cstr,
22222226
list<dag> pattern>
22232227
: InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
2228+
bits<0> p;
22242229
let OutOperandList = oops;
22252230
let InOperandList = !con(iops, (ins pred:$p));
22262231
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
@@ -2234,6 +2239,7 @@ class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
22342239
InstrItinClass itin, string opc, string asm, string cstr,
22352240
list<dag> pattern>
22362241
: InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
2242+
bits<0> p;
22372243
let OutOperandList = oops;
22382244
let InOperandList = !con(iops, (ins pred:$p));
22392245
let AsmString = !strconcat(opc, "${p}", "\t", asm);

‎llvm/lib/Target/ARM/ARMInstrThumb.td‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -484,6 +484,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
484484
def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
485485
T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
486486
// A6.2.3 & A8.6.25
487+
bits<0> p;
487488
bits<4> Rm;
488489
let Inst{6-3} = Rm;
489490
let Inst{2-0} = 0b000;
@@ -492,6 +493,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
492493
def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>,
493494
Requires<[IsThumb, Has8MSecExt]>,
494495
T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
496+
bits<0> p;
495497
bits<4> Rm;
496498
let Inst{6-3} = Rm;
497499
let Inst{2-0} = 0b100;
@@ -524,6 +526,7 @@ let isCall = 1,
524526
"bl${p}\t$func",
525527
[(ARMcall tglobaladdr:$func)]>,
526528
Requires<[IsThumb]>, Sched<[WriteBrL]> {
529+
bits<0> p;
527530
bits<24> func;
528531
let Inst{26} = func{23};
529532
let Inst{25-16} = func{20-11};
@@ -537,6 +540,7 @@ let isCall = 1,
537540
(outs), (ins pred:$p, thumb_blx_target:$func), IIC_Br,
538541
"blx${p}\t$func", []>,
539542
Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> {
543+
bits<0> p;
540544
bits<24> func;
541545
let Inst{26} = func{23};
542546
let Inst{25-16} = func{20-11};
@@ -551,6 +555,7 @@ let isCall = 1,
551555
"blx${p}\t$func", []>,
552556
Requires<[IsThumb, HasV5T]>,
553557
T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
558+
bits<0> p;
554559
bits<4> func;
555560
let Inst{6-3} = func;
556561
let Inst{2-0} = 0b000;
@@ -566,6 +571,7 @@ let isCall = 1,
566571
"blxns${p}\t$func", []>,
567572
Requires<[IsThumb, Has8MSecExt]>,
568573
T1Special<{1,1,1,?}>, Sched<[WriteBrL]> {
574+
bits<0> p;
569575
bits<4> func;
570576
let Inst{6-3} = func;
571577
let Inst{2-0} = 0b100;
@@ -825,6 +831,7 @@ let hasSideEffects = 0 in {
825831
let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in
826832
def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
827833
IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
834+
bits<0> p;
828835
bits<3> Rn;
829836
bits<8> regs;
830837
let Inst{10-8} = Rn;
@@ -855,6 +862,7 @@ def tSTMIA_UPD : Thumb1I<(outs tGPR:$wb),
855862
AddrModeNone, 2, IIC_iStore_mu,
856863
"stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
857864
T1Encoding<{1,1,0,0,0,?}> {
865+
bits<0> p;
858866
bits<3> Rn;
859867
bits<8> regs;
860868
let Inst{10-8} = Rn;
@@ -873,6 +881,7 @@ def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
873881
IIC_iPop,
874882
"pop${p}\t$regs", []>,
875883
T1Misc<{1,1,0,?,?,?,?}>, Sched<[WriteLd]> {
884+
bits<0> p;
876885
bits<16> regs;
877886
let Inst{8} = regs{15};
878887
let Inst{7-0} = regs{7-0};
@@ -883,6 +892,7 @@ def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
883892
IIC_iStore_m,
884893
"push${p}\t$regs", []>,
885894
T1Misc<{0,1,0,?,?,?,?}>, Sched<[WriteST]> {
895+
bits<0> p;
886896
bits<16> regs;
887897
let Inst{8} = regs{14};
888898
let Inst{7-0} = regs{7-0};

‎llvm/lib/Target/ARM/ARMInstrThumb2.td‎

Lines changed: 20 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2059,6 +2059,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
20592059
def IA :
20602060
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
20612061
itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
2062+
bits<0> p;
20622063
bits<4> Rn;
20632064
bits<16> regs;
20642065

@@ -2074,6 +2075,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
20742075
def IA_UPD :
20752076
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
20762077
itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
2078+
bits<0> p;
20772079
bits<4> Rn;
20782080
bits<16> regs;
20792081

@@ -2089,6 +2091,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
20892091
def DB :
20902092
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
20912093
itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
2094+
bits<0> p;
20922095
bits<4> Rn;
20932096
bits<16> regs;
20942097

@@ -2104,6 +2107,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
21042107
def DB_UPD :
21052108
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
21062109
itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2110+
bits<0> p;
21072111
bits<4> Rn;
21082112
bits<16> regs;
21092113

@@ -2128,6 +2132,7 @@ multiclass thumb2_st_mult<string asm, InstrItinClass itin,
21282132
def IA :
21292133
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
21302134
itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
2135+
bits<0> p;
21312136
bits<4> Rn;
21322137
bits<16> regs;
21332138

@@ -2146,6 +2151,7 @@ multiclass thumb2_st_mult<string asm, InstrItinClass itin,
21462151
def IA_UPD :
21472152
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
21482153
itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
2154+
bits<0> p;
21492155
bits<4> Rn;
21502156
bits<16> regs;
21512157

@@ -2164,6 +2170,7 @@ multiclass thumb2_st_mult<string asm, InstrItinClass itin,
21642170
def DB :
21652171
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
21662172
itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
2173+
bits<0> p;
21672174
bits<4> Rn;
21682175
bits<16> regs;
21692176

@@ -2182,6 +2189,7 @@ multiclass thumb2_st_mult<string asm, InstrItinClass itin,
21822189
def DB_UPD :
21832190
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
21842191
itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2192+
bits<0> p;
21852193
bits<4> Rn;
21862194
bits<16> regs;
21872195

@@ -4030,9 +4038,11 @@ def t2TBH : T2I<(outs), (ins (addrmode_tbh $Rn, $Rm):$addr), IIC_Br,
40304038
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
40314039
// a two-value operand where a dag node expects ", "two operands. :(
40324040
let isBranch = 1, isTerminator = 1 in
4033-
def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
4034-
"b", ".w\t$target",
4035-
[/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> {
4041+
def t2Bcc : Thumb2XI<(outs), (ins brtarget:$target, pred:$p),
4042+
AddrModeNone, 4, IIC_Br,
4043+
"b${p}.w\t$target", "",
4044+
[/*(ARMbrcond bb:$target, imm:$cc)*/]>,
4045+
Sched<[WriteBr]> {
40364046
let Inst{31-27} = 0b11110;
40374047
let Inst{15-14} = 0b10;
40384048
let Inst{12} = 0;
@@ -5481,6 +5491,7 @@ class V8_1MI<dag oops, dag iops, AddrMode am, InstrItinClass itin, string asm,
54815491
def t2CLRM : V8_1MI<(outs),
54825492
(ins pred:$p, reglist_with_apsr:$regs, variable_ops),
54835493
AddrModeNone, NoItinerary, "clrm${p}", "$regs", "", []> {
5494+
bits<0> p;
54845495
bits<16> regs;
54855496

54865497
let Inst{31-16} = 0b1110100010011111;
@@ -5509,6 +5520,7 @@ def t2BF_LabelPseudo
55095520

55105521
def t2BFi : t2BF<(ins bflabel_u4:$b_label, bflabel_s16:$label, pred:$p),
55115522
!strconcat("bf", "${p}"), "$b_label, $label"> {
5523+
bits<0> p;
55125524
bits<4> b_label;
55135525
bits<16> label;
55145526

@@ -5540,6 +5552,7 @@ def t2BFic : t2BF<(ins bflabel_u4:$b_label, bflabel_s12:$label,
55405552

55415553
def t2BFr : t2BF<(ins bflabel_u4:$b_label, rGPR:$Rn, pred:$p),
55425554
!strconcat("bfx", "${p}"), "$b_label, $Rn"> {
5555+
bits<0> p;
55435556
bits<4> b_label;
55445557
bits<4> Rn;
55455558

@@ -5551,6 +5564,7 @@ def t2BFr : t2BF<(ins bflabel_u4:$b_label, rGPR:$Rn, pred:$p),
55515564

55525565
def t2BFLi : t2BF<(ins bflabel_u4:$b_label, bflabel_s18:$label, pred:$p),
55535566
!strconcat("bfl", "${p}"), "$b_label, $label"> {
5567+
bits<0> p;
55545568
bits<4> b_label;
55555569
bits<18> label;
55565570

@@ -5563,6 +5577,7 @@ def t2BFLi : t2BF<(ins bflabel_u4:$b_label, bflabel_s18:$label, pred:$p),
55635577

55645578
def t2BFLr : t2BF<(ins bflabel_u4:$b_label, rGPR:$Rn, pred:$p),
55655579
!strconcat("bflx", "${p}"), "$b_label, $Rn"> {
5580+
bits<0> p;
55665581
bits<4> b_label;
55675582
bits<4> Rn;
55685583

@@ -5826,6 +5841,7 @@ let Predicates = [IsThumb2, HasV8_1MMainline, HasPACBTI] in {
58265841
def t2PACG : V8_1MI<(outs rGPR:$Rd),
58275842
(ins pred:$p, GPRnopc:$Rn, GPRnopc:$Rm),
58285843
AddrModeNone, NoItinerary, "pacg${p}", "$Rd, $Rn, $Rm", "", []> {
5844+
bits<0> p;
58295845
bits<4> Rd;
58305846
bits<4> Rn;
58315847
bits<4> Rm;
@@ -5841,6 +5857,7 @@ let hasSideEffects = 1 in {
58415857
class PACBTIAut<dag iops, string asm, bit b>
58425858
: V8_1MI<(outs), iops,
58435859
AddrModeNone, NoItinerary, asm, "$Ra, $Rn, $Rm", "", []> {
5860+
bits<0> p;
58445861
bits<4> Ra;
58455862
bits<4> Rn;
58465863
bits<4> Rm;

‎llvm/lib/Target/ARM/CMakeLists.txt‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,7 @@ tablegen(LLVM ARMGenAsmMatcher.inc -gen-asm-matcher)
66
tablegen(LLVM ARMGenAsmWriter.inc -gen-asm-writer)
77
tablegen(LLVM ARMGenCallingConv.inc -gen-callingconv)
88
tablegen(LLVM ARMGenDAGISel.inc -gen-dag-isel)
9-
tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler
10-
-ignore-non-decodable-operands)
9+
tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler)
1110
tablegen(LLVM ARMGenFastISel.inc -gen-fast-isel)
1211
tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel)
1312
tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)

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