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Merge pull request #50 from yontank/yona_dev
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‎src/context/SimulationContext.tsx‎

Lines changed: 19 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ import {
2222
} from "react"
2323
import { toast } from "sonner"
2424

25-
type PlacedNode = {
25+
export type PlacedNode = {
2626
/**
2727
* The X coordinate of the node on the diagram.
2828
*/
@@ -144,6 +144,24 @@ export function SimulationContextProvider({ children }: Props) {
144144
const startSimulation = () => {
145145
if (editorRef.current == undefined)
146146
throw Error("Undefined Reference to the editor")
147+
148+
if (isNaN(parseInt(initialPC))) {
149+
toast.error("Empty Initial PC", {
150+
position: "bottom-left",
151+
description: "Please enter a value inside the initial PC input bar.",
152+
})
153+
return
154+
}
155+
156+
if(parseInt(initialPC) % 4 != 0){
157+
toast.error("PC Address must be divisible by 4", {
158+
position: "bottom-left",
159+
description: "all MIPS addresses must be divisible by 4.",
160+
})
161+
162+
return;
163+
}
164+
147165
const value = editorRef.current.getValue()
148166

149167
const r = assemble(value, Number(initialPC))

‎src/data/exams/2021.ts‎

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
import type { SimulationTemplate } from "./types"
2+
3+
export const Exams2021: Record<string, SimulationTemplate> = {
4+
//TODO: this exam uses a modified diagram (signExtend is replaced with shift left 16)
5+
"a-83": {
6+
/** Note: This exam sets its register values as UNKNOWN. */
7+
PCAddr: 0x07700024,
8+
code: "addi $16,$0,0x44\nsw $17,-0x4($16)\nadd $20,$16,$19\nsub $12,$16,$20\nand $19,$17,$20",
9+
registerInit: [
10+
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11+
0, 0, 0, 0, 0, 0, 0,
12+
],
13+
placedNodes: {},
14+
lineExecution: 2,
15+
},
16+
17+
"a-89": {
18+
PCAddr: 0x2855738c,
19+
code: "lw $11, 256($8)\nadd $7,$11,$11\nsub $9,$7,$12\nsw $9,0(16$)\nbeq $7,$11,0x00000000",
20+
registerInit: [
21+
0, 48, 96, 144, 192, 240, 288, 336, 384, 432, 480, 528, 576, 624, 672,
22+
720, 768, 816, 864, 912, 960, 1008, 1056, 1104, 1152, 1200, 1248, 1296,
23+
1344, 1392, 1440, 1488,
24+
],
25+
memoryInit: (address) => (address < 1000 ? -address : 0),
26+
lineExecution: 1,
27+
},
28+
29+
"c-83": {
30+
PCAddr: 0x02d0005c,
31+
code: "add $6, $7, $8\nlw $6,100($6)\nsub $10,$2,$6\nor $5, $7,$8",
32+
registerInit: [
33+
0, 3145728, 6291456, 9437184, 12582912, 15728640, 18874368, 22020096,
34+
25165824, 28311552, 31457280, 34603008, 37748736, 40894464, 44040192,
35+
47185920, 50331648, 53477376, 56623104, 59768832, 62914560, 66060288,
36+
69206016, 72351744, 75497472, 78643200, 81788928, 84934656, 88080384,
37+
91226112, 94371840, 97517568,
38+
],
39+
lineExecution: 2,
40+
},
41+
}

‎src/data/exams/2022.ts‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,78 @@
1+
import { makeShifter } from "@/logic/nodeTypes/shift"
2+
import type { SimulationTemplate } from "./types"
3+
4+
export const Exams2021: Record<string, SimulationTemplate> = {
5+
"a-82": {
6+
PCAddr: 0x0000300c,
7+
code: "sw $10,-0x100(10$)\naddi $10,$10,4\nadd $9,$10,$8\nlw $5,-0x100($10)\nor $3,$5,$10",
8+
registerInit: [
9+
0, 1904, 3808, 5712, 7616, 9520, 11424, 13328, 15232, 17136, 19040, 20944,
10+
22848, 24752, 26656, 28560, 30464, 32368, 34272, 36176, 38080, 39984,
11+
41888, 43792, 45696, 47600, 49504, 51408, 53312, 55216, 57120, 59024,
12+
],
13+
placedNodes: {
14+
"alu-in0": {
15+
x: 673,
16+
y: 406,
17+
nodeType: makeShifter("right", 1),
18+
},
19+
},
20+
lineExecution: 1,
21+
},
22+
23+
"a-62": {
24+
PCAddr: 0xad4aff00,
25+
code: "sw $10,-0x100(10$)\naddi $10,$10,4\nadd $9,$10,$8\nlw $5,-0x100(10$)\nor $3,$5,$10",
26+
registerInit: [
27+
0, 1904, 3808, 5712, 7616, 9520, 11424, 13328, 15232, 17136, 19040, 20944,
28+
22848, 24752, 26656, 28560, 30464, 32368, 34272, 36176, 38080, 39984,
29+
41888, 43792, 45696, 47600, 49504, 51408, 53312, 55216, 57120, 59024,
30+
],
31+
lineExecution: 1,
32+
},
33+
34+
/** NOTE: Register Values Unknown. */
35+
"a-75": {
36+
PCAddr: 0x00400000,
37+
code: "addi $16,$0,10\nlw $11,32(16$)\nor $7,$16,$11\nsub $9,$7,$11\nsw $9,4(16$)\n",
38+
registerInit: [
39+
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
40+
0, 0, 0, 0, 0, 0, 0,
41+
],
42+
placedNodes: {
43+
"muxMemToReg-in0": {
44+
x: 987,
45+
y: 644,
46+
nodeType: makeShifter("left", 5),
47+
},
48+
},
49+
memoryInit: (address) => (address < 125 ? 0x3d3d3d : 0),
50+
lineExecution: 3,
51+
},
52+
53+
"c-65": {
54+
PCAddr: 0x000020f4,
55+
code: "and $13,$7,$8\nlw $10,0x100($6)\nor $12,$6,$10\nbeq $6,$12,2,0xfffffffc",
56+
registerInit: [
57+
0, 1536, 3072, 4608, 6144, 7680, 9216, 10752, 12288, 13824, 15360, 16896,
58+
18432, 19968, 21504, 23040, 24576, 26112, 27648, 29184, 30720, 32256,
59+
33792, 35328, 36864, 38400, 39936, 41472, 43008, 44544, 46080, 47616,
60+
],
61+
lineExecution: 2,
62+
},
63+
"c-92": {
64+
/**
65+
* TODO: Modified PC to PC+8 + all shiftLeft2 replaced with shiftLeft3
66+
*
67+
*/
68+
PCAddr: 0x00002000,
69+
code: "sub $9,$8,$9\naddi $8,$9,0x100\naddi $8,$9,0x100\nbeq $1,$2,0x00000005\nlw $9,0x100($8)\nslt $1,$2,$1\nadd $17,$15,$9\nor $2,$6,$11\nsub $10,$4,$9",
70+
registerInit: [
71+
0, 272, 288, 304, 320, 336, 352, 368, 384, 400, 416, 432, 448, 464, 480,
72+
496, 512, 528, 544, 560, 576, 592, 608, 624, 640, 656, 672, 688, 704, 720,
73+
736, 752,
74+
],
75+
memoryInit: (address) => (address < 0x1000 * 4 ? address / 4 : 0),
76+
lineExecution: 5,
77+
},
78+
}

‎src/data/exams/2023.ts‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
import type { SimulationTemplate } from "./types"
2+
3+
export const Exams2023: Record<string, SimulationTemplate> = {
4+
// TODO: this exam uses a modified diagram (branchImmediateAdder becomes a Sub)
5+
"a-89": {
6+
PCAddr: 0x00aa889c,
7+
code: "lw $9, 0x400($16)\nadd $12,$17,$9\nsub $10,$12,$9\nbeq $9,$8,0xfffffffe",
8+
registerInit: [
9+
0, 64, 128, 192, 256, 320, 384, 448, 512, 576, 640, 704, 768, 832, 896,
10+
960, 1024, 1088, 1152, 1216, 1280, 1344, 1408, 1472, 1536, 1600, 1664,
11+
1728, 1792, 1856, 1920, 1984,
12+
],
13+
memoryInit: (address) => (address < 0x1000 ? address : 0),
14+
lineExecution: 1,
15+
},
16+
17+
// This exam changes too many things for us to implement, so we'll ignore it for now
18+
// "a-57": {
19+
20+
// }
21+
}

‎src/data/exams/2024.ts‎

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
import { not } from "@/logic/nodeTypes/not"
2+
import type { SimulationTemplate } from "./types"
3+
import { makeShifter } from "@/logic/nodeTypes/shift"
4+
5+
export const Exams2024: Record<string, SimulationTemplate> = {
6+
"c-93": {
7+
PCAddr: 0xaa573818,
8+
code: "ori $9,$30,0x4000\n lw $9,0x100($18)\nor $4,$9,$9 \nslt $5,$8,$6 \n",
9+
registerInit: [
10+
0, 592, 1184, 1776, 2368, 2960, 3552, 4144, 4736, 5328, 5920, 6512, 7104,
11+
7696, 8288, 8880, 9472, 10064, 10656, 11248, 11840, 12432, 13024, 13616,
12+
14208, 14800, 15392, 15984, 16576, 17168, 17760, 18352,
13+
],
14+
placedNodes: {
15+
"registers-readRegister1": {
16+
x: 409,
17+
y: 383,
18+
nodeType: makeShifter("rightLogical", 1),
19+
},
20+
},
21+
memoryInit: (address) =>
22+
address < 2500
23+
? 0xdededede
24+
: address < 5000
25+
? 0xfcfcfcfc
26+
: address < 7500
27+
? 0x575757
28+
: 0,
29+
lineExecution: 3,
30+
},
31+
32+
"a-91": {
33+
PCAddr: 0x0acd8080,
34+
code: "add $2,$2,$2 \nsub $2,$2,$1\nlw $3,0x2000($2)\n sub $30,$3,$2",
35+
registerInit: [
36+
0, 4194304, 8388608, 12582912, 16777216, 20971520, 25165824, 29360128,
37+
33554432, 37748736, 41943040, 46137344, 50331648, 54525952, 58720256,
38+
62914560, 67108864, 71303168, 75497472, 79691776, 83886080, 88080384,
39+
92274688, 96468992, 100663296, 104857600, 109051904, 113246208, 117440512,
40+
121634816, 125829120, 130023424,
41+
],
42+
placedNodes: {
43+
"splitterReadData2-in": {
44+
x: 661,
45+
y: 468,
46+
nodeType: makeShifter("left", 3),
47+
},
48+
},
49+
lineExecution: 2,
50+
},
51+
52+
"c-84": {
53+
PCAddr: 0x00001020,
54+
code: "and $5,$4,$4\nor $9,$3,$3\nlw $5,0x1024($9)\nsw $5,0x1028($9)\nslt $9,$5,$3",
55+
registerInit: [
56+
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
57+
0, 0, 0, 0, 0, 0, 0,
58+
],
59+
placedNodes: {
60+
"alu-in0": {
61+
x: 673,
62+
y: 406,
63+
nodeType: not,
64+
},
65+
},
66+
},
67+
}

‎src/data/exams/2025.ts‎

Lines changed: 65 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,65 @@
1+
import { makeShifter } from "@/logic/nodeTypes/shift"
2+
import type { SimulationTemplate } from "./types"
3+
import { not } from "@/logic/nodeTypes/not"
4+
import { neg } from "@/logic/nodeTypes/neg"
5+
6+
export const Exams2025: Record<string, SimulationTemplate> = {
7+
"a-94": {
8+
PCAddr: 0x0000bf70,
9+
code: "nop\nadd $4,$12,$6\nlw $4,-128($8)\naddi $4,$4,-128\nsw $6,-128($4)",
10+
registerInit: [
11+
0, 4096, 8192, 12288, 16384, 20480, 24576, 28672, 32768, 36864, 40960,
12+
45056, 49152, 53248, 57344, 61440, 65536, 69632, 73728, 77824, 81920,
13+
86016, 90112, 94208, 98304, 102400, 106496, 110592, 114688, 118784,
14+
122880, 126976,
15+
],
16+
placedNodes: {
17+
"registers-readRegister1": {
18+
x: 409,
19+
y: 383,
20+
nodeType: makeShifter("rightLogical", 1),
21+
},
22+
},
23+
lineExecution: 4,
24+
},
25+
26+
"a-81": {
27+
PCAddr: 0xaa00bb08,
28+
code: "sub $9,$9,$8\nori $9,$9,0x88\nlw $1,0x200($9)\nadd $2,$1,$8\nslt $2,$7,$4",
29+
registerInit: [
30+
0, 128, 256, 384, 512, 640, 768, 896, 1024, 1152, 1280, 1408, 1536, 1664,
31+
1792, 1920, 2048, 2176, 2304, 2432, 2560, 2688, 2816, 2944, 3072, 3200,
32+
3328, 3456, 3584, 3712, 3840, 3968,
33+
],
34+
placedNodes: {
35+
"registers-writeData": {
36+
x: 1033,
37+
y: 701,
38+
nodeType: not
39+
},
40+
},
41+
memoryInit: (address) =>
42+
address < 0x400
43+
? 0x17171717
44+
: address < 0x800
45+
? 0x23232323
46+
: address < 0xc00
47+
? 0xfefefefe
48+
: 0,
49+
lineExecution: 5,
50+
},
51+
52+
"a-87": {
53+
PCAddr: 0x00004af4,
54+
code: "addi $3,$0,-2816\nsw $3,0x4000($3)\nlw $2,19200($0)\nslt $4,$3,$2",
55+
registerInit: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
56+
placedNodes: {
57+
"muxMemToReg-in0": {
58+
x: 1046,
59+
y: 648,
60+
nodeType: neg
61+
}
62+
},
63+
lineExecution: 3
64+
}
65+
}

‎src/data/exams/types.ts‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
import type { PlacedNode } from "@/context/SimulationContext"
2+
import type { InputID } from "@/logic/simulation"
3+
4+
export type SimulationTemplate = {
5+
/**
6+
* The address of the first instruction in the code.
7+
*/
8+
PCAddr: number
9+
/**
10+
* The assembly code.
11+
*/
12+
code: string
13+
/**
14+
* An optional function that, given an address (of a word), returns the value at that address.
15+
*/
16+
memoryInit?: (address: number) => number
17+
/**
18+
* Initial values of all registers.
19+
*/
20+
registerInit: number[]
21+
/**
22+
* Additional nodes that are placed on the diagram.
23+
*/
24+
placedNodes?: Record<InputID, PlacedNode>
25+
/**
26+
* The line that the question asks to examine (probably unused)
27+
*/
28+
lineExecution?: number
29+
}

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