[AMDGPU] Handle phys regs in flat_scratch_base_hi operand check (llvm#170395)

Author: rampitec

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

@@ -6260,7 +6260,8 @@ bool SIInstrInfo::isLegalRegOperand(const MachineInstr &MI, unsigned OpIdx,
   if (ST.hasFlatScratchHiInB64InstHazard() &&
       MO.getReg() == AMDGPU::SRC_FLAT_SCRATCH_BASE_HI && isSALU(MI)) {
     if (const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::sdst)) {
-      if (AMDGPU::getRegBitWidth(*MRI.getRegClass(Dst->getReg())) == 64)
+      if (AMDGPU::getRegBitWidth(*RI.getRegClassForReg(MRI, Dst->getReg())) ==
+          64)
         return false;
     }
     if (Opc == AMDGPU::S_BITCMP0_B64 || Opc == AMDGPU::S_BITCMP1_B64)

llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir

@@ -143,3 +143,16 @@ body:             |
     %0:sreg_32 = COPY $src_flat_scratch_base_hi
     %1:sreg_64 = S_BITSET1_B64 %0, undef %1:sreg_64, implicit-def $scc
 ...
+
+---
+name:            s_ashr_i64_phys_dst
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; GCN-LABEL: name: s_ashr_i64_phys_dst
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
+    ; GCN-NEXT: $sgpr0_sgpr1 = S_ASHR_I64 undef %1:sreg_64, [[COPY]], implicit-def $scc
+    %0:sreg_32 = COPY $src_flat_scratch_base_hi
+    $sgpr0_sgpr1 = S_ASHR_I64 undef %1:sreg_64, %0, implicit-def $scc
+...