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[AMDGPU] Remove Dwarf encodings for subregisters
Previously, registers and subregisters mapped to the same Dwarf encoding. We don't really have any way to refer to subregisters directly from Dwarf, the expression emitter should instead use DW_OPs to stencil out the subregister from the whole register. This was also confusing tools that need to map back to the llvm reg (e.g. dwarfdump), since getLLVMRegNum() would arbitrarily return the _LO16 register. This is a cherry-pick of github.com/llvm/pull/117891 with test fixes. Change-Id: I155bce592c7d556c01a7e3048bb8b251109dd51d
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‎llvm/lib/Target/AMDGPU/SIRegisterInfo.td‎

Lines changed: 16 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -153,14 +153,16 @@ class SIRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList>
153153
}
154154

155155
multiclass SIRegLoHi16 <string n, bits<8> regIdx, bit ArtificialHigh = 1,
156-
bit isVGPR = 0, bit isAGPR = 0> {
156+
bit isVGPR = 0, bit isAGPR = 0,
157+
list<int> DwarfEncodings = [-1, -1]> {
157158
def _LO16 : SIReg<n#".l", regIdx, isVGPR, isAGPR>;
158159
def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx, isVGPR, isAGPR,
159160
/* isHi16 */ 1> {
160161
let isArtificial = ArtificialHigh;
161162
}
162163
def "" : RegisterWithSubRegs<n, [!cast<Register>(NAME#"_LO16"),
163-
!cast<Register>(NAME#"_HI16")]> {
164+
!cast<Register>(NAME#"_HI16")]>,
165+
DwarfRegNum<DwarfEncodings> {
164166
let Namespace = "AMDGPU";
165167
let SubRegIndices = [lo16, hi16];
166168
let CoveredBySubRegs = !not(ArtificialHigh);
@@ -197,7 +199,8 @@ def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> {
197199
let HWEncoding = VCC_LO.HWEncoding;
198200
}
199201

200-
defm EXEC_LO : SIRegLoHi16<"exec_lo", 126>, DwarfRegNum<[1, 1]>;
202+
defm EXEC_LO : SIRegLoHi16<"exec_lo", 126, /*ArtificialHigh=*/1, /*isVGPR=*/0,
203+
/*isAGPR=*/0, /*DwarfEncodings=*/[1, 1]>;
201204
defm EXEC_HI : SIRegLoHi16<"exec_hi", 127>;
202205

203206
def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> {
@@ -337,25 +340,26 @@ def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>;
337340
// SGPR registers
338341
foreach Index = 0...105 in {
339342
defm SGPR#Index :
340-
SIRegLoHi16 <"s"#Index, Index>,
341-
DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)),
342-
!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>;
343+
SIRegLoHi16 <"s"#Index, Index, /*ArtificialHigh=*/1,
344+
/*isVGPR=*/0, /*isAGPR=*/0, /*DwarfEncodings=*/
345+
[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)),
346+
!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>;
343347
}
344348

345349
// VGPR registers
346350
foreach Index = 0...255 in {
347351
defm VGPR#Index :
348-
SIRegLoHi16 <"v"#Index, Index, /* ArtificialHigh= */ 0,
349-
/* isVGPR= */ 1, /* isAGPR= */ 0>,
350-
DwarfRegNum<[!add(Index, 2560), !add(Index, 1536)]>;
352+
SIRegLoHi16 <"v"#Index, Index, /*ArtificialHigh=*/ 0,
353+
/*isVGPR=*/ 1, /*isAGPR=*/ 0, /*DwarfEncodings=*/
354+
[!add(Index, 2560), !add(Index, 1536)]>;
351355
}
352356

353357
// AccVGPR registers
354358
foreach Index = 0...255 in {
355359
defm AGPR#Index :
356-
SIRegLoHi16 <"a"#Index, Index, /* ArtificialHigh= */ 1,
357-
/* isVGPR= */ 0, /* isAGPR= */ 1>,
358-
DwarfRegNum<[!add(Index, 3072), !add(Index, 2048)]>;
360+
SIRegLoHi16 <"a"#Index, Index, /*ArtificialHigh=*/ 1,
361+
/*isVGPR=*/ 0, /*isAGPR=*/ 1, /*DwarfEncodings=*/
362+
[!add(Index, 3072), !add(Index, 2048)]>;
359363
}
360364

361365
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir‎

Lines changed: 7476 additions & 7476 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -11,15 +11,15 @@ body: |
1111
; GFX908: liveins: $vgpr0, $vgpr1
1212
; GFX908-NEXT: {{ $}}
1313
; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa <badreg>, 0, 6
14-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30_lo16, 32, $sgpr31_lo16, 32
15-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0_lo16
16-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1_lo16
17-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2_lo16
18-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3_lo16
19-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4_lo16
20-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5_lo16
21-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6_lo16
22-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7_lo16
14+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
15+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0
16+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1
17+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2
18+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3
19+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4
20+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5
21+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6
22+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7
2323
; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3
2424
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec
2525
; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec
@@ -51,14 +51,14 @@ body: |
5151
; GFX908-LABEL: name: src_is_spill
5252
; GFX908: liveins: $vgpr0, $vgpr1
5353
; GFX908-NEXT: {{ $}}
54-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32_lo16, 0, 6
55-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30_lo16, 32, $sgpr31_lo16, 32
56-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0_lo16
57-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1_lo16
58-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0_lo16
59-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1_lo16
60-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2_lo16
61-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3_lo16
54+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6
55+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
56+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0
57+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1
58+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0
59+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1
60+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2
61+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3
6262
; GFX908-NEXT: $agpr0_agpr1 = IMPLICIT_DEF
6363
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1
6464
; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit killed $agpr0_agpr1
@@ -84,11 +84,11 @@ body: |
8484
; GFX908: liveins: $agpr0_agpr1_agpr2_agpr3
8585
; GFX908-NEXT: {{ $}}
8686
; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa <badreg>, 0, 6
87-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30_lo16, 32, $sgpr31_lo16, 32
88-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1_lo16
89-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2_lo16
90-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3_lo16
91-
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4_lo16
87+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
88+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1
89+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2
90+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3
91+
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4
9292
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
9393
; GFX908-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit-def $agpr1_agpr2_agpr3_agpr4
9494
; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3

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