arc64: Remove mmpy64 option

Author: Claudiu Zissulescu

gcc/config/arc64/arc64.h

@@ -525,8 +525,6 @@ extern const enum reg_class arc64_regno_to_regclass[];
 #undef TARGET_ARC64_DIVREM_DEFAULT
 #define TARGET_ARC64_DIVREM_DEFAULT 0
 
-#define TARGET_ARC64_MPY64 TARGET_MPY64
-
 /* IFCVT macros.  */
 #define STORE_FLAG_VALUE 1
 #define MAX_CONDITIONAL_EXECUTE 12

gcc/config/arc64/arc64.md

@@ -105,10 +105,6 @@
 ;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
 (define_mode_iterator GPI [SI DI])
 
-;; Iterator for General Purpose Integer registers (32- and 64-bit
-;; modes) used by MPY instructions
-(define_mode_iterator GPIM [SI (DI "TARGET_ARC64_MPY64")])
-
 ;; Iterator for QI and HI modes
 (define_mode_iterator SHORT [QI HI])
 
@@ -139,9 +135,6 @@
 ;; Three operand arithmetic operations
 (define_code_iterator ARITH [plus minus mult])
 
-;; Three operand 64 bit arithmetic operations
-(define_code_iterator ARITH64 [plus minus (mult "TARGET_ARC64_MPY64")])
-
 ;; Three operand logic operations
 (define_code_iterator LOGIC [and ior xor smin smax])
 
@@ -1026,8 +1019,8 @@ umodl, unknown, xbfu, xor, xorl"
 
 (define_expand "<optab>di3"
   [(set (match_operand:DI 0 "register_operand")
-	(ARITH64:DI (match_operand:DI 1 "register_operand")
-		    (match_operand:DI 2 "nonmemory_operand")))]
+	(ARITH:DI (match_operand:DI 1 "register_operand")
+		  (match_operand:DI 2 "nonmemory_operand")))]
   ""
   {
    if (!register_operand (operands[2], DImode))

gcc/config/arc64/arc64.opt

@@ -60,10 +60,6 @@ mdiv-rem
 Target Report Var(TARGET_ARC64_DIVREM) Init(TARGET_ARC64_DIVREM_DEFAULT)
 Enable DIV-REM instructions.
 
-mmpy64
-Target Report Mask(MPY64)
-Enable MPY64 multiplication instructions.
-
 mcpu=
 Target RejectNegative Joined
 -mcpu= Generate code for specific ARCv3 CPU variant.

gcc/config/arc64/arith.md

@@ -562,9 +562,9 @@
    (set_attr "predicable" "yes,no,no,yes,no")])
 
 (define_insn "*mul<mode>3"
- [(set (match_operand:GPIM 0 "register_operand"             "=q,q,     r,     r,    r,    r,    r")
-       (mult:GPIM (match_operand:GPIM 1 "register_operand"  "%0,q,     0,     r,    0,    0,    r")
-		  (match_operand:GPIM 2 "nonmemory_operand"  "q,0,rU06S0,rU06S0,S12S0,S32S0,S32S0")))]
+ [(set (match_operand:GPI 0 "register_operand"             "=q,q,     r,     r,    r,    r,    r")
+       (mult:GPI (match_operand:GPI 1 "register_operand"  "%0,q,     0,     r,    0,    0,    r")
+		 (match_operand:GPI 2 "nonmemory_operand"  "q,0,rU06S0,rU06S0,S12S0,S32S0,S32S0")))]
  ""
  "@
   mpy<sfxtab>%?\\t%0,%1,%2
@@ -583,9 +583,9 @@
   [(cond_exec
     (match_operator 3 "ordered_comparison_operator"
 		    [(match_operand 4 "cc_register" "") (const_int 0)])
-    (set (match_operand:GPIM 0 "register_operand"             "=     r,    r")
-	 (mult:GPIM (match_operand:GPIM 1 "register_operand"  "%     0,    0")
-		    (match_operand:GPIM 2 "nonmemory_operand"  "rU06S0,S32S0"))))]
+    (set (match_operand:GPI 0 "register_operand"             "=     r,    r")
+	 (mult:GPI (match_operand:GPI 1 "register_operand"  "%     0,    0")
+		   (match_operand:GPI 2 "nonmemory_operand"  "rU06S0,S32S0"))))]
  ""
  "mpy<sfxtab>.%m3\\t%0,%1,%2"
  [(set_attr "length" "4,8")
@@ -594,12 +594,12 @@
 (define_insn "*mul<mode>3_cmp0"
   [(set (reg:CC_ZN CC_REGNUM)
 	(compare:CC_ZN
-	 (mult:GPIM
-	  (match_operand:GPIM 1 "register_operand"  "%     0,     r,    0,    0,    r")
-	  (match_operand:GPIM 2 "nonmemory_operand"  "rU06S0,rU06S0,S12S0,S32S0,S32S0"))
+	 (mult:GPI
+	  (match_operand:GPI 1 "register_operand"  "%     0,     r,    0,    0,    r")
+	  (match_operand:GPI 2 "nonmemory_operand"  "rU06S0,rU06S0,S12S0,S32S0,S32S0"))
 	 (const_int 0)))
-   (set (match_operand:GPIM 0 "register_operand"   "=     r,     r,    r,    r,    r")
-	(mult:GPIM (match_dup 1) (match_dup 2)))]
+   (set (match_operand:GPI 0 "register_operand"   "=     r,     r,    r,    r,    r")
+	(mult:GPI (match_dup 1) (match_dup 2)))]
  ""
  "mpy<sfxtab>%?.f\\t%0,%1,%2"
  [(set_attr "length" "4,4,4,8,8")
@@ -610,9 +610,9 @@
 (define_insn "*mul<mode>3_cmp0_noout"
   [(set (reg:CC_ZN CC_REGNUM)
 	(compare:CC_ZN
-	 (mult:GPIM
-	  (match_operand:GPIM 0 "register_operand"  "%     r,    r,    r")
-	  (match_operand:GPIM 1 "nonmemory_operand"  "rU06S0,S12S0,S32S0"))
+	 (mult:GPI
+	  (match_operand:GPI 0 "register_operand"  "%     r,    r,    r")
+	  (match_operand:GPI 1 "nonmemory_operand"  "rU06S0,S12S0,S32S0"))
 	 (const_int 0)))]
  ""
  "mpy<sfxtab>%?.f\\t0,%0,%1"
@@ -643,7 +643,7 @@
 	   (ANY_EXTEND:TI (match_operand:DI 1 "register_operand" "%0,r"))
 	   (ANY_EXTEND:TI (match_operand:DI 2 "register_operand" "r,r")))
 	  (const_int 64))))]
-  "TARGET_ARC64_MPY64"
+  ""
   "mpym<su_optab>l%?\\t%0,%1,%2"
   [(set_attr "type" "mpyl")
    (set_attr "length" "4")
@@ -653,7 +653,7 @@
   [(set (match_operand:TI 0 "register_operand")
 	(mult:TI (ANY_EXTEND:TI (match_operand:DI 1 "register_operand"))
 		 (ANY_EXTEND:TI (match_operand:DI 2 "register_operand"))))]
-  "TARGET_ARC64_MPY64"
+  ""
 {
   rtx low = gen_reg_rtx (DImode);
   emit_insn (gen_muldi3 (low, operands[1], operands[2]));
@@ -670,7 +670,7 @@
   [(set (match_operand:TI                          0 "register_operand")
 	(mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand"))
 		 (sign_extend:TI (match_operand:DI 2 "register_operand"))))]
-  "TARGET_ARC64_MPY64"
+  ""
 {
   rtx low = gen_reg_rtx (DImode);
   emit_insn (gen_muldi3 (low, operands[1], operands[2]));
@@ -692,7 +692,7 @@
 		   (sign_extend:TI
 		    (match_operand:DI 2 "register_operand" " r")))
 	  (const_int 64))))]
-  "TARGET_ARC64_MPY64"
+  ""
   "mpymsul\t%0,%2,%1"
   [(set_attr "type" "mpyl")
    (set_attr "length" "4")])