arc64: Add the new ARCv3 ATO instruction support.

Add support for the new atld.<ops>/arldl.<ops> instructions.
The following operations are supported by GCC:
-ADD
-AND
-OR
-XOR

The next builtin macros are defined:
__ARC64_ATOMIC_1__
__ARC64_ATOMIC_2__
__ARC64_ATOMIC_3__

The following builtin macro is removed:
__ARC64_ATOMIC__

Signed-off-by: Claudiu Zissulescu <[email protected]>

Author: Claudiu Zissulescu

gcc/config/arc64/arc64-c.c

@@ -56,9 +56,6 @@ arc64_cpu_cpp_builtins (cpp_reader * pfile)
   builtin_define ("__LITTLE_ENDIAN__");
   builtin_define ("__ARCV3__");
 
-  if (arc64_atomic_option)
-    builtin_define_with_int_value ("__ARC64_ATOMIC__", arc64_atomic_option);
-
   if (arc64_cmodel_var == ARC64_CMODEL_SMALL)
     builtin_define ("__ARC64_CMODEL_SMALL__");
   else if (arc64_cmodel_var == ARC64_CMODEL_MEDIUM)

gcc/config/arc64/arc64-c.def

@@ -17,7 +17,9 @@
    <http://www.gnu.org/licenses/>.
 */
 
-//ARC_C_DEF ("__ARC_UNALIGNED__", unaligned_access)
+ARC64_C_DEF ("__ARC64_ATOMIC_1__", arc64_atomic_option == 1)
+ARC64_C_DEF ("__ARC64_ATOMIC_2__", arc64_atomic_option == 2)
+ARC64_C_DEF ("__ARC64_ATOMIC_3__", arc64_atomic_option == 3)
 
 /* Local Variables: */
 /* mode: c */

gcc/config/arc64/arc64-protos.h

@@ -27,6 +27,8 @@ extern rtx arc64_eh_return_handler_rtx (void);
 extern int arc64_asm_preferred_eh_data_format (int, int);
 
 extern void arc64_expand_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx);
+extern void arc64_pre_atomic_barrier (enum memmodel);
+extern void arc64_post_atomic_barrier (enum memmodel);
 extern void arc64_expand_compare_and_swap (rtx []);
 extern void arc64_split_compare_and_swap (rtx []);
 extern bool arc64_allow_direct_access_p (rtx);

gcc/config/arc64/arc64.c

@@ -2240,26 +2240,6 @@ emit_unlikely_jump (rtx insn)
   add_reg_br_prob_note (jump, profile_probability::very_unlikely ());
 }
 
-/* Emit a (pre) memory barrier around an atomic sequence according to
-   MODEL.  */
-
-static void
-arc64_pre_atomic_barrier (enum memmodel model)
-{
-  if (need_atomic_barrier_p (model, true))
-    emit_insn (gen_memory_barrier ());
-}
-
-/* Emit a (post) memory barrier around an atomic sequence according to
-   MODEL.  */
-
-static void
-arc64_post_atomic_barrier (enum memmodel model)
-{
-  if (need_atomic_barrier_p (model, false))
-    emit_insn (gen_memory_barrier ());
-}
-
 /* Expand code to perform a 8 or 16-bit compare and swap by doing
    32-bit compare and swap on the word containing the byte or
    half-word.  The difference between a weak and a strong CAS is that
@@ -2995,6 +2975,26 @@ arc64_asm_preferred_eh_data_format (int code ATTRIBUTE_UNUSED, int global)
    return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
 }
 
+/* Emit a (pre) memory barrier around an atomic sequence according to
+   MODEL.  */
+
+void
+arc64_pre_atomic_barrier (enum memmodel model)
+{
+  if (need_atomic_barrier_p (model, true))
+    emit_insn (gen_memory_barrier ());
+}
+
+/* Emit a (post) memory barrier around an atomic sequence according to
+   MODEL.  */
+
+void
+arc64_post_atomic_barrier (enum memmodel model)
+{
+  if (need_atomic_barrier_p (model, false))
+    emit_insn (gen_memory_barrier ());
+}
+
 /* Expand an atomic fetch-and-operate pattern.  CODE is the binary operation
    to perform.  MEM is the memory on which to operate.  VAL is the second
    operand of the binary operator.  BEFORE and AFTER are optional locations to

gcc/config/arc64/arc64.md

@@ -90,6 +90,7 @@
    ARC64_VUNSPEC_SC
    ARC64_VUNSPEC_LL
    ARC64_VUNSPEC_SYNC
+   ARC64_VUNSPEC_ATOOPS
 
    ARC64_UNSPEC_MEMBAR
    ])
@@ -241,13 +242,14 @@
 ;; this.  For optimizing for size the "length" attribute is used instead.
 (define_attr "cost" "" (const_int 0))
 
-(define_attr "type" "abs, adcl, add, addhl, addl, and, andl, asl, asll, asr,
-asrl, bic, bl, block, bmsk, branch, branchcc, brk, bset, bsetl, btst, bxor,
-bxorl, compare, dbnz, dmb, ex, div, divl, ext, flag, jl, jump, ld, llock,
-lsr, lsrl, lr, max, maxl, min, minl, move, movecc, mod, modl, neg, nop,
-norm, normh, norml, mpy, mpyl, not, notl, or, orl, return, ror,rol, sbcl,
-scond, setcc, sex, sr, st, sub, subl, swape, swapel, sync, trap, udiv,
-udivl, umod, umodl, unknown, xbfu, xor, xorl"
+(define_attr "type" "abs, adcl, add, addhl, addl, and, andl, asl,
+asll, asr, asrl, atldop, atldlop, bic, bl, block, bmsk, branch,
+branchcc, brk, bset, bsetl, btst, bxor, bxorl, compare, dbnz, dmb, ex,
+div, divl, ext, flag, jl, jump, ld, llock, lsr, lsrl, lr, max, maxl,
+min, minl, move, movecc, mod, modl, neg, nop, norm, normh, norml, mpy,
+mpyl, not, notl, or, orl, return, ror,rol, sbcl, scond, setcc, sex,
+sr, st, sub, subl, swape, swapel, sync, trap, udiv, udivl, umod,
+umodl, unknown, xbfu, xor, xorl"
   (const_string "unknown"))
 
 (define_attr "iscompact" "yes,no,maybe" (const_string "no"))

gcc/config/arc64/atomic.md

@@ -20,6 +20,9 @@
 ;; Operations which can be used with atomic loads and stores.
 (define_code_iterator ATOPS [plus minus ior xor and])
 
+;; Operations which are supported by hardware.
+(define_code_iterator ATHWOPS [plus ior xor and])
+
 (define_expand "memory_barrier"
   [(set (match_dup 0)
 	(unspec:BLK [(match_dup 0)] ARC64_UNSPEC_MEMBAR))]
@@ -82,7 +85,7 @@
 	  [(match_operand:GPI 1 "mem_noofs_operand" "ATOMC")]
 	  ARC64_VUNSPEC_LL))]
   "ARC64_HAS_ATOMIC_1"
-  "llock<mcctab> %0,%1"
+  "llock<mcctab>\\t%0,%1"
   [(set_attr "type" "llock")
    (set_attr "iscompact" "no")
    (set_attr "predicable" "no")
@@ -94,7 +97,7 @@
 			   ARC64_VUNSPEC_SC))
    (clobber (reg:CC_Z CC_REGNUM))]
   "ARC64_HAS_ATOMIC_1"
-  "scond<mcctab> %1,%0"
+  "scond<mcctab>\\t%1,%0"
   [(set_attr "type" "scond")
    (set_attr "iscompact" "no")
    (set_attr "predicable" "no")
@@ -122,12 +125,35 @@
    (set (match_dup 1)
 	(match_operand:GPI 2 "register_operand" "0"))]
   ""
-  "ex<mcctab> %0,%1"
+  "ex<mcctab>\\t%0,%1"
   [(set_attr "type" "ex")
    (set_attr "iscompact" "no")
    (set_attr "predicable" "no")
    (set_attr "length" "*")])
 
+;; New Atomic options enabled by option 2
+(define_insn_and_split "atld_<optab><mode>"
+  [(set (match_operand:GPI 0 "register_operand" "=&r,r")
+	(match_operand:GPI 1 "mem_noofs_operand" "+ATOMC,ATOMC"))
+   (set (match_dup 1)
+	(unspec_volatile:GPI
+	 [(ATHWOPS:GPI (match_dup 0)
+		       (match_operand:GPI 2 "register_operand" "0,r"))
+	  (match_operand:SI 3 "const_int_operand")]
+	 ARC64_VUNSPEC_ATOOPS))]
+  "ARC64_HAS_ATOMIC_2"
+  "@
+   atld<sfxtab>.<optab>\\t%0,%1
+   #"
+  "&& reload_completed && !operands_match_p (operands[0], operands[2])"
+  [(const_int 0)]
+  {
+   emit_insn (gen_rtx_SET (operands[0], operands[2]));
+   emit_insn (gen_atld_<optab><mode> (operands[0], operands[1], operands[0], operands[3]));
+   DONE;
+  }
+  [(set_attr "type" "atld<sfxtab>op")])
+
 (define_expand "atomic_<optab><mode>"
   [(match_operand:GPI 0 "mem_noofs_operand" "")  ;; memory
    (ATOPS:GPI (match_dup 0)
@@ -152,17 +178,46 @@
 })
 
 (define_expand "atomic_fetch_<optab><mode>"
-  [(match_operand:GPI 0 "register_operand" "")	;; output
-   (match_operand:GPI 1 "mem_noofs_operand" "")	;; memory
-   (ATOPS:GPI (match_dup 1)
-	      (match_operand:GPI 2 "register_operand" "")) ;; operand
-   (match_operand:SI 3 "const_int_operand" "")]	;; model
+  [(set (match_operand:GPI 0 "register_operand")	;; output
+	(match_operand:GPI 1 "mem_noofs_operand"))	;; memory
+   (set (match_dup 1)
+	(unspec_volatile:GPI
+	 [(ATHWOPS:GPI (match_dup 1)
+		     (match_operand:GPI 2 "register_operand")) ;; operand
+	  (match_operand:SI 3 "const_int_operand")]	;; model
+	 ARC64_VUNSPEC_ATOOPS))]
   "ARC64_HAS_ATOMIC_1"
-{
-  arc64_expand_atomic_op (<CODE>, operands[1], operands[2],
-				operands[0], NULL_RTX, operands[3]);
-  DONE;
-})
+  {
+   if (!ARC64_HAS_ATOMIC_2)
+     {
+       arc64_expand_atomic_op (<CODE>, operands[1], operands[2],
+			       operands[0], NULL_RTX, operands[3]);
+       DONE;
+     }
+    if (!ARC64_HAS_ATOMIC_3)
+      arc64_pre_atomic_barrier ((enum memmodel) INTVAL (operands[3]));
+    emit_insn (gen_atld_<optab><mode> (operands[0], operands[1], operands[2], operands[3]));
+    if (!ARC64_HAS_ATOMIC_3)
+      arc64_post_atomic_barrier ((enum memmodel) INTVAL (operands[3]));
+    DONE;
+   })
+
+;; ARCv3 doesn't have a MINUS atomic memory operation.
+(define_expand "atomic_fetch_sub<mode>"
+  [(set (match_operand:GPI 0 "register_operand")	;; output
+	(match_operand:GPI 1 "mem_noofs_operand"))	;; memory
+   (set (match_dup 1)
+	(unspec_volatile:GPI
+	 [(minus:GPI (match_dup 1)
+		     (match_operand:GPI 2 "register_operand")) ;; operand
+	  (match_operand:SI 3 "const_int_operand")]	;; model
+	 ARC64_VUNSPEC_ATOOPS))]
+  "ARC64_HAS_ATOMIC_1"
+  {
+    arc64_expand_atomic_op (MINUS, operands[1], operands[2],
+			    operands[0], NULL_RTX, operands[3]);
+    DONE;
+  })
 
 (define_expand "atomic_fetch_nand<mode>"
   [(match_operand:GPI 0 "register_operand" "")	;; output
@@ -201,3 +256,13 @@
   DONE;
 })
 
+
+;; mode:emacs-lisp
+;; comment-start: ";; "
+;; eval: (set-syntax-table (caopy-sequence (syntax-table)))
+;; eval: (modify-syntax-entry ?[ "(]")
+;; eval: (modify-syntax-entry ?] ")[")
+;; eval: (modify-syntax-entry ?{ "(}")
+;; eval: (modify-syntax-entry ?} "){")
+;; eval: (setq indent-tabs-mode t)
+;; End: