arc64: Use sign_extend when loading.

Author: Claudiu Zissulescu

gcc/config/arc64/arc64.c

@@ -2791,17 +2791,6 @@ arc_expand_compare_and_swap_qh (rtx bool_result, rtx result, rtx mem,
   emit_move_insn (result, gen_lowpart (GET_MODE (result), res));
 }
 
-/* On some RISC architectures with 64-bit registers, the processor
-   also maintains 32-bit condition codes that make it possible to do
-   real 32-bit arithmetic, although the operations are performed on
-   the full registers.  This hook needs to be define if
-   WORD_REGISTER_OPERATIONS is not defined to 1.  */
-
-static unsigned int
-arc64_min_arithmeric_precision (void)
-{
-  return 32;
-}
 
 /* This hook may conditionally modify five variables: fixed_regs,
    call_used_regs, global_regs, reg_names and reg_class_contents.  */
@@ -3470,6 +3459,12 @@ arc64_rtx_costs (rtx x, machine_mode mode, rtx_code outer,
       op0 = XEXP (x, 0);
 
       /* Zero extending from an SI operation is cheap.  */
+      if (MEM_P (op0))
+	{
+	  /* All loads can zero extend to any size for free.  */
+	  *cost += rtx_cost (op0, VOIDmode, ZERO_EXTEND, 0, speed);
+	  return true;
+	}
       if (mode == DImode
 	  && GET_MODE (op0) == SImode
 	  && outer == SET)
@@ -3479,12 +3474,6 @@ arc64_rtx_costs (rtx x, machine_mode mode, rtx_code outer,
 	    *cost = op_cost;
 	  return true;
 	}
-      else if (MEM_P (op0))
-	{
-	  /* All loads can zero extend to any size for free.  */
-	  *cost = rtx_cost (op0, VOIDmode, ZERO_EXTEND, 0, speed);
-	  return true;
-	}
       break;
 
     case SIGN_EXTEND:
@@ -4926,9 +4915,6 @@ arc64_expand_fvect_shr (rtx *operands)
 #undef  TARGET_MACHINE_DEPENDENT_REORG
 #define TARGET_MACHINE_DEPENDENT_REORG arc64_reorg
 
-#undef TARGET_MIN_ARITHMETIC_PRECISION
-#define TARGET_MIN_ARITHMETIC_PRECISION arc64_min_arithmeric_precision
-
 #undef TARGET_CONDITIONAL_REGISTER_USAGE
 #define TARGET_CONDITIONAL_REGISTER_USAGE arc64_conditional_register_usage
 

gcc/config/arc64/arc64.h

@@ -344,16 +344,15 @@ enum reg_class
 /* Tell GCC to use RETURN_IN_MEMORY.  */
 #define DEFAULT_PCC_STRUCT_RETURN 0
 
-/* WORD_REGISTER_OPERATIONS does not hold for arc64.  The assigned
-   word_mode is DImode but operations narrower than SImode behave as
-   32-bit operations.  */
-#define WORD_REGISTER_OPERATIONS 0
+/* To be check: WORD_REGISTER_OPERATIONS, ARC64 has 32bit
+   opertations.  */
+#define WORD_REGISTER_OPERATIONS 1
 
 /* Define if loading from memory in MODE, an integral mode narrower than
    BITS_PER_WORD will either zero-extend or sign-extend.  The value of this
    macro should be the code that says which one of the two operations is
    implicitly done, or UNKNOWN if none.  */
-#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
+#define LOAD_EXTEND_OP(MODE) (((MODE) == SImode) ? SIGN_EXTEND : ZERO_EXTEND)
 
 #define SLOW_BYTE_ACCESS 0
 

gcc/config/arc64/arc64.md

@@ -1518,7 +1518,7 @@ vfrep, vpack, xbfu, xor, xorl"
   [(set (match_operand:DI 0 "register_operand"       "=r,r")
 	(sign_extend:DI
 	 (match_operand:EXT 1 "nonimmediate_operand"  "r,m")))]
-   ""
+   "(!TARGET_VOLATILE_DI) || (!MEM_VOLATILE_P (operands[1]))"
    "@
    sex<exttab>l\\t%0,%1
    ld<sfxtab>.x%U1\\t%0,%1"