Revert "arc64: Add table-jump support."

This reverts commit 8cc5bee986806d0dc60a11e0b7bd625f631b72ad.

Author: Claudiu Zissulescu

gcc/config/arc64/arc64-protos.h

@@ -29,7 +29,6 @@ extern int arc64_asm_preferred_eh_data_format (int, int);
 extern void arc64_expand_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx);
 extern void arc64_expand_compare_and_swap (rtx []);
 extern void arc64_split_compare_and_swap (rtx []);
-extern void arc64_expand_casesi (rtx []);
 extern bool arc64_allow_direct_access_p (rtx);
 
 #endif /* RTX_CODE */

gcc/config/arc64/arc64.c

@@ -3181,6 +3181,7 @@ arc64_split_compare_and_swap (rtx operands[])
     emit_label (label2);
 }
 
+#if 0
 /* Expander for casesi.  The vector table is always PC-relative, and
    it is made up of branch instructions.  When we have CODE_DENSITY
    option enabled, we use BI instruction, otherwise, depending on the
@@ -3241,6 +3242,7 @@ void arc64_expand_casesi (rtx operands[])
 
   emit_jump_insn (gen_casesi_dispatch (operands[0], operands[3]));
 }
+#endif
 
 bool
 arc64_allow_direct_access_p (rtx op)

gcc/config/arc64/arc64.h

@@ -423,11 +423,7 @@ extern const enum reg_class arc64_regno_to_regclass[];
 /* Names to predefine in the preprocessor for this target machine.  */
 #define TARGET_CPU_CPP_BUILTINS() arc64_cpu_cpp_builtins (pfile)
 
-/* Dispatch tables.  */
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-#define CASE_VECTOR_MODE SImode
-#define CASE_VECTOR_PC_RELATIVE 1
-#define ADDR_VEC_ALIGN(VEC_INSN) 0
+#define CASE_VECTOR_MODE Pmode
 
 /* Define this macro if it is advisable to hold scalars in registers
    in a wider mode than that declared by the program.  In such cases,
@@ -473,16 +469,6 @@ extern const enum reg_class arc64_regno_to_regclass[];
     }							\
   while (0)
 
-#define LOCAL_LABEL_PREFIX	"."
-
-/* This is how to output an element of a PIC case-vector. */
-#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)		\
-  fprintf (STREAM, "\tb\t@%sL%d\n",					\
-	   LOCAL_LABEL_PREFIX, VALUE)
-
-/* Defined to also emit an .align in elfos.h.  We don't want that.  */
-#undef ASM_OUTPUT_CASE_LABEL
-
 /* Section selection.  */
 
 /* Globalizing directive for a label.  */
@@ -536,8 +522,6 @@ extern const enum reg_class arc64_regno_to_regclass[];
 
 #define TARGET_ARC64_MPY64 TARGET_MPY64
 
-#define ARC64_HAS_CODE_DENSITY TARGET_CODE_DENSITY
-
 /* IFCVT macros.  */
 #define STORE_FLAG_VALUE 1
 #define MAX_CONDITIONAL_EXECUTE 12

gcc/config/arc64/arc64.md

@@ -76,10 +76,8 @@
    ARC64_UNSPEC_TLS_GD
    ARC64_UNSPEC_TLS_IE
    ARC64_UNSPEC_TLS_OFF
-   ARC64_UNSPEC_MEMBAR
-   ARC64_UNSPEC_CASESI
-
    ARC64_VUNSPEC_BLOCKAGE
+
    ARC64_VUNSPEC_LR
    ARC64_VUNSPEC_SR
    ARC64_VUNSPEC_FLAG
@@ -93,6 +91,7 @@
    ARC64_VUNSPEC_LL
    ARC64_VUNSPEC_SYNC
 
+   ARC64_UNSPEC_MEMBAR
    ])
 
 (include "constraints.md")
@@ -290,17 +289,6 @@ udivl, umod, umodl, unknown, xbfu, xor, xorl"
     ]
    (const_int 8)))
 
-;; Select various CPU features.
-(define_attr "cpu_facility" "std,cd"
-  (const_string "std"))
-
-(define_attr "enabled" "no,yes"
-  (cond [(and (eq_attr "cpu_facility" "cd")
-	      (not (match_test ("ARC64_HAS_CODE_DENSITY"))))
-	 (const_string "no")
-	 ]
-	(const_string "yes")))
-
 ;; -------------------------------------------------------------------
 ;; Pipeline descriptions and scheduling
 ;; -------------------------------------------------------------------
@@ -925,64 +913,6 @@ udivl, umod, umodl, unknown, xbfu, xor, xorl"
   [(set_attr "type" "return")
    (set_attr "length" "4")])
 
-; jump tables
-(define_expand "casesi"
-  [(match_operand:SI 0 "register_operand" "")	; Index
-   (match_operand 1 "const_int_operand" "")	; Lower bound
-   (match_operand 2 "const_int_operand" "")	; Total range
-   (match_operand 3 "" "")		; Table label
-   (match_operand 4 "" "")]		; Out of range label
-  ""
- {
-   arc64_expand_casesi (operands);
-   DONE;
-   })
-
-(define_insn "casesi_dispatch"
-  [(set (pc)
-	(unspec:DI [(match_operand:SI 0 "register_operand" "r,q,r")
-		    (label_ref (match_operand 1 "" ""))
-		    (const_int 0)]
-		   ARC64_UNSPEC_CASESI))]
-  ""
-  "@
-  bi\\t[%0]
-  j_s\\t[%0]
-  j\\t[%0]"
-  [(set_attr "type" "jump")
-   (set_attr "length" "4,2,4")
-   (set_attr "cpu_facility" "cd,*,*")])
-
-(define_insn "casesi_addaddr"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(unspec:SI [(match_operand:SI 1 "register_operand" "r")
-		    (label_ref (match_operand 2 "" ""))
-		    (const_int 1)]
-		   ARC64_UNSPEC_CASESI))]
-  ""
-  "add2\\t%0,%l2,%1"
-  [(set_attr "type" "add")
-   (set_attr "length" "8")])
-
-(define_insn "casesi_addaddrdi"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(unspec:DI [(match_operand:SI 1 "register_operand" "r")
-		    (match_operand:DI 2 "register_operand" "r")
-		    (const_int 2)]
-		   ARC64_UNSPEC_CASESI))]
-  ""
-  "add2l\\t%0,%2,%1"
-  [(set_attr "type" "addl")
-   (set_attr "length" "4")])
-
-(define_insn "casesi_dispatchdi"
-  [(set (pc) (match_operand:DI 0 "register_operand" "q,r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "j%?\\t[%0]"
-  [(set_attr "type" "jump")
-   (set_attr "length" "2,4")])
-
 
 ;; -------------------------------------------------------------------
 ;; Sign/Zero extension

gcc/config/arc64/arc64.opt

@@ -67,7 +67,3 @@ Enable MPY64 multiplication instructions.
 mcpu=
 Target RejectNegative Joined
 -mcpu= Generate code for specific ARCv3 CPU variant.
-
-mcode-density
-Target Report Mask(CODE_DENSITY)
-Enable code-density instructions.