Skip to content

Commit eff9536

Browse files
kito-chengstephanosio
kito-cheng
authored and
stephanosio
committed
RISC-V: Rename constraint c0* to k0*
Rename those constraint since we want define other constraint start with `c`, those constraints are internal and undocumented, so it's fine to rename. gcc/ChangeLog: * config/riscv/constraints.md (c01): Rename to... (k01): ...this. (c02): Rename to... (k02): ...this. (c03): Rename to... (k03): ...this. (c04): Rename to... (k04): ...this. (c08): Rename to... (k08): ...this. * config/riscv/corev.md (riscv_cv_simd_add_h_si): Update constraints. (riscv_cv_simd_sub_h_si): Ditto. (riscv_cv_simd_cplxmul_i_si): Ditto. (riscv_cv_simd_subrotmj_si): Ditto. * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Update constraints. * config/riscv/vector-iterators.md (stride_load_constraint): Update constraints. (stride_store_constraint): Ditto. (cherry picked from commit 1a2e0fc)
1 parent 2836263 commit eff9536

File tree

4 files changed

+51
-51
lines changed

4 files changed

+51
-51
lines changed

‎gcc/config/riscv/constraints.md

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -45,27 +45,27 @@
4545
(and (match_code "const_int")
4646
(match_test "ival == 0")))
4747

48-
(define_constraint "c01"
48+
(define_constraint "k01"
4949
"Constant value 1."
5050
(and (match_code "const_int")
5151
(match_test "ival == 1")))
5252

53-
(define_constraint "c02"
53+
(define_constraint "k02"
5454
"Constant value 2"
5555
(and (match_code "const_int")
5656
(match_test "ival == 2")))
5757

58-
(define_constraint "c03"
58+
(define_constraint "k03"
5959
"Constant value 3"
6060
(and (match_code "const_int")
6161
(match_test "ival == 3")))
6262

63-
(define_constraint "c04"
63+
(define_constraint "k04"
6464
"Constant value 4"
6565
(and (match_code "const_int")
6666
(match_test "ival == 4")))
6767

68-
(define_constraint "c08"
68+
(define_constraint "k08"
6969
"Constant value 8"
7070
(and (match_code "const_int")
7171
(match_test "ival == 8")))

‎gcc/config/riscv/corev.md

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -871,7 +871,7 @@
871871
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
872872
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r")
873873
(match_operand:SI 2 "register_operand" "r,r,r,r")
874-
(match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")]
874+
(match_operand:QI 3 "const_int2_operand" "J,k01,k02,k03")]
875875
UNSPEC_CV_ADD_H))]
876876
"TARGET_XCVSIMD && !TARGET_64BIT"
877877
"@
@@ -924,7 +924,7 @@
924924
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
925925
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r")
926926
(match_operand:SI 2 "register_operand" "r,r,r,r")
927-
(match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")]
927+
(match_operand:QI 3 "const_int2_operand" "J,k01,k02,k03")]
928928
UNSPEC_CV_SUB_H))]
929929
"TARGET_XCVSIMD && !TARGET_64BIT"
930930
"@
@@ -2561,7 +2561,7 @@
25612561
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r")
25622562
(match_operand:SI 2 "register_operand" "r,r,r,r")
25632563
(match_operand:SI 3 "register_operand" "0,0,0,0")
2564-
(match_operand:QI 4 "const_int2_operand" "J,c01,c02,c03")]
2564+
(match_operand:QI 4 "const_int2_operand" "J,k01,k02,k03")]
25652565
UNSPEC_CV_CPLXMUL_R))]
25662566
"TARGET_XCVSIMD && !TARGET_64BIT"
25672567
"@
@@ -2578,7 +2578,7 @@
25782578
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r")
25792579
(match_operand:SI 2 "register_operand" "r,r,r,r")
25802580
(match_operand:SI 3 "register_operand" "0,0,0,0")
2581-
(match_operand:QI 4 "const_int2_operand" "J,c01,c02,c03")]
2581+
(match_operand:QI 4 "const_int2_operand" "J,k01,k02,k03")]
25822582
UNSPEC_CV_CPLXMUL_I))]
25832583
"TARGET_XCVSIMD && !TARGET_64BIT"
25842584
"@
@@ -2604,7 +2604,7 @@
26042604
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
26052605
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r")
26062606
(match_operand:SI 2 "register_operand" "r,r,r,r")
2607-
(match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")]
2607+
(match_operand:QI 3 "const_int2_operand" "J,k01,k02,k03")]
26082608
UNSPEC_CV_SUBROTMJ))]
26092609
"TARGET_XCVSIMD && !TARGET_64BIT"
26102610
"@

‎gcc/config/riscv/riscv-v.cc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5234,7 +5234,7 @@ splat_to_scalar_move_p (rtx *ops)
52345234
return satisfies_constraint_Wc1 (ops[1])
52355235
&& satisfies_constraint_vu (ops[2])
52365236
&& !MEM_P (ops[3])
5237-
&& satisfies_constraint_c01 (ops[4])
5237+
&& satisfies_constraint_k01 (ops[4])
52385238
&& INTVAL (ops[7]) == NONVLMAX
52395239
&& known_ge (GET_MODE_SIZE (Pmode), GET_MODE_SIZE (GET_MODE (ops[3])));
52405240
}

‎gcc/config/riscv/vector-iterators.md

Lines changed: 40 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -3434,61 +3434,61 @@
34343434
])
34353435

34363436
(define_mode_attr stride_load_constraint [
3437-
(RVVM8QI "rJ,rJ,rJ,c01,c01,c01") (RVVM4QI "rJ,rJ,rJ,c01,c01,c01")
3438-
(RVVM2QI "rJ,rJ,rJ,c01,c01,c01") (RVVM1QI "rJ,rJ,rJ,c01,c01,c01")
3439-
(RVVMF2QI "rJ,rJ,rJ,c01,c01,c01") (RVVMF4QI "rJ,rJ,rJ,c01,c01,c01")
3440-
(RVVMF8QI "rJ,rJ,rJ,c01,c01,c01")
3437+
(RVVM8QI "rJ,rJ,rJ,k01,k01,k01") (RVVM4QI "rJ,rJ,rJ,k01,k01,k01")
3438+
(RVVM2QI "rJ,rJ,rJ,k01,k01,k01") (RVVM1QI "rJ,rJ,rJ,k01,k01,k01")
3439+
(RVVMF2QI "rJ,rJ,rJ,k01,k01,k01") (RVVMF4QI "rJ,rJ,rJ,k01,k01,k01")
3440+
(RVVMF8QI "rJ,rJ,rJ,k01,k01,k01")
34413441

3442-
(RVVM8HI "rJ,rJ,rJ,c02,c02,c02") (RVVM4HI "rJ,rJ,rJ,c02,c02,c02")
3443-
(RVVM2HI "rJ,rJ,rJ,c02,c02,c02") (RVVM1HI "rJ,rJ,rJ,c02,c02,c02")
3444-
(RVVMF2HI "rJ,rJ,rJ,c02,c02,c02") (RVVMF4HI "rJ,rJ,rJ,c02,c02,c02")
3442+
(RVVM8HI "rJ,rJ,rJ,k02,k02,k02") (RVVM4HI "rJ,rJ,rJ,k02,k02,k02")
3443+
(RVVM2HI "rJ,rJ,rJ,k02,k02,k02") (RVVM1HI "rJ,rJ,rJ,k02,k02,k02")
3444+
(RVVMF2HI "rJ,rJ,rJ,k02,k02,k02") (RVVMF4HI "rJ,rJ,rJ,k02,k02,k02")
34453445

3446-
(RVVM8HF "rJ,rJ,rJ,c02,c02,c02") (RVVM4HF "rJ,rJ,rJ,c02,c02,c02")
3447-
(RVVM2HF "rJ,rJ,rJ,c02,c02,c02") (RVVM1HF "rJ,rJ,rJ,c02,c02,c02")
3448-
(RVVMF2HF "rJ,rJ,rJ,c02,c02,c02") (RVVMF4HF "rJ,rJ,rJ,c02,c02,c02")
3446+
(RVVM8HF "rJ,rJ,rJ,k02,k02,k02") (RVVM4HF "rJ,rJ,rJ,k02,k02,k02")
3447+
(RVVM2HF "rJ,rJ,rJ,k02,k02,k02") (RVVM1HF "rJ,rJ,rJ,k02,k02,k02")
3448+
(RVVMF2HF "rJ,rJ,rJ,k02,k02,k02") (RVVMF4HF "rJ,rJ,rJ,k02,k02,k02")
34493449

3450-
(RVVM8SI "rJ,rJ,rJ,c04,c04,c04") (RVVM4SI "rJ,rJ,rJ,c04,c04,c04")
3451-
(RVVM2SI "rJ,rJ,rJ,c04,c04,c04") (RVVM1SI "rJ,rJ,rJ,c04,c04,c04")
3452-
(RVVMF2SI "rJ,rJ,rJ,c04,c04,c04")
3450+
(RVVM8SI "rJ,rJ,rJ,k04,k04,k04") (RVVM4SI "rJ,rJ,rJ,k04,k04,k04")
3451+
(RVVM2SI "rJ,rJ,rJ,k04,k04,k04") (RVVM1SI "rJ,rJ,rJ,k04,k04,k04")
3452+
(RVVMF2SI "rJ,rJ,rJ,k04,k04,k04")
34533453

3454-
(RVVM8SF "rJ,rJ,rJ,c04,c04,c04") (RVVM4SF "rJ,rJ,rJ,c04,c04,c04")
3455-
(RVVM2SF "rJ,rJ,rJ,c04,c04,c04") (RVVM1SF "rJ,rJ,rJ,c04,c04,c04")
3456-
(RVVMF2SF "rJ,rJ,rJ,c04,c04,c04")
3454+
(RVVM8SF "rJ,rJ,rJ,k04,k04,k04") (RVVM4SF "rJ,rJ,rJ,k04,k04,k04")
3455+
(RVVM2SF "rJ,rJ,rJ,k04,k04,k04") (RVVM1SF "rJ,rJ,rJ,k04,k04,k04")
3456+
(RVVMF2SF "rJ,rJ,rJ,k04,k04,k04")
34573457

3458-
(RVVM8DI "rJ,rJ,rJ,c08,c08,c08") (RVVM4DI "rJ,rJ,rJ,c08,c08,c08")
3459-
(RVVM2DI "rJ,rJ,rJ,c08,c08,c08") (RVVM1DI "rJ,rJ,rJ,c08,c08,c08")
3458+
(RVVM8DI "rJ,rJ,rJ,k08,k08,k08") (RVVM4DI "rJ,rJ,rJ,k08,k08,k08")
3459+
(RVVM2DI "rJ,rJ,rJ,k08,k08,k08") (RVVM1DI "rJ,rJ,rJ,k08,k08,k08")
34603460

3461-
(RVVM8DF "rJ,rJ,rJ,c08,c08,c08") (RVVM4DF "rJ,rJ,rJ,c08,c08,c08")
3462-
(RVVM2DF "rJ,rJ,rJ,c08,c08,c08") (RVVM1DF "rJ,rJ,rJ,c08,c08,c08")
3461+
(RVVM8DF "rJ,rJ,rJ,k08,k08,k08") (RVVM4DF "rJ,rJ,rJ,k08,k08,k08")
3462+
(RVVM2DF "rJ,rJ,rJ,k08,k08,k08") (RVVM1DF "rJ,rJ,rJ,k08,k08,k08")
34633463
])
34643464

34653465
(define_mode_attr stride_store_constraint [
3466-
(RVVM8QI "rJ,c01") (RVVM4QI "rJ,c01")
3467-
(RVVM2QI "rJ,c01") (RVVM1QI "rJ,c01")
3468-
(RVVMF2QI "rJ,c01") (RVVMF4QI "rJ,c01")
3469-
(RVVMF8QI "rJ,c01")
3466+
(RVVM8QI "rJ,k01") (RVVM4QI "rJ,k01")
3467+
(RVVM2QI "rJ,k01") (RVVM1QI "rJ,k01")
3468+
(RVVMF2QI "rJ,k01") (RVVMF4QI "rJ,k01")
3469+
(RVVMF8QI "rJ,k01")
34703470

3471-
(RVVM8HI "rJ,c02") (RVVM4HI "rJ,c02")
3472-
(RVVM2HI "rJ,c02") (RVVM1HI "rJ,c02")
3473-
(RVVMF2HI "rJ,c02") (RVVMF4HI "rJ,c02")
3471+
(RVVM8HI "rJ,k02") (RVVM4HI "rJ,k02")
3472+
(RVVM2HI "rJ,k02") (RVVM1HI "rJ,k02")
3473+
(RVVMF2HI "rJ,k02") (RVVMF4HI "rJ,k02")
34743474

3475-
(RVVM8HF "rJ,c02") (RVVM4HF "rJ,c02")
3476-
(RVVM2HF "rJ,c02") (RVVM1HF "rJ,c02")
3477-
(RVVMF2HF "rJ,c02") (RVVMF4HF "rJ,c02")
3475+
(RVVM8HF "rJ,k02") (RVVM4HF "rJ,k02")
3476+
(RVVM2HF "rJ,k02") (RVVM1HF "rJ,k02")
3477+
(RVVMF2HF "rJ,k02") (RVVMF4HF "rJ,k02")
34783478

3479-
(RVVM8SI "rJ,c04") (RVVM4SI "rJ,c04")
3480-
(RVVM2SI "rJ,c04") (RVVM1SI "rJ,c04")
3481-
(RVVMF2SI "rJ,c04")
3479+
(RVVM8SI "rJ,k04") (RVVM4SI "rJ,k04")
3480+
(RVVM2SI "rJ,k04") (RVVM1SI "rJ,k04")
3481+
(RVVMF2SI "rJ,k04")
34823482

3483-
(RVVM8SF "rJ,c04") (RVVM4SF "rJ,c04")
3484-
(RVVM2SF "rJ,c04") (RVVM1SF "rJ,c04")
3485-
(RVVMF2SF "rJ,c04")
3483+
(RVVM8SF "rJ,k04") (RVVM4SF "rJ,k04")
3484+
(RVVM2SF "rJ,k04") (RVVM1SF "rJ,k04")
3485+
(RVVMF2SF "rJ,k04")
34863486

3487-
(RVVM8DI "rJ,c08") (RVVM4DI "rJ,c08")
3488-
(RVVM2DI "rJ,c08") (RVVM1DI "rJ,c08")
3487+
(RVVM8DI "rJ,k08") (RVVM4DI "rJ,k08")
3488+
(RVVM2DI "rJ,k08") (RVVM1DI "rJ,k08")
34893489

3490-
(RVVM8DF "rJ,c08") (RVVM4DF "rJ,c08")
3491-
(RVVM2DF "rJ,c08") (RVVM1DF "rJ,c08")
3490+
(RVVM8DF "rJ,k08") (RVVM4DF "rJ,k08")
3491+
(RVVM2DF "rJ,k08") (RVVM1DF "rJ,k08")
34923492
])
34933493

34943494
(define_mode_attr gs_extension [

0 commit comments

Comments
 (0)