wifi: winc1500: update HAL version to 19.7.6

Author: lromeraj

asf/common/components/wifi/winc1500/bsp/include/nm_bsp.h

@@ -1,14 +1,120 @@
-/*
- * Copyright (c) 2016 Intel Corporation.
+/**
+ *
+ * \file
+ *
+ * \brief This module contains NMC1500 BSP APIs declarations.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
  *
- * SPDX-License-Identifier: Apache-2.0
  */
-
+/**@defgroup  BSPDefine Defines
+ * @ingroup nm_bsp
+ * @{
+ */
 #ifndef _NM_BSP_INTERNAL_H_
 #define _NM_BSP_INTERNAL_H_
 
-#if defined(CONFIG_WIFI_WINC1500)
-#include <wifi_winc1500_nm_bsp_internal.h>
-#endif /* CONFIG_WIFI_WINC1500 */
 
-#endif //_NM_BSP_INTERNAL_H_
+
+#ifdef WIN32
+#include "nm_bsp_win32.h"
+#endif
+
+#ifdef __K20D50M__
+#include "nm_bsp_k20d50m.h"
+#endif
+
+#ifdef __MSP430FR5739__
+#include "bsp_msp430fr5739.h"
+#endif
+
+#ifdef _FREESCALE_MCF51CN128_
+#include "bsp/include/nm_bsp_mcf51cn128.h"
+#endif
+
+#ifdef __MCF964548__
+#include "bsp/include/nm_bsp_mc96f4548.h"
+#endif
+
+#ifdef __APP_APS3_CORTUS__
+#include "nm_bsp_aps3_cortus.h"
+#endif
+
+#if (defined __SAMR21G18A__) || (defined __SAMR21E18A__)
+#include "bsp/include/nm_bsp_samr21.h"
+#endif
+
+#if (defined __SAML21J18A__) || (defined __SAML21J18B__)
+#include "bsp/include/nm_bsp_saml21.h"
+#endif
+
+#if (defined __SAML22N18A__)
+#include "bsp/include/nm_bsp_saml22.h"
+#endif
+
+#if (defined __SAMD21J18A__) || (defined __SAMD21G18A__)
+#include "bsp/include/nm_bsp_samd21.h"
+#endif
+
+#if (defined __SAM4S16C__) || (defined __SAM4SD32C__)
+#include "bsp/include/nm_bsp_sam4s.h"
+#endif
+
+#ifdef __SAMG53N19__
+#include "bsp/include/nm_bsp_samg53.h"
+#endif
+
+#ifdef __SAMG55J19__
+#include "bsp/include/nm_bsp_samg55.h"
+#endif
+
+#if (defined __SAME70Q21__) || (defined __SAME70Q21B__) || (defined __SAMV71Q21__)
+#include "bsp/include/nm_bsp_same70.h"
+#endif
+
+#if (defined __SAMR30G18A__) || (defined __SAMR30E18A__)
+#include "bsp/include/nm_bsp_samr30.h"
+#endif
+
+#ifdef CORTUS_APP
+#include "crt_iface.h"
+#endif
+
+#ifdef NRF51
+#include "nm_bsp_nrf51822.h"
+#endif
+
+#ifdef _ARDUINO_UNO_
+#include "bsp/include/nm_bsp_arduino_uno.h"
+#endif
+
+#ifdef CONFIG_ATMEL_WINC1500
+#include "wifi_winc1500_nm_bsp_internal.h"
+#endif
+
+
+#endif //_NM_BSP_INTERNAL_H_

asf/common/components/wifi/winc1500/bsp/include/nm_bsp_internal.h

@@ -4,36 +4,29 @@
  *
  * \brief This module contains NMC1000 bus wrapper APIs declarations.
  *
- * Copyright (c) 2016-2017 Atmel Corporation. All rights reserved.
+ * Copyright (c) 2016-2021 Microchip Technology Inc. and its subsidiaries.
  *
  * \asf_license_start
  *
  * \page License
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
  *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
  *
  * \asf_license_stop
  *
@@ -59,12 +52,12 @@
 												(same start/stop conditions) ==> I2C only. Parameter:tstrNmI2cSpecial */
 #define NM_BUS_IOCTL_RW			((uint8)3)	/*!< Read/Write at the same time ==> SPI only. Parameter:tstrNmSpiRw */
 
-#define NM_BUS_IOCTL_WR_RESTART	((uint8)4)				/*!< Write buffer then made restart condition then read ==> I2C only. parameter:tstrNmI2cSpecial */
+#define NM_BUS_IOCTL_WR_RESTART	((uint8)4)				/*!< Write buffer then made restart condition then read ==> I2C only. parameter:tstrNmI2cSpecial */ 
 /**
 *	@struct	tstrNmBusCapabilities
 *	@brief	Structure holding bus capabilities information
 *	@sa	NM_BUS_TYPE_I2C, NM_BUS_TYPE_SPI
-*/
+*/ 
 typedef struct
 {
 	uint16	u16MaxTrxSz;	/*!< Maximum transfer size. Must be >= 16 bytes*/
@@ -74,7 +67,7 @@ typedef struct
 *	@struct	tstrNmI2cDefault
 *	@brief	Structure holding I2C default operation parameters
 *	@sa		NM_BUS_IOCTL_R, NM_BUS_IOCTL_W
-*/
+*/ 
 typedef struct
 {
 	uint8 u8SlaveAdr;
@@ -86,12 +79,12 @@ typedef struct
 *	@struct	tstrNmI2cSpecial
 *	@brief	Structure holding I2C special operation parameters
 *	@sa		NM_BUS_IOCTL_W_SPECIAL
-*/
+*/ 
 typedef struct
 {
 	uint8 u8SlaveAdr;
 	uint8	*pu8Buf1;	/*!< pointer to the 1st buffer */
-	uint8	*pu8Buf2;	/*!< pointer to the 2nd buffer */
+	uint8	*pu8Buf2;	/*!< pointer to the 2nd buffer */	
 	uint16	u16Sz1;		/*!< 1st buffer size */
 	uint16	u16Sz2;		/*!< 2nd buffer size */
 } tstrNmI2cSpecial;
@@ -100,22 +93,22 @@ typedef struct
 *	@struct	tstrNmSpiRw
 *	@brief	Structure holding SPI R/W parameters
 *	@sa		NM_BUS_IOCTL_RW
-*/
+*/ 
 typedef struct
 {
-	uint8	*pu8InBuf;		/*!< pointer to input buffer.
+	uint8	*pu8InBuf;		/*!< pointer to input buffer. 
 							Can be set to null and in this case zeros should be sent at MOSI */
-	uint8	*pu8OutBuf;		/*!< pointer to output buffer.
+	uint8	*pu8OutBuf;		/*!< pointer to output buffer. 
 							Can be set to null and in this case data from MISO can be ignored  */
-	uint16	u16Sz;			/*!< Transfere size */
+	uint16	u16Sz;			/*!< Transfere size */	
 } tstrNmSpiRw;
 
 
 /**
 *	@struct	tstrNmUartDefault
 *	@brief	Structure holding UART default operation parameters
 *	@sa		NM_BUS_IOCTL_R, NM_BUS_IOCTL_W
-*/
+*/ 
 typedef struct
 {
 	uint8	*pu8Buf;	/*!< Operation buffer */
@@ -132,7 +125,7 @@ extern tstrNmBusCapabilities egstrNmBusCapabilities;
 *	@fn		nm_bus_init
 *	@brief	Initialize the bus wrapper
 *	@return	ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure
-*/
+*/ 
 sint8 nm_bus_init(void *);
 
 /**
@@ -144,14 +137,14 @@ sint8 nm_bus_init(void *);
 *					Arbitrary parameter depending on IOCTL
 *	@return	ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure
 *	@note	For SPI only, it's important to be able to send/receive at the same time
-*/
+*/ 
 sint8 nm_bus_ioctl(uint8 u8Cmd, void* pvParameter);
 
 /**
 *	@fn		nm_bus_deinit
 *	@brief	De-initialize the bus wrapper
 *	@return	ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure
-*/
+*/ 
 sint8 nm_bus_deinit(void);
 
 /*
@@ -166,11 +159,24 @@ sint8 nm_bus_reinit(void *);
 *	@fn			nm_bus_get_chip_type
 *	@brief		get chip type
 *	@return		ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure
-*/
+*/ 
 #ifdef CONF_WINC_USE_UART
 uint8 nm_bus_get_chip_type(void);
 sint8 nm_bus_break(void);
 #endif
+
+/**
+ *  @fn         spi_rw
+ *  @brief      Process SPI Read/Write operation
+ *  @param      pu8Mosi TX Data buffer
+ *  @param      pu8Miso RX Data buffer
+ *  @param      u16Sz Transfer length
+ *  @return     ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure
+ */
+#ifdef CONF_WINC_USE_SPI
+sint8 nm_spi_rw(uint8* pu8Mosi, uint8* pu8Miso, uint16 u16Sz);
+#endif
+
 #ifdef __cplusplus
 	 }
  #endif