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ext: Import Atmel SAMR35 header files from ASF library
Atmel Software Framework (ASF) provides a set of low-level header files that give access to different hardware peripherals of Atmel's ICs. Origin: Atmel SAMR35 Series Device Support (1.0.10) License: Apache-2.0 URL: http://packs.download.atmel.com/Atmel.SAMR35_DFP.1.0.10.atpack Purpose: Introduction of ASF for the SAM0 series. Maintained-by: External Signed-off-by: Attie Grande <[email protected]>
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‎asf/sam0/include/samr35/component-version.h‎

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/**
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* \file
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*
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* \brief Component version header file
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*
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* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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#ifndef _COMPONENT_VERSION_H_INCLUDED
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#define _COMPONENT_VERSION_H_INCLUDED
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#define COMPONENT_VERSION_MAJOR 1
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#define COMPONENT_VERSION_MINOR 0
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//
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// The COMPONENT_VERSION define is composed of the major and the minor version number.
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//
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// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
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// The rest of the COMPONENT_VERSION is the major version.
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//
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#define COMPONENT_VERSION 10000
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//
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// The build number does not refer to the component, but to the build number
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// of the device pack that provides the component.
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//
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#define BUILD_NUMBER 10
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//
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// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
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//
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#define COMPONENT_VERSION_STRING "1.0"
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//
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// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
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//
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// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
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//
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// "%Y-%m-%d %H:%M:%S"
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//
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//
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#define COMPONENT_DATE_STRING "2018-10-26 15:19:18"
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#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
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‎asf/sam0/include/samr35/component/ac.h‎

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‎asf/sam0/include/samr35/component/adc.h‎

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‎asf/sam0/include/samr35/component/aes.h‎

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‎asf/sam0/include/samr35/component/ccl.h‎

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/**
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* \file
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*
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* \brief Component description for CCL
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMR35_CCL_COMPONENT_
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#define _SAMR35_CCL_COMPONENT_
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/* ========================================================================== */
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/** SOFTWARE API DEFINITION FOR CCL */
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/* ========================================================================== */
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/** \addtogroup SAMR35_CCL Configurable Custom Logic */
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/*@{*/
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#define CCL_U2225
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#define REV_CCL 0x101
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/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t SWRST:1; /*!< bit: 0 Software Reset */
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uint8_t ENABLE:1; /*!< bit: 1 Enable */
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uint8_t :4; /*!< bit: 2.. 5 Reserved */
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uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
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uint8_t :1; /*!< bit: 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} CCL_CTRL_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */
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#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */
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#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */
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#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos)
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#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */
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#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos)
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#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run during Standby */
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#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos)
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#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */
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/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */
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uint8_t :4; /*!< bit: 4.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} CCL_SEQCTRL_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */
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#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */
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#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */
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#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos)
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#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos))
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#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */
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#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */
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#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */
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#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */
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#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */
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#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos)
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#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos)
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#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos)
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#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos)
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#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos)
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#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */
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/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t :1; /*!< bit: 0 Reserved */
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uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */
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uint32_t :2; /*!< bit: 2.. 3 Reserved */
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uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */
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uint32_t :1; /*!< bit: 6 Reserved */
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uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */
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uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */
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uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */
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uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */
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uint32_t INVEI:1; /*!< bit: 20 Input Event Invert */
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uint32_t LUTEI:1; /*!< bit: 21 Event Input Enable */
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uint32_t LUTEO:1; /*!< bit: 22 Event Output Enable */
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uint32_t :1; /*!< bit: 23 Reserved */
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uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} CCL_LUTCTRL_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */
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#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */
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#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */
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#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos)
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#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */
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#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos)
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#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos))
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#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */
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#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */
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#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */
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#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos)
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#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos)
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#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos)
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#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */
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#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos)
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#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */
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#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos)
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#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos))
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#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
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#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
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#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
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#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event in put source */
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#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
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#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
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#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
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#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
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#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
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#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM inout source */
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#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos)
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#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos)
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#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos)
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#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos)
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#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos)
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#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos)
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#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos)
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#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos)
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#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos)
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#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos)
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#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */
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#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos)
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#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos))
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#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */
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#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos)
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#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos))
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#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Input Event Invert */
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#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos)
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#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) Event Input Enable */
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#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos)
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#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) Event Output Enable */
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#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos)
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#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */
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#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos)
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#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos))
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#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */
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/** \brief CCL hardware registers */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef struct {
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__IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
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RoReg8 Reserved1[0x3];
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__IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */
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RoReg8 Reserved2[0x2];
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__IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */
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} Ccl;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/*@}*/
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#endif /* _SAMR35_CCL_COMPONENT_ */

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