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Raffael Rostagno
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soc: clock: esp32h: Add RNG clock control
Add RNG peripheral clock control. Signed-off-by: Raffael Rostagno <[email protected]>
1 parent 48c17ae commit 0e604d1

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2 files changed

+56
-26
lines changed

2 files changed

+56
-26
lines changed

‎components/esp_rom/esp32h2/ld/esp32h2.rom.newlib.ld

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ memrchr = 0x40000518;
5353
strcasecmp = 0x4000051c;
5454
strcasestr = 0x40000520;
5555
strcat = 0x40000524;
56-
strdup = 0x40000528;
56+
PROVIDE ( strdup = 0x40000528 );
5757
strchr = 0x4000052c;
5858
strcspn = 0x40000530;
5959
strcoll = 0x40000534;
@@ -62,7 +62,7 @@ strlcpy = 0x4000053c;
6262
strlwr = 0x40000540;
6363
strncasecmp = 0x40000544;
6464
strncat = 0x40000548;
65-
strndup = 0x4000054c;
65+
PROVIDE ( strndup = 0x4000054c );
6666
strnlen = 0x40000550;
6767
strrchr = 0x40000554;
6868
strsep = 0x40000558;
@@ -76,22 +76,22 @@ div = 0x40000574;
7676
labs = 0x40000578;
7777
ldiv = 0x4000057c;
7878
qsort = 0x40000580;
79-
rand_r = 0x40000584;
80-
rand = 0x40000588;
81-
srand = 0x4000058c;
79+
PROVIDE ( rand_r = 0x40000584 );
80+
PROVIDE ( rand = 0x40000588 );
81+
PROVIDE ( srand = 0x4000058c );
8282
utoa = 0x40000590;
8383
itoa = 0x40000594;
84-
atoi = 0x40000598;
85-
atol = 0x4000059c;
86-
strtol = 0x400005a0;
87-
strtoul = 0x400005a4;
88-
fflush = 0x400005a8;
89-
_fflush_r = 0x400005ac;
90-
_fwalk = 0x400005b0;
91-
_fwalk_reent = 0x400005b4;
84+
PROVIDE ( atoi = 0x40000598 );
85+
PROVIDE ( atol = 0x4000059c );
86+
PROVIDE ( strtol = 0x400005a0 );
87+
PROVIDE ( strtoul = 0x400005a4 );
88+
PROVIDE ( fflush = 0x400005a8 );
89+
PROVIDE ( _fflush_r = 0x400005ac );
90+
PROVIDE ( _fwalk = 0x400005b0 );
91+
PROVIDE ( _fwalk_reent = 0x400005b4 );
9292
__smakebuf_r = 0x400005b8;
9393
__swhatbuf_r = 0x400005bc;
94-
__swbuf_r = 0x400005c0;
94+
PROVIDE ( __swbuf_r = 0x400005c0 );
9595
__swbuf = 0x400005c4;
9696
__swsetup_r = 0x400005c8;
9797
/* Data (.data, .bss, .rodata) */

‎components/hal/esp32h2/include/hal/clk_gate_ll.h

Lines changed: 42 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -11,6 +11,7 @@
1111
#include "soc/periph_defs.h"
1212
#include "soc/pcr_reg.h"
1313
#include "soc/soc.h"
14+
#include "soc/lpperi_reg.h"
1415

1516
#ifdef __cplusplus
1617
extern "C" {
@@ -77,8 +78,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
7778
return PCR_TSENS_CLK_EN;
7879
case PERIPH_REGDMA_MODULE:
7980
return PCR_REGDMA_CLK_EN;
80-
// case PERIPH_RNG_MODULE:
81-
// return PCR_WIFI_CLK_RNG_EN;
8281
// case PERIPH_WIFI_MODULE:
8382
// return PCR_WIFI_CLK_WIFI_EN_M;
8483
// case PERIPH_BT_MODULE:
@@ -89,6 +88,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
8988
// return PCR_BT_BASEBAND_EN;
9089
// case PERIPH_BT_LC_MODULE:
9190
// return PCR_BT_LC_EN;
91+
case PERIPH_RNG_MODULE:
92+
return LPPERI_RNG_CK_EN;
9293
default:
9394
return 0;
9495
}
@@ -197,7 +198,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
197198
static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
198199
{// ESP32H2-TODO: IDF-6400
199200
switch (periph) {
200-
// case PERIPH_RNG_MODULE:
201201
// case PERIPH_WIFI_MODULE:
202202
// case PERIPH_BT_MODULE:
203203
// case PERIPH_WIFI_BT_COMMON_MODULE:
@@ -263,6 +263,8 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
263263
return PCR_TSENS_CLK_CONF_REG;
264264
case PERIPH_REGDMA_MODULE:
265265
return PCR_REGDMA_CONF_REG;
266+
case PERIPH_RNG_MODULE:
267+
return LPPERI_CLK_EN_REG;
266268
default:
267269
return 0;
268270
}
@@ -337,14 +339,30 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
337339

338340
static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph)
339341
{
340-
SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
341-
CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true));
342+
uint32_t clk_en_reg = periph_ll_get_clk_en_reg(periph);
343+
uint32_t rst_en_reg = periph_ll_get_rst_en_reg(periph);
344+
345+
if (clk_en_reg != 0) {
346+
SET_PERI_REG_MASK(clk_en_reg, periph_ll_get_clk_en_mask(periph));
347+
}
348+
349+
if (rst_en_reg != 0) {
350+
CLEAR_PERI_REG_MASK(rst_en_reg, periph_ll_get_rst_en_mask(periph, true));
351+
}
342352
}
343353

344354
static inline void periph_ll_disable_clk_set_rst(periph_module_t periph)
345355
{
346-
CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
347-
SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
356+
uint32_t clk_en_reg = periph_ll_get_clk_en_reg(periph);
357+
uint32_t rst_en_reg = periph_ll_get_rst_en_reg(periph);
358+
359+
if (clk_en_reg != 0) {
360+
CLEAR_PERI_REG_MASK(clk_en_reg, periph_ll_get_clk_en_mask(periph));
361+
}
362+
363+
if (rst_en_reg != 0) {
364+
SET_PERI_REG_MASK(rst_en_reg, periph_ll_get_rst_en_mask(periph, false));
365+
}
348366
}
349367

350368
static inline void periph_ll_wifi_bt_module_enable_clk(void)
@@ -359,14 +377,26 @@ static inline void periph_ll_wifi_bt_module_disable_clk(void)
359377

360378
static inline void periph_ll_reset(periph_module_t periph)
361379
{
362-
SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
363-
CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
380+
uint32_t rst_en_reg = periph_ll_get_rst_en_reg(periph);
381+
382+
if (rst_en_reg != 0) {
383+
SET_PERI_REG_MASK(rst_en_reg, periph_ll_get_rst_en_mask(periph, false));
384+
CLEAR_PERI_REG_MASK(rst_en_reg, periph_ll_get_rst_en_mask(periph, false));
385+
}
364386
}
365387

366388
static inline bool periph_ll_periph_enabled(periph_module_t periph)
367389
{
368-
return REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
369-
REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
390+
uint32_t clk_en_reg = periph_ll_get_clk_en_reg(periph);
391+
uint32_t rst_en_reg = periph_ll_get_rst_en_reg(periph);
392+
393+
bool clk_enabled = (clk_en_reg != 0) &&
394+
(REG_GET_BIT(clk_en_reg, periph_ll_get_clk_en_mask(periph)) != 0);
395+
396+
bool rst_disabled = (rst_en_reg == 0) ||
397+
(REG_GET_BIT(rst_en_reg, periph_ll_get_rst_en_mask(periph, false)) == 0);
398+
399+
return clk_enabled && rst_disabled;
370400
}
371401

372402
static inline void periph_ll_wifi_module_enable_clk_clear_rst(void)

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