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sylvioalvessylvioalves
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cmake/soc: update source list
Remove BOOTLOADER_BUILD from all SoCS as it is not necessary anymore after having implementing proper flash initialization code. Move some especific MCUBoot sources to common area to allow code sharing. Add esp32s2 random source code. Signed-off-by: Sylvio Alves <[email protected]>
1 parent 114d2f4 commit 5527588

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17 files changed

+128
-119
lines changed

17 files changed

+128
-119
lines changed

‎zephyr/common/soc_init.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include "hal/efuse_hal.h"
1616
#include "soc/chip_revision.h"
1717
#include <hal/wdt_hal.h>
18+
#include "soc_init.h"
1819

1920
#define IS_MAX_REV_SET(max_chip_rev_full) \
2021
(((max_chip_rev_full) != 65535) && ((max_chip_rev_full) != 0))
@@ -45,11 +46,12 @@ void print_banner(void)
4546
int read_bootloader_header(void)
4647
{
4748
/* load bootloader image header */
48-
if (bootloader_flash_read(FIXED_PARTITION_OFFSET(boot_partition), &bootloader_image_hdr,
49-
sizeof(esp_image_header_t), true) != 0) {
49+
if (bootloader_flash_read_rom(FIXED_PARTITION_OFFSET(boot_partition), &bootloader_image_hdr,
50+
sizeof(esp_image_header_t), true) != 0) {
5051
ESP_EARLY_LOGE(TAG, "failed to load bootloader image header!");
5152
return -EIO;
5253
}
54+
5355
return 0;
5456
}
5557

‎zephyr/esp32/CMakeLists.txt

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,6 @@ if(CONFIG_SOC_SERIES_ESP32)
55
zephyr_compile_options(-fstrict-volatile-bitfields)
66
zephyr_compile_definitions_ifndef(CONFIG_MCUBOOT CONFIG_APP_BUILD_USE_FLASH_SECTIONS)
77

8-
zephyr_compile_definitions_ifdef(CONFIG_MCUBOOT BOOTLOADER_BUILD)
9-
zephyr_compile_definitions_ifdef(CONFIG_ESP_SIMPLE_BOOT BOOTLOADER_BUILD)
10-
118
zephyr_compile_definitions(CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5)
129

1310
if(CONFIG_MCUBOOT)
@@ -272,10 +269,7 @@ if(CONFIG_SOC_SERIES_ESP32)
272269
../../components/hal/mpu_hal.c
273270
../../components/bootloader_support/bootloader_flash/src/flash_qio_mode.c
274271
../common/console_init.c
275-
../common/flash_init.c
276272
../common/soc_init.c
277-
src/soc_init.c
278-
279273
)
280274

281275
zephyr_sources_ifdef(
@@ -289,10 +283,7 @@ if(CONFIG_SOC_SERIES_ESP32)
289283
../../components/soc/${CONFIG_SOC_SERIES}/rtc_io_periph.c
290284
../../components/soc/${CONFIG_SOC_SERIES}/dport_access.c
291285

292-
../../components/bootloader_support/bootloader_flash/src/bootloader_flash.c
293286
../../components/bootloader_support/src/bootloader_efuse.c
294-
../../components/bootloader_support/src/bootloader_random_${CONFIG_SOC_SERIES}.c
295-
../../components/bootloader_support/src/${CONFIG_SOC_SERIES}/bootloader_soc.c
296287

297288
../../components/esp_hw_support/cpu.c
298289
../../components/esp_hw_support/clk_ctrl_os.c
@@ -348,9 +339,13 @@ if(CONFIG_SOC_SERIES_ESP32)
348339

349340
../port/heap/heap_caps_zephyr.c
350341
../port/host_flash/cache_utils.c
342+
../port/bootloader/bootloader_flash.c
343+
344+
../common/flash_init.c
351345

352346
src/stubs.c
353347
src/soc_random.c
348+
src/soc_init.c
354349
src/soc_flash_init.c
355350
)
356351

‎zephyr/esp32/src/soc_init.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,3 +85,9 @@ void reset_mmu(void)
8585
*/
8686
DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
8787
}
88+
89+
/* Not supported but common bootloader calls the function. Do nothing */
90+
void ana_clock_glitch_reset_config(bool enable)
91+
{
92+
(void)enable;
93+
}

‎zephyr/esp32/src/soc_random.c

Lines changed: 1 addition & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -11,22 +11,15 @@
1111
#include "soc/i2s_periph.h"
1212
#include "esp_log.h"
1313
#include "soc/io_mux_reg.h"
14-
15-
#ifndef BOOTLOADER_BUILD
1614
#include "esp_private/periph_ctrl.h"
17-
#endif
1815

1916
void soc_random_enable(void)
2017
{
2118
/* Ensure the hardware RNG is enabled following a soft reset. This should always be the
2219
* case already (this clock is never disabled while the CPU is running), this is a "belts
2320
* and braces" type check.
2421
*/
25-
#ifdef BOOTLOADER_BUILD
26-
DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN);
27-
#else
2822
periph_module_enable(PERIPH_RNG_MODULE);
29-
#endif /* BOOTLOADER_BUILD */
3023

3124
/* Enable SAR ADC in test mode to feed ADC readings of the 1.1V
3225
* reference via I2S into the RNG entropy input.
@@ -37,11 +30,8 @@ void soc_random_enable(void)
3730
SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
3831
SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST);
3932

40-
#ifdef BOOTLOADER_BUILD
41-
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
42-
#else
4333
periph_module_enable(PERIPH_I2S0_MODULE);
44-
#endif /* BOOTLOADER_BUILD */
34+
4535
CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP);
4636
CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP);
4737

@@ -94,11 +84,7 @@ void soc_random_disable(void)
9484
CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE);
9585

9686
/* Disable i2s clock */
97-
#ifdef BOOTLOADER_BUILD
98-
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
99-
#else
10087
periph_module_disable(PERIPH_I2S0_MODULE);
101-
#endif /* BOOTLOADER_BUILD */
10288

10389
/* Restore SYSCON mode registers */
10490
CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
@@ -114,12 +100,7 @@ void soc_random_disable(void)
114100
SYSCON_SARADC_START_WAIT_S);
115101

116102
/* Reset i2s peripheral */
117-
#ifdef BOOTLOADER_BUILD
118-
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
119-
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
120-
#else
121103
periph_module_reset(PERIPH_I2S0_MODULE);
122-
#endif
123104

124105
/* Disable pull supply voltage to SAR ADC */
125106
CLEAR_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);

‎zephyr/esp32c2/CMakeLists.txt

Lines changed: 6 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,6 @@ if(CONFIG_SOC_SERIES_ESP32C2)
44

55
zephyr_compile_options(-fstrict-volatile-bitfields)
66
zephyr_compile_definitions_ifndef(CONFIG_MCUBOOT CONFIG_APP_BUILD_USE_FLASH_SECTIONS)
7-
zephyr_compile_definitions_ifdef(CONFIG_MCUBOOT BOOTLOADER_BUILD)
8-
9-
if(CONFIG_ESP_SIMPLE_BOOT)
10-
zephyr_compile_definitions_ifdef(CONFIG_ESPTOOLPY_FLASHMODE_QIO BOOTLOADER_BUILD)
11-
zephyr_compile_definitions_ifdef(CONFIG_ESPTOOLPY_FLASHMODE_QOUT BOOTLOADER_BUILD)
12-
endif()
137

148
zephyr_compile_definitions_ifndef(asm asm=__asm__)
159

@@ -202,21 +196,14 @@ if(CONFIG_SOC_SERIES_ESP32C2)
202196
../../components/hal/mpu_hal.c
203197
../../components/bootloader_support/bootloader_flash/src/flash_qio_mode.c
204198
../common/console_init.c
205-
../common/flash_init.c
206199
../common/soc_init.c
207-
src/soc_init.c
208-
src/soc_flash_init.c
209200
)
210201
endif()
211202

212203
zephyr_sources(
213204

214205
../../components/soc/${CONFIG_SOC_SERIES}/gpio_periph.c
215206

216-
../../components/bootloader_support/bootloader_flash/src/bootloader_flash.c
217-
../../components/bootloader_support/src/bootloader_random_${CONFIG_SOC_SERIES}.c
218-
../../components/bootloader_support/src/${CONFIG_SOC_SERIES}/bootloader_soc.c
219-
220207
../../components/esp_hw_support/cpu.c
221208
../../components/esp_hw_support/clk_ctrl_os.c
222209
../../components/esp_hw_support/esp_clk.c
@@ -275,8 +262,14 @@ if(CONFIG_SOC_SERIES_ESP32C2)
275262
../port/heap/heap_caps_zephyr.c
276263
../port/host_flash/cache_utils.c
277264
../../components/riscv/interrupt.c
265+
../port/bootloader/bootloader_flash.c
266+
267+
../common/flash_init.c
278268

279269
src/stubs.c
270+
src/soc_random.c
271+
src/soc_init.c
272+
src/soc_flash_init.c
280273
)
281274

282275
zephyr_link_libraries_ifdef(CONFIG_NEWLIB_LIBC c)

‎zephyr/esp32c2/src/soc_init.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -73,3 +73,9 @@ void check_wdt_reset(void)
7373

7474
wdt_reset_cpu0_info_enable();
7575
}
76+
77+
/* Not supported but common bootloader calls the function. Do nothing */
78+
void ana_clock_glitch_reset_config(bool enable)
79+
{
80+
(void)enable;
81+
}

‎zephyr/esp32c2/src/soc_random.c

Lines changed: 68 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,68 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#include "sdkconfig.h"
7+
#include "bootloader_random.h"
8+
#include "esp_log.h"
9+
#include "soc/syscon_reg.h"
10+
#include "soc/rtc_cntl_reg.h"
11+
#include "soc/apb_saradc_reg.h"
12+
#include "soc/system_reg.h"
13+
#include "esp_private/regi2c_ctrl.h"
14+
#include "soc/regi2c_saradc.h"
15+
16+
void soc_random_enable(void)
17+
{
18+
/* RNG module is always clock enabled */
19+
REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 0x3);
20+
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU_M);
21+
22+
// Bridging sar2 internal reference voltage
23+
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1);
24+
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
25+
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
26+
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
27+
28+
// Enable SAR ADC2 internal channel to read adc2 ref voltage for additional entropy
29+
SET_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_APB_SARADC_CLK_EN_M);
30+
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_APB_SARADC_RST_M);
31+
REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_REG_CLK_SEL, 0x2);
32+
SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN_M);
33+
SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_GATED_M);
34+
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_XPD_SAR_FORCE, 0x3);
35+
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 1);
36+
37+
REG_SET_FIELD(APB_SARADC_FSM_WAIT_REG, APB_SARADC_RSTB_WAIT, 8);
38+
REG_SET_FIELD(APB_SARADC_FSM_WAIT_REG, APB_SARADC_XPD_WAIT, 5);
39+
REG_SET_FIELD(APB_SARADC_FSM_WAIT_REG, APB_SARADC_STANDBY_WAIT, 100);
40+
41+
SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_P_CLEAR_M);
42+
CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_P_CLEAR_M);
43+
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_LEN, 0);
44+
REG_SET_FIELD(APB_SARADC_SAR_PATT_TAB1_REG, APB_SARADC_SAR_PATT_TAB1,
45+
0x9cffff); // Set adc2 internal channel & atten
46+
REG_SET_FIELD(APB_SARADC_SAR_PATT_TAB2_REG, APB_SARADC_SAR_PATT_TAB2, 0xffffff);
47+
// Set ADC sampling frequency
48+
REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_TARGET, 100);
49+
REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_REG_CLKM_DIV_NUM, 15);
50+
CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_MEAS_NUM_LIMIT);
51+
SET_PERI_REG_MASK(APB_SARADC_DMA_CONF_REG, APB_SARADC_APB_ADC_TRANS_M);
52+
SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN);
53+
}
54+
55+
void soc_random_disable(void)
56+
{
57+
/* Restore internal I2C bus state */
58+
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
59+
60+
/* Restore SARADC to default mode */
61+
CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN);
62+
CLEAR_PERI_REG_MASK(APB_SARADC_DMA_CONF_REG, APB_SARADC_APB_ADC_TRANS_M);
63+
REG_SET_FIELD(APB_SARADC_SAR_PATT_TAB1_REG, APB_SARADC_SAR_PATT_TAB1, 0xffffff);
64+
REG_SET_FIELD(APB_SARADC_SAR_PATT_TAB2_REG, APB_SARADC_SAR_PATT_TAB2, 0xffffff);
65+
CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN_M);
66+
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_XPD_SAR_FORCE, 0);
67+
REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 0);
68+
}

‎zephyr/esp32c3/CMakeLists.txt

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,6 @@ if(CONFIG_SOC_SERIES_ESP32C3)
44

55
zephyr_compile_options(-fstrict-volatile-bitfields)
66
zephyr_compile_definitions_ifndef(CONFIG_MCUBOOT CONFIG_APP_BUILD_USE_FLASH_SECTIONS)
7-
zephyr_compile_definitions_ifdef(CONFIG_MCUBOOT BOOTLOADER_BUILD)
8-
9-
if(CONFIG_ESP_SIMPLE_BOOT)
10-
zephyr_compile_definitions_ifdef(CONFIG_ESPTOOLPY_FLASHMODE_QIO BOOTLOADER_BUILD)
11-
zephyr_compile_definitions_ifdef(CONFIG_ESPTOOLPY_FLASHMODE_QOUT BOOTLOADER_BUILD)
12-
endif()
137

148
zephyr_compile_definitions_ifndef(asm asm=__asm__)
159

@@ -274,10 +268,8 @@ if(CONFIG_SOC_SERIES_ESP32C3)
274268
../../components/esp_rom/patches/esp_rom_sys.c
275269
../../components/hal/mpu_hal.c
276270
../common/console_init.c
277-
../common/flash_init.c
278271
../common/soc_init.c
279-
src/soc_flash_init.c
280-
)
272+
)
281273

282274
zephyr_sources_ifdef(
283275
CONFIG_MCUBOOT
@@ -288,8 +280,6 @@ if(CONFIG_SOC_SERIES_ESP32C3)
288280
zephyr_sources(
289281
../../components/soc/${CONFIG_SOC_SERIES}/gpio_periph.c
290282

291-
../../components/bootloader_support/bootloader_flash/src/bootloader_flash.c
292-
293283
../../components/esp_hw_support/cpu.c
294284
../../components/esp_hw_support/clk_ctrl_os.c
295285
../../components/esp_hw_support/esp_clk.c
@@ -352,10 +342,14 @@ if(CONFIG_SOC_SERIES_ESP32C3)
352342
../port/heap/heap_caps_zephyr.c
353343
../port/host_flash/cache_utils.c
354344
../../components/riscv/interrupt.c
345+
../port/bootloader/bootloader_flash.c
346+
347+
../common/flash_init.c
355348

356349
src/stubs.c
357-
src/soc_init.c
358350
src/soc_random.c
351+
src/soc_init.c
352+
src/soc_flash_init.c
359353
)
360354

361355
## shared WIFI/BT resources

‎zephyr/esp32c3/src/soc_random.c

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -13,12 +13,8 @@
1313
#include <esp_private/regi2c_ctrl.h>
1414
#include <soc/regi2c_saradc.h>
1515

16-
#define TAG "soc_random"
17-
1816
void soc_random_enable(void)
1917
{
20-
ESP_EARLY_LOGI(TAG, "Enabling RNG early entropy source");
21-
2218
/* RNG module is always clock enabled */
2319
REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 0x3);
2420
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU_M);
@@ -58,8 +54,6 @@ void soc_random_enable(void)
5854

5955
void soc_random_disable(void)
6056
{
61-
ESP_EARLY_LOGI(TAG, "Disabling RNG early entropy source");
62-
6357
/* Restore internal I2C bus state */
6458
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
6559

‎zephyr/esp32c6/CMakeLists.txt

Lines changed: 5 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -8,11 +8,6 @@ if(CONFIG_SOC_SERIES_ESP32C6)
88

99
zephyr_compile_definitions(CONFIG_IDF_TARGET_ARCH_RISCV)
1010

11-
if(CONFIG_ESP_SIMPLE_BOOT)
12-
zephyr_compile_definitions_ifdef(CONFIG_ESPTOOLPY_FLASHMODE_QIO BOOTLOADER_BUILD)
13-
zephyr_compile_definitions_ifdef(CONFIG_ESPTOOLPY_FLASHMODE_QOUT BOOTLOADER_BUILD)
14-
endif()
15-
1611
if(CONFIG_MCUBOOT)
1712
zephyr_compile_options(-fdump-rtl-expand)
1813
endif()
@@ -194,9 +189,6 @@ if(CONFIG_SOC_SERIES_ESP32C6)
194189
)
195190

196191
if (CONFIG_MCUBOOT)
197-
zephyr_compile_definitions(BOOTLOADER_BUILD)
198-
zephyr_compile_definitions(NDEBUG)
199-
200192
zephyr_sources(
201193
../port/boot/esp_image_loader.c
202194
)
@@ -212,10 +204,7 @@ if(CONFIG_SOC_SERIES_ESP32C6)
212204
../../components/hal/mpu_hal.c
213205
../../components/bootloader_support/bootloader_flash/src/flash_qio_mode.c
214206
../common/console_init.c
215-
../common/flash_init.c
216207
../common/soc_init.c
217-
src/soc_init.c
218-
src/soc_flash_init.c
219208
)
220209
endif()
221210

@@ -225,8 +214,6 @@ if(CONFIG_SOC_SERIES_ESP32C6)
225214
../../components/soc/${CONFIG_SOC_SERIES}/rtc_io_periph.c
226215
../../components/soc/${CONFIG_SOC_SERIES}/temperature_sensor_periph.c
227216

228-
../../components/bootloader_support/bootloader_flash/src/bootloader_flash.c
229-
230217
../../components/esp_hw_support/adc_share_hw_ctrl.c
231218
../../components/esp_hw_support/cpu.c
232219
../../components/esp_hw_support/clk_ctrl_os.c
@@ -288,9 +275,14 @@ if(CONFIG_SOC_SERIES_ESP32C6)
288275
../port/heap/heap_caps_zephyr.c
289276
../port/host_flash/cache_utils.c
290277
../../components/riscv/interrupt.c
278+
../port/bootloader/bootloader_flash.c
279+
280+
../common/flash_init.c
291281

292282
src/stubs.c
293283
src/soc_random.c
284+
src/soc_init.c
285+
src/soc_flash_init.c
294286
)
295287

296288
zephyr_sources_ifdef(

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