zephyr: Add LP UART support for C6

Add LP UART support for LP Core on C6

Signed-off-by: Lucas Tamborrino <[email protected]>

Author: LucasTambor

components/esp_hw_support/port/esp32c6/rtc_clk.c

@@ -364,7 +364,9 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
 {
     uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
     if (xtal_freq_mhz == 0) {
+#if !defined(CONFIG_SOC_ESP32C6_LPCORE)
         ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
+#endif
         clk_ll_xtal_store_freq_mhz(RTC_XTAL_FREQ_40M);
         return RTC_XTAL_FREQ_40M;
     }

components/hal/esp32c6/clk_tree_hal.c

@@ -10,7 +10,9 @@
 #include "hal/assert.h"
 #include "hal/log.h"
 
+#if !defined(CONFIG_SOC_ESP32C6_LPCORE)
 static const char *CLK_HAL_TAG = "clk_hal";
+#endif
 
 uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
 {
@@ -69,7 +71,9 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
 {
     uint32_t freq = clk_ll_xtal_load_freq_mhz();
     if (freq == 0) {
+#if !defined(CONFIG_SOC_ESP32C6_LPCORE)
         HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
+#endif
         return (uint32_t)RTC_XTAL_FREQ_40M;
     }
     return freq;

components/hal/esp32c6/include/hal/uart_ll.h

@@ -125,7 +125,7 @@ FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_c
  * @param  hw Address offset of the LP UART peripheral registers
  * @param  src_clk Source clock for the LP UART peripheral
  */
-static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_clk_src_t src_clk)
+FORCE_INLINE_ATTR void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_clk_src_t src_clk)
 {
     (void)hw;
     switch (src_clk) {
@@ -141,9 +141,6 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_
     }
 }
 
-/// LP_CLKRST.lpperi is a shared register, so this function must be used in an atomic way
-#define lp_uart_ll_set_source_clk(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_set_source_clk(__VA_ARGS__)
-
 /**
  * @brief  Configure the lp uart baud-rate.
  *
@@ -155,18 +152,28 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_
  */
 FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
 {
-#define DIV_UP(a, b)    (((a) + (b) - 1) / (b))
-    const uint32_t max_div = BIT(12) - 1;   // UART divider integer part only has 12 bits
-    uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
+    // Constants
+    const uint32_t MAX_DIV_BITS = 12;  // UART divider integer part bits
+    const uint32_t MAX_DIV = (1U << MAX_DIV_BITS) - 1;  // Maximum divider value
 
-    if (sclk_div == 0) abort();
+    // Ensure baud rate and sclk_freq are valid
+    if (baud == 0 || sclk_freq == 0) abort();
 
-    uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
-    // The baud rate configuration register is divided into
-    // an integer part and a fractional part.
-    hw->clkdiv_sync.clkdiv_int = clk_div >> 4;
-    hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
+    // Calculate sclk divider
+    uint32_t sclk_div = (sclk_freq + MAX_DIV * baud - 1) / (MAX_DIV * baud);
+    if (sclk_div == 0) abort();  // Handle invalid sclk_div
+
+    // Calculate clk_div with integer and fractional parts
+    uint32_t clk_div = (sclk_freq * 16) / (baud * sclk_div);
+    uint32_t clk_div_int = clk_div >> 4;  // Integer part
+    uint32_t clk_div_frac = clk_div & 0xF;  // Fractional part
+
+    // Configure hardware registers
+    hw->clkdiv_sync.clkdiv_int = clk_div_int;
+    hw->clkdiv_sync.clkdiv_frag = clk_div_frac;
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
+
+    // Update UART hardware
     uart_ll_update(hw);
 }
 
@@ -176,15 +183,12 @@ FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, ui
  * @param hw_id LP UART instance ID
  * @param enable True to enable, False to disable
  */
-static inline void _lp_uart_ll_enable_bus_clock(int hw_id, bool enable)
+FORCE_INLINE_ATTR void lp_uart_ll_enable_bus_clock(int hw_id, bool enable)
 {
     (void)hw_id;
     LPPERI.clk_en.lp_uart_ck_en = enable;
 }
 
-/// LPPERI.clk_en is a shared register, so this function must be used in an atomic way
-#define lp_uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _lp_uart_ll_enable_bus_clock(__VA_ARGS__)
-
 /**
  * @brief  Enable the UART clock.
  *

zephyr/esp32c6/CMakeLists.txt

@@ -353,7 +353,7 @@ if(CONFIG_SOC_SERIES_ESP32C6)
     ../../components/efuse/${CONFIG_SOC_SERIES}/esp_efuse_utility.c
     )
   endif()
-  
+
   if(CONFIG_SOC_ESP32C6_LPCORE)
     zephyr_compile_definitions(IS_ULP_COCPU)
     zephyr_ld_options("-nostartfiles")
@@ -367,7 +367,6 @@ if(CONFIG_SOC_SERIES_ESP32C6)
       ../../components/ulp/lp_core/lp_core.c
       ../../components/ulp/lp_core/shared/ulp_lp_core_lp_timer_shared.c
       ../../components/ulp/lp_core/shared/ulp_lp_core_memory_shared.c
-      ../../components/driver/gpio/rtc_io.c
       ../../components/hal/rtc_io_hal.c
       )