hal: esp32h2: Fix HAL files for initial support

Raffael Rostagno · Raffael Rostagno · commit 8f30421e09d9 · 2025-08-11T18:18:04.000-03:00
Fix HAL files for initial ESP32-H2 support.

Signed-off-by: Raffael Rostagno &lt;raffael.rostagno@espressif.com&gt;
diff --git a/components/driver/gpio/include/driver/rtc_io.h b/components/driver/gpio/include/driver/rtc_io.h
@@ -28,7 +28,7 @@ bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num);
 
 #define RTC_GPIO_IS_VALID_GPIO(gpio_num) rtc_gpio_is_valid_gpio(gpio_num)
 
-#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
+#if SOC_RTCIO_PIN_COUNT > 0
 /**
  * @brief Get RTC IO index number by gpio number.
  *
diff --git a/components/esp_hw_support/port/esp32h2/cpu_region_protect.c b/components/esp_hw_support/port/esp32h2/cpu_region_protect.c
@@ -127,9 +127,6 @@ void esp_cpu_configure_region_protection(void)
     _Static_assert(SOC_IROM_MASK_LOW < SOC_IROM_MASK_HIGH, "Invalid I/D-ROM region");
 
     if (esp_cpu_dbgr_is_attached()) {
-        // Anti-FI check that cpu is really in ocd mode
-        ESP_FAULT_ASSERT(esp_cpu_dbgr_is_attached());
-
         // 5. IRAM and DRAM
         PMP_ENTRY_SET(5, SOC_IRAM_LOW, NONE);
         PMP_ENTRY_SET(6, SOC_IRAM_HIGH, PMP_TOR | RWX);
diff --git a/components/esp_hw_support/port/esp32h2/esp_cpu_intr.c b/components/esp_hw_support/port/esp32h2/esp_cpu_intr.c
@@ -10,13 +10,14 @@
 void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
 {
     /* On the ESP32-H2, interrupt:
+     * - 0 is unavailable according to TRM
      * - 1 is for Wi-Fi
      * - 6 for "permanently disabled interrupt"
      *
      * Interrupts 3, 4 and 7 are unavailable for PULP CPU as they are bound to Core-Local Interrupts (CLINT)
      */
     // [TODO: IDF-2465]
-    const uint32_t rsvd_mask = BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(7);
+    const uint32_t rsvd_mask = BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(7);
 
     intr_desc_ret->priority = 1;
     intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk.c b/components/esp_hw_support/port/esp32h2/rtc_clk.c
@@ -159,8 +159,14 @@ soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void)
 
 static void rtc_clk_bbpll_disable(void)
 {
+#if defined(CLK_BBPLL_DISABLE)
+    /* Disabling BBPLL is commented due to issues when transitioning
+     * from PLL to XTAL clock sources. Comprehensive clock management
+     * must be implemented for peripherals as well (ZEP-827).
+     */
     clk_ll_bbpll_disable();
     s_cur_pll_freq = 0;
+#endif
 }
 
 static void rtc_clk_bbpll_enable(void)
diff --git a/components/esp_rom/esp32h2/ld/esp32h2.rom.newlib.ld b/components/esp_rom/esp32h2/ld/esp32h2.rom.newlib.ld
@@ -53,7 +53,7 @@ memrchr = 0x40000518;
 strcasecmp = 0x4000051c;
 strcasestr = 0x40000520;
 strcat = 0x40000524;
-strdup = 0x40000528;
+PROVIDE ( strdup = 0x40000528 );
 strchr = 0x4000052c;
 strcspn = 0x40000530;
 strcoll = 0x40000534;
@@ -62,7 +62,7 @@ strlcpy = 0x4000053c;
 strlwr = 0x40000540;
 strncasecmp = 0x40000544;
 strncat = 0x40000548;
-strndup = 0x4000054c;
+PROVIDE ( strndup = 0x4000054c );
 strnlen = 0x40000550;
 strrchr = 0x40000554;
 strsep = 0x40000558;
@@ -76,22 +76,22 @@ div = 0x40000574;
 labs = 0x40000578;
 ldiv = 0x4000057c;
 qsort = 0x40000580;
-rand_r = 0x40000584;
-rand = 0x40000588;
-srand = 0x4000058c;
+PROVIDE ( rand_r = 0x40000584 );
+PROVIDE ( rand = 0x40000588 );
+PROVIDE ( srand = 0x4000058c );
 utoa = 0x40000590;
 itoa = 0x40000594;
-atoi = 0x40000598;
-atol = 0x4000059c;
-strtol = 0x400005a0;
-strtoul = 0x400005a4;
-fflush = 0x400005a8;
-_fflush_r = 0x400005ac;
-_fwalk = 0x400005b0;
-_fwalk_reent = 0x400005b4;
+PROVIDE ( atoi = 0x40000598 );
+PROVIDE ( atol = 0x4000059c );
+PROVIDE ( strtol = 0x400005a0 );
+PROVIDE ( strtoul = 0x400005a4 );
+PROVIDE ( fflush = 0x400005a8 );
+PROVIDE ( _fflush_r = 0x400005ac );
+PROVIDE ( _fwalk = 0x400005b0 );
+PROVIDE ( _fwalk_reent = 0x400005b4 );
 __smakebuf_r = 0x400005b8;
 __swhatbuf_r = 0x400005bc;
-__swbuf_r = 0x400005c0;
+PROVIDE ( __swbuf_r = 0x400005c0 );
 __swbuf = 0x400005c4;
 __swsetup_r = 0x400005c8;
 /* Data (.data, .bss, .rodata) */
diff --git a/components/esp_rom/include/esp32h2/rom/rtc.h b/components/esp_rom/include/esp32h2/rom/rtc.h
@@ -8,6 +8,7 @@
 
 #include <stdbool.h>
 #include <stdint.h>
+#include <stddef.h>
 
 #include "soc/soc.h"
 #include "soc/lp_aon_reg.h"
diff --git a/components/esp_rom/include/esp32h2/rom/uart.h b/components/esp_rom/include/esp32h2/rom/uart.h
@@ -114,7 +114,7 @@ typedef enum {
 } UartFlowCtrl;
 
 typedef enum {
-    EMPTY,
+    EMPTY_,
     UNDER_WRITE,
     WRITE_OVER
 } RcvMsgBuffState;
diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c
@@ -6,7 +6,6 @@
 
 #include <stdint.h>
 #include <sys/cdefs.h>
-#include <sys/time.h>
 #include <sys/param.h>
 #include "sdkconfig.h"
 #include "esp_attr.h"
@@ -35,8 +34,6 @@
  */
 #define SLOW_CLK_CAL_CYCLES     CONFIG_RTC_CLK_CAL_CYCLES
 
-#define MHZ (1000000)
-
 static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src);
 static __attribute__((unused)) void recalib_bbpll(void);
 
diff --git a/components/esp_system/port/soc/esp32h2/reset_reason.c b/components/esp_system/port/soc/esp32h2/reset_reason.c
@@ -68,7 +68,7 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
     }
 }
 
-static void esp_reset_reason_init(void)
+void esp_reset_reason_init(void)
 {
     esp_reset_reason_t hint = esp_reset_reason_get_hint();
     s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
diff --git a/components/hal/esp32h2/include/hal/clk_tree_ll.h b/components/hal/esp32h2/include/hal/clk_tree_ll.h
@@ -25,7 +25,10 @@
 extern "C" {
 #endif
 
+#if !defined(DT_DRV_COMPAT)
+#undef MHZ
 #define MHZ                 (1000000)
+#endif
 
 #define CLK_LL_PLL_8M_FREQ_MHZ    (8)
 #define CLK_LL_PLL_48M_FREQ_MHZ   (48)
diff --git a/components/hal/esp32h2/include/hal/uart_ll.h b/components/hal/esp32h2/include/hal/uart_ll.h
@@ -752,6 +752,18 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
     uart_ll_update(hw);
 }
 
+/**
+ * @brief  Get the rs485_half_duplex mode.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ *
+ * @return True if RS485 half duplex mode enabled.
+ */
+FORCE_INLINE_ATTR bool uart_ll_is_mode_rs485_half_duplex(uart_dev_t *hw)
+{
+    return (!hw->rs485_conf_sync.rs485rxby_tx_en && hw->rs485_conf_sync.rs485_en);
+}
+
 /**
  * @brief  Configure the UART work in collision_detect mode.
  *
diff --git a/components/soc/esp32h2/include/soc/ext_mem_defs.h b/components/soc/esp32h2/include/soc/ext_mem_defs.h
@@ -152,8 +152,9 @@ extern "C" {
 /**
  * I/D share the MMU linear address range
  */
+#ifndef __ASSEMBLER__
 _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
-
+#endif
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32h2/include/soc/pmu_struct.h b/components/soc/esp32h2/include/soc/pmu_struct.h
@@ -6,6 +6,7 @@
 #pragma once
 
 #include <stdint.h>
+#include <stddef.h>
 #include "soc/pmu_reg.h"
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/soc/esp32h2/include/soc/rtc.h b/components/soc/esp32h2/include/soc/rtc.h
@@ -8,6 +8,7 @@
 #include <stdbool.h>
 #include <stddef.h>
 #include <stdint.h>
+#include "stubs.h"
 #include "soc/soc.h"
 #include "soc/clk_tree_defs.h"
 
@@ -43,8 +44,6 @@ extern "C" {
  * - rtc_sleep: entry into sleep modes
  */
 
-#define MHZ (1000000)
-
 #define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles)  (cycles << 10)
 #define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles)   (cycles << 12)
 #define RTC_FAST_CLK_8M_CAL_TIMEOUT_THRES(cycles)    (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value
diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,6 +11,7 @@
 #include "esp_assert.h"
 #endif
 
+#include "soc/ext_mem_defs.h"
 #include "esp_bit_defs.h"
 #include "reg_base.h"
 
@@ -164,7 +165,7 @@
 #define SOC_IRAM_HIGH   0x40850000
 #define SOC_DRAM_LOW    0x40800000
 #define SOC_DRAM_HIGH   0x40850000
-#define SOC_RTC_IRAM_LOW  0x50000000 // ESP32-H2 only has 16k LP memory
+#define SOC_RTC_IRAM_LOW  0x50000000 // ESP32-H2 only has 4k LP memory
 #define SOC_RTC_IRAM_HIGH 0x50001000
 #define SOC_RTC_DRAM_LOW  0x50000000
 #define SOC_RTC_DRAM_HIGH 0x50001000
diff --git a/zephyr/port/boot/esp_image_loader.c b/zephyr/port/boot/esp_image_loader.c
@@ -17,7 +17,8 @@
 
 #if !defined(CONFIG_SOC_SERIES_ESP32C2) &&	\
 	!defined(CONFIG_SOC_SERIES_ESP32C3) &&	\
-	!defined(CONFIG_SOC_SERIES_ESP32C6)
+	!defined(CONFIG_SOC_SERIES_ESP32C6) &&	\
+	!defined(CONFIG_SOC_SERIES_ESP32H2)
 #include "soc/dport_reg.h"
 #endif
 
@@ -48,6 +49,9 @@
 #elif CONFIG_SOC_SERIES_ESP32C6
 #include "esp32c6/rom/uart.h"
 #define LP_RTC_PREFIX "LP"
+#elif CONFIG_SOC_SERIES_ESP32H2
+#include "esp32h2/rom/uart.h"
+#define LP_RTC_PREFIX "LP"
 #endif
 
 #include "esp_mcuboot_image.h"
diff --git a/zephyr/port/host_flash/cache_utils.c b/zephyr/port/host_flash/cache_utils.c
@@ -30,6 +30,10 @@
 #include "esp32c6/rom/cache.h"
 #include "soc/extmem_reg.h"
 #include "soc/ext_mem_defs.h"
+#elif CONFIG_SOC_SERIES_ESP32H2
+#include "esp32h2/rom/cache.h"
+#include "soc/extmem_reg.h"
+#include "soc/ext_mem_defs.h"
 #endif
 
 #include "esp_private/spi_flash_os.h"
@@ -74,12 +78,12 @@ void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void)
 {
 	s_intr_saved_state = irq_lock();
 #if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C3) &&                  \
-	!defined(CONFIG_SOC_SERIES_ESP32C6)
+	!defined(CONFIG_SOC_SERIES_ESP32C6) && !defined(CONFIG_SOC_SERIES_ESP32H2)
 	esp_intr_noniram_disable();
 #endif
 
 #if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C3) &&                  \
-	!defined(CONFIG_SOC_SERIES_ESP32C6)
+	!defined(CONFIG_SOC_SERIES_ESP32C6) && !defined(CONFIG_SOC_SERIES_ESP32H2)
 	int cpu_id = esp_cpu_get_core_id();
 #else
 	int cpu_id = PRO_CPU_NUM;
@@ -95,7 +99,7 @@ void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void)
 void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu(void)
 {
 #if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C3) &&                  \
-	!defined(CONFIG_SOC_SERIES_ESP32C6)
+	!defined(CONFIG_SOC_SERIES_ESP32C6) && !defined(CONFIG_SOC_SERIES_ESP32H2)
 	int cpu_id = esp_cpu_get_core_id();
 #else
 	int cpu_id = PRO_CPU_NUM;
@@ -108,7 +112,7 @@ void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu(void)
 #endif
 
 #if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C3) &&                  \
-	!defined(CONFIG_SOC_SERIES_ESP32C6)
+	!defined(CONFIG_SOC_SERIES_ESP32C6) && !defined(CONFIG_SOC_SERIES_ESP32H2)
 	esp_intr_noniram_enable();
 #endif
 	irq_unlock(s_intr_saved_state);
@@ -195,7 +199,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
 	bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true;
 	uint32_t drom0_in_icache = 1; // always 1 in esp32s2
 #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 ||         \
-	CONFIG_IDF_TARGET_ESP32C6
+	CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
 	drom0_in_icache = 0;
 #endif
 
diff --git a/zephyr/port/include/stubs.h b/zephyr/port/include/stubs.h
@@ -21,7 +21,8 @@
 #define DT_CPU_COMPAT espressif_xtensa_lx6
 #elif defined(CONFIG_SOC_SERIES_ESP32S2) || defined(CONFIG_SOC_SERIES_ESP32S3)
 #define DT_CPU_COMPAT espressif_xtensa_lx7
-#elif defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
+#elif defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3) || \
+	  defined(CONFIG_SOC_SERIES_ESP32C6) || defined(CONFIG_SOC_SERIES_ESP32H2)
 #define DT_CPU_COMPAT espressif_riscv
 #endif
 
@@ -40,6 +41,8 @@
 #define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ ESP_SOC_DEFAULT_CPU_FREQ_MHZ
 #elif defined(CONFIG_SOC_SERIES_ESP32C6)
 #define CONFIG_ESP32C6_DEFAULT_CPU_FREQ_MHZ ESP_SOC_DEFAULT_CPU_FREQ_MHZ
+#elif defined(CONFIG_SOC_SERIES_ESP32H2)
+#define CONFIG_ESP32H2_DEFAULT_CPU_FREQ_MHZ ESP_SOC_DEFAULT_CPU_FREQ_MHZ
 #endif
 
 #endif /* _STUBS_H_ */

Original file line number	Diff line number	Diff line change
`@@ -28,7 +28,7 @@ bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num);`
`28`	`28`
`29`	`29`	`#define RTC_GPIO_IS_VALID_GPIO(gpio_num) rtc_gpio_is_valid_gpio(gpio_num)`
`30`	`30`
`31`		`-#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED`
	`31`	`+#if SOC_RTCIO_PIN_COUNT > 0`
`32`	`32`	`/**`
`33`	`33`	`* @brief Get RTC IO index number by gpio number.`
`34`	`34`	`*`
Original file line number	Diff line number	Diff line change
`@@ -159,8 +159,14 @@ soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void)`
`159`	`159`
`160`	`160`	`static void rtc_clk_bbpll_disable(void)`
`161`	`161`	`{`
	`162`	`+#if defined(CLK_BBPLL_DISABLE)`
	`163`	`+ /* Disabling BBPLL is commented due to issues when transitioning`
	`164`	`+ * from PLL to XTAL clock sources. Comprehensive clock management`
	`165`	`+ * must be implemented for peripherals as well (ZEP-827).`
	`166`	`+ */`
`162`	`167`	`clk_ll_bbpll_disable();`
`163`	`168`	`s_cur_pll_freq = 0;`
	`169`	`+#endif`
`164`	`170`	`}`
`165`	`171`
`166`	`172`	`static void rtc_clk_bbpll_enable(void)`
Original file line number	Diff line number	Diff line change
`@@ -68,7 +68,7 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,`
`68`	`68`	`}`
`69`	`69`	`}`
`70`	`70`
`71`		`-static void esp_reset_reason_init(void)`
	`71`	`+void esp_reset_reason_init(void)`
`72`	`72`	`{`
`73`	`73`	`esp_reset_reason_t hint = esp_reset_reason_get_hint();`
`74`	`74`	`s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);`