diff --git a/components/driver/gpio/include/driver/rtc_io.h b/components/driver/gpio/include/driver/rtc_io.h
index 3b17696f01..eed7f7fcce 100644
--- a/components/driver/gpio/include/driver/rtc_io.h
+++ b/components/driver/gpio/include/driver/rtc_io.h
@@ -28,7 +28,7 @@ bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num);
 
 #define RTC_GPIO_IS_VALID_GPIO(gpio_num) rtc_gpio_is_valid_gpio(gpio_num)
 
-#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
+#if SOC_RTCIO_PIN_COUNT > 0
 /**
  * @brief Get RTC IO index number by gpio number.
  *
diff --git a/components/esp_hw_support/port/esp32h2/cpu_region_protect.c b/components/esp_hw_support/port/esp32h2/cpu_region_protect.c
index c8817ca176..379fe986cb 100644
--- a/components/esp_hw_support/port/esp32h2/cpu_region_protect.c
+++ b/components/esp_hw_support/port/esp32h2/cpu_region_protect.c
@@ -127,9 +127,6 @@ void esp_cpu_configure_region_protection(void)
     _Static_assert(SOC_IROM_MASK_LOW < SOC_IROM_MASK_HIGH, "Invalid I/D-ROM region");
 
     if (esp_cpu_dbgr_is_attached()) {
-        // Anti-FI check that cpu is really in ocd mode
-        ESP_FAULT_ASSERT(esp_cpu_dbgr_is_attached());
-
         // 5. IRAM and DRAM
         PMP_ENTRY_SET(5, SOC_IRAM_LOW, NONE);
         PMP_ENTRY_SET(6, SOC_IRAM_HIGH, PMP_TOR | RWX);
diff --git a/components/esp_hw_support/port/esp32h2/esp_cpu_intr.c b/components/esp_hw_support/port/esp32h2/esp_cpu_intr.c
index 9ce7dfa69c..7301df6a90 100644
--- a/components/esp_hw_support/port/esp32h2/esp_cpu_intr.c
+++ b/components/esp_hw_support/port/esp32h2/esp_cpu_intr.c
@@ -10,13 +10,14 @@
 void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
 {
     /* On the ESP32-H2, interrupt:
+     * - 0 is unavailable according to TRM
      * - 1 is for Wi-Fi
      * - 6 for "permanently disabled interrupt"
      *
      * Interrupts 3, 4 and 7 are unavailable for PULP CPU as they are bound to Core-Local Interrupts (CLINT)
      */
     // [TODO: IDF-2465]
-    const uint32_t rsvd_mask = BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(7);
+    const uint32_t rsvd_mask = BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(7);
 
     intr_desc_ret->priority = 1;
     intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk.c b/components/esp_hw_support/port/esp32h2/rtc_clk.c
index bee509acb2..d4fe605672 100644
--- a/components/esp_hw_support/port/esp32h2/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32h2/rtc_clk.c
@@ -159,8 +159,14 @@ soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void)
 
 static void rtc_clk_bbpll_disable(void)
 {
+#if defined(CLK_BBPLL_DISABLE)
+    /* Disabling BBPLL is commented due to issues when transitioning
+     * from PLL to XTAL clock sources. Comprehensive clock management
+     * must be implemented for peripherals as well (ZEP-827).
+     */
     clk_ll_bbpll_disable();
     s_cur_pll_freq = 0;
+#endif
 }
 
 static void rtc_clk_bbpll_enable(void)
diff --git a/components/esp_rom/esp32h2/ld/esp32h2.rom.newlib.ld b/components/esp_rom/esp32h2/ld/esp32h2.rom.newlib.ld
index 211299b3a5..4ee9d06aba 100644
--- a/components/esp_rom/esp32h2/ld/esp32h2.rom.newlib.ld
+++ b/components/esp_rom/esp32h2/ld/esp32h2.rom.newlib.ld
@@ -53,7 +53,7 @@ memrchr = 0x40000518;
 strcasecmp = 0x4000051c;
 strcasestr = 0x40000520;
 strcat = 0x40000524;
-strdup = 0x40000528;
+PROVIDE ( strdup = 0x40000528 );
 strchr = 0x4000052c;
 strcspn = 0x40000530;
 strcoll = 0x40000534;
@@ -62,7 +62,7 @@ strlcpy = 0x4000053c;
 strlwr = 0x40000540;
 strncasecmp = 0x40000544;
 strncat = 0x40000548;
-strndup = 0x4000054c;
+PROVIDE ( strndup = 0x4000054c );
 strnlen = 0x40000550;
 strrchr = 0x40000554;
 strsep = 0x40000558;
@@ -76,22 +76,22 @@ div = 0x40000574;
 labs = 0x40000578;
 ldiv = 0x4000057c;
 qsort = 0x40000580;
-rand_r = 0x40000584;
-rand = 0x40000588;
-srand = 0x4000058c;
+PROVIDE ( rand_r = 0x40000584 );
+PROVIDE ( rand = 0x40000588 );
+PROVIDE ( srand = 0x4000058c );
 utoa = 0x40000590;
 itoa = 0x40000594;
-atoi = 0x40000598;
-atol = 0x4000059c;
-strtol = 0x400005a0;
-strtoul = 0x400005a4;
-fflush = 0x400005a8;
-_fflush_r = 0x400005ac;
-_fwalk = 0x400005b0;
-_fwalk_reent = 0x400005b4;
+PROVIDE ( atoi = 0x40000598 );
+PROVIDE ( atol = 0x4000059c );
+PROVIDE ( strtol = 0x400005a0 );
+PROVIDE ( strtoul = 0x400005a4 );
+PROVIDE ( fflush = 0x400005a8 );
+PROVIDE ( _fflush_r = 0x400005ac );
+PROVIDE ( _fwalk = 0x400005b0 );
+PROVIDE ( _fwalk_reent = 0x400005b4 );
 __smakebuf_r = 0x400005b8;
 __swhatbuf_r = 0x400005bc;
-__swbuf_r = 0x400005c0;
+PROVIDE ( __swbuf_r = 0x400005c0 );
 __swbuf = 0x400005c4;
 __swsetup_r = 0x400005c8;
 /* Data (.data, .bss, .rodata) */
diff --git a/components/esp_rom/include/esp32h2/rom/rtc.h b/components/esp_rom/include/esp32h2/rom/rtc.h
index 3cb3320a93..a49ccc62c0 100644
--- a/components/esp_rom/include/esp32h2/rom/rtc.h
+++ b/components/esp_rom/include/esp32h2/rom/rtc.h
@@ -8,6 +8,7 @@
 
 #include <stdbool.h>
 #include <stdint.h>
+#include <stddef.h>
 
 #include "soc/soc.h"
 #include "soc/lp_aon_reg.h"
diff --git a/components/esp_rom/include/esp32h2/rom/uart.h b/components/esp_rom/include/esp32h2/rom/uart.h
index 9045c42f6f..c0bd8be497 100644
--- a/components/esp_rom/include/esp32h2/rom/uart.h
+++ b/components/esp_rom/include/esp32h2/rom/uart.h
@@ -114,7 +114,7 @@ typedef enum {
 } UartFlowCtrl;
 
 typedef enum {
-    EMPTY,
+    EMPTY_,
     UNDER_WRITE,
     WRITE_OVER
 } RcvMsgBuffState;
diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c
index 3a81d9c0d6..52b60dc78d 100644
--- a/components/esp_system/port/soc/esp32h2/clk.c
+++ b/components/esp_system/port/soc/esp32h2/clk.c
@@ -6,7 +6,6 @@
 
 #include <stdint.h>
 #include <sys/cdefs.h>
-#include <sys/time.h>
 #include <sys/param.h>
 #include "sdkconfig.h"
 #include "esp_attr.h"
@@ -35,8 +34,6 @@
  */
 #define SLOW_CLK_CAL_CYCLES     CONFIG_RTC_CLK_CAL_CYCLES
 
-#define MHZ (1000000)
-
 static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src);
 static __attribute__((unused)) void recalib_bbpll(void);
 
diff --git a/components/esp_system/port/soc/esp32h2/reset_reason.c b/components/esp_system/port/soc/esp32h2/reset_reason.c
index 36aa8d6ede..f3de897215 100644
--- a/components/esp_system/port/soc/esp32h2/reset_reason.c
+++ b/components/esp_system/port/soc/esp32h2/reset_reason.c
@@ -68,7 +68,7 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
     }
 }
 
-static void esp_reset_reason_init(void)
+void esp_reset_reason_init(void)
 {
     esp_reset_reason_t hint = esp_reset_reason_get_hint();
     s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
diff --git a/components/hal/esp32h2/include/hal/clk_gate_ll.h b/components/hal/esp32h2/include/hal/clk_gate_ll.h
index 64fb1475b7..6b81f09d8e 100644
--- a/components/hal/esp32h2/include/hal/clk_gate_ll.h
+++ b/components/hal/esp32h2/include/hal/clk_gate_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,6 +11,7 @@
 #include "soc/periph_defs.h"
 #include "soc/pcr_reg.h"
 #include "soc/soc.h"
+#include "soc/lpperi_reg.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -77,8 +78,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
             return PCR_TSENS_CLK_EN;
         case PERIPH_REGDMA_MODULE:
             return PCR_REGDMA_CLK_EN;
-        // case PERIPH_RNG_MODULE:
-        //     return PCR_WIFI_CLK_RNG_EN;
         // case PERIPH_WIFI_MODULE:
         //     return PCR_WIFI_CLK_WIFI_EN_M;
         // case PERIPH_BT_MODULE:
@@ -89,6 +88,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
         //     return PCR_BT_BASEBAND_EN;
         // case PERIPH_BT_LC_MODULE:
         //     return PCR_BT_LC_EN;
+        case PERIPH_RNG_MODULE:
+            return LPPERI_RNG_CK_EN;
         default:
             return 0;
     }
@@ -197,7 +198,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
 static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
 {// ESP32H2-TODO: IDF-6400
     switch (periph) {
-    // case PERIPH_RNG_MODULE:
     // case PERIPH_WIFI_MODULE:
     // case PERIPH_BT_MODULE:
     // case PERIPH_WIFI_BT_COMMON_MODULE:
@@ -263,6 +263,8 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
             return PCR_TSENS_CLK_CONF_REG;
         case PERIPH_REGDMA_MODULE:
             return PCR_REGDMA_CONF_REG;
+        case PERIPH_RNG_MODULE:
+            return LPPERI_CLK_EN_REG;
     default:
         return 0;
     }
@@ -337,14 +339,30 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
 
 static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph)
 {
-    SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
-    CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true));
+    uint32_t clk_en_reg = periph_ll_get_clk_en_reg(periph);
+    uint32_t rst_en_reg = periph_ll_get_rst_en_reg(periph);
+
+    if (clk_en_reg != 0) {
+        SET_PERI_REG_MASK(clk_en_reg, periph_ll_get_clk_en_mask(periph));
+    }
+
+    if (rst_en_reg != 0) {
+        CLEAR_PERI_REG_MASK(rst_en_reg, periph_ll_get_rst_en_mask(periph, true));
+    }
 }
 
 static inline void periph_ll_disable_clk_set_rst(periph_module_t periph)
 {
-    CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
-    SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
+    uint32_t clk_en_reg = periph_ll_get_clk_en_reg(periph);
+    uint32_t rst_en_reg = periph_ll_get_rst_en_reg(periph);
+
+    if (clk_en_reg != 0) {
+        CLEAR_PERI_REG_MASK(clk_en_reg, periph_ll_get_clk_en_mask(periph));
+    }
+
+    if (rst_en_reg != 0) {
+        SET_PERI_REG_MASK(rst_en_reg, periph_ll_get_rst_en_mask(periph, false));
+    }
 }
 
 static inline void periph_ll_wifi_bt_module_enable_clk(void)
@@ -359,14 +377,26 @@ static inline void periph_ll_wifi_bt_module_disable_clk(void)
 
 static inline void periph_ll_reset(periph_module_t periph)
 {
-    SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
-    CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
+    uint32_t rst_en_reg = periph_ll_get_rst_en_reg(periph);
+
+    if (rst_en_reg != 0) {
+        SET_PERI_REG_MASK(rst_en_reg, periph_ll_get_rst_en_mask(periph, false));
+        CLEAR_PERI_REG_MASK(rst_en_reg, periph_ll_get_rst_en_mask(periph, false));
+    }
 }
 
 static inline bool periph_ll_periph_enabled(periph_module_t periph)
 {
-    return REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
-           REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
+    uint32_t clk_en_reg = periph_ll_get_clk_en_reg(periph);
+    uint32_t rst_en_reg = periph_ll_get_rst_en_reg(periph);
+
+    bool clk_enabled = (clk_en_reg != 0) && 
+                       (REG_GET_BIT(clk_en_reg, periph_ll_get_clk_en_mask(periph)) != 0);
+
+    bool rst_disabled = (rst_en_reg == 0) || 
+                        (REG_GET_BIT(rst_en_reg, periph_ll_get_rst_en_mask(periph, false)) == 0);
+
+    return clk_enabled && rst_disabled;
 }
 
 static inline void periph_ll_wifi_module_enable_clk_clear_rst(void)
diff --git a/components/hal/esp32h2/include/hal/clk_tree_ll.h b/components/hal/esp32h2/include/hal/clk_tree_ll.h
index d1a34a7089..070182dd1b 100644
--- a/components/hal/esp32h2/include/hal/clk_tree_ll.h
+++ b/components/hal/esp32h2/include/hal/clk_tree_ll.h
@@ -25,7 +25,10 @@
 extern "C" {
 #endif
 
+#if !defined(DT_DRV_COMPAT)
+#undef MHZ
 #define MHZ                 (1000000)
+#endif
 
 #define CLK_LL_PLL_8M_FREQ_MHZ    (8)
 #define CLK_LL_PLL_48M_FREQ_MHZ   (48)
diff --git a/components/hal/esp32h2/include/hal/uart_ll.h b/components/hal/esp32h2/include/hal/uart_ll.h
index e101e0d3c7..b9c88440f5 100644
--- a/components/hal/esp32h2/include/hal/uart_ll.h
+++ b/components/hal/esp32h2/include/hal/uart_ll.h
@@ -752,6 +752,18 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
     uart_ll_update(hw);
 }
 
+/**
+ * @brief  Get the rs485_half_duplex mode.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ *
+ * @return True if RS485 half duplex mode enabled.
+ */
+FORCE_INLINE_ATTR bool uart_ll_is_mode_rs485_half_duplex(uart_dev_t *hw)
+{
+    return (!hw->rs485_conf_sync.rs485rxby_tx_en && hw->rs485_conf_sync.rs485_en);
+}
+
 /**
  * @brief  Configure the UART work in collision_detect mode.
  *
diff --git a/components/soc/esp32h2/include/soc/ext_mem_defs.h b/components/soc/esp32h2/include/soc/ext_mem_defs.h
index 6d5e3ce451..d384700ecc 100644
--- a/components/soc/esp32h2/include/soc/ext_mem_defs.h
+++ b/components/soc/esp32h2/include/soc/ext_mem_defs.h
@@ -152,8 +152,9 @@ extern "C" {
 /**
  * I/D share the MMU linear address range
  */
+#ifndef __ASSEMBLER__
 _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
-
+#endif
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32h2/include/soc/pmu_struct.h b/components/soc/esp32h2/include/soc/pmu_struct.h
index a38ff690ec..74753c6981 100644
--- a/components/soc/esp32h2/include/soc/pmu_struct.h
+++ b/components/soc/esp32h2/include/soc/pmu_struct.h
@@ -6,6 +6,7 @@
 #pragma once
 
 #include <stdint.h>
+#include <stddef.h>
 #include "soc/pmu_reg.h"
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/soc/esp32h2/include/soc/rtc.h b/components/soc/esp32h2/include/soc/rtc.h
index 3c6010db02..bc96c10c15 100644
--- a/components/soc/esp32h2/include/soc/rtc.h
+++ b/components/soc/esp32h2/include/soc/rtc.h
@@ -8,6 +8,7 @@
 #include <stdbool.h>
 #include <stddef.h>
 #include <stdint.h>
+#include "stubs.h"
 #include "soc/soc.h"
 #include "soc/clk_tree_defs.h"
 
@@ -43,8 +44,6 @@ extern "C" {
  * - rtc_sleep: entry into sleep modes
  */
 
-#define MHZ (1000000)
-
 #define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles)  (cycles << 10)
 #define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles)   (cycles << 12)
 #define RTC_FAST_CLK_8M_CAL_TIMEOUT_THRES(cycles)    (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value
diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h
index bfa1a9a3cc..8fe52ceff3 100644
--- a/components/soc/esp32h2/include/soc/soc.h
+++ b/components/soc/esp32h2/include/soc/soc.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,6 +11,7 @@
 #include "esp_assert.h"
 #endif
 
+#include "soc/ext_mem_defs.h"
 #include "esp_bit_defs.h"
 #include "reg_base.h"
 
@@ -164,7 +165,7 @@
 #define SOC_IRAM_HIGH   0x40850000
 #define SOC_DRAM_LOW    0x40800000
 #define SOC_DRAM_HIGH   0x40850000
-#define SOC_RTC_IRAM_LOW  0x50000000 // ESP32-H2 only has 16k LP memory
+#define SOC_RTC_IRAM_LOW  0x50000000 // ESP32-H2 only has 4k LP memory
 #define SOC_RTC_IRAM_HIGH 0x50001000
 #define SOC_RTC_DRAM_LOW  0x50000000
 #define SOC_RTC_DRAM_HIGH 0x50001000
diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt
index ec875c7431..41654d4f58 100644
--- a/zephyr/CMakeLists.txt
+++ b/zephyr/CMakeLists.txt
@@ -8,5 +8,6 @@ add_subdirectory_ifdef(CONFIG_SOC_SERIES_ESP32 esp32)
 add_subdirectory_ifdef(CONFIG_SOC_SERIES_ESP32C2 esp32c2)
 add_subdirectory_ifdef(CONFIG_SOC_SERIES_ESP32C3 esp32c3)
 add_subdirectory_ifdef(CONFIG_SOC_SERIES_ESP32C6 esp32c6)
+add_subdirectory_ifdef(CONFIG_SOC_SERIES_ESP32H2 esp32h2)
 add_subdirectory_ifdef(CONFIG_SOC_SERIES_ESP32S2 esp32s2)
 add_subdirectory_ifdef(CONFIG_SOC_SERIES_ESP32S3 esp32s3)
diff --git a/zephyr/Kconfig b/zephyr/Kconfig
index 458a15ab0a..f5dcd57a8b 100644
--- a/zephyr/Kconfig
+++ b/zephyr/Kconfig
@@ -31,6 +31,7 @@ config IDF_FIRMWARE_CHIP_ID
 	default 0x000C if SOC_SERIES_ESP32C2
 	default 0x0005 if SOC_SERIES_ESP32C3
 	default 0x000D if SOC_SERIES_ESP32C6
+	default 0x0010 if IDF_TARGET_ESP32H2
 
 config SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
 	bool
@@ -68,6 +69,10 @@ config IDF_TARGET_ESP32C6
 	bool
 	default y if SOC_SERIES_ESP32C6
 
+config IDF_TARGET_ESP32H2
+	bool
+	default y if SOC_SERIES_ESP32H2
+
 config ESP_TIMER_IMPL_TG0_LAC
 	bool
 	default y
diff --git a/zephyr/esp32h2/CMakeLists.txt b/zephyr/esp32h2/CMakeLists.txt
new file mode 100644
index 0000000000..d47158233f
--- /dev/null
+++ b/zephyr/esp32h2/CMakeLists.txt
@@ -0,0 +1,256 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_SERIES_ESP32H2)
+
+  zephyr_compile_options(-fstrict-volatile-bitfields)
+  zephyr_compile_definitions_ifndef(CONFIG_MCUBOOT CONFIG_APP_BUILD_USE_FLASH_SECTIONS)
+  zephyr_compile_definitions_ifndef(asm asm=__asm__)
+
+  zephyr_compile_definitions(CONFIG_IDF_TARGET_ARCH_RISCV)
+
+  if(CONFIG_MCUBOOT)
+    zephyr_compile_options(-fdump-rtl-expand)
+  endif()
+
+  zephyr_include_directories(
+    include
+    ../port/include
+    ../common/include
+
+    ../../components/efuse/include
+    ../../components/efuse/private_include
+    ../../components/efuse/${CONFIG_SOC_SERIES}/include
+    ../../components/efuse/${CONFIG_SOC_SERIES}/private_include
+
+    ../../components/esp_common/include
+
+    ../../components/esp_hw_support/dma
+    ../../components/esp_hw_support/include
+    ../../components/esp_hw_support/include/esp_private
+    ../../components/esp_hw_support/include/hal
+    ../../components/esp_hw_support/include/soc
+    ../../components/esp_hw_support/include/soc/${CONFIG_SOC_SERIES}
+    ../../components/esp_hw_support/port/${CONFIG_SOC_SERIES}
+    ../../components/esp_hw_support/port/${CONFIG_SOC_SERIES}/private_include
+    ../../components/esp_hw_support/port/include
+    ../../components/esp_rom/${CONFIG_SOC_SERIES}
+    ../../components/esp_rom/${CONFIG_SOC_SERIES}/ld
+    ../../components/esp_rom/include/
+    ../../components/esp_rom/include/${CONFIG_SOC_SERIES}
+
+    ../../components/esp_system/include
+    ../../components/esp_system/include/esp_private
+    ../../components/esp_system/port/include
+    ../../components/esp_system/port/include/private/esp_private
+    ../../components/esp_system/port/include/private
+
+    ../../components/hal/${CONFIG_SOC_SERIES}/include
+    ../../components/hal/include
+    ../../components/hal/platform_port/include
+
+    ../../components/log/include
+
+    ../../components/soc/${CONFIG_SOC_SERIES}/include
+    ../../components/soc/${CONFIG_SOC_SERIES}/ld
+    ../../components/soc/include
+
+    ../../components/riscv/${CONFIG_SOC_SERIES}/include
+    ../../components/riscv/include
+    ../../components/riscv/include/esp_private
+    ../../components/riscv/include/xtensa
+
+    ../../components/esp_timer/include
+    ../../components/esp_timer/private_include
+
+    ../../components/driver/include
+    ../../components/driver/deprecated
+    ../../components/driver/gpio/include
+    ../../components/driver/uart/include
+    ../../components/driver/spi/include
+
+    ../../components/spi_flash/include
+    ../../components/spi_flash/include/spi_flash
+
+    ../../components/esp_pm/include
+
+    ../../components/bootloader_support/include
+    ../../components/bootloader_support/private_include
+    ../../components/bootloader_support/bootloader_flash/include
+
+    ../../components/heap/include
+
+    ../../components/esp_mm/include
+
+    ../../components/esp_phy/include
+    ../../components/esp_phy/include/esp_private
+    ../../components/esp_phy/${CONFIG_SOC_SERIES}/include
+    ../../components/esp_event/include
+
+    ../port/include/boot
+  )
+
+  zephyr_link_libraries(
+    gcc
+    -T${CMAKE_CURRENT_SOURCE_DIR}/src/linker/${CONFIG_SOC_SERIES}.rom.alias.ld
+    -T${CMAKE_CURRENT_SOURCE_DIR}/../../components/esp_rom/${CONFIG_SOC_SERIES}/ld/${CONFIG_SOC_SERIES}.rom.ld
+    -T${CMAKE_CURRENT_SOURCE_DIR}/../../components/esp_rom/${CONFIG_SOC_SERIES}/ld/${CONFIG_SOC_SERIES}.rom.api.ld
+    -T${CMAKE_CURRENT_SOURCE_DIR}/../../components/esp_rom/${CONFIG_SOC_SERIES}/ld/${CONFIG_SOC_SERIES}.rom.newlib.ld
+    -T${CMAKE_CURRENT_SOURCE_DIR}/../../components/esp_rom/${CONFIG_SOC_SERIES}/ld/${CONFIG_SOC_SERIES}.rom.libgcc.ld
+    -T${CMAKE_CURRENT_SOURCE_DIR}/../../components/esp_rom/${CONFIG_SOC_SERIES}/ld/${CONFIG_SOC_SERIES}.rom.version.ld
+    -T${CMAKE_CURRENT_SOURCE_DIR}/../../components/esp_rom/${CONFIG_SOC_SERIES}/ld/${CONFIG_SOC_SERIES}.rom.wdt.ld
+    -T${CMAKE_CURRENT_SOURCE_DIR}/../../components/soc/${CONFIG_SOC_SERIES}/ld/${CONFIG_SOC_SERIES}.peripherals.ld
+    -T${CMAKE_CURRENT_SOURCE_DIR}/../../tools/flasher_stub/ld/rom_32h2.ld
+  )
+
+  zephyr_compile_definitions(ESP_PLATFORM)
+
+  zephyr_sources(
+    ../../components/efuse/src/esp_efuse_api.c
+    ../../components/efuse/src/esp_efuse_utility.c
+    ../../components/efuse/${CONFIG_SOC_SERIES}/esp_efuse_table.c
+    ../../components/efuse/${CONFIG_SOC_SERIES}/esp_efuse_utility.c
+    ../../components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c
+  )
+
+  if(CONFIG_SOC_FLASH_ESP32 OR NOT CONFIG_BOOTLOADER_MCUBOOT)
+    zephyr_sources(
+    ../../components/esp_mm/esp_mmu_map.c
+    ../../components/esp_mm/port/${CONFIG_SOC_SERIES}/ext_mem_layout.c
+    ../../components/bootloader_support/src/flash_encrypt.c
+    ../../components/esp_hw_support/esp_gpio_reserve.c
+    ../../components/hal/cache_hal.c
+    ../../components/hal/mmu_hal.c
+    ../../components/hal/spi_flash_encrypt_hal_iram.c
+    ../../components/hal/spi_flash_hal.c
+    ../../components/hal/spi_flash_hal_iram.c
+    ../../components/hal/spi_flash_hal_gpspi.c
+    ../../components/spi_flash/esp_flash_api.c
+    ../../components/spi_flash/esp_flash_spi_init.c
+    ../../components/spi_flash/flash_mmap.c
+    ../../components/spi_flash/flash_ops.c
+    ../../components/spi_flash/memspi_host_driver.c
+    ../../components/spi_flash/spi_flash_chip_boya.c
+    ../../components/spi_flash/spi_flash_chip_drivers.c
+    ../../components/spi_flash/spi_flash_chip_gd.c
+    ../../components/spi_flash/spi_flash_chip_generic.c
+    ../../components/spi_flash/spi_flash_chip_issi.c
+    ../../components/spi_flash/spi_flash_chip_mxic.c
+    ../../components/spi_flash/spi_flash_chip_mxic_opi.c
+    ../../components/spi_flash/spi_flash_chip_th.c
+    ../../components/spi_flash/spi_flash_chip_winbond.c
+    ../../components/spi_flash/spi_flash_os_func_noos.c
+    ../../components/spi_flash/spi_flash_os_func_app.c
+    )
+  endif()
+
+  if (CONFIG_MCUBOOT)
+    zephyr_sources(
+      ../port/boot/esp_image_loader.c
+      )
+  endif()
+
+  if (CONFIG_MCUBOOT OR NOT CONFIG_BOOTLOADER_MCUBOOT)
+    zephyr_include_directories(
+      ../../components/esp_rom/${CONFIG_SOC_SERIES}
+      )
+
+    zephyr_sources(
+      ../../components/bootloader_support/src/bootloader_clock_init.c
+      ../../components/hal/mpu_hal.c
+      ../../components/bootloader_support/bootloader_flash/src/flash_qio_mode.c
+      ../common/console_init.c
+      ../common/soc_init.c
+      )
+  endif()
+
+  zephyr_sources_ifdef(
+    CONFIG_SOC_ESP32H2
+
+    ../../components/soc/${CONFIG_SOC_SERIES}/gpio_periph.c
+    ../../components/soc/${CONFIG_SOC_SERIES}/rtc_io_periph.c
+    ../../components/soc/${CONFIG_SOC_SERIES}/temperature_sensor_periph.c
+
+    ../../components/esp_hw_support/adc_share_hw_ctrl.c
+    ../../components/esp_hw_support/cpu.c
+    ../../components/esp_hw_support/clk_ctrl_os.c
+    ../../components/esp_hw_support/hw_random.c
+    ../../components/esp_hw_support/esp_clk.c
+    ../../components/esp_hw_support/mac_addr.c
+    ../../components/esp_hw_support/modem_clock.c
+    ../../components/esp_hw_support/periph_ctrl.c
+    ../../components/esp_hw_support/regi2c_ctrl.c
+    ../../components/esp_hw_support/sar_periph_ctrl_common.c
+    ../../components/esp_hw_support/sleep_modes.c
+    ../../components/esp_hw_support/sleep_retention.c
+    ../../components/esp_hw_support/port/esp_clk_tree_common.c
+    ../../components/esp_hw_support/port/regdma_link.c
+    ../../components/esp_hw_support/port/${CONFIG_SOC_SERIES}/esp_cpu_intr.c
+    ../../components/esp_hw_support/port/${CONFIG_SOC_SERIES}/esp_clk_tree.c
+    ../../components/esp_hw_support/port/${CONFIG_SOC_SERIES}/rtc_clk.c
+    ../../components/esp_hw_support/port/${CONFIG_SOC_SERIES}/rtc_clk_init.c
+    ../../components/esp_hw_support/port/${CONFIG_SOC_SERIES}/rtc_time.c
+    ../../components/esp_hw_support/port/${CONFIG_SOC_SERIES}/sar_periph_ctrl.c
+    ../../components/esp_hw_support/port/${CONFIG_SOC_SERIES}/systimer.c
+    ../../components/esp_hw_support/port/${CONFIG_SOC_SERIES}/pmu_init.c
+    ../../components/esp_hw_support/port/${CONFIG_SOC_SERIES}/pmu_param.c
+    ../../components/esp_hw_support/port/${CONFIG_SOC_SERIES}/pmu_sleep.c
+    ../../components/esp_hw_support/port/${CONFIG_SOC_SERIES}/cpu_region_protect.c
+    ../../components/esp_rom/patches/esp_rom_crc.c
+    ../../components/esp_rom/patches/esp_rom_sys.c
+    ../../components/esp_rom/patches/esp_rom_uart.c
+    ../../components/esp_rom/patches/esp_rom_spiflash.c
+    ../../components/esp_rom/patches/esp_rom_efuse.c
+    ../../components/esp_rom/patches/esp_rom_gpio.c
+    ../../components/esp_rom/patches/esp_rom_systimer.c
+    ../../components/esp_rom/patches/esp_rom_wdt.c
+    ../../components/esp_rom/patches/esp_rom_regi2c_esp32h2.c
+
+    ../../components/esp_system/port/soc/${CONFIG_SOC_SERIES}/clk.c
+    ../../components/esp_system/port/soc/${CONFIG_SOC_SERIES}/system_internal.c
+    ../../components/esp_system/port/soc/${CONFIG_SOC_SERIES}/reset_reason.c
+    ../../components/esp_system/esp_err.c
+
+    ../../components/esp_timer/src/ets_timer_legacy.c
+    ../../components/esp_timer/src/esp_timer.c
+    ../../components/esp_timer/src/esp_timer_etm.c
+    ../../components/esp_timer/src/esp_timer_impl_common.c
+    ../../components/esp_timer/src/esp_timer_impl_systimer.c
+    ../../components/esp_timer/src/system_time.c
+
+    ../../components/hal/efuse_hal.c
+    ../../components/hal/systimer_hal.c
+    ../../components/hal/wdt_hal_iram.c
+    ../../components/hal/${CONFIG_SOC_SERIES}/clk_tree_hal.c
+    ../../components/hal/${CONFIG_SOC_SERIES}/efuse_hal.c
+    ../../components/hal/${CONFIG_SOC_SERIES}/modem_clock_hal.c
+    ../../components/hal/lp_timer_hal.c
+
+    ../../components/log/log_noos.c
+    ../../components/log/log.c
+
+    ../../components/riscv/interrupt.c
+    ../../components/riscv/instruction_decode.c
+
+    ../port/heap/heap_caps_zephyr.c
+    ../port/host_flash/cache_utils.c
+    ../port/bootloader/bootloader_flash.c
+
+    ../common/flash_init.c
+    ../common/esp_restart.c
+
+    src/stubs.c
+    src/soc_random.c
+    src/soc_init.c
+    src/soc_flash_init.c
+  )
+
+  zephyr_sources_ifdef(
+    CONFIG_UART_ESP32
+    ../../components/hal/uart_hal.c
+    ../../components/hal/uart_hal_iram.c
+    ../../components/soc/${CONFIG_SOC_SERIES}/uart_periph.c
+    )
+
+  zephyr_link_libraries_ifdef(CONFIG_NEWLIB_LIBC c)
+
+endif()
diff --git a/zephyr/esp32h2/include/sdkconfig.h b/zephyr/esp32h2/include/sdkconfig.h
new file mode 100644
index 0000000000..5f26e03c6f
--- /dev/null
+++ b/zephyr/esp32h2/include/sdkconfig.h
@@ -0,0 +1,5 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
diff --git a/zephyr/esp32h2/src/linker/esp32h2.rom.alias.ld b/zephyr/esp32h2/src/linker/esp32h2.rom.alias.ld
new file mode 100644
index 0000000000..58651c2fdc
--- /dev/null
+++ b/zephyr/esp32h2/src/linker/esp32h2.rom.alias.ld
@@ -0,0 +1,24 @@
+/* Aliases used on Zephyr environment */
+
+/* Consider using prefix in all names when adding it */
+/* into zephyr source files */
+
+PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char );
+PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char );
+PROVIDE ( esp_rom_uart_attach = uart_attach );
+PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle );
+PROVIDE ( esp_rom_intr_matrix_set = intr_matrix_set );
+PROVIDE ( esp_rom_ets_set_user_start = ets_set_user_start );
+PROVIDE ( esp_rom_ets_printf = ets_printf );
+PROVIDE ( esp_rom_ets_delay_us = ets_delay_us );
+PROVIDE ( esp_rom_cache_set_idrom_mmu_size = Cache_Set_IDROM_MMU_Size );
+PROVIDE ( esp_rom_Cache_Invalidate_Addr = Cache_Invalidate_Addr );
+PROVIDE ( esp_rom_Cache_Suspend_ICache = Cache_Suspend_ICache );
+PROVIDE ( esp_rom_Cache_Invalidate_ICache_All = Cache_Invalidate_ICache_All );
+PROVIDE ( esp_rom_Cache_Dbus_MMU_Set = Cache_Dbus_MMU_Set );
+PROVIDE ( esp_rom_Cache_Ibus_MMU_Set = Cache_Ibus_MMU_Set );
+PROVIDE ( esp_rom_Cache_Resume_ICache = Cache_Resume_ICache );
+PROVIDE ( esp_rom_gpio_matrix_in = gpio_matrix_in );
+PROVIDE ( esp_rom_gpio_matrix_out = gpio_matrix_out );
+PROVIDE ( esp_rom_usb_uart_rx_one_char = usb_uart_rx_one_char);
+PROVIDE ( esp_rom_usb_uart_tx_one_char = usb_uart_tx_one_char);
diff --git a/zephyr/esp32h2/src/soc_flash_init.c b/zephyr/esp32h2/src/soc_flash_init.c
new file mode 100644
index 0000000000..3c33728184
--- /dev/null
+++ b/zephyr/esp32h2/src/soc_flash_init.c
@@ -0,0 +1,228 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdbool.h>
+#include <assert.h>
+#include <string.h>
+#include "esp_err.h"
+#include "esp_log.h"
+#include "esp_rom_gpio.h"
+#include "esp_rom_efuse.h"
+#include "esp32h2/rom/gpio.h"
+#include "esp32h2/rom/spi_flash.h"
+#include "esp32h2/rom/efuse.h"
+#include "soc/gpio_periph.h"
+#include "soc/efuse_reg.h"
+#include "soc/spi_reg.h"
+#include "soc/spi_mem_reg.h"
+#include "soc/soc_caps.h"
+#include "flash_qio_mode.h"
+#include "bootloader_flash_config.h"
+#include "bootloader_common.h"
+#include "bootloader_flash_priv.h"
+#include "bootloader_init.h"
+#include "hal/mmu_hal.h"
+#include "hal/cache_hal.h"
+#include "hal/mmu_ll.h"
+#include "soc/pcr_reg.h"
+
+#define TAG "flash_init"
+
+extern esp_image_header_t bootloader_image_hdr;
+
+void flash_update_id(void)
+{
+	esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
+
+	chip->device_id = bootloader_read_flash_id();
+}
+
+void flash_cs_timing_config(void)
+{
+	SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
+	SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
+	SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0,
+			  SPI_MEM_CS_SETUP_TIME_S);
+}
+
+void flash_clock_config(const esp_image_header_t *pfhdr)
+{
+	uint32_t spi_clk_div = 0;
+
+	switch (pfhdr->spi_speed) {
+	case ESP_IMAGE_SPI_SPEED_DIV_1:
+		spi_clk_div = 1;
+		break;
+	case ESP_IMAGE_SPI_SPEED_DIV_2:
+		spi_clk_div = 2;
+		break;
+	case ESP_IMAGE_SPI_SPEED_DIV_3:
+		spi_clk_div = 3;
+		break;
+	case ESP_IMAGE_SPI_SPEED_DIV_4:
+		spi_clk_div = 4;
+		break;
+	default:
+		break;
+	}
+	esp_rom_spiflash_config_clk(spi_clk_div, 0);
+}
+
+void configure_spi_pins(int drv)
+{
+	uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+	uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
+	uint8_t d_gpio_num = SPI_D_GPIO_NUM;
+	uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+	uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
+	uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
+
+	esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
+	esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
+	esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
+	esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
+	esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
+	esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
+}
+
+static void flash_clock_init(void)
+{
+	/* At this moment, BBPLL should be enabled. It is safe to switch the
+	 * MSPI clock source to PLL_F64M (default clock source) to raise speed.
+	 */
+	REG_SET_FIELD(PCR_MSPI_CONF_REG, PCR_MSPI_CLK_SEL, 2);
+}
+
+static void update_flash_config(const esp_image_header_t *bootloader_hdr)
+{
+	volatile uint32_t size;
+
+	switch (bootloader_hdr->spi_size) {
+	case ESP_IMAGE_FLASH_SIZE_1MB:
+		size = 1;
+		break;
+	case ESP_IMAGE_FLASH_SIZE_2MB:
+		size = 2;
+		break;
+	case ESP_IMAGE_FLASH_SIZE_4MB:
+		size = 4;
+		break;
+	case ESP_IMAGE_FLASH_SIZE_8MB:
+		size = 8;
+		break;
+	case ESP_IMAGE_FLASH_SIZE_16MB:
+		size = 16;
+		break;
+	default:
+		size = 2;
+	}
+	cache_hal_disable(CACHE_TYPE_ALL);
+	/* Set flash chip size */
+	esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000,
+					  0x10000, 0x1000, 0x100, 0xffff);
+	cache_hal_enable(CACHE_TYPE_ALL);
+}
+
+static void print_flash_info(const esp_image_header_t *bootloader_hdr)
+{
+	ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
+	ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
+	ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
+	ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
+	ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
+
+	const char *str;
+
+	switch (bootloader_hdr->spi_speed) {
+	case ESP_IMAGE_SPI_SPEED_DIV_2:
+		str = "32MHz";
+		break;
+	case ESP_IMAGE_SPI_SPEED_DIV_3:
+		str = "21.3MHz";
+		break;
+	case ESP_IMAGE_SPI_SPEED_DIV_4:
+		str = "16MHz";
+		break;
+	case ESP_IMAGE_SPI_SPEED_DIV_1:
+		str = "64MHz";
+		break;
+	default:
+		str = "16MHz";
+		break;
+	}
+	ESP_EARLY_LOGI(TAG, "SPI Speed      : %s", str);
+
+	/* SPI mode could have been set to QIO during boot already,
+	 * so test the SPI registers not the flash header
+	 */
+	uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
+
+	if (spi_ctrl & SPI_MEM_FREAD_QIO) {
+		str = "QIO";
+	} else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
+		str = "QOUT";
+	} else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
+		str = "DIO";
+	} else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
+		str = "DOUT";
+	} else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
+		str = "FAST READ";
+	} else {
+		str = "SLOW READ";
+	}
+	ESP_EARLY_LOGI(TAG, "SPI Mode       : %s", str);
+
+	switch (bootloader_hdr->spi_size) {
+	case ESP_IMAGE_FLASH_SIZE_1MB:
+		str = "1MB";
+		break;
+	case ESP_IMAGE_FLASH_SIZE_2MB:
+		str = "2MB";
+		break;
+	case ESP_IMAGE_FLASH_SIZE_4MB:
+		str = "4MB";
+		break;
+	case ESP_IMAGE_FLASH_SIZE_8MB:
+		str = "8MB";
+		break;
+	case ESP_IMAGE_FLASH_SIZE_16MB:
+		str = "16MB";
+		break;
+	default:
+		str = "2MB";
+		break;
+	}
+	ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str);
+}
+
+static void init_flash_configure(void)
+{
+	flash_clock_init();
+	configure_spi_pins(1);
+	flash_cs_timing_config();
+}
+
+static void spi_flash_resume(void)
+{
+	bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
+	esp_rom_spiflash_wait_idle(&g_rom_flashchip);
+}
+
+esp_err_t init_spi_flash(void)
+{
+	init_flash_configure();
+	spi_flash_resume();
+	bootloader_flash_unlock();
+
+#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
+	bootloader_enable_qio_mode();
+#endif
+
+	print_flash_info(&bootloader_image_hdr);
+	update_flash_config(&bootloader_image_hdr);
+	/* ensure the flash is write-protected */
+	bootloader_enable_wp();
+	return ESP_OK;
+}
diff --git a/zephyr/esp32h2/src/soc_init.c b/zephyr/esp32h2/src/soc_init.c
new file mode 100644
index 0000000000..519600e42f
--- /dev/null
+++ b/zephyr/esp32h2/src/soc_init.c
@@ -0,0 +1,94 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdbool.h>
+#include <assert.h>
+#include "soc_init.h"
+#include <soc/soc.h>
+#include "soc/lp_analog_peri_reg.h"
+#include "hal/clk_tree_ll.h"
+#include "soc/system_reg.h"
+#include "soc/assist_debug_reg.h"
+#include "esp_private/regi2c_ctrl.h"
+#include "soc/regi2c_lp_bias.h"
+#include "soc/regi2c_bias.h"
+#include "modem/modem_lpcon_reg.h"
+#include "soc/pcr_reg.h"
+#include "soc/lp_wdt_reg.h"
+#include "esp_log.h"
+
+const static char *TAG = "soc_init";
+
+void soc_hw_init(void)
+{
+	/* Enable analog i2c master clock */
+	SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
+	/* Fix low temp issue, need to increase this internal voltage */
+	REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_0P8, 8);
+}
+
+void ana_super_wdt_reset_config(bool enable)
+{
+	/* H2 doesn't support bypass super WDT reset */
+	assert(enable);
+	REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
+}
+
+void ana_bod_reset_config(bool enable)
+{
+	REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
+
+	if (enable) {
+		REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG,
+				LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
+	} else {
+		REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG,
+				LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
+	}
+}
+
+void ana_reset_config(void)
+{
+	ana_super_wdt_reset_config(true);
+	ana_bod_reset_config(true);
+}
+
+void super_wdt_auto_feed(void)
+
+{
+	REG_WRITE(LP_WDT_SWD_WPROTECT_REG, LP_WDT_SWD_WKEY_VALUE);
+	REG_SET_BIT(LP_WDT_SWD_CONFIG_REG, LP_WDT_SWD_AUTO_FEED_EN);
+	REG_WRITE(LP_WDT_SWD_WPROTECT_REG, 0);
+}
+
+void wdt_reset_cpu0_info_enable(void)
+{
+	REG_SET_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_CLK_EN);
+	REG_CLR_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_RST_EN);
+	REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG,
+		  ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
+}
+
+void check_wdt_reset(void)
+{
+	int wdt_rst = 0;
+	soc_reset_reason_t rst_reas;
+
+	rst_reas = esp_rom_get_reset_reason(0);
+	if (rst_reas == RESET_REASON_CORE_RTC_WDT || rst_reas == RESET_REASON_CORE_MWDT0 ||
+		rst_reas == RESET_REASON_CORE_MWDT1 || rst_reas == RESET_REASON_CPU0_MWDT0 ||
+		rst_reas == RESET_REASON_CPU0_MWDT1 || rst_reas == RESET_REASON_CPU0_RTC_WDT) {
+		ESP_EARLY_LOGW(TAG, "PRO CPU has been reset by WDT.");
+		wdt_rst = 1;
+	}
+
+	wdt_reset_cpu0_info_enable();
+}
+
+/* Not supported but common bootloader calls the function. Do nothing */
+void ana_clock_glitch_reset_config(bool enable)
+{
+	(void)enable;
+}
diff --git a/zephyr/esp32h2/src/soc_random.c b/zephyr/esp32h2/src/soc_random.c
new file mode 100644
index 0000000000..9b0825653d
--- /dev/null
+++ b/zephyr/esp32h2/src/soc_random.c
@@ -0,0 +1,88 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc_random.h"
+#include <soc/soc.h>
+#include <soc/pcr_reg.h>
+#include <soc/apb_saradc_reg.h>
+#include <soc/pmu_reg.h>
+#include <hal/regi2c_ctrl.h>
+#include <soc/regi2c_saradc.h>
+#include <esp_log.h>
+
+static const uint32_t SAR2_CHANNEL = 9;
+static const uint32_t PATTERN_BIT_WIDTH = 6;
+static const uint32_t SAR1_ATTEN = 1;
+static const uint32_t SAR2_ATTEN = 1;
+
+void soc_random_enable(void)
+{
+	REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
+	REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
+
+	REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN);
+
+	REG_SET_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN);
+
+	// select XTAL clock (40 MHz) source for ADC_CTRL_CLK
+	REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0);
+
+	REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0);
+
+	// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
+	SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+
+	REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, 0);
+	REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 1);
+	REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 1);
+
+	REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_MSB, 0X08);
+	REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_LSB, 0X66);
+	REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_MSB, 0X08);
+	REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_LSB, 0X66);
+
+	// create patterns and set them in pattern table
+	uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN;
+	uint32_t pattern_two = SAR1_ATTEN; // we want channel 0 with max attenuation, channel doesn't really matter here
+	uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH;
+	REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, pattern_table);
+
+	// set pattern length to 2 (APB_SARADC_SAR_PATT_LEN counts from 0)
+	REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 0);
+
+	// Same as in C3
+	REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15);
+
+	// set timer expiry (timer is ADC_CTRL_CLK)
+	REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200);
+
+	// ENABLE_TIMER
+	REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
+}
+
+void soc_random_disable(void)
+{
+	// disable timer
+	REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
+
+	// Write reset value of this register
+	REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, 0xFFFFFF);
+
+	// Revert ADC I2C configuration and initial voltage source setting
+	REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_MSB, 0x60);
+	REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_LSB, 0x0);
+	REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_MSB, 0x60);
+	REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_LSB, 0x0);
+	REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, 0);
+	REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 0);
+	REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 0);
+
+	// disable ADC_CTRL_CLK (SAR ADC function clock)
+	REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
+
+	// Set PCR_SARADC_CONF_REG to initial state
+	REG_WRITE(PCR_SARADC_CONF_REG, 0x5);
+}
diff --git a/zephyr/esp32h2/src/stubs.c b/zephyr/esp32h2/src/stubs.c
new file mode 100644
index 0000000000..3134716c60
--- /dev/null
+++ b/zephyr/esp32h2/src/stubs.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "stubs.h"
diff --git a/zephyr/port/boot/esp_image_loader.c b/zephyr/port/boot/esp_image_loader.c
index 1bfb8c879b..5dc9c272d3 100644
--- a/zephyr/port/boot/esp_image_loader.c
+++ b/zephyr/port/boot/esp_image_loader.c
@@ -17,7 +17,8 @@
 
 #if !defined(CONFIG_SOC_SERIES_ESP32C2) &&	\
 	!defined(CONFIG_SOC_SERIES_ESP32C3) &&	\
-	!defined(CONFIG_SOC_SERIES_ESP32C6)
+	!defined(CONFIG_SOC_SERIES_ESP32C6) &&	\
+	!defined(CONFIG_SOC_SERIES_ESP32H2)
 #include "soc/dport_reg.h"
 #endif
 
@@ -48,6 +49,9 @@
 #elif CONFIG_SOC_SERIES_ESP32C6
 #include "esp32c6/rom/uart.h"
 #define LP_RTC_PREFIX "LP"
+#elif CONFIG_SOC_SERIES_ESP32H2
+#include "esp32h2/rom/uart.h"
+#define LP_RTC_PREFIX "LP"
 #endif
 
 #include "esp_mcuboot_image.h"
diff --git a/zephyr/port/host_flash/cache_utils.c b/zephyr/port/host_flash/cache_utils.c
index 91417a688d..74546d39b5 100644
--- a/zephyr/port/host_flash/cache_utils.c
+++ b/zephyr/port/host_flash/cache_utils.c
@@ -30,6 +30,10 @@
 #include "esp32c6/rom/cache.h"
 #include "soc/extmem_reg.h"
 #include "soc/ext_mem_defs.h"
+#elif CONFIG_SOC_SERIES_ESP32H2
+#include "esp32h2/rom/cache.h"
+#include "soc/extmem_reg.h"
+#include "soc/ext_mem_defs.h"
 #endif
 
 #include "esp_private/spi_flash_os.h"
@@ -74,12 +78,12 @@ void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void)
 {
 	s_intr_saved_state = irq_lock();
 #if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C3) &&                  \
-	!defined(CONFIG_SOC_SERIES_ESP32C6)
+	!defined(CONFIG_SOC_SERIES_ESP32C6) && !defined(CONFIG_SOC_SERIES_ESP32H2)
 	esp_intr_noniram_disable();
 #endif
 
 #if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C3) &&                  \
-	!defined(CONFIG_SOC_SERIES_ESP32C6)
+	!defined(CONFIG_SOC_SERIES_ESP32C6) && !defined(CONFIG_SOC_SERIES_ESP32H2)
 	int cpu_id = esp_cpu_get_core_id();
 #else
 	int cpu_id = PRO_CPU_NUM;
@@ -95,7 +99,7 @@ void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void)
 void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu(void)
 {
 #if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C3) &&                  \
-	!defined(CONFIG_SOC_SERIES_ESP32C6)
+	!defined(CONFIG_SOC_SERIES_ESP32C6) && !defined(CONFIG_SOC_SERIES_ESP32H2)
 	int cpu_id = esp_cpu_get_core_id();
 #else
 	int cpu_id = PRO_CPU_NUM;
@@ -108,7 +112,7 @@ void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu(void)
 #endif
 
 #if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C3) &&                  \
-	!defined(CONFIG_SOC_SERIES_ESP32C6)
+	!defined(CONFIG_SOC_SERIES_ESP32C6) && !defined(CONFIG_SOC_SERIES_ESP32H2)
 	esp_intr_noniram_enable();
 #endif
 	irq_unlock(s_intr_saved_state);
@@ -195,7 +199,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
 	bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true;
 	uint32_t drom0_in_icache = 1; // always 1 in esp32s2
 #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 ||         \
-	CONFIG_IDF_TARGET_ESP32C6
+	CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
 	drom0_in_icache = 0;
 #endif
 
diff --git a/zephyr/port/include/stubs.h b/zephyr/port/include/stubs.h
index 01961736c2..7bad7473be 100644
--- a/zephyr/port/include/stubs.h
+++ b/zephyr/port/include/stubs.h
@@ -21,7 +21,8 @@
 #define DT_CPU_COMPAT espressif_xtensa_lx6
 #elif defined(CONFIG_SOC_SERIES_ESP32S2) || defined(CONFIG_SOC_SERIES_ESP32S3)
 #define DT_CPU_COMPAT espressif_xtensa_lx7
-#elif defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
+#elif defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3) || \
+	  defined(CONFIG_SOC_SERIES_ESP32C6) || defined(CONFIG_SOC_SERIES_ESP32H2)
 #define DT_CPU_COMPAT espressif_riscv
 #endif
 
@@ -40,6 +41,8 @@
 #define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ ESP_SOC_DEFAULT_CPU_FREQ_MHZ
 #elif defined(CONFIG_SOC_SERIES_ESP32C6)
 #define CONFIG_ESP32C6_DEFAULT_CPU_FREQ_MHZ ESP_SOC_DEFAULT_CPU_FREQ_MHZ
+#elif defined(CONFIG_SOC_SERIES_ESP32H2)
+#define CONFIG_ESP32H2_DEFAULT_CPU_FREQ_MHZ ESP_SOC_DEFAULT_CPU_FREQ_MHZ
 #endif
 
 #endif /* _STUBS_H_ */
diff --git a/zephyr/port/pincfgs/esp32h2.yml b/zephyr/port/pincfgs/esp32h2.yml
new file mode 100644
index 0000000000..ddc87a3b9e
--- /dev/null
+++ b/zephyr/port/pincfgs/esp32h2.yml
@@ -0,0 +1,42 @@
+# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+uart0:
+  tx:
+    sigo: u0txd_out
+    gpio: [[0, 5], [8, 14], [22, 27]]
+  rx:
+    sigi: u0rxd_in
+    gpio: [[0, 5], [8, 14], [22, 27]]
+  rts:
+    sigo: u0rts_out
+    gpio: [[0, 5], [8, 14], [22, 27]]
+  cts:
+    sigi: u0cts_in
+    gpio: [[0, 5], [8, 14], [22, 27]]
+  dtr:
+    sigo: u0dtr_out
+    gpio: [[0, 5], [8, 14], [22, 27]]
+  dsr:
+    sigi: u0dsr_in
+    gpio: [[0, 5], [8, 14], [22, 27]]
+
+uart1:
+  tx:
+    sigo: u1txd_out
+    gpio: [[0, 5], [8, 14], [22, 27]]
+  rx:
+    sigi: u1rxd_in
+    gpio: [[0, 5], [8, 14], [22, 27]]
+  rts:
+    sigo: u1rts_out
+    gpio: [[0, 5], [8, 14], [22, 27]]
+  cts:
+    sigi: u1cts_in
+    gpio: [[0, 5], [8, 14], [22, 27]]
+  dtr:
+    sigo: u1dtr_out
+    gpio: [[0, 5], [8, 14], [22, 27]]
+  dsr:
+    sigi: u1dsr_in
+    gpio: [[0, 5], [8, 14], [22, 27]]