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gd32e10x: update HAL to v1.3.0
gd32e10x: update HAL to v1.3.0 Signed-off-by: YuLong Yao <[email protected]>
1 parent b0b6e0a commit 74ad25d

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lines changed

‎gd32e10x/cmsis/gd/gd32e10x/include/gd32e10x.h‎

Lines changed: 3 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,12 @@
44
55
\version 2017-12-26, V1.0.1, firmware for GD32E10x
66
\version 2020-09-30, V1.1.0, firmware for GD32E10x
7+
\version 2020-12-31, V1.2.0, firmware for GD32E10x
8+
\version 2022-06-30, V1.3.0, firmware for GD32E10x
79
*/
810

911
/*
10-
Copyright (c) 2020, GigaDevice Semiconductor Inc.
12+
Copyright (c) 2022, GigaDevice Semiconductor Inc.
1113
1214
Redistribution and use in source and binary forms, with or without modification,
1315
are permitted provided that the following conditions are met:
@@ -60,14 +62,6 @@ OF SUCH DAMAGE.
6062
#error "Please select the target board type used in your application (in gd32e10x.h file)"
6163
#endif
6264
#endif /* high speed crystal oscillator value */
63-
64-
#if HXTAL_VALUE == 8000000
65-
#define HXTAL_VALUE_8M HXTAL_VALUE
66-
#elif HXTAL_VALUE == 25000000
67-
#define HXTAL_VALUE_25M HXTAL_VALUE
68-
#else
69-
#error "GD32E10X lib only support 8M and 25M oscillator (HXTAL)"
70-
#endif
7165

7266
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
7367
#if !defined (HXTAL_STARTUP_TIMEOUT)
@@ -201,9 +195,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
201195
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
202196
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
203197
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
204-
#ifndef BIT
205198
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
206-
#endif
207199
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
208200
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
209201

‎gd32e10x/cmsis/gd/gd32e10x/source/system_gd32e10x.c‎

Lines changed: 25 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,17 @@ OF SUCH DAMAGE.
6161
#define SEL_IRC8M 0x00U
6262
#define SEL_HXTAL 0x01U
6363
#define SEL_PLL 0x02U
64+
#define RCU_MODIFY(__delay) do{ \
65+
volatile uint32_t i; \
66+
if(0 != __delay){ \
67+
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \
68+
for(i=0; i<__delay; i++){ \
69+
} \
70+
RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \
71+
for(i=0; i<__delay; i++){ \
72+
} \
73+
} \
74+
}while(0)
6475

6576
/* set the system clock frequency and declare the system clock configuration function */
6677
#ifdef __SYSTEM_CLOCK_IRC8M
@@ -114,29 +125,31 @@ void SystemInit (void)
114125
/* reset the RCU clock configuration to the default reset state */
115126
/* Set IRC8MEN bit */
116127
RCU_CTL |= RCU_CTL_IRC8MEN;
117-
118-
/* Reset CFG0 and CFG1 registers */
119-
RCU_CFG0 = 0x00000000U;
120-
RCU_CFG1 = 0x00000000U;
128+
while(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
129+
}
130+
RCU_MODIFY(0x50);
131+
RCU_CFG0 &= ~RCU_CFG0_SCS;
121132

122133
/* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */
123134
RCU_CTL &= ~(RCU_CTL_PLLEN |RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
124135
/* disable all interrupts */
125136
RCU_INT = 0x00ff0000U;
126137

138+
/* Reset CFG0 and CFG1 registers */
139+
RCU_CFG0 = 0x00000000U;
140+
RCU_CFG1 = 0x00000000U;
141+
127142
/* reset HXTALBPS bit */
128143
RCU_CTL &= ~(RCU_CTL_HXTALBPS);
129144

130145
/* configure the system clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */
131146
system_clock_config();
132-
133-
/*
134-
#ifdef VECT_TAB_SRAM
135-
nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET);
136-
#else
137-
nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET);
138-
#endif
139-
*/
147+
148+
#ifdef VECT_TAB_SRAM
149+
nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET);
150+
#else
151+
nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET);
152+
#endif
140153

141154
}
142155

‎gd32e10x/standard_peripheral/include/gd32e10x_adc.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,11 @@
55
\version 2017-12-26, V1.0.0, firmware for GD32E10x
66
\version 2020-09-30, V1.1.0, firmware for GD32E10x
77
\version 2020-12-31, V1.2.0, firmware for GD32E10x
8+
\version 2022-06-30, V1.3.0, firmware for GD32E10x
89
*/
910

1011
/*
11-
Copyright (c) 2020, GigaDevice Semiconductor Inc.
12+
Copyright (c) 2022, GigaDevice Semiconductor Inc.
1213
1314
Redistribution and use in source and binary forms, with or without modification,
1415
are permitted provided that the following conditions are met:

‎gd32e10x/standard_peripheral/include/gd32e10x_bkp.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,11 @@
55
\version 2017-12-26, V1.0.0, firmware for GD32E10x
66
\version 2020-09-30, V1.1.0, firmware for GD32E10x
77
\version 2020-12-31, V1.2.0, firmware for GD32E10x
8+
\version 2022-06-30, V1.3.0, firmware for GD32E10x
89
*/
910

1011
/*
11-
Copyright (c) 2020, GigaDevice Semiconductor Inc.
12+
Copyright (c) 2022, GigaDevice Semiconductor Inc.
1213
1314
Redistribution and use in source and binary forms, with or without modification,
1415
are permitted provided that the following conditions are met:
@@ -179,7 +180,7 @@ typedef enum
179180
#define RTC_CLOCK_DIV_1 ((uint16_t)BKP_OCTL_CCOSEL) /*!< RTC clock div 1 */
180181

181182
/* RTC clock calibration direction */
182-
#define RTC_CLOCK_SLOWED_DOWN ((uint16_t)0x0000U) /*!< RTC clock slow down */
183+
#define RTC_CLOCK_SLOW_DOWN ((uint16_t)0x0000U) /*!< RTC clock slow down */
183184
#define RTC_CLOCK_SPEED_UP ((uint16_t)BKP_OCTL_CALDIR) /*!< RTC clock speed up */
184185

185186
/* tamper pin active level */

‎gd32e10x/standard_peripheral/include/gd32e10x_crc.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,11 @@
55
\version 2017-12-26, V1.0.0, firmware for GD32E10x
66
\version 2020-09-30, V1.1.0, firmware for GD32E10x
77
\version 2020-12-31, V1.2.0, firmware for GD32E10x
8+
\version 2022-06-30, V1.3.0, firmware for GD32E10x
89
*/
910

1011
/*
11-
Copyright (c) 2020, GigaDevice Semiconductor Inc.
12+
Copyright (c) 2022, GigaDevice Semiconductor Inc.
1213
1314
Redistribution and use in source and binary forms, with or without modification,
1415
are permitted provided that the following conditions are met:

‎gd32e10x/standard_peripheral/include/gd32e10x_ctc.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,11 @@
55
\version 2017-12-26, V1.0.0, firmware for GD32E10x
66
\version 2020-09-30, V1.1.0, firmware for GD32E10x
77
\version 2020-12-31, V1.2.0, firmware for GD32E10x
8+
\version 2022-06-30, V1.3.0, firmware for GD32E10x
89
*/
910

1011
/*
11-
Copyright (c) 2020, GigaDevice Semiconductor Inc.
12+
Copyright (c) 2022, GigaDevice Semiconductor Inc.
1213
1314
Redistribution and use in source and binary forms, with or without modification,
1415
are permitted provided that the following conditions are met:
@@ -96,7 +97,6 @@ OF SUCH DAMAGE.
9697
#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
9798
#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */
9899
#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is selected */
99-
#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBFS_SOF is selected */
100100

101101
/* reference signal source prescaler definitions */
102102
#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))

‎gd32e10x/standard_peripheral/include/gd32e10x_dac.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,11 @@
55
\version 2017-12-26, V1.0.0, firmware for GD32E10x
66
\version 2020-09-30, V1.1.0, firmware for GD32E10x
77
\version 2020-12-31, V1.2.0, firmware for GD32E10x
8+
\version 2022-06-30, V1.3.0, firmware for GD32E10x
89
*/
910

1011
/*
11-
Copyright (c) 2020, GigaDevice Semiconductor Inc.
12+
Copyright (c) 2022, GigaDevice Semiconductor Inc.
1213
1314
Redistribution and use in source and binary forms, with or without modification,
1415
are permitted provided that the following conditions are met:

‎gd32e10x/standard_peripheral/include/gd32e10x_dbg.h‎

Lines changed: 2 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,11 @@
55
\version 2017-12-26, V1.0.0, firmware for GD32E10x
66
\version 2020-09-30, V1.1.0, firmware for GD32E10x
77
\version 2020-12-31, V1.2.0, firmware for GD32E10x
8+
\version 2022-06-30, V1.3.0, firmware for GD32E10x
89
*/
910

1011
/*
11-
Copyright (c) 2020, GigaDevice Semiconductor Inc.
12+
Copyright (c) 2022, GigaDevice Semiconductor Inc.
1213
1314
Redistribution and use in source and binary forms, with or without modification,
1415
are permitted provided that the following conditions are met:
@@ -55,7 +56,6 @@ OF SUCH DAMAGE.
5556
#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
5657
#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
5758
#define DBG_CTL_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */
58-
#define DBG_CTL_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */
5959
#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
6060
#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
6161
#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */
@@ -103,13 +103,6 @@ typedef enum
103103
DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */
104104
}dbg_periph_enum;
105105

106-
/* DBG_CTL0_TRACE_MODE configurations */
107-
#define CTL_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U))
108-
#define TRACE_MODE_ASYNC CTL_TRACE_MODE(0) /*!< trace pin used for async mode */
109-
#define TRACE_MODE_SYNC_DATASIZE_1 CTL_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */
110-
#define TRACE_MODE_SYNC_DATASIZE_2 CTL_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */
111-
#define TRACE_MODE_SYNC_DATASIZE_4 CTL_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */
112-
113106
/* function declarations */
114107
/* read DBG_ID code register */
115108
uint32_t dbg_id_get(void);
@@ -128,7 +121,5 @@ void dbg_periph_disable(dbg_periph_enum dbg_periph);
128121
void dbg_trace_pin_enable(void);
129122
/* disable trace pin assignment */
130123
void dbg_trace_pin_disable(void);
131-
/* set trace pin mode */
132-
void dbg_trace_pin_mode_set(uint32_t trace_mode);
133124

134125
#endif /* GD32E10X_DBG_H */

‎gd32e10x/standard_peripheral/include/gd32e10x_dma.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,11 @@
55
\version 2017-12-26, V1.0.0, firmware for GD32E10x
66
\version 2020-09-30, V1.1.0, firmware for GD32E10x
77
\version 2020-12-31, V1.2.0, firmware for GD32E10x
8+
\version 2022-06-30, V1.3.0, firmware for GD32E10x
89
*/
910

1011
/*
11-
Copyright (c) 2020, GigaDevice Semiconductor Inc.
12+
Copyright (c) 2022, GigaDevice Semiconductor Inc.
1213
1314
Redistribution and use in source and binary forms, with or without modification,
1415
are permitted provided that the following conditions are met:

‎gd32e10x/standard_peripheral/include/gd32e10x_exmc.h‎

Lines changed: 17 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,11 @@
55
\version 2017-12-26, V1.0.0, firmware for GD32E10x
66
\version 2020-09-30, V1.1.0, firmware for GD32E10x
77
\version 2020-12-31, V1.2.0, firmware for GD32E10x
8+
\version 2022-06-30, V1.3.0, firmware for GD32E10x
89
*/
910

1011
/*
11-
Copyright (c) 2020, GigaDevice Semiconductor Inc.
12+
Copyright (c) 2022, GigaDevice Semiconductor Inc.
1213
1314
Redistribution and use in source and binary forms, with or without modification,
1415
are permitted provided that the following conditions are met:
@@ -163,21 +164,21 @@ typedef struct
163164
/* synchronous clock divide ratio */
164165
#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
165166
#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */
166-
#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */
167-
#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */
168-
#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */
169-
#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */
170-
#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */
171-
#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */
172-
#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */
173-
#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */
174-
#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */
175-
#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */
176-
#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */
177-
#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */
178-
#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */
179-
#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */
180-
#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */
167+
#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< frequency EXMC_CLK = HCLK/2 */
168+
#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< frequency EXMC_CLK = HCLK/3 */
169+
#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< frequency EXMC_CLK = HCLK/4 */
170+
#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< frequency EXMC_CLK = HCLK/5 */
171+
#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< frequency EXMC_CLK = HCLK/6 */
172+
#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< frequency EXMC_CLK = HCLK/7 */
173+
#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< frequency EXMC_CLK = HCLK/8 */
174+
#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< frequency EXMC_CLK = HCLK/9 */
175+
#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< frequency EXMC_CLK = HCLK/10 */
176+
#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< frequency EXMC_CLK = HCLK/11 */
177+
#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< frequency EXMC_CLK = HCLK/12 */
178+
#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< frequency EXMC_CLK = HCLK/13 */
179+
#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< frequency EXMC_CLK = HCLK/14 */
180+
#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< frequency EXMC_CLK = HCLK/15 */
181+
#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< frequency EXMC_CLK = HCLK/16 */
181182

182183
/* EXMC NOR/SRAM write mode */
183184
#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */

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