diff --git a/gd32e10x/cmsis/gd/gd32e10x/include/gd32e10x.h b/gd32e10x/cmsis/gd/gd32e10x/include/gd32e10x.h index 58e86d25..7af80693 100644 --- a/gd32e10x/cmsis/gd/gd32e10x/include/gd32e10x.h +++ b/gd32e10x/cmsis/gd/gd32e10x/include/gd32e10x.h @@ -60,6 +60,14 @@ OF SUCH DAMAGE. #error "Please select the target board type used in your application (in gd32e10x.h file)" #endif #endif /* high speed crystal oscillator value */ + +#if HXTAL_VALUE == 8000000 + #define HXTAL_VALUE_8M HXTAL_VALUE +#elif HXTAL_VALUE == 25000000 + #define HXTAL_VALUE_25M HXTAL_VALUE +#else + #error "GD32E10X lib only support 8M and 25M oscillator (HXTAL)" +#endif /* define startup timeout value of high speed crystal oscillator (HXTAL) */ #if !defined (HXTAL_STARTUP_TIMEOUT) diff --git a/gd32e10x/cmsis/gd/gd32e10x/source/system_gd32e10x.c b/gd32e10x/cmsis/gd/gd32e10x/source/system_gd32e10x.c index 2c027675..535ab95a 100644 --- a/gd32e10x/cmsis/gd/gd32e10x/source/system_gd32e10x.c +++ b/gd32e10x/cmsis/gd/gd32e10x/source/system_gd32e10x.c @@ -129,12 +129,14 @@ void SystemInit (void) /* configure the system clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ system_clock_config(); - -#ifdef VECT_TAB_SRAM - nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET); -#else - nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET); -#endif + + /* + #ifdef VECT_TAB_SRAM + nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET); + #else + nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET); + #endif + */ } diff --git a/gd32e10x/standard_peripheral/include/gd32e10x_fmc.c b/gd32e10x/standard_peripheral/include/gd32e10x_fmc.c deleted file mode 100644 index 11a8c1c2..00000000 --- a/gd32e10x/standard_peripheral/include/gd32e10x_fmc.c +++ /dev/null @@ -1,880 +0,0 @@ -/*! - \file gd32e10x_fmc.c - \brief FMC driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2020-05-11, V1.0.1, firmware for GD32E10x - \version 2020-09-30, V1.1.0, firmware for GD32E10x - \version 2020-12-31, V1.2.0, firmware for GD32E10x -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_fmc.h" - -/* FMC mask */ -#define LOW_8BITS_MASK ((uint32_t)0x000000FFU) -#define HIGH_8BITS_MASK ((uint32_t)0x0000FF00U) -#define LOW_8BITS_MASK1 ((uint32_t)0x00FF0000U) -#define HIGH_8BITS_MASK1 ((uint32_t)0xFF000000U) -#define LOW_16BITS_MASK ((uint32_t)0x0000FFFFU) -#define HIGH_16BITS_MASK ((uint32_t)0xFFFF0000U) - -/* USER of option bytes mask */ -#define OB_USER_MASK ((uint8_t)0xF8U) - -/* OB_WP mask */ -#define OB_WP0_MASK ((uint32_t)0x000000FFU) -#define OB_WP1_MASK ((uint32_t)0x0000FF00U) -#define OB_WP2_MASK ((uint32_t)0x00FF0000U) -#define OB_WP3_MASK ((uint32_t)0xFF000000U) - -/* return the FMC state */ -static fmc_state_enum fmc_state_get(void); -/* check FMC ready or not */ -static fmc_state_enum fmc_ready_wait(uint32_t timeout); - -/* FMC main memory programming functions */ - -/*! - \brief enable pre-fetch - \param[in] none - \param[out] none - \retval none -*/ -void fmc_prefetch_enable(void) -{ - FMC_WS |= FMC_WS_PFEN; -} - -/*! - \brief disable pre-fetch - \param[in] none - \param[out] none - \retval none -*/ -void fmc_prefetch_disable(void) -{ - FMC_WS &= ~FMC_WS_PFEN; -} - -/*! - \brief enable IBUS cache - \param[in] none - \param[out] none - \retval none -*/ -void fmc_ibus_enable(void) -{ - FMC_WS |= FMC_WS_ICEN; -} - -/*! - \brief disable IBUS cache - \param[in] none - \param[out] none - \retval none -*/ -void fmc_ibus_disable(void) -{ - FMC_WS &= ~FMC_WS_ICEN; -} - -/*! - \brief enable DBUS cache - \param[in] none - \param[out] none - \retval none -*/ -void fmc_dbus_enable(void) -{ - FMC_WS |= FMC_WS_DCEN; -} - -/*! - \brief disable DBUS cache - \param[in] none - \param[out] none - \retval none -*/ -void fmc_dbus_disable(void) -{ - FMC_WS &= ~FMC_WS_DCEN; -} - -/*! - \brief reset IBUS cache - \param[in] none - \param[out] none - \retval none -*/ -void fmc_ibus_reset(void) -{ - FMC_WS |= FMC_WS_ICRST; -} - -/*! - \brief reset DBUS cache - \param[in] none - \param[out] none - \retval none -*/ -void fmc_dbus_reset(void) -{ - FMC_WS |= FMC_WS_DCRST; -} - -/*! - \brief set program width to flash memory - \param[in] pgw - only one parameter can be selected which is shown as below: - \arg FMC_PROG_W_32B: 32-bit program width to flash memory - \arg FMC_PROG_W_64B: 64-bit program width to flash memory - \param[out] none - \retval none -*/ -void fmc_program_width_set(uint32_t pgw) -{ - uint32_t reg; - - reg = FMC_WS; - /* configure program width to flash memory */ - reg &= ~FMC_WS_PGW; - FMC_WS = (reg | pgw); -} - -/*! - \brief unlock the main FMC operation - \param[in] none - \param[out] none - \retval none -*/ -void fmc_unlock(void) -{ - if(RESET != (FMC_CTL & FMC_CTL_LK)){ - /* write the FMC unlock key */ - FMC_KEY = UNLOCK_KEY0; - FMC_KEY = UNLOCK_KEY1; - } -} - -/*! - \brief lock the main FMC operation - \param[in] none - \param[out] none - \retval none -*/ -void fmc_lock(void) -{ - /* set the LK bit */ - FMC_CTL |= FMC_CTL_LK; -} - -/*! - \brief set the wait state counter value - \param[in] wscnt:wait state counter value - only one parameter can be selected which is shown as below: - \arg FMC_WAIT_STATE_0: FMC 0 wait - \arg FMC_WAIT_STATE_1: FMC 1 wait - \arg FMC_WAIT_STATE_2: FMC 2 wait - \arg FMC_WAIT_STATE_3: FMC 3 wait - \param[out] none - \retval none -*/ -void fmc_wscnt_set(uint32_t wscnt) -{ - uint32_t reg; - - reg = FMC_WS; - /* set the wait state counter value */ - reg &= ~FMC_WS_WSCNT; - FMC_WS = (reg | wscnt); -} - -/*! - \brief FMC erase page - \param[in] page_address: target page address - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum fmc_page_erase(uint32_t page_address) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - FMC_CTL |= FMC_CTL_PER; - FMC_ADDR = page_address; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the PER bit */ - FMC_CTL &= ~FMC_CTL_PER; - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief FMC erase whole chip - \param[in] none - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum fmc_mass_erase(void) -{ - fmc_state_enum fmc_state; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* start whole chip erase */ - FMC_CTL |= FMC_CTL_MER; - FMC_CTL |= FMC_CTL_START; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL &= ~FMC_CTL_MER; - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief FMC program a double word at the corresponding address - \param[in] address: address to program - \param[in] data: double word to program - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PGW and PG bit to start program */ - FMC_WS |= FMC_WS_PGW; - FMC_CTL |= FMC_CTL_PG; - *(__IO uint64_t*)(address) = data; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the PG and PGW bit */ - FMC_CTL &= ~FMC_CTL_PG; - FMC_WS &= ~FMC_WS_PGW; - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief FMC program a word at the corresponding address - \param[in] address: address to program - \param[in] data: word to program - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL |= FMC_CTL_PG; - REG32(address) = data; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief unlock the option byte operation - it is better to used in pairs with ob_lock - \param[in] none - \param[out] none - \retval none -*/ -void ob_unlock(void) -{ - if(RESET == (FMC_CTL & FMC_CTL_OBWEN)){ - /* write the FMC key */ - FMC_OBKEY = UNLOCK_KEY0; - FMC_OBKEY = UNLOCK_KEY1; - } -} - -/*! - \brief lock the option byte operation - it is better to used in pairs with ob_unlock after an operation - \param[in] none - \param[out] none - \retval none -*/ -void ob_lock(void) -{ - /* reset the OBWEN bit */ - FMC_CTL &= ~FMC_CTL_OBWEN; -} - -/*! - \brief erase the FMC option bytes - programmer must ensure FMC & option byte are both unlocked before calling this function - \param[in] none - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum ob_erase(void) -{ - uint8_t temp_spc; - uint32_t temp; - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* check the option bytes security protection value */ - if(RESET == ob_security_protection_flag_get()){ - temp_spc = FMC_NSPC; - }else{ - temp_spc = FMC_USPC; - } - - temp = HIGH_16BITS_MASK | ((uint32_t)temp_spc); - - if(FMC_READY == fmc_state){ - /* start erase the option bytes */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* reset the OBER bit and enable the option bytes programming */ - FMC_CTL &= ~FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_OBPG; - - /* restore the last get option byte security protection code */ - OB_SPC_USER = temp; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - }else{ - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief enable write protection - \param[in] ob_wp: specify sector to be write protected - one or more parameters can be selected which are shown as below: - \arg OB_WP_NONE: disable all write protection - \arg OB_WP_x(x=0..31): write protect specify sector - \arg OB_WP_ALL: write protect all sector - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) -{ - uint32_t i; - uint32_t op_byte[4]; - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - for(i = 0U; i < 4U; i++){ - op_byte[i] = OP_BYTE(i); - } - ob_wp = (uint32_t)(~ob_wp); - op_byte[2] = (ob_wp & LOW_8BITS_MASK) | ((ob_wp & HIGH_8BITS_MASK) << 8U); - op_byte[3] = ((ob_wp & LOW_8BITS_MASK1) >> 16U) | ((ob_wp & HIGH_8BITS_MASK1) >> 8U); - - if(FMC_READY == fmc_state){ - /* start erase the option byte */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* reset the OBER bit and enable the option bytes programming */ - FMC_CTL &= ~FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_OBPG; - - for(i = 0U; i < 4U; i++){ - OP_BYTE(i) = op_byte[i]; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY != fmc_state){ - break; - } - } - - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - }else{ - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - } - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief configure security protection - \param[in] ob_spc: specify security protection code - only one parameter can be selected which is shown as below: - \arg FMC_NSPC: no security protection - \arg FMC_USPC: under security protection - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum ob_security_protection_config(uint8_t ob_spc) -{ - uint8_t i; - uint32_t op_byte[4]; - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - for(i = 0U; i < 4U; i++){ - op_byte[i] = OP_BYTE(i); - } - op_byte[0] = ((uint32_t)(ob_spc)) | ((op_byte[0] & HIGH_16BITS_MASK)); - - if(FMC_READY == fmc_state){ - /* start erase the option byte */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* reset the OBER bit and enable the option bytes programming */ - FMC_CTL &= ~FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_OBPG; - - for(i = 0U; i < 4U; i++){ - OP_BYTE(i) = op_byte[i]; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY != fmc_state){ - break; - } - } - - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - }else{ - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - } - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program option bytes USER - programmer must ensure FMC & option bytes are both unlocked before calling this function - \param[in] ob_fwdgt: option bytes free watchdog value - only one parameter can be selected which is shown as below: - \arg OB_FWDGT_SW: software free watchdog - \arg OB_FWDGT_HW: hardware free watchdog - \param[in] ob_deepsleep: option bytes deepsleep reset value - only one parameter can be selected which is shown as below: - \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode - \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode - \param[in] ob_stdby: option bytes standby reset value - only one parameter can be selected which is shown as below: - \arg OB_STDBY_NRST: no reset when entering standby mode - \arg OB_STDBY_RST: generate a reset instead of entering standby mode - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby) -{ - uint8_t i; - uint32_t temp; - uint32_t op_byte[4]; - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - for(i = 0U; i < 4U; i++){ - op_byte[i] = OP_BYTE(i); - } - temp = ((uint8_t)((uint8_t)((uint8_t)(ob_fwdgt) | ob_deepsleep) | ob_stdby) | (OB_USER_MASK)); - op_byte[0] = ((uint32_t)(temp) << 16U) | ((op_byte[0] & LOW_16BITS_MASK)); - - if(FMC_READY == fmc_state){ - /* start erase the option byte */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* reset the OBER bit and enable the option bytes programming */ - FMC_CTL &= ~FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_OBPG; - - for(i = 0U; i < 4U; i++){ - OP_BYTE(i) = op_byte[i]; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY != fmc_state){ - break; - } - } - - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - }else{ - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - } - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program option bytes data - \param[in] ob_data: the byte to be programmed - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_TOERR: timeout error -*/ - -fmc_state_enum ob_data_program(uint16_t ob_data) -{ - uint8_t i; - uint32_t op_byte[4]; - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - for(i = 0U; i < 4U; i++){ - op_byte[i] = OP_BYTE(i); - } - op_byte[1] = (uint32_t)((ob_data & LOW_8BITS_MASK) | ((ob_data & HIGH_8BITS_MASK) << 8U)); - - if(FMC_READY == fmc_state){ - /* start erase the option byte */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* reset the OBER bit and enable the option bytes programming */ - FMC_CTL &= ~FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_OBPG; - - for(i = 0U; i < 4U; i++){ - OP_BYTE(i) = op_byte[i]; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY != fmc_state){ - break; - } - } - - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - }else{ - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - } - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief get OB_USER in register FMC_OBSTAT - \param[in] none - \param[out] none - \retval the FMC user option bytes values -*/ -uint8_t ob_user_get(void) -{ - /* return the FMC user option bytes value */ - return (uint8_t)(FMC_OBSTAT >> 2U); -} - -/*! - \brief get OB_DATA in register FMC_OBSTAT - \param[in] none - \param[out] none - \retval ob_data -*/ -uint16_t ob_data_get(void) -{ - return (uint16_t)(FMC_OBSTAT >> 10U); -} - -/*! - \brief get the FMC option byte write protection (OB_WP) in register FMC_WP - \param[in] none - \param[out] none - \retval the FMC write protection option bytes value -*/ -uint32_t ob_write_protection_get(void) -{ - /* return the FMC write protection option bytes value */ - return FMC_WP; -} - -/*! - \brief get the FMC option bytes security protection state - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus ob_security_protection_flag_get(void) -{ - FlagStatus spc_state = RESET; - - if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){ - spc_state = SET; - }else{ - spc_state = RESET; - } - return spc_state; -} - -/*! - \brief check flag is set or not - \param[in] flag: check FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_BUSY: FMC busy flag bit - \arg FMC_FLAG_PGERR: FMC operation error flag bit - \arg FMC_FLAG_PGAERR: FMC program alignment error flag bit - \arg FMC_FLAG_WPERR: FMC erase/program protection error flag bit - \arg FMC_FLAG_END: FMC end of operation flag bit - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_flag_get(uint32_t flag) -{ - FlagStatus status = RESET; - - if(FMC_STAT & flag){ - status = SET; - } - /* return the state of corresponding FMC flag */ - return status; -} - -/*! - \brief clear the FMC flag - \param[in] flag: clear FMC flag - one or more parameters can be selected which is shown as below: - \arg FMC_FLAG_PGERR: FMC operation error flag bit - \arg FMC_FLAG_PGAERR: FMC program alignment error flag bit - \arg FMC_FLAG_WPERR: FMC erase/program protection error flag bit - \arg FMC_FLAG_END: FMC end of operation flag bit - \param[out] none - \retval none -*/ -void fmc_flag_clear(uint32_t flag) -{ - /* clear the flags */ - FMC_STAT = flag; -} - -/*! - \brief enable FMC interrupt - \param[in] interrupt: the FMC interrupt source - only one parameter can be selected which is shown as below: - \arg FMC_INT_END: enable FMC end of program interrupt - \arg FMC_INT_ERR: enable FMC error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_enable(uint32_t interrupt) -{ - FMC_CTL |= interrupt; -} - -/*! - \brief disable FMC interrupt - \param[in] interrupt: the FMC interrupt source - only one parameter can be selected which is shown as below: - \arg FMC_INT_END: enable FMC end of program interrupt - \arg FMC_INT_ERR: enable FMC error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_disable(uint32_t interrupt) -{ - FMC_CTL &= ~(uint32_t)interrupt; -} - -/*! - \brief get FMC interrupt flag state - \param[in] flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg FMC_INT_FLAG_PGERR: FMC operation error interrupt flag bit - \arg FMC_FLAG_PGAERR: FMC program alignment error flag bit - \arg FMC_INT_FLAG_WPERR: FMC erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag bit - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_interrupt_flag_get(uint32_t flag) -{ - FlagStatus status = RESET; - - if(FMC_STAT & flag){ - status = SET; - } - /* return the state of corresponding FMC flag */ - return status; -} - -/*! - \brief clear FMC interrupt flag state - \param[in] flag: FMC interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg FMC_INT_FLAG_PGERR: FMC operation error interrupt flag bit - \arg FMC_FLAG_PGAERR: FMC program alignment error flag bit - \arg FMC_INT_FLAG_WPERR: FMC erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag bit - \param[out] none - \retval none -*/ -void fmc_interrupt_flag_clear(uint32_t flag) -{ - /* clear the flag */ - FMC_STAT = flag; -} - -/*! - \brief get the FMC state - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -static fmc_state_enum fmc_state_get(void) -{ - fmc_state_enum fmc_state = FMC_READY; - - if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)){ - fmc_state = FMC_BUSY; - }else{ - if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR)){ - fmc_state = FMC_WPERR; - }else{ - if((uint32_t)0x00U != (FMC_STAT & (FMC_STAT_PGERR))){ - fmc_state = FMC_PGERR; - }else{ - if((uint32_t)0x00U != (FMC_STAT & (FMC_STAT_PGAERR))){ - fmc_state = FMC_PGAERR; - } - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief check whether FMC is ready or not - \param[in] timeout: count of loop - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -static fmc_state_enum fmc_ready_wait(uint32_t timeout) -{ - fmc_state_enum fmc_state = FMC_BUSY; - - /* wait for FMC ready */ - do{ - /* get FMC state */ - fmc_state = fmc_state_get(); - timeout--; - }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); - - if(FMC_BUSY == fmc_state){ - fmc_state = FMC_TOERR; - } - /* return the FMC state */ - return fmc_state; -} diff --git a/gd32e10x/standard_peripheral/include/gd32e10x_libopt.h b/gd32e10x/standard_peripheral/include/gd32e10x_libopt.h new file mode 100644 index 00000000..0d04f15a --- /dev/null +++ b/gd32e10x/standard_peripheral/include/gd32e10x_libopt.h @@ -0,0 +1,62 @@ +/*! + \file gd32e10x_libopt.h + \brief library optional for gd32e10x + + \version 2018-03-26, V1.0.0, demo for GD32E103 + \version 2020-09-30, V1.1.0, demo for GD32E103 + \version 2020-12-31, V1.2.0, demo for GD32E103 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E10X_LIBOPT_H +#define GD32E10X_LIBOPT_H + +#include "gd32e10x_rcu.h" +#include "gd32e10x_adc.h" +#include "gd32e10x_crc.h" +#include "gd32e10x_ctc.h" +#include "gd32e10x_dac.h" +#include "gd32e10x_dbg.h" +#include "gd32e10x_dma.h" +#include "gd32e10x_exti.h" +#include "gd32e10x_fmc.h" +#include "gd32e10x_fwdgt.h" +#include "gd32e10x_gpio.h" +#include "gd32e10x_i2c.h" +#include "gd32e10x_pmu.h" +#include "gd32e10x_bkp.h" +#include "gd32e10x_rtc.h" +#include "gd32e10x_spi.h" +#include "gd32e10x_timer.h" +#include "gd32e10x_usart.h" +#include "gd32e10x_wwdgt.h" +#include "gd32e10x_misc.h" +#include "gd32e10x_exmc.h" + +#endif /* GD32E10X_LIBOPT_H */ diff --git a/include/dt-bindings/pinctrl/gd32e103c(b-8)xx-pinctrl.h b/include/dt-bindings/pinctrl/gd32e103c(b-8)xx-pinctrl.h new file mode 100644 index 00000000..4d805595 --- /dev/null +++ b/include/dt-bindings/pinctrl/gd32e103c(b-8)xx-pinctrl.h @@ -0,0 +1,689 @@ +/* + * Autogenerated file + * + * SPDX-License-Identifier: Apache 2.0 + */ + +#include "gd32e103xx-afio.h" + +/* ADC01_IN0 */ +#define ADC01_IN0_PA0 \ + GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) + +/* ADC01_IN1 */ +#define ADC01_IN1_PA1 \ + GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) + +/* ADC01_IN2 */ +#define ADC01_IN2_PA2 \ + GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) + +/* ADC01_IN3 */ +#define ADC01_IN3_PA3 \ + GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) + +/* ADC01_IN4 */ +#define ADC01_IN4_PA4 \ + GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) + +/* ADC01_IN5 */ +#define ADC01_IN5_PA5 \ + GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) + +/* ADC01_IN6 */ +#define ADC01_IN6_PA6 \ + GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) + +/* ADC01_IN7 */ +#define ADC01_IN7_PA7 \ + GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) + +/* ADC01_IN8 */ +#define ADC01_IN8_PB0 \ + GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) + +/* ADC01_IN9 */ +#define ADC01_IN9_PB1 \ + GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) + +/* ANALOG */ +#define ANALOG_PA0 \ + GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) +#define ANALOG_PA1 \ + GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) +#define ANALOG_PA10 \ + GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP) +#define ANALOG_PA11 \ + GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP) +#define ANALOG_PA12 \ + GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP) +#define ANALOG_PA13 \ + GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP) +#define ANALOG_PA14 \ + GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP) +#define ANALOG_PA15 \ + GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP) +#define ANALOG_PA2 \ + GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) +#define ANALOG_PA3 \ + GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) +#define ANALOG_PA4 \ + GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) +#define ANALOG_PA5 \ + GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) +#define ANALOG_PA6 \ + GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) +#define ANALOG_PA7 \ + GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) +#define ANALOG_PA8 \ + GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP) +#define ANALOG_PA9 \ + GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP) +#define ANALOG_PB0 \ + GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) +#define ANALOG_PB1 \ + GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) +#define ANALOG_PB10 \ + GD32_PINMUX_AFIO('B', 10, ANALOG, NORMP) +#define ANALOG_PB11 \ + GD32_PINMUX_AFIO('B', 11, ANALOG, NORMP) +#define ANALOG_PB12 \ + GD32_PINMUX_AFIO('B', 12, ANALOG, NORMP) +#define ANALOG_PB13 \ + GD32_PINMUX_AFIO('B', 13, ANALOG, NORMP) +#define ANALOG_PB14 \ + GD32_PINMUX_AFIO('B', 14, ANALOG, NORMP) +#define ANALOG_PB15 \ + GD32_PINMUX_AFIO('B', 15, ANALOG, NORMP) +#define ANALOG_PB2 \ + GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP) +#define ANALOG_PB3 \ + GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP) +#define ANALOG_PB4 \ + GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP) +#define ANALOG_PB5 \ + GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP) +#define ANALOG_PB6 \ + GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP) +#define ANALOG_PB7 \ + GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP) +#define ANALOG_PB8 \ + GD32_PINMUX_AFIO('B', 8, ANALOG, NORMP) +#define ANALOG_PB9 \ + GD32_PINMUX_AFIO('B', 9, ANALOG, NORMP) +#define ANALOG_PC13 \ + GD32_PINMUX_AFIO('C', 13, ANALOG, NORMP) +#define ANALOG_PC14 \ + GD32_PINMUX_AFIO('C', 14, ANALOG, NORMP) +#define ANALOG_PC15 \ + GD32_PINMUX_AFIO('C', 15, ANALOG, NORMP) +#define ANALOG_PD0 \ + GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP) +#define ANALOG_PD1 \ + GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP) + +/* CK_OUT0 */ +#define CK_OUT0_PA8 \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) + +/* CTC_SYNC */ +#define CTC_SYNC_PA8 \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) + +/* DAC_OUT0 */ +#define DAC_OUT0_PA4 \ + GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) + +/* DAC_OUT1 */ +#define DAC_OUT1_PA5 \ + GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) + +/* I2C0_SCL */ +#define I2C0_SCL_PB6_NORMP \ + GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP) +#define I2C0_SCL_PB8_RMP \ + GD32_PINMUX_AFIO('B', 8, ALTERNATE, I2C0_RMP) + +/* I2C0_SDA */ +#define I2C0_SDA_PB7_NORMP \ + GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP) +#define I2C0_SDA_PB9_RMP \ + GD32_PINMUX_AFIO('B', 9, ALTERNATE, I2C0_RMP) + +/* I2C0_SMBA */ +#define I2C0_SMBA_PB5 \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP) + +/* I2C0_TXFRAME */ +#define I2C0_TXFRAME_PB4 \ + GD32_PINMUX_AFIO('B', 4, ALTERNATE, NORMP) + +/* I2C1_SCL */ +#define I2C1_SCL_PB10 \ + GD32_PINMUX_AFIO('B', 10, ALTERNATE, NORMP) + +/* I2C1_SDA */ +#define I2C1_SDA_PB11 \ + GD32_PINMUX_AFIO('B', 11, ALTERNATE, NORMP) + +/* I2C1_SMBA */ +#define I2C1_SMBA_PB12 \ + GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) + +/* I2C1_TXFRAME */ +#define I2C1_TXFRAME_PB13 \ + GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) + +/* I2S1_CK */ +#define I2S1_CK_PB13 \ + GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) + +/* I2S1_SD */ +#define I2S1_SD_PB15_INP \ + GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) +#define I2S1_SD_PB15_OUT \ + GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) + +/* I2S1_WS */ +#define I2S1_WS_PB12_INP \ + GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) +#define I2S1_WS_PB12_OUT \ + GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) + +/* I2S2_CK */ +#define I2S2_CK_PB3_NORMP \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, I2S2_NORMP) + +/* I2S2_SD */ +#define I2S2_SD_PB5_INP_NORMP \ + GD32_PINMUX_AFIO('B', 5, GPIO_IN, I2S2_NORMP) +#define I2S2_SD_PB5_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, I2S2_NORMP) + +/* I2S2_WS */ +#define I2S2_WS_PA15_INP_NORMP \ + GD32_PINMUX_AFIO('A', 15, GPIO_IN, I2S2_NORMP) +#define I2S2_WS_PA15_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 15, ALTERNATE, I2S2_NORMP) +#define I2S2_WS_PA4_INP_RMP \ + GD32_PINMUX_AFIO('A', 4, GPIO_IN, I2S2_RMP) +#define I2S2_WS_PA4_OUT_RMP \ + GD32_PINMUX_AFIO('A', 4, ALTERNATE, I2S2_RMP) + +/* RTC_TAMPER */ +#define RTC_TAMPER_PC13 \ + GD32_PINMUX_AFIO('C', 13, GPIO_IN, NORMP) + +/* SPI0_IO2 */ +#define SPI0_IO2_PA2_NORMP \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, SPI0_NORMP) +#define SPI0_IO2_PB6_RMP \ + GD32_PINMUX_AFIO('B', 6, ALTERNATE, SPI0_RMP) + +/* SPI0_IO3 */ +#define SPI0_IO3_PA3_NORMP \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, SPI0_NORMP) +#define SPI0_IO3_PB7_RMP \ + GD32_PINMUX_AFIO('B', 7, ALTERNATE, SPI0_RMP) + +/* SPI0_MISO */ +#define SPI0_MISO_PA6_INP_NORMP \ + GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP) +#define SPI0_MISO_PA6_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP) +#define SPI0_MISO_PB4_INP_RMP \ + GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP) +#define SPI0_MISO_PB4_OUT_RMP \ + GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP) + +/* SPI0_MOSI */ +#define SPI0_MOSI_PA7_INP_NORMP \ + GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP) +#define SPI0_MOSI_PA7_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP) +#define SPI0_MOSI_PB5_INP_RMP \ + GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP) +#define SPI0_MOSI_PB5_OUT_RMP \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP) + +/* SPI0_NSS */ +#define SPI0_NSS_PA4_INP_NORMP \ + GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP) +#define SPI0_NSS_PA4_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP) +#define SPI0_NSS_PA15_INP_RMP \ + GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP) +#define SPI0_NSS_PA15_OUT_RMP \ + GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP) + +/* SPI0_SCK */ +#define SPI0_SCK_PA5_INP_NORMP \ + GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP) +#define SPI0_SCK_PA5_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP) +#define SPI0_SCK_PB3_INP_RMP \ + GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP) +#define SPI0_SCK_PB3_OUT_RMP \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP) + +/* SPI1_MISO */ +#define SPI1_MISO_PB14_INP \ + GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP) +#define SPI1_MISO_PB14_OUT \ + GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP) + +/* SPI1_MOSI */ +#define SPI1_MOSI_PB15_INP \ + GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) +#define SPI1_MOSI_PB15_OUT \ + GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) + +/* SPI1_NSS */ +#define SPI1_NSS_PB12_INP \ + GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) +#define SPI1_NSS_PB12_OUT \ + GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) + +/* SPI1_SCK */ +#define SPI1_SCK_PB13_INP \ + GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP) +#define SPI1_SCK_PB13_OUT \ + GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) + +/* SPI2_MISO */ +#define SPI2_MISO_PB4_INP_NORMP \ + GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI2_NORMP) +#define SPI2_MISO_PB4_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI2_NORMP) + +/* SPI2_MOSI */ +#define SPI2_MOSI_PB5_INP_NORMP \ + GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI2_NORMP) +#define SPI2_MOSI_PB5_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI2_NORMP) + +/* SPI2_NSS */ +#define SPI2_NSS_PA15_INP_NORMP \ + GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI2_NORMP) +#define SPI2_NSS_PA15_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI2_NORMP) +#define SPI2_NSS_PA4_INP_RMP \ + GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI2_RMP) +#define SPI2_NSS_PA4_OUT_RMP \ + GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI2_RMP) + +/* SPI2_SCK */ +#define SPI2_SCK_PB3_INP_NORMP \ + GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI2_NORMP) +#define SPI2_SCK_PB3_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI2_NORMP) + +/* TIMER0_BKIN */ +#define TIMER0_BKIN_PB12_NORMP \ + GD32_PINMUX_AFIO('B', 12, GPIO_IN, TIMER0_NORMP) +#define TIMER0_BKIN_PA6_PRMP \ + GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER0_PRMP) + +/* TIMER0_CH0 */ +#define TIMER0_CH0_PA8_INP_NORMP \ + GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH0_PA8_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH0_PA8_INP_PRMP \ + GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH0_PA8_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_CH0_ON */ +#define TIMER0_CH0_ON_PB13_INP_NORMP \ + GD32_PINMUX_AFIO('B', 13, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH0_ON_PB13_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 13, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH0_ON_PA7_INP_PRMP \ + GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH0_ON_PA7_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_CH1 */ +#define TIMER0_CH1_PA9_INP_NORMP \ + GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH1_PA9_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH1_PA9_INP_PRMP \ + GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH1_PA9_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_CH1_ON */ +#define TIMER0_CH1_ON_PB14_INP_NORMP \ + GD32_PINMUX_AFIO('B', 14, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH1_ON_PB14_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 14, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH1_ON_PB0_INP_PRMP \ + GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH1_ON_PB0_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_CH2 */ +#define TIMER0_CH2_PA10_INP_NORMP \ + GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH2_PA10_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH2_PA10_INP_PRMP \ + GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH2_PA10_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_CH2_ON */ +#define TIMER0_CH2_ON_PB15_NORMP \ + GD32_PINMUX_AFIO('B', 15, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH2_ON_PB1_PRMP \ + GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_CH3 */ +#define TIMER0_CH3_PA11_INP_NORMP \ + GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH3_PA11_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH3_PA11_INP_PRMP \ + GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH3_PA11_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_ETI */ +#define TIMER0_ETI_PA12_NORMP \ + GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP) +#define TIMER0_ETI_PA12_PRMP \ + GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP) + +/* TIMER10_CH0 */ +#define TIMER10_CH0_PB9_INP \ + GD32_PINMUX_AFIO('B', 9, GPIO_IN, NORMP) +#define TIMER10_CH0_PB9_OUT \ + GD32_PINMUX_AFIO('B', 9, ALTERNATE, NORMP) + +/* TIMER11_CH0 */ +#define TIMER11_CH0_PB14_INP \ + GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP) +#define TIMER11_CH0_PB14_OUT \ + GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP) + +/* TIMER11_CH11 */ +#define TIMER11_CH11_PB15_INP \ + GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) +#define TIMER11_CH11_PB15_OUT \ + GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) + +/* TIMER12_CH0 */ +#define TIMER12_CH0_PA6_INP \ + GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP) +#define TIMER12_CH0_PA6_OUT \ + GD32_PINMUX_AFIO('A', 6, ALTERNATE, NORMP) + +/* TIMER13_CH0 */ +#define TIMER13_CH0_PA7_INP \ + GD32_PINMUX_AFIO('A', 7, GPIO_IN, NORMP) +#define TIMER13_CH0_PA7_OUT \ + GD32_PINMUX_AFIO('A', 7, ALTERNATE, NORMP) + +/* TIMER1_CH0_ETI */ +#define TIMER1_CH0_ETI_PA0 \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) + +/* TIMER1_CH1 */ +#define TIMER1_CH1_PA1_INP_NORMP \ + GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_NORMP) +#define TIMER1_CH1_PA1_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_NORMP) +#define TIMER1_CH1_PA1_INP_PRMP2 \ + GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_PRMP2) +#define TIMER1_CH1_PA1_OUT_PRMP2 \ + GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_PRMP2) +#define TIMER1_CH1_PB3_INP_PRMP1 \ + GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_PRMP1) +#define TIMER1_CH1_PB3_OUT_PRMP1 \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_PRMP1) +#define TIMER1_CH1_PB3_INP_FRMP \ + GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_FRMP) +#define TIMER1_CH1_PB3_OUT_FRMP \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_FRMP) + +/* TIMER1_CH2 */ +#define TIMER1_CH2_PA2_INP_NORMP \ + GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_NORMP) +#define TIMER1_CH2_PA2_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_NORMP) +#define TIMER1_CH2_PA2_INP_PRMP1 \ + GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_PRMP1) +#define TIMER1_CH2_PA2_OUT_PRMP1 \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_PRMP1) +#define TIMER1_CH2_PB10_INP_PRMP2 \ + GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_PRMP2) +#define TIMER1_CH2_PB10_OUT_PRMP2 \ + GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_PRMP2) +#define TIMER1_CH2_PB10_INP_FRMP \ + GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_FRMP) +#define TIMER1_CH2_PB10_OUT_FRMP \ + GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_FRMP) + +/* TIMER1_CH3 */ +#define TIMER1_CH3_PA3_INP_NORMP \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_NORMP) +#define TIMER1_CH3_PA3_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_NORMP) +#define TIMER1_CH3_PA3_INP_PRMP1 \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_PRMP1) +#define TIMER1_CH3_PA3_OUT_PRMP1 \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_PRMP1) +#define TIMER1_CH3_PB11_INP_PRMP2 \ + GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_PRMP2) +#define TIMER1_CH3_PB11_OUT_PRMP2 \ + GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_PRMP2) +#define TIMER1_CH3_PB11_INP_FRMP \ + GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_FRMP) +#define TIMER1_CH3_PB11_OUT_FRMP \ + GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_FRMP) + +/* TIMER2_CH0 */ +#define TIMER2_CH0_PA6_INP_NORMP \ + GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP) +#define TIMER2_CH0_PA6_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP) +#define TIMER2_CH0_PB4_INP_PRMP \ + GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP) +#define TIMER2_CH0_PB4_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP) + +/* TIMER2_CH1 */ +#define TIMER2_CH1_PA7_INP_NORMP \ + GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP) +#define TIMER2_CH1_PA7_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP) +#define TIMER2_CH1_PB5_INP_PRMP \ + GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP) +#define TIMER2_CH1_PB5_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP) + +/* TIMER2_CH2 */ +#define TIMER2_CH2_PB0_INP_NORMP \ + GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP) +#define TIMER2_CH2_PB0_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP) +#define TIMER2_CH2_PB0_INP_PRMP \ + GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP) +#define TIMER2_CH2_PB0_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP) + +/* TIMER2_CH3 */ +#define TIMER2_CH3_PB1_INP_NORMP \ + GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP) +#define TIMER2_CH3_PB1_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP) +#define TIMER2_CH3_PB1_INP_PRMP \ + GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP) +#define TIMER2_CH3_PB1_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP) + +/* TIMER3_CH0 */ +#define TIMER3_CH0_PB6_INP_NORMP \ + GD32_PINMUX_AFIO('B', 6, GPIO_IN, TIMER3_NORMP) +#define TIMER3_CH0_PB6_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 6, ALTERNATE, TIMER3_NORMP) + +/* TIMER3_CH1 */ +#define TIMER3_CH1_PB7_INP_NORMP \ + GD32_PINMUX_AFIO('B', 7, GPIO_IN, TIMER3_NORMP) +#define TIMER3_CH1_PB7_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 7, ALTERNATE, TIMER3_NORMP) + +/* TIMER3_CH2 */ +#define TIMER3_CH2_PB8_INP_NORMP \ + GD32_PINMUX_AFIO('B', 8, GPIO_IN, TIMER3_NORMP) +#define TIMER3_CH2_PB8_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 8, ALTERNATE, TIMER3_NORMP) + +/* TIMER3_CH3 */ +#define TIMER3_CH3_PB9_INP_NORMP \ + GD32_PINMUX_AFIO('B', 9, GPIO_IN, TIMER3_NORMP) +#define TIMER3_CH3_PB9_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 9, ALTERNATE, TIMER3_NORMP) + +/* TIMER4_CH0 */ +#define TIMER4_CH0_PA0_INP \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) +#define TIMER4_CH0_PA0_OUT \ + GD32_PINMUX_AFIO('A', 0, ALTERNATE, NORMP) + +/* TIMER4_CH1 */ +#define TIMER4_CH1_PA1_INP \ + GD32_PINMUX_AFIO('A', 1, GPIO_IN, NORMP) +#define TIMER4_CH1_PA1_OUT \ + GD32_PINMUX_AFIO('A', 1, ALTERNATE, NORMP) + +/* TIMER4_CH2 */ +#define TIMER4_CH2_PA2_INP \ + GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP) +#define TIMER4_CH2_PA2_OUT \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP) + +/* TIMER4_CH3 */ +#define TIMER4_CH3_PA3_INP \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP) +#define TIMER4_CH3_PA3_OUT \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP) + +/* TIMER8_CH0 */ +#define TIMER8_CH0_PA2_INP \ + GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP) +#define TIMER8_CH0_PA2_OUT \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP) + +/* TIMER8_CH1 */ +#define TIMER8_CH1_PA3_INP \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP) +#define TIMER8_CH1_PA3_OUT \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP) + +/* TIMER9_CH0 */ +#define TIMER9_CH0_PB8_INP \ + GD32_PINMUX_AFIO('B', 8, GPIO_IN, NORMP) +#define TIMER9_CH0_PB8_OUT \ + GD32_PINMUX_AFIO('B', 8, ALTERNATE, NORMP) + +/* USART0_CK */ +#define USART0_CK_PA8 \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) + +/* USART0_CTS */ +#define USART0_CTS_PA11 \ + GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) + +/* USART0_RTS */ +#define USART0_RTS_PA12 \ + GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) + +/* USART0_RX */ +#define USART0_RX_PA10_NORMP \ + GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP) +#define USART0_RX_PB7_RMP \ + GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP) + +/* USART0_TX */ +#define USART0_TX_PA9_NORMP \ + GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP) +#define USART0_TX_PB6_RMP \ + GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP) + +/* USART1_CK */ +#define USART1_CK_PA4_NORMP \ + GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP) + +/* USART1_CTS */ +#define USART1_CTS_PA0_NORMP \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP) + +/* USART1_RTS */ +#define USART1_RTS_PA1_NORMP \ + GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP) + +/* USART1_RX */ +#define USART1_RX_PA3_NORMP \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP) + +/* USART1_TX */ +#define USART1_TX_PA2_NORMP \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP) + +/* USART2_CK */ +#define USART2_CK_PB12_NORMP \ + GD32_PINMUX_AFIO('B', 12, ALTERNATE, USART2_NORMP) + +/* USART2_CTS */ +#define USART2_CTS_PB13_NORMP \ + GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_NORMP) +#define USART2_CTS_PB13_PRMP \ + GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_PRMP) + +/* USART2_RTS */ +#define USART2_RTS_PB14_NORMP \ + GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_NORMP) +#define USART2_RTS_PB14_PRMP \ + GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_PRMP) + +/* USART2_RX */ +#define USART2_RX_PB11_NORMP \ + GD32_PINMUX_AFIO('B', 11, GPIO_IN, USART2_NORMP) + +/* USART2_TX */ +#define USART2_TX_PB10_NORMP \ + GD32_PINMUX_AFIO('B', 10, ALTERNATE, USART2_NORMP) + +/* USBFS_DM */ +#define USBFS_DM_PA11_INP \ + GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) +#define USBFS_DM_PA11_OUT \ + GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP) + +/* USBFS_DP */ +#define USBFS_DP_PA12_INP \ + GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP) +#define USBFS_DP_PA12_OUT \ + GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) + +/* USBFS_ID */ +#define USBFS_ID_PA10_INP \ + GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP) +#define USBFS_ID_PA10_OUT \ + GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP) + +/* USBFS_SOF */ +#define USBFS_SOF_PA8 \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) + +/* USBFS_VBUS */ +#define USBFS_VBUS_PA9 \ + GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP) + +/* WKUP */ +#define WKUP_PA0 \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) diff --git a/include/dt-bindings/pinctrl/gd32e103r(b-8)xx-pinctrl.h b/include/dt-bindings/pinctrl/gd32e103r(b-8)xx-pinctrl.h new file mode 100644 index 00000000..5d8def9c --- /dev/null +++ b/include/dt-bindings/pinctrl/gd32e103r(b-8)xx-pinctrl.h @@ -0,0 +1,857 @@ +/* + * Autogenerated file + * + * SPDX-License-Identifier: Apache 2.0 + */ + +#include "gd32e103xx-afio.h" + +/* ADC01_IN0 */ +#define ADC01_IN0_PA0 \ + GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) + +/* ADC01_IN1 */ +#define ADC01_IN1_PA1 \ + GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) + +/* ADC01_IN10 */ +#define ADC01_IN10_PC0 \ + GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP) + +/* ADC01_IN11 */ +#define ADC01_IN11_PC1 \ + GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP) + +/* ADC01_IN12 */ +#define ADC01_IN12_PC2 \ + GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP) + +/* ADC01_IN13 */ +#define ADC01_IN13_PC3 \ + GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP) + +/* ADC01_IN14 */ +#define ADC01_IN14_PC4 \ + GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP) + +/* ADC01_IN15 */ +#define ADC01_IN15_PC5 \ + GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP) + +/* ADC01_IN2 */ +#define ADC01_IN2_PA2 \ + GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) + +/* ADC01_IN3 */ +#define ADC01_IN3_PA3 \ + GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) + +/* ADC01_IN4 */ +#define ADC01_IN4_PA4 \ + GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) + +/* ADC01_IN5 */ +#define ADC01_IN5_PA5 \ + GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) + +/* ADC01_IN6 */ +#define ADC01_IN6_PA6 \ + GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) + +/* ADC01_IN7 */ +#define ADC01_IN7_PA7 \ + GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) + +/* ADC01_IN8 */ +#define ADC01_IN8_PB0 \ + GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) + +/* ADC01_IN9 */ +#define ADC01_IN9_PB1 \ + GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) + +/* ANALOG */ +#define ANALOG_PA0 \ + GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) +#define ANALOG_PA1 \ + GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) +#define ANALOG_PA10 \ + GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP) +#define ANALOG_PA11 \ + GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP) +#define ANALOG_PA12 \ + GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP) +#define ANALOG_PA13 \ + GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP) +#define ANALOG_PA14 \ + GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP) +#define ANALOG_PA15 \ + GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP) +#define ANALOG_PA2 \ + GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) +#define ANALOG_PA3 \ + GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) +#define ANALOG_PA4 \ + GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) +#define ANALOG_PA5 \ + GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) +#define ANALOG_PA6 \ + GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) +#define ANALOG_PA7 \ + GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) +#define ANALOG_PA8 \ + GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP) +#define ANALOG_PA9 \ + GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP) +#define ANALOG_PB0 \ + GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) +#define ANALOG_PB1 \ + GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) +#define ANALOG_PB10 \ + GD32_PINMUX_AFIO('B', 10, ANALOG, NORMP) +#define ANALOG_PB11 \ + GD32_PINMUX_AFIO('B', 11, ANALOG, NORMP) +#define ANALOG_PB12 \ + GD32_PINMUX_AFIO('B', 12, ANALOG, NORMP) +#define ANALOG_PB13 \ + GD32_PINMUX_AFIO('B', 13, ANALOG, NORMP) +#define ANALOG_PB14 \ + GD32_PINMUX_AFIO('B', 14, ANALOG, NORMP) +#define ANALOG_PB15 \ + GD32_PINMUX_AFIO('B', 15, ANALOG, NORMP) +#define ANALOG_PB2 \ + GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP) +#define ANALOG_PB3 \ + GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP) +#define ANALOG_PB4 \ + GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP) +#define ANALOG_PB5 \ + GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP) +#define ANALOG_PB6 \ + GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP) +#define ANALOG_PB7 \ + GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP) +#define ANALOG_PB8 \ + GD32_PINMUX_AFIO('B', 8, ANALOG, NORMP) +#define ANALOG_PB9 \ + GD32_PINMUX_AFIO('B', 9, ANALOG, NORMP) +#define ANALOG_PC0 \ + GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP) +#define ANALOG_PC1 \ + GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP) +#define ANALOG_PC10 \ + GD32_PINMUX_AFIO('C', 10, ANALOG, NORMP) +#define ANALOG_PC11 \ + GD32_PINMUX_AFIO('C', 11, ANALOG, NORMP) +#define ANALOG_PC12 \ + GD32_PINMUX_AFIO('C', 12, ANALOG, NORMP) +#define ANALOG_PC13 \ + GD32_PINMUX_AFIO('C', 13, ANALOG, NORMP) +#define ANALOG_PC14 \ + GD32_PINMUX_AFIO('C', 14, ANALOG, NORMP) +#define ANALOG_PC15 \ + GD32_PINMUX_AFIO('C', 15, ANALOG, NORMP) +#define ANALOG_PC2 \ + GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP) +#define ANALOG_PC3 \ + GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP) +#define ANALOG_PC4 \ + GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP) +#define ANALOG_PC5 \ + GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP) +#define ANALOG_PC6 \ + GD32_PINMUX_AFIO('C', 6, ANALOG, NORMP) +#define ANALOG_PC7 \ + GD32_PINMUX_AFIO('C', 7, ANALOG, NORMP) +#define ANALOG_PC8 \ + GD32_PINMUX_AFIO('C', 8, ANALOG, NORMP) +#define ANALOG_PC9 \ + GD32_PINMUX_AFIO('C', 9, ANALOG, NORMP) +#define ANALOG_PD0 \ + GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP) +#define ANALOG_PD1 \ + GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP) +#define ANALOG_PD2 \ + GD32_PINMUX_AFIO('D', 2, ANALOG, NORMP) + +/* CK_OUT0 */ +#define CK_OUT0_PA8 \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) + +/* CTC_SYNC */ +#define CTC_SYNC_PA8 \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) + +/* DAC_OUT0 */ +#define DAC_OUT0_PA4 \ + GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) + +/* DAC_OUT1 */ +#define DAC_OUT1_PA5 \ + GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) + +/* I2C0_SCL */ +#define I2C0_SCL_PB6_NORMP \ + GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP) +#define I2C0_SCL_PB8_RMP \ + GD32_PINMUX_AFIO('B', 8, ALTERNATE, I2C0_RMP) + +/* I2C0_SDA */ +#define I2C0_SDA_PB7_NORMP \ + GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP) +#define I2C0_SDA_PB9_RMP \ + GD32_PINMUX_AFIO('B', 9, ALTERNATE, I2C0_RMP) + +/* I2C0_SMBA */ +#define I2C0_SMBA_PB5 \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP) + +/* I2C0_TXFRAME */ +#define I2C0_TXFRAME_PB4 \ + GD32_PINMUX_AFIO('B', 4, ALTERNATE, NORMP) + +/* I2C1_SCL */ +#define I2C1_SCL_PB10 \ + GD32_PINMUX_AFIO('B', 10, ALTERNATE, NORMP) + +/* I2C1_SDA */ +#define I2C1_SDA_PB11 \ + GD32_PINMUX_AFIO('B', 11, ALTERNATE, NORMP) + +/* I2C1_SMBA */ +#define I2C1_SMBA_PB12 \ + GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) + +/* I2C1_TXFRAME */ +#define I2C1_TXFRAME_PB13 \ + GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) + +/* I2S1_CK */ +#define I2S1_CK_PB13 \ + GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) + +/* I2S1_MCK */ +#define I2S1_MCK_PC6 \ + GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP) + +/* I2S1_SD */ +#define I2S1_SD_PB15_INP \ + GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) +#define I2S1_SD_PB15_OUT \ + GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) + +/* I2S1_WS */ +#define I2S1_WS_PB12_INP \ + GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) +#define I2S1_WS_PB12_OUT \ + GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) + +/* I2S2_CK */ +#define I2S2_CK_PB3_NORMP \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, I2S2_NORMP) +#define I2S2_CK_PC10_RMP \ + GD32_PINMUX_AFIO('C', 10, ALTERNATE, I2S2_RMP) + +/* I2S2_MCK */ +#define I2S2_MCK_PC7 \ + GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP) + +/* I2S2_SD */ +#define I2S2_SD_PB5_INP_NORMP \ + GD32_PINMUX_AFIO('B', 5, GPIO_IN, I2S2_NORMP) +#define I2S2_SD_PB5_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, I2S2_NORMP) +#define I2S2_SD_PC12_INP_RMP \ + GD32_PINMUX_AFIO('C', 12, GPIO_IN, I2S2_RMP) +#define I2S2_SD_PC12_OUT_RMP \ + GD32_PINMUX_AFIO('C', 12, ALTERNATE, I2S2_RMP) + +/* I2S2_WS */ +#define I2S2_WS_PA15_INP_NORMP \ + GD32_PINMUX_AFIO('A', 15, GPIO_IN, I2S2_NORMP) +#define I2S2_WS_PA15_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 15, ALTERNATE, I2S2_NORMP) +#define I2S2_WS_PA4_INP_RMP \ + GD32_PINMUX_AFIO('A', 4, GPIO_IN, I2S2_RMP) +#define I2S2_WS_PA4_OUT_RMP \ + GD32_PINMUX_AFIO('A', 4, ALTERNATE, I2S2_RMP) + +/* RTC_TAMPER */ +#define RTC_TAMPER_PC13 \ + GD32_PINMUX_AFIO('C', 13, GPIO_IN, NORMP) + +/* SPI0_IO2 */ +#define SPI0_IO2_PA2_NORMP \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, SPI0_NORMP) +#define SPI0_IO2_PB6_RMP \ + GD32_PINMUX_AFIO('B', 6, ALTERNATE, SPI0_RMP) + +/* SPI0_IO3 */ +#define SPI0_IO3_PA3_NORMP \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, SPI0_NORMP) +#define SPI0_IO3_PB7_RMP \ + GD32_PINMUX_AFIO('B', 7, ALTERNATE, SPI0_RMP) + +/* SPI0_MISO */ +#define SPI0_MISO_PA6_INP_NORMP \ + GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP) +#define SPI0_MISO_PA6_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP) +#define SPI0_MISO_PB4_INP_RMP \ + GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP) +#define SPI0_MISO_PB4_OUT_RMP \ + GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP) + +/* SPI0_MOSI */ +#define SPI0_MOSI_PA7_INP_NORMP \ + GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP) +#define SPI0_MOSI_PA7_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP) +#define SPI0_MOSI_PB5_INP_RMP \ + GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP) +#define SPI0_MOSI_PB5_OUT_RMP \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP) + +/* SPI0_NSS */ +#define SPI0_NSS_PA4_INP_NORMP \ + GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP) +#define SPI0_NSS_PA4_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP) +#define SPI0_NSS_PA15_INP_RMP \ + GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP) +#define SPI0_NSS_PA15_OUT_RMP \ + GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP) + +/* SPI0_SCK */ +#define SPI0_SCK_PA5_INP_NORMP \ + GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP) +#define SPI0_SCK_PA5_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP) +#define SPI0_SCK_PB3_INP_RMP \ + GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP) +#define SPI0_SCK_PB3_OUT_RMP \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP) + +/* SPI1_MISO */ +#define SPI1_MISO_PB14_INP \ + GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP) +#define SPI1_MISO_PB14_OUT \ + GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP) + +/* SPI1_MOSI */ +#define SPI1_MOSI_PB15_INP \ + GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) +#define SPI1_MOSI_PB15_OUT \ + GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) + +/* SPI1_NSS */ +#define SPI1_NSS_PB12_INP \ + GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) +#define SPI1_NSS_PB12_OUT \ + GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) + +/* SPI1_SCK */ +#define SPI1_SCK_PB13_INP \ + GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP) +#define SPI1_SCK_PB13_OUT \ + GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) + +/* SPI2_MISO */ +#define SPI2_MISO_PB4_INP_NORMP \ + GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI2_NORMP) +#define SPI2_MISO_PB4_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI2_NORMP) +#define SPI2_MISO_PC11_INP_RMP \ + GD32_PINMUX_AFIO('C', 11, GPIO_IN, SPI2_RMP) +#define SPI2_MISO_PC11_OUT_RMP \ + GD32_PINMUX_AFIO('C', 11, ALTERNATE, SPI2_RMP) + +/* SPI2_MOSI */ +#define SPI2_MOSI_PB5_INP_NORMP \ + GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI2_NORMP) +#define SPI2_MOSI_PB5_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI2_NORMP) +#define SPI2_MOSI_PC12_INP_RMP \ + GD32_PINMUX_AFIO('C', 12, GPIO_IN, SPI2_RMP) +#define SPI2_MOSI_PC12_OUT_RMP \ + GD32_PINMUX_AFIO('C', 12, ALTERNATE, SPI2_RMP) + +/* SPI2_NSS */ +#define SPI2_NSS_PA15_INP_NORMP \ + GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI2_NORMP) +#define SPI2_NSS_PA15_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI2_NORMP) +#define SPI2_NSS_PA4_INP_RMP \ + GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI2_RMP) +#define SPI2_NSS_PA4_OUT_RMP \ + GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI2_RMP) + +/* SPI2_SCK */ +#define SPI2_SCK_PB3_INP_NORMP \ + GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI2_NORMP) +#define SPI2_SCK_PB3_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI2_NORMP) +#define SPI2_SCK_PC10_INP_RMP \ + GD32_PINMUX_AFIO('C', 10, GPIO_IN, SPI2_RMP) +#define SPI2_SCK_PC10_OUT_RMP \ + GD32_PINMUX_AFIO('C', 10, ALTERNATE, SPI2_RMP) + +/* TIMER0_BKIN */ +#define TIMER0_BKIN_PB12_NORMP \ + GD32_PINMUX_AFIO('B', 12, GPIO_IN, TIMER0_NORMP) +#define TIMER0_BKIN_PA6_PRMP \ + GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER0_PRMP) + +/* TIMER0_CH0 */ +#define TIMER0_CH0_PA8_INP_NORMP \ + GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH0_PA8_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH0_PA8_INP_PRMP \ + GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH0_PA8_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_CH0_ON */ +#define TIMER0_CH0_ON_PB13_INP_NORMP \ + GD32_PINMUX_AFIO('B', 13, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH0_ON_PB13_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 13, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH0_ON_PA7_INP_PRMP \ + GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH0_ON_PA7_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_CH1 */ +#define TIMER0_CH1_PA9_INP_NORMP \ + GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH1_PA9_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH1_PA9_INP_PRMP \ + GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH1_PA9_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_CH1_ON */ +#define TIMER0_CH1_ON_PB14_INP_NORMP \ + GD32_PINMUX_AFIO('B', 14, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH1_ON_PB14_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 14, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH1_ON_PB0_INP_PRMP \ + GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH1_ON_PB0_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_CH2 */ +#define TIMER0_CH2_PA10_INP_NORMP \ + GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH2_PA10_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH2_PA10_INP_PRMP \ + GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH2_PA10_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_CH2_ON */ +#define TIMER0_CH2_ON_PB15_NORMP \ + GD32_PINMUX_AFIO('B', 15, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH2_ON_PB1_PRMP \ + GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_CH3 */ +#define TIMER0_CH3_PA11_INP_NORMP \ + GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH3_PA11_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH3_PA11_INP_PRMP \ + GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH3_PA11_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_ETI */ +#define TIMER0_ETI_PA12_NORMP \ + GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP) +#define TIMER0_ETI_PA12_PRMP \ + GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP) + +/* TIMER10_CH0 */ +#define TIMER10_CH0_PB9_INP \ + GD32_PINMUX_AFIO('B', 9, GPIO_IN, NORMP) +#define TIMER10_CH0_PB9_OUT \ + GD32_PINMUX_AFIO('B', 9, ALTERNATE, NORMP) + +/* TIMER11_CH0 */ +#define TIMER11_CH0_PB14_INP \ + GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP) +#define TIMER11_CH0_PB14_OUT \ + GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP) + +/* TIMER11_CH11 */ +#define TIMER11_CH11_PB15_INP \ + GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) +#define TIMER11_CH11_PB15_OUT \ + GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) + +/* TIMER12_CH0 */ +#define TIMER12_CH0_PA6_INP \ + GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP) +#define TIMER12_CH0_PA6_OUT \ + GD32_PINMUX_AFIO('A', 6, ALTERNATE, NORMP) + +/* TIMER13_CH0 */ +#define TIMER13_CH0_PA7_INP \ + GD32_PINMUX_AFIO('A', 7, GPIO_IN, NORMP) +#define TIMER13_CH0_PA7_OUT \ + GD32_PINMUX_AFIO('A', 7, ALTERNATE, NORMP) + +/* TIMER1_CH0_ETI */ +#define TIMER1_CH0_ETI_PA0 \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) + +/* TIMER1_CH1 */ +#define TIMER1_CH1_PA1_INP_NORMP \ + GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_NORMP) +#define TIMER1_CH1_PA1_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_NORMP) +#define TIMER1_CH1_PA1_INP_PRMP2 \ + GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_PRMP2) +#define TIMER1_CH1_PA1_OUT_PRMP2 \ + GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_PRMP2) +#define TIMER1_CH1_PB3_INP_PRMP1 \ + GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_PRMP1) +#define TIMER1_CH1_PB3_OUT_PRMP1 \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_PRMP1) +#define TIMER1_CH1_PB3_INP_FRMP \ + GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_FRMP) +#define TIMER1_CH1_PB3_OUT_FRMP \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_FRMP) + +/* TIMER1_CH2 */ +#define TIMER1_CH2_PA2_INP_NORMP \ + GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_NORMP) +#define TIMER1_CH2_PA2_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_NORMP) +#define TIMER1_CH2_PA2_INP_PRMP1 \ + GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_PRMP1) +#define TIMER1_CH2_PA2_OUT_PRMP1 \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_PRMP1) +#define TIMER1_CH2_PB10_INP_PRMP2 \ + GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_PRMP2) +#define TIMER1_CH2_PB10_OUT_PRMP2 \ + GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_PRMP2) +#define TIMER1_CH2_PB10_INP_FRMP \ + GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_FRMP) +#define TIMER1_CH2_PB10_OUT_FRMP \ + GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_FRMP) + +/* TIMER1_CH3 */ +#define TIMER1_CH3_PA3_INP_NORMP \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_NORMP) +#define TIMER1_CH3_PA3_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_NORMP) +#define TIMER1_CH3_PA3_INP_PRMP1 \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_PRMP1) +#define TIMER1_CH3_PA3_OUT_PRMP1 \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_PRMP1) +#define TIMER1_CH3_PB11_INP_PRMP2 \ + GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_PRMP2) +#define TIMER1_CH3_PB11_OUT_PRMP2 \ + GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_PRMP2) +#define TIMER1_CH3_PB11_INP_FRMP \ + GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_FRMP) +#define TIMER1_CH3_PB11_OUT_FRMP \ + GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_FRMP) + +/* TIMER2_CH0 */ +#define TIMER2_CH0_PA6_INP_NORMP \ + GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP) +#define TIMER2_CH0_PA6_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP) +#define TIMER2_CH0_PB4_INP_PRMP \ + GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP) +#define TIMER2_CH0_PB4_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP) +#define TIMER2_CH0_PC6_INP_FRMP \ + GD32_PINMUX_AFIO('C', 6, GPIO_IN, TIMER2_FRMP) +#define TIMER2_CH0_PC6_OUT_FRMP \ + GD32_PINMUX_AFIO('C', 6, ALTERNATE, TIMER2_FRMP) + +/* TIMER2_CH1 */ +#define TIMER2_CH1_PA7_INP_NORMP \ + GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP) +#define TIMER2_CH1_PA7_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP) +#define TIMER2_CH1_PB5_INP_PRMP \ + GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP) +#define TIMER2_CH1_PB5_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP) +#define TIMER2_CH1_PC7_INP_FRMP \ + GD32_PINMUX_AFIO('C', 7, GPIO_IN, TIMER2_FRMP) +#define TIMER2_CH1_PC7_OUT_FRMP \ + GD32_PINMUX_AFIO('C', 7, ALTERNATE, TIMER2_FRMP) + +/* TIMER2_CH2 */ +#define TIMER2_CH2_PB0_INP_NORMP \ + GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP) +#define TIMER2_CH2_PB0_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP) +#define TIMER2_CH2_PB0_INP_PRMP \ + GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP) +#define TIMER2_CH2_PB0_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP) +#define TIMER2_CH2_PC8_INP_FRMP \ + GD32_PINMUX_AFIO('C', 8, GPIO_IN, TIMER2_FRMP) +#define TIMER2_CH2_PC8_OUT_FRMP \ + GD32_PINMUX_AFIO('C', 8, ALTERNATE, TIMER2_FRMP) + +/* TIMER2_CH3 */ +#define TIMER2_CH3_PB1_INP_NORMP \ + GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP) +#define TIMER2_CH3_PB1_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP) +#define TIMER2_CH3_PB1_INP_PRMP \ + GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP) +#define TIMER2_CH3_PB1_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP) +#define TIMER2_CH3_PC9_INP_FRMP \ + GD32_PINMUX_AFIO('C', 9, GPIO_IN, TIMER2_FRMP) +#define TIMER2_CH3_PC9_OUT_FRMP \ + GD32_PINMUX_AFIO('C', 9, ALTERNATE, TIMER2_FRMP) + +/* TIMER2_ETI */ +#define TIMER2_ETI_PD2 \ + GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP) + +/* TIMER3_CH0 */ +#define TIMER3_CH0_PB6_INP_NORMP \ + GD32_PINMUX_AFIO('B', 6, GPIO_IN, TIMER3_NORMP) +#define TIMER3_CH0_PB6_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 6, ALTERNATE, TIMER3_NORMP) + +/* TIMER3_CH1 */ +#define TIMER3_CH1_PB7_INP_NORMP \ + GD32_PINMUX_AFIO('B', 7, GPIO_IN, TIMER3_NORMP) +#define TIMER3_CH1_PB7_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 7, ALTERNATE, TIMER3_NORMP) + +/* TIMER3_CH2 */ +#define TIMER3_CH2_PB8_INP_NORMP \ + GD32_PINMUX_AFIO('B', 8, GPIO_IN, TIMER3_NORMP) +#define TIMER3_CH2_PB8_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 8, ALTERNATE, TIMER3_NORMP) + +/* TIMER3_CH3 */ +#define TIMER3_CH3_PB9_INP_NORMP \ + GD32_PINMUX_AFIO('B', 9, GPIO_IN, TIMER3_NORMP) +#define TIMER3_CH3_PB9_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 9, ALTERNATE, TIMER3_NORMP) + +/* TIMER4_CH0 */ +#define TIMER4_CH0_PA0_INP \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) +#define TIMER4_CH0_PA0_OUT \ + GD32_PINMUX_AFIO('A', 0, ALTERNATE, NORMP) + +/* TIMER4_CH1 */ +#define TIMER4_CH1_PA1_INP \ + GD32_PINMUX_AFIO('A', 1, GPIO_IN, NORMP) +#define TIMER4_CH1_PA1_OUT \ + GD32_PINMUX_AFIO('A', 1, ALTERNATE, NORMP) + +/* TIMER4_CH2 */ +#define TIMER4_CH2_PA2_INP \ + GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP) +#define TIMER4_CH2_PA2_OUT \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP) + +/* TIMER4_CH3 */ +#define TIMER4_CH3_PA3_INP \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP) +#define TIMER4_CH3_PA3_OUT \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP) + +/* TIMER7_BKIN */ +#define TIMER7_BKIN_PA6 \ + GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP) + +/* TIMER7_CH0 */ +#define TIMER7_CH0_PC6_INP \ + GD32_PINMUX_AFIO('C', 6, GPIO_IN, NORMP) +#define TIMER7_CH0_PC6_OUT \ + GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP) + +/* TIMER7_CH0_ON */ +#define TIMER7_CH0_ON_PA7_INP \ + GD32_PINMUX_AFIO('A', 7, GPIO_IN, NORMP) +#define TIMER7_CH0_ON_PA7_OUT \ + GD32_PINMUX_AFIO('A', 7, ALTERNATE, NORMP) + +/* TIMER7_CH1 */ +#define TIMER7_CH1_PC7_INP \ + GD32_PINMUX_AFIO('C', 7, GPIO_IN, NORMP) +#define TIMER7_CH1_PC7_OUT \ + GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP) + +/* TIMER7_CH1_ON */ +#define TIMER7_CH1_ON_PB0_INP \ + GD32_PINMUX_AFIO('B', 0, GPIO_IN, NORMP) +#define TIMER7_CH1_ON_PB0_OUT \ + GD32_PINMUX_AFIO('B', 0, ALTERNATE, NORMP) + +/* TIMER7_CH2 */ +#define TIMER7_CH2_PC8_INP \ + GD32_PINMUX_AFIO('C', 8, GPIO_IN, NORMP) +#define TIMER7_CH2_PC8_OUT \ + GD32_PINMUX_AFIO('C', 8, ALTERNATE, NORMP) + +/* TIMER7_CH2_ON */ +#define TIMER7_CH2_ON_PB1 \ + GD32_PINMUX_AFIO('B', 1, ALTERNATE, NORMP) + +/* TIMER7_CH3 */ +#define TIMER7_CH3_PC9_INP \ + GD32_PINMUX_AFIO('C', 9, GPIO_IN, NORMP) +#define TIMER7_CH3_PC9_OUT \ + GD32_PINMUX_AFIO('C', 9, ALTERNATE, NORMP) + +/* TIMER7_ETI */ +#define TIMER7_ETI_PA0 \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) + +/* TIMER8_CH0 */ +#define TIMER8_CH0_PA2_INP \ + GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP) +#define TIMER8_CH0_PA2_OUT \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP) + +/* TIMER8_CH1 */ +#define TIMER8_CH1_PA3_INP \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP) +#define TIMER8_CH1_PA3_OUT \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP) + +/* TIMER9_CH0 */ +#define TIMER9_CH0_PB8_INP \ + GD32_PINMUX_AFIO('B', 8, GPIO_IN, NORMP) +#define TIMER9_CH0_PB8_OUT \ + GD32_PINMUX_AFIO('B', 8, ALTERNATE, NORMP) + +/* UART3_RX */ +#define UART3_RX_PC11 \ + GD32_PINMUX_AFIO('C', 11, GPIO_IN, NORMP) + +/* UART3_TX */ +#define UART3_TX_PC10 \ + GD32_PINMUX_AFIO('C', 10, ALTERNATE, NORMP) + +/* UART4_RX */ +#define UART4_RX_PD2 \ + GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP) + +/* UART4_TX */ +#define UART4_TX_PC12 \ + GD32_PINMUX_AFIO('C', 12, ALTERNATE, NORMP) + +/* USART0_CK */ +#define USART0_CK_PA8 \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) + +/* USART0_CTS */ +#define USART0_CTS_PA11 \ + GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) + +/* USART0_RTS */ +#define USART0_RTS_PA12 \ + GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) + +/* USART0_RX */ +#define USART0_RX_PA10_NORMP \ + GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP) +#define USART0_RX_PB7_RMP \ + GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP) + +/* USART0_TX */ +#define USART0_TX_PA9_NORMP \ + GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP) +#define USART0_TX_PB6_RMP \ + GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP) + +/* USART1_CK */ +#define USART1_CK_PA4_NORMP \ + GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP) + +/* USART1_CTS */ +#define USART1_CTS_PA0_NORMP \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP) + +/* USART1_RTS */ +#define USART1_RTS_PA1_NORMP \ + GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP) + +/* USART1_RX */ +#define USART1_RX_PA3_NORMP \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP) + +/* USART1_TX */ +#define USART1_TX_PA2_NORMP \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP) + +/* USART2_CK */ +#define USART2_CK_PB12_NORMP \ + GD32_PINMUX_AFIO('B', 12, ALTERNATE, USART2_NORMP) +#define USART2_CK_PC12_PRMP \ + GD32_PINMUX_AFIO('C', 12, ALTERNATE, USART2_PRMP) + +/* USART2_CTS */ +#define USART2_CTS_PB13_NORMP \ + GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_NORMP) +#define USART2_CTS_PB13_PRMP \ + GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_PRMP) + +/* USART2_RTS */ +#define USART2_RTS_PB14_NORMP \ + GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_NORMP) +#define USART2_RTS_PB14_PRMP \ + GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_PRMP) + +/* USART2_RX */ +#define USART2_RX_PB11_NORMP \ + GD32_PINMUX_AFIO('B', 11, GPIO_IN, USART2_NORMP) +#define USART2_RX_PC11_PRMP \ + GD32_PINMUX_AFIO('C', 11, GPIO_IN, USART2_PRMP) + +/* USART2_TX */ +#define USART2_TX_PB10_NORMP \ + GD32_PINMUX_AFIO('B', 10, ALTERNATE, USART2_NORMP) +#define USART2_TX_PC10_PRMP \ + GD32_PINMUX_AFIO('C', 10, ALTERNATE, USART2_PRMP) + +/* USBFS_DM */ +#define USBFS_DM_PA11_INP \ + GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) +#define USBFS_DM_PA11_OUT \ + GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP) + +/* USBFS_DP */ +#define USBFS_DP_PA12_INP \ + GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP) +#define USBFS_DP_PA12_OUT \ + GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) + +/* USBFS_ID */ +#define USBFS_ID_PA10_INP \ + GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP) +#define USBFS_ID_PA10_OUT \ + GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP) + +/* USBFS_SOF */ +#define USBFS_SOF_PA8 \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) + +/* USBFS_VBUS */ +#define USBFS_VBUS_PA9 \ + GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP) + +/* WKUP */ +#define WKUP_PA0 \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) diff --git a/include/dt-bindings/pinctrl/gd32e103t(b-8)xx-pinctrl.h b/include/dt-bindings/pinctrl/gd32e103t(b-8)xx-pinctrl.h new file mode 100644 index 00000000..1757434e --- /dev/null +++ b/include/dt-bindings/pinctrl/gd32e103t(b-8)xx-pinctrl.h @@ -0,0 +1,423 @@ +/* + * Autogenerated file + * + * SPDX-License-Identifier: Apache 2.0 + */ + +#include "gd32e103xx-afio.h" + +/* ADC01_IN0 */ +#define ADC01_IN0_PA0 \ + GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) + +/* ADC01_IN1 */ +#define ADC01_IN1_PA1 \ + GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) + +/* ADC01_IN2 */ +#define ADC01_IN2_PA2 \ + GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) + +/* ADC01_IN3 */ +#define ADC01_IN3_PA3 \ + GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) + +/* ADC01_IN4 */ +#define ADC01_IN4_PA4 \ + GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) + +/* ADC01_IN5 */ +#define ADC01_IN5_PA5 \ + GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) + +/* ADC01_IN6 */ +#define ADC01_IN6_PA6 \ + GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) + +/* ADC01_IN7 */ +#define ADC01_IN7_PA7 \ + GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) + +/* ADC01_IN8 */ +#define ADC01_IN8_PB0 \ + GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) + +/* ADC01_IN9 */ +#define ADC01_IN9_PB1 \ + GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) + +/* ANALOG */ +#define ANALOG_PA0 \ + GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) +#define ANALOG_PA1 \ + GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) +#define ANALOG_PA10 \ + GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP) +#define ANALOG_PA11 \ + GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP) +#define ANALOG_PA12 \ + GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP) +#define ANALOG_PA13 \ + GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP) +#define ANALOG_PA14 \ + GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP) +#define ANALOG_PA15 \ + GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP) +#define ANALOG_PA2 \ + GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) +#define ANALOG_PA3 \ + GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) +#define ANALOG_PA4 \ + GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) +#define ANALOG_PA5 \ + GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) +#define ANALOG_PA6 \ + GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) +#define ANALOG_PA7 \ + GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) +#define ANALOG_PA8 \ + GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP) +#define ANALOG_PA9 \ + GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP) +#define ANALOG_PB0 \ + GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) +#define ANALOG_PB1 \ + GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) +#define ANALOG_PB2 \ + GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP) +#define ANALOG_PB3 \ + GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP) +#define ANALOG_PB4 \ + GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP) +#define ANALOG_PB5 \ + GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP) +#define ANALOG_PB6 \ + GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP) +#define ANALOG_PB7 \ + GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP) +#define ANALOG_PD0 \ + GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP) +#define ANALOG_PD1 \ + GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP) + +/* CK_OUT0 */ +#define CK_OUT0_PA8 \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) + +/* CTC_SYNC */ +#define CTC_SYNC_PA8 \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) + +/* DAC_OUT0 */ +#define DAC_OUT0_PA4 \ + GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) + +/* DAC_OUT1 */ +#define DAC_OUT1_PA5 \ + GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) + +/* I2C0_SCL */ +#define I2C0_SCL_PB6_NORMP \ + GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP) + +/* I2C0_SDA */ +#define I2C0_SDA_PB7_NORMP \ + GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP) + +/* I2C0_SMBA */ +#define I2C0_SMBA_PB5 \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP) + +/* I2C0_TXFRAME */ +#define I2C0_TXFRAME_PB4 \ + GD32_PINMUX_AFIO('B', 4, ALTERNATE, NORMP) + +/* SPI0_IO2 */ +#define SPI0_IO2_PA2_NORMP \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, SPI0_NORMP) +#define SPI0_IO2_PB6_RMP \ + GD32_PINMUX_AFIO('B', 6, ALTERNATE, SPI0_RMP) + +/* SPI0_IO3 */ +#define SPI0_IO3_PA3_NORMP \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, SPI0_NORMP) +#define SPI0_IO3_PB7_RMP \ + GD32_PINMUX_AFIO('B', 7, ALTERNATE, SPI0_RMP) + +/* SPI0_MISO */ +#define SPI0_MISO_PA6_INP_NORMP \ + GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP) +#define SPI0_MISO_PA6_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP) +#define SPI0_MISO_PB4_INP_RMP \ + GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP) +#define SPI0_MISO_PB4_OUT_RMP \ + GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP) + +/* SPI0_MOSI */ +#define SPI0_MOSI_PA7_INP_NORMP \ + GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP) +#define SPI0_MOSI_PA7_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP) +#define SPI0_MOSI_PB5_INP_RMP \ + GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP) +#define SPI0_MOSI_PB5_OUT_RMP \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP) + +/* SPI0_NSS */ +#define SPI0_NSS_PA4_INP_NORMP \ + GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP) +#define SPI0_NSS_PA4_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP) +#define SPI0_NSS_PA15_INP_RMP \ + GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP) +#define SPI0_NSS_PA15_OUT_RMP \ + GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP) + +/* SPI0_SCK */ +#define SPI0_SCK_PA5_INP_NORMP \ + GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP) +#define SPI0_SCK_PA5_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP) +#define SPI0_SCK_PB3_INP_RMP \ + GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP) +#define SPI0_SCK_PB3_OUT_RMP \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP) + +/* TIMER0_CH0 */ +#define TIMER0_CH0_PA8_INP_NORMP \ + GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH0_PA8_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH0_PA8_INP_PRMP \ + GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH0_PA8_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_CH1 */ +#define TIMER0_CH1_PA9_INP_NORMP \ + GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH1_PA9_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH1_PA9_INP_PRMP \ + GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH1_PA9_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_CH2 */ +#define TIMER0_CH2_PA10_INP_NORMP \ + GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH2_PA10_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH2_PA10_INP_PRMP \ + GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH2_PA10_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_CH3 */ +#define TIMER0_CH3_PA11_INP_NORMP \ + GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH3_PA11_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH3_PA11_INP_PRMP \ + GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH3_PA11_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP) + +/* TIMER0_ETI */ +#define TIMER0_ETI_PA12_NORMP \ + GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP) +#define TIMER0_ETI_PA12_PRMP \ + GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP) + +/* TIMER1_CH0_ETI */ +#define TIMER1_CH0_ETI_PA0 \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) + +/* TIMER1_CH1 */ +#define TIMER1_CH1_PA1_INP_NORMP \ + GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_NORMP) +#define TIMER1_CH1_PA1_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_NORMP) +#define TIMER1_CH1_PA1_INP_PRMP2 \ + GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_PRMP2) +#define TIMER1_CH1_PA1_OUT_PRMP2 \ + GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_PRMP2) +#define TIMER1_CH1_PB3_INP_PRMP1 \ + GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_PRMP1) +#define TIMER1_CH1_PB3_OUT_PRMP1 \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_PRMP1) +#define TIMER1_CH1_PB3_INP_FRMP \ + GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_FRMP) +#define TIMER1_CH1_PB3_OUT_FRMP \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_FRMP) + +/* TIMER1_CH2 */ +#define TIMER1_CH2_PA2_INP_NORMP \ + GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_NORMP) +#define TIMER1_CH2_PA2_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_NORMP) +#define TIMER1_CH2_PA2_INP_PRMP1 \ + GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_PRMP1) +#define TIMER1_CH2_PA2_OUT_PRMP1 \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_PRMP1) + +/* TIMER1_CH3 */ +#define TIMER1_CH3_PA3_INP_NORMP \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_NORMP) +#define TIMER1_CH3_PA3_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_NORMP) +#define TIMER1_CH3_PA3_INP_PRMP1 \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_PRMP1) +#define TIMER1_CH3_PA3_OUT_PRMP1 \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_PRMP1) + +/* TIMER2_CH0 */ +#define TIMER2_CH0_PA6_INP_NORMP \ + GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP) +#define TIMER2_CH0_PA6_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP) +#define TIMER2_CH0_PB4_INP_PRMP \ + GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP) +#define TIMER2_CH0_PB4_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP) + +/* TIMER2_CH1 */ +#define TIMER2_CH1_PA7_INP_NORMP \ + GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP) +#define TIMER2_CH1_PA7_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP) +#define TIMER2_CH1_PB5_INP_PRMP \ + GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP) +#define TIMER2_CH1_PB5_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP) + +/* TIMER2_CH2 */ +#define TIMER2_CH2_PB0_INP_NORMP \ + GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP) +#define TIMER2_CH2_PB0_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP) +#define TIMER2_CH2_PB0_INP_PRMP \ + GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP) +#define TIMER2_CH2_PB0_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP) + +/* TIMER2_CH3 */ +#define TIMER2_CH3_PB1_INP_NORMP \ + GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP) +#define TIMER2_CH3_PB1_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP) +#define TIMER2_CH3_PB1_INP_PRMP \ + GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP) +#define TIMER2_CH3_PB1_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP) + +/* TIMER3_CH0 */ +#define TIMER3_CH0_PB6_INP_NORMP \ + GD32_PINMUX_AFIO('B', 6, GPIO_IN, TIMER3_NORMP) +#define TIMER3_CH0_PB6_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 6, ALTERNATE, TIMER3_NORMP) + +/* TIMER3_CH1 */ +#define TIMER3_CH1_PB7_INP_NORMP \ + GD32_PINMUX_AFIO('B', 7, GPIO_IN, TIMER3_NORMP) +#define TIMER3_CH1_PB7_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 7, ALTERNATE, TIMER3_NORMP) + +/* TIMER4_CH0 */ +#define TIMER4_CH0_PA0_INP \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) +#define TIMER4_CH0_PA0_OUT \ + GD32_PINMUX_AFIO('A', 0, ALTERNATE, NORMP) + +/* TIMER4_CH1 */ +#define TIMER4_CH1_PA1_INP \ + GD32_PINMUX_AFIO('A', 1, GPIO_IN, NORMP) +#define TIMER4_CH1_PA1_OUT \ + GD32_PINMUX_AFIO('A', 1, ALTERNATE, NORMP) + +/* TIMER4_CH2 */ +#define TIMER4_CH2_PA2_INP \ + GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP) +#define TIMER4_CH2_PA2_OUT \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP) + +/* TIMER4_CH3 */ +#define TIMER4_CH3_PA3_INP \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP) +#define TIMER4_CH3_PA3_OUT \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP) + +/* USART0_CK */ +#define USART0_CK_PA8 \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) + +/* USART0_CTS */ +#define USART0_CTS_PA11 \ + GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) + +/* USART0_RTS */ +#define USART0_RTS_PA12 \ + GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) + +/* USART0_RX */ +#define USART0_RX_PA10_NORMP \ + GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP) +#define USART0_RX_PB7_RMP \ + GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP) + +/* USART0_TX */ +#define USART0_TX_PA9_NORMP \ + GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP) +#define USART0_TX_PB6_RMP \ + GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP) + +/* USART1_CK */ +#define USART1_CK_PA4_NORMP \ + GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP) + +/* USART1_CTS */ +#define USART1_CTS_PA0_NORMP \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP) + +/* USART1_RTS */ +#define USART1_RTS_PA1_NORMP \ + GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP) + +/* USART1_RX */ +#define USART1_RX_PA3_NORMP \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP) + +/* USART1_TX */ +#define USART1_TX_PA2_NORMP \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP) + +/* USBFS_DM */ +#define USBFS_DM_PA11_INP \ + GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) +#define USBFS_DM_PA11_OUT \ + GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP) + +/* USBFS_DP */ +#define USBFS_DP_PA12_INP \ + GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP) +#define USBFS_DP_PA12_OUT \ + GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) + +/* USBFS_ID */ +#define USBFS_ID_PA10_INP \ + GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP) +#define USBFS_ID_PA10_OUT \ + GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP) + +/* USBFS_SOF */ +#define USBFS_SOF_PA8 \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) + +/* USBFS_VBUS */ +#define USBFS_VBUS_PA9 \ + GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP) + +/* WKUP */ +#define WKUP_PA0 \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) diff --git a/include/dt-bindings/pinctrl/gd32e103v(b-8)xx-pinctrl.h b/include/dt-bindings/pinctrl/gd32e103v(b-8)xx-pinctrl.h new file mode 100644 index 00000000..5cd5cab5 --- /dev/null +++ b/include/dt-bindings/pinctrl/gd32e103v(b-8)xx-pinctrl.h @@ -0,0 +1,1133 @@ +/* + * Autogenerated file + * + * SPDX-License-Identifier: Apache 2.0 + */ + +#include "gd32e103xx-afio.h" + +/* ADC01_IN0 */ +#define ADC01_IN0_PA0 \ + GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) + +/* ADC01_IN1 */ +#define ADC01_IN1_PA1 \ + GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) + +/* ADC01_IN10 */ +#define ADC01_IN10_PC0 \ + GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP) + +/* ADC01_IN11 */ +#define ADC01_IN11_PC1 \ + GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP) + +/* ADC01_IN12 */ +#define ADC01_IN12_PC2 \ + GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP) + +/* ADC01_IN13 */ +#define ADC01_IN13_PC3 \ + GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP) + +/* ADC01_IN14 */ +#define ADC01_IN14_PC4 \ + GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP) + +/* ADC01_IN15 */ +#define ADC01_IN15_PC5 \ + GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP) + +/* ADC01_IN2 */ +#define ADC01_IN2_PA2 \ + GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) + +/* ADC01_IN3 */ +#define ADC01_IN3_PA3 \ + GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) + +/* ADC01_IN4 */ +#define ADC01_IN4_PA4 \ + GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) + +/* ADC01_IN5 */ +#define ADC01_IN5_PA5 \ + GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) + +/* ADC01_IN6 */ +#define ADC01_IN6_PA6 \ + GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) + +/* ADC01_IN7 */ +#define ADC01_IN7_PA7 \ + GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) + +/* ADC01_IN8 */ +#define ADC01_IN8_PB0 \ + GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) + +/* ADC01_IN9 */ +#define ADC01_IN9_PB1 \ + GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) + +/* ANALOG */ +#define ANALOG_PA0 \ + GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP) +#define ANALOG_PA1 \ + GD32_PINMUX_AFIO('A', 1, ANALOG, NORMP) +#define ANALOG_PA10 \ + GD32_PINMUX_AFIO('A', 10, ANALOG, NORMP) +#define ANALOG_PA11 \ + GD32_PINMUX_AFIO('A', 11, ANALOG, NORMP) +#define ANALOG_PA12 \ + GD32_PINMUX_AFIO('A', 12, ANALOG, NORMP) +#define ANALOG_PA13 \ + GD32_PINMUX_AFIO('A', 13, ANALOG, NORMP) +#define ANALOG_PA14 \ + GD32_PINMUX_AFIO('A', 14, ANALOG, NORMP) +#define ANALOG_PA15 \ + GD32_PINMUX_AFIO('A', 15, ANALOG, NORMP) +#define ANALOG_PA2 \ + GD32_PINMUX_AFIO('A', 2, ANALOG, NORMP) +#define ANALOG_PA3 \ + GD32_PINMUX_AFIO('A', 3, ANALOG, NORMP) +#define ANALOG_PA4 \ + GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) +#define ANALOG_PA5 \ + GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) +#define ANALOG_PA6 \ + GD32_PINMUX_AFIO('A', 6, ANALOG, NORMP) +#define ANALOG_PA7 \ + GD32_PINMUX_AFIO('A', 7, ANALOG, NORMP) +#define ANALOG_PA8 \ + GD32_PINMUX_AFIO('A', 8, ANALOG, NORMP) +#define ANALOG_PA9 \ + GD32_PINMUX_AFIO('A', 9, ANALOG, NORMP) +#define ANALOG_PB0 \ + GD32_PINMUX_AFIO('B', 0, ANALOG, NORMP) +#define ANALOG_PB1 \ + GD32_PINMUX_AFIO('B', 1, ANALOG, NORMP) +#define ANALOG_PB10 \ + GD32_PINMUX_AFIO('B', 10, ANALOG, NORMP) +#define ANALOG_PB11 \ + GD32_PINMUX_AFIO('B', 11, ANALOG, NORMP) +#define ANALOG_PB12 \ + GD32_PINMUX_AFIO('B', 12, ANALOG, NORMP) +#define ANALOG_PB13 \ + GD32_PINMUX_AFIO('B', 13, ANALOG, NORMP) +#define ANALOG_PB14 \ + GD32_PINMUX_AFIO('B', 14, ANALOG, NORMP) +#define ANALOG_PB15 \ + GD32_PINMUX_AFIO('B', 15, ANALOG, NORMP) +#define ANALOG_PB2 \ + GD32_PINMUX_AFIO('B', 2, ANALOG, NORMP) +#define ANALOG_PB3 \ + GD32_PINMUX_AFIO('B', 3, ANALOG, NORMP) +#define ANALOG_PB4 \ + GD32_PINMUX_AFIO('B', 4, ANALOG, NORMP) +#define ANALOG_PB5 \ + GD32_PINMUX_AFIO('B', 5, ANALOG, NORMP) +#define ANALOG_PB6 \ + GD32_PINMUX_AFIO('B', 6, ANALOG, NORMP) +#define ANALOG_PB7 \ + GD32_PINMUX_AFIO('B', 7, ANALOG, NORMP) +#define ANALOG_PB8 \ + GD32_PINMUX_AFIO('B', 8, ANALOG, NORMP) +#define ANALOG_PB9 \ + GD32_PINMUX_AFIO('B', 9, ANALOG, NORMP) +#define ANALOG_PC0 \ + GD32_PINMUX_AFIO('C', 0, ANALOG, NORMP) +#define ANALOG_PC1 \ + GD32_PINMUX_AFIO('C', 1, ANALOG, NORMP) +#define ANALOG_PC10 \ + GD32_PINMUX_AFIO('C', 10, ANALOG, NORMP) +#define ANALOG_PC11 \ + GD32_PINMUX_AFIO('C', 11, ANALOG, NORMP) +#define ANALOG_PC12 \ + GD32_PINMUX_AFIO('C', 12, ANALOG, NORMP) +#define ANALOG_PC13 \ + GD32_PINMUX_AFIO('C', 13, ANALOG, NORMP) +#define ANALOG_PC14 \ + GD32_PINMUX_AFIO('C', 14, ANALOG, NORMP) +#define ANALOG_PC15 \ + GD32_PINMUX_AFIO('C', 15, ANALOG, NORMP) +#define ANALOG_PC2 \ + GD32_PINMUX_AFIO('C', 2, ANALOG, NORMP) +#define ANALOG_PC3 \ + GD32_PINMUX_AFIO('C', 3, ANALOG, NORMP) +#define ANALOG_PC4 \ + GD32_PINMUX_AFIO('C', 4, ANALOG, NORMP) +#define ANALOG_PC5 \ + GD32_PINMUX_AFIO('C', 5, ANALOG, NORMP) +#define ANALOG_PC6 \ + GD32_PINMUX_AFIO('C', 6, ANALOG, NORMP) +#define ANALOG_PC7 \ + GD32_PINMUX_AFIO('C', 7, ANALOG, NORMP) +#define ANALOG_PC8 \ + GD32_PINMUX_AFIO('C', 8, ANALOG, NORMP) +#define ANALOG_PC9 \ + GD32_PINMUX_AFIO('C', 9, ANALOG, NORMP) +#define ANALOG_PD0 \ + GD32_PINMUX_AFIO('D', 0, ANALOG, NORMP) +#define ANALOG_PD1 \ + GD32_PINMUX_AFIO('D', 1, ANALOG, NORMP) +#define ANALOG_PD10 \ + GD32_PINMUX_AFIO('D', 10, ANALOG, NORMP) +#define ANALOG_PD11 \ + GD32_PINMUX_AFIO('D', 11, ANALOG, NORMP) +#define ANALOG_PD12 \ + GD32_PINMUX_AFIO('D', 12, ANALOG, NORMP) +#define ANALOG_PD13 \ + GD32_PINMUX_AFIO('D', 13, ANALOG, NORMP) +#define ANALOG_PD14 \ + GD32_PINMUX_AFIO('D', 14, ANALOG, NORMP) +#define ANALOG_PD15 \ + GD32_PINMUX_AFIO('D', 15, ANALOG, NORMP) +#define ANALOG_PD2 \ + GD32_PINMUX_AFIO('D', 2, ANALOG, NORMP) +#define ANALOG_PD3 \ + GD32_PINMUX_AFIO('D', 3, ANALOG, NORMP) +#define ANALOG_PD4 \ + GD32_PINMUX_AFIO('D', 4, ANALOG, NORMP) +#define ANALOG_PD5 \ + GD32_PINMUX_AFIO('D', 5, ANALOG, NORMP) +#define ANALOG_PD6 \ + GD32_PINMUX_AFIO('D', 6, ANALOG, NORMP) +#define ANALOG_PD7 \ + GD32_PINMUX_AFIO('D', 7, ANALOG, NORMP) +#define ANALOG_PD8 \ + GD32_PINMUX_AFIO('D', 8, ANALOG, NORMP) +#define ANALOG_PD9 \ + GD32_PINMUX_AFIO('D', 9, ANALOG, NORMP) +#define ANALOG_PE0 \ + GD32_PINMUX_AFIO('E', 0, ANALOG, NORMP) +#define ANALOG_PE1 \ + GD32_PINMUX_AFIO('E', 1, ANALOG, NORMP) +#define ANALOG_PE10 \ + GD32_PINMUX_AFIO('E', 10, ANALOG, NORMP) +#define ANALOG_PE11 \ + GD32_PINMUX_AFIO('E', 11, ANALOG, NORMP) +#define ANALOG_PE12 \ + GD32_PINMUX_AFIO('E', 12, ANALOG, NORMP) +#define ANALOG_PE13 \ + GD32_PINMUX_AFIO('E', 13, ANALOG, NORMP) +#define ANALOG_PE14 \ + GD32_PINMUX_AFIO('E', 14, ANALOG, NORMP) +#define ANALOG_PE15 \ + GD32_PINMUX_AFIO('E', 15, ANALOG, NORMP) +#define ANALOG_PE2 \ + GD32_PINMUX_AFIO('E', 2, ANALOG, NORMP) +#define ANALOG_PE3 \ + GD32_PINMUX_AFIO('E', 3, ANALOG, NORMP) +#define ANALOG_PE4 \ + GD32_PINMUX_AFIO('E', 4, ANALOG, NORMP) +#define ANALOG_PE5 \ + GD32_PINMUX_AFIO('E', 5, ANALOG, NORMP) +#define ANALOG_PE6 \ + GD32_PINMUX_AFIO('E', 6, ANALOG, NORMP) +#define ANALOG_PE7 \ + GD32_PINMUX_AFIO('E', 7, ANALOG, NORMP) +#define ANALOG_PE8 \ + GD32_PINMUX_AFIO('E', 8, ANALOG, NORMP) +#define ANALOG_PE9 \ + GD32_PINMUX_AFIO('E', 9, ANALOG, NORMP) + +/* CK_OUT0 */ +#define CK_OUT0_PA8 \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) + +/* CTC_SYNC */ +#define CTC_SYNC_PA8 \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) + +/* DAC_OUT0 */ +#define DAC_OUT0_PA4 \ + GD32_PINMUX_AFIO('A', 4, ANALOG, NORMP) + +/* DAC_OUT1 */ +#define DAC_OUT1_PA5 \ + GD32_PINMUX_AFIO('A', 5, ANALOG, NORMP) + +/* EXMC_A16 */ +#define EXMC_A16_PD11 \ + GD32_PINMUX_AFIO('D', 11, ALTERNATE, NORMP) + +/* EXMC_A17 */ +#define EXMC_A17_PD12 \ + GD32_PINMUX_AFIO('D', 12, ALTERNATE, NORMP) + +/* EXMC_A18 */ +#define EXMC_A18_PD13 \ + GD32_PINMUX_AFIO('D', 13, ALTERNATE, NORMP) + +/* EXMC_A19 */ +#define EXMC_A19_PE3 \ + GD32_PINMUX_AFIO('E', 3, ALTERNATE, NORMP) + +/* EXMC_A20 */ +#define EXMC_A20_PE4 \ + GD32_PINMUX_AFIO('E', 4, ALTERNATE, NORMP) + +/* EXMC_A21 */ +#define EXMC_A21_PE5 \ + GD32_PINMUX_AFIO('E', 5, ALTERNATE, NORMP) + +/* EXMC_A22 */ +#define EXMC_A22_PE6 \ + GD32_PINMUX_AFIO('E', 6, ALTERNATE, NORMP) + +/* EXMC_A23 */ +#define EXMC_A23_PE2 \ + GD32_PINMUX_AFIO('E', 2, ALTERNATE, NORMP) + +/* EXMC_CLK */ +#define EXMC_CLK_PD3 \ + GD32_PINMUX_AFIO('D', 3, ALTERNATE, NORMP) + +/* EXMC_D0 */ +#define EXMC_D0_PD14 \ + GD32_PINMUX_AFIO('D', 14, ALTERNATE, NORMP) + +/* EXMC_D1 */ +#define EXMC_D1_PD15 \ + GD32_PINMUX_AFIO('D', 15, ALTERNATE, NORMP) + +/* EXMC_D10 */ +#define EXMC_D10_PE13 \ + GD32_PINMUX_AFIO('E', 13, ALTERNATE, NORMP) + +/* EXMC_D11 */ +#define EXMC_D11_PE14 \ + GD32_PINMUX_AFIO('E', 14, ALTERNATE, NORMP) + +/* EXMC_D12 */ +#define EXMC_D12_PE15 \ + GD32_PINMUX_AFIO('E', 15, ALTERNATE, NORMP) + +/* EXMC_D13 */ +#define EXMC_D13_PD8 \ + GD32_PINMUX_AFIO('D', 8, ALTERNATE, NORMP) + +/* EXMC_D14 */ +#define EXMC_D14_PD9 \ + GD32_PINMUX_AFIO('D', 9, ALTERNATE, NORMP) + +/* EXMC_D15 */ +#define EXMC_D15_PD10 \ + GD32_PINMUX_AFIO('D', 10, ALTERNATE, NORMP) + +/* EXMC_D2 */ +#define EXMC_D2_PD0 \ + GD32_PINMUX_AFIO('D', 0, ALTERNATE, NORMP) + +/* EXMC_D3 */ +#define EXMC_D3_PD1 \ + GD32_PINMUX_AFIO('D', 1, ALTERNATE, NORMP) + +/* EXMC_D4 */ +#define EXMC_D4_PE7 \ + GD32_PINMUX_AFIO('E', 7, ALTERNATE, NORMP) + +/* EXMC_D5 */ +#define EXMC_D5_PE8 \ + GD32_PINMUX_AFIO('E', 8, ALTERNATE, NORMP) + +/* EXMC_D6 */ +#define EXMC_D6_PE9 \ + GD32_PINMUX_AFIO('E', 9, ALTERNATE, NORMP) + +/* EXMC_D7 */ +#define EXMC_D7_PE10 \ + GD32_PINMUX_AFIO('E', 10, ALTERNATE, NORMP) + +/* EXMC_D8 */ +#define EXMC_D8_PE11 \ + GD32_PINMUX_AFIO('E', 11, ALTERNATE, NORMP) + +/* EXMC_D9 */ +#define EXMC_D9_PE12 \ + GD32_PINMUX_AFIO('E', 12, ALTERNATE, NORMP) + +/* EXMC_NBL0 */ +#define EXMC_NBL0_PE0 \ + GD32_PINMUX_AFIO('E', 0, ALTERNATE, NORMP) + +/* EXMC_NBL1 */ +#define EXMC_NBL1_PE1 \ + GD32_PINMUX_AFIO('E', 1, ALTERNATE, NORMP) + +/* EXMC_NE0 */ +#define EXMC_NE0_PD7 \ + GD32_PINMUX_AFIO('D', 7, ALTERNATE, NORMP) + +/* EXMC_NL(NADV) */ +#define EXMC_NL(NADV)_PB7 \ + GD32_PINMUX_AFIO('B', 7, ALTERNATE, NORMP) + +/* EXMC_NOE */ +#define EXMC_NOE_PD4 \ + GD32_PINMUX_AFIO('D', 4, ALTERNATE, NORMP) + +/* EXMC_NWAIT */ +#define EXMC_NWAIT_PD6 \ + GD32_PINMUX_AFIO('D', 6, GPIO_IN, NORMP) + +/* EXMC_NWE */ +#define EXMC_NWE_PD5 \ + GD32_PINMUX_AFIO('D', 5, ALTERNATE, NORMP) + +/* I2C0_SCL */ +#define I2C0_SCL_PB6_NORMP \ + GD32_PINMUX_AFIO('B', 6, ALTERNATE, I2C0_NORMP) +#define I2C0_SCL_PB8_RMP \ + GD32_PINMUX_AFIO('B', 8, ALTERNATE, I2C0_RMP) + +/* I2C0_SDA */ +#define I2C0_SDA_PB7_NORMP \ + GD32_PINMUX_AFIO('B', 7, ALTERNATE, I2C0_NORMP) +#define I2C0_SDA_PB9_RMP \ + GD32_PINMUX_AFIO('B', 9, ALTERNATE, I2C0_RMP) + +/* I2C0_SMBA */ +#define I2C0_SMBA_PB5 \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, NORMP) + +/* I2C0_TXFRAME */ +#define I2C0_TXFRAME_PB4 \ + GD32_PINMUX_AFIO('B', 4, ALTERNATE, NORMP) + +/* I2C1_SCL */ +#define I2C1_SCL_PB10 \ + GD32_PINMUX_AFIO('B', 10, ALTERNATE, NORMP) + +/* I2C1_SDA */ +#define I2C1_SDA_PB11 \ + GD32_PINMUX_AFIO('B', 11, ALTERNATE, NORMP) + +/* I2C1_SMBA */ +#define I2C1_SMBA_PB12 \ + GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) + +/* I2C1_TXFRAME */ +#define I2C1_TXFRAME_PB13 \ + GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) + +/* I2S1_CK */ +#define I2S1_CK_PB13 \ + GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) + +/* I2S1_MCK */ +#define I2S1_MCK_PC6 \ + GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP) + +/* I2S1_SD */ +#define I2S1_SD_PB15_INP \ + GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) +#define I2S1_SD_PB15_OUT \ + GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) + +/* I2S1_WS */ +#define I2S1_WS_PB12_INP \ + GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) +#define I2S1_WS_PB12_OUT \ + GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) + +/* I2S2_CK */ +#define I2S2_CK_PB3_NORMP \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, I2S2_NORMP) +#define I2S2_CK_PC10_RMP \ + GD32_PINMUX_AFIO('C', 10, ALTERNATE, I2S2_RMP) + +/* I2S2_MCK */ +#define I2S2_MCK_PC7 \ + GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP) + +/* I2S2_SD */ +#define I2S2_SD_PB5_INP_NORMP \ + GD32_PINMUX_AFIO('B', 5, GPIO_IN, I2S2_NORMP) +#define I2S2_SD_PB5_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, I2S2_NORMP) +#define I2S2_SD_PC12_INP_RMP \ + GD32_PINMUX_AFIO('C', 12, GPIO_IN, I2S2_RMP) +#define I2S2_SD_PC12_OUT_RMP \ + GD32_PINMUX_AFIO('C', 12, ALTERNATE, I2S2_RMP) + +/* I2S2_WS */ +#define I2S2_WS_PA15_INP_NORMP \ + GD32_PINMUX_AFIO('A', 15, GPIO_IN, I2S2_NORMP) +#define I2S2_WS_PA15_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 15, ALTERNATE, I2S2_NORMP) +#define I2S2_WS_PA4_INP_RMP \ + GD32_PINMUX_AFIO('A', 4, GPIO_IN, I2S2_RMP) +#define I2S2_WS_PA4_OUT_RMP \ + GD32_PINMUX_AFIO('A', 4, ALTERNATE, I2S2_RMP) + +/* RTC_TAMPER */ +#define RTC_TAMPER_PC13 \ + GD32_PINMUX_AFIO('C', 13, GPIO_IN, NORMP) + +/* SPI0_IO2 */ +#define SPI0_IO2_PA2_NORMP \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, SPI0_NORMP) +#define SPI0_IO2_PB6_RMP \ + GD32_PINMUX_AFIO('B', 6, ALTERNATE, SPI0_RMP) + +/* SPI0_IO3 */ +#define SPI0_IO3_PA3_NORMP \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, SPI0_NORMP) +#define SPI0_IO3_PB7_RMP \ + GD32_PINMUX_AFIO('B', 7, ALTERNATE, SPI0_RMP) + +/* SPI0_MISO */ +#define SPI0_MISO_PA6_INP_NORMP \ + GD32_PINMUX_AFIO('A', 6, GPIO_IN, SPI0_NORMP) +#define SPI0_MISO_PA6_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 6, ALTERNATE, SPI0_NORMP) +#define SPI0_MISO_PB4_INP_RMP \ + GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI0_RMP) +#define SPI0_MISO_PB4_OUT_RMP \ + GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI0_RMP) + +/* SPI0_MOSI */ +#define SPI0_MOSI_PA7_INP_NORMP \ + GD32_PINMUX_AFIO('A', 7, GPIO_IN, SPI0_NORMP) +#define SPI0_MOSI_PA7_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 7, ALTERNATE, SPI0_NORMP) +#define SPI0_MOSI_PB5_INP_RMP \ + GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI0_RMP) +#define SPI0_MOSI_PB5_OUT_RMP \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI0_RMP) + +/* SPI0_NSS */ +#define SPI0_NSS_PA4_INP_NORMP \ + GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI0_NORMP) +#define SPI0_NSS_PA4_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI0_NORMP) +#define SPI0_NSS_PA15_INP_RMP \ + GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI0_RMP) +#define SPI0_NSS_PA15_OUT_RMP \ + GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI0_RMP) + +/* SPI0_SCK */ +#define SPI0_SCK_PA5_INP_NORMP \ + GD32_PINMUX_AFIO('A', 5, GPIO_IN, SPI0_NORMP) +#define SPI0_SCK_PA5_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 5, ALTERNATE, SPI0_NORMP) +#define SPI0_SCK_PB3_INP_RMP \ + GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI0_RMP) +#define SPI0_SCK_PB3_OUT_RMP \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI0_RMP) + +/* SPI1_MISO */ +#define SPI1_MISO_PB14_INP \ + GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP) +#define SPI1_MISO_PB14_OUT \ + GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP) + +/* SPI1_MOSI */ +#define SPI1_MOSI_PB15_INP \ + GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) +#define SPI1_MOSI_PB15_OUT \ + GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) + +/* SPI1_NSS */ +#define SPI1_NSS_PB12_INP \ + GD32_PINMUX_AFIO('B', 12, GPIO_IN, NORMP) +#define SPI1_NSS_PB12_OUT \ + GD32_PINMUX_AFIO('B', 12, ALTERNATE, NORMP) + +/* SPI1_SCK */ +#define SPI1_SCK_PB13_INP \ + GD32_PINMUX_AFIO('B', 13, GPIO_IN, NORMP) +#define SPI1_SCK_PB13_OUT \ + GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP) + +/* SPI2_MISO */ +#define SPI2_MISO_PB4_INP_NORMP \ + GD32_PINMUX_AFIO('B', 4, GPIO_IN, SPI2_NORMP) +#define SPI2_MISO_PB4_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 4, ALTERNATE, SPI2_NORMP) +#define SPI2_MISO_PC11_INP_RMP \ + GD32_PINMUX_AFIO('C', 11, GPIO_IN, SPI2_RMP) +#define SPI2_MISO_PC11_OUT_RMP \ + GD32_PINMUX_AFIO('C', 11, ALTERNATE, SPI2_RMP) + +/* SPI2_MOSI */ +#define SPI2_MOSI_PB5_INP_NORMP \ + GD32_PINMUX_AFIO('B', 5, GPIO_IN, SPI2_NORMP) +#define SPI2_MOSI_PB5_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, SPI2_NORMP) +#define SPI2_MOSI_PC12_INP_RMP \ + GD32_PINMUX_AFIO('C', 12, GPIO_IN, SPI2_RMP) +#define SPI2_MOSI_PC12_OUT_RMP \ + GD32_PINMUX_AFIO('C', 12, ALTERNATE, SPI2_RMP) + +/* SPI2_NSS */ +#define SPI2_NSS_PA15_INP_NORMP \ + GD32_PINMUX_AFIO('A', 15, GPIO_IN, SPI2_NORMP) +#define SPI2_NSS_PA15_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 15, ALTERNATE, SPI2_NORMP) +#define SPI2_NSS_PA4_INP_RMP \ + GD32_PINMUX_AFIO('A', 4, GPIO_IN, SPI2_RMP) +#define SPI2_NSS_PA4_OUT_RMP \ + GD32_PINMUX_AFIO('A', 4, ALTERNATE, SPI2_RMP) + +/* SPI2_SCK */ +#define SPI2_SCK_PB3_INP_NORMP \ + GD32_PINMUX_AFIO('B', 3, GPIO_IN, SPI2_NORMP) +#define SPI2_SCK_PB3_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, SPI2_NORMP) +#define SPI2_SCK_PC10_INP_RMP \ + GD32_PINMUX_AFIO('C', 10, GPIO_IN, SPI2_RMP) +#define SPI2_SCK_PC10_OUT_RMP \ + GD32_PINMUX_AFIO('C', 10, ALTERNATE, SPI2_RMP) + +/* TIMER0_BKIN */ +#define TIMER0_BKIN_PB12_NORMP \ + GD32_PINMUX_AFIO('B', 12, GPIO_IN, TIMER0_NORMP) +#define TIMER0_BKIN_PA6_PRMP \ + GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER0_PRMP) +#define TIMER0_BKIN_PE15_FRMP \ + GD32_PINMUX_AFIO('E', 15, GPIO_IN, TIMER0_FRMP) + +/* TIMER0_CH0 */ +#define TIMER0_CH0_PA8_INP_NORMP \ + GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH0_PA8_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH0_PA8_INP_PRMP \ + GD32_PINMUX_AFIO('A', 8, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH0_PA8_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, TIMER0_PRMP) +#define TIMER0_CH0_PE9_INP_FRMP \ + GD32_PINMUX_AFIO('E', 9, GPIO_IN, TIMER0_FRMP) +#define TIMER0_CH0_PE9_OUT_FRMP \ + GD32_PINMUX_AFIO('E', 9, ALTERNATE, TIMER0_FRMP) + +/* TIMER0_CH0_ON */ +#define TIMER0_CH0_ON_PB13_INP_NORMP \ + GD32_PINMUX_AFIO('B', 13, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH0_ON_PB13_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 13, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH0_ON_PA7_INP_PRMP \ + GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH0_ON_PA7_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER0_PRMP) +#define TIMER0_CH0_ON_PE8_INP_FRMP \ + GD32_PINMUX_AFIO('E', 8, GPIO_IN, TIMER0_FRMP) +#define TIMER0_CH0_ON_PE8_OUT_FRMP \ + GD32_PINMUX_AFIO('E', 8, ALTERNATE, TIMER0_FRMP) + +/* TIMER0_CH1 */ +#define TIMER0_CH1_PA9_INP_NORMP \ + GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH1_PA9_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH1_PA9_INP_PRMP \ + GD32_PINMUX_AFIO('A', 9, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH1_PA9_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 9, ALTERNATE, TIMER0_PRMP) +#define TIMER0_CH1_PE11_INP_FRMP \ + GD32_PINMUX_AFIO('E', 11, GPIO_IN, TIMER0_FRMP) +#define TIMER0_CH1_PE11_OUT_FRMP \ + GD32_PINMUX_AFIO('E', 11, ALTERNATE, TIMER0_FRMP) + +/* TIMER0_CH1_ON */ +#define TIMER0_CH1_ON_PB14_INP_NORMP \ + GD32_PINMUX_AFIO('B', 14, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH1_ON_PB14_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 14, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH1_ON_PB0_INP_PRMP \ + GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH1_ON_PB0_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER0_PRMP) +#define TIMER0_CH1_ON_PE10_INP_FRMP \ + GD32_PINMUX_AFIO('E', 10, GPIO_IN, TIMER0_FRMP) +#define TIMER0_CH1_ON_PE10_OUT_FRMP \ + GD32_PINMUX_AFIO('E', 10, ALTERNATE, TIMER0_FRMP) + +/* TIMER0_CH2 */ +#define TIMER0_CH2_PA10_INP_NORMP \ + GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH2_PA10_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH2_PA10_INP_PRMP \ + GD32_PINMUX_AFIO('A', 10, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH2_PA10_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 10, ALTERNATE, TIMER0_PRMP) +#define TIMER0_CH2_PE13_INP_FRMP \ + GD32_PINMUX_AFIO('E', 13, GPIO_IN, TIMER0_FRMP) +#define TIMER0_CH2_PE13_OUT_FRMP \ + GD32_PINMUX_AFIO('E', 13, ALTERNATE, TIMER0_FRMP) + +/* TIMER0_CH2_ON */ +#define TIMER0_CH2_ON_PB15_NORMP \ + GD32_PINMUX_AFIO('B', 15, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH2_ON_PB1_PRMP \ + GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER0_PRMP) +#define TIMER0_CH2_ON_PE12_FRMP \ + GD32_PINMUX_AFIO('E', 12, ALTERNATE, TIMER0_FRMP) + +/* TIMER0_CH3 */ +#define TIMER0_CH3_PA11_INP_NORMP \ + GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_NORMP) +#define TIMER0_CH3_PA11_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_NORMP) +#define TIMER0_CH3_PA11_INP_PRMP \ + GD32_PINMUX_AFIO('A', 11, GPIO_IN, TIMER0_PRMP) +#define TIMER0_CH3_PA11_OUT_PRMP \ + GD32_PINMUX_AFIO('A', 11, ALTERNATE, TIMER0_PRMP) +#define TIMER0_CH3_PE14_INP_FRMP \ + GD32_PINMUX_AFIO('E', 14, GPIO_IN, TIMER0_FRMP) +#define TIMER0_CH3_PE14_OUT_FRMP \ + GD32_PINMUX_AFIO('E', 14, ALTERNATE, TIMER0_FRMP) + +/* TIMER0_ETI */ +#define TIMER0_ETI_PA12_NORMP \ + GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_NORMP) +#define TIMER0_ETI_PA12_PRMP \ + GD32_PINMUX_AFIO('A', 12, GPIO_IN, TIMER0_PRMP) +#define TIMER0_ETI_PE7_FRMP \ + GD32_PINMUX_AFIO('E', 7, GPIO_IN, TIMER0_FRMP) + +/* TIMER10_CH0 */ +#define TIMER10_CH0_PB9_INP \ + GD32_PINMUX_AFIO('B', 9, GPIO_IN, NORMP) +#define TIMER10_CH0_PB9_OUT \ + GD32_PINMUX_AFIO('B', 9, ALTERNATE, NORMP) + +/* TIMER11_CH0 */ +#define TIMER11_CH0_PB14_INP \ + GD32_PINMUX_AFIO('B', 14, GPIO_IN, NORMP) +#define TIMER11_CH0_PB14_OUT \ + GD32_PINMUX_AFIO('B', 14, ALTERNATE, NORMP) + +/* TIMER11_CH11 */ +#define TIMER11_CH11_PB15_INP \ + GD32_PINMUX_AFIO('B', 15, GPIO_IN, NORMP) +#define TIMER11_CH11_PB15_OUT \ + GD32_PINMUX_AFIO('B', 15, ALTERNATE, NORMP) + +/* TIMER12_CH0 */ +#define TIMER12_CH0_PA6_INP \ + GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP) +#define TIMER12_CH0_PA6_OUT \ + GD32_PINMUX_AFIO('A', 6, ALTERNATE, NORMP) + +/* TIMER13_CH0 */ +#define TIMER13_CH0_PA7_INP \ + GD32_PINMUX_AFIO('A', 7, GPIO_IN, NORMP) +#define TIMER13_CH0_PA7_OUT \ + GD32_PINMUX_AFIO('A', 7, ALTERNATE, NORMP) + +/* TIMER1_CH0_ETI */ +#define TIMER1_CH0_ETI_PA0 \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) + +/* TIMER1_CH1 */ +#define TIMER1_CH1_PA1_INP_NORMP \ + GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_NORMP) +#define TIMER1_CH1_PA1_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_NORMP) +#define TIMER1_CH1_PA1_INP_PRMP2 \ + GD32_PINMUX_AFIO('A', 1, GPIO_IN, TIMER1_PRMP2) +#define TIMER1_CH1_PA1_OUT_PRMP2 \ + GD32_PINMUX_AFIO('A', 1, ALTERNATE, TIMER1_PRMP2) +#define TIMER1_CH1_PB3_INP_PRMP1 \ + GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_PRMP1) +#define TIMER1_CH1_PB3_OUT_PRMP1 \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_PRMP1) +#define TIMER1_CH1_PB3_INP_FRMP \ + GD32_PINMUX_AFIO('B', 3, GPIO_IN, TIMER1_FRMP) +#define TIMER1_CH1_PB3_OUT_FRMP \ + GD32_PINMUX_AFIO('B', 3, ALTERNATE, TIMER1_FRMP) + +/* TIMER1_CH2 */ +#define TIMER1_CH2_PA2_INP_NORMP \ + GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_NORMP) +#define TIMER1_CH2_PA2_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_NORMP) +#define TIMER1_CH2_PA2_INP_PRMP1 \ + GD32_PINMUX_AFIO('A', 2, GPIO_IN, TIMER1_PRMP1) +#define TIMER1_CH2_PA2_OUT_PRMP1 \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, TIMER1_PRMP1) +#define TIMER1_CH2_PB10_INP_PRMP2 \ + GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_PRMP2) +#define TIMER1_CH2_PB10_OUT_PRMP2 \ + GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_PRMP2) +#define TIMER1_CH2_PB10_INP_FRMP \ + GD32_PINMUX_AFIO('B', 10, GPIO_IN, TIMER1_FRMP) +#define TIMER1_CH2_PB10_OUT_FRMP \ + GD32_PINMUX_AFIO('B', 10, ALTERNATE, TIMER1_FRMP) + +/* TIMER1_CH3 */ +#define TIMER1_CH3_PA3_INP_NORMP \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_NORMP) +#define TIMER1_CH3_PA3_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_NORMP) +#define TIMER1_CH3_PA3_INP_PRMP1 \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, TIMER1_PRMP1) +#define TIMER1_CH3_PA3_OUT_PRMP1 \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, TIMER1_PRMP1) +#define TIMER1_CH3_PB11_INP_PRMP2 \ + GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_PRMP2) +#define TIMER1_CH3_PB11_OUT_PRMP2 \ + GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_PRMP2) +#define TIMER1_CH3_PB11_INP_FRMP \ + GD32_PINMUX_AFIO('B', 11, GPIO_IN, TIMER1_FRMP) +#define TIMER1_CH3_PB11_OUT_FRMP \ + GD32_PINMUX_AFIO('B', 11, ALTERNATE, TIMER1_FRMP) + +/* TIMER2_CH0 */ +#define TIMER2_CH0_PA6_INP_NORMP \ + GD32_PINMUX_AFIO('A', 6, GPIO_IN, TIMER2_NORMP) +#define TIMER2_CH0_PA6_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 6, ALTERNATE, TIMER2_NORMP) +#define TIMER2_CH0_PB4_INP_PRMP \ + GD32_PINMUX_AFIO('B', 4, GPIO_IN, TIMER2_PRMP) +#define TIMER2_CH0_PB4_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 4, ALTERNATE, TIMER2_PRMP) +#define TIMER2_CH0_PC6_INP_FRMP \ + GD32_PINMUX_AFIO('C', 6, GPIO_IN, TIMER2_FRMP) +#define TIMER2_CH0_PC6_OUT_FRMP \ + GD32_PINMUX_AFIO('C', 6, ALTERNATE, TIMER2_FRMP) + +/* TIMER2_CH1 */ +#define TIMER2_CH1_PA7_INP_NORMP \ + GD32_PINMUX_AFIO('A', 7, GPIO_IN, TIMER2_NORMP) +#define TIMER2_CH1_PA7_OUT_NORMP \ + GD32_PINMUX_AFIO('A', 7, ALTERNATE, TIMER2_NORMP) +#define TIMER2_CH1_PB5_INP_PRMP \ + GD32_PINMUX_AFIO('B', 5, GPIO_IN, TIMER2_PRMP) +#define TIMER2_CH1_PB5_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 5, ALTERNATE, TIMER2_PRMP) +#define TIMER2_CH1_PC7_INP_FRMP \ + GD32_PINMUX_AFIO('C', 7, GPIO_IN, TIMER2_FRMP) +#define TIMER2_CH1_PC7_OUT_FRMP \ + GD32_PINMUX_AFIO('C', 7, ALTERNATE, TIMER2_FRMP) + +/* TIMER2_CH2 */ +#define TIMER2_CH2_PB0_INP_NORMP \ + GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_NORMP) +#define TIMER2_CH2_PB0_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_NORMP) +#define TIMER2_CH2_PB0_INP_PRMP \ + GD32_PINMUX_AFIO('B', 0, GPIO_IN, TIMER2_PRMP) +#define TIMER2_CH2_PB0_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 0, ALTERNATE, TIMER2_PRMP) +#define TIMER2_CH2_PC8_INP_FRMP \ + GD32_PINMUX_AFIO('C', 8, GPIO_IN, TIMER2_FRMP) +#define TIMER2_CH2_PC8_OUT_FRMP \ + GD32_PINMUX_AFIO('C', 8, ALTERNATE, TIMER2_FRMP) + +/* TIMER2_CH3 */ +#define TIMER2_CH3_PB1_INP_NORMP \ + GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_NORMP) +#define TIMER2_CH3_PB1_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_NORMP) +#define TIMER2_CH3_PB1_INP_PRMP \ + GD32_PINMUX_AFIO('B', 1, GPIO_IN, TIMER2_PRMP) +#define TIMER2_CH3_PB1_OUT_PRMP \ + GD32_PINMUX_AFIO('B', 1, ALTERNATE, TIMER2_PRMP) +#define TIMER2_CH3_PC9_INP_FRMP \ + GD32_PINMUX_AFIO('C', 9, GPIO_IN, TIMER2_FRMP) +#define TIMER2_CH3_PC9_OUT_FRMP \ + GD32_PINMUX_AFIO('C', 9, ALTERNATE, TIMER2_FRMP) + +/* TIMER2_ETI */ +#define TIMER2_ETI_PD2 \ + GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP) + +/* TIMER3_CH0 */ +#define TIMER3_CH0_PB6_INP_NORMP \ + GD32_PINMUX_AFIO('B', 6, GPIO_IN, TIMER3_NORMP) +#define TIMER3_CH0_PB6_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 6, ALTERNATE, TIMER3_NORMP) +#define TIMER3_CH0_PD12_INP_RMP \ + GD32_PINMUX_AFIO('D', 12, GPIO_IN, TIMER3_RMP) +#define TIMER3_CH0_PD12_OUT_RMP \ + GD32_PINMUX_AFIO('D', 12, ALTERNATE, TIMER3_RMP) + +/* TIMER3_CH1 */ +#define TIMER3_CH1_PB7_INP_NORMP \ + GD32_PINMUX_AFIO('B', 7, GPIO_IN, TIMER3_NORMP) +#define TIMER3_CH1_PB7_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 7, ALTERNATE, TIMER3_NORMP) +#define TIMER3_CH1_PD13_INP_RMP \ + GD32_PINMUX_AFIO('D', 13, GPIO_IN, TIMER3_RMP) +#define TIMER3_CH1_PD13_OUT_RMP \ + GD32_PINMUX_AFIO('D', 13, ALTERNATE, TIMER3_RMP) + +/* TIMER3_CH2 */ +#define TIMER3_CH2_PB8_INP_NORMP \ + GD32_PINMUX_AFIO('B', 8, GPIO_IN, TIMER3_NORMP) +#define TIMER3_CH2_PB8_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 8, ALTERNATE, TIMER3_NORMP) +#define TIMER3_CH2_PD14_INP_RMP \ + GD32_PINMUX_AFIO('D', 14, GPIO_IN, TIMER3_RMP) +#define TIMER3_CH2_PD14_OUT_RMP \ + GD32_PINMUX_AFIO('D', 14, ALTERNATE, TIMER3_RMP) + +/* TIMER3_CH3 */ +#define TIMER3_CH3_PB9_INP_NORMP \ + GD32_PINMUX_AFIO('B', 9, GPIO_IN, TIMER3_NORMP) +#define TIMER3_CH3_PB9_OUT_NORMP \ + GD32_PINMUX_AFIO('B', 9, ALTERNATE, TIMER3_NORMP) +#define TIMER3_CH3_PD15_INP_RMP \ + GD32_PINMUX_AFIO('D', 15, GPIO_IN, TIMER3_RMP) +#define TIMER3_CH3_PD15_OUT_RMP \ + GD32_PINMUX_AFIO('D', 15, ALTERNATE, TIMER3_RMP) + +/* TIMER3_ETI */ +#define TIMER3_ETI_PE0 \ + GD32_PINMUX_AFIO('E', 0, GPIO_IN, NORMP) + +/* TIMER4_CH0 */ +#define TIMER4_CH0_PA0_INP \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) +#define TIMER4_CH0_PA0_OUT \ + GD32_PINMUX_AFIO('A', 0, ALTERNATE, NORMP) + +/* TIMER4_CH1 */ +#define TIMER4_CH1_PA1_INP \ + GD32_PINMUX_AFIO('A', 1, GPIO_IN, NORMP) +#define TIMER4_CH1_PA1_OUT \ + GD32_PINMUX_AFIO('A', 1, ALTERNATE, NORMP) + +/* TIMER4_CH2 */ +#define TIMER4_CH2_PA2_INP \ + GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP) +#define TIMER4_CH2_PA2_OUT \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP) + +/* TIMER4_CH3 */ +#define TIMER4_CH3_PA3_INP \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP) +#define TIMER4_CH3_PA3_OUT \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP) + +/* TIMER7_BKIN */ +#define TIMER7_BKIN_PA6 \ + GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP) + +/* TIMER7_CH0 */ +#define TIMER7_CH0_PC6_INP \ + GD32_PINMUX_AFIO('C', 6, GPIO_IN, NORMP) +#define TIMER7_CH0_PC6_OUT \ + GD32_PINMUX_AFIO('C', 6, ALTERNATE, NORMP) + +/* TIMER7_CH0_ON */ +#define TIMER7_CH0_ON_PA7_INP \ + GD32_PINMUX_AFIO('A', 7, GPIO_IN, NORMP) +#define TIMER7_CH0_ON_PA7_OUT \ + GD32_PINMUX_AFIO('A', 7, ALTERNATE, NORMP) + +/* TIMER7_CH1 */ +#define TIMER7_CH1_PC7_INP \ + GD32_PINMUX_AFIO('C', 7, GPIO_IN, NORMP) +#define TIMER7_CH1_PC7_OUT \ + GD32_PINMUX_AFIO('C', 7, ALTERNATE, NORMP) + +/* TIMER7_CH1_ON */ +#define TIMER7_CH1_ON_PB0_INP \ + GD32_PINMUX_AFIO('B', 0, GPIO_IN, NORMP) +#define TIMER7_CH1_ON_PB0_OUT \ + GD32_PINMUX_AFIO('B', 0, ALTERNATE, NORMP) + +/* TIMER7_CH2 */ +#define TIMER7_CH2_PC8_INP \ + GD32_PINMUX_AFIO('C', 8, GPIO_IN, NORMP) +#define TIMER7_CH2_PC8_OUT \ + GD32_PINMUX_AFIO('C', 8, ALTERNATE, NORMP) + +/* TIMER7_CH2_ON */ +#define TIMER7_CH2_ON_PB1 \ + GD32_PINMUX_AFIO('B', 1, ALTERNATE, NORMP) + +/* TIMER7_CH3 */ +#define TIMER7_CH3_PC9_INP \ + GD32_PINMUX_AFIO('C', 9, GPIO_IN, NORMP) +#define TIMER7_CH3_PC9_OUT \ + GD32_PINMUX_AFIO('C', 9, ALTERNATE, NORMP) + +/* TIMER7_ETI */ +#define TIMER7_ETI_PA0 \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) + +/* TIMER8_CH0 */ +#define TIMER8_CH0_PA2_INP \ + GD32_PINMUX_AFIO('A', 2, GPIO_IN, NORMP) +#define TIMER8_CH0_PA2_OUT \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, NORMP) + +/* TIMER8_CH1 */ +#define TIMER8_CH1_PA3_INP \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, NORMP) +#define TIMER8_CH1_PA3_OUT \ + GD32_PINMUX_AFIO('A', 3, ALTERNATE, NORMP) + +/* TIMER9_CH0 */ +#define TIMER9_CH0_PB8_INP \ + GD32_PINMUX_AFIO('B', 8, GPIO_IN, NORMP) +#define TIMER9_CH0_PB8_OUT \ + GD32_PINMUX_AFIO('B', 8, ALTERNATE, NORMP) + +/* TRACECK */ +#define TRACECK_PE2 \ + GD32_PINMUX_AFIO('E', 2, ALTERNATE, NORMP) + +/* TRACED0 */ +#define TRACED0_PE3 \ + GD32_PINMUX_AFIO('E', 3, ALTERNATE, NORMP) + +/* TRACED1 */ +#define TRACED1_PE4 \ + GD32_PINMUX_AFIO('E', 4, ALTERNATE, NORMP) + +/* TRACED2 */ +#define TRACED2_PE5 \ + GD32_PINMUX_AFIO('E', 5, ALTERNATE, NORMP) + +/* TRACED3 */ +#define TRACED3_PE6 \ + GD32_PINMUX_AFIO('E', 6, ALTERNATE, NORMP) + +/* UART3_RX */ +#define UART3_RX_PC11 \ + GD32_PINMUX_AFIO('C', 11, GPIO_IN, NORMP) + +/* UART3_TX */ +#define UART3_TX_PC10 \ + GD32_PINMUX_AFIO('C', 10, ALTERNATE, NORMP) + +/* UART4_RX */ +#define UART4_RX_PD2 \ + GD32_PINMUX_AFIO('D', 2, GPIO_IN, NORMP) + +/* UART4_TX */ +#define UART4_TX_PC12 \ + GD32_PINMUX_AFIO('C', 12, ALTERNATE, NORMP) + +/* USART0_CK */ +#define USART0_CK_PA8 \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) + +/* USART0_CTS */ +#define USART0_CTS_PA11 \ + GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) + +/* USART0_RTS */ +#define USART0_RTS_PA12 \ + GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) + +/* USART0_RX */ +#define USART0_RX_PA10_NORMP \ + GD32_PINMUX_AFIO('A', 10, GPIO_IN, USART0_NORMP) +#define USART0_RX_PB7_RMP \ + GD32_PINMUX_AFIO('B', 7, GPIO_IN, USART0_RMP) + +/* USART0_TX */ +#define USART0_TX_PA9_NORMP \ + GD32_PINMUX_AFIO('A', 9, ALTERNATE, USART0_NORMP) +#define USART0_TX_PB6_RMP \ + GD32_PINMUX_AFIO('B', 6, ALTERNATE, USART0_RMP) + +/* USART1_CK */ +#define USART1_CK_PA4_NORMP \ + GD32_PINMUX_AFIO('A', 4, ALTERNATE, USART1_NORMP) +#define USART1_CK_PD7_RMP \ + GD32_PINMUX_AFIO('D', 7, ALTERNATE, USART1_RMP) + +/* USART1_CTS */ +#define USART1_CTS_PA0_NORMP \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, USART1_NORMP) +#define USART1_CTS_PD3_RMP \ + GD32_PINMUX_AFIO('D', 3, GPIO_IN, USART1_RMP) + +/* USART1_RTS */ +#define USART1_RTS_PA1_NORMP \ + GD32_PINMUX_AFIO('A', 1, ALTERNATE, USART1_NORMP) +#define USART1_RTS_PD4_RMP \ + GD32_PINMUX_AFIO('D', 4, ALTERNATE, USART1_RMP) + +/* USART1_RX */ +#define USART1_RX_PA3_NORMP \ + GD32_PINMUX_AFIO('A', 3, GPIO_IN, USART1_NORMP) +#define USART1_RX_PD6_RMP \ + GD32_PINMUX_AFIO('D', 6, GPIO_IN, USART1_RMP) + +/* USART1_TX */ +#define USART1_TX_PA2_NORMP \ + GD32_PINMUX_AFIO('A', 2, ALTERNATE, USART1_NORMP) +#define USART1_TX_PD5_RMP \ + GD32_PINMUX_AFIO('D', 5, ALTERNATE, USART1_RMP) + +/* USART2_CK */ +#define USART2_CK_PB12_NORMP \ + GD32_PINMUX_AFIO('B', 12, ALTERNATE, USART2_NORMP) +#define USART2_CK_PC12_PRMP \ + GD32_PINMUX_AFIO('C', 12, ALTERNATE, USART2_PRMP) +#define USART2_CK_PD10_FRMP \ + GD32_PINMUX_AFIO('D', 10, ALTERNATE, USART2_FRMP) + +/* USART2_CTS */ +#define USART2_CTS_PB13_NORMP \ + GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_NORMP) +#define USART2_CTS_PB13_PRMP \ + GD32_PINMUX_AFIO('B', 13, GPIO_IN, USART2_PRMP) +#define USART2_CTS_PD11_FRMP \ + GD32_PINMUX_AFIO('D', 11, GPIO_IN, USART2_FRMP) + +/* USART2_RTS */ +#define USART2_RTS_PB14_NORMP \ + GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_NORMP) +#define USART2_RTS_PB14_PRMP \ + GD32_PINMUX_AFIO('B', 14, ALTERNATE, USART2_PRMP) +#define USART2_RTS_PD12_FRMP \ + GD32_PINMUX_AFIO('D', 12, ALTERNATE, USART2_FRMP) + +/* USART2_RX */ +#define USART2_RX_PB11_NORMP \ + GD32_PINMUX_AFIO('B', 11, GPIO_IN, USART2_NORMP) +#define USART2_RX_PC11_PRMP \ + GD32_PINMUX_AFIO('C', 11, GPIO_IN, USART2_PRMP) +#define USART2_RX_PD9_FRMP \ + GD32_PINMUX_AFIO('D', 9, GPIO_IN, USART2_FRMP) + +/* USART2_TX */ +#define USART2_TX_PB10_NORMP \ + GD32_PINMUX_AFIO('B', 10, ALTERNATE, USART2_NORMP) +#define USART2_TX_PC10_PRMP \ + GD32_PINMUX_AFIO('C', 10, ALTERNATE, USART2_PRMP) +#define USART2_TX_PD8_FRMP \ + GD32_PINMUX_AFIO('D', 8, ALTERNATE, USART2_FRMP) + +/* USBFS_DM */ +#define USBFS_DM_PA11_INP \ + GD32_PINMUX_AFIO('A', 11, GPIO_IN, NORMP) +#define USBFS_DM_PA11_OUT \ + GD32_PINMUX_AFIO('A', 11, ALTERNATE, NORMP) + +/* USBFS_DP */ +#define USBFS_DP_PA12_INP \ + GD32_PINMUX_AFIO('A', 12, GPIO_IN, NORMP) +#define USBFS_DP_PA12_OUT \ + GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP) + +/* USBFS_ID */ +#define USBFS_ID_PA10_INP \ + GD32_PINMUX_AFIO('A', 10, GPIO_IN, NORMP) +#define USBFS_ID_PA10_OUT \ + GD32_PINMUX_AFIO('A', 10, ALTERNATE, NORMP) + +/* USBFS_SOF */ +#define USBFS_SOF_PA8 \ + GD32_PINMUX_AFIO('A', 8, ALTERNATE, NORMP) + +/* USBFS_VBUS */ +#define USBFS_VBUS_PA9 \ + GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP) + +/* WKUP */ +#define WKUP_PA0 \ + GD32_PINMUX_AFIO('A', 0, GPIO_IN, NORMP) diff --git a/include/dt-bindings/pinctrl/gd32e103xx-afio.h b/include/dt-bindings/pinctrl/gd32e103xx-afio.h new file mode 100644 index 00000000..bd95636d --- /dev/null +++ b/include/dt-bindings/pinctrl/gd32e103xx-afio.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2021 YuLong Yao + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef GD32E103XX_AFIO_H_ +#define GD32E103XX_AFIO_H_ + +#include "gd32-afio.h" + +/** SPI0 (no remap) */ +#define GD32_SPI0_NORMP GD32_REMAP(0U, 0U, 0x1U, 0U) +/** SPI0 (remap) */ +#define GD32_SPI0_RMP GD32_REMAP(0U, 0U, 0x1U, 1U) + +/** I2C0 (no remap) */ +#define GD32_I2C0_NORMP GD32_REMAP(0U, 1U, 0x1U, 0U) +/** I2C0 (remap) */ +#define GD32_I2C0_RMP GD32_REMAP(0U, 1U, 0x1U, 1U) + +/** USART0 (no remap) */ +#define GD32_USART0_NORMP GD32_REMAP(0U, 2U, 0x1U, 0U) +/** USART0 (remap) */ +#define GD32_USART0_RMP GD32_REMAP(0U, 2U, 0x1U, 1U) + +/** USART1 (no remap) */ +#define GD32_USART1_NORMP GD32_REMAP(0U, 3U, 0x1U, 0U) +/** USART1 (remap) */ +#define GD32_USART1_RMP GD32_REMAP(0U, 3U, 0x1U, 1U) + +/** USART2 (no remap) */ +#define GD32_USART2_NORMP GD32_REMAP(0U, 4U, 0x3U, 0U) +/** USART2 (partial remap) */ +#define GD32_USART2_PRMP GD32_REMAP(0U, 4U, 0x3U, 1U) +/** USART2 (full remap) */ +#define GD32_USART2_FRMP GD32_REMAP(0U, 4U, 0x3U, 3U) + +/** TIMER0 (no remap) */ +#define GD32_TIMER0_NORMP GD32_REMAP(0U, 6U, 0x3U, 0U) +/** TIMER0 (partial remap) */ +#define GD32_TIMER0_PRMP GD32_REMAP(0U, 6U, 0x3U, 1U) +/** TIMER0 (full remap) */ +#define GD32_TIMER0_FRMP GD32_REMAP(0U, 6U, 0x3U, 3U) + +/** TIMER1 (no remap) */ +#define GD32_TIMER1_NORMP GD32_REMAP(0U, 8U, 0x3U, 0U) +/** TIMER1 (partial remap 1) */ +#define GD32_TIMER1_PRMP1 GD32_REMAP(0U, 8U, 0x3U, 1U) +/** TIMER1 (partial remap 2) */ +#define GD32_TIMER1_PRMP2 GD32_REMAP(0U, 8U, 0x3U, 2U) +/** TIMER1 (full remap) */ +#define GD32_TIMER1_FRMP GD32_REMAP(0U, 8U, 0x3U, 3U) + +/** TIMER2 (no remap) */ +#define GD32_TIMER2_NORMP GD32_REMAP(0U, 10U, 0x3U, 0U) +/** TIMER2 (partial remap) */ +#define GD32_TIMER2_PRMP GD32_REMAP(0U, 10U, 0x3U, 2U) +/** TIMER2 (full remap) */ +#define GD32_TIMER2_FRMP GD32_REMAP(0U, 10U, 0x3U, 3U) + +/** TIMER3 (no remap) */ +#define GD32_TIMER3_NORMP GD32_REMAP(0U, 12U, 0x1U, 0U) +/** TIMER3 (remap) */ +#define GD32_TIMER3_RMP GD32_REMAP(0U, 12U, 0x1U, 1U) + +/** TIMER4CH3 (no remap) */ +#define GD32_TIMER4CH3_NORMP GD32_REMAP(0U, 16U, 0x1U, 0U) +/** TIMER4CH3 (remap) */ +#define GD32_TIMER4CH3_RMP GD32_REMAP(0U, 16U, 0x1U, 1U) + +/** SPI2 (no remap) */ +#define GD32_SPI2_NORMP GD32_REMAP(0U, 28U, 0x1U, 0U) +/** SPI2 (remap) */ +#define GD32_SPI2_RMP GD32_REMAP(0U, 28U, 0x1U, 1U) + +/** TIMER1_ITR0 (no remap) */ +#define GD32_TIMER1ITR0_NORMP GD32_REMAP(0U, 29U, 0x1U, 0U) +/** TIMER1_ITR0 (remap) */ +#define GD32_TIMER1ITR0_RMP GD32_REMAP(0U, 29U, 0x1U, 1U) + +/** TIMER8 (no remap) */ +#define GD32_TIMER8_NORMP GD32_REMAP(1U, 5U, 0x1U, 0U) +/** TIMER8 (remap) */ +#define GD32_TIMER8_RMP GD32_REMAP(1U, 5U, 0x1U, 1U) + +/** CTC (no remap) */ +#define GD32_CTC_NORMP GD32_REMAP(1U, 11U, 0x3U, 0U) +/** CTC (remap) */ +#define GD32_CTC_PRMP GD32_REMAP(1U, 11U, 0x3U, 1U) + +#endif /* GD32E103XX_AFIO_H_ */ diff --git a/pinconfigs/gd32e103xx.yml b/pinconfigs/gd32e103xx.yml new file mode 100644 index 00000000..3f340b4b --- /dev/null +++ b/pinconfigs/gd32e103xx.yml @@ -0,0 +1,790 @@ +# GD32E103XX pin definitions +# +# Sources: +# - GD32E103XX Datasheet (Revision 1.5) +# - GD32E103 User Manual (Revision 1.5) +# +# Pin codes: +# +# - 100 pins: V +# - 64 pins: R +# - 48 pins: C +# - 36 pins: T +# +# Memory codes: +# +# - 128Kb Flash, 32Kb SRAM: B +# - 64Kb Flash, 20Kb SRAM: 8 +# +# Copyright (c) 2021 YuLong Yao +# SPDX-License-Identifier: Apache 2.0 + +model: afio + +series: gd32e103 + +variants: + - pincode: V + memories: [B, 8] + - pincode: R + memories: [B, 8] + - pincode: C + memories: [B, 8] + - pincode: T + memories: [B, 8] + +signal-configs: + ADC01_IN0: + modes: [analog] + ADC01_IN1: + modes: [analog] + ADC01_IN10: + modes: [analog] + exclude-pincodes: [T, C] + ADC01_IN11: + modes: [analog] + exclude-pincodes: [T, C] + ADC01_IN12: + modes: [analog] + exclude-pincodes: [T, C] + ADC01_IN13: + modes: [analog] + exclude-pincodes: [T, C] + ADC01_IN14: + modes: [analog] + exclude-pincodes: [T, C] + ADC01_IN15: + modes: [analog] + exclude-pincodes: [T, C] + ADC01_IN2: + modes: [analog] + ADC01_IN3: + modes: [analog] + ADC01_IN4: + modes: [analog] + ADC01_IN5: + modes: [analog] + ADC01_IN6: + modes: [analog] + ADC01_IN7: + modes: [analog] + ADC01_IN8: + modes: [analog] + ADC01_IN9: + modes: [analog] + CK_OUT0: + modes: [out] + CTC_SYNC: + modes: [out] + DAC_OUT0: + modes: [analog] + DAC_OUT1: + modes: [analog] + EXMC_A16: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_A17: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_A18: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_A19: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_A20: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_A21: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_A22: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_A23: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_CLK: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_D0: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_D1: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_D10: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_D11: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_D12: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_D13: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_D14: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_D15: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_D2: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_D3: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_D4: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_D5: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_D6: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_D7: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_D8: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_D9: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_NBL0: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_NBL1: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_NE0: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_NL(NADV): + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_NOE: + modes: [out] + exclude-pincodes: [T, R, C] + EXMC_NWAIT: + modes: [inp] + exclude-pincodes: [T, R, C] + EXMC_NWE: + modes: [out] + exclude-pincodes: [T, R, C] + I2C0_SCL: + modes: [out] + I2C0_SDA: + modes: [out] + I2C0_SMBA: + modes: [out] + I2C0_TXFRAME: + modes: [out] + I2C1_SCL: + modes: [out] + exclude-pincodes: [T] + I2C1_SDA: + modes: [out] + exclude-pincodes: [T] + I2C1_SMBA: + modes: [out] + exclude-pincodes: [T] + I2C1_TXFRAME: + modes: [out] + exclude-pincodes: [T] + I2S1_CK: + modes: [out] + exclude-pincodes: [T] + I2S1_MCK: + modes: [out] + exclude-pincodes: [T, C] + I2S1_SD: + modes: [inp, out] + exclude-pincodes: [T] + I2S1_WS: + modes: [inp, out] + exclude-pincodes: [T] + I2S2_CK: + modes: [out] + exclude-pincodes: [T] + I2S2_MCK: + modes: [out] + exclude-pincodes: [T, C] + I2S2_SD: + modes: [inp, out] + exclude-pincodes: [T] + I2S2_WS: + modes: [inp, out] + exclude-pincodes: [T] + RTC_TAMPER: + modes: [inp] + exclude-pincodes: [T] + SPI0_IO2: + modes: [out] + SPI0_IO3: + modes: [out] + SPI0_MISO: + modes: [inp, out] + SPI0_MOSI: + modes: [inp, out] + SPI0_NSS: + modes: [inp, out] + SPI0_SCK: + modes: [inp, out] + SPI1_MISO: + modes: [inp, out] + exclude-pincodes: [T] + SPI1_MOSI: + modes: [inp, out] + exclude-pincodes: [T] + SPI1_NSS: + modes: [inp, out] + exclude-pincodes: [T] + SPI1_SCK: + modes: [inp, out] + exclude-pincodes: [T] + SPI2_MISO: + modes: [inp, out] + exclude-pincodes: [T] + SPI2_MOSI: + modes: [inp, out] + exclude-pincodes: [T] + SPI2_NSS: + modes: [inp, out] + exclude-pincodes: [T] + SPI2_SCK: + modes: [inp, out] + exclude-pincodes: [T] + TIMER0_BKIN: + modes: [inp] + exclude-pincodes: [T] + TIMER0_CH0: + modes: [inp, out] + TIMER0_CH0_ON: + modes: [inp, out] + exclude-pincodes: [T] + TIMER0_CH1: + modes: [inp, out] + TIMER0_CH1_ON: + modes: [inp, out] + exclude-pincodes: [T] + TIMER0_CH2: + modes: [inp, out] + TIMER0_CH2_ON: + modes: [out] + exclude-pincodes: [T] + TIMER0_CH3: + modes: [inp, out] + TIMER0_ETI: + modes: [inp] + TIMER10_CH0: + modes: [inp, out] + exclude-pincodes: [T] + TIMER11_CH0: + modes: [inp, out] + exclude-pincodes: [T] + TIMER11_CH11: + modes: [inp, out] + exclude-pincodes: [T] + TIMER12_CH0: + modes: [inp, out] + exclude-pincodes: [T] + TIMER13_CH0: + modes: [inp, out] + exclude-pincodes: [T] + TIMER1_CH0_ETI: + modes: [inp] + TIMER1_CH1: + modes: [inp, out] + TIMER1_CH2: + modes: [inp, out] + TIMER1_CH3: + modes: [inp, out] + TIMER2_CH0: + modes: [inp, out] + TIMER2_CH1: + modes: [inp, out] + TIMER2_CH2: + modes: [inp, out] + TIMER2_CH3: + modes: [inp, out] + TIMER2_ETI: + modes: [inp] + exclude-pincodes: [T, C] + TIMER3_CH0: + modes: [inp, out] + TIMER3_CH1: + modes: [inp, out] + TIMER3_CH2: + modes: [inp, out] + exclude-pincodes: [T] + TIMER3_CH3: + modes: [inp, out] + exclude-pincodes: [T] + TIMER3_ETI: + modes: [inp] + exclude-pincodes: [T, R, C] + TIMER4_CH0: + modes: [inp, out] + TIMER4_CH1: + modes: [inp, out] + TIMER4_CH2: + modes: [inp, out] + TIMER4_CH3: + modes: [inp, out] + TIMER7_BKIN: + modes: [inp] + exclude-pincodes: [T, C] + TIMER7_CH0: + modes: [inp, out] + exclude-pincodes: [T, C] + TIMER7_CH0_ON: + modes: [inp, out] + exclude-pincodes: [T, C] + TIMER7_CH1: + modes: [inp, out] + exclude-pincodes: [T, C] + TIMER7_CH1_ON: + modes: [inp, out] + exclude-pincodes: [T, C] + TIMER7_CH2: + modes: [inp, out] + exclude-pincodes: [T, C] + TIMER7_CH2_ON: + modes: [out] + exclude-pincodes: [T, C] + TIMER7_CH3: + modes: [inp, out] + exclude-pincodes: [T, C] + TIMER7_ETI: + modes: [inp] + exclude-pincodes: [T, C] + TIMER8_CH0: + modes: [inp, out] + exclude-pincodes: [T] + TIMER8_CH1: + modes: [inp, out] + exclude-pincodes: [T] + TIMER9_CH0: + modes: [inp, out] + exclude-pincodes: [T] + TRACECK: + modes: [out] + exclude-pincodes: [T, R, C] + TRACED0: + modes: [out] + exclude-pincodes: [T, R, C] + TRACED1: + modes: [out] + exclude-pincodes: [T, R, C] + TRACED2: + modes: [out] + exclude-pincodes: [T, R, C] + TRACED3: + modes: [out] + exclude-pincodes: [T, R, C] + UART3_RX: + modes: [inp] + exclude-pincodes: [T, C] + UART3_TX: + modes: [out] + exclude-pincodes: [T, C] + UART4_RX: + modes: [inp] + exclude-pincodes: [T, C] + UART4_TX: + modes: [out] + exclude-pincodes: [T, C] + USART0_CK: + modes: [out] + USART0_CTS: + modes: [inp] + USART0_RTS: + modes: [out] + USART0_RX: + modes: [inp] + USART0_TX: + modes: [out] + USART1_CK: + modes: [out] + USART1_CTS: + modes: [inp] + USART1_RTS: + modes: [out] + USART1_RX: + modes: [inp] + USART1_TX: + modes: [out] + USART2_CK: + modes: [out] + exclude-pincodes: [T] + USART2_CTS: + modes: [inp] + exclude-pincodes: [T] + USART2_RTS: + modes: [out] + exclude-pincodes: [T] + USART2_RX: + modes: [inp] + exclude-pincodes: [T] + USART2_TX: + modes: [out] + exclude-pincodes: [T] + USBFS_DM: + modes: [inp, out] + USBFS_DP: + modes: [inp, out] + USBFS_ID: + modes: [inp, out] + USBFS_SOF: + modes: [out] + USBFS_VBUS: + modes: [inp] + WKUP: + modes: [inp] + +pins: + PA0: + pincodes: [C, V, R, T] + afs: [TIMER7_ETI, ADC01_IN0, TIMER1_CH0_ETI, TIMER4_CH0, USART1_CTS, WKUP] + PA1: + pincodes: [C, V, R, T] + afs: [TIMER1_CH1, TIMER4_CH1, ADC01_IN1, USART1_RTS] + PA2: + pincodes: [C, V, R, T] + afs: [TIMER1_CH2, ADC01_IN2, TIMER4_CH2, SPI0_IO2, TIMER8_CH0, USART1_TX] + PA3: + pincodes: [C, V, R, T] + afs: [ADC01_IN3, USART1_RX, TIMER8_CH1, TIMER4_CH3, TIMER1_CH3, SPI0_IO3] + PA4: + pincodes: [C, V, R, T] + afs: [ADC01_IN4, DAC_OUT0, SPI0_NSS, USART1_CK] + PA5: + pincodes: [C, V, R, T] + afs: [SPI0_SCK, ADC01_IN5, DAC_OUT1] + PA6: + pincodes: [C, V, R, T] + afs: [TIMER2_CH0, TIMER12_CH0, ADC01_IN6, SPI0_MISO, TIMER7_BKIN] + PA7: + pincodes: [C, V, R, T] + afs: [TIMER13_CH0, ADC01_IN7, SPI0_MOSI, TIMER2_CH1, TIMER7_CH0_ON] + PA8: + pincodes: [C, V, R, T] + afs: [CK_OUT0, USBFS_SOF, USART0_CK, VCORE, CTC_SYNC, TIMER0_CH0] + PA9: + pincodes: [C, V, R, T] + afs: [USBFS_VBUS, USART0_TX, TIMER0_CH1] + PA10: + pincodes: [C, V, R, T] + afs: [TIMER0_CH2, USART0_RX, USBFS_ID, V1REF] + PA11: + pincodes: [C, V, R, T] + afs: [USART0_CTS, TIMER0_CH3, USBFS_DM] + PA12: + pincodes: [C, V, R, T] + afs: [USBFS_DP, USART0_RTS, TIMER0_ETI] + PA13: + pincodes: [C, V, R, T] + afs: [] + PA14: + pincodes: [C, V, R, T] + afs: [] + PA15: + pincodes: [C, V, R, T] + afs: [SPI2_NSS, I2S2_WS] + PB0: + pincodes: [C, V, R, T] + afs: [ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON] + PB1: + pincodes: [C, V, R, T] + afs: [ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON] + PB2: + pincodes: [C, V, R, T] + afs: [] + PB3: + pincodes: [C, V, R, T] + afs: [SPI2_SCK, I2S2_CK] + PB4: + pincodes: [C, V, R, T] + afs: [SPI2_MISO, I2C0_TXFRAME] + PB5: + pincodes: [C, V, R, T] + afs: [I2S2_SD, SPI2_MOSI, I2C0_SMBA] + PB6: + pincodes: [C, V, R, T] + afs: [I2C0_SCL, TIMER3_CH0] + PB7: + pincodes: [C, V, R, T] + afs: [TIMER3_CH1, EXMC_NL(NADV), I2C0_SDA] + PB8: + pincodes: [C, V, R] + afs: [TIMER9_CH0, TIMER3_CH2] + PB9: + pincodes: [C, V, R] + afs: [TIMER10_CH0, TIMER3_CH3] + PB10: + pincodes: [C, V, R] + afs: [I2C1_SCL, USART2_TX] + PB11: + pincodes: [C, V, R] + afs: [USART2_RX, I2C1_SDA] + PB12: + pincodes: [C, V, R] + afs: [SPI1_NSS, TIMER0_BKIN, I2S1_WS, I2C1_SMBA, USART2_CK] + PB13: + pincodes: [C, V, R] + afs: [USART2_CTS, SPI1_SCK, I2C1_TXFRAME, TIMER0_CH0_ON, I2S1_CK] + PB14: + pincodes: [C, V, R] + afs: [USART2_RTS, TIMER11_CH0, SPI1_MISO, TIMER0_CH1_ON] + PB15: + pincodes: [C, V, R] + afs: [TIMER11_CH11, SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD] + PC0: + pincodes: [V, R] + afs: [ADC01_IN10] + PC1: + pincodes: [V, R] + afs: [ADC01_IN11] + PC2: + pincodes: [V, R] + afs: [ADC01_IN12] + PC3: + pincodes: [V, R] + afs: [ADC01_IN13] + PC4: + pincodes: [V, R] + afs: [ADC01_IN14] + PC5: + pincodes: [V, R] + afs: [ADC01_IN15] + PC6: + pincodes: [V, R] + afs: [TIMER7_CH0, I2S1_MCK] + PC7: + pincodes: [V, R] + afs: [TIMER7_CH1, I2S2_MCK] + PC8: + pincodes: [V, R] + afs: [TIMER7_CH2] + PC9: + pincodes: [V, R] + afs: [TIMER7_CH3] + PC10: + pincodes: [V, R] + afs: [UART3_TX] + PC11: + pincodes: [V, R] + afs: [UART3_RX] + PC12: + pincodes: [V, R] + afs: [UART4_TX] + PC13: + pincodes: [C, V, R] + afs: [RTC_TAMPER] + PC14: + pincodes: [C, V, R] + afs: [OSC32IN] + PC15: + pincodes: [C, V, R] + afs: [OSC32OUT] + PD0: + pincodes: [C, V, R, T] + afs: [EXMC_D2] + PD1: + pincodes: [C, V, R, T] + afs: [EXMC_D3] + PD2: + pincodes: [V, R] + afs: [UART4_RX, TIMER2_ETI] + PD3: + pincodes: [V] + afs: [EXMC_CLK] + PD4: + pincodes: [V] + afs: [EXMC_NOE] + PD5: + pincodes: [V] + afs: [EXMC_NWE] + PD6: + pincodes: [V] + afs: [EXMC_NWAIT] + PD7: + pincodes: [V] + afs: [EXMC_NE0] + PD8: + pincodes: [V] + afs: [EXMC_D13] + PD9: + pincodes: [V] + afs: [EXMC_D14] + PD10: + pincodes: [V] + afs: [EXMC_D15] + PD11: + pincodes: [V] + afs: [EXMC_A16] + PD12: + pincodes: [V] + afs: [EXMC_A17] + PD13: + pincodes: [V] + afs: [EXMC_A18] + PD14: + pincodes: [V] + afs: [EXMC_D0] + PD15: + pincodes: [V] + afs: [EXMC_D1] + PE0: + pincodes: [V] + afs: [EXMC_NBL0, TIMER3_ETI] + PE1: + pincodes: [V] + afs: [EXMC_NBL1] + PE2: + pincodes: [V] + afs: [EXMC_A23, TRACECK] + PE3: + pincodes: [V] + afs: [EXMC_A19, TRACED0] + PE4: + pincodes: [V] + afs: [EXMC_A20, TRACED1] + PE5: + pincodes: [V] + afs: [TRACED2, EXMC_A21] + PE6: + pincodes: [V] + afs: [TRACED3, EXMC_A22] + PE7: + pincodes: [V] + afs: [EXMC_D4] + PE8: + pincodes: [V] + afs: [EXMC_D5] + PE9: + pincodes: [V] + afs: [EXMC_D6] + PE10: + pincodes: [V] + afs: [EXMC_D7] + PE11: + pincodes: [V] + afs: [EXMC_D8] + PE12: + pincodes: [V] + afs: [EXMC_D9] + PE13: + pincodes: [V] + afs: [EXMC_D10] + PE14: + pincodes: [V] + afs: [EXMC_D11] + PE15: + pincodes: [V] + afs: [EXMC_D12] + +remaps: + I2C0_SCL: + pins: [PB6, PB8] + I2C0_SDA: + pins: [PB7, PB9] + I2S2_SD: + pins: [PB5, PC12] + I2S2_WS: + pins: [PA15, PA4] + I2S2_CK: + pins: [PB3, PC10] + SPI0_MISO: + pins: [PA6, PB4] + SPI0_MOSI: + pins: [PA7, PB5] + SPI0_NSS: + pins: [PA4, PA15] + SPI0_SCK: + pins: [PA5, PB3] + SPI0_IO2: + pins: [PA2, PB6] + SPI0_IO3: + pins: [PA3, PB7] + SPI2_MISO: + pins: [PB4, PC11] + SPI2_MOSI: + pins: [PB5, PC12] + SPI2_NSS: + pins: [PA15, PA4] + SPI2_SCK: + pins: [PB3, PC10] + TIMER0_BKIN: + pins: [PB12, PA6, null, PE15] + TIMER0_CH0: + pins: [PA8, PA8, null, PE9] + TIMER0_CH1: + pins: [PA9, PA9, null, PE11] + TIMER0_CH2: + pins: [PA10, PA10, null, PE13] + TIMER0_CH3: + pins: [PA11, PA11, null, PE14] + TIMER0_CH0_ON: + pins: [PB13, PA7, null, PE8] + TIMER0_CH1_ON: + pins: [PB14, PB0, null, PE10] + TIMER0_CH2_ON: + pins: [PB15, PB1, null, PE12] + TIMER0_ETI: + pins: [PA12, PA12, null, PE7] + TIMER1_CH0: + pins: [PA0, PA15, PA0, PA15] + TIMER1_CH1: + pins: [PA1, PB3, PA1, PB3] + TIMER1_CH2: + pins: [PA2, PA2, PB10, PB10] + TIMER1_CH3: + pins: [PA3, PA3, PB11, PB11] + TIMER1_ETI: + pins: [PA0, PA15, PA0, PA15] + TIMER2_CH0: + pins: [PA6, null, PB4, PC6] + TIMER2_CH1: + pins: [PA7, null, PB5, PC7] + TIMER2_CH2: + pins: [PB0, null, PB0, PC8] + TIMER2_CH3: + pins: [PB1, null, PB1, PC9] + TIMER3_CH0: + pins: [PB6, PD12] + TIMER3_CH1: + pins: [PB7, PD13] + TIMER3_CH2: + pins: [PB8, PD14] + TIMER3_CH3: + pins: [PB9, PD15] + USART0_RX: + pins: [PA10, PB7] + USART0_TX: + pins: [PA9, PB6] + USART1_CK: + pins: [PA4, PD7] + USART1_CTS: + pins: [PA0, PD3] + USART1_RTS: + pins: [PA1, PD4] + USART1_RX: + pins: [PA3, PD6] + USART1_TX: + pins: [PA2, PD5] + USART2_CK: + pins: [PB12, PC12, null, PD10] + USART2_CTS: + pins: [PB13, PB13, null, PD11] + USART2_RTS: + pins: [PB14, PB14, null, PD12] + USART2_RX: + pins: [PB11, PC11, null, PD9] + USART2_TX: + pins: [PB10, PC10, null, PD8]