diff --git a/README.md b/README.md index aff0f54..3721f48 100644 --- a/README.md +++ b/README.md @@ -22,9 +22,11 @@ Each ARM firmware library is organized in the following structure:    ├── cmsis    │   └── gd    │   └── gd32xxx -    └── standard_peripheral -    ├── include -    └── source +    ├── standard_peripheral +    │ ├── include +    │ └── source + └── support (optional) + └── GigaDevice.GD32xxx_DFP.1.0.0.pack (Only for packs not in [Keil MDK5 Software Packs](https://www.keil.com/dd2/pack/)) ``` ### RISC-V @@ -125,3 +127,19 @@ conflict resolution. See below list with the proposed solution: - i2c have different implement than current gd32 i2c driver. no need to patch upper i2c speed requirement. + +- gd32a50x + + - `SystemCoreClockUpdate` function contain an `pllmf` calculate error. + Fix by change `0xFU` to `RCU_CFG0_PLLMF`: + ``` diff + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + pllmf += ((RCU_CFG0 & RCU_CFG0_PLLMF_4) ? 15U : 0U); + - pllmf += ((0xFU == (RCU_CFG0 & RCU_CFG0_PLLMF)) ? 1U : 2U); + + pllmf += ((RCU_CFG0_PLLMF == (RCU_CFG0 & RCU_CFG0_PLLMF)) ? 1U : 2U); + ``` + - For debug this board, `pyocd` need a pack file from Gigadevice, + But Gigadevice don't upload pack file to [keil packs repo](https://www.keil.com/dd2/pack/). + Fix: Storage pack as `gd32a50x/support/GigaDevice.GD32A50x_DFP.1.0.0.pack` + (Download from https://gd32mcu.com/cn/download/7?kw=GD32A5 -> GD32A50x AddOn) diff --git a/common_include/gd32_adc.h b/common_include/gd32_adc.h index 684e80a..43ee038 100644 --- a/common_include/gd32_adc.h +++ b/common_include/gd32_adc.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_bkp.h b/common_include/gd32_bkp.h index b315f15..38aec16 100644 --- a/common_include/gd32_bkp.h +++ b/common_include/gd32_bkp.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_can.h b/common_include/gd32_can.h index 9310901..91d8066 100644 --- a/common_include/gd32_can.h +++ b/common_include/gd32_can.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E50X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E50X) #include #elif defined(CONFIG_SOC_SERIES_GD32F403) #include diff --git a/common_include/gd32_cmp.h b/common_include/gd32_cmp.h index ee45a12..45356e6 100644 --- a/common_include/gd32_cmp.h +++ b/common_include/gd32_cmp.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E50X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E50X) #include #elif defined(CONFIG_SOC_SERIES_GD32F3X0) #include diff --git a/common_include/gd32_crc.h b/common_include/gd32_crc.h index 14ba14f..6b5671d 100644 --- a/common_include/gd32_crc.h +++ b/common_include/gd32_crc.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_dac.h b/common_include/gd32_dac.h index 3b0aa4d..29c8415 100644 --- a/common_include/gd32_dac.h +++ b/common_include/gd32_dac.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_dbg.h b/common_include/gd32_dbg.h index f5ee6ba..c0410e9 100644 --- a/common_include/gd32_dbg.h +++ b/common_include/gd32_dbg.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_dma.h b/common_include/gd32_dma.h index b7d3446..2ad8f6c 100644 --- a/common_include/gd32_dma.h +++ b/common_include/gd32_dma.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_exti.h b/common_include/gd32_exti.h index eed9eb4..dbca3aa 100644 --- a/common_include/gd32_exti.h +++ b/common_include/gd32_exti.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_fmc.h b/common_include/gd32_fmc.h index 46967e3..8794d39 100644 --- a/common_include/gd32_fmc.h +++ b/common_include/gd32_fmc.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_fwdgt.h b/common_include/gd32_fwdgt.h index c1f6558..376e0a4 100644 --- a/common_include/gd32_fwdgt.h +++ b/common_include/gd32_fwdgt.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_gpio.h b/common_include/gd32_gpio.h index 6c4c4f5..585e815 100644 --- a/common_include/gd32_gpio.h +++ b/common_include/gd32_gpio.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_i2c.h b/common_include/gd32_i2c.h index f0884a1..94cbfd9 100644 --- a/common_include/gd32_i2c.h +++ b/common_include/gd32_i2c.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_mfcom.h b/common_include/gd32_mfcom.h new file mode 100644 index 0000000..4c61730 --- /dev/null +++ b/common_include/gd32_mfcom.h @@ -0,0 +1,9 @@ +/* + * NOTE: Autogenerated file using gd32headers.py + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#endif diff --git a/common_include/gd32_misc.h b/common_include/gd32_misc.h index 664b5f6..632b216 100644 --- a/common_include/gd32_misc.h +++ b/common_include/gd32_misc.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_pmu.h b/common_include/gd32_pmu.h index 36c1897..3ee8a92 100644 --- a/common_include/gd32_pmu.h +++ b/common_include/gd32_pmu.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_rcu.h b/common_include/gd32_rcu.h index 0a81344..8f2c83e 100644 --- a/common_include/gd32_rcu.h +++ b/common_include/gd32_rcu.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_rtc.h b/common_include/gd32_rtc.h index 2e17c25..c168203 100644 --- a/common_include/gd32_rtc.h +++ b/common_include/gd32_rtc.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_spi.h b/common_include/gd32_spi.h index 2286fdf..4b7d78e 100644 --- a/common_include/gd32_spi.h +++ b/common_include/gd32_spi.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_syscfg.h b/common_include/gd32_syscfg.h index 4acda46..b2d9f3f 100644 --- a/common_include/gd32_syscfg.h +++ b/common_include/gd32_syscfg.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32F3X0) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32F3X0) #include #elif defined(CONFIG_SOC_SERIES_GD32F4XX) #include diff --git a/common_include/gd32_timer.h b/common_include/gd32_timer.h index 6964588..3ff90ac 100644 --- a/common_include/gd32_timer.h +++ b/common_include/gd32_timer.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_trigsel.h b/common_include/gd32_trigsel.h new file mode 100644 index 0000000..70a6944 --- /dev/null +++ b/common_include/gd32_trigsel.h @@ -0,0 +1,9 @@ +/* + * NOTE: Autogenerated file using gd32headers.py + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#endif diff --git a/common_include/gd32_usart.h b/common_include/gd32_usart.h index d27da2b..47fc55b 100644 --- a/common_include/gd32_usart.h +++ b/common_include/gd32_usart.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/common_include/gd32_wwdgt.h b/common_include/gd32_wwdgt.h index 7c5bd5f..66164f8 100644 --- a/common_include/gd32_wwdgt.h +++ b/common_include/gd32_wwdgt.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_GD32E10X) +#if defined(CONFIG_SOC_SERIES_GD32A50X) +#include +#elif defined(CONFIG_SOC_SERIES_GD32E10X) #include #elif defined(CONFIG_SOC_SERIES_GD32E50X) #include diff --git a/gd32a50x/cmsis/gd/gd32a50x/include/gd32a50x.h b/gd32a50x/cmsis/gd/gd32a50x/include/gd32a50x.h new file mode 100644 index 0000000..4a0f0ea --- /dev/null +++ b/gd32a50x/cmsis/gd/gd32a50x/include/gd32a50x.h @@ -0,0 +1,257 @@ +/*! + \file gd32a50x.h + \brief general definitions for GD32A50x + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_H +#define GD32A50X_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if !defined (GD32A50X) +#error "Please select the target GD32A50X device used in your application (in gd32a50x.h file)" +#endif /* undefine GD32A50X tip */ + +/* define value of high speed crystal oscillator (HXTAL) in Hz */ +#if !defined HXTAL_VALUE +#define HXTAL_VALUE ((uint32_t)8000000) /*!< value of the external oscillator in Hz */ +#endif /* high speed crystal oscillator value */ + +/* define startup timeout value of high speed crystal oscillator (HXTAL) */ +#if !defined (HXTAL_STARTUP_TIMEOUT) +#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0FFFF) +#endif /* high speed crystal oscillator startup timeout */ + +/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ +#if !defined (IRC8M_VALUE) +#define IRC8M_VALUE ((uint32_t)8000000) +#endif /* internal 8MHz RC oscillator value */ + +/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ +#if !defined (IRC8M_STARTUP_TIMEOUT) +#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) +#endif /* internal 8MHz RC oscillator startup timeout */ + +/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ +#if !defined (IRC40K_VALUE) +#define IRC40K_VALUE ((uint32_t)40000) +#endif /* internal 40KHz RC oscillator value */ + +/* define value of low speed crystal oscillator (LXTAL)in Hz */ +#if !defined (LXTAL_VALUE) +#define LXTAL_VALUE ((uint32_t)32768) +#endif /* low speed crystal oscillator value */ + +/* GD32E50x firmware library version number V1.0 */ +#define __GD32A50X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __GD32A50X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __GD32A50X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __GD32A50X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __GD32A50X_STDPERIPH_VERSION ((__GD32A50X_STDPERIPH_VERSION_MAIN << 24)\ + |(__GD32A50X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__GD32A50X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__GD32A50X_STDPERIPH_VERSION_RC)) + +/* configuration of the Cortex-M33 processor and core peripherals */ +#define __CM33_REV 0x0003U /*!< Core revision r0p3 */ +#define __SAUREGION_PRESENT 0U /*!< SAU regions are not present */ +#define __MPU_PRESENT 1U /*!< MPU is present */ +#define __VTOR_PRESENT 1U /*!< VTOR is present */ +#define __NVIC_PRIO_BITS 4U /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __DSP_PRESENT 1U /*!< DSP present */ + +/* define interrupt number */ +typedef enum IRQn +{ + /* Cortex-M33 processor exceptions numbers */ + NonMaskableInt_IRQn = -14, /*!< non mask-able interrupt */ + HardFault_IRQn = -13, /*!< hard-fault interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M33 memory management interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M33 bus fault interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M33 usage fault interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M33 sv call interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M33 debug monitor interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M33 pend sv interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M33 system tick interrupt */ + /* interrupt numbers */ + WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */ + LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ + RTC_IRQn = 3, /*!< RTC Wakeup interrupt */ + FMC_IRQn = 4, /*!< FMC interrupt */ + RCU_IRQn = 5, /*!< RCU and CTC interrupt */ + EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ + EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */ + EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ + EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ + EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ + DMA0_Channel0_IRQn = 11, /*!< DMA0 channel 0 interrupt */ + DMA0_Channel1_IRQn = 12, /*!< DMA0 channel 1 interrupt */ + DMA0_Channel2_IRQn = 13, /*!< DMA0 channel 2 interrupt */ + DMA0_Channel3_IRQn = 14, /*!< DMA0 channel 3 interrupt */ + DMA0_Channel4_IRQn = 15, /*!< DMA0 channel 4 interrupt */ + DMA0_Channel5_IRQn = 16, /*!< DMA0 channel 5 interrupt */ + DMA0_Channel6_IRQn = 17, /*!< DMA0 channel 6 interrupt */ + ADC0_1_IRQn = 18, /*!< ADC0_1 interrupts */ + CAN0_Message_IRQn = 19, /*!< CAN0 message buffer interrupt */ + CAN0_Busoff_IRQn = 20, /*!< CAN0 bus off interrupt */ + CAN0_Error_IRQn = 21, /*!< CAN0 error interrupt */ + CAN0_FastError_IRQn = 22, /*!< CAN0 fast transmission error interrupt */ + CAN0_TEC_IRQn = 23, /*!< CAN0 transmit warning interrupt */ + CAN0_REC_IRQn = 24, /*!< CAN0 receive warning interrupt */ + CAN0_WKUP_IRQn = 25, /*!< CAN0 wakeup through EXTI Line detection interrupt */ + TIMER0_BRK_UP_TRG_CMT_IRQn = 26, /*!< TIMER0 break, update, trigger and commutation interrupt */ + TIMER0_Channel_IRQn = 27, /*!< TIMER0 capture compare interrupt */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER19_BRK_UP_TRG_CMT_IRQn = 29, /*!< TIMER19 break, update, trigger and commutation interrupt */ + TIMER19_Channel_IRQn = 30, /*!< TIMER19 capture compare interrupt */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI line 10 to 15 interrupts */ + EXTI5_9_IRQn = 41, /*!< EXTI line 5 to 9 interrupts */ + TAMPER_IRQn = 42, /*!< BKP Tamper interrupt */ + TIMER20_BRK_UP_TRG_CMT_IRQn = 43, /*!< TIMER20 break, update, trigger and commutation interrupt */ + TIMER20_Channel_IRQn = 44, /*!< TIMER20 capture compare interrupt */ + TIMER7_BRK_UP_TRG_CMT_IRQn = 45, /*!< TIMER7 break, update, trigger and commutation interrupt */ + TIMER7_Channel_IRQn = 46, /*!< TIMER7 capture compare interrupt */ + DMAMUX_IRQn = 47, /*!< DMAMUX interrupt */ + SRAMC_ECCSE_IRQn = 48, /*!< SYSCFG SRAM ECC single err interrupt */ + CMP_IRQn = 49, /*!< Comparator interrupt */ + OVD_IRQn = 51, /*!< Over voltage detector interrupt */ + TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC interrupt */ + TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel 0 interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel 1 interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel 2 interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel 3 interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel 4 interrupt */ + CAN1_WKUP_IRQn = 62, /*!< CAN1 wakeup through EXTI Line detection interrupt */ + CAN1_Message_IRQn = 63, /*!< CAN1 message buffer interrupt */ + CAN1_Busoff_IRQn = 64, /*!< CAN1 bus off interrupt */ + CAN1_Error_IRQn = 65, /*!< CAN1 error interrupt */ + CAN1_FastError_IRQn = 66, /*!< CAN1 fast transmission error interrupt */ + CAN1_TEC_IRQn = 67, /*!< CAN1 transmit warning interrupt */ + CAN1_REC_IRQn = 68, /*!< CAN1 receive warning interrupt */ + FPU_IRQn = 69, /*!< FPU interrupt */ + MFCOM_IRQn = 70 /*!< MFCOM interrupt */ +} IRQn_Type; + +/* includes */ +#include "core_cm33.h" +#include "system_gd32a50x.h" +#include + +/* enum definitions */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; +typedef enum {RESET = 0, SET = !RESET} FlagStatus; +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + +/* bit operations */ +#define REG64(addr) (*(volatile uint64_t *)(uint32_t)(addr)) +#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) +#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) +#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) +#ifndef BIT +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +#endif /* BIT */ +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) + +/* main flash and SRAM memory map */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */ + +/* peripheral memory map */ +#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ +#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ +#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ +#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb3 base address */ + +/* advanced peripheral bus 1 memory map */ +#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ +#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ +#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ +#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ +#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ +#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ +#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ +#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ +#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ +#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ + +/* advanced peripheral bus 2 memory map */ +#define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */ +#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ +#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ +#define CMP_BASE (APB2_BUS_BASE + 0x00007C00U) /*!< CMP base address */ +#define TRIGSEL_BASE (APB2_BUS_BASE + 0x00008400U) /*!< TRIGSEL base address */ +#define CAN_BASE (APB2_BUS_BASE + 0x0000A000U) /*!< CAN base address */ + +/* advanced high performance bus 1 memory map */ +#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */ +#define DMAMUX_BASE (AHB1_BUS_BASE + 0x00000800U) /*!< DMAMUX base address */ +#define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */ +#define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */ +#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */ +#define MFCOM_BASE (AHB1_BUS_BASE + 0x00018400U) /*!< MFCOM base address */ + +/* advanced high performance bus 2 memory map */ +#define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */ + +/* option byte and debug memory map */ +#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ + +#define DBG_BASE ((uint32_t)0xE0044000U) /*!< DBG base address */ + +/* define marco USE_STDPERIPH_DRIVER */ +#if !defined USE_STDPERIPH_DRIVER +#define USE_STDPERIPH_DRIVER +#endif +#ifdef USE_STDPERIPH_DRIVER +#include "gd32a50x_libopt.h" +#endif /* USE_STDPERIPH_DRIVER */ + +#ifdef __cplusplus +} +#endif + +#endif /* GD32A50X_H */ diff --git a/gd32a50x/cmsis/gd/gd32a50x/include/system_gd32a50x.h b/gd32a50x/cmsis/gd/gd32a50x/include/system_gd32a50x.h new file mode 100644 index 0000000..4ce71da --- /dev/null +++ b/gd32a50x/cmsis/gd/gd32a50x/include/system_gd32a50x.h @@ -0,0 +1,58 @@ +/*! + \file system_gd32a50x.h + \brief CMSIS Cortex-M33 Device Peripheral Access Layer Header File for + GD32A50X Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#ifndef SYSTEM_GD32A50X_H +#define SYSTEM_GD32A50X_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* system clock frequency (core clock) */ +extern uint32_t SystemCoreClock; + +/* function declarations */ +/* initialize the system and update the SystemCoreClock variable */ +extern void SystemInit(void); +/* update the SystemCoreClock with current core clock retrieved from CPU registers */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_GD32A50X_H */ diff --git a/gd32a50x/cmsis/gd/gd32a50x/source/system_gd32a50x.c b/gd32a50x/cmsis/gd/gd32a50x/source/system_gd32a50x.c new file mode 100644 index 0000000..435329e --- /dev/null +++ b/gd32a50x/cmsis/gd/gd32a50x/source/system_gd32a50x.c @@ -0,0 +1,827 @@ +/*! + \file system_gd32a50x.c + \brief CMSIS Cortex-M33 Device Peripheral Access Layer Source File for + GD32A50X Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32a50x.h" + +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ + +#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */ + +/* select a system clock by uncommenting the following line */ +/* use IRC8M */ +//#define __SYSTEM_CLOCK_IRC8M (uint32_t)(__IRC8M) +//#define __SYSTEM_CLOCK_24M_PLL_IRC8M (uint32_t)(24000000) +//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_100M_PLL_IRC8M (uint32_t)(100000000) + +/* use HXTAL(CK_HXTAL = 8M)*/ +//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL) +//#define __SYSTEM_CLOCK_24M_PLL_HXTAL (uint32_t)(24000000) +//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +#define __SYSTEM_CLOCK_100M_PLL_HXTAL (uint32_t)(100000000) + + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_IRC8M +uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC8M; +static void system_clock_8m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_24M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_IRC8M; +static void system_clock_24m_pll_irc8m(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; +static void system_clock_48m_pll_irc8m(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; +static void system_clock_72m_pll_irc8m(void); +#elif defined (__SYSTEM_CLOCK_100M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_100M_PLL_IRC8M; +static void system_clock_100m_pll_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; +static void system_clock_hxtal(void); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL; +static void system_clock_24m_pll_hxtal(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; +static void system_clock_48m_pll_hxtal(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_pll_hxtal(void); +#elif defined (__SYSTEM_CLOCK_100M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_100M_PLL_HXTAL; +static void system_clock_100m_pll_hxtal(void); +#endif /* __SYSTEM_CLOCK_IRC8M */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief setup the micro-controller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit(void) +{ + /* FPU settings */ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ +#endif + /* reset the RCU clock configuration to the default reset state */ + /* set IRC8MEN bit */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + RCU_CFG0 &= ~RCU_CFG0_SCS; + /* reset HXTALSCAL, LCKMEN, PLLMEN, PLLEN, CKMEN and HXTALEN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN | RCU_CTL_HXTALSCAL | RCU_CTL_LCKMEN | RCU_CTL_PLLMEN); + /* disable all interrupts */ + RCU_INT = 0x00FF0000U; + + /* Reset CFG0 and CFG1 registers */ + RCU_CFG0 = 0x00020000U; + RCU_CFG1 = 0x00000000U; + + /* reset HXTALBPS bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* configure the system clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ + system_clock_config(); + + /* LXTALBPS configuration */ + if(0U == (RCU_APB1EN & RCU_APB1EN_PMUEN)) { + /* check whether PMU clock is enabled */ + RCU_APB1EN |= RCU_APB1EN_PMUEN; + if(0U == (PMU_CTL & PMU_CTL_BKPWEN)) { + /* BKPWEN bit is not been set */ + PMU_CTL |= PMU_CTL_BKPWEN; + /* LXTALBPS bit must be configured to 1 */ + RCU_BDCTL |= RCU_BDCTL_LXTALBPS; + /* clear the BKPWEN bit */ + PMU_CTL &= ~PMU_CTL_BKPWEN; + } else { + /* LXTALBPS bit must be configured to 1 */ + RCU_BDCTL |= RCU_BDCTL_LXTALBPS; + } + + /* disable the PMU clock */ + RCU_APB1EN &= ~RCU_APB1EN_PMUEN; + } else { + /* the PMU clock is already enabled */ + if(0U == (PMU_CTL & PMU_CTL_BKPWEN)) { + /* BKPWEN bit is not been set */ + PMU_CTL |= PMU_CTL_BKPWEN; + /* LXTALBPS bit must be configured to 1 */ + RCU_BDCTL |= RCU_BDCTL_LXTALBPS; + /* clear the BKPWEN bit */ + PMU_CTL &= ~PMU_CTL_BKPWEN; + } else { + /* LXTALBPS bit must be configured to 1 */ + RCU_BDCTL |= RCU_BDCTL_LXTALBPS; + } + } +} + +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_IRC8M + system_clock_8m_irc8m(); +#elif defined (__SYSTEM_CLOCK_24M_PLL_IRC8M) + system_clock_24m_pll_irc8m(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) + system_clock_48m_pll_irc8m(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) + system_clock_72m_pll_irc8m(); +#elif defined (__SYSTEM_CLOCK_100M_PLL_IRC8M) + system_clock_100m_pll_irc8m(); + +#elif defined (__SYSTEM_CLOCK_HXTAL) + system_clock_hxtal(); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) + system_clock_24m_pll_hxtal(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) + system_clock_48m_pll_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_pll_hxtal(); +#elif defined (__SYSTEM_CLOCK_100M_PLL_HXTAL) + system_clock_100m_pll_hxtal(); +#endif /* __SYSTEM_CLOCK_IRC8M */ +} + +#ifdef __SYSTEM_CLOCK_IRC8M +/*! + \brief configure the system clock to 8M by IRC8M + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_8m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) { + while(1) { + } + } + + FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(0); + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/1 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; + + /* select IRC8M as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_IRC8M; + + /* wait until IRC8M is selected as system clock */ + while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_IRC8M) { + } +} +/*! + \brief configure the system clock to 24M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +#elif defined (__SYSTEM_CLOCK_24M_PLL_IRC8M) +static void system_clock_24m_pll_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) { + while(1) { + } + } + + FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(0); + + /* LDO output voltage high mode */ + RCU_APB1EN |= RCU_APB1EN_PMUEN; + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 6 = 24 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL6; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { + } +} + + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +/*! + \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_pll_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) { + while(1) { + } + } + + FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(1); + + /* LDO output voltage high mode */ + RCU_APB1EN |= RCU_APB1EN_PMUEN; + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL12; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_pll_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) { + while(1) { + } + } + + FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(2); + + /* LDO output voltage high mode */ + RCU_APB1EN |= RCU_APB1EN_PMUEN; + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL18; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { + } +} + +#elif defined (__SYSTEM_CLOCK_100M_PLL_IRC8M) +/*! + \brief configure the system clock to 100M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_100m_pll_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) { + while(1) { + } + } + + FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(3); + + /* LDO output voltage high mode */ + RCU_APB1EN |= RCU_APB1EN_PMUEN; + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 25 = 100 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL25; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { + } +} + +#elif defined (__SYSTEM_CLOCK_HXTAL) +/*! + \brief configure the system clock to HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while(1) { + } + } + + FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(0); + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/1 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_HXTAL) { + } +} + +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +/*! + \brief configure the system clock to 24M by PLL which selects HXTAL as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_24m_pll_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while(1) { + } + } + + FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(0); + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (HXTAL / 2) * 6 = 24 MHz */ + RCU_CFG1 |= RCU_PREDV_DIV2; + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +/*! + \brief configure the system clock to 48M by PLL which selects HXTAL as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_pll_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while(1) { + } + } + + FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(1); + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (HXTAL / 2) * 12 = 48 MHz */ + RCU_CFG1 |= RCU_PREDV_DIV2; + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_pll_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while(1) { + } + } + + FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(2); + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (HXTAL / 2) * 18 = 72 MHz */ + RCU_CFG1 |= RCU_PREDV_DIV2; + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { + } +} + +#elif defined (__SYSTEM_CLOCK_100M_PLL_HXTAL) +/*! + \brief configure the system clock to 100M by PLL which selects HXTAL as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_100m_pll_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while(1) { + } + } + + FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(3); + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (HXTAL / 2) * 25 = 100 MHz */ + RCU_CFG1 |= RCU_PREDV_DIV2; + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL25); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_PLL) { + } +} +#endif /* __SYSTEM_CLOCK_IRC8M */ + +/*! + \brief update the SystemCoreClock with current core clock retrieved from CPU registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate(void) +{ + uint32_t sws; + uint32_t pllsel, pllmf, ck_src, idx, clk_exp; + uint32_t predv0; + + /* exponent of AHB, APB1 and APB2 clock divider */ + uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + sws = RCU_CFG0 & RCU_CFG0_SCSS; + switch(sws) { + /* IRC8M is selected as CK_SYS */ + case RCU_SCSS_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case RCU_SCSS_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + /* PLL is selected as CK_SYS */ + case RCU_SCSS_PLL: + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + if(RCU_PLLSRC_HXTAL == pllsel) { + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV) + 1U; + ck_src /= predv0; + } else { + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE / 2U; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + pllmf += ((RCU_CFG0 & RCU_CFG0_PLLMF_4) ? 15U : 0U); + pllmf += ((RCU_CFG0_PLLMF == (RCU_CFG0 & RCU_CFG0_PLLMF)) ? 1U : 2U); + + SystemCoreClock = ck_src * pllmf; + + break; + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } + + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + SystemCoreClock >>= clk_exp; +} diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_adc.h b/gd32a50x/standard_peripheral/include/gd32a50x_adc.h new file mode 100644 index 0000000..ada21f8 --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_adc.h @@ -0,0 +1,430 @@ +/*! + \file gd32a50x_adc.h + \brief definitions for the ADC + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_ADC_H +#define GD32A50X_ADC_H + +#include "gd32a50x.h" + +/* ADC definitions */ +#define ADC0 ADC_BASE +#define ADC1 (ADC_BASE + 0x00000400U) + +/* registers definitions */ +#define ADC_STAT(adcx) REG32((adcx) + 0x00000000U) /*!< ADC status register */ +#define ADC_CTL0(adcx) REG32((adcx) + 0x00000004U) /*!< ADC control register 0 */ +#define ADC_CTL1(adcx) REG32((adcx) + 0x00000008U) /*!< ADC control register 1 */ +#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0000000CU) /*!< ADC sampling time register 0 */ +#define ADC_SAMPT1(adcx) REG32((adcx) + 0x00000010U) /*!< ADC sampling time register 1 */ +#define ADC_IOFF0(adcx) REG32((adcx) + 0x00000014U) /*!< ADC inserted channel data offset register 0 */ +#define ADC_IOFF1(adcx) REG32((adcx) + 0x00000018U) /*!< ADC inserted channel data offset register 1 */ +#define ADC_IOFF2(adcx) REG32((adcx) + 0x0000001CU) /*!< ADC inserted channel data offset register 2 */ +#define ADC_IOFF3(adcx) REG32((adcx) + 0x00000020U) /*!< ADC inserted channel data offset register 3 */ +#define ADC_WDHT0(adcx) REG32((adcx) + 0x00000024U) /*!< ADC watchdog high threshold register 0 */ +#define ADC_WDLT0(adcx) REG32((adcx) + 0x00000028U) /*!< ADC watchdog low threshold register 0 */ +#define ADC_RSQ0(adcx) REG32((adcx) + 0x0000002CU) /*!< ADC regular sequence register 0 */ +#define ADC_RSQ1(adcx) REG32((adcx) + 0x00000030U) /*!< ADC regular sequence register 1 */ +#define ADC_RSQ2(adcx) REG32((adcx) + 0x00000034U) /*!< ADC regular sequence register 2 */ +#define ADC_ISQ(adcx) REG32((adcx) + 0x00000038U) /*!< ADC inserted sequence register */ +#define ADC_IDATA0(adcx) REG32((adcx) + 0x0000003CU) /*!< ADC inserted data register 0 */ +#define ADC_IDATA1(adcx) REG32((adcx) + 0x00000040U) /*!< ADC inserted data register 1 */ +#define ADC_IDATA2(adcx) REG32((adcx) + 0x00000044U) /*!< ADC inserted data register 2 */ +#define ADC_IDATA3(adcx) REG32((adcx) + 0x00000048U) /*!< ADC inserted data register 3 */ +#define ADC_RDATA(adcx) REG32((adcx) + 0x0000004CU) /*!< ADC regular data register */ +#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x00000080U) /*!< ADC oversampling control register */ +#define ADC_WD1SR(adcx) REG32((adcx) + 0x000000A0U) /*!< ADC watchdog 1 channel selection register */ +#define ADC_WDT1(adcx) REG32((adcx) + 0x000000A8U) /*!< ADC watchdog threshold register 1 */ + +/* bits definitions */ +/* ADC_STAT */ +#define ADC_STAT_WDE0 BIT(0) /*!< analog watchdog 0 event flag */ +#define ADC_STAT_EOC BIT(1) /*!< end of group conversion flag */ +#define ADC_STAT_EOIC BIT(2) /*!< end of inserted group conversion flag */ +#define ADC_STAT_STIC BIT(3) /*!< start flag of inserted channel group */ +#define ADC_STAT_STRC BIT(4) /*!< start flag of regular channel group */ +#define ADC_STAT_WDE1 BIT(30) /*!< analog watchdog 1 event flag */ + +/* ADC_CTL0 */ +#define ADC_CTL0_WD0CHSEL BITS(0, 4) /*!< analog watchdog 0 channel select bits */ +#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ +#define ADC_CTL0_WDE0IE BIT(6) /*!< analog watchdog 0 interrupt enable */ +#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ +#define ADC_CTL0_SM BIT(8) /*!< scan mode */ +#define ADC_CTL0_WD0SC BIT(9) /*!< when in scan mode, analog watchdog 0 is effective on a single channel */ +#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ +#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ +#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +#define ADC_CTL0_DISNUM BITS(13, 15) /*!< discontinuous mode channel count */ +#define ADC_CTL0_SYNCM BITS(16, 19) /*!< sync mode selection */ +#define ADC_CTL0_IWD0EN BIT(22) /*!< analog watchdog 0 enable on inserted channels */ +#define ADC_CTL0_RWD0EN BIT(23) /*!< analog watchdog 0 enable on regular channels */ +#define ADC_CTL0_WDE1IE BIT(30) /*!< analog watchdog 1 interrupt enable */ + +/* ADC_CTL1 */ +#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ +#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ +#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ +#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ +#define ADC_CTL1_DMA BIT(8) /*!< DMA request enable */ +#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +#define ADC_CTL1_ETSIC BIT(12) /*!< external trigger select for inserted channel */ +#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ +#define ADC_CTL1_ETSRC BIT(17) /*!< external trigger select for regular channel */ +#define ADC_CTL1_ETERC BIT(20) /*!< external trigger enable for regular channel */ +#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ +#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ +#define ADC_CTL1_TSVEN BIT(23) /*!< channel 16 enable of ADC0 */ +#define ADC_CTL1_INREFEN BIT(24) /*!< channel 17 enable of ADC0 */ + +/* ADC_SAMPTx x=0..1 */ +#define ADC_SAMPTX_SPTN BITS(0, 2) /*!< channel n(n=0..17) sample time selection */ + +/* ADC_IOFFx x=0..3 */ +#define ADC_IOFFX_IOFF BITS(0, 11) /*!< data offset for inserted channel x */ + +/* ADC_WDHT */ +#define ADC_WDHT0_WDHT0 BITS(0, 11) /*!< analog watchdog 0 high threshold */ + +/* ADC_WDLT */ +#define ADC_WDLT0_WDLT0 BITS(0, 11) /*!< analog watchdog 0 low threshold */ + +/* ADC_RSQx x=0..2 */ +#define ADC_RSQX_RSQN BITS(0, 4) /*!< n conversion in regular sequence */ +#define ADC_RSQ0_RL BITS(20, 23) /*!< regular channel sequence length */ + +/* ADC_ISQ */ +#define ADC_ISQ_ISQN BITS(0, 4) /*!< n conversion in regular sequence */ +#define ADC_ISQ_IL BITS(20, 21) /*!< inserted sequence length */ + +/* ADC_IDATAx x=0..3 */ +#define ADC_IDATAX_IDATAN BITS(0, 15) /*!< inserted channel x conversion data */ + +/* ADC_RDATA */ +#define ADC_RDATA_RDATA BITS(0, 15) /*!< regular data */ +#define ADC_RDATA_ADC1RDTR BITS(16, 31) /*!< ADC1 regular channel data */ + +/* ADC_OVSAMPCTL */ +#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ +#define ADC_OVSAMPCTL_OVSR BITS(2, 4) /*!< oversampling ratio */ +#define ADC_OVSAMPCTL_OVSS BITS(5, 8) /*!< oversampling shift */ +#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ +#define ADC_OVSAMPCTL_DRES BITS(12, 13) /*!< ADC resolution */ + +/* ADC_WD1SR */ +#define ADC_WD1SR_AWD1CS BITS(0, 17) /*!< analog watchdog 1 channel selection */ + +/* ADC_WDT1 */ +#define ADC_WDT1_WDLT1 BITS(0, 7) /*!< analog watchdog 1 low threshold */ +#define ADC_WDT1_WDHT1 BITS(16, 23) /*!< analog watchdog 1 high threshold */ + +/* constants definitions */ +/* ADC flag definitions */ +#define ADC_FLAG_WDE0 ADC_STAT_WDE0 /*!< analog watchdog 0 event flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ +#define ADC_FLAG_WDE1 ADC_STAT_WDE1 /*!< analog watchdog 1 event flag */ + +/* configure number of conversions in discontinuous mode */ +#define CTL0_DISNUM(regval) (BITS(13, 15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ + +/* ADC special function definitions */ +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ + +/* ADC synchronization mode */ +#define CTL0_SYNCM(regval) (BITS(16, 19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ +#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ +#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ +#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ +#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ +#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ +#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ +#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ +#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ + +/* ADC data alignment */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ + +/* ADC external trigger select for regular channel */ +#define ADC0_1_EXTTRIG_REGULAR_TRIGSEL ((uint32_t)0x00000000U) /*!< TRIGSEL trigger */ +#define ADC0_1_EXTTRIG_REGULAR_NONE ADC_CTL1_ETSRC /*!< software trigger */ + +/* ADC external trigger select for inserted channel */ +#define ADC0_1_EXTTRIG_INSERTED_TRIGSEL ((uint32_t)0x00000000U) /*!< TRIGSEL trigger */ +#define ADC0_1_EXTTRIG_INSERTED_NONE ADC_CTL1_ETSIC /*!< software trigger */ + +/* ADC_SAMPTX register value */ +#define SAMPTX_SPT(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ +#define ADC_SAMPLETIME_2POINT5 SAMPTX_SPT(0) /*!< 2.5 sampling cycles */ +#define ADC_SAMPLETIME_14POINT5 SAMPTX_SPT(1) /*!< 14.5 sampling cycles */ +#define ADC_SAMPLETIME_27POINT5 SAMPTX_SPT(2) /*!< 27.5 sampling cycles */ +#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(3) /*!< 55.5 sampling cycles */ +#define ADC_SAMPLETIME_83POINT5 SAMPTX_SPT(4) /*!< 83.5 sampling cycles */ +#define ADC_SAMPLETIME_111POINT5 SAMPTX_SPT(5) /*!< 111.5 sampling cycles */ +#define ADC_SAMPLETIME_143POINT5 SAMPTX_SPT(6) /*!< 143.5 sampling cycles */ +#define ADC_SAMPLETIME_479POINT5 SAMPTX_SPT(7) /*!< 479.5 sampling cycles */ + +/* ADC data offset for inserted channel x */ +#define IOFFX_IOFF(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) + +/* ADC analog watchdog 0 high threshold */ +#define WDHT0_WDHT0(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) + +/* ADC analog watchdog 0 low threshold */ +#define WDLT0_WDLT0(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) + +/* ADC analog watchdog 1 high threshold */ +#define WDT1_WDHT1(regval) (BITS(16, 23) & ((uint32_t)(regval) << 16)) + +/* ADC analog watchdog 1 low threshold */ +#define WDT1_WDLT1(regval) (BITS(0, 7) & ((uint32_t)(regval) << 0)) + +/* ADC regular channel group length */ +#define RSQ0_RL(regval) (BITS(20, 23) & ((uint32_t)(regval) << 20)) + +/* ADC inserted channel group length */ +#define ISQ_IL(regval) (BITS(20, 21) & ((uint32_t)(regval) << 20)) + +/* adc_ovsampctl register value */ +/* ADC resolution */ +#define OVSAMPCTL_DRES(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */ +#define ADC_RESOLUTION_12B OVSAMPCTL_DRES(0) /*!< 12-bit ADC resolution */ +#define ADC_RESOLUTION_10B OVSAMPCTL_DRES(1) /*!< 10-bit ADC resolution */ +#define ADC_RESOLUTION_8B OVSAMPCTL_DRES(2) /*!< 8-bit ADC resolution */ +#define ADC_RESOLUTION_6B OVSAMPCTL_DRES(3) /*!< 6-bit ADC resolution */ + +/* oversampling shift */ +#define OVSAMPCTL_OVSS(regval) (BITS(5, 8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ +#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ + +/* oversampling ratio */ +#define OVSAMPCTL_OVSR(regval) (BITS(2, 4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ +#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ +#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ +#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ +#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ +#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ +#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ +#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ +#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ + +/* triggered oversampling */ +#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ +#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ + +/* ADC channel group definitions */ +#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */ +#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ + +/* ADC inserted channel definitions */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */ + +/* ADC channel definitions */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ +#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ +#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ +#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ +#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ +#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ + +/* analog watchdog 1 channel selection for channel n(n=0..17) */ +#define ADC_AWD1_SELECTION_CHANNEL_0 ((uint32_t)0x00000001U) /*!< ADC channel 0 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_1 ((uint32_t)0x00000002U) /*!< ADC channel 1 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_2 ((uint32_t)0x00000004U) /*!< ADC channel 2 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_3 ((uint32_t)0x00000008U) /*!< ADC channel 3 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_4 ((uint32_t)0x00000010U) /*!< ADC channel 4 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_5 ((uint32_t)0x00000020U) /*!< ADC channel 5 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_6 ((uint32_t)0x00000040U) /*!< ADC channel 6 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_7 ((uint32_t)0x00000080U) /*!< ADC channel 7 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_8 ((uint32_t)0x00000100U) /*!< ADC channel 8 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_9 ((uint32_t)0x00000200U) /*!< ADC channel 9 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_10 ((uint32_t)0x00000400U) /*!< ADC channel 10 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_11 ((uint32_t)0x00000800U) /*!< ADC channel 11 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_12 ((uint32_t)0x00001000U) /*!< ADC channel 12 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_13 ((uint32_t)0x00002000U) /*!< ADC channel 13 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_14 ((uint32_t)0x00004000U) /*!< ADC channel 14 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_15 ((uint32_t)0x00008000U) /*!< ADC channel 15 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_16 ((uint32_t)0x00010000U) /*!< ADC channel 16 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_17 ((uint32_t)0x00020000U) /*!< ADC channel 17 analog watchdog 1 selection */ +#define ADC_AWD1_SELECTION_CHANNEL_ALL ((uint32_t)0x0003FFFFU) /*!< all ADC channels analog watchdog 1 selection */ + +/* ADC interrupt */ +#define ADC_INT_WDE0 ADC_STAT_WDE0 /*!< analog watchdog 0 event interrupt */ +#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ +#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ +#define ADC_INT_WDE1 ADC_STAT_WDE1 /*!< analog watchdog 1 event interrupt */ + +/* ADC interrupt flag */ +#define ADC_INT_FLAG_WDE0 ADC_STAT_WDE0 /*!< analog watchdog 0 event interrupt flag */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ +#define ADC_INT_FLAG_WDE1 ADC_STAT_WDE1 /*!< analog watchdog 1 event interrupt flag */ + +/* function declarations */ + +/* ADC deinitialization and initialization functions */ +/* reset ADC */ +void adc_deinit(uint32_t adc_periph); +/* enable ADC interface */ +void adc_enable(uint32_t adc_periph); +/* disable ADC interface */ +void adc_disable(uint32_t adc_periph); + +/* ADC calibration and DMA functions */ +/* ADC calibration and reset calibration */ +void adc_calibration_enable(uint32_t adc_periph); +/* enable DMA request */ +void adc_dma_mode_enable(uint32_t adc_periph); +/* disable DMA request */ +void adc_dma_mode_disable(uint32_t adc_periph); + +/* configure ADC temperature sensor and vrefint channel */ +/* enable the temperature sensor channel */ +void adc_tempsensor_enable(void); +/* disable the temperature sensor channel */ +void adc_tempsensor_disable(void); +/* enable vrefint channel */ +void adc_vrefint_enable(void); +/* disable vrefint channel */ +void adc_vrefint_disable(void); + +/* ADC special function functions */ +/* configure ADC discontinuous mode */ +void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length); +/* configure the ADC0 mode */ +void adc_mode_config(uint32_t mode); +/* configure ADC special function */ +void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue); + +/* ADC channel configuration functions */ +/* configure ADC data alignment */ +void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment); +/* configure the length of regular channel group or inserted channel group */ +void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length); +/* configure ADC regular channel */ +void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); +/* configure ADC inserted channel */ +void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); +/* configure ADC inserted channel offset */ +void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); + + +/* ADC external trigger functions */ +/* configure ADC external trigger */ +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); +/* configure ADC external trigger source */ +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); +/* enable ADC software trigger */ +void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group); + +/* ADC data read functions */ +/* read ADC regular group data register */ +uint16_t adc_regular_data_read(uint32_t adc_periph); +/* read ADC inserted group data register */ +uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); +/* read the last ADC0 and ADC1 conversion result data in sync mode */ +uint32_t adc_sync_mode_convert_value_read(void); + +/* ADC analog watchdog functions */ +/* configure ADC analog watchdog 0 single channel */ +void adc_watchdog0_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); +/* configure ADC analog watchdog 0 group channel */ +void adc_watchdog0_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); +/* disable ADC analog watchdog 0 */ +void adc_watchdog0_disable(uint32_t adc_periph); +/* configure ADC analog watchdog 1 channel */ +void adc_watchdog1_channel_config(uint32_t adc_periph, uint32_t adc_channel, ControlStatus newvalue); +/* disable ADC analog watchdog 1 */ +void adc_watchdog1_disable(uint32_t adc_periph); +/* configure ADC analog watchdog 0 threshold */ +void adc_watchdog0_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold); +/* configure ADC analog watchdog 1 threshold */ +void adc_watchdog1_threshold_config(uint32_t adc_periph , uint8_t low_threshold , uint8_t high_threshold); + +/* ADC resolution and oversample functions */ +/* configure ADC resolution */ +void adc_resolution_config(uint32_t adc_periph , uint32_t resolution); +/* configure ADC oversample mode */ +void adc_oversample_mode_config(uint32_t adc_periph , uint32_t mode , uint16_t shift , uint8_t ratio); +/* enable ADC oversample mode */ +void adc_oversample_mode_enable(uint32_t adc_periph); +/* disable ADC oversample mode */ +void adc_oversample_mode_disable(uint32_t adc_periph); + +/* flag and interrupt functions */ +/* get the ADC flag */ +FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t flag); +/* clear the ADC flag */ +void adc_flag_clear(uint32_t adc_periph , uint32_t flag); +/* enable ADC interrupt */ +void adc_interrupt_enable(uint32_t adc_periph , uint32_t interrupt); +/* disable ADC interrupt */ +void adc_interrupt_disable(uint32_t adc_periph , uint32_t interrupt); +/* get the ADC interrupt */ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t int_flag); +/* clear the ADC flag */ +void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t int_flag); + +#endif /* GD32A50X_ADC_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_bkp.h b/gd32a50x/standard_peripheral/include/gd32a50x_bkp.h new file mode 100644 index 0000000..61993ed --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_bkp.h @@ -0,0 +1,184 @@ +/*! + \file gd32a50x_bkp.h + \brief definitions for the BKP + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_BKP_H +#define GD32A50X_BKP_H + +#include "gd32a50x.h" + +/* BKP definitions */ +#define BKP BKP_BASE /*!< BKP base address */ + +/* registers definitions */ +#define BKP_DATA0 REG16((BKP) + 0x0004U) /*!< BKP data register 0 */ +#define BKP_DATA1 REG16((BKP) + 0x0008U) /*!< BKP data register 1 */ +#define BKP_DATA2 REG16((BKP) + 0x000CU) /*!< BKP data register 2 */ +#define BKP_DATA3 REG16((BKP) + 0x0010U) /*!< BKP data register 3 */ +#define BKP_DATA4 REG16((BKP) + 0x0014U) /*!< BKP data register 4 */ +#define BKP_DATA5 REG16((BKP) + 0x0018U) /*!< BKP data register 5 */ +#define BKP_DATA6 REG16((BKP) + 0x001CU) /*!< BKP data register 6 */ +#define BKP_DATA7 REG16((BKP) + 0x0020U) /*!< BKP data register 7 */ +#define BKP_DATA8 REG16((BKP) + 0x0024U) /*!< BKP data register 8 */ +#define BKP_DATA9 REG16((BKP) + 0x0028U) /*!< BKP data register 9 */ +#define BKP_OCTL REG16((BKP) + 0x002CU) /*!< RTC signal output control register */ +#define BKP_TPCTL REG16((BKP) + 0x0030U) /*!< tamper pin control register */ +#define BKP_TPCS REG16((BKP) + 0x0034U) /*!< tamper control and status register */ + +/* bits definitions */ +/* BKP_DATA */ +#define BKP_DATA BITS(0,15) /*!< backup data */ + +/* BKP_OCTL */ +#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ +#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ +#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ +#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ +#define BKP_OCTL_CCOSEL BIT(14) /*!< RTC clock output selection */ +#define BKP_OCTL_CALDIR BIT(15) /*!< RTC clock calibration direction */ + +/* BKP_TPCTL */ +#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */ +#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */ +#define BKP_TPCTL_PCSEL BIT(15) /*!< OSC32IN pin select */ + +/* BKP_TPCS */ +#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */ +#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */ +#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */ +#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */ +#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */ + +/* constants definitions */ +/* BKP register */ +#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U) + +/* get data of BKP data register */ +#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) + +/* RTC clock calibration value */ +#define OCTL_RCCV(regval) (BITS(0,6) & (uint32_t)(regval)) + +/* RTC output selection */ +#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ +#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */ + +/* RTC clock output selection */ +#define RTC_CLOCK_DIV_64 ((uint16_t)0x0000U) /*!< RTC clock div 64 */ +#define RTC_CLOCK_DIV_1 ((uint16_t)0x4000U) /*!< RTC clock div 1 */ + +/* RTC clock calibration direction */ +#define RTC_CLOCK_SLOWED_DOWN ((uint16_t)0x0000U) /*!< RTC clock slow down */ +#define RTC_CLOCK_SPEED_UP ((uint16_t)0x8000U) /*!< RTC clock speed up */ + +/* OSC32IN pin select */ +#define OSC32IN_PC13 ((uint16_t)0x0000U) /*!< OSC32IN pin is PC13 */ +#define OSC32IN_PC14 ((uint16_t)0x8000U) /*!< OSC32IN pin is PC14 */ + +/* tamper pin active level */ +#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */ +#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */ + +/* tamper flag */ +#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */ + +/* tamper interrupt flag */ +#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */ + +/* BKP data register number */ +typedef enum +{ + BKP_DATA_0 = 1, /*!< BKP data register 0 */ + BKP_DATA_1, /*!< BKP data register 1 */ + BKP_DATA_2, /*!< BKP data register 2 */ + BKP_DATA_3, /*!< BKP data register 3 */ + BKP_DATA_4, /*!< BKP data register 4 */ + BKP_DATA_5, /*!< BKP data register 5 */ + BKP_DATA_6, /*!< BKP data register 6 */ + BKP_DATA_7, /*!< BKP data register 7 */ + BKP_DATA_8, /*!< BKP data register 8 */ + BKP_DATA_9, /*!< BKP data register 9 */ +}bkp_data_register_enum; + +/* function declarations */ +/* reset BKP registers */ +void bkp_deinit(void); +/* write BKP data register */ +void bkp_data_write(bkp_data_register_enum register_number, uint16_t data); +/* read BKP data register */ +uint16_t bkp_data_read(bkp_data_register_enum register_number); + +/* RTC related functions */ +/* enable RTC clock calibration output */ +void bkp_rtc_calibration_output_enable(void); +/* disable RTC clock calibration output */ +void bkp_rtc_calibration_output_disable(void); +/* enable RTC alarm or second signal output */ +void bkp_rtc_signal_output_enable(void); +/* disable RTC alarm or second signal output */ +void bkp_rtc_signal_output_disable(void); +/* select RTC output */ +void bkp_rtc_output_select(uint16_t outputsel); +/* select RTC clock output */ +void bkp_rtc_clock_output_select(uint16_t clocksel); +/* RTC clock calibration direction */ +void bkp_rtc_clock_calibration_direction(uint16_t direction); +/* set RTC clock calibration value */ +void bkp_rtc_calibration_value_set(uint8_t value); + +/* select OSC32IN pin */ +void bkp_osc32in_pin_select(uint16_t inputpin); + +/* tamper pin related functions */ +/* enable tamper pin detection */ +void bkp_tamper_detection_enable(void); +/* disable tamper pin detection */ +void bkp_tamper_detection_disable(void); +/* set tamper pin active level */ +void bkp_tamper_active_level_set(uint16_t level); +/* enable tamper pin interrupt */ +void bkp_tamper_interrupt_enable(void); +/* disable tamper pin interrupt */ +void bkp_tamper_interrupt_disable(void); + +/* flag functions */ +/* get BKP flag state */ +FlagStatus bkp_flag_get(uint16_t flag); +/* clear BKP flag state */ +void bkp_flag_clear(uint16_t flag); +/* get BKP interrupt flag state */ +FlagStatus bkp_interrupt_flag_get(uint16_t flag); +/* clear BKP interrupt flag state */ +void bkp_interrupt_flag_clear(uint16_t flag); + +#endif /* GD32A50X_BKP_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_can.h b/gd32a50x/standard_peripheral/include/gd32a50x_can.h new file mode 100644 index 0000000..a3fcf28 --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_can.h @@ -0,0 +1,1274 @@ +/*! + \file gd32a50x_can.h + \brief definitions for the CAN + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_CAN_H +#define GD32A50X_CAN_H + +#include "gd32a50x.h" + +/* CAN definitions */ +#define CAN0 CAN_BASE /*!< CAN0 base address */ +#define CAN1 (CAN_BASE + 0x00001000U) /*!< CAN1 base address */ +#define CAN_RAM(canx) ((uint32_t)((canx) + 0x00000080U)) /*!< can ram base address */ +#define CAN_PN_RAM(canx) ((uint32_t)(canx) + 0x00000B40U) /*!< Pretended Networking ram base address */ + +/* registers definitions */ +#define CAN_CTL0(canx) REG32((canx) + 0x00000000U) /*!< CAN control register 0 */ +#define CAN_CTL1(canx) REG32((canx) + 0x00000004U) /*!< CAN control register 1 */ +#define CAN_TIMER(canx) REG32((canx) + 0x00000008U) /*!< CAN timer register */ +#define CAN_RMPUBF(canx) REG32((canx) + 0x00000010U) /*!< CAN receive mailbox public filter register */ +#define CAN_ERR0(canx) REG32((canx) + 0x0000001CU) /*!< CAN error register 0 */ +#define CAN_ERR1(canx) REG32((canx) + 0x00000020U) /*!< CAN error register 1 */ +#define CAN_INTEN(canx) REG32((canx) + 0x00000028U) /*!< CAN interrupt enable register */ +#define CAN_STAT(canx) REG32((canx) + 0x00000030U) /*!< CAN status register */ +#define CAN_CTL2(canx) REG32((canx) + 0x00000034U) /*!< CAN control register 2 */ +#define CAN_CRCC(canx) REG32((canx) + 0x00000044U) /*!< CAN crc for classical frame register */ +#define CAN_RFIFOPUBF(canx) REG32((canx) + 0x00000048U) /*!< CAN receive fifo public filter register */ +#define CAN_RFIFOIFMN(canx) REG32((canx) + 0x0000004CU) /*!< CAN receive fifo identifier filter matching number register */ +#define CAN_BT(canx) REG32((canx) + 0x00000050U) /*!< CAN bit timing register */ +#define CAN_RFIFOMPF0(canx) REG32((canx) + 0x00000880U) /*!< CAN receive fifo / mailbox private filter 0 register */ +#define CAN_RFIFOMPF1(canx) REG32((canx) + 0x00000884U) /*!< CAN receive fifo / mailbox private filter 1 register */ +#define CAN_RFIFOMPF2(canx) REG32((canx) + 0x00000888U) /*!< CAN receive fifo / mailbox private filter 2 register */ +#define CAN_RFIFOMPF3(canx) REG32((canx) + 0x0000088CU) /*!< CAN receive fifo / mailbox private filter 3 register */ +#define CAN_RFIFOMPF4(canx) REG32((canx) + 0x00000890U) /*!< CAN receive fifo / mailbox private filter 4 register */ +#define CAN_RFIFOMPF5(canx) REG32((canx) + 0x00000894U) /*!< CAN receive fifo / mailbox private filter 5 register */ +#define CAN_RFIFOMPF6(canx) REG32((canx) + 0x00000898U) /*!< CAN receive fifo / mailbox private filter 6 register */ +#define CAN_RFIFOMPF7(canx) REG32((canx) + 0x0000089CU) /*!< CAN receive fifo / mailbox private filter 7 register */ +#define CAN_RFIFOMPF8(canx) REG32((canx) + 0x000008A0U) /*!< CAN receive fifo / mailbox private filter 8 register */ +#define CAN_RFIFOMPF9(canx) REG32((canx) + 0x000008A4U) /*!< CAN receive fifo / mailbox private filter 9 register */ +#define CAN_RFIFOMPF10(canx) REG32((canx) + 0x000008A8U) /*!< CAN receive fifo / mailbox private filter 10 register */ +#define CAN_RFIFOMPF11(canx) REG32((canx) + 0x000008ACU) /*!< CAN receive fifo / mailbox private filter 11 register */ +#define CAN_RFIFOMPF12(canx) REG32((canx) + 0x000008B0U) /*!< CAN receive fifo / mailbox private filter 12 register */ +#define CAN_RFIFOMPF13(canx) REG32((canx) + 0x000008B4U) /*!< CAN receive fifo / mailbox private filter 13 register */ +#define CAN_RFIFOMPF14(canx) REG32((canx) + 0x000008B8U) /*!< CAN receive fifo / mailbox private filter 14 register */ +#define CAN_RFIFOMPF15(canx) REG32((canx) + 0x000008BCU) /*!< CAN receive fifo / mailbox private filter 15 register */ +#define CAN_RFIFOMPF16(canx) REG32((canx) + 0x000008C0U) /*!< CAN receive fifo / mailbox private filter 16 register */ +#define CAN_RFIFOMPF17(canx) REG32((canx) + 0x000008C4U) /*!< CAN receive fifo / mailbox private filter 17 register */ +#define CAN_RFIFOMPF18(canx) REG32((canx) + 0x000008C8U) /*!< CAN receive fifo / mailbox private filter 18 register */ +#define CAN_RFIFOMPF19(canx) REG32((canx) + 0x000008CCU) /*!< CAN receive fifo / mailbox private filter 19 register */ +#define CAN_RFIFOMPF20(canx) REG32((canx) + 0x000008D0U) /*!< CAN receive fifo / mailbox private filter 20 register */ +#define CAN_RFIFOMPF21(canx) REG32((canx) + 0x000008D4U) /*!< CAN receive fifo / mailbox private filter 21 register */ +#define CAN_RFIFOMPF22(canx) REG32((canx) + 0x000008D8U) /*!< CAN receive fifo / mailbox private filter 22 register */ +#define CAN_RFIFOMPF23(canx) REG32((canx) + 0x000008DCU) /*!< CAN receive fifo / mailbox private filter 23 register */ +#define CAN_RFIFOMPF24(canx) REG32((canx) + 0x000008E0U) /*!< CAN receive fifo / mailbox private filter 24 register */ +#define CAN_RFIFOMPF25(canx) REG32((canx) + 0x000008E4U) /*!< CAN receive fifo / mailbox private filter 25 register */ +#define CAN_RFIFOMPF26(canx) REG32((canx) + 0x000008E8U) /*!< CAN receive fifo / mailbox private filter 26 register */ +#define CAN_RFIFOMPF27(canx) REG32((canx) + 0x000008ECU) /*!< CAN receive fifo / mailbox private filter 27 register */ +#define CAN_RFIFOMPF28(canx) REG32((canx) + 0x000008F0U) /*!< CAN receive fifo / mailbox private filter 28 register */ +#define CAN_RFIFOMPF29(canx) REG32((canx) + 0x000008F4U) /*!< CAN receive fifo / mailbox private filter 29 register */ +#define CAN_RFIFOMPF30(canx) REG32((canx) + 0x000008F8U) /*!< CAN receive fifo / mailbox private filter 30 register */ +#define CAN_RFIFOMPF31(canx) REG32((canx) + 0x000008FCU) /*!< CAN receive fifo / mailbox private filter 31 register */ +#define CAN_PN_CTL0(canx) REG32((canx) + 0x00000B00U) /*!< Pretended Networking mode control register 0 */ +#define CAN_PN_TO(canx) REG32((canx) + 0x00000B04U) /*!< Pretended Networking mode timeout register */ +#define CAN_PN_STAT(canx) REG32((canx) + 0x00000B08U) /*!< Pretended Networking mode status register */ +#define CAN_PN_EID0(canx) REG32((canx) + 0x00000B0CU) /*!< Pretended Networking mode expected identifier 0 register */ +#define CAN_PN_EDLC(canx) REG32((canx) + 0x00000B10U) /*!< Pretended Networking mode expected dlc register */ +#define CAN_PN_EDL0(canx) REG32((canx) + 0x00000B14U) /*!< Pretended Networking mode expected data low 0 register */ +#define CAN_PN_EDL1(canx) REG32((canx) + 0x00000B18U) /*!< Pretended Networking mode expected data low 1 register */ +#define CAN_PN_IFEID1(canx) REG32((canx) + 0x00000B1CU) /*!< Pretended Networking mode identifier filter / expected identifier 1 register */ +#define CAN_PN_DF0EDH0(canx) REG32((canx) + 0x00000B20U) /*!< Pretended Networking mode data 0 filter / expected data high 0 register */ +#define CAN_PN_DF1EDH1(canx) REG32((canx) + 0x00000B24U) /*!< Pretended Networking mode data 1 filter / expected data high 1 register */ +#define CAN_PN_RWM0CS(canx) REG32((canx) + 0x00000B40U) /*!< Pretended Networking mode received wakeup mailbox 0 control status information register */ +#define CAN_PN_RWM0I(canx) REG32((canx) + 0x00000B44U) /*!< Pretended Networking mode received wakeup mailbox 0 identifier register */ +#define CAN_PN_RWM0D0(canx) REG32((canx) + 0x00000B48U) /*!< Pretended Networking mode received wakeup mailbox 0 data 0 register */ +#define CAN_PN_RWM0D1(canx) REG32((canx) + 0x00000B4CU) /*!< Pretended Networking mode received wakeup mailbox 0 data 1 register */ +#define CAN_PN_RWM1CS(canx) REG32((canx) + 0x00000B50U) /*!< Pretended Networking mode received wakeup mailbox 1 control status information register */ +#define CAN_PN_RWM1I(canx) REG32((canx) + 0x00000B54U) /*!< Pretended Networking mode received wakeup mailbox 1 identifier register */ +#define CAN_PN_RWM1D0(canx) REG32((canx) + 0x00000B58U) /*!< Pretended Networking mode received wakeup mailbox 1 data 0 register */ +#define CAN_PN_RWM1D1(canx) REG32((canx) + 0x00000B5CU) /*!< Pretended Networking mode received wakeup mailbox 1 data 1 register */ +#define CAN_PN_RWM2CS(canx) REG32((canx) + 0x00000B60U) /*!< Pretended Networking mode received wakeup mailbox 2 control status information register */ +#define CAN_PN_RWM2I(canx) REG32((canx) + 0x00000B64U) /*!< Pretended Networking mode received wakeup mailbox 2 identifier register */ +#define CAN_PN_RWM2D0(canx) REG32((canx) + 0x00000B68U) /*!< Pretended Networking mode received wakeup mailbox 2 data 0 register */ +#define CAN_PN_RWM2D1(canx) REG32((canx) + 0x00000B6CU) /*!< Pretended Networking mode received wakeup mailbox 2 data 1 register */ +#define CAN_PN_RWM3CS(canx) REG32((canx) + 0x00000B70U) /*!< Pretended Networking mode received wakeup mailbox 3 control status information register */ +#define CAN_PN_RWM3I(canx) REG32((canx) + 0x00000B74U) /*!< Pretended Networking mode received wakeup mailbox 3 identifier register */ +#define CAN_PN_RWM3D0(canx) REG32((canx) + 0x00000B78U) /*!< Pretended Networking mode received wakeup mailbox 3 data 0 register */ +#define CAN_PN_RWM3D1(canx) REG32((canx) + 0x00000B7CU) /*!< Pretended Networking mode received wakeup mailbox 3 data 1 register */ +#define CAN_FDCTL(canx) REG32((canx) + 0x00000C00U) /*!< CAN FD control register */ +#define CAN_FDBT(canx) REG32((canx) + 0x00000C04U) /*!< CAN bit timing register */ +#define CAN_CRCCFD(canx) REG32((canx) + 0x00000C08U) /*!< CAN CRC for classical and FD frame register */ + +/* bits definitions */ +/* CAN_CTL0 */ +#define CAN_CTL0_MSZ BITS(0, 4) /*!< memory size */ +#define CAN_CTL0_FS BITS(8, 9) /*!< format selection */ +#define CAN_CTL0_FDEN BIT(11) /*!< CAN FD operation enable */ +#define CAN_CTL0_MST BIT(12) /*!< mailbox stop transmission */ +#define CAN_CTL0_LAPRIOEN BIT(13) /*!< enable local arbitration priority */ +#define CAN_CTL0_PNMOD BIT(14) /*!< Pretended Networking mode selection */ +#define CAN_CTL0_DMAEN BIT(15) /*!< enable DMA */ +#define CAN_CTL0_RPFQEN BIT(16) /*!< enable rx private filters enable & rx mailbox queue */ +#define CAN_CTL0_SRDIS BIT(17) /*!< enable self reception */ +#define CAN_CTL0_PNS BIT(18) /*!< Pretended Networking state */ +#define CAN_CTL0_PNEN BIT(19) /*!< enable Pretended Networking mode */ +#define CAN_CTL0_LPS BIT(20) /*!< low power state */ +#define CAN_CTL0_WERREN BIT(21) /*!< enable error warning */ +#define CAN_CTL0_INAS BIT(24) /*!< inactive mode state */ +#define CAN_CTL0_SWRST BIT(25) /*!< software reset */ +#define CAN_CTL0_NRDY BIT(27) /*!< not ready */ +#define CAN_CTL0_HALT BIT(28) /*!< halt CAN */ +#define CAN_CTL0_RFEN BIT(29) /*!< rx fifo enable */ +#define CAN_CTL0_INAMOD BIT(30) /*!< enable inactive mode */ +#define CAN_CTL0_CANDIS BIT(31) /*!< disable CAN */ + +/* CAN_CTL1 */ +#define CAN_CTL1_MMOD BIT(3) /*!< monitor mode */ +#define CAN_CTL1_MTO BIT(4) /*!< mailbox transmission order */ +#define CAN_CTL1_TSYNC BIT(5) /*!< enable time synchronization */ +#define CAN_CTL1_ABORDIS BIT(6) /*!< not enable automatic bus off recovery */ +#define CAN_CTL1_BSPMOD BIT(7) /*!< bit sampling mode */ +#define CAN_CTL1_RWERRIE BIT(10) /*!< enable rx error warning interrupt */ +#define CAN_CTL1_TWERRIE BIT(11) /*!< enable tx error warning interrupt */ +#define CAN_CTL1_LSCMOD BIT(12) /*!< loopback and silent communication mode */ +#define CAN_CTL1_ERRSIE BIT(14) /*!< enable error summary interrupt */ +#define CAN_CTL1_BOIE BIT(15) /*!< enable bus off interrupt */ + +/* CAN_TIMER */ +#define CAN_TIMER_CNT BITS(0,15) /*!< counter value */ + +/* CAN_RMPUBF */ +#define CAN_RMPUBF_MFD0 BIT(0) /*!< mailbox filter data bit 0 */ +#define CAN_RMPUBF_MFD1 BIT(1) /*!< mailbox filter data bit 1 */ +#define CAN_RMPUBF_MFD2 BIT(2) /*!< mailbox filter data bit 2 */ +#define CAN_RMPUBF_MFD3 BIT(3) /*!< mailbox filter data bit 3 */ +#define CAN_RMPUBF_MFD4 BIT(4) /*!< mailbox filter data bit 4 */ +#define CAN_RMPUBF_MFD5 BIT(5) /*!< mailbox filter data bit 5 */ +#define CAN_RMPUBF_MFD6 BIT(6) /*!< mailbox filter data bit 6 */ +#define CAN_RMPUBF_MFD7 BIT(7) /*!< mailbox filter data bit 7 */ +#define CAN_RMPUBF_MFD8 BIT(8) /*!< mailbox filter data bit 8 */ +#define CAN_RMPUBF_MFD9 BIT(9) /*!< mailbox filter data bit 9 */ +#define CAN_RMPUBF_MFD10 BIT(10) /*!< mailbox filter data bit 10 */ +#define CAN_RMPUBF_MFD11 BIT(11) /*!< mailbox filter data bit 11 */ +#define CAN_RMPUBF_MFD12 BIT(12) /*!< mailbox filter data bit 12 */ +#define CAN_RMPUBF_MFD13 BIT(13) /*!< mailbox filter data bit 13 */ +#define CAN_RMPUBF_MFD14 BIT(14) /*!< mailbox filter data bit 14 */ +#define CAN_RMPUBF_MFD15 BIT(15) /*!< mailbox filter data bit 15 */ +#define CAN_RMPUBF_MFD16 BIT(16) /*!< mailbox filter data bit 16 */ +#define CAN_RMPUBF_MFD17 BIT(17) /*!< mailbox filter data bit 17 */ +#define CAN_RMPUBF_MFD18 BIT(18) /*!< mailbox filter data bit 18 */ +#define CAN_RMPUBF_MFD19 BIT(19) /*!< mailbox filter data bit 19 */ +#define CAN_RMPUBF_MFD20 BIT(20) /*!< mailbox filter data bit 20 */ +#define CAN_RMPUBF_MFD21 BIT(21) /*!< mailbox filter data bit 21 */ +#define CAN_RMPUBF_MFD22 BIT(22) /*!< mailbox filter data bit 22 */ +#define CAN_RMPUBF_MFD23 BIT(23) /*!< mailbox filter data bit 23 */ +#define CAN_RMPUBF_MFD24 BIT(24) /*!< mailbox filter data bit 24 */ +#define CAN_RMPUBF_MFD25 BIT(25) /*!< mailbox filter data bit 25 */ +#define CAN_RMPUBF_MFD26 BIT(26) /*!< mailbox filter data bit 26 */ +#define CAN_RMPUBF_MFD27 BIT(27) /*!< mailbox filter data bit 27 */ +#define CAN_RMPUBF_MFD28 BIT(28) /*!< mailbox filter data bit 28 */ +#define CAN_RMPUBF_MFD29 BIT(29) /*!< mailbox filter data bit 29 */ +#define CAN_RMPUBF_MFD30 BIT(30) /*!< mailbox filter data bit 30 */ +#define CAN_RMPUBF_MFD31 BIT(31) /*!< mailbox filter data bit 31 */ + +/* CAN_ERR0 */ +#define CAN_ERR0_TECNT BITS(0, 7) /*!< transmit error count defined by the CAN standard */ +#define CAN_ERR0_RECNT BITS(8, 15) /*!< receive error count defined by the CAN standard */ +#define CAN_ERR0_TEFCNT BITS(16, 23) /*!< transmit error count for the data phase of FD frames with BRS bit set */ +#define CAN_ERR0_REFCNT BITS(24, 31) /*!< receive error count for the data phase of FD frames with BRS bit set */ + +/* CAN_ERR1 */ +#define CAN_ERR1_ERRSF BIT(1) /*!< error summary flag */ +#define CAN_ERR1_BOF BIT(2) /*!< bus off flag */ +#define CAN_ERR1_RS BIT(3) /*!< receiving state */ +#define CAN_ERR1_ERRSI BITS(4, 5) /*!< error state indicator */ +#define CAN_ERR1_TS BIT(6) /*!< transmitting state */ +#define CAN_ERR1_IDLEF BIT(7) /*!< idle flag */ +#define CAN_ERR1_RWERRF BIT(8) /*!< rx error warning flag */ +#define CAN_ERR1_TWERRF BIT(9) /*!< tx error warning flag */ +#define CAN_ERR1_STFERR BIT(10) /*!< stuff error */ +#define CAN_ERR1_FMERR BIT(11) /*!< form error */ +#define CAN_ERR1_CRCERR BIT(12) /*!< CRC error */ +#define CAN_ERR1_ACKERR BIT(13) /*!< ACK error */ +#define CAN_ERR1_BDERR BIT(14) /*!< bit dominant error for all format frames */ +#define CAN_ERR1_BRERR BIT(15) /*!< bit recessive error for all format frames */ +#define CAN_ERR1_RWERRIF BIT(16) /*!< rx error warning interrupt flag */ +#define CAN_ERR1_TWERRIF BIT(17) /*!< tx error warning interrupt flag */ +#define CAN_ERR1_SYN BIT(18) /*!< synchronization flag */ +#define CAN_ERR1_BORF BIT(19) /*!< bus off recovery flag */ +#define CAN_ERR1_ERRFSF BIT(20) /*!< error summary flag for data phase of FD frames with BRS bit set */ +#define CAN_ERR1_ERROVR BIT(21) /*!< error overrun */ +#define CAN_ERR1_STFFERR BIT(26) /*!< stuff error in data phase of FD frames with BRS bit set */ +#define CAN_ERR1_FMFERR BIT(27) /*!< form error in data phase of FD frames with BRS bit set */ +#define CAN_ERR1_CRCFERR BIT(28) /*!< CRC error in data phase of FD frames with BRS bit set */ +#define CAN_ERR1_BDFERR BIT(30) /*!< bit dominant error in data phase of FD frames with BRS bit set */ +#define CAN_ERR1_BRFERR BIT(31) /*!< bit recessive error in data phase of FD frames with BRS bit set */ + +/* CAN_INTEN */ +#define CAN_INTEN_MIE0 BIT(0) /*!< enable message 0 transmission and reception interrupt */ +#define CAN_INTEN_MIE1 BIT(1) /*!< enable message 1 transmission and reception interrupt */ +#define CAN_INTEN_MIE2 BIT(2) /*!< enable message 2 transmission and reception interrupt */ +#define CAN_INTEN_MIE3 BIT(3) /*!< enable message 3 transmission and reception interrupt */ +#define CAN_INTEN_MIE4 BIT(4) /*!< enable message 4 transmission and reception interrupt */ +#define CAN_INTEN_MIE5 BIT(5) /*!< enable message 5 transmission and reception interrupt */ +#define CAN_INTEN_MIE6 BIT(6) /*!< enable message 6 transmission and reception interrupt */ +#define CAN_INTEN_MIE7 BIT(7) /*!< enable message 7 transmission and reception interrupt */ +#define CAN_INTEN_MIE8 BIT(8) /*!< enable message 8 transmission and reception interrupt */ +#define CAN_INTEN_MIE9 BIT(9) /*!< enable message 9 transmission and reception interrupt */ +#define CAN_INTEN_MIE10 BIT(10) /*!< enable message 10 transmission and reception interrupt */ +#define CAN_INTEN_MIE11 BIT(11) /*!< enable message 11 transmission and reception interrupt */ +#define CAN_INTEN_MIE12 BIT(12) /*!< enable message 12 transmission and reception interrupt */ +#define CAN_INTEN_MIE13 BIT(13) /*!< enable message 13 transmission and reception interrupt */ +#define CAN_INTEN_MIE14 BIT(14) /*!< enable message 14 transmission and reception interrupt */ +#define CAN_INTEN_MIE15 BIT(15) /*!< enable message 15 transmission and reception interrupt */ +#define CAN_INTEN_MIE16 BIT(16) /*!< enable message 16 transmission and reception interrupt */ +#define CAN_INTEN_MIE17 BIT(17) /*!< enable message 17 transmission and reception interrupt */ +#define CAN_INTEN_MIE18 BIT(18) /*!< enable message 18 transmission and reception interrupt */ +#define CAN_INTEN_MIE19 BIT(19) /*!< enable message 19 transmission and reception interrupt */ +#define CAN_INTEN_MIE20 BIT(20) /*!< enable message 20 transmission and reception interrupt */ +#define CAN_INTEN_MIE21 BIT(21) /*!< enable message 21 transmission and reception interrupt */ +#define CAN_INTEN_MIE22 BIT(22) /*!< enable message 22 transmission and reception interrupt */ +#define CAN_INTEN_MIE23 BIT(23) /*!< enable message 23 transmission and reception interrupt */ +#define CAN_INTEN_MIE24 BIT(24) /*!< enable message 24 transmission and reception interrupt */ +#define CAN_INTEN_MIE25 BIT(25) /*!< enable message 25 transmission and reception interrupt */ +#define CAN_INTEN_MIE26 BIT(26) /*!< enable message 26 transmission and reception interrupt */ +#define CAN_INTEN_MIE27 BIT(27) /*!< enable message 27 transmission and reception interrupt */ +#define CAN_INTEN_MIE28 BIT(28) /*!< enable message 28 transmission and reception interrupt */ +#define CAN_INTEN_MIE29 BIT(29) /*!< enable message 29 transmission and reception interrupt */ +#define CAN_INTEN_MIE30 BIT(30) /*!< enable message 30 transmission and reception interrupt */ +#define CAN_INTEN_MIE31 BIT(31) /*!< enable message 31 transmission and reception interrupt */ + +/* CAN_STAT */ +#define CAN_STAT_MS0_RFC BIT(0) /*!< mailbox 0 state / clear rx fifo bit */ +#define CAN_STAT_MS1_RES BIT(1) /*!< mailbox 1 state */ +#define CAN_STAT_MS2_RES BIT(2) /*!< mailbox 2 state */ +#define CAN_STAT_MS3_RES BIT(3) /*!< mailbox 3 state */ +#define CAN_STAT_MS4_RES BIT(4) /*!< mailbox 4 state */ +#define CAN_STAT_MS5_RFNE BIT(5) /*!< mailbox 5 state / rx fifo not empty */ +#define CAN_STAT_MS6_RFW BIT(6) /*!< mailbox 6 state / rx fifo warning */ +#define CAN_STAT_MS7_RFO BIT(7) /*!< mailbox 7 state / rx fifo overflow */ +#define CAN_STAT_MS8 BIT(8) /*!< mailbox 8 state */ +#define CAN_STAT_MS9 BIT(9) /*!< mailbox 9 state */ +#define CAN_STAT_MS10 BIT(10) /*!< mailbox 10 state */ +#define CAN_STAT_MS11 BIT(11) /*!< mailbox 11 state */ +#define CAN_STAT_MS12 BIT(12) /*!< mailbox 12 state */ +#define CAN_STAT_MS13 BIT(13) /*!< mailbox 13 state */ +#define CAN_STAT_MS14 BIT(14) /*!< mailbox 14 state */ +#define CAN_STAT_MS15 BIT(15) /*!< mailbox 15 state */ +#define CAN_STAT_MS16 BIT(16) /*!< mailbox 16 state */ +#define CAN_STAT_MS17 BIT(17) /*!< mailbox 17 state */ +#define CAN_STAT_MS18 BIT(18) /*!< mailbox 18 state */ +#define CAN_STAT_MS19 BIT(19) /*!< mailbox 19 state */ +#define CAN_STAT_MS20 BIT(20) /*!< mailbox 20 state */ +#define CAN_STAT_MS21 BIT(21) /*!< mailbox 21 state */ +#define CAN_STAT_MS22 BIT(22) /*!< mailbox 22 state */ +#define CAN_STAT_MS23 BIT(23) /*!< mailbox 23 state */ +#define CAN_STAT_MS24 BIT(24) /*!< mailbox 24 state */ +#define CAN_STAT_MS25 BIT(25) /*!< mailbox 25 state */ +#define CAN_STAT_MS26 BIT(26) /*!< mailbox 26 state */ +#define CAN_STAT_MS27 BIT(27) /*!< mailbox 27 state */ +#define CAN_STAT_MS28 BIT(28) /*!< mailbox 28 state */ +#define CAN_STAT_MS29 BIT(29) /*!< mailbox 29 state */ +#define CAN_STAT_MS30 BIT(30) /*!< mailbox 30 state */ +#define CAN_STAT_MS31 BIT(31) /*!< mailbox 31 state */ + +/* CAN_CTL2 */ +#define CAN_CTL2_EFDIS BIT(11) /*!< disable edge filtering */ +#define CAN_CTL2_ISO BIT(12) /*!< ISO CAN FD */ +#define CAN_CTL2_PREEN BIT(14) /*!< protocol exception detection enable by CAN standard */ +#define CAN_CTL2_ITSRC BIT(15) /*!< internal counter source */ +#define CAN_CTL2_IDERTR_RMF BIT(16) /*!< IDE and RTR field filter type for rx mailbox reception */ +#define CAN_CTL2_RRFRMS BIT(17) /*!< remote request frame is stored */ +#define CAN_CTL2_RFO BIT(18) /*!< receive filter order */ +#define CAN_CTL2_ASD BITS(19, 23) /*!< arbitration start delay */ +#define CAN_CTL2_RFFN BITS(24, 27) /*!< rx fifo filter number */ +#define CAN_CTL2_BORIE BIT(30) /*!< enable bus off recovery interrupt */ +#define CAN_CTL2_ERRFSIE BIT(31) /*!< error summary interrupt enable bit for data phase of FD frames with BRS bit set */ + +/* CAN_CRCC */ +#define CAN_CRCC_CRCTC BITS(0, 14) /*!< transmitted CRC value for classical frames */ +#define CAN_CRCC_ANTM BITS(16, 20) /*!< associated number of mailbox for transmitting the CRCTC[14:0] value */ + +/* CAN_RFIFOPUBF */ +#define CAN_RFIFOPUBF_FFD0 BIT(0) /*!< rx fifo filter data bit 0 */ +#define CAN_RFIFOPUBF_FFD1 BIT(1) /*!< rx fifo filter data bit 1 */ +#define CAN_RFIFOPUBF_FFD2 BIT(2) /*!< rx fifo filter data bit 2 */ +#define CAN_RFIFOPUBF_FFD3 BIT(3) /*!< rx fifo filter data bit 3 */ +#define CAN_RFIFOPUBF_FFD4 BIT(4) /*!< rx fifo filter data bit 4 */ +#define CAN_RFIFOPUBF_FFD5 BIT(5) /*!< rx fifo filter data bit 5 */ +#define CAN_RFIFOPUBF_FFD6 BIT(6) /*!< rx fifo filter data bit 6 */ +#define CAN_RFIFOPUBF_FFD7 BIT(7) /*!< rx fifo filter data bit 7 */ +#define CAN_RFIFOPUBF_FFD8 BIT(8) /*!< rx fifo filter data bit 8 */ +#define CAN_RFIFOPUBF_FFD9 BIT(9) /*!< rx fifo filter data bit 9 */ +#define CAN_RFIFOPUBF_FFD10 BIT(10) /*!< rx fifo filter data bit 10 */ +#define CAN_RFIFOPUBF_FFD11 BIT(11) /*!< rx fifo filter data bit 11 */ +#define CAN_RFIFOPUBF_FFD12 BIT(12) /*!< rx fifo filter data bit 12 */ +#define CAN_RFIFOPUBF_FFD13 BIT(13) /*!< rx fifo filter data bit 13 */ +#define CAN_RFIFOPUBF_FFD14 BIT(14) /*!< rx fifo filter data bit 14 */ +#define CAN_RFIFOPUBF_FFD15 BIT(15) /*!< rx fifo filter data bit 15 */ +#define CAN_RFIFOPUBF_FFD16 BIT(16) /*!< rx fifo filter data bit 16 */ +#define CAN_RFIFOPUBF_FFD17 BIT(17) /*!< rx fifo filter data bit 17 */ +#define CAN_RFIFOPUBF_FFD18 BIT(18) /*!< rx fifo filter data bit 18 */ +#define CAN_RFIFOPUBF_FFD19 BIT(19) /*!< rx fifo filter data bit 19 */ +#define CAN_RFIFOPUBF_FFD20 BIT(20) /*!< rx fifo filter data bit 20 */ +#define CAN_RFIFOPUBF_FFD21 BIT(21) /*!< rx fifo filter data bit 21 */ +#define CAN_RFIFOPUBF_FFD22 BIT(22) /*!< rx fifo filter data bit 22 */ +#define CAN_RFIFOPUBF_FFD23 BIT(23) /*!< rx fifo filter data bit 23 */ +#define CAN_RFIFOPUBF_FFD24 BIT(24) /*!< rx fifo filter data bit 24 */ +#define CAN_RFIFOPUBF_FFD25 BIT(25) /*!< rx fifo filter data bit 25 */ +#define CAN_RFIFOPUBF_FFD26 BIT(26) /*!< rx fifo filter data bit 26 */ +#define CAN_RFIFOPUBF_FFD27 BIT(27) /*!< rx fifo filter data bit 27 */ +#define CAN_RFIFOPUBF_FFD28 BIT(28) /*!< rx fifo filter data bit 28 */ +#define CAN_RFIFOPUBF_FFD29 BIT(29) /*!< rx fifo filter data bit 29 */ +#define CAN_RFIFOPUBF_FFD30 BIT(30) /*!< rx fifo filter data bit 30 */ +#define CAN_RFIFOPUBF_FFD31 BIT(31) /*!< rx fifo filter data bit 31 */ + +/* CAN_RFIFOIFMN */ +#define CAN_RFIFOIFMN_IDFMN BITS(0, 8) /*!< identifier filter matching number */ + +/* CAN_BT */ +#define CAN_BT_PBS2 BITS(0, 4) /*!< phase buffer segment 2 */ +#define CAN_BT_PBS1 BITS(5, 9) /*!< phase buffer segment 1 */ +#define CAN_BT_PTS BITS(10, 15) /*!< propagation time segment */ +#define CAN_BT_SJW BITS(16, 20) /*!< resynchronization jump width */ +#define CAN_BT_BAUDPSC BITS(21, 30) /*!< baud rate prescaler */ + +/* CAN_RFIFOMPFx, x = 0..31 */ +#define CAN_RFIFOMPF_FMFD0 BIT(0) /*!< fifo / mailbox filter data bit 0 */ +#define CAN_RFIFOMPF_FMFD1 BIT(1) /*!< fifo / mailbox filter data bit 1 */ +#define CAN_RFIFOMPF_FMFD2 BIT(2) /*!< fifo / mailbox filter data bit 2 */ +#define CAN_RFIFOMPF_FMFD3 BIT(3) /*!< fifo / mailbox filter data bit 3 */ +#define CAN_RFIFOMPF_FMFD4 BIT(4) /*!< fifo / mailbox filter data bit 4 */ +#define CAN_RFIFOMPF_FMFD5 BIT(5) /*!< fifo / mailbox filter data bit 5 */ +#define CAN_RFIFOMPF_FMFD6 BIT(6) /*!< fifo / mailbox filter data bit 6 */ +#define CAN_RFIFOMPF_FMFD7 BIT(7) /*!< fifo / mailbox filter data bit 7 */ +#define CAN_RFIFOMPF_FMFD8 BIT(8) /*!< fifo / mailbox filter data bit 8 */ +#define CAN_RFIFOMPF_FMFD9 BIT(9) /*!< fifo / mailbox filter data bit 9 */ +#define CAN_RFIFOMPF_FMFD10 BIT(10) /*!< fifo / mailbox filter data bit 10 */ +#define CAN_RFIFOMPF_FMFD11 BIT(11) /*!< fifo / mailbox filter data bit 11 */ +#define CAN_RFIFOMPF_FMFD12 BIT(12) /*!< fifo / mailbox filter data bit 12 */ +#define CAN_RFIFOMPF_FMFD13 BIT(13) /*!< fifo / mailbox filter data bit 13 */ +#define CAN_RFIFOMPF_FMFD14 BIT(14) /*!< fifo / mailbox filter data bit 14 */ +#define CAN_RFIFOMPF_FMFD15 BIT(15) /*!< fifo / mailbox filter data bit 15 */ +#define CAN_RFIFOMPF_FMFD16 BIT(16) /*!< fifo / mailbox filter data bit 16 */ +#define CAN_RFIFOMPF_FMFD17 BIT(17) /*!< fifo / mailbox filter data bit 17 */ +#define CAN_RFIFOMPF_FMFD18 BIT(18) /*!< fifo / mailbox filter data bit 18 */ +#define CAN_RFIFOMPF_FMFD19 BIT(19) /*!< fifo / mailbox filter data bit 19 */ +#define CAN_RFIFOMPF_FMFD20 BIT(20) /*!< fifo / mailbox filter data bit 20 */ +#define CAN_RFIFOMPF_FMFD21 BIT(21) /*!< fifo / mailbox filter data bit 21 */ +#define CAN_RFIFOMPF_FMFD22 BIT(22) /*!< fifo / mailbox filter data bit 22 */ +#define CAN_RFIFOMPF_FMFD23 BIT(23) /*!< fifo / mailbox filter data bit 23 */ +#define CAN_RFIFOMPF_FMFD24 BIT(24) /*!< fifo / mailbox filter data bit 24 */ +#define CAN_RFIFOMPF_FMFD25 BIT(25) /*!< fifo / mailbox filter data bit 25 */ +#define CAN_RFIFOMPF_FMFD26 BIT(26) /*!< fifo / mailbox filter data bit 26 */ +#define CAN_RFIFOMPF_FMFD27 BIT(27) /*!< fifo / mailbox filter data bit 27 */ +#define CAN_RFIFOMPF_FMFD28 BIT(28) /*!< fifo / mailbox filter data bit 28 */ +#define CAN_RFIFOMPF_FMFD29 BIT(29) /*!< fifo / mailbox filter data bit 29 */ +#define CAN_RFIFOMPF_FMFD30 BIT(30) /*!< fifo / mailbox filter data bit 30 */ +#define CAN_RFIFOMPF_FMFD31 BIT(31) /*!< fifo / mailbox filter data bit 31 */ + +/* CAN_PN_CTL0 */ +#define CAN_PN_CTL0_FFT BITS(0, 1) /*!< frame filtering type in Pretended Networking mode */ +#define CAN_PN_CTL0_IDFT BITS(2, 3) /*!< ID field filtering type in Pretended Networking mode */ +#define CAN_PN_CTL0_DATAFT BITS(4, 5) /*!< data field filtering type in Pretended Networking mode */ +#define CAN_PN_CTL0_NMM BITS(8, 15) /*!< number of messages matching times */ +#define CAN_PN_CTL0_WMIE BIT(16) /*!< enable wakeup match interrupt */ +#define CAN_PN_CTL0_WTOIE BIT(17) /*!< enable wakeup timeout interrupt */ + +/* CAN_PN_TO */ +#define CAN_PN_TO_WTO BITS(0, 15) /*!< wakeup timeout */ + +/* CAN_PN_STAT */ +#define CAN_PN_STAT_MMCNTS BIT(7) /*!< matching message counter state */ +#define CAN_PN_STAT_MMCNT BITS(8, 15) /*!< matching message counter in Pretended Networking mode */ +#define CAN_PN_STAT_WMS BIT(16) /*!< wakeup match flag status */ +#define CAN_PN_STAT_WTOS BIT(17) /*!< wakeup timeout flag status */ + +/* CAN_PN_EID0 */ +#define CAN_PN_EID0_EID_ELT BITS(0, 28) /*!< expected ID field / expected ID low threshold in Pretended Networking mode */ +#define CAN_PN_EID0_ERTR BIT(29) /*!< expected RTR in Pretended Networking mode */ +#define CAN_PN_EID0_EIDE BIT(30) /*!< expected IDE in Pretended Networking mode */ + +/* CAN_PN_EDLC */ +#define CAN_PN_EDLC_DLCEHT BITS(0, 3) /*!< DLC expected high threshold in Pretended Networking mode */ +#define CAN_PN_EDLC_DLCELT BITS(16, 19) /*!< DLC expected low threshold in Pretended Networking mode */ + +/* CAN_PN_EDL0 */ +#define CAN_PN_EDL0_DB3ELT BITS(0, 7) /*!< data byte 3 expected low threshold in Pretended Networking mode */ +#define CAN_PN_EDL0_DB2ELT BITS(8, 15) /*!< data byte 2 expected low threshold in Pretended Networking mode */ +#define CAN_PN_EDL0_DB1ELT BITS(16, 23) /*!< data byte 1 expected low threshold in Pretended Networking mode */ +#define CAN_PN_EDL0_DB0ELT BITS(24, 31) /*!< data byte 0 expected low threshold in Pretended Networking mode */ + +/* CAN_PN_EDL1 */ +#define CAN_PN_EDL1_DB7ELT BITS(0, 7) /*!< data byte 7 expected low threshold in Pretended Networking mode */ +#define CAN_PN_EDL1_DB6ELT BITS(8, 15) /*!< data byte 6 expected low threshold in Pretended Networking mode */ +#define CAN_PN_EDL1_DB5ELT BITS(16, 23) /*!< data byte 5 expected low threshold in Pretended Networking mode */ +#define CAN_PN_EDL1_DB4ELT BITS(24, 31) /*!< data byte 4 expected low threshold in Pretended Networking mode */ + +/* CAN_PN_IFEID1 */ +#define CAN_PN_IFEID1_IDFD_EHT BITS(0, 28) /*!< IDE filter data in Pretended Networking mode */ +#define CAN_PN_IFEID1_RTRFD BIT(29) /*!< RTR filter data in Pretended Networking mode */ +#define CAN_PN_IFEID1_IDEFD BIT(30) /*!< ID filter data / ID expected high threshold in Pretended Networking mode */ + +/* CAN_PN_DF0EDH0 */ +#define CAN_PN_DF0EDH0_DB3FD_EHT BITS(0, 7) /*!< data byte 3 filter data / data byte 3 expected high threshold in Pretended Networking mode */ +#define CAN_PN_DF0EDH0_DB2FD_EHT BITS(8, 15) /*!< data byte 2 filter data / data byte 2 expected high threshold in Pretended Networking mode */ +#define CAN_PN_DF0EDH0_DB1FD_EHT BITS(16, 23) /*!< data byte 1 filter data / data byte 1 expected high threshold in Pretended Networking mode */ +#define CAN_PN_DF0EDH0_DB0FD_EHT BITS(24, 31) /*!< data byte 0 filter data / data byte 0 expected high threshold in Pretended Networking mode */ + +/* CAN_PN_DF1EDH1 */ +#define CAN_PN_DF1EDH1_DB7FD_EHT BITS(0, 7) /*!< data byte 7 filter data / data byte 7 expected high threshold in Pretended Networking mode */ +#define CAN_PN_DF1EDH1_DB6FD_EHT BITS(8, 15) /*!< data byte 6 filter data / data byte 6 expected high threshold in Pretended Networking mode */ +#define CAN_PN_DF1EDH1_DB5FD_EHT BITS(16, 23) /*!< data byte 5 filter data / data byte 5 expected high threshold in Pretended Networking mode */ +#define CAN_PN_DF1EDH1_DB4FD_EHT BITS(24, 31) /*!< data byte 4 filter data / data byte 4 expected high threshold in Pretended Networking mode */ + +/* CAN_PN_RWMxCS, x = 0..3 */ +#define CAN_PN_RWMXCS_RDLC BITS(16, 19) /*!< received DLC bits */ +#define CAN_PN_RWMXCS_RRTR BIT(20) /*!< received RTR bit */ +#define CAN_PN_RWMXCS_RIDE BIT(21) /*!< received IDE bit */ +#define CAN_PN_RWMXCS_RSRR BIT(22) /*!< received SRR bit */ + +/* CAN_PN_RWMxI, x = 0..3 */ +#define CAN_PN_RWMXI_RID BITS(0, 28) /*!< received ID bits */ + +/* CAN_PN_RWMxD0, x = 0..3 */ +#define CAN_PN_RWMXD0_RDB3 BITS(0, 7) /*!< received data byte 3 */ +#define CAN_PN_RWMXD0_RDB2 BITS(8, 15) /*!< received data byte 2 */ +#define CAN_PN_RWMXD0_RDB1 BITS(16, 23) /*!< received data byte 1 */ +#define CAN_PN_RWMXD0_RDB0 BITS(24, 31) /*!< received data byte 0 */ + +/* CAN_PN_RWMxD1, x = 0..3 */ +#define CAN_PN_RWMXD1_RDB7 BITS(0, 7) /*!< received data byte 7 */ +#define CAN_PN_RWMXD1_RDB6 BITS(8, 15) /*!< received data byte 6 */ +#define CAN_PN_RWMXD1_RDB5 BITS(16, 23) /*!< received data byte 5 */ +#define CAN_PN_RWMXD1_RDB4 BITS(24, 31) /*!< received data byte 4 */ + +/* CAN_FDCTL */ +#define CAN_FDCTL_TDCV BITS(0, 5) /*!< transmitter delay compensation value */ +#define CAN_FDCTL_TDCO BITS(8, 12) /*!< transmitter delay compensation offset */ +#define CAN_FDCTL_TDCS BIT(14) /*!< transmitter delay compensation status */ +#define CAN_FDCTL_TDCEN BIT(15) /*!< transmitter delay compensation enable */ +#define CAN_FDCTL_MDSZ BITS(16, 17) /*!< mailbox data size */ +#define CAN_FDCTL_BRSEN BIT(31) /*!< bit rate of data switch enable */ + +/* CAN_FDBT */ +#define CAN_FDBT_DPBS2 BITS(0, 2) /*!< phase buffer segment 2 for data bit time */ +#define CAN_FDBT_DPBS1 BITS(5, 7) /*!< phase buffer segment 1 for data bit time */ +#define CAN_FDBT_DPTS BITS(10, 14) /*!< propagation time segment for data bit time */ +#define CAN_FDBT_DSJW BITS(16, 18) /*!< resynchronization jump width for data bit time */ +#define CAN_FDBT_DBAUDPSC BITS(20, 29) /*!< baud rate prescaler for data bit time */ + +/* CAN_CRCCFD */ +#define CAN_CRCCFD_CRCTCI BITS(0, 20) /*!< transmitted CRC value for classical and ISO / non-ISO frames */ +#define CAN_CRCCFD_ANTM BITS(24, 28) /*!< associated number of mailbox for transmitting the CRCTCI[20:0] value */ + +/* CAN_MDES0 */ +#define CAN_MDES0_TIMESTAMP BITS(0, 15) /*!< free-running counter timestamp */ +#define CAN_MDES0_DLC BITS(16, 19) /*!< data length code in bytes */ +#define CAN_MDES0_RTR BIT(20) /*!< remote transmission request */ +#define CAN_MDES0_IDE BIT(21) /*!< ID extended bit */ +#define CAN_MDES0_SRR BIT(22) /*!< substitute remote request */ +#define CAN_MDES0_CODE BITS(24, 27) /*!< mailbox code */ +#define CAN_MDES0_ESI BIT(29) /*!< error state indicator */ +#define CAN_MDES0_BRS BIT(30) /*!< bit rate switch */ +#define CAN_MDES0_FDF BIT(31) /*!< FD format indicator */ + +/* CAN_MDES1 */ +#define CAN_MDES1_ID_EXD BITS(0, 17) /*!< identifier for extended frame */ +#define CAN_MDES1_ID_STD BITS(18, 28) /*!< identifier for standard frame */ +#define CAN_MDES1_PRIO BITS(29, 31) /*!< local priority */ + +/* CAN_FDES0 */ +#define CAN_FDES0_TIMESTAMP BITS(0, 15) /*!< free-running counter timestamp */ +#define CAN_FDES0_DLC BITS(16, 19) /*!< data length code in bytes */ +#define CAN_FDES0_RTR BIT(20) /*!< remote transmission request */ +#define CAN_FDES0_IDE BIT(21) /*!< ID extended bit */ +#define CAN_FDES0_SRR BIT(22) /*!< substitute remote request */ +#define CAN_FDES0_IDFMN BITS(23, 31) /*!< identifier filter matching number */ + +/* CAN_FDES1 */ +#define CAN_FDES1_ID_EXT BITS(0, 17) /*!< identifier for extended frame */ +#define CAN_FDES1_ID_STD BITS(18, 28) /*!< identifier for standard frame */ + +/* CAN_FDESX_A */ +#define CAN_FDESX_ID_EXD_A BITS(0, 28) /*!< extended ID in format A */ +#define CAN_FDESX_ID_STD_A BITS(18, 28) /*!< standard ID in format A */ +#define CAN_FDESX_IDE_A BIT(30) /*!< ID extended frame for format A */ +#define CAN_FDESX_RTR_A BIT(31) /*!< remote frame for format A */ + +/* CAN_FDESX_B */ +#define CAN_FDESX_ID_EXD_B_1 BITS(0, 13) /*!< extended ID 1 in format B */ +#define CAN_FDESX_ID_STD_B_1 BITS(3, 13) /*!< standard ID 1 in format B */ +#define CAN_FDESX_IDE_B1 BIT(14) /*!< ID extended frame 1 for format B */ +#define CAN_FDESX_RTR_B1 BIT(15) /*!< remote frame 1 for format B */ +#define CAN_FDESX_ID_EXD_B_0 BITS(16, 29) /*!< extended ID 0 in format B */ +#define CAN_FDESX_ID_STD_B_0 BITS(19, 29) /*!< standard ID 0 in format B */ +#define CAN_FDESX_IDE_B0 BIT(30) /*!< ID extended frame 0 for format B */ +#define CAN_FDESX_RTR_B0 BIT(31) /*!< remote frame 0 for format B */ + +/* CAN_FDESX_C */ +#define CAN_FDESX_ID_C_3 BITS(0, 7) /*!< ID for frame 3 for format C */ +#define CAN_FDESX_ID_C_2 BITS(8, 15) /*!< ID for frame 2 for format C */ +#define CAN_FDESX_ID_C_1 BITS(16, 23) /*!< ID for frame 1 for format C */ +#define CAN_FDESX_ID_C_0 BITS(24, 31) /*!< ID for frame 0 for format C */ + +/* consts definitions */ +/* define the CAN bit position and its register index offset */ +#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6U) | (uint32_t)(bitpos)) +#define CAN_REG_VAL(canx, offset) (REG32((uint32_t)(canx) + ((uint32_t)(offset) >> 6U))) +#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) +#define CAN_RFIFOMPF(canx, num) REG32((canx) + 0x00000880U + (num) * 0x00000004U) /*!< CAN receive fifo / mailbox private filter x register */ + +/* register offset */ +#define CTL0_REG_OFFSET ((uint32_t)0x00000000U) /*!< CTL0 register offset */ +#define CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */ +#define ERR1_REG_OFFSET ((uint32_t)0x00000020U) /*!< ERR1 register offset */ +#define INTEN_REG_OFFSET ((uint32_t)0x00000028U) /*!< INTEN register offset */ +#define STAT_REG_OFFSET ((uint32_t)0x00000030U) /*!< STAT register offset */ +#define CTL2_REG_OFFSET ((uint32_t)0x00000034U) /*!< CTL2 register offset */ +#define PN_CTL0_REG_OFFSET ((uint32_t)0x00000B00U) /*!< PN_CTL0 register offset */ +#define PN_STAT_REG_OFFSET ((uint32_t)0x00000B08U) /*!< PN_STAT register offset */ +#define FDCTL_REG_OFFSET ((uint32_t)0x00000C00U) /*!< FDCTL register offset */ + +/* CAN interrupt enable or disable */ +typedef enum { + /* interrupt in CLT1 register */ + CAN_INT_RX_WARNING = CAN_REGIDX_BIT(CTL1_REG_OFFSET, 10U), /*!< receive warning interrupt */ + CAN_INT_TX_WARNING = CAN_REGIDX_BIT(CTL1_REG_OFFSET, 11U), /*!< transmit warning interrupt */ + CAN_INT_ERR_SUMMARY = CAN_REGIDX_BIT(CTL1_REG_OFFSET, 14U), /*!< error interrupt */ + CAN_INT_BUSOFF = CAN_REGIDX_BIT(CTL1_REG_OFFSET, 15U), /*!< bus off interrupt */ + /* interrupt in CLT2 register */ + CAN_INT_BUSOFF_RECOVERY = CAN_REGIDX_BIT(CTL2_REG_OFFSET, 30U), /*!< bus off recovery interrupt */ + CAN_INT_ERR_SUMMARY_FD = CAN_REGIDX_BIT(CTL2_REG_OFFSET, 31U), /*!< fd error interrupt */ + /* interrupt in INTEN register */ + CAN_INT_MB0 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 0U), /*!< mailbox 0 interrupt */ + CAN_INT_MB1 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 1U), /*!< mailbox 1 interrupt */ + CAN_INT_MB2 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 2U), /*!< mailbox 2 interrupt */ + CAN_INT_MB3 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 3U), /*!< mailbox 3 interrupt */ + CAN_INT_MB4 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 4U), /*!< mailbox 4 interrupt */ + CAN_INT_MB5 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 5U), /*!< mailbox 5 interrupt */ + CAN_INT_MB6 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 6U), /*!< mailbox 6 interrupt */ + CAN_INT_MB7 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 7U), /*!< mailbox 7 interrupt */ + CAN_INT_MB8 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 8U), /*!< mailbox 8 interrupt */ + CAN_INT_MB9 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 9U), /*!< mailbox 9 interrupt */ + CAN_INT_MB10 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 10U), /*!< mailbox 10 interrupt */ + CAN_INT_MB11 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 11U), /*!< mailbox 11 interrupt */ + CAN_INT_MB12 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 12U), /*!< mailbox 12 interrupt */ + CAN_INT_MB13 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 13U), /*!< mailbox 13 interrupt */ + CAN_INT_MB14 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 14U), /*!< mailbox 14 interrupt */ + CAN_INT_MB15 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 15U), /*!< mailbox 15 interrupt */ + CAN_INT_MB16 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 16U), /*!< mailbox 16 interrupt */ + CAN_INT_MB17 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 17U), /*!< mailbox 17 interrupt */ + CAN_INT_MB18 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 18U), /*!< mailbox 18 interrupt */ + CAN_INT_MB19 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 19U), /*!< mailbox 19 interrupt */ + CAN_INT_MB20 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 20U), /*!< mailbox 20 interrupt */ + CAN_INT_MB21 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 21U), /*!< mailbox 21 interrupt */ + CAN_INT_MB22 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 22U), /*!< mailbox 22 interrupt */ + CAN_INT_MB23 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 23U), /*!< mailbox 23 interrupt */ + CAN_INT_MB24 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 24U), /*!< mailbox 24 interrupt */ + CAN_INT_MB25 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 25U), /*!< mailbox 25 interrupt */ + CAN_INT_MB26 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 26U), /*!< mailbox 26 interrupt */ + CAN_INT_MB27 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 27U), /*!< mailbox 27 interrupt */ + CAN_INT_MB28 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 28U), /*!< mailbox 28 interrupt */ + CAN_INT_MB29 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 29U), /*!< mailbox 29 interrupt */ + CAN_INT_MB30 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 30U), /*!< mailbox 30 interrupt */ + CAN_INT_MB31 = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 31U), /*!< mailbox 31 interrupt */ + CAN_INT_FIFO_AVAILABLE = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 5U), /*!< fifo availabe interrupt */ + CAN_INT_FIFO_WARNING = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 6U), /*!< fifo warning interrupt */ + CAN_INT_FIFO_OVERFLOW = CAN_REGIDX_BIT(INTEN_REG_OFFSET, 7U), /*!< fifo overflow interrupt */ + /* interrupt in PN_CTL0 registeister */ + CAN_INT_WAKEUP_MATCH = CAN_REGIDX_BIT(PN_CTL0_REG_OFFSET, 16U), /*!< Pretended Networking match interrupt */ + CAN_INT_WAKEUP_TIMEOUT = CAN_REGIDX_BIT(PN_CTL0_REG_OFFSET, 17U) /*!< Pretended Networking timeout wakeup interrupt */ +} can_interrupt_enum; + +/* CAN flags */ +typedef enum { + /* flags in CTL0 register */ + CAN_FLAG_CAN_PN = CAN_REGIDX_BIT(CTL0_REG_OFFSET, 18U), /*!< Pretended Networking state flag */ + CAN_FLAG_SOFT_RST = CAN_REGIDX_BIT(CTL0_REG_OFFSET, 25U), /*!< software reset flag */ + /* flags in ERR1 register */ + CAN_FLAG_ERR_SUMMARY = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 1U), /*!< error summary flag */ + CAN_FLAG_BUSOFF = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 2U), /*!< bus off flag */ + CAN_FLAG_RECEIVING = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 3U), /*!< receiving state flag */ + CAN_FLAG_TRANSMITTING = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 6U), /*!< transmitting state flag */ + CAN_FLAG_IDLE = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 7U), /*!< IDLE state flag */ + CAN_FLAG_RX_WARNING = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 8U), /*!< receive warning flag */ + CAN_FLAG_TX_WARNING = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 9U), /*!< transmit warning flag */ + CAN_FLAG_STUFF_ERR = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 10U), /*!< stuff error flag */ + CAN_FLAG_FORM_ERR = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 11U), /*!< form error flag */ + CAN_FLAG_CRC_ERR = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 12U), /*!< CRC error flag */ + CAN_FLAG_ACK_ERR = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 13U), /*!< ACK error flag */ + CAN_FLAG_BIT_DOMINANT_ERR = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 14U), /*!< bit dominant error flag */ + CAN_FLAG_BIT_RECESSIVE_ERR = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 15U), /*!< bit recessive error flag */ + CAN_FLAG_SYNC_ERR = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 18U), /*!< synchronization flag */ + CAN_FLAG_BUSOFF_RECOVERY = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 19U), /*!< bus off recovery flag */ + CAN_FLAG_ERR_SUMMARY_FD = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 20U), /*!< FD error summary flag */ + CAN_FLAG_ERR_OVERRUN = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 21U), /*!< error overrun flag */ + CAN_FLAG_STUFF_ERR_FD = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 26U), /*!< stuff error in FD data phase flag */ + CAN_FLAG_FORM_ERR_FD = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 27U), /*!< form error in FD data phase flag */ + CAN_FLAG_CRC_ERR_FD = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 28U), /*!< CRC error in FD data phase flag */ + CAN_FLAG_BIT_DOMINANT_ERR_FD = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 30U), /*!< bit dominant error in FD data phase flag */ + CAN_FLAG_BIT_RECESSIVE_ERR_FD = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 31U), /*!< bit recessive error in FD data phase flag */ + /* flags in STAT register */ + CAN_FLAG_MB0 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< mailbox 0 flag */ + CAN_FLAG_MB1 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< mailbox 1 flag */ + CAN_FLAG_MB2 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< mailbox 2 flag */ + CAN_FLAG_MB3 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< mailbox 3 flag */ + CAN_FLAG_MB4 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< mailbox 4 flag */ + CAN_FLAG_MB5 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 5U), /*!< mailbox 5 flag */ + CAN_FLAG_MB6 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 6U), /*!< mailbox 6 flag */ + CAN_FLAG_MB7 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 7U), /*!< mailbox 7 flag */ + CAN_FLAG_MB8 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< mailbox 8 flag */ + CAN_FLAG_MB9 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< mailbox 9 flag */ + CAN_FLAG_MB10 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< mailbox 10 flag */ + CAN_FLAG_MB11 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< mailbox 11 flag */ + CAN_FLAG_MB12 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 12U), /*!< mailbox 12 flag */ + CAN_FLAG_MB13 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 13U), /*!< mailbox 13 flag */ + CAN_FLAG_MB14 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 14U), /*!< mailbox 14 flag */ + CAN_FLAG_MB15 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 15U), /*!< mailbox 15 flag */ + CAN_FLAG_MB16 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 16U), /*!< mailbox 16 flag */ + CAN_FLAG_MB17 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 17U), /*!< mailbox 17 flag */ + CAN_FLAG_MB18 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 18U), /*!< mailbox 18 flag */ + CAN_FLAG_MB19 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 19U), /*!< mailbox 19 flag */ + CAN_FLAG_MB20 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 20U), /*!< mailbox 20 flag */ + CAN_FLAG_MB21 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 21U), /*!< mailbox 21 flag */ + CAN_FLAG_MB22 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 22U), /*!< mailbox 22 flag */ + CAN_FLAG_MB23 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 23U), /*!< mailbox 23 flag */ + CAN_FLAG_MB24 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 24U), /*!< mailbox 24 flag */ + CAN_FLAG_MB25 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 25U), /*!< mailbox 25 flag */ + CAN_FLAG_MB26 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 26U), /*!< mailbox 26 flag */ + CAN_FLAG_MB27 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 27U), /*!< mailbox 27 flag */ + CAN_FLAG_MB28 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 28U), /*!< mailbox 28 flag */ + CAN_FLAG_MB29 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 29U), /*!< mailbox 29 flag */ + CAN_FLAG_MB30 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 30U), /*!< mailbox 30 flag */ + CAN_FLAG_MB31 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 31U), /*!< mailbox 31 flag */ + CAN_FLAG_FIFO_AVAILABLE = CAN_REGIDX_BIT(STAT_REG_OFFSET, 5U), /*!< fifo availabe flag */ + CAN_FLAG_FIFO_WARNING = CAN_REGIDX_BIT(STAT_REG_OFFSET, 6U), /*!< fifo warning flag */ + CAN_FLAG_FIFO_OVERFLOW = CAN_REGIDX_BIT(STAT_REG_OFFSET, 7U), /*!< fifo overflow flag */ + /* flags in PN_STAT register */ + CAN_FLAG_WAKEUP_MATCH = CAN_REGIDX_BIT(PN_STAT_REG_OFFSET, 16U), /*!< Pretended Networking match flag */ + CAN_FLAG_WAKEUP_TIMEOUT = CAN_REGIDX_BIT(PN_STAT_REG_OFFSET, 17U), /*!< Pretended Networking timeout wakeup flag */ + /* flags in FDCTL register */ + CAN_FLAG_TDC_OUT_OF_RANGE = CAN_REGIDX_BIT(FDCTL_REG_OFFSET, 14U), /*!< transmitter delay is out of compensation range flag */ +} can_flag_enum; + +/* CAN interrupt flags */ +typedef enum { + /* interrupt flags in ERR1 register */ + CAN_INT_FLAG_ERR_SUMMARY = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 1U), /*!< error summary interrupt flag */ + CAN_INT_FLAG_BUSOFF = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 2U), /*!< bus off interrupt flag */ + CAN_INT_FLAG_RX_WARNING = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 16U), /*!< receive warning interrupt flag */ + CAN_INT_FLAG_TX_WARNING = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 17U), /*!< transmit warning interrupt flag */ + CAN_INT_FLAG_BUSOFF_RECOVERY = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 19U), /*!< bus off recovery interrupt flag */ + CAN_INT_FLAG_ERR_SUMMARY_FD = CAN_REGIDX_BIT(ERR1_REG_OFFSET, 20U), /*!< fd error summary interrupt flag */ + /* interrupt flags in STAT register */ + CAN_INT_FLAG_MB0 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< mailbox 0 interrupt flag */ + CAN_INT_FLAG_MB1 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< mailbox 1 interrupt flag */ + CAN_INT_FLAG_MB2 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< mailbox 2 interrupt flag */ + CAN_INT_FLAG_MB3 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< mailbox 3 interrupt flag */ + CAN_INT_FLAG_MB4 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< mailbox 4 interrupt flag */ + CAN_INT_FLAG_MB5 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 5U), /*!< mailbox 5 interrupt flag */ + CAN_INT_FLAG_MB6 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 6U), /*!< mailbox 6 interrupt flag */ + CAN_INT_FLAG_MB7 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 7U), /*!< mailbox 7 interrupt flag */ + CAN_INT_FLAG_MB8 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< mailbox 8 interrupt flag */ + CAN_INT_FLAG_MB9 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< mailbox 9 interrupt flag */ + CAN_INT_FLAG_MB10 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< mailbox 10 interrupt flag */ + CAN_INT_FLAG_MB11 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< mailbox 11 interrupt flag */ + CAN_INT_FLAG_MB12 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 12U), /*!< mailbox 12 interrupt flag */ + CAN_INT_FLAG_MB13 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 13U), /*!< mailbox 13 interrupt flag */ + CAN_INT_FLAG_MB14 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 14U), /*!< mailbox 14 interrupt flag */ + CAN_INT_FLAG_MB15 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 15U), /*!< mailbox 15 interrupt flag */ + CAN_INT_FLAG_MB16 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 16U), /*!< mailbox 16 interrupt flag */ + CAN_INT_FLAG_MB17 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 17U), /*!< mailbox 17 interrupt flag */ + CAN_INT_FLAG_MB18 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 18U), /*!< mailbox 18 interrupt flag */ + CAN_INT_FLAG_MB19 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 19U), /*!< mailbox 19 interrupt flag */ + CAN_INT_FLAG_MB20 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 20U), /*!< mailbox 20 interrupt flag */ + CAN_INT_FLAG_MB21 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 21U), /*!< mailbox 21 interrupt flag */ + CAN_INT_FLAG_MB22 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 22U), /*!< mailbox 22 interrupt flag */ + CAN_INT_FLAG_MB23 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 23U), /*!< mailbox 23 interrupt flag */ + CAN_INT_FLAG_MB24 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 24U), /*!< mailbox 24 interrupt flag */ + CAN_INT_FLAG_MB25 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 25U), /*!< mailbox 25 interrupt flag */ + CAN_INT_FLAG_MB26 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 26U), /*!< mailbox 26 interrupt flag */ + CAN_INT_FLAG_MB27 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 27U), /*!< mailbox 27 interrupt flag */ + CAN_INT_FLAG_MB28 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 28U), /*!< mailbox 28 interrupt flag */ + CAN_INT_FLAG_MB29 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 29U), /*!< mailbox 29 interrupt flag */ + CAN_INT_FLAG_MB30 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 30U), /*!< mailbox 30 interrupt flag */ + CAN_INT_FLAG_MB31 = CAN_REGIDX_BIT(STAT_REG_OFFSET, 31U), /*!< mailbox 31 interrupt flag */ + CAN_INT_FLAG_FIFO_AVAILABLE = CAN_REGIDX_BIT(STAT_REG_OFFSET, 5U), /*!< fifo availabe interrupt flag */ + CAN_INT_FLAG_FIFO_WARNING = CAN_REGIDX_BIT(STAT_REG_OFFSET, 6U), /*!< fifo warning interrupt flag */ + CAN_INT_FLAG_FIFO_OVERFLOW = CAN_REGIDX_BIT(STAT_REG_OFFSET, 7U), /*!< fifo overflow interrupt flag */ + /* interrupt flags in PN_STAT register */ + CAN_INT_FLAG_WAKEUP_MATCH = CAN_REGIDX_BIT(PN_STAT_REG_OFFSET, 16U), /*!< Pretended Networking match interrupt flag */ + CAN_INT_FLAG_WAKEUP_TIMEOUT = CAN_REGIDX_BIT(PN_STAT_REG_OFFSET, 17U) /*!< Pretended Networking timeout wakeup interrupt flag */ +} can_interrupt_flag_enum; + +/* operation modes */ +typedef enum { + GD32_CAN_NORMAL_MODE = 0U, /*!< normal mode */ + GD32_CAN_MONITOR_MODE = 1U, /*!< monitor mode */ + GD32_CAN_LOOPBACK_SILENT_MODE = 2U, /*!< loopback mode */ + GD32_CAN_INACTIVE_MODE = 3U, /*!< inactive mode */ + GD32_CAN_DISABLE_MODE = 4U, /*!< disable mode */ + GD32_CAN_PN_MODE = 5U /*!< Pretended Networking mode */ +} can_operation_modes_enum; + +/* initiliaze parameter type */ +typedef enum { + CAN_INIT_STRUCT = 0U, /*!< CAN initiliaze parameters struct */ + CAN_FD_INIT_STRUCT = 1U, /*!< CAN FD parameters struct */ + CAN_FIFO_INIT_STRUCT = 2U, /*!< CAN fifo parameters struct */ + CAN_PN_MODE_INIT_STRUCT = 3U, /*!< Pretended Networking mode parameter strcut */ + CAN_PN_MODE_FILTER_STRUCT = 4U, /*!< Pretended Networking mode filter parameter strcut */ + CAN_MDSC_STRUCT = 5U, /*!< mailbox descriptor strcut */ + CAN_FDES_STRUCT = 6U, /*!< Rx fifo descriptor strcut */ + CAN_FIFO_ID_FILTER_STRUCT = 7U, /*!< Rx fifo id filter strcut */ + CAN_CRC_STRUCT = 8U, /*!< CRC strcut */ + CAN_ERRCNT_STRUCT = 9U, /*!< error counter strcut */ +} can_struct_type_enum; + +/* error state indicator */ +typedef enum { + CAN_ERROR_STATE_ACTIVE = 0U, /*!< CAN in error active */ + CAN_ERROR_STATE_PASSIVE = 1U, /*!< CAN in error passive */ + CAN_ERROR_STATE_BUS_OFF = 2U /*!< CAN in bus off */ +} can_error_state_enum; + +/* error counter structure */ +typedef struct { + uint8_t fd_data_phase_rx_errcnt; /*!< receive error counter for data phase of FD frames with BRS bit set */ + uint8_t fd_data_phase_tx_errcnt; /*!< transmit error count for the data phase of FD frames with BRS bit set */ + uint8_t rx_errcnt; /*!< receive error count defined by the CAN standard */ + uint8_t tx_errcnt; /*!< transmit error count defined by the CAN standard */ +} can_error_counter_struct; + +/* CAN initiliaze parameters structure */ +typedef struct { + uint32_t internal_counter_source; /*!< internal counter source */ + uint32_t mb_tx_order; /*!< mailbox transmit order */ + uint32_t mb_rx_ide_rtr_type; /*!< IDE and RTR field fitler type */ + uint32_t mb_remote_frame; /*!< remote request frame is stored */ + uint8_t self_reception; /*!< enable or disable self reception */ + uint8_t mb_tx_abort_enable; /*!< enable or disable transmit abort */ + uint8_t local_priority_enable; /*!< enable or disable local priority */ + uint8_t rx_private_filter_queue_enable; /*!< private filter and queue enable */ + uint32_t edge_filter_enable; /*!< edge filter enable*/ + uint32_t protocol_exception_enable; /*!< protocol exception enable */ + uint32_t rx_filter_order; /*!< receive filter order */ + uint32_t memory_size; /*!< memory size */ + uint32_t mb_public_filter; /*!< mailbox public filter */ + uint32_t prescaler; /*!< baudrate prescaler */ + uint8_t resync_jump_width; /*!< resynchronization jump width */ + uint8_t prop_time_segment; /*!< propagation time segment */ + uint8_t time_segment_1; /*!< time segment 1 */ + uint8_t time_segment_2; /*!< time segment 2 */ +} can_parameter_struct; + +/* mailbox descriptor struct */ +typedef struct { + uint32_t timestamp : 16; /*!< free-running counter timestamp */ + uint32_t dlc : 4; /*!< data length code in bytes */ + uint32_t rtr : 1; /*!< remote transmission request */ + uint32_t ide : 1; /*!< ID extended bit */ + uint32_t srr : 1; /*!< substitute remote request */ + uint32_t reserve1 : 1; /*!< reserve bit 1 */ + uint32_t code : 4; /*!< mailbox code */ + uint32_t reserve2 : 1; /*!< reserve bit 2 */ + uint32_t esi : 1; /*!< error state indicator */ + uint32_t brs : 1; /*!< bit rate switch */ + uint32_t fdf : 1; /*!< FD format indicator */ + uint32_t id : 29; /*!< identifier for frame */ + uint32_t prio : 3; /*!< local priority */ + uint32_t *data; /*!< data */ + uint32_t data_bytes; /*!< data bytes */ + uint8_t padding; /*!< FD mode padding data */ +} can_mailbox_descriptor_struct; + +/* fifo descriptor struct */ +typedef struct { + uint32_t timestamp : 16; /*!< free-running counter timestamp */ + uint32_t dlc : 4; /*!< data length code in bytes */ + uint32_t rtr : 1; /*!< remote transmission request */ + uint32_t ide : 1; /*!< ID extended bit */ + uint32_t srr : 1; /*!< substitute remote request */ + uint32_t idhit : 9; /*!< identifier filter matching number */ + uint32_t id; /*!< identifier for frame */ + uint32_t data[2]; /*!< fifo data */ +} can_rx_fifo_struct; + +/* FD initiliaze parameter struct */ +typedef struct { + uint32_t iso_can_fd_enable; /*!< ISO CAN FD protocol enable */ + uint32_t bitrate_switch_enable; /*!< data bit rate switch */ + uint32_t mailbox_data_size; /*!< mailbox data size */ + uint32_t tdc_enable; /*!< trnasmitter delay compensation enable */ + uint32_t tdc_offset; /*!< trnasmitter delay compensation offset */ + uint32_t prescaler; /*!< baudrate prescaler */ + uint8_t resync_jump_width; /*!< resynchronization jump width */ + uint8_t prop_time_segment; /*!< propagation time segment */ + uint8_t time_segment_1; /*!< time segment 1 */ + uint8_t time_segment_2; /*!< time segment 2 */ +} can_fd_parameter_struct; + +/* FIFO ID filter table struct */ +typedef struct { + uint32_t remote_frame; /*!< expected remote frame*/ + uint32_t extended_frame; /*!< expected extended frame */ + uint32_t id; /*!< expected id */ +} can_rx_fifo_id_filter_struct; + +/* FIFO initiliaze parameter struct */ +typedef struct { + uint8_t dma_enable; /*!< DMA enable */ + uint32_t filter_format_and_number; /*!< FIFO ID filter format and number */ + uint32_t fifo_public_filter; /*!< FIFO ID public filter */ +} can_fifo_parameter_struct; + +/* Pretended Networking mode filter parameter struct */ +typedef struct { + uint32_t remote_frame; /*!< remote frame */ + uint32_t extended_frame; /*!< extended frame */ + uint32_t id; /*!< id */ + uint32_t dlc_high_threshold; /*!< DLC expected high threshold */ + uint32_t dlc_low_threshold; /*!< DLC expected low threshold */ + uint32_t payload[2]; /*!< data */ +} can_pn_mode_filter_struct; + +/* Pretended Networking mode initiliaze parameter struct */ +typedef struct { + uint32_t timeout_int; /*!< enable or disable timeout interrupt */ + uint32_t match_int; /*!< enable or disable match interrupt */ + uint32_t num_matches; /*!< set number of message matching times */ + uint32_t match_timeout; /*!< set wakeup timeout value */ + uint32_t frame_filter; /*!< set frame filtering type */ + uint32_t id_filter; /*!< set id filtering type */ + uint32_t data_filter; /*!< set data filtering type */ +} can_pn_mode_config_struct; + +/* CRC parameter struct */ +typedef struct { + uint32_t classical_frm_mb_number; /*!< associated number of mailbox for transmitting the CRCTC[14:0] value */ + uint32_t classical_frm_transmitted_crc; /*!< transmitted CRC value for classical frames */ + uint32_t classical_fd_frm_mb_number; /*!< associated number of mailbox for transmitting the CRCTCI[20:0] value */ + uint32_t classical_fd_frm_transmitted_crc; /*!< transmitted CRC value for classical and ISO / non-ISO FD frames */ +} can_crc_struct; + +/* CAN_CTL0 register */ +#define CTL0_MSZ(regval) (CAN_CTL0_MSZ & ((uint32_t)(regval) << 0U)) /*!< write value to CAN_CTL0_MSZ bit field */ +#define CAN_MEMSIZE_1_UNIT CTL0_MSZ(0U) /*!< 1 unit for message transmission and reception */ +#define CAN_MEMSIZE_2_UNIT CTL0_MSZ(1U) /*!< 2 units for message transmission and reception */ +#define CAN_MEMSIZE_3_UNIT CTL0_MSZ(2U) /*!< 3 units for message transmission and reception */ +#define CAN_MEMSIZE_4_UNIT CTL0_MSZ(3U) /*!< 4 units for message transmission and reception */ +#define CAN_MEMSIZE_5_UNIT CTL0_MSZ(4U) /*!< 5 units for message transmission and reception */ +#define CAN_MEMSIZE_6_UNIT CTL0_MSZ(5U) /*!< 6 units for message transmission and reception */ +#define CAN_MEMSIZE_7_UNIT CTL0_MSZ(6U) /*!< 7 units for message transmission and reception */ +#define CAN_MEMSIZE_8_UNIT CTL0_MSZ(7U) /*!< 8 units for message transmission and reception */ +#define CAN_MEMSIZE_9_UNIT CTL0_MSZ(8U) /*!< 9 units for message transmission and reception */ +#define CAN_MEMSIZE_10_UNIT CTL0_MSZ(9U) /*!< 10 units for message transmission and reception */ +#define CAN_MEMSIZE_11_UNIT CTL0_MSZ(10U) /*!< 11 units for message transmission and reception */ +#define CAN_MEMSIZE_12_UNIT CTL0_MSZ(11U) /*!< 12 units for message transmission and reception */ +#define CAN_MEMSIZE_13_UNIT CTL0_MSZ(12U) /*!< 13 units for message transmission and reception */ +#define CAN_MEMSIZE_14_UNIT CTL0_MSZ(13U) /*!< 14 units for message transmission and reception */ +#define CAN_MEMSIZE_15_UNIT CTL0_MSZ(14U) /*!< 15 units for message transmission and reception */ +#define CAN_MEMSIZE_16_UNIT CTL0_MSZ(15U) /*!< 16 units for message transmission and reception */ +#define CAN_MEMSIZE_17_UNIT CTL0_MSZ(16U) /*!< 17 units for message transmission and reception */ +#define CAN_MEMSIZE_18_UNIT CTL0_MSZ(17U) /*!< 18 units for message transmission and reception */ +#define CAN_MEMSIZE_19_UNIT CTL0_MSZ(18U) /*!< 19 units for message transmission and reception */ +#define CAN_MEMSIZE_20_UNIT CTL0_MSZ(19U) /*!< 20 units for message transmission and reception */ +#define CAN_MEMSIZE_21_UNIT CTL0_MSZ(20U) /*!< 21 units for message transmission and reception */ +#define CAN_MEMSIZE_22_UNIT CTL0_MSZ(21U) /*!< 22 units for message transmission and reception */ +#define CAN_MEMSIZE_23_UNIT CTL0_MSZ(22U) /*!< 23 units for message transmission and reception */ +#define CAN_MEMSIZE_24_UNIT CTL0_MSZ(23U) /*!< 24 units for message transmission and reception */ +#define CAN_MEMSIZE_25_UNIT CTL0_MSZ(24U) /*!< 25 units for message transmission and reception */ +#define CAN_MEMSIZE_26_UNIT CTL0_MSZ(25U) /*!< 26 units for message transmission and reception */ +#define CAN_MEMSIZE_27_UNIT CTL0_MSZ(26U) /*!< 27 units for message transmission and reception */ +#define CAN_MEMSIZE_28_UNIT CTL0_MSZ(27U) /*!< 28 units for message transmission and reception */ +#define CAN_MEMSIZE_29_UNIT CTL0_MSZ(28U) /*!< 29 units for message transmission and reception */ +#define CAN_MEMSIZE_30_UNIT CTL0_MSZ(29U) /*!< 30 units for message transmission and reception */ +#define CAN_MEMSIZE_31_UNIT CTL0_MSZ(30U) /*!< 31 units for message transmission and reception */ +#define CAN_MEMSIZE_32_UNIT CTL0_MSZ(31U) /*!< 32 units for message transmission and reception */ + +#define CTL0_FS(regval) (CAN_CTL0_FS & ((uint32_t)(regval) << 8U)) /*!< write value to CAN_CTL0_FS bit field */ +#define CAN_FIFO_FILTER_FORMAT_A CTL0_FS(0U) /*!< FIFO filter format A */ +#define CAN_FIFO_FILTER_FORMAT_B CTL0_FS(1U) /*!< FIFO filter format B */ +#define CAN_FIFO_FILTER_FORMAT_C CTL0_FS(2U) /*!< FIFO filter format C */ +#define CAN_FIFO_FILTER_FORMAT_D CTL0_FS(3U) /*!< FIFO filter format D */ + +#define GET_CTL0_FS(regval) GET_BITS((regval),8,9) /*!< get CAN_CTL0_FS bit field */ + +/* CAN_CTL1 register */ +#define CAN_TX_HIGH_PRIORITY_MB_FIRST ((uint32_t)0x00000000U) /*!< highest priority mailbox first */ +#define CAN_TX_LOW_NUM_MB_FIRST CAN_CTL1_MTO /*!< low number mailbox first */ + +#define CAN_BSP_MODE_ONE_SAMPLE ((uint32_t)0x00000000U) /*!< one sample for the received bit */ +#define CAN_BSP_MODE_THREE_SAMPLES CAN_CTL1_BSPMOD /*!< three sample for received bit */ + +/* CAN_ERR0 register */ +#define GET_ERR0_REFCNT(regval) GET_BITS((regval),24,31) /*!< get receive error counter for data phase of FD frames with BRS bit set */ +#define GET_ERR0_TEFCNT(regval) GET_BITS((regval),16,23) /*!< get transmit error counter for data phase of FD frames with BRS bit set */ +#define GET_ERR0_RECNT(regval) GET_BITS((regval),8,15) /*!< get receive error counter defined by the CAN standard */ +#define GET_ERR0_TECNT(regval) GET_BITS((regval),0,7) /*!< get transmit error counter defined by the CAN standard */ +#define ERR0_REFCNT(regval) (BITS(24,31) & ((uint32_t)(regval) << 24U)) /*!< set receive error counter for data phase of FD frames with BRS bit set */ +#define ERR0_TEFCNT(regval) (BITS(16,23) & ((uint32_t)(regval) << 16U)) /*!< set transmit error counter for data phase of FD frames with BRS bit set */ +#define ERR0_RECNT(regval) (BITS(8,15) & ((uint32_t)(regval) << 8U)) /*!< set receive error counter defined by the CAN standard */ +#define ERR0_TECNT(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< set transmit error counter defined by the CAN standard */ + +/* CAN_ERR1 register */ +#define GET_ERR1_ERRSI(regval) GET_BITS((regval),4,5) /*!< read CAN_ERR1_ERRSI bit field */ + +/* CAN_STAT register */ +#define STAT_MS(regval) BIT(regval) /*!< write value to CAN_STAT_MS bit field */ + +/* CAN_CTL2 register */ +#define CAN_TIMER_SOURCE_BIT_CLOCK ((uint32_t)0x00000000U) /*!< internal counter source is CAN bit clock */ +#define CAN_TIMER_SOURCE_EXTERNAL_TIME_TICK CAN_CTL2_ITSRC /*!< internal counter source is external time tick */ + +#define CAN_IDE_RTR_COMPARED ((uint32_t)0x00000000U) /*!< always compare IDE bit, never compare RTR bit */ +#define CAN_IDE_RTR_FILTERED CAN_CTL2_IDERTR_RMF /*!< filtering IDE and RTR fields */ + +#define CAN_GEN_REMOTE_RESPONSE_FRAME ((uint32_t)0x00000000U) /* remote response frame is generated when a mailbox with CODE RANSWER is found with the same ID */ +#define CAN_STORE_REMOTE_REQUEST_FRAME CAN_CTL2_RRFRMS /* remote request frame is stored as a data frame without automatic remote response frame transmitted */ + +#define CAN_RX_FILTER_ORDER_FIFO_FIRST ((uint32_t)0x00000000U) /*!< receive search FIFO first */ +#define CAN_RX_FILTER_ORDER_MAILBOX_FIRST CAN_CTL2_RFO /*!< receive search mailbox first */ + +#define CTL2_ASD(regval) (BITS(19,23) & ((uint32_t)(regval) << 19U)) /*!< write value to CAN_CTL2_ASD bit field */ + +#define CTL2_RFFN(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) /*!< write value to CAN_CTL2_RFFN bit field */ +#define GET_CTL2_RFFN(regval) GET_BITS((regval),24,27) /*!< get CAN_CTL2_RFFN bit field */ +#define CAN_RXFIFO_FILTER_A_NUM_8 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(0U)) /*!< FIFO ID filter format A and 8 filters */ +#define CAN_RXFIFO_FILTER_A_NUM_16 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(1U)) /*!< FIFO ID filter format A and 16 filters */ +#define CAN_RXFIFO_FILTER_A_NUM_24 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(2U)) /*!< FIFO ID filter format A and 24 filters */ +#define CAN_RXFIFO_FILTER_A_NUM_32 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(3U)) /*!< FIFO ID filter format A and 32 filters */ +#define CAN_RXFIFO_FILTER_A_NUM_40 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(4U)) /*!< FIFO ID filter format A and 40 filters */ +#define CAN_RXFIFO_FILTER_A_NUM_48 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(5U)) /*!< FIFO ID filter format A and 48 filters */ +#define CAN_RXFIFO_FILTER_A_NUM_56 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(6U)) /*!< FIFO ID filter format A and 56 filters */ +#define CAN_RXFIFO_FILTER_A_NUM_64 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(7U)) /*!< FIFO ID filter format A and 64 filters */ +#define CAN_RXFIFO_FILTER_A_NUM_72 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(8U)) /*!< FIFO ID filter format A and 72 filters */ +#define CAN_RXFIFO_FILTER_A_NUM_80 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(9U)) /*!< FIFO ID filter format A and 80 filters */ +#define CAN_RXFIFO_FILTER_A_NUM_88 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(10U)) /*!< FIFO ID filter format A and 88 filters */ +#define CAN_RXFIFO_FILTER_A_NUM_96 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(11U)) /*!< FIFO ID filter format A and 96 filters */ +#define CAN_RXFIFO_FILTER_A_NUM_104 (CAN_FIFO_FILTER_FORMAT_A | CTL2_RFFN(12U)) /*!< FIFO ID filter format A and 104 filters */ +#define CAN_RXFIFO_FILTER_B_NUM_16 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(0U)) /*!< FIFO ID filter format B and 16 filters */ +#define CAN_RXFIFO_FILTER_B_NUM_32 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(1U)) /*!< FIFO ID filter format B and 32 filters */ +#define CAN_RXFIFO_FILTER_B_NUM_48 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(2U)) /*!< FIFO ID filter format B and 48 filters */ +#define CAN_RXFIFO_FILTER_B_NUM_64 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(3U)) /*!< FIFO ID filter format B and 64 filters */ +#define CAN_RXFIFO_FILTER_B_NUM_80 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(4U)) /*!< FIFO ID filter format B and 80 filters */ +#define CAN_RXFIFO_FILTER_B_NUM_96 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(5U)) /*!< FIFO ID filter format B and 96 filters */ +#define CAN_RXFIFO_FILTER_B_NUM_112 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(6U)) /*!< FIFO ID filter format B and 112 filters */ +#define CAN_RXFIFO_FILTER_B_NUM_128 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(7U)) /*!< FIFO ID filter format B and 128 filters */ +#define CAN_RXFIFO_FILTER_B_NUM_144 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(8U)) /*!< FIFO ID filter format B and 144 filters */ +#define CAN_RXFIFO_FILTER_B_NUM_160 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(9U)) /*!< FIFO ID filter format B and 160 filters */ +#define CAN_RXFIFO_FILTER_B_NUM_176 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(10U)) /*!< FIFO ID filter format B and 176 filters */ +#define CAN_RXFIFO_FILTER_B_NUM_192 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(11U)) /*!< FIFO ID filter format B and 192 filters */ +#define CAN_RXFIFO_FILTER_B_NUM_208 (CAN_FIFO_FILTER_FORMAT_B | CTL2_RFFN(12U)) /*!< FIFO ID filter format B and 208 filters */ +#define CAN_RXFIFO_FILTER_C_NUM_32 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(0U)) /*!< FIFO ID filter format C and 32 filters */ +#define CAN_RXFIFO_FILTER_C_NUM_64 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(1U)) /*!< FIFO ID filter format C and 64 filters */ +#define CAN_RXFIFO_FILTER_C_NUM_96 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(2U)) /*!< FIFO ID filter format C and 96 filters */ +#define CAN_RXFIFO_FILTER_C_NUM_128 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(3U)) /*!< FIFO ID filter format C and 128 filters */ +#define CAN_RXFIFO_FILTER_C_NUM_160 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(4U)) /*!< FIFO ID filter format C and 160 filters */ +#define CAN_RXFIFO_FILTER_C_NUM_192 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(5U)) /*!< FIFO ID filter format C and 192 filters */ +#define CAN_RXFIFO_FILTER_C_NUM_224 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(6U)) /*!< FIFO ID filter format C and 224 filters */ +#define CAN_RXFIFO_FILTER_C_NUM_256 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(7U)) /*!< FIFO ID filter format C and 256 filters */ +#define CAN_RXFIFO_FILTER_C_NUM_288 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(8U)) /*!< FIFO ID filter format C and 288 filters */ +#define CAN_RXFIFO_FILTER_C_NUM_320 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(9U)) /*!< FIFO ID filter format C and 320 filters */ +#define CAN_RXFIFO_FILTER_C_NUM_352 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(10U)) /*!< FIFO ID filter format C and 352 filters */ +#define CAN_RXFIFO_FILTER_C_NUM_384 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(11U)) /*!< FIFO ID filter format C and 384 filters */ +#define CAN_RXFIFO_FILTER_C_NUM_416 (CAN_FIFO_FILTER_FORMAT_C | CTL2_RFFN(12U)) /*!< FIFO ID filter format C and 416 filters */ +#define CAN_RXFIFO_FILTER_D CAN_FIFO_FILTER_FORMAT_D /*!< FIFO ID filter format D */ + +/* CAN_CRCC register */ +#define GET_CRCC_ANTM(regval) GET_BITS((regval),16,20) /*!< get associated number of mailbox for transmitting the CRCTC[14:0] value */ +#define GET_CRCC_CRCTC(regval) GET_BITS((regval),0,14) /*!< get transmitted CRC value for classical frames */ + +/* CAN_RFIFOIFMN register */ +#define GET_RFIFOIFMN_IDFMN(regval) GET_BITS((regval),0,8) /*!< get identifier filter matching number */ + +/* CAN_BT register */ +#define BT_PBS2(regval) (BITS(0,4) & ((uint32_t)(regval) << 0U)) /*!< write value to CAN_BT_PBS2 bit field */ +#define BT_PBS1(regval) (BITS(5,9) & ((uint32_t)(regval) << 5U)) /*!< write value to CAN_BT_PBS1 bit field */ +#define BT_PTS(regval) (BITS(10,15) & ((uint32_t)(regval) << 10U)) /*!< write value to CAN_BT_PTS bit field */ +#define BT_SJW(regval) (BITS(16,20) & ((uint32_t)(regval) << 16U)) /*!< write value to CAN_BT_SJW bit field */ +#define BT_BAUDPSC(regval) (BITS(21,30) & ((uint32_t)(regval) << 21U)) /*!< write value to CAN_BT_BAUDPSC bit field */ + +/* CAN_FDCTL register */ +#define GET_FDCTL_MDSZ(regval) GET_BITS((regval),16,17) /*!< get mailbox data size */ + +/* CAN_PN_CTL0 register */ +#define PN_CTL0_FFT(regval) (BITS(0,1) & ((uint32_t)(regval) << 0U)) /*!< write value to CAN_PN_CTL0_FFT bit field */ +#define CAN_PN_FRAME_FILTERING_ID PN_CTL0_FFT(0U) /*!< all fields except DATA field, DLC field are filtered */ +#define CAN_PN_FRAME_FILTERING_ID_DATA PN_CTL0_FFT(1U) /*!< all fields are filtered */ +#define CAN_PN_FRAME_FILTERING_ID_NMM PN_CTL0_FFT(2U) /*!< all fields except DATA field, DLC field are filtered with NMM[7:0] matching times */ +#define CAN_PN_FRAME_FILTERING_ID_DATA_NMM PN_CTL0_FFT(3U) /*!< all fields are filtered with NMM[7:0] matching times */ + +#define PN_CTL0_IDFT(regval) (BITS(2,3) & ((uint32_t)(regval) << 2U)) /*!< write value to CAN_PN_CTL0_IDFT bit field */ +#define CAN_PN_ID_FILTERING_EXACT PN_CTL0_IDFT(0U) /*!< DATA field equal to the expected data field */ +#define CAN_PN_ID_FILTERING_GREATER PN_CTL0_IDFT(1U) /*!< DATA field greater than or equal to the expected data */ +#define CAN_PN_ID_FILTERING_SMALLER PN_CTL0_IDFT(2U) /*!< DATA field greater than or equal to the expected data */ +#define CAN_PN_ID_FILTERING_RANGE PN_CTL0_IDFT(3U) /*!< DATA field is between expected data high threshold and low threshold */ + +#define PN_CTL0_DATAFT(regval) (BITS(4,5) & ((uint32_t)(regval) << 4U)) /*!< write value to CAN_PN_CTL0_DATAFT bit field */ +#define CAN_PN_DATA_FILTERING_EXACT PN_CTL0_DATAFT(0U) /*!< ID field equal to the expected identifie */ +#define CAN_PN_DATA_FILTERING_GREATER PN_CTL0_DATAFT(1U) /*!< ID field greater than or equal to the expected identifier */ +#define CAN_PN_DATA_FILTERING_SMALLER PN_CTL0_DATAFT(2U) /*!< ID field smaller than or equal to the expected identifier */ +#define CAN_PN_DATA_FILTERING_RANGE PN_CTL0_DATAFT(3U) /*!< ID field is between expected idetifier high threshold and low threshold */ + +#define PN_CTL0_NMM(regval) (BITS(8,15) & ((uint32_t)(regval) << 8U)) /*!< write value to CAN_PN_CTL0_NMM bit field */ + +#define PN_CTL0_WMIE(regval) (BIT(16) & ((uint32_t)(regval) << 16U)) /*!< write value to CAN_PN_CTL0_WMIE bit */ + +#define PN_CTL0_WTOIE(regval) (BIT(17) & ((uint32_t)(regval) << 17U)) /*!< write value to CAN_PN_CTL0_WTOIE bit */ + +/* CAN_PN_TO register */ +#define PN_TO_WTO(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to CAN_PN_TO_WTO bit field */ + +/* CAN_PN_STAT register */ +#define GET_PN_STAT_MMCNT(regval) GET_BITS((regval),8,15) /*!< get matching message counter in Pretended Networking mode */ + +/* CAN_PN_EID0 register */ +#define PN_EID0_EIDF_ELT_STD(regval) (BITS(18,28) & ((uint32_t)(regval) << 18U)) /*!< write value to CAN_PN_EID0_EIDF_ELT bit field for standard frames */ +#define PN_EID0_EIDF_ELT_EXD(regval) (BITS(0,28) & ((uint32_t)(regval) << 0U)) /*!< write value to CAN_PN_EID0_EIDF_ELT bit field for extended frames */ + +/* CAN_PN_EDLC register */ +#define PN_EDLC_DLCEHT(regval) (BITS(0,3) & ((uint32_t)(regval) << 0U)) /*!< write value to CAN_PN_EDLC_DLCEHT bit field */ +#define PN_EDLC_DLCELT(regval) (BITS(16,19) & ((uint32_t)(regval) << 16U)) /*!< write value to CAN_PN_EDLC_DLCELT bit field */ + +/* CAN_PN_IFEID1 register */ +#define PN_IFEID1_IDEFD_STD(regval) (BITS(18,28) & ((uint32_t)(regval) << 18U)) /*!< write value to CAN_PN_IFEID1_IDEFD bit field for standard frames */ +#define PN_IFEID1_IDEFD_EXD(regval) (BITS(0,28) & ((uint32_t)(regval) << 0U)) /*!< write value to CAN_PN_IFEID1_IDEFD bit field for extended frames */ + +/* CAN_FDCTL register */ +#define GET_FDCTL_TDCV(regval) GET_BITS((regval),0,5) /*!< get transmitter delay compensation value */ + +#define FDCTL_TDCO(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to CAN_FDCTL_TDCO bit field */ + +#define FDCTL_MDSZ(regval) (BITS(16,17) & ((uint32_t)(regval) << 16U)) /*!< write value to CAN_FDCTL_MDSZ bit field */ +#define CAN_MAILBOX_DATA_SIZE_8_BYTES FDCTL_MDSZ(0U) /*!< mailbox data size is 8 bytes */ +#define CAN_MAILBOX_DATA_SIZE_16_BYTES FDCTL_MDSZ(1U) /*!< mailbox data size is 16 bytes */ +#define CAN_MAILBOX_DATA_SIZE_32_BYTES FDCTL_MDSZ(2U) /*!< mailbox data size is 32 bytes */ +#define CAN_MAILBOX_DATA_SIZE_64_BYTES FDCTL_MDSZ(3U) /*!< mailbox data size is 64 bytes */ + +/* CAN_FDBT register */ +#define FDBT_DPBS2(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U)) /*!< write value to CAN_FDBT_DPBS2 bit field */ +#define FDBT_DPBS1(regval) (BITS(5,7) & ((uint32_t)(regval) << 5U)) /*!< write value to CAN_FDBT_DPBS1 bit field */ +#define FDBT_DPTS(regval) (BITS(10,14) & ((uint32_t)(regval) << 10U)) /*!< write value to CAN_FDBT_DPTS bit field */ +#define FDBT_DSJW(regval) (BITS(16,18) & ((uint32_t)(regval) << 16U)) /*!< write value to CAN_FDBT_DSJW bit field */ +#define FDBT_DBAUDPSC(regval) (BITS(20,29) & ((uint32_t)(regval) << 20U)) /*!< write value to CAN_FDBT_DBAUDPSC bit field */ + +/* CAN_CRCCFD register */ +#define GET_CRCCFD_CRCTCI(regval) GET_BITS((regval),0,20) /*!< get transmitted CRC value for classical and ISO / non-ISO FD frames */ +#define GET_CRCCFD_ANTM(regval) GET_BITS((regval),24,28) /*!< get associated number of mailbox for transmitting the CRCTCI[20:0] value */ + +/* MDES0 descriptor */ +#define MDES0_DLC(regval) (BITS(16,19) & ((uint32_t)(regval) << 16U)) /*!< write value to MDES0 descriptor DLC bit field */ + +#define MDES0_CODE(regval) (((uint32_t)(regval) << 24U) & CAN_MDES0_CODE) +#define CAN_MB_RX_STATUS_INACTIVE (0U) /*!< mailbox receive status inactive */ +#define CAN_MB_RX_STATUS_FULL (2U) /*!< mailbox receive status full */ +#define CAN_MB_RX_STATUS_EMPTY (4U) /*!< mailbox receive status empty */ +#define CAN_MB_RX_STATUS_OVERRUN (6U) /*!< mailbox receive status overrun */ +#define CAN_MB_RX_STATUS_RANSWER (10U) /*!< mailbox receive status answer */ +#define CAN_MB_RX_STATUS_BUSY (1U) /*!< mailbox receive status busy */ +#define CAN_MB_TX_STATUS_INACTIVE (8U) /*!< mailbox transmit status inactive */ +#define CAN_MB_TX_STATUS_ABORT (9U) /*!< mailbox transmit status abort */ +#define CAN_MB_TX_STATUS_DATA (12U) /*!< mailbox transmit status data */ + +#define GET_MDES0_CODE(regval) GET_BITS((regval),24,27) /*!< get MDES0 descriptor CODE bit field */ + +/* MDES1 descriptor */ +#define GET_MDES1_ID_EXD(regval) GET_BITS((regval),0,28) /*!< get MDES1 descriptor ID_STD and ID_EXD bit field */ +#define MDES1_ID_EXD(regval) (BITS(0,28) & ((uint32_t)(regval) << 0U)) /*!< write value to MDES1 descriptor ID_STD and ID_EXD bit field */ + +#define GET_MDES1_ID_STD(regval) GET_BITS((regval),18,28) /*!< get MDES1 descriptor ID_STD bit field */ +#define MDES1_ID_STD(regval) (BITS(18,28) & ((uint32_t)(regval) << 18U)) /*!< write value to MDES1 descriptor ID_STD bit field */ + +#define MDES1_PRIO(regval) (BITS(29,31) & ((uint32_t)(regval) << 29U)) /*!< write value to MDES1 descriptor PRIO bit field */ + +/* FDES1 descriptor */ +#define GET_FDES1_ID_EXD(regval) GET_BITS((regval),0,28) /*!< get FDES1 descriptor ID_STD and ID_EXD bit field */ +#define FDES1_ID_EXD(regval) (BITS(0,28) & ((uint32_t)(regval) << 0U)) /*!< write value to FDES1 descriptor ID_STD and ID_EXD bit field */ + +#define GET_FDES1_ID_STD(regval) GET_BITS((regval),18,28) /*!< get FDES1 descriptor ID_STD bit field */ +#define FDES1_ID_STD(regval) (BITS(18,28) & ((uint32_t)(regval) << 18U)) /*!< write value to FDES1 descriptor ID_STD bit field */ + +/* FDESx descriptor */ +#define CAN_DATA_FRAME_ACCEPTED ((uint32_t)0x00000000U) /*!< remote frames are rejected and data frames can be stored */ +#define CAN_REMOTE_FRAME_ACCEPTED ((uint32_t)0x00000001U) /*!< remote frames can be stored and data frames are rejected */ + +#define CAN_STANDARD_FRAME_ACCEPTED ((uint32_t)0x00000000U) /*!< extended frames are rejected and standard frames can be stored */ +#define CAN_EXTENDED_FRAME_ACCEPTED ((uint32_t)0x00000001U) /*!< extended frames can be stored and standard frames are rejected */ + +#define FIFO_FILTER_ID_EXD_A(val) (((uint32_t)(val) << 0U) & CAN_FDESX_ID_EXD_A) /*!< valid extended ID filter field in format A */ +#define FIFO_FILTER_ID_STD_A(val) (((uint32_t)(val) << 18U) & CAN_FDESX_ID_STD_A)/*!< valid standard ID filter field in format A */ +#define FIFO_FILTER_ID_EXD_B0(val) (GET_BITS((val),15,28) << 16U) /*!< valid extended ID filter field in format B */ +#define FIFO_FILTER_ID_EXD_B1(val) (GET_BITS((val),15,28) << 0U) /*!< valid extended ID filter field in format B */ +#define FIFO_FILTER_ID_STD_B0(val) (GET_BITS((val),0,10) << 19U) /*!< valid standard ID filter field in format B */ +#define FIFO_FILTER_ID_STD_B1(val) (GET_BITS((val),0,10) << 3U) /*!< valid standard ID filter field in format B */ +#define FIFO_FILTER_ID_EXD_C0(val) (GET_BITS((val),21,28) << 24U) /*!< valid extended ID filter field in format C */ +#define FIFO_FILTER_ID_EXD_C1(val) (GET_BITS((val),21,28) << 16U) /*!< valid extended ID filter field in format C */ +#define FIFO_FILTER_ID_EXD_C2(val) (GET_BITS((val),21,28) << 8U) /*!< valid extended ID filter field in format C */ +#define FIFO_FILTER_ID_EXD_C3(val) (GET_BITS((val),21,28) << 0U) /*!< valid extended ID filter field in format C */ +#define FIFO_FILTER_ID_STD_C0(val) (GET_BITS((val),3,10) << 24U) /*!< valid standard ID filter field in format C */ +#define FIFO_FILTER_ID_STD_C1(val) (GET_BITS((val),3,10) << 16U) /*!< valid standard ID filter field in format C */ +#define FIFO_FILTER_ID_STD_C2(val) (GET_BITS((val),3,10) << 8U) /*!< valid standard ID filter field in format C */ +#define FIFO_FILTER_ID_STD_C3(val) (GET_BITS((val),3,10) << 0U) /*!< valid standard ID filter field in format C */ + +/* timeout definitions */ +#define CAN_DELAY ((uint32_t)0x01FFFFFFU) /*!< state timeout */ +#define CAN_MAX_MAILBOX_NUM 32U /*!< the supported maximum mailbox number */ +#define CAN_MAX_RAM_SIZE (CAN_MAX_MAILBOX_NUM * 4U) /*!< the maximum RAM size used for CAN mailbox */ + + +/* function declarations */ +/* CAN module initialize */ +/* deinitialize CAN */ +void can_deinit(uint32_t can_periph); +/* reset CAN interanl state machines and CAN registers */ +ErrStatus can_software_reset(uint32_t can_periph); +/* CAN module initialization */ +ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init); +/* initialize CAN parameter structure with a default value */ +void can_struct_para_init(can_struct_type_enum type, void *p_struct); +/* configure receive fifo/mailbox private filter */ +void can_private_filter_config(uint32_t can_periph, uint32_t index, uint32_t filter_data); + +/* CAN operation modes */ +/* enter the corresponding mode */ +ErrStatus can_operation_mode_enter(uint32_t can_periph, can_operation_modes_enum mode); +/* get operation mode */ +can_operation_modes_enum can_operation_mode_get(uint32_t can_periph); +/* exit inactive mode */ +ErrStatus can_inactive_mode_exit(uint32_t can_periph); +/* exit Pretended Networking mode */ +ErrStatus can_pn_mode_exit(uint32_t can_periph); + +/* CAN FD mode configuration */ +/* can FD initialize */ +void can_fd_config(uint32_t can_periph, can_fd_parameter_struct *can_fd_para_init); +/* enable bit rate switching */ +void can_bitrate_switch_enable(uint32_t can_periph); +/* disable bit rate switching */ +void can_bitrate_switch_disable(uint32_t can_periph); +/* get transmitter delay compensation value */ +uint32_t can_tdc_get(uint32_t can_periph); +/* enable transmitter delay compensation */ +void can_tdc_enable(uint32_t can_periph); +/* disable transmitter delay compensation */ +void can_tdc_disable(uint32_t can_periph); + +/* CAN FIFO configuration */ +/* configure rx FIFO */ +void can_rx_fifo_config(uint32_t can_periph, can_fifo_parameter_struct *can_fifo_para_init); +/* configure rx FIFO filter table */ +void can_rx_fifo_filter_table_config(uint32_t can_periph, can_rx_fifo_id_filter_struct id_filter_table[]); +/* read rx FIFO data */ +void can_rx_fifo_read(uint32_t can_periph, can_rx_fifo_struct *rx_fifo); +/* get rx FIFO filter matching number */ +uint32_t can_rx_fifo_filter_matching_number_get(uint32_t can_periph); +/* clear rx FIFO */ +void can_rx_fifo_clear(uint32_t can_periph); + +/* CAN mailbox operation */ +/* get mailbox RAM address */ +uint32_t *can_ram_address_get(uint32_t can_periph, uint32_t index); +/* config mailbox */ +void can_mailbox_config(uint32_t can_periph, uint32_t index, can_mailbox_descriptor_struct *mdpara); +/* abort mailbox transmit */ +void can_mailbox_transmit_abort(uint32_t can_periph, uint32_t index); +/* inactive transmit mailbox */ +void can_mailbox_transmit_inactive(uint32_t can_periph, uint32_t index); +/* read receive mailbox data */ +ErrStatus can_mailbox_receive_data_read(uint32_t can_periph, uint32_t index, can_mailbox_descriptor_struct *mdpara); +/* lock the receive mailbox */ +void can_mailbox_receive_lock(uint32_t can_periph, uint32_t index); +/* unlock the receive mailbox */ +void can_mailbox_receive_unlock(uint32_t can_periph); +/* inactive the receive mailbox */ +void can_mailbox_receive_inactive(uint32_t can_periph, uint32_t index); +/* get mailbox code value */ +uint32_t can_mailbox_code_get(uint32_t can_periph, uint32_t index); + +/* errors & CRC */ +/* configure error counter */ +void can_error_counter_config(uint32_t can_periph, can_error_counter_struct *errcnt_struct); +/* get error count */ +void can_error_counter_get(uint32_t can_periph, can_error_counter_struct *errcnt_struct); +/* get error state indicator */ +can_error_state_enum can_error_state_get(uint32_t can_periph); +/* get mailbox CRC value */ +void can_crc_get(uint32_t can_periph, can_crc_struct *crc_struct); + +/* Pretended Networking mode configuration */ +/* configure Pretended Networking mode parameter */ +void can_pn_mode_config(uint32_t can_periph, can_pn_mode_config_struct *pnmod_config); +/* configure pn mode filter */ +void can_pn_mode_filter_config(uint32_t can_periph, can_pn_mode_filter_struct *expect, can_pn_mode_filter_struct *filter); +/* get matching message counter of Pretended Networking mode */ +int32_t can_pn_mode_num_of_match_get(uint32_t can_periph); +/* get matching message */ +void can_pn_mode_data_read(uint32_t can_periph, uint32_t index, can_mailbox_descriptor_struct *mdpara); + +/* others */ +/* enable self reception */ +void can_self_reception_enable(uint32_t can_periph); +/* disable self reception */ +void can_self_reception_disable(uint32_t can_periph); +/* enable transmit abort */ +void can_transmit_abort_enable(uint32_t can_periph); +/* disable transmit abort */ +void can_transmit_abort_disable(uint32_t can_periph); +/* enable auto bus off recovery mode */ +void can_auto_busoff_recovery_enable(uint32_t can_periph); +/* disable auto bus off recovery mode */ +void can_auto_busoff_recovery_disable(uint32_t can_periph); +/* enable time sync mode */ +void can_time_sync_enable(uint32_t can_periph); +/* disable time sync mode */ +void can_time_sync_disable(uint32_t can_periph); +/* enable edge filter mode */ +void can_edge_filter_mode_enable(uint32_t can_periph); +/* disable edge filter mode */ +void can_edge_filter_mode_disable(uint32_t can_periph); +/* enable protocol exception detection mode */ +void can_ped_mode_enable(uint32_t can_periph); +/* disable protocol exception detection mode */ +void can_ped_mode_disable(uint32_t can_periph); +/* configure arbitation delay bits */ +void can_arbitation_delay_bits_config(uint32_t can_periph, uint32_t delay_bits); +/* configure bit sampling mode */ +void can_bsp_mode_config(uint32_t can_periph, uint32_t sampling_mode); + +/* CAN interrupt and flag */ +/* get CAN flag */ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); +/* clear CAN flag */ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag); +/* enable CAN interrupt */ +void can_interrupt_enable(uint32_t can_periph, can_interrupt_enum interrupt); +/* disable CAN interrupt */ +void can_interrupt_disable(uint32_t can_periph, can_interrupt_enum interrupt); +/* get CAN interrupt flag */ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum int_flag); +/* clear CAN interrupt flag */ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum int_flag); + +#endif /* GD32A50X_CAN_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_cmp.h b/gd32a50x/standard_peripheral/include/gd32a50x_cmp.h new file mode 100644 index 0000000..df6304e --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_cmp.h @@ -0,0 +1,240 @@ +/*! + \file gd32a50x_cmp.h + \brief definitions for the CMP + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_CMP_H +#define GD32A50X_CMP_H + +#include "gd32a50x.h" + +/* CMP definitions */ +#define CMP CMP_BASE + 0x00000000U /*!< CMP base address */ + +/* registers definitions */ +#define CMP_CS REG32(CMP + 0x00000000U) /*!< CMP control and status register */ + +/* bits definitions */ +/* CMP_CS */ +#define CMP_CS_EN BIT(0) /*!< CMP enable */ +#define CMP_CS_PM BITS(2,3) /*!< CMP mode */ +#define CMP_CS_MESEL BITS(4,6) /*!< CMP_IM external input selection */ +#define CMP_CS_MISEL BITS(7,9) /*!< CMP_IM internal input selection */ +#define CMP_CS_PSEL BITS(10,12) /*!< CMP_IP input selection */ +#define CMP_CS_OSEL BITS(13,14) /*!< CMP output selection */ +#define CMP_CS_PL BIT(15) /*!< polarity of CMP output */ +#define CMP_CS_HST BITS(16,17) /*!< CMP hysteresis */ +#define CMP_CS_BLK BITS(18,20) /*!< CMP output blanking source */ +#define CMP_CS_BEN BIT(22) /*!< scaler bridge enable bit */ +#define CMP_CS_SEN BIT(23) /*!< voltage input scaler */ +#define CMP_CS_OT BIT(30) /*!< CMP output */ +#define CMP_CS_LK BIT(31) /*!< CMP lock */ + +/* constants definitions */ +/* operating mode */ +typedef enum { + CMP_HIGHSPEED = 0, /*!< high speed mode */ + CMP_MIDDLESPEED = 1, /*!< middle speed mode */ + CMP_LOWSPEED = 3 /*!< low speed mode */ +} operating_mode_enum; + +/* inverting input */ +typedef enum { + CMP_1_4VREFINT = 0, /*!< VREFINT /4 input */ + CMP_1_2VREFINT = 8, /*!< VREFINT /2 input */ + CMP_3_4VREFINT = 16, /*!< VREFINT *3/4 input */ + CMP_VREFINT = 24, /*!< VREFINT input */ + CMP_DAC_OUT = 32, /*!< DAC_OUT input */ + CMP_IM_PC11 = 40, /*!< PC11*/ + CMP_IM_PC10 = 41, /*!< PC10 */ + CMP_IM_PB8 = 42, /*!< PB8 */ + CMP_IM_PA0 = 43, /*!< PA0 */ + CMP_IM_PA3 = 44, /*!< PA3 */ + CMP_IM_PA4 = 45, /*!< PA4 */ + CMP_IM_PA5 = 46, /*!< PA5 */ + CMP_IM_PA6 = 47, /*!< PA6 */ +} cmp_inverting_input_enum; + +/* plus input */ +typedef enum { + CMP_IP_PC11 = 0, /*!< PC11*/ + CMP_IP_PC10, /*!< PC10 */ + CMP_IP_PB8, /*!< PB8 */ + CMP_IP_PA0, /*!< PA0 */ + CMP_IP_PA3, /*!< PA3 */ + CMP_IP_PA4, /*!< PA4 */ + CMP_IP_PA5, /*!< PA5 */ + CMP_IP_PA6 /*!< PA6 */ +} cmp_plus_input_enum; + +/* hysteresis */ +typedef enum { + CMP_HYSTERESIS_NO = 0, /*!< output no hysteresis */ + CMP_HYSTERESIS_LOW, /*!< output low hysteresis */ + CMP_HYSTERESIS_MIDDLE, /*!< output middle hysteresis */ + CMP_HYSTERESIS_HIGH /*!< output high hysteresis */ +} cmp_hysteresis_enum; + +/* output */ +typedef enum { + CMP_OUTPUT_NONE = 0, /*!< output no selection */ + CMP_OUTPUT_TIMER0IC0, /*!< TIMER 0 channel0 input capture */ + CMP_OUTPUT_TIMER7IC0 /*!< TIMER 7 channel0 input capture */ +} cmp_output_enum; + +/* output inv */ +typedef enum { + CMP_OUTPUT_POLARITY_NOINVERTED = 0, /*!< output is not inverted */ + CMP_OUTPUT_POLARITY_INVERTED /*!< output is inverted */ +} cmp_output_inv_enum; + +/* blanking_source*/ +typedef enum { + CMP_BLANKING_NONE = 0, /*!< no blanking */ + CMP_BLANKING_TIMER0_OC1, /*!< select TIMER0_CH1 as blanking source */ + CMP_BLANKING_TIMER7_OC1, /*!< select TIMER7_CH1 as blanking source */ + CMP_BLANKING_TIMER1_OC1 /*!< select TIMER1_CH1 as blanking source */ +} blanking_source_enum; + +/* output state */ +typedef enum { + CMP_OUTPUTLEVEL_LOW = 0, /*!< the output is low */ + CMP_OUTPUTLEVEL_HIGH /*!< the output is high */ +} cmp_output_state_enum; + +/* CMP mode */ +#define CS_CMPPM(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define CS_CMPPM_HIGHSPEED CS_CMPPM(0) /*!< CMP mode high speed */ +#define CS_CMPPM_MIDDLESPEED CS_CMPPM(1) /*!< CMP mode middle speed */ +#define CS_CMPPM_LOWSPEED CS_CMPPM(3) /*!< CMP mode low speed */ + +/* CMP input */ +/* IM input */ +#define CS_CMPMSEL(regval) (BITS(4,9) & ((uint32_t)(regval) << 4)) +#define CS_CMPMSEL_1_4VREFINT CS_CMPMSEL(0) /*!< CMP inverting internal input VREFINT *1/4 */ +#define CS_CMPMSEL_1_2VREFINT CS_CMPMSEL(8) /*!< CMP inverting internal input VREFINT *1/2 */ +#define CS_CMPMSEL_3_4VREFINT CS_CMPMSEL(16) /*!< CMP inverting internal input VREFINT *3/4 */ +#define CS_CMPMSEL_VREFINT CS_CMPMSEL(24) /*!< CMP inverting internal input VREFINT */ +#define CS_CMPMSEL_DAC_OUT CS_CMPMSEL(32) /*!< CMP inverting internal input DAC_OUT */ +#define CS_CMPMSEL_PC11 CS_CMPMSEL(40) /*!< CMP inverting external input PC11 */ +#define CS_CMPMSEL_PC10 CS_CMPMSEL(41) /*!< CMP inverting external input PC10 */ +#define CS_CMPMSEL_PB8 CS_CMPMSEL(42) /*!< CMP inverting external input PB8 */ +#define CS_CMPMSEL_PA0 CS_CMPMSEL(43) /*!< CMP inverting external input PA0 */ +#define CS_CMPMSEL_PA3 CS_CMPMSEL(44) /*!< CMP inverting external input PA3 */ +#define CS_CMPMSEL_PA4 CS_CMPMSEL(45) /*!< CMP inverting external input PA4 */ +#define CS_CMPMSEL_PA5 CS_CMPMSEL(46) /*!< CMP inverting external input PA5 */ +#define CS_CMPMSEL_PA6 CS_CMPMSEL(47) /*!< CMP inverting external input PA6 */ + +/* IP input */ +#define CS_CMPPSEL(regval) (BITS(10,12) & ((uint32_t)(regval) << 10)) +#define CS_CMPPSEL_PC11 CS_CMPPSEL(0) /*!< CMP plus input PC11 */ +#define CS_CMPPSEL_PC10 CS_CMPPSEL(1) /*!< CMP plus input PC10 */ +#define CS_CMPPSEL_PB8 CS_CMPPSEL(2) /*!< CMP plus input PB8 */ +#define CS_CMPPSEL_PA0 CS_CMPPSEL(3) /*!< CMP plus input PA0 */ +#define CS_CMPPSEL_PA3 CS_CMPPSEL(4) /*!< CMP plus input PA3 */ +#define CS_CMPPSEL_PA4 CS_CMPPSEL(5) /*!< CMP plus input PA4 */ +#define CS_CMPPSEL_PA5 CS_CMPPSEL(6) /*!< CMP plus input PA5 */ +#define CS_CMPPSEL_PA6 CS_CMPPSEL(7) /*!< CMP plus input PA6 */ + +/* CMP output selection */ +#define CS_CMPOSEL(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) +#define CS_CMPOSEL_NOSELECTION CS_CMPOSEL(0) /*!< CMP no output selection */ +#define CS_CMPOSEL_TIMER0IC0 CS_CMPOSEL(1) /*!< CMP as TIMER0 channel0 input capture source */ +#define CS_CMPOSEL_TIMER7IC0 CS_CMPOSEL(2) /*!< CMP as TIMER7 channel0 input capture source */ + +/* CMP output polarity*/ +#define CS_CMPPL(regval) (BIT(15) & ((uint32_t)(regval) << 15)) +#define CS_CMPPL_NOT CS_CMPPL(0) /*!< CMP output not inverted */ +#define CS_CMPPL_INV CS_CMPPL(1) /*!< CMP output inverted */ + +/* CMP hysteresis */ +#define CS_CMPHST(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) +#define CS_CMPHST_HYSTERESIS_NO CS_CMPHST(0) /*!< CMP output no hysteresis */ +#define CS_CMPHST_HYSTERESIS_LOW CS_CMPHST(1) /*!< CMP output low hysteresis */ +#define CS_CMPHST_HYSTERESIS_MIDDLE CS_CMPHST(2) /*!< CMP output middle hysteresis */ +#define CS_CMPHST_HYSTERESIS_HIGH CS_CMPHST(3) /*!< CMP output high hysteresis */ + +/* CMP blanking suorce */ +#define CS_CMPBLK(regval) (BITS(18,20) & ((uint32_t)(regval) << 18)) +#define CS_CMPBLK_NOBLK CS_CMPBLK(0) /*!< CMP no blanking */ +#define CS_CMPBLK_TIMER0_OC1 CS_CMPBLK(1) /*!< CMP TIMER0 OC1 selected as blanking source */ +#define CS_CMPBLK_TIMER7_OC1 CS_CMPBLK(2) /*!< CMP TIMER7 OC1 selected as blanking source */ +#define CS_CMPBLK_TIMER1_OC1 CS_CMPBLK(4) /*!< CMP TIMER1 OC1 selected as blanking source */ + +/* CMP bridge enable*/ +#define CS_CMPBEN(regval) (BIT(22) & ((uint32_t)(regval) << 22)) +#define CS_CMPBEN_DISABLE CS_CMPBEN(0) /*!< CMP bridge enable */ +#define CS_CMPBEN_ENABLE CS_CMPBEN(1) /*!< CMP bridge disable */ + +/* CMP voltage scaler*/ +#define CS_CMPSEN(regval) (BIT(23) & ((uint32_t)(regval) << 23)) +#define CS_CMPSEN_DISABLE CS_CMPSEN(0) /*!< CMP voltage scaler enable */ +#define CS_CMPSEN_ENABLE CS_CMPSEN(1) /*!< CMP voltage scaler disable */ + +/* CMP lock bit*/ +#define CS_CMPLK(regval) (BIT(31) & ((uint32_t)(regval) << 31)) +#define CS_CMPLK_DISABLE CS_CMPLK(0) /*!< CMP_CS bits are read-write */ +#define CS_CMPLK_ENABLE CS_CMPLK(1) /*!< CMP_CS bits are read-only */ + +/* function declarations */ +/* initialization functions */ +/* deinitialize comparator */ +void cmp_deinit(void); +/* initialize comparator mode */ +void cmp_mode_init(operating_mode_enum operating_mode, cmp_inverting_input_enum inverting_input, cmp_plus_input_enum plus_input, + cmp_hysteresis_enum output_hysteresis); +/* initialize comparator output */ +void cmp_output_init(cmp_output_enum output_selection, cmp_output_inv_enum output_polarity); +/* initialize comparator blanking function */ +void cmp_outputblank_init(blanking_source_enum blanking_source_selection); + +/* enable functions */ +/* enable comparator */ +void cmp_enable(void); +/* disable comparator */ +void cmp_disable(void); +/* enable the voltage scaler */ +void cmp_voltage_scaler_enable(void); +/* disable the voltage scaler */ +void cmp_voltage_scaler_disable(void); +/* enable the scaler bridge */ +void cmp_scaler_bridge_enable(void); +/* disable the scaler bridge */ +void cmp_scaler_bridge_disable(void); +/* lock the comparator */ +void cmp_lock_enable(void); + +/* output functions */ +/* get output level */ +cmp_output_state_enum cmp_output_level_get(void); + +#endif /* GD32A50X_CMP_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_crc.h b/gd32a50x/standard_peripheral/include/gd32a50x_crc.h new file mode 100644 index 0000000..7100fcb --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_crc.h @@ -0,0 +1,122 @@ +/*! + \file gd32a50x_crc.h + \brief definitions for the CRC + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_CRC_H +#define GD32A50X_CRC_H + +#include "gd32a50x.h" + +/* CRC definitions */ +#define CRC CRC_BASE /*!< CRC bsae address */ + +/* registers definitions */ +#define CRC_DATA REG32((CRC) + 0x00000000U) /*!< CRC data register */ +#define CRC_FDATA REG32((CRC) + 0x00000004U) /*!< CRC free data register */ +#define CRC_CTL REG32((CRC) + 0x00000008U) /*!< CRC control register */ +#define CRC_IDATA REG32((CRC) + 0x00000010U) /*!< CRC initialization data register */ +#define CRC_POLY REG32((CRC) + 0x00000014U) /*!< CRC polynomial register */ + +/* bits definitions */ +/* CRC_DATA */ +#define CRC_DATA_DATA BITS(0, 31) /*!< CRC data bits */ + +/* CRC_FDATA */ +#define CRC_FDATA_FDATA BITS(0, 7) /*!< CRC free data bits */ + +/* CRC_CTL */ +#define CRC_CTL_RST BIT(0) /*!< CRC reset bit */ +#define CRC_CTL_PS BITS(3, 4) /*!< size of polynomial function bits */ +#define CRC_CTL_REV_I BITS(5, 6) /*!< input data reverse function bits */ +#define CRC_CTL_REV_O BIT(7) /*!< output data reverse function bit */ + +/* CRC_INIT */ +#define CRC_IDATA_IDATA BITS(0, 31) /*!< CRC initialization data bits */ + +/* CRC_POLY */ +#define CRC_POLY_POLY BITS(0, 31) /*!< CRC polynomial value bits */ + +/* constants definitions */ +/* size of polynomial function */ +#define CTL_PS(regval) (BITS(3, 4) & ((regval) << 3)) +#define CRC_CTL_PS_32 CTL_PS(0) /*!< 32-bit polynomial for CRC calculation */ +#define CRC_CTL_PS_16 CTL_PS(1) /*!< 16-bit polynomial for CRC calculation */ +#define CRC_CTL_PS_8 CTL_PS(2) /*!< 8-bit polynomial for CRC calculation */ +#define CRC_CTL_PS_7 CTL_PS(3) /*!< 7-bit polynomial for CRC calculation */ + +/* input data reverse function */ +#define CTL_REV_I(regval) (BITS(5, 6) & ((regval) << 5)) +#define CRC_INPUT_DATA_NOT CTL_REV_I(0) /*!< input data not reverse */ +#define CRC_INPUT_DATA_BYTE CTL_REV_I(1) /*!< input data reversed by byte type */ +#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2) /*!< input data reversed by half-word type */ +#define CRC_INPUT_DATA_WORD CTL_REV_I(3) /*!< input data reversed by word type */ + +/* input data format */ +#define INPUT_FORMAT_WORD 0U /*!< input data in word format */ +#define INPUT_FORMAT_HALFWORD 1U /*!< input data in half-word format */ +#define INPUT_FORMAT_BYTE 2U /*!< input data in byte format */ + +/* function declarations */ +/* deinit CRC calculation unit */ +void crc_deinit(void); +/* enable the reverse operation of output data */ +void crc_reverse_output_data_enable(void); +/* disable the reverse operation of output data */ +void crc_reverse_output_data_disable(void); + +/* reset data register to the value of initialization data register */ +void crc_data_register_reset(void); +/* read the data register */ +uint32_t crc_data_register_read(void); + +/* read the free data register */ +uint8_t crc_free_data_register_read(void); +/* write the free data register */ +void crc_free_data_register_write(uint8_t free_data); + +/* write the initial value register */ +void crc_init_data_register_write(uint32_t init_data); +/* configure the CRC input data function */ +void crc_input_data_reverse_config(uint32_t data_reverse); + +/* configure the CRC size of polynomial function */ +void crc_polynomial_size_set(uint32_t poly_size); +/* configure the CRC polynomial value function */ +void crc_polynomial_set(uint32_t poly); + +/* CRC calculate single data */ +uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format); +/* CRC calculate a data array */ +uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format); + +#endif /* GD32A50X_CRC_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_dac.h b/gd32a50x/standard_peripheral/include/gd32a50x_dac.h new file mode 100644 index 0000000..17d000f --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_dac.h @@ -0,0 +1,210 @@ +/*! + \file gd32fxxx_dac.h + \brief definitions for the DAC + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_DAC_H +#define GD32A50X_DAC_H + +#include "gd32a50x.h" + +/* DAC definitions */ +#define DAC DAC_BASE /*!< DAC base address */ + +/* registers definitions */ +#define DAC_CTL REG32(DAC + 0x00000000U) /*!< DAC control register */ +#define DAC_SWT REG32(DAC + 0x00000004U) /*!< DAC software trigger register */ +#define OUT_R12DH REG32(DAC + 0x00000008U) /*!< DAC_OUT 12-bit right-aligned data holding register */ +#define OUT_L12DH REG32(DAC + 0x0000000CU) /*!< DAC_OUT 12-bit left-aligned data holding register */ +#define OUT_R8DH REG32(DAC + 0x00000010U) /*!< DAC_OUT 8-bit right-aligned data holding register */ +#define OUT_DO REG32(DAC + 0x00000014U) /*!< DAC_OUT data output register */ +#define DAC_STAT REG32(DAC + 0x00000018U) /*!< DAC status register */ + +/* bits definitions */ +/* DAC_CTL */ +#define DAC_CTL_DEN BIT(0) /*!< DAC_OUT enable/disable bit */ +#define DAC_CTL_DBOFF BIT(1) /*!< DAC_OUT output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN BIT(2) /*!< DAC_OUT trigger enable/disable bit */ +#define DAC_CTL_DTSEL BITS(3,4) /*!< DAC_OUT trigger source selection enable/disable bits */ +#define DAC_CTL_DWM BITS(6,7) /*!< DAC_OUT noise wave mode */ +#define DAC_CTL_DWBW BITS(8,11) /*!< DAC_OUT noise wave bit width */ +#define DAC_CTL_DDMAEN BIT(12) /*!< DAC_OUT DMA enable/disable bit */ +#define DAC_CTL_DDUDRIE BIT(13) /*!< DAC_OUT DMA underrun interrupt enable/disable bit */ +#define DAC_CTL_DDISC BIT(14) + +/* DAC_SWT */ +#define DAC_SWT_SWTR BIT(0) /*!< DAC_OUT software trigger bit, cleared by hardware */ + +/* OUT_R12DH */ +#define OUT_R12DH_OUT_DH BITS(0,11) /*!< DAC_OUT 12-bit right-aligned data bits */ + +/* OUT_L12DH */ +#define OUT_L12DH_OUT_DH BITS(4,15) /*!< DAC_OUT 12-bit left-aligned data bits */ + +/* OUT_R8DH */ +#define OUT_R8DH_OUT_DH BITS(0,7) /*!< DAC_OUT 8-bit right-aligned data bits */ + +/* OUT_DO */ +#define OUT_DO_OUT_DO BITS(0,11) /*!< DAC_OUT 12-bit output data bits */ + +/* DAC_STAT0 */ +#define DAC_STAT_DDUDR BIT(13) /*!< DAC_OUT DMA underrun flag */ + +/* constants definitions */ +/* DAC trigger source */ +#define CTL_DTSEL(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) +#define DAC_TRIGGER_EXTRIG CTL_DTSEL(0) /*!< external trigger source */ +#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(1) /*!< software trigger */ + +/* DAC noise wave mode */ +#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ +#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ +#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ + +/* DAC noise wave bit width */ +#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ +#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ +#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ +#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ +#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ +#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ +#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ +#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ +#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ +#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ +#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ +#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ + +/* unmask LFSR bits in DAC LFSR noise mode */ +#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ +#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ +#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ +#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ +#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ +#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ +#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ +#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ +#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ +#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ +#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ +#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ + +/* DAC data alignment */ +#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< 12-bit right-aligned data */ +#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< 12-bit left-aligned data */ +#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< 8-bit right-aligned data */ + +/* triangle amplitude in DAC triangle noise mode */ +#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ +#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ +#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ +#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ +#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ +#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ +#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ +#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ +#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ +#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ +#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ +#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ + + +/* DAC interrupt */ +#define DAC_INT_DDUDRIE DAC_CTL_DDUDRIE /*!< DAC_OUT DMA underrun interrupt enable */ + +/* DAC interrupt flag */ +#define DAC_INT_FLAG_DDUDR DAC_STAT_DDUDR /*!< DAC_OUT DMA underrun interrupt flag */ + +/* DAC flag */ +#define DAC_FLAG_DDUDR DAC_STAT_DDUDR /*!< DAC_OUT DMA underrun flag */ + +/* function declarations */ +/* initialization functions */ +/* deinitialize DAC */ +void dac_deinit(void); +/* enable DAC */ +void dac_enable(void); +/* disable DAC */ +void dac_disable(void); +/* enable DAC DMA */ +void dac_dma_enable(void); +/* disable DAC DMA */ +void dac_dma_disable(void); +/* enable DAC output buffer */ +void dac_output_buffer_enable(void); +/* disable DAC output buffer */ +void dac_output_buffer_disable(void); +/* get DAC output value */ +uint16_t dac_output_value_get(void); +/* set DAC data holding register value */ +void dac_data_set(uint32_t dac_align, uint16_t data); + +/* DAC trigger configuration */ +/* enable DAC trigger */ +void dac_trigger_enable(void); +/* disable DAC trigger */ +void dac_trigger_disable(void); +/* configure DAC trigger source */ +void dac_trigger_source_config(uint32_t triggersource); +/* enable DAC software trigger */ +void dac_software_trigger_enable(void); +/* disable DAC software trigger */ +void dac_software_trigger_disable(void); + +/* DAC wave mode configuration */ +/* configure DAC wave mode */ +void dac_wave_mode_config(uint32_t wave_mode); +/* configure DAC wave bit width */ +void dac_wave_bit_width_config(uint32_t bit_width); +/* configure DAC LFSR noise mode */ +void dac_lfsr_noise_config(uint32_t unmask_bits); +/* configure DAC triangle noise mode */ +void dac_triangle_noise_config(uint32_t amplitude); + +/* interrupt and flag functions */ +/* get DAC flag */ +FlagStatus dac_flag_get(uint32_t flag); +/* clear DAC flag */ +void dac_flag_clear(uint32_t flag); +/* enable DAC interrupt */ +void dac_interrupt_enable(uint32_t interrupt); +/* disable DAC interrupt */ +void dac_interrupt_disable(uint32_t interrupt); +/* get DAC interrupt flag */ +FlagStatus dac_interrupt_flag_get(uint32_t int_flag); +/* clear DAC interrupt flag */ +void dac_interrupt_flag_clear(uint32_t int_flag); + +#endif /* GD32A50X_DAC_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_dbg.h b/gd32a50x/standard_peripheral/include/gd32a50x_dbg.h new file mode 100644 index 0000000..31e10c6 --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_dbg.h @@ -0,0 +1,120 @@ +/*! + \file gd32a50x_dbg.h + \brief definitions for the DBG + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_DBG_H +#define GD32A50X_DBG_H + +#include "gd32a50x.h" + +/* DBG definitions */ +#define DBG DBG_BASE /*!< DBG base address */ + +/* registers definitions */ +#define DBG_ID REG32(DBG + 0x00000000U) /*!< DBG_ID code register */ +#define DBG_CTL REG32(DBG + 0x00000004U) /*!< DBG control register */ + +/* bits definitions */ +/* DBG_ID */ +#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code */ + +/* DBG_CTL */ +#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ +#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ +#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ +#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< hold FWDGT counter when core is halted */ +#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< hold WWDGT counter when core is halted */ +#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ +#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ +#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus timeout when core is halted */ +#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus timeout when core is halted */ +#define DBG_CTL_TIMER7_HOLD BIT(17) /*!< hold TIMER7 counter when core is halted */ +#define DBG_CTL_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */ +#define DBG_CTL_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */ +#define DBG_CTL_MFCOM_HOLD BIT(21) /*!< hold MFCOM counter when core is halted */ +#define DBG_CTL_CAN0_HOLD BIT(22) /*!< hold CAN0 counter when core is halted */ +#define DBG_CTL_CAN1_HOLD BIT(23) /*!< hold CAN1 counter when core is halted */ +#define DBG_CTL_TIMER20_HOLD BIT(30) /*!< hold TIMER20 counter when core is halted */ +#define DBG_CTL_TIMER19_HOLD BIT(31) /*!< hold TIMER19 counter when core is halted */ + + +/* constants definitions */ +#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */ +#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ +#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */ + +/* define the peripheral debug hold bit position and its register index offset */ +#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) +#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) +#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* register index */ +#define DBG_IDX_CTL ((uint32_t)0x00000004U) + +typedef enum +{ + DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 8U), /*!< hold FWDGT counter when core is halted */ + DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 9U), /*!< hold WWDGT counter when core is halted */ + DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 10U), /*!< hold TIMER0 counter when core is halted */ + DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 11U), /*!< hold TIMER1 counter when core is halted */ + DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 15U), /*!< hold I2C0 smbus timeout when core is halted */ + DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 16U), /*!< hold I2C1 smbus timeout when core is halted */ + DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 17U), /*!< hold TIMER7 counter when core is halted */ + DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 19U), /*!< hold TIMER5 counter when core is halted */ + DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 20U), /*!< hold TIMER6 counter when core is halted */ + DBG_MFCOM_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 21U), /*!< hold MFCOM counter when core is halted */ + DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 22U), /*!< hold CAN0 counter when core is halted */ + DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 23U), /*!< hold CAN1 counter when core is halted */ + DBG_TIMER20_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 30U), /*!< hold TIMER20 counter when core is halted */ + DBG_TIMER19_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 31U), /*!< hold TIMER19 counter when core is halted */ +}dbg_periph_enum; + + +/* function declarations */ +/* deinitialize the DBG */ +void dbg_deinit(void); +/* read DBG_ID code register */ +uint32_t dbg_id_get(void); + +/* enable low power behavior when the MCU is in debug mode */ +void dbg_low_power_enable(uint32_t dbg_low_power); +/* disable low power behavior when the MCU is in debug mode */ +void dbg_low_power_disable(uint32_t dbg_low_power); + +/* enable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_enable(dbg_periph_enum dbg_periph); +/* disable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_disable(dbg_periph_enum dbg_periph); + + +#endif /* GD32A50X_DBG_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_dma.h b/gd32a50x/standard_peripheral/include/gd32a50x_dma.h new file mode 100644 index 0000000..1f141d5 --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_dma.h @@ -0,0 +1,709 @@ +/*! + \file gd32a50x_dma.h + \brief definitions for the DMA + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_DMA_H +#define GD32A50X_DMA_H + +#include "gd32a50x.h" + +/* DMAx(x=0,1) definitions */ +#define DMA0 DMA_BASE /*!< DMA0 base address */ +#define DMA1 (DMA_BASE + 0x00000400U) /*!< DMA1 base address */ +/* DMAMUX definitions */ +#define DMAMUX DMAMUX_BASE /*!< DMA base address */ + +/* DMAx(x=0,1) registers definitions */ +#define DMA_INTF(dmax) REG32((dmax) + 0x00000000U) /*!< DMA interrupt flag register */ +#define DMA_INTC(dmax) REG32((dmax) + 0x00000004U) /*!< DMA interrupt flag clear register */ +#define DMA_CH0CTL(dmax) REG32((dmax) + 0x00000008U) /*!< DMA channel 0 control register */ +#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0000000CU) /*!< DMA channel 0 counter register */ +#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x00000010U) /*!< DMA channel 0 peripheral base address register */ +#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x00000014U) /*!< DMA channel 0 memory base address register */ +#define DMA_CH1CTL(dmax) REG32((dmax) + 0x0000001CU) /*!< DMA channel 1 control register */ +#define DMA_CH1CNT(dmax) REG32((dmax) + 0x00000020U) /*!< DMA channel 1 counter register */ +#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x00000024U) /*!< DMA channel 1 peripheral base address register */ +#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x00000028U) /*!< DMA channel 1 memory base address register */ +#define DMA_CH2CTL(dmax) REG32((dmax) + 0x00000030U) /*!< DMA channel 2 control register */ +#define DMA_CH2CNT(dmax) REG32((dmax) + 0x00000034U) /*!< DMA channel 2 counter register */ +#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x00000038U) /*!< DMA channel 2 peripheral base address register */ +#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x0000003CU) /*!< DMA channel 2 memory base address register */ +#define DMA_CH3CTL(dmax) REG32((dmax) + 0x00000044U) /*!< DMA channel 3 control register */ +#define DMA_CH3CNT(dmax) REG32((dmax) + 0x00000048U) /*!< DMA channel 3 counter register */ +#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x0000004CU) /*!< DMA channel 3 peripheral base address register */ +#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x00000050U) /*!< DMA channel 3 memory base address register */ +#define DMA_CH4CTL(dmax) REG32((dmax) + 0x00000058U) /*!< DMA channel 4 control register */ +#define DMA_CH4CNT(dmax) REG32((dmax) + 0x0000005CU) /*!< DMA channel 4 counter register */ +#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x00000060U) /*!< DMA channel 4 peripheral base address register */ +#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x00000064U) /*!< DMA channel 4 memory base address register */ + +/* DMAx(x=0) registers definitions */ +#define DMA_CH5CTL(dmax) REG32((dmax) + 0x0000006CU) /*!< DMA channel 5 control register */ +#define DMA_CH5CNT(dmax) REG32((dmax) + 0x00000070U) /*!< DMA channel 5 counter register */ +#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x00000074U) /*!< DMA channel 5 peripheral base address register */ +#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x00000078U) /*!< DMA channel 5 memory base address register */ +#define DMA_CH6CTL(dmax) REG32((dmax) + 0x00000080U) /*!< DMA channel 6 control register */ +#define DMA_CH6CNT(dmax) REG32((dmax) + 0x00000084U) /*!< DMA channel 6 counter register */ +#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x00000088U) /*!< DMA channel 6 peripheral base address register */ +#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x0000008CU) /*!< DMA channel 6 memory base address register */ + +#define DMAMUX_RM_CH0CFG REG32(DMAMUX + 0x00000000U) /*!< DMAMUX request multiplexer channel 0 configuration register */ +#define DMAMUX_RM_CH1CFG REG32(DMAMUX + 0x00000004U) /*!< DMAMUX request multiplexer channel 1 configuration register */ +#define DMAMUX_RM_CH2CFG REG32(DMAMUX + 0x00000008U) /*!< DMAMUX request multiplexer channel 2 configuration register */ +#define DMAMUX_RM_CH3CFG REG32(DMAMUX + 0x0000000CU) /*!< DMAMUX request multiplexer channel 3 configuration register */ +#define DMAMUX_RM_CH4CFG REG32(DMAMUX + 0x00000010U) /*!< DMAMUX request multiplexer channel 4 configuration register */ +#define DMAMUX_RM_CH5CFG REG32(DMAMUX + 0x00000014U) /*!< DMAMUX request multiplexer channel 5 configuration register */ +#define DMAMUX_RM_CH6CFG REG32(DMAMUX + 0x00000018U) /*!< DMAMUX request multiplexer channel 6 configuration register */ +#define DMAMUX_RM_CH7CFG REG32(DMAMUX + 0x0000001CU) /*!< DMAMUX request multiplexer channel 7 configuration register */ +#define DMAMUX_RM_CH8CFG REG32(DMAMUX + 0x00000020U) /*!< DMAMUX request multiplexer channel 8 configuration register */ +#define DMAMUX_RM_CH9CFG REG32(DMAMUX + 0x00000024U) /*!< DMAMUX request multiplexer channel 9 configuration register */ +#define DMAMUX_RM_CH10CFG REG32(DMAMUX + 0x00000028U) /*!< DMAMUX request multiplexer channel 10 configuration register */ +#define DMAMUX_RM_CH11CFG REG32(DMAMUX + 0x0000002CU) /*!< DMAMUX request multiplexer channel 11 configuration register */ + +#define DMAMUX_RM_INTF REG32(DMAMUX + 0x00000080U) /*!< DMAMUX request multiplexer channel interrupt flag register */ +#define DMAMUX_RM_INTC REG32(DMAMUX + 0x00000084U) /*!< DMAMUX request multiplexer channel interrupt flag clear register */ +#define DMAMUX_RG_CH0CFG REG32(DMAMUX + 0x00000100U) /*!< DMAMUX generator channel 0 configuration register */ +#define DMAMUX_RG_CH1CFG REG32(DMAMUX + 0x00000104U) /*!< DMAMUX generator channel 1 configuration register */ +#define DMAMUX_RG_CH2CFG REG32(DMAMUX + 0x00000108U) /*!< DMAMUX generator channel 2 configuration register */ +#define DMAMUX_RG_CH3CFG REG32(DMAMUX + 0x0000010CU) /*!< DMAMUX generator channel 3 configuration register */ +#define DMAMUX_RG_INTF REG32(DMAMUX + 0x00000140U) /*!< DMAMUX generator channel interrupt flag register */ +#define DMAMUX_RG_INTC REG32(DMAMUX + 0x00000144U) /*!< DMAMUX rgenerator channel interrupt flag clear register */ + +/* bits definitions */ +/* DMA_INTF */ +#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ +#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ +#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ +#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ + +/* DMA_INTC */ +#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ +#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ +#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ +#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ + +/* DMA_CHxCTL,x=0..6 */ +#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */ +#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel x transfer complete interrupt */ +#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel x transfer half complete interrupt */ +#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel x error interrupt */ +#define DMA_CHXCTL_DIR BIT(4) /*!< direction of the data transfer on the channel */ +#define DMA_CHXCTL_CMEN BIT(5) /*!< circulation mode */ +#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ +#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ +#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data size of peripheral */ +#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data size of memory */ +#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level of channelx */ +#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ + +/* DMA_CHxCNT,x=0..6 */ +#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ + +/* DMA_CHxPADDR,x=0..6 */ +#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ + +/* DMA_CHxMADDR,x=0..6 */ +#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ + +/* DMAMUX_RM_CHxCFG,x=0..6 */ +#define DMAMUX_RM_CHXCFG_MUXID BITS(0,6) /*!< multiplexer input identification */ +#define DMAMUX_RM_CHXCFG_SOIE BIT(8) /*!< synchronization overrun interrupt enable */ +#define DMAMUX_RM_CHXCFG_EVGEN BIT(9) /*!< event generation enable */ +#define DMAMUX_RM_CHXCFG_SYNCEN BIT(16) /*!< synchronization enable */ +#define DMAMUX_RM_CHXCFG_SYNCP BITS(17,18) /*!< synchronization input polarity */ +#define DMAMUX_RM_CHXCFG_NBR BITS(19,23) /*!< number of DMA requests to forward */ +#define DMAMUX_RM_CHXCFG_SYNCID BITS(24,28) /*!< synchronization input identification */ + +/* DMAMUX_RM_INTF */ +#define DMAMUX_RM_INTF_SOIF0 BIT(0) /*!< synchronization overrun event flag of request multiplexer channel 0 */ +#define DMAMUX_RM_INTF_SOIF1 BIT(1) /*!< synchronization overrun event flag of request multiplexer channel 1 */ +#define DMAMUX_RM_INTF_SOIF2 BIT(2) /*!< synchronization overrun event flag of request multiplexer channel 2 */ +#define DMAMUX_RM_INTF_SOIF3 BIT(3) /*!< synchronization overrun event flag of request multiplexer channel 3 */ +#define DMAMUX_RM_INTF_SOIF4 BIT(4) /*!< synchronization overrun event flag of request multiplexer channel 4 */ +#define DMAMUX_RM_INTF_SOIF5 BIT(5) /*!< synchronization overrun event flag of request multiplexer channel 5 */ +#define DMAMUX_RM_INTF_SOIF6 BIT(6) /*!< synchronization overrun event flag of request multiplexer channel 6 */ +#define DMAMUX_RM_INTF_SOIF7 BIT(7) /*!< synchronization overrun event flag of request multiplexer channel 7 */ +#define DMAMUX_RM_INTF_SOIF8 BIT(8) /*!< synchronization overrun event flag of request multiplexer channel 8 */ +#define DMAMUX_RM_INTF_SOIF9 BIT(9) /*!< synchronization overrun event flag of request multiplexer channel 9 */ +#define DMAMUX_RM_INTF_SOIF10 BIT(10) /*!< synchronization overrun event flag of request multiplexer channel 10 */ +#define DMAMUX_RM_INTF_SOIF11 BIT(11) /*!< synchronization overrun event flag of request multiplexer channel 11 */ + +/* DMAMUX_RM_INTC */ +#define DMAMUX_RM_INTF_SOIFC0 BIT(0) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 0 */ +#define DMAMUX_RM_INTF_SOIFC1 BIT(1) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 1 */ +#define DMAMUX_RM_INTF_SOIFC2 BIT(2) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 2 */ +#define DMAMUX_RM_INTF_SOIFC3 BIT(3) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 3 */ +#define DMAMUX_RM_INTF_SOIFC4 BIT(4) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 4 */ +#define DMAMUX_RM_INTF_SOIFC5 BIT(5) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 5 */ +#define DMAMUX_RM_INTF_SOIFC6 BIT(6) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 6 */ +#define DMAMUX_RM_INTF_SOIFC7 BIT(7) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 7 */ +#define DMAMUX_RM_INTF_SOIFC8 BIT(8) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 8 */ +#define DMAMUX_RM_INTF_SOIFC9 BIT(9) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 9 */ +#define DMAMUX_RM_INTF_SOIFC10 BIT(10) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 10 */ +#define DMAMUX_RM_INTF_SOIFC11 BIT(11) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 11 */ + +/* DMAMUX_RG_CHxCFG,x=0..3 */ +#define DMAMUX_RG_CHXCFG_TID BITS(0,4) /*!< trigger input identification */ +#define DMAMUX_RG_CHXCFG_TOIE BIT(8) /*!< trigger overrun interrupt enable */ +#define DMAMUX_RG_CHXCFG_RGEN BIT(16) /*!< DMA request generator channel x enable */ +#define DMAMUX_RG_CHXCFG_RGTP BITS(17,18) /*!< DMA request generator trigger polarity */ +#define DMAMUX_RG_CHXCFG_NBRG BITS(19,23) /*!< number of DMA requests to be generated */ + +/* DMAMUX_RG_INTF */ +#define DMAMUX_RG_INTF_TOIF0 BIT(0) /*!< trigger overrun event flag of request generator channel 0 */ +#define DMAMUX_RG_INTF_TOIF1 BIT(1) /*!< trigger overrun event flag of request generator channel 1 */ +#define DMAMUX_RG_INTF_TOIF2 BIT(2) /*!< trigger overrun event flag of request generator channel 2 */ +#define DMAMUX_RG_INTF_TOIF3 BIT(3) /*!< trigger overrun event flag of request generator channel 3 */ + +/* DMAMUX_RG_INTC */ +#define DMAMUX_RG_INTF_TOIFC0 BIT(0) /*!< clear bit for trigger overrun event flag of request generator channel 0 */ +#define DMAMUX_RG_INTF_TOIFC1 BIT(1) /*!< clear bit for trigger overrun event flag of request generator channel 1 */ +#define DMAMUX_RG_INTF_TOIFC2 BIT(2) /*!< clear bit for trigger overrun event flag of request generator channel 2 */ +#define DMAMUX_RG_INTF_TOIFC3 BIT(3) /*!< clear bit for trigger overrun event flag of request generator channel 3 */ + +/* constants definitions */ +/* define the DMAMUX bit position and its register index offset */ +#define DMAMUX_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6U) | (uint32_t)(bitpos)) +#define DMAMUX_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22U) | (uint32_t)((bitpos2) << 16U) \ + | (((uint32_t)(regidx) << 6U) | (uint32_t)(bitpos))) + +#define DMAMUX_REG_VAL(offset) (REG32(DMAMUX + (((uint32_t)(offset) & 0x0000FFFFU) >> 6U))) +#define DMAMUX_REG_VAL2(offset) (REG32(DMAMUX + ((uint32_t)(offset) >> 22U))) +#define DMAMUX_REG_VAL3(offset) (REG32(DMAMUX + (((uint32_t)(offset) & 0x0000FFFFU) >> 6U) + 0x4U)) + +#define DMAMUX_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define DMAMUX_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16U) + +/* register offset */ +#define DMAMUX_RM_CH0CFG_REG_OFFSET 0x00000000U /*!< DMAMUX_RM_CH0CFG register offset */ +#define DMAMUX_RM_CH1CFG_REG_OFFSET 0x00000004U /*!< DMAMUX_RM_CH1CFG register offset */ +#define DMAMUX_RM_CH2CFG_REG_OFFSET 0x00000008U /*!< DMAMUX_RM_CH2CFG register offset */ +#define DMAMUX_RM_CH3CFG_REG_OFFSET 0x0000000CU /*!< DMAMUX_RM_CH3CFG register offset */ +#define DMAMUX_RM_CH4CFG_REG_OFFSET 0x00000010U /*!< DMAMUX_RM_CH4CFG register offset */ +#define DMAMUX_RM_CH5CFG_REG_OFFSET 0x00000014U /*!< DMAMUX_RM_CH5CFG register offset */ +#define DMAMUX_RM_CH6CFG_REG_OFFSET 0x00000018U /*!< DMAMUX_RM_CH6CFG register offset */ +#define DMAMUX_RM_CH7CFG_REG_OFFSET 0x0000001CU /*!< DMAMUX_RM_CH7CFG register offset */ +#define DMAMUX_RM_CH8CFG_REG_OFFSET 0x00000020U /*!< DMAMUX_RM_CH8CFG register offset */ +#define DMAMUX_RM_CH9CFG_REG_OFFSET 0x00000024U /*!< DMAMUX_RM_CH9CFG register offset */ +#define DMAMUX_RM_CH10CFG_REG_OFFSET 0x00000028U /*!< DMAMUX_RM_CH10CFG register offset */ +#define DMAMUX_RM_CH11CFG_REG_OFFSET 0x0000002CU /*!< DMAMUX_RM_CH11CFG register offset */ + +#define DMAMUX_RG_CH0CFG_REG_OFFSET 0x00000100U /*!< DMAMUX_RG_CH0CFG register offset */ +#define DMAMUX_RG_CH1CFG_REG_OFFSET 0x00000104U /*!< DMAMUX_RG_CH1CFG register offset */ +#define DMAMUX_RG_CH2CFG_REG_OFFSET 0x00000108U /*!< DMAMUX_RG_CH2CFG register offset */ +#define DMAMUX_RG_CH3CFG_REG_OFFSET 0x0000010CU /*!< DMAMUX_RG_CH3CFG register offset */ + +#define DMAMUX_RM_INTF_REG_OFFSET 0x00000080U /*!< DMAMUX_RM_INTF register offset */ +#define DMAMUX_RM_INTC_REG_OFFSET 0x00000084U /*!< DMAMUX_RM_INTC register offset */ +#define DMAMUX_RG_INTF_REG_OFFSET 0x00000140U /*!< DMAMUX_RG_INTF register offset */ +#define DMAMUX_RG_INTC_REG_OFFSET 0x00000144U /*!< DMAMUX_RG_INTC register offset */ + +/* DMA channel select */ +typedef enum +{ + DMA_CH0 = 0U, /*!< DMA Channel 0 */ + DMA_CH1, /*!< DMA Channel 1 */ + DMA_CH2, /*!< DMA Channel 2 */ + DMA_CH3, /*!< DMA Channel 3 */ + DMA_CH4, /*!< DMA Channel 4 */ + DMA_CH5, /*!< DMA Channel 5 */ + DMA_CH6, /*!< DMA Channel 6 */ +} dma_channel_enum; + +/* DMAMUX request line multiplexer channel */ +typedef enum +{ + DMAMUX_MULTIPLEXER_CH0 = 0, /*!< DMAMUX request multiplexer Channel0 */ + DMAMUX_MULTIPLEXER_CH1, /*!< DMAMUX request multiplexer Channel1 */ + DMAMUX_MULTIPLEXER_CH2, /*!< DMAMUX request multiplexer Channel2 */ + DMAMUX_MULTIPLEXER_CH3, /*!< DMAMUX request multiplexer Channel3 */ + DMAMUX_MULTIPLEXER_CH4, /*!< DMAMUX request multiplexer Channel4 */ + DMAMUX_MULTIPLEXER_CH5, /*!< DMAMUX request multiplexer Channel5 */ + DMAMUX_MULTIPLEXER_CH6, /*!< DMAMUX request multiplexer Channel6 */ + DMAMUX_MULTIPLEXER_CH7, /*!< DMAMUX request multiplexer Channel7 */ + DMAMUX_MULTIPLEXER_CH8, /*!< DMAMUX request multiplexer Channel8 */ + DMAMUX_MULTIPLEXER_CH9, /*!< DMAMUX request multiplexer Channel9 */ + DMAMUX_MULTIPLEXER_CH10, /*!< DMAMUX request multiplexer Channel10 */ + DMAMUX_MULTIPLEXER_CH11, /*!< DMAMUX request multiplexer Channel11 */ +} dmamux_multiplexer_channel_enum; + +/* DMAMUX request generator channel */ +typedef enum { + DMAMUX_GENCH0 = 0U, /*!< DMAMUX request generator Channel0 */ + DMAMUX_GENCH1, /*!< DMAMUX request generator Channel1 */ + DMAMUX_GENCH2, /*!< DMAMUX request generator Channel2 */ + DMAMUX_GENCH3, /*!< DMAMUX request generator Channel3 */ +} dmamux_generator_channel_enum; + +/* DMAMUX interrupt enable or disable */ +typedef enum { + /* interrupts in CHxCFG register */ + DMAMUX_INT_MUXCH0_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH0CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 0 synchronization overrun interrupt */ + DMAMUX_INT_MUXCH1_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH1CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 1 synchronization overrun interrupt */ + DMAMUX_INT_MUXCH2_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH2CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 2 synchronization overrun interrupt */ + DMAMUX_INT_MUXCH3_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH3CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 3 synchronization overrun interrupt */ + DMAMUX_INT_MUXCH4_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH4CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 4 synchronization overrun interrupt */ + DMAMUX_INT_MUXCH5_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH5CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 5 synchronization overrun interrupt */ + DMAMUX_INT_MUXCH6_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH6CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun interrupt */ + DMAMUX_INT_MUXCH7_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH7CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun interrupt */ + DMAMUX_INT_MUXCH8_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH8CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun interrupt */ + DMAMUX_INT_MUXCH9_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH9CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun interrupt */ + DMAMUX_INT_MUXCH10_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH10CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun interrupt */ + DMAMUX_INT_MUXCH11_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH11CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun interrupt */ + DMAMUX_INT_GENCH0_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_CH0CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 0 trigger overrun interrupt */ + DMAMUX_INT_GENCH1_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_CH1CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 1 trigger overrun interrupt */ + DMAMUX_INT_GENCH2_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_CH2CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 2 trigger overrun interrupt */ + DMAMUX_INT_GENCH3_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_CH3CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 3 trigger overrun interrupt */ +} dmamux_interrupt_enum; + + +/* DMAMUX flags */ +typedef enum { + /* flags in INTF register */ + DMAMUX_FLAG_MUXCH0_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 0U), /*!< DMAMUX request multiplexer channel 0 synchronization overrun flag */ + DMAMUX_FLAG_MUXCH1_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 1U), /*!< DMAMUX request multiplexer channel 1 synchronization overrun flag */ + DMAMUX_FLAG_MUXCH2_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 2U), /*!< DMAMUX request multiplexer channel 2 synchronization overrun flag */ + DMAMUX_FLAG_MUXCH3_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 3U), /*!< DMAMUX request multiplexer channel 3 synchronization overrun flag */ + DMAMUX_FLAG_MUXCH4_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 4U), /*!< DMAMUX request multiplexer channel 4 synchronization overrun flag */ + DMAMUX_FLAG_MUXCH5_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 5U), /*!< DMAMUX request multiplexer channel 5 synchronization overrun flag */ + DMAMUX_FLAG_MUXCH6_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 6U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun flag */ + DMAMUX_FLAG_MUXCH7_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 7U), /*!< DMAMUX request multiplexer channel 7 synchronization overrun flag */ + DMAMUX_FLAG_MUXCH8_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 8 synchronization overrun flag */ + DMAMUX_FLAG_MUXCH9_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 9U), /*!< DMAMUX request multiplexer channel 9 synchronization overrun flag */ + DMAMUX_FLAG_MUXCH10_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 10U), /*!< DMAMUX request multiplexer channel 10 synchronization overrun flag */ + DMAMUX_FLAG_MUXCH11_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 11U), /*!< DMAMUX request multiplexer channel 11 synchronization overrun flag */ + DMAMUX_FLAG_GENCH0_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_INTF_REG_OFFSET, 0U), /*!< DMAMUX request generator channel 0 trigger overrun flag */ + DMAMUX_FLAG_GENCH1_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_INTF_REG_OFFSET, 1U), /*!< DMAMUX request generator channel 1 trigger overrun flag */ + DMAMUX_FLAG_GENCH2_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_INTF_REG_OFFSET, 2U), /*!< DMAMUX request generator channel 2 trigger overrun flag */ + DMAMUX_FLAG_GENCH3_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_INTF_REG_OFFSET, 3U), /*!< DMAMUX request generator channel 3 trigger overrun flag */ +} dmamux_flag_enum; + +/* DMAMUX interrupt flags */ +typedef enum { + /* interrupt flags in INTF register */ + DMAMUX_INT_FLAG_MUXCH0_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 0U, DMAMUX_RM_CH0CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 0 synchronization overrun interrupt flag */ + DMAMUX_INT_FLAG_MUXCH1_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 1U, DMAMUX_RM_CH1CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 1 synchronization overrun interrupt flag */ + DMAMUX_INT_FLAG_MUXCH2_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 2U, DMAMUX_RM_CH2CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 2 synchronization overrun interrupt flag */ + DMAMUX_INT_FLAG_MUXCH3_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 3U, DMAMUX_RM_CH3CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 3 synchronization overrun interrupt flag */ + DMAMUX_INT_FLAG_MUXCH4_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 4U, DMAMUX_RM_CH4CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 4 synchronization overrun interrupt flag */ + DMAMUX_INT_FLAG_MUXCH5_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 5U, DMAMUX_RM_CH5CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 5 synchronization overrun interrupt flag */ + DMAMUX_INT_FLAG_MUXCH6_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 6U, DMAMUX_RM_CH6CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun interrupt flag */ + DMAMUX_INT_FLAG_MUXCH7_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 7U, DMAMUX_RM_CH7CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 7 synchronization overrun interrupt flag */ + DMAMUX_INT_FLAG_MUXCH8_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 8U, DMAMUX_RM_CH8CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 8 synchronization overrun interrupt flag */ + DMAMUX_INT_FLAG_MUXCH9_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 9U, DMAMUX_RM_CH9CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 9 synchronization overrun interrupt flag */ + DMAMUX_INT_FLAG_MUXCH10_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 10U, DMAMUX_RM_CH10CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 10 synchronization overrun interrupt flag */ + DMAMUX_INT_FLAG_MUXCH11_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 11U, DMAMUX_RM_CH11CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 11 synchronization overrun interrupt flag */ + DMAMUX_INT_FLAG_GENCH0_TO = DMAMUX_REGIDX_BIT2(DMAMUX_RG_INTF_REG_OFFSET, 0U, DMAMUX_RG_CH0CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 0 trigger overrun interrupt flag */ + DMAMUX_INT_FLAG_GENCH1_TO = DMAMUX_REGIDX_BIT2(DMAMUX_RG_INTF_REG_OFFSET, 1U, DMAMUX_RG_CH1CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 1 trigger overrun interrupt flag */ + DMAMUX_INT_FLAG_GENCH2_TO = DMAMUX_REGIDX_BIT2(DMAMUX_RG_INTF_REG_OFFSET, 2U, DMAMUX_RG_CH2CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 2 trigger overrun interrupt flag */ + DMAMUX_INT_FLAG_GENCH3_TO = DMAMUX_REGIDX_BIT2(DMAMUX_RG_INTF_REG_OFFSET, 3U, DMAMUX_RG_CH3CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 3 trigger overrun interrupt flag */ +} dmamux_interrupt_flag_enum; + +/* DMA initialization structure */ +typedef struct +{ + uint32_t periph_addr; /*!< peripheral base address */ + uint32_t periph_width; /*!< transfer data size of peripheral */ + uint32_t memory_addr; /*!< memory base address */ + uint32_t memory_width; /*!< transfer data size of memory */ + uint32_t number; /*!< channel transfer number */ + uint32_t priority; /*!< channel priority level */ + uint8_t periph_inc; /*!< peripheral increasing mode */ + uint8_t memory_inc; /*!< memory increasing mode */ + uint8_t direction; /*!< channel data transfer direction */ + uint32_t request; /*!< channel input identification */ +} dma_parameter_struct; + +/* DMAMUX request multiplexer synchronization configuration structure */ +typedef struct +{ + uint32_t sync_id; /*!< synchronization input identification */ + uint32_t sync_polarity; /*!< synchronization input polarity */ + uint32_t request_number; /*!< number of DMA requests to forward */ +} dmamux_sync_parameter_struct; + +/* DMAMUX request generator trigger configuration structure */ +typedef struct +{ + uint32_t trigger_id; /*!< trigger input identification */ + uint32_t trigger_polarity; /*!< DMA request generator trigger polarity */ + uint32_t request_number; /*!< number of DMA requests to be generated */ +} dmamux_gen_parameter_struct; + +/* DMA reset value */ +#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ +#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ +#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ +#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ +#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ + DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< the reset value of DMA channel DMA_INTF register */ + +#define DMA_FLAG_ADD(flag, shift) ((uint32_t)flag << ((uint32_t)(shift) * 4U)) /*!< DMA channel flag shift */ + +/* DMA channel shift bit */ +#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x00000008U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ +#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0000000CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ +#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x00000010U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ +#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x00000014U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ + +/* DMAMUX_RM_CHxCFG base address */ +#define DMAMUX_RM_CHXCFG_BASE (DMAMUX) /*!< the base address of DMAMUX channel CHxCFG register */ + +/* DMAMUX request multiplexer channel shift bit */ +#define DMAMUX_RM_CHXCFG(channel) REG32(DMAMUX_RM_CHXCFG_BASE + 0x4U * (uint32_t)(channel)) /*!< the address of DMAMUX channel CHxCFG register */ + +/* DMAMUX_RG_CHxCFG base address */ +#define DMAMUX_RG_CHXCFG_BASE (DMAMUX + 0x00000100U) /*!< the base address of DMAMUX channel request generator CHxCFG register */ + +/* DMAMUX request generator channel shift bit */ +#define DMAMUX_RG_CHXCFG(channel) REG32(DMAMUX_RG_CHXCFG_BASE + 0x4U * (uint32_t)(channel)) /*!< the address of DMAMUX channel request generator CHxCFG register */ + +/* DMA interrupt flag bits */ +#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ + +/* DMA flag bits */ +#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ +#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ +#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ + +/* DMA interrupt enable bits */ +#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ + +/* DMA transfer direction */ +#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x00U) /*!< read from peripheral and write to memory */ +#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x01U) /*!< read from memory and write to peripheral */ + +/* DMA peripheral increasing mode */ +#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00U) /*!< next address of peripheral is fixed address mode */ +#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x01U) /*!< next address of peripheral is increasing address mode */ + +/* DMA memory increasing mode */ +#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00U) /*!< next address of memory is fixed address mode */ +#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x01U) /*!< next address of memory is increasing address mode */ + +/* DMA transfer data size of peripheral */ +#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8U)) /*!< transfer data size of peripheral */ +#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ +#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ +#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ + +/* DMA transfer data size of memory */ +#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10U)) /*!< transfer data size of memory */ +#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ +#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ +#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ + +/* DMA channel priority level */ +#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12U)) /*!< DMA channel priority level */ +#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ +#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ +#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ +#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */ + +/* DMA transfer counter */ +#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */ + +/* DMAMUX request multiplexer channel input identification */ +#define RM_CHXCFG_MUXID(regval) (BITS(0,5) & ((regval) << 0U)) /*!< multiplexer input identification */ +#define DMA_REQUEST_M2M RM_CHXCFG_MUXID(0U) /*!< memory to memory transfer */ +#define DMA_REQUEST_GENERATOR0 RM_CHXCFG_MUXID(1U) /*!< DMAMUX request generator 0 */ +#define DMA_REQUEST_GENERATOR1 RM_CHXCFG_MUXID(2U) /*!< DMAMUX request generator 1 */ +#define DMA_REQUEST_GENERATOR2 RM_CHXCFG_MUXID(3U) /*!< DMAMUX request generator 2 */ +#define DMA_REQUEST_GENERATOR3 RM_CHXCFG_MUXID(4U) /*!< DMAMUX request generator 3 */ +#define DMA_REQUEST_ADC RM_CHXCFG_MUXID(5U) /*!< DMAMUX ADC request */ +#define DMA_REQUEST_DAC_CH0 RM_CHXCFG_MUXID(6U) /*!< DMAMUX DAC CH0 request */ +#define DMA_REQUEST_I2C1_RX RM_CHXCFG_MUXID(8U) /*!< DMAMUX I2C1 RX request */ +#define DMA_REQUEST_I2C1_TX RM_CHXCFG_MUXID(9U) /*!< DMAMUX I2C1 TX request */ +#define DMA_REQUEST_I2C0_RX RM_CHXCFG_MUXID(10U) /*!< DMAMUX I2C0 RX request */ +#define DMA_REQUEST_I2C0_TX RM_CHXCFG_MUXID(11U) /*!< DMAMUX I2C0 TX request */ +#define DMA_REQUESR_SSTAT0 RM_CHXCFG_MUXID(12U) /*!< DMAMUX SSTAT0 request */ +#define DMA_REQUESR_SSTAT1 RM_CHXCFG_MUXID(13U) /*!< DMAMUX SSTAT1 request */ +#define DMA_REQUESR_SSTAT2 RM_CHXCFG_MUXID(14U) /*!< DMAMUX SSTAT2 request */ +#define DMA_REQUESR_SSTAT3 RM_CHXCFG_MUXID(15U) /*!< DMAMUX SSTAT3 request */ +#define DMA_REQUEST_SPI0_RX RM_CHXCFG_MUXID(16U) /*!< DMAMUX SPI0 RX request */ +#define DMA_REQUEST_SPI0_TX RM_CHXCFG_MUXID(17U) /*!< DMAMUX SPI0 TX request */ +#define DMA_REQUEST_SPI1_RX RM_CHXCFG_MUXID(18U) /*!< DMAMUX SPI1 RX request */ +#define DMA_REQUEST_SPI1_TX RM_CHXCFG_MUXID(19U) /*!< DMAMUX SPI1 TX request */ +#define DMA_REQUEST_TIMER0_CH0 RM_CHXCFG_MUXID(20U) /*!< DMAMUX TIMER0 CH0 request */ +#define DMA_REQUEST_TIMER0_CH1 RM_CHXCFG_MUXID(21U) /*!< DMAMUX TIMER0 CH1 request */ +#define DMA_REQUEST_TIMER0_CH2 RM_CHXCFG_MUXID(22U) /*!< DMAMUX TIMER0 CH2 request */ +#define DMA_REQUEST_TIMER0_CH3 RM_CHXCFG_MUXID(23U) /*!< DMAMUX TIMER0 CH3 request */ +#define DMA_REQUEST_TIMER0_TI RM_CHXCFG_MUXID(24U) /*!< DMAMUX TIMER0 TI request */ +#define DMA_REQUEST_TIMER0_UP RM_CHXCFG_MUXID(25U) /*!< DMAMUX TIMER0 UP request */ +#define DMA_REQUEST_TIMER0_CO RM_CHXCFG_MUXID(26U) /*!< DMAMUX TIMER0 CO request */ +#define DMA_REQUEST_TIMER0_MCH0 RM_CHXCFG_MUXID(27U) /*!< DMAMUX TIMER0 MCH0 request */ +#define DMA_REQUEST_TIMER0_MCH1 RM_CHXCFG_MUXID(28U) /*!< DMAMUX TIMER0 MCH1 request */ +#define DMA_REQUEST_TIMER0_MCH2 RM_CHXCFG_MUXID(29U) /*!< DMAMUX TIMER0 MCH2 request */ +#define DMA_REQUEST_TIMER0_MCH3 RM_CHXCFG_MUXID(30U) /*!< DMAMUX TIMER0 MCH3 request */ +#define DMA_REQUEST_TIMER1_CH0 RM_CHXCFG_MUXID(31U) /*!< DMAMUX TIMER1 CH0 request */ +#define DMA_REQUEST_TIMER1_CH1 RM_CHXCFG_MUXID(32U) /*!< DMAMUX TIMER1 CH1 request */ +#define DMA_REQUEST_TIMER1_CH2 RM_CHXCFG_MUXID(33U) /*!< DMAMUX TIMER1 CH2 request */ +#define DMA_REQUEST_TIMER1_CH3 RM_CHXCFG_MUXID(34U) /*!< DMAMUX TIMER1 CH3 request */ +#define DMA_REQUEST_TIMER1_TI RM_CHXCFG_MUXID(35U) /*!< DMAMUX TIMER1 TI request */ +#define DMA_REQUEST_TIMER1_UP RM_CHXCFG_MUXID(36U) /*!< DMAMUX TIMER1 UP request */ +#define DMA_REQUEST_TIMER7_CH0 RM_CHXCFG_MUXID(37U) /*!< DMAMUX TIMER7 CH0 request */ +#define DMA_REQUEST_TIMER7_CH1 RM_CHXCFG_MUXID(38U) /*!< DMAMUX TIMER7 CH1 request */ +#define DMA_REQUEST_TIMER7_CH2 RM_CHXCFG_MUXID(39U) /*!< DMAMUX TIMER7 CH2 request */ +#define DMA_REQUEST_TIMER7_CH3 RM_CHXCFG_MUXID(40U) /*!< DMAMUX TIMER7 CH3 request */ +#define DMA_REQUEST_TIMER7_TI RM_CHXCFG_MUXID(41U) /*!< DMAMUX TIMER7 TI request */ +#define DMA_REQUEST_TIMER7_UP RM_CHXCFG_MUXID(42U) /*!< DMAMUX TIMER7 UP request */ +#define DMA_REQUEST_TIMER7_CO RM_CHXCFG_MUXID(43U) /*!< DMAMUX TIMER7 CO request */ +#define DMA_REQUEST_TIMER7_MCH0 RM_CHXCFG_MUXID(44U) /*!< DMAMUX TIMER7 MCH0 request */ +#define DMA_REQUEST_TIMER7_MCH1 RM_CHXCFG_MUXID(45U) /*!< DMAMUX TIMER7 MCH1 request */ +#define DMA_REQUEST_TIMER7_MCH2 RM_CHXCFG_MUXID(46U) /*!< DMAMUX TIMER7 MCH2 request */ +#define DMA_REQUEST_TIMER7_MCH3 RM_CHXCFG_MUXID(47U) /*!< DMAMUX TIMER7 MCH3 request */ +#define DMA_REQUEST_CAN1 RM_CHXCFG_MUXID(48U) /*!< DMAMUX CAN1 request */ +#define DMA_REQUEST_CAN0 RM_CHXCFG_MUXID(49U) /*!< DMAMUX CAN0 request */ +#define DMA_REQUEST_USART0_RX RM_CHXCFG_MUXID(50U) /*!< DMAMUX USART0 RX request */ +#define DMA_REQUEST_USART0_TX RM_CHXCFG_MUXID(51U) /*!< DMAMUX USART0 TX request */ +#define DMA_REQUEST_USART1_RX RM_CHXCFG_MUXID(52U) /*!< DMAMUX USART1 RX request */ +#define DMA_REQUEST_USART1_TX RM_CHXCFG_MUXID(53U) /*!< DMAMUX USART1 TX request */ +#define DMA_REQUEST_USART2_RX RM_CHXCFG_MUXID(54U) /*!< DMAMUX USART2 RX request */ +#define DMA_REQUEST_USART2_TX RM_CHXCFG_MUXID(55U) /*!< DMAMUX USART2 TX request */ +#define DMA_REQUEST_TIMER5_UP RM_CHXCFG_MUXID(56U) /*!< DMAMUX TIMER5 UP request */ +#define DMA_REQUEST_TIMER6_UP RM_CHXCFG_MUXID(57U) /*!< DMAMUX TIMER6 UP request */ +#define DMA_REQUEST_TIMER19_CH0 RM_CHXCFG_MUXID(58U) /*!< DMAMUX TIMER19 CH0 request */ +#define DMA_REQUEST_TIMER19_CH1 RM_CHXCFG_MUXID(59U) /*!< DMAMUX TIMER19 CH1 request */ +#define DMA_REQUEST_TIMER19_CH2 RM_CHXCFG_MUXID(60U) /*!< DMAMUX TIMER19 CH2 request */ +#define DMA_REQUEST_TIMER19_CH3 RM_CHXCFG_MUXID(61U) /*!< DMAMUX TIMER19 CH3 request */ +#define DMA_REQUEST_TIMER19_TI RM_CHXCFG_MUXID(62U) /*!< DMAMUX TIMER19 TI request */ +#define DMA_REQUEST_TIMER19_UP RM_CHXCFG_MUXID(63U) /*!< DMAMUX TIMER19 UP request */ +#define DMA_REQUEST_TIMER19_CO RM_CHXCFG_MUXID(64U) /*!< DMAMUX TIMER19 CO request */ +#define DMA_REQUEST_TIMER19_MCH0 RM_CHXCFG_MUXID(65U) /*!< DMAMUX TIMER19 MCH0 request */ +#define DMA_REQUEST_TIMER19_MCH1 RM_CHXCFG_MUXID(66U) /*!< DMAMUX TIMER19 MCH1 request */ +#define DMA_REQUEST_TIMER19_MCH2 RM_CHXCFG_MUXID(67U) /*!< DMAMUX TIMER19 MCH2 request */ +#define DMA_REQUEST_TIMER19_MCH3 RM_CHXCFG_MUXID(68U) /*!< DMAMUX TIMER19 MCH3 request */ +#define DMA_REQUEST_TIMER20_CH0 RM_CHXCFG_MUXID(69U) /*!< DMAMUX TIMER20 CH0 request */ +#define DMA_REQUEST_TIMER20_CH1 RM_CHXCFG_MUXID(70U) /*!< DMAMUX TIMER20 CH1 request */ +#define DMA_REQUEST_TIMER20_CH2 RM_CHXCFG_MUXID(71U) /*!< DMAMUX TIMER20 CH2 request */ +#define DMA_REQUEST_TIMER20_CH3 RM_CHXCFG_MUXID(72U) /*!< DMAMUX TIMER20 CH3 request */ +#define DMA_REQUEST_TIMER20_TI RM_CHXCFG_MUXID(73U) /*!< DMAMUX TIMER20 TI request */ +#define DMA_REQUEST_TIMER20_UP RM_CHXCFG_MUXID(74U) /*!< DMAMUX TIMER20 UP request */ +#define DMA_REQUEST_TIMER20_CO RM_CHXCFG_MUXID(75U) /*!< DMAMUX TIMER20 CO request */ +#define DMA_REQUEST_TIMER20_MCH0 RM_CHXCFG_MUXID(76U) /*!< DMAMUX TIMER20 MCH0 request */ +#define DMA_REQUEST_TIMER20_MCH1 RM_CHXCFG_MUXID(77U) /*!< DMAMUX TIMER20 MCH1 request */ +#define DMA_REQUEST_TIMER20_MCH2 RM_CHXCFG_MUXID(78U) /*!< DMAMUX TIMER20 MCH2 request */ +#define DMA_REQUEST_TIMER20_MCH3 RM_CHXCFG_MUXID(79U) /*!< DMAMUX TIMER20 MCH3 request */ + +/* DMAMUX request generator trigger input identification */ +#define RG_CHXCFG_TID(regval) (BITS(0,4) & ((regval) << 0U)) /*!< trigger input identification */ +#define DMAMUX_TRIGGER_EXTI0 RG_CHXCFG_TID(0U) /*!< trigger input is EXTI0 */ +#define DMAMUX_TRIGGER_EXTI1 RG_CHXCFG_TID(1U) /*!< trigger input is EXTI1 */ +#define DMAMUX_TRIGGER_EXTI2 RG_CHXCFG_TID(2U) /*!< trigger input is EXTI2 */ +#define DMAMUX_TRIGGER_EXTI3 RG_CHXCFG_TID(3U) /*!< trigger input is EXTI3 */ +#define DMAMUX_TRIGGER_EXTI4 RG_CHXCFG_TID(4U) /*!< trigger input is EXTI4 */ +#define DMAMUX_TRIGGER_EXTI5 RG_CHXCFG_TID(5U) /*!< trigger input is EXTI5 */ +#define DMAMUX_TRIGGER_EXTI6 RG_CHXCFG_TID(6U) /*!< trigger input is EXTI6 */ +#define DMAMUX_TRIGGER_EXTI7 RG_CHXCFG_TID(7U) /*!< trigger input is EXTI7 */ +#define DMAMUX_TRIGGER_EXTI8 RG_CHXCFG_TID(8U) /*!< trigger input is EXTI8 */ +#define DMAMUX_TRIGGER_EXTI9 RG_CHXCFG_TID(9U) /*!< trigger input is EXTI9 */ +#define DMAMUX_TRIGGER_EXTI10 RG_CHXCFG_TID(10U) /*!< trigger input is EXTI10 */ +#define DMAMUX_TRIGGER_EXTI11 RG_CHXCFG_TID(11U) /*!< trigger input is EXTI11 */ +#define DMAMUX_TRIGGER_EXTI12 RG_CHXCFG_TID(12U) /*!< trigger input is EXTI12 */ +#define DMAMUX_TRIGGER_EXTI13 RG_CHXCFG_TID(13U) /*!< trigger input is EXTI13 */ +#define DMAMUX_TRIGGER_EXTI14 RG_CHXCFG_TID(14U) /*!< trigger input is EXTI14 */ +#define DMAMUX_TRIGGER_EXTI15 RG_CHXCFG_TID(15U) /*!< trigger input is EXTI15 */ +#define DMAMUX_TRIGGER_EVTX_OUT0 RG_CHXCFG_TID(16U) /*!< trigger input is Evtx_out0 */ +#define DMAMUX_TRIGGER_EVTX_OUT1 RG_CHXCFG_TID(17U) /*!< trigger input is Evtx_out1 */ +#define DMAMUX_TRIGGER_EVTX_OUT2 RG_CHXCFG_TID(18U) /*!< trigger input is Evtx_out2 */ +#define DMAMUX_TRIGGER_EVTX_OUT3 RG_CHXCFG_TID(19U) /*!< trigger input is Evtx_out3 */ +#define DMAMUX_TRIGGER_TIMER20_CH0_O RG_CHXCFG_TID(22U) /*!< trigger input is TIMER20_CH0_O */ + +/* DMAMUX request generator trigger polarity */ +#define RM_CHXCFG_RGTP(regval) (BITS(17,18) & ((regval) << 17U)) /*!< DMA request generator trigger polarity */ +#define DMAMUX_GEN_NO_EVENT RM_CHXCFG_RGTP(0U) /*!< no event detection */ +#define DMAMUX_GEN_RISING RM_CHXCFG_RGTP(1U) /*!< rising edge */ +#define DMAMUX_GEN_FALLING RM_CHXCFG_RGTP(2U) /*!< falling edge */ +#define DMAMUX_GEN_RISING_FALLING RM_CHXCFG_RGTP(3U) /*!< rising and falling edges */ + +/* number of DMA requests to be generated */ +#define RG_CHXCFG_NBRG(regval) (BITS(19,23) & ((regval) << 19U)) /*!< number of DMA requests to be generated */ + +/* DMAMUX request multiplexer channel synchronization input identification */ +#define RM_CHXCFG_SYNCID(regval) (BITS(24,28) & ((regval) << 24U)) /*!< synchronization input identification */ +#define DMAMUX_SYNC_EXTI0 RM_CHXCFG_SYNCID(0U) /*!< synchronization input is EXTI0 */ +#define DMAMUX_SYNC_EXTI1 RM_CHXCFG_SYNCID(1U) /*!< synchronization input is EXTI1 */ +#define DMAMUX_SYNC_EXTI2 RM_CHXCFG_SYNCID(2U) /*!< synchronization input is EXTI2 */ +#define DMAMUX_SYNC_EXTI3 RM_CHXCFG_SYNCID(3U) /*!< synchronization input is EXTI3 */ +#define DMAMUX_SYNC_EXTI4 RM_CHXCFG_SYNCID(4U) /*!< synchronization input is EXTI4 */ +#define DMAMUX_SYNC_EXTI5 RM_CHXCFG_SYNCID(5U) /*!< synchronization input is EXTI5 */ +#define DMAMUX_SYNC_EXTI6 RM_CHXCFG_SYNCID(6U) /*!< synchronization input is EXTI6 */ +#define DMAMUX_SYNC_EXTI7 RM_CHXCFG_SYNCID(7U) /*!< synchronization input is EXTI7 */ +#define DMAMUX_SYNC_EXTI8 RM_CHXCFG_SYNCID(8U) /*!< synchronization input is EXTI8 */ +#define DMAMUX_SYNC_EXTI9 RM_CHXCFG_SYNCID(9U) /*!< synchronization input is EXTI9 */ +#define DMAMUX_SYNC_EXTI10 RM_CHXCFG_SYNCID(10U) /*!< synchronization input is EXTI10 */ +#define DMAMUX_SYNC_EXTI11 RM_CHXCFG_SYNCID(11U) /*!< synchronization input is EXTI11 */ +#define DMAMUX_SYNC_EXTI12 RM_CHXCFG_SYNCID(12U) /*!< synchronization input is EXTI12 */ +#define DMAMUX_SYNC_EXTI13 RM_CHXCFG_SYNCID(13U) /*!< synchronization input is EXTI13 */ +#define DMAMUX_SYNC_EXTI14 RM_CHXCFG_SYNCID(14U) /*!< synchronization input is EXTI14 */ +#define DMAMUX_SYNC_EXTI15 RM_CHXCFG_SYNCID(15U) /*!< synchronization input is EXTI15 */ +#define DMAMUX_SYNC_EVTX_OUT0 RM_CHXCFG_SYNCID(16U) /*!< synchronization input is Evtx_out0 */ +#define DMAMUX_SYNC_EVTX_OUT1 RM_CHXCFG_SYNCID(17U) /*!< synchronization input is Evtx_out1 */ +#define DMAMUX_SYNC_EVTX_OUT2 RM_CHXCFG_SYNCID(18U) /*!< synchronization input is Evtx_out2 */ +#define DMAMUX_SYNC_EVTX_OUT3 RM_CHXCFG_SYNCID(19U) /*!< synchronization input is Evtx_out3 */ +#define DMAMUX_SYNC_TIMER20_CH0_O RM_CHXCFG_SYNCID(22U) /*!< synchronization input is TIMER20_CH0_O */ + +/* DMAMUX request multiplexer synchronization input polarity */ +#define RM_CHXCFG_SYNCP(regval) (BITS(17,18) & ((regval) << 17U)) /*!< synchronization input polarity */ +#define DMAMUX_SYNC_NO_EVENT RM_CHXCFG_SYNCP(0U) /*!< no event detection */ +#define DMAMUX_SYNC_RISING RM_CHXCFG_SYNCP(1U) /*!< rising edge */ +#define DMAMUX_SYNC_FALLING RM_CHXCFG_SYNCP(2U) /*!< falling edge */ +#define DMAMUX_SYNC_RISING_FALLING RM_CHXCFG_SYNCP(3U) /*!< rising and falling edges */ + +/* number of DMA requests to forward */ +#define RM_CHXCFG_NBR(regval) (BITS(19,23) & ((regval) << 19)) /*!< number of DMA requests to forward */ + +/* function declarations */ +/* DMA functions */ +/* DMA initialization functions */ +/* deinitialize DMA channel registers */ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); +/* initialize the parameters of DMA structure with the default values */ +void dma_struct_para_init(dma_parameter_struct* init_struct); +/* initialize DMA channel */ +void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct* init_struct); +/* enable DMA circulation mode */ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA circulation mode */ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable memory to memory mode */ +void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable memory to memory mode */ +void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable DMA channel */ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA channel */ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); + +/* DMA configuration functions */ +/* set DMA peripheral base address */ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); +/* configure DMA memory base address */ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); +/* configure the number of remaining data to be transferred by the DMA */ +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number); +/* get the number of remaining data to be transferred by the DMA */ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); +/* configure priority level of DMA channel */ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); +/* configure transfer data size of memory */ +void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth); +/* configure transfer data size of peripheral */ +void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth); +/* enable next address increasement algorithm of memory */ +void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable next address increasement algorithm of memory */ +void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable next address increasement algorithm of peripheral */ +void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable next address increasement algorithm of peripheral */ +void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* configure the direction of data transfer on the channel */ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction); + +/* DMA interrupt and flag functions */ +/* check DMA flag is set or not */ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* clear a DMA channel flag */ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* enable DMA interrupt */ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); +/* disable DMA interrupt */ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); +/* check DMA flag and interrupt enable bit is set or not */ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t int_flag); +/* clear a DMA channel interrupt flag */ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t int_flag); + +/* DMAMUX functions */ +/* DMAMUX request multiplexer functions */ +/* initialize the parameters of DMAMUX synchronization mode structure with the default values */ +void dmamux_sync_struct_para_init(dmamux_sync_parameter_struct *init_struct); +/* initialize DMAMUX request multiplexer channel synchronization mode */ +void dmamux_synchronization_init(dmamux_multiplexer_channel_enum channelx, dmamux_sync_parameter_struct *init_struct); +/* enable synchronization mode */ +void dmamux_synchronization_enable(dmamux_multiplexer_channel_enum channelx); +/* disable synchronization mode */ +void dmamux_synchronization_disable(dmamux_multiplexer_channel_enum channelx); +/* enable event generation */ +void dmamux_event_generation_enable(dmamux_multiplexer_channel_enum channelx); +/* disable event generation */ +void dmamux_event_generation_disable(dmamux_multiplexer_channel_enum channelx); + +/* DMAMUX request generator functions */ +/* initialize the parameters of DMAMUX request generator structure with the default values */ +void dmamux_gen_struct_para_init(dmamux_gen_parameter_struct *init_struct); +/* initialize DMAMUX request generator channel */ +void dmamux_request_generator_init(dmamux_generator_channel_enum channelx, dmamux_gen_parameter_struct *init_struct); +/* enable DMAMUX request generator channel */ +void dmamux_request_generator_channel_enable(dmamux_generator_channel_enum channelx); +/* disable DMAMUX request generator channel */ +void dmamux_request_generator_channel_disable(dmamux_generator_channel_enum channelx); + +/* DMAMUX configuration functions */ +/* configure synchronization input polarity */ +void dmamux_synchronization_polarity_config(dmamux_multiplexer_channel_enum channelx, uint32_t polarity); +/* configure number of DMA requests to forward */ +void dmamux_request_forward_number_config(dmamux_multiplexer_channel_enum channelx, uint32_t number); +/* configure synchronization input identification */ +void dmamux_sync_id_config(dmamux_multiplexer_channel_enum channelx, uint32_t id); +/* configure multiplexer input identification */ +void dmamux_request_id_config(dmamux_multiplexer_channel_enum channelx, uint32_t id); +/* configure trigger input polarity */ +void dmamux_trigger_polarity_config(dmamux_generator_channel_enum channelx, uint32_t polarity); +/* configure number of DMA requests to be generated */ +void dmamux_request_generate_number_config(dmamux_generator_channel_enum channelx, uint32_t number); +/* configure trigger input identification */ +void dmamux_trigger_id_config(dmamux_generator_channel_enum channelx, uint32_t id); + +/* DMAMUX interrupt and flag functions */ +/* get DMAMUX flag */ +FlagStatus dmamux_flag_get(dmamux_flag_enum flag); +/* clear DMAMUX flag */ +void dmamux_flag_clear(dmamux_flag_enum flag); +/* enable DMAMUX interrupt */ +void dmamux_interrupt_enable(dmamux_interrupt_enum interrupt); +/* disable DMAMUX interrupt */ +void dmamux_interrupt_disable(dmamux_interrupt_enum interrupt); +/* get DMAMUX interrupt flag */ +FlagStatus dmamux_interrupt_flag_get(dmamux_interrupt_flag_enum int_flag); +/* clear DMAMUX interrupt flag */ +void dmamux_interrupt_flag_clear(dmamux_interrupt_flag_enum int_flag); + +#endif /* GD32A50X_DMA_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_exti.h b/gd32a50x/standard_peripheral/include/gd32a50x_exti.h new file mode 100644 index 0000000..3c9dfaa --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_exti.h @@ -0,0 +1,286 @@ +/*! + \file gd32a50x_exti.h + \brief definitions for the EXTI + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_EXTI_H +#define GD32A50X_EXTI_H + +#include "gd32a50x.h" + +/* EXTI definitions */ +#define EXTI EXTI_BASE + +/* registers definitions */ +#define EXTI_INTEN REG32(EXTI + 0x00000000U) /*!< interrupt enable register */ +#define EXTI_EVEN REG32(EXTI + 0x00000004U) /*!< event enable register */ +#define EXTI_RTEN REG32(EXTI + 0x00000008U) /*!< rising edge trigger enable register */ +#define EXTI_FTEN REG32(EXTI + 0x0000000CU) /*!< falling trigger enable register */ +#define EXTI_SWIEV REG32(EXTI + 0x00000010U) /*!< software interrupt event register */ +#define EXTI_PD REG32(EXTI + 0x00000014U) /*!< pending register */ + +/* bits definitions */ +/* EXTI_INTEN */ +#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ +#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ +#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ +#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ +#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ +#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ +#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ +#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ +#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ +#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ +#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ +#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ +#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ +#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ +#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ +#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ +#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ +#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ +#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ +#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ +#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */ +#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */ +#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */ +#define EXTI_INTEN_INTEN23 BIT(23) /*!< interrupt from line 23 */ +#define EXTI_INTEN_INTEN24 BIT(24) /*!< interrupt from line 24 */ +/* EXTI_EVEN */ +#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ +#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ +#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ +#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ +#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ +#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ +#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ +#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ +#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ +#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ +#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ +#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ +#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ +#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ +#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ +#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ +#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ +#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ +#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ +#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ +#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */ +#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */ +#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */ +#define EXTI_EVEN_EVEN23 BIT(23) /*!< event from line 23 */ +#define EXTI_EVEN_EVEN24 BIT(24) /*!< event from line 24 */ + +/* EXTI_RTEN */ +#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ +#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ +#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ +#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ +#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ +#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ +#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ +#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ +#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ +#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ +#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ +#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ +#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ +#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ +#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ +#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ +#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ +#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ +#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ +#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ +#define EXTI_RTEN_RTEN20 BIT(20) /*!< rising edge from line 20 */ +#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */ +#define EXTI_RTEN_RTEN22 BIT(22) /*!< rising edge from line 22 */ +#define EXTI_RTEN_RTEN23 BIT(23) /*!< rising edge from line 23 */ +#define EXTI_RTEN_RTEN24 BIT(24) /*!< rising edge from line 24 */ + +/* EXTI_FTEN */ +#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ +#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ +#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ +#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ +#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ +#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ +#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ +#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ +#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ +#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ +#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ +#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ +#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ +#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ +#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ +#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ +#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ +#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ +#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ +#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ +#define EXTI_FTEN_FTEN20 BIT(20) /*!< falling edge from line 20 */ +#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */ +#define EXTI_FTEN_FTEN22 BIT(22) /*!< falling edge from line 22 */ +#define EXTI_FTEN_FTEN23 BIT(23) /*!< falling edge from line 23 */ +#define EXTI_FTEN_FTEN24 BIT(24) /*!< falling edge from line 24 */ +/* EXTI_SWIEV */ +#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ +#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ +#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ +#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ +#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ +#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ +#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ +#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ +#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ +#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ +#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ +#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ +#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ +#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ +#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ +#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ +#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ +#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ +#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ +#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ +#define EXTI_SWIEV_SWIEV20 BIT(20) /*!< software interrupt/event request from line 20 */ +#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */ +#define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */ +#define EXTI_SWIEV_SWIEV23 BIT(23) /*!< software interrupt/event request from line 23 */ +#define EXTI_SWIEV_SWIEV24 BIT(24) /*!< software interrupt/event request from line 24 */ + +/* EXTI_PD */ +#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ +#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ +#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ +#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ +#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ +#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ +#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ +#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ +#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ +#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ +#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ +#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ +#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ +#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ +#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ +#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ +#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ +#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ +#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ +#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ +#define EXTI_PD_PD20 BIT(20) /*!< interrupt/event pending status from line 20 */ +#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */ +#define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */ +#define EXTI_PD_PD23 BIT(23) /*!< interrupt/event pending status from line 23 */ +#define EXTI_PD_PD24 BIT(24) /*!< interrupt/event pending status from line 24 */ + +/* constants definitions */ +/* EXTI line number */ +typedef enum +{ + EXTI_0 = BIT(0), /*!< EXTI line 0 */ + EXTI_1 = BIT(1), /*!< EXTI line 1 */ + EXTI_2 = BIT(2), /*!< EXTI line 2 */ + EXTI_3 = BIT(3), /*!< EXTI line 3 */ + EXTI_4 = BIT(4), /*!< EXTI line 4 */ + EXTI_5 = BIT(5), /*!< EXTI line 5 */ + EXTI_6 = BIT(6), /*!< EXTI line 6 */ + EXTI_7 = BIT(7), /*!< EXTI line 7 */ + EXTI_8 = BIT(8), /*!< EXTI line 8 */ + EXTI_9 = BIT(9), /*!< EXTI line 9 */ + EXTI_10 = BIT(10), /*!< EXTI line 10 */ + EXTI_11 = BIT(11), /*!< EXTI line 11 */ + EXTI_12 = BIT(12), /*!< EXTI line 12 */ + EXTI_13 = BIT(13), /*!< EXTI line 13 */ + EXTI_14 = BIT(14), /*!< EXTI line 14 */ + EXTI_15 = BIT(15), /*!< EXTI line 15 */ + EXTI_16 = BIT(16), /*!< EXTI line 16 */ + EXTI_17 = BIT(17), /*!< EXTI line 17 */ + EXTI_18 = BIT(18), /*!< EXTI line 18 */ + EXTI_19 = BIT(19), /*!< EXTI line 19 */ + EXTI_20 = BIT(20), /*!< EXTI line 20 */ + EXTI_21 = BIT(21), /*!< EXTI line 21 */ + EXTI_22 = BIT(22), /*!< EXTI line 22 */ + EXTI_23 = BIT(23), /*!< EXTI line 23 */ + EXTI_24 = BIT(24), /*!< EXTI line 24 */ +}exti_line_enum; + +/* external interrupt and event */ +typedef enum +{ + EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ + EXTI_EVENT /*!< EXTI event mode */ +}exti_mode_enum; + +/* interrupt trigger mode */ +typedef enum +{ + EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ + EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ + EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */ + EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */ +}exti_trig_type_enum; + +/* function declarations */ +/* deinitialize the EXTI */ +void exti_deinit(void); +/* initialize the EXTI */ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); +/* enable the interrupts from EXTI line x */ +void exti_interrupt_enable(exti_line_enum linex); +/* disable the interrupts from EXTI line x */ +void exti_interrupt_disable(exti_line_enum linex); +/* enable the events from EXTI line x */ +void exti_event_enable(exti_line_enum linex); +/* disable the events from EXTI line x */ +void exti_event_disable(exti_line_enum linex); + +/* enable the EXTI software interrupt event */ +void exti_software_interrupt_enable(exti_line_enum linex); +/* disable the EXTI software interrupt event */ +void exti_software_interrupt_disable(exti_line_enum linex); +/* get EXTI line x pending flag */ +FlagStatus exti_flag_get(exti_line_enum linex); +/* clear EXTI line x pending flag */ +void exti_flag_clear(exti_line_enum linex); +/* get EXTI line x flag when the interrupt flag is set */ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex); +/* clear EXTI line x pending flag */ +void exti_interrupt_flag_clear(exti_line_enum linex); + +#endif /* GD32A50X_EXTI_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_fmc.h b/gd32a50x/standard_peripheral/include/gd32a50x_fmc.h new file mode 100644 index 0000000..24d9f25 --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_fmc.h @@ -0,0 +1,537 @@ +/*! + \file gd32a50x_fmc.h + \brief definitions for the FMC + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_FMC_H +#define GD32A50X_FMC_H + +#include "gd32a50x.h" + +/* FMC and option bytes definition */ +#define FMC FMC_BASE /*!< FMC register base address */ +#define OB OB_BASE /*!< option bytes 0 base address */ + +/* registers definitions */ +#define FMC_WS REG32((FMC) + 0x00000000U) /*!< FMC wait state register */ +#define FMC_ECCCS REG32((FMC) + 0x00000004U) /*!< FMC ECC control and status register */ +#define FMC_KEY0 REG32((FMC) + 0x00000008U) /*!< FMC unlock key register 0 */ +#define FMC_STAT0 REG32((FMC) + 0x0000000CU) /*!< FMC status register 0 */ +#define FMC_CTL0 REG32((FMC) + 0x00000010U) /*!< FMC control register 0 */ +#define FMC_ADDR0 REG32((FMC) + 0x00000014U) /*!< FMC address register 0 */ +#define FMC_OBKEY REG32((FMC) + 0x00000044U) /*!< FMC option byte unlock key register */ +#define FMC_KEY1 REG32((FMC) + 0x00000048U) /*!< FMC unlock key register 1 */ +#define FMC_STAT1 REG32((FMC) + 0x0000004CU) /*!< FMC status register 1 */ +#define FMC_CTL1 REG32((FMC) + 0x00000050U) /*!< FMC control register 1 */ +#define FMC_ADDR1 REG32((FMC) + 0x00000054U) /*!< FMC address register 1 */ +#define FMC_EPCNT REG32((FMC) + 0x00000058U) /*!< FMC EEPROM counter register */ +#define FMC_OBSTAT REG32((FMC) + 0x0000005CU) /*!< FMC option byte status register */ +#define FMC_WP0 REG32((FMC) + 0x00000060U) /*!< FMC erase/program protection register 0 */ +#define FMC_WP1 REG32((FMC) + 0x00000064U) /*!< FMC erase/program protection register 1 */ +#define FMC_OB1CS REG32((FMC) + 0x00000068U) /*!< FMC option byte 1 control and status register */ +#define FMC_PID REG32((FMC) + 0x00000100U) /*!< FMC product ID register */ + +#define OP_BYTE(x) REG32(OB + ((uint32_t)((uint32_t)0x04U * (x)))) /*!< option bytes 0 value */ +#define OB_SPC REG16((OB) + 0x00000000U) /*!< option bytes 0 security protection value*/ +#define OB_USER REG16((OB) + 0x00000002U) /*!< option bytes 0 user value*/ +#define OB_SPC_USER REG32((OB) + 0x00000000U) /*!< option bytes 0 security protection value and user value */ +#define OB_DATA REG32((OB) + 0x00000004U) /*!< option bytes 0 data value */ + +/* bits definitions */ +/* FMC_WS */ +#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ +#define FMC_WS_PFEN BIT(4) /*!< pre-fetch enable */ +#define FMC_WS_IDCEN BIT(9) /*!< cache enable */ +#define FMC_WS_IDRST BIT(11) /*!< cache reset */ +#define FMC_WS_SLEEP_SLP BIT(14) /*!< flash goto sleep mode or power-down mode when MCU enters deepsleep mode */ +#define FMC_WS_ERAMRDY BIT(16) /*!< EEPROM SRAM ready flag */ +#define FMC_WS_BRAMRDY BIT(17) /*!< basic SRAM ready flag */ +#define FMC_WS_PRAMRDY BIT(18) /*!< fast PG SRAM ready flag */ + +/* FMC_ECCCS */ +#define FMC_ECCCS_ECCADDR BITS(0,14) /*!< the offset address of double word where an ECC error is detected */ +#define FMC_ECCCS_OB0_ECC BIT(19) /*!< option bytes 0 one bit error flag */ +#define FMC_ECCCS_BK1_ECC BIT(20) /*!< bank1 one bit error flag */ +#define FMC_ECCCS_SYS_ECC BIT(21) /*!< system memory one bit error flag */ +#define FMC_ECCCS_DF_ECC BIT(22) /*!< data flash one bit error flag */ +#define FMC_ECCCS_OTP_ECC BIT(23) /*!< OTP one bit error flag */ +#define FMC_ECCCS_ECCCORIE BIT(24) /*!< one bit error correct interrupt enable */ +#define FMC_ECCCS_ECCDETIE BIT(25) /*!< two bits error detect interrupt enable */ +#define FMC_ECCCS_OB1ECCDET BIT(26) /*!< option bytes 1 two bits error detect flag */ +#define FMC_ECCCS_OB0ECCDET BIT(27) /*!< option bytes 0 two bits error detect flag */ +#define FMC_ECCCS_EPECCDET BIT(29) /*!< EEPROM two bits error detect flag */ +#define FMC_ECCCS_ECCCOR BIT(30) /*!< one bit error detected and correct flag */ +#define FMC_ECCCS_ECCDET BIT(31) /*!< two bits error detect flag */ + +/* FMC_KEY0 */ +#define FMC_KEY0_KEY BITS(0,31) /*!< flash bank0 unlock key bits */ + +/* FMC_STAT0 */ +#define FMC_STAT0_BUSY BIT(0) /*!< flash bank0 busy flag */ +#define FMC_STAT0_PGSERR BIT(1) /*!< flash bank0 program sequence error flag */ +#define FMC_STAT0_PGERR BIT(2) /*!< flash bank0 program error flag */ +#define FMC_STAT0_PGAERR BIT(3) /*!< flash bank0 program alignment error flag */ +#define FMC_STAT0_WPERR BIT(4) /*!< flash bank0 erase/program protection error flag */ +#define FMC_STAT0_ENDF BIT(5) /*!< flash bank0 end of operation flag */ +#define FMC_STAT0_CBCMDERR BIT(6) /*!< flash bank0 checked area by the check blank command is all 0xFF or not */ +#define FMC_STAT0_RSTERR BIT(15) /*!< flash bank0 BOR/POR or system reset during erase/program flag */ + +/* FMC_CTL0 */ +#define FMC_CTL0_PG BIT(0) /*!< flash bank0 program command bit */ +#define FMC_CTL0_PER BIT(1) /*!< flash bank0 page erase bit */ +#define FMC_CTL0_MER BIT(2) /*!< flash bank0 mass erase bit */ +#define FMC_CTL0_START BIT(6) /*!< send erase command to flash bank0 bit */ +#define FMC_CTL0_LK BIT(7) /*!< flash bank0 lock bit */ +#define FMC_CTL0_FSTPG BIT(8) /*!< flash bank0 fast program command bit */ +#define FMC_CTL0_ERRIE BIT(10) /*!< flash bank0 error interrupt enable bit */ +#define FMC_CTL0_ENDIE BIT(12) /*!< flash bank0 end of operation interrupt enable bit */ +#define FMC_CTL0_CBCMD BIT(16) /*!< send check blank command to flash bank0 bit */ +#define FMC_CTL0_CBCMDLEN BITS(29,31) /*!< check blank command read length to flash bank0 */ + +/* FMC_ADDR0 */ +#define FMC_ADDR0_ADDR BITS(0,31) /*!< flash bank0 command address bits */ + +/* FMC_OBKEY */ +#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ + +/* FMC_KEY1 */ +#define FMC_KEY1_KEY BITS(0,31) /*!< flash bank1 unlock key bits */ + +/* FMC_STAT1 */ +#define FMC_STAT1_BUSY BIT(0) /*!< flash bank1 busy flag */ +#define FMC_STAT1_PGSERR BIT(1) /*!< flash bank1 program sequence error flag */ +#define FMC_STAT1_PGERR BIT(2) /*!< flash bank1 program error flag */ +#define FMC_STAT1_PGAERR BIT(3) /*!< flash bank1 program alignment error flag */ +#define FMC_STAT1_WPERR BIT(4) /*!< flash bank1 erase/program protection error flag */ +#define FMC_STAT1_ENDF BIT(5) /*!< flash bank1 end of operation flag */ +#define FMC_STAT1_CBCMDERR BIT(6) /*!< flash bank1 checked area by the check blank command is all 0xFF or not */ +#define FMC_STAT1_RSTERR BIT(15) /*!< flash bank1 BOR/POR or system reset during erase/program flag */ + +/* FMC_CTL1 */ +#define FMC_CTL1_PG BIT(0) /*!< flash bank1 program command bit */ +#define FMC_CTL1_PER BIT(1) /*!< flash bank1 page erase bit */ +#define FMC_CTL1_MER BIT(2) /*!< flash bank1 mass erase bit */ +#define FMC_CTL1_MERDF BIT(3) /*!< data flash mass erase bit */ +#define FMC_CTL1_OB0PG BIT(4) /*!< option bytes 0 program command bit */ +#define FMC_CTL1_OB0ER BIT(5) /*!< option bytes 0 erase command bit */ +#define FMC_CTL1_START BIT(6) /*!< send erase command to FMC bit */ +#define FMC_CTL1_LK BIT(7) /*!< flash bank1 lock bit */ +#define FMC_CTL1_FSTPG BIT(8) /*!< fast program command bit */ +#define FMC_CTL1_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ +#define FMC_CTL1_ERRIE BIT(10) /*!< flash bank1 error interrupt enable bit */ +#define FMC_CTL1_ENDIE BIT(12) /*!< flash bank1 end of operation interrupt enable bit */ +#define FMC_CTL1_OBRLD BIT(13) /*!< option bytes reload bit */ +#define FMC_CTL1_CBCMD BIT(16) /*!< send check blank command to flash bank1 bit */ +#define FMC_CTL1_SRAMCMD BITS(24,25) /*!< send shared SRAM command */ +#define FMC_CTL1_CBCMDLEN BITS(29,31) /*!< check blank command read length to flash bank1 */ + +/* FMC_ADDR1 */ +#define FMC_ADDR1_ADDR BITS(0,31) /*!< flash bank1 command address bits */ + +/* FMC_EPCNT */ +#define FMC_EPCNT_EPCNT BITS(0,31) /*!< EEPROM erase counter */ + +/* FMC_OBSTAT */ +#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit */ +#define FMC_OBSTAT_PLEVEL BITS(1,2) /*!< protection level bits */ +#define FMC_OBSTAT_USER BITS(8,15) /*!< option bytes user bits */ +#define FMC_OBSTAT_DATA BITS(16,31) /*!< option bytes data bits */ + +/* FMC_WP0 */ +#define FMC_WP0_BK0WP BITS(0,31) /*!< store OB_BK0WP[31:0] of option bytes 0 block after system reset */ + +/* FMC_WP1 */ +#define FMC_WP1_BK1WP BITS(0,7) /*!< store OB_BK1WP[7:0] of option bytes 0 block after system reset */ +#define FMC_WP1_DFWP BITS(8,15) /*!< store OB_DFWP[7:0] of option bytes 0 block after system reset */ +#define FMC_WP1_EPWP BITS(16,23) /*!< store OB_EPWP[7:0] of option bytes 0 block after system reset */ + +/* FMC_OB1CS */ +#define FMC_OB1CS_OB1ERR BIT(0) /*!< option bytes 1 read error bit */ +#define FMC_OB1CS_OB1START BIT(1) /*!< send option bytes 1 change command to FMC */ +#define FMC_OB1CS_OB1LK BIT(2) /*!< option bytes 1 lock bit */ +#define FMC_OB1CS_EFALC BITS(4,7) /*!< load EFALC of option bytes 1 after reset */ +#define FMC_OB1CS_EPSIZE BITS(8,11) /*!< load EPSIZE of option bytes 1 after reset */ +#define FMC_OB1CS_EPLOAD BIT(15) /*!< load EPLOAD of option bytes 1 after reset */ +#define FMC_OB1CS_LKVAL BITS(16,31) /*!< load LKVAL of option bytes 1 after reset */ + +/* FMC_PID */ +#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ + +/* constants definitions */ +/* fmc state */ +typedef enum { + FMC_READY, /*!< the operation has been completed */ + FMC_BUSY, /*!< the operation is in progress */ + FMC_PGSERR, /*!< program sequence error */ + FMC_PGERR, /*!< program error */ + FMC_PGAERR, /*!< program alignment error */ + FMC_WPERR, /*!< erase/program protection error */ + FMC_TOERR, /*!< timeout error */ + FMC_CBCMDERR, /*!< the checked area not blank error */ + FMC_RSTERR, /*!< BOR/POR or system reset during flash erase/program error */ + FMC_OB_HSPC, /*!< FMC is under high security protection */ + FMC_OB1_LK /*!< option bytes 1 is locked */ +} fmc_state_enum; + +/* shared SRAM mode */ +typedef enum { + NO_SRAM_MODE = 0, /*!< SRAM mode is not configured */ + FASTPG_SRAM_MODE = 1, /*!< fast program SRAM mode */ + BASIC_SRAM_MODE = 2, /*!< basic SRAM mode */ + EEPROM_SRAM_MODE = 3 /*!< EEPROM SRAM mode */ +} fmc_sram_mode_enum; + +/* FMC area */ +typedef enum { + BANK0_AREA = 0, /*!< main flash bank0 area */ + BANK1_AREA = 1, /*!< main flash bank1 area */ + DATA_FLASH_AREA = 2, /*!< data flash area */ + EEPROM_AREA = 3 /*!< EEPROM area */ +} fmc_area_enum; + +/* define the FMC bit position and its register index offset */ +#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define FMC_REG_VAL(offset) (REG32(FMC + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) +#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) +#define FMC_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define FMC_REG_VAL2(offset) (REG32(FMC + ((uint32_t)(offset) >> 22))) +#define FMC_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) + +/* register offset */ +#define FMC_STAT0_REG_OFFSET ((uint32_t)0x0000000CU) /*!< STAT0 register offset */ +#define FMC_STAT1_REG_OFFSET ((uint32_t)0x0000004CU) /*!< STAT1 register offset */ +#define FMC_ECCCS_REG_OFFSET ((uint32_t)0x00000004U) /*!< ECCCS register offset */ +#define FMC_OB1CS_REG_OFFSET ((uint32_t)0x00000068U) /*!< OB1CS register offset */ +#define FMC_CTL0_REG_OFFSET ((uint32_t)0x00000010U) /*!< CTL0 register offset */ +#define FMC_CTL1_REG_OFFSET ((uint32_t)0x00000050U) /*!< CTL1 register offset */ +#define FMC_OBSTAT_REG_OFFSET ((uint32_t)0x0000005CU) /*!< OBSTAT register offset */ + +/* FMC flags */ +typedef enum { + /* flags in STAT0 register */ + FMC_BANK0_FLAG_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< flash bank0 busy flag */ + FMC_BANK0_FLAG_PGSERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 1U), /*!< flash bank0 program sequence error flag */ + FMC_BANK0_FLAG_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< flash bank0 program error flag */ + FMC_BANK0_FLAG_PGAERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 3U), /*!< flash bank0 program alignment error flag */ + FMC_BANK0_FLAG_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< flash bank0 erase/program protection error flag */ + FMC_BANK0_FLAG_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< flash bank0 end of operation flag */ + FMC_BANK0_FLAG_CBCMDERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 6U), /*!< flash bank0 checked area by the check blank command is all 0xFF or not flag */ + FMC_BANK0_FLAG_RSTERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 15U), /*!< flash bank0 BOR/POR or system reset during erase/program flag */ + /* flags in STAT1 register */ + FMC_BANK1_FLAG_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U), /*!< flash bank1 busy flag */ + FMC_BANK1_FLAG_PGSERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 1U), /*!< flash bank1 program sequence error flag */ + FMC_BANK1_FLAG_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), /*!< flash bank1 program error flag */ + FMC_BANK1_FLAG_PGAERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 3U), /*!< flash bank1 program alignment error flag */ + FMC_BANK1_FLAG_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U), /*!< flash bank1 erase/program protection error flag */ + FMC_BANK1_FLAG_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U), /*!< flash bank1 end of operation flag */ + FMC_BANK1_FLAG_CBCMDERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 6U), /*!< flash bank1 checked area by the check blank command is all 0xFF or not flag */ + FMC_BANK1_FLAG_RSTERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 15U), /*!< flash bank1 BOR/POR or system reset during erase/program flag */ + /* flags in ECCCS register */ + FMC_FLAG_BK0ECC = FMC_REGIDX_BIT(FMC_ECCCS_REG_OFFSET, 28U), /*!< an ECC bit error is detected in bank 0 flag */ + FMC_FLAG_OB0ECC = FMC_REGIDX_BIT(FMC_ECCCS_REG_OFFSET, 19U), /*!< an ECC bit error is detected in option byte 0 flag */ + FMC_FLAG_BK1ECC = FMC_REGIDX_BIT(FMC_ECCCS_REG_OFFSET, 20U), /*!< an ECC bit error is detected in bank 1 flag */ + FMC_FLAG_SYSECC = FMC_REGIDX_BIT(FMC_ECCCS_REG_OFFSET, 21U), /*!< an ECC bit error is detected in system memory flag */ + FMC_FLAG_DFECC = FMC_REGIDX_BIT(FMC_ECCCS_REG_OFFSET, 22U), /*!< an ECC bit error is detected in data flash flag */ + FMC_FLAG_OTPECC = FMC_REGIDX_BIT(FMC_ECCCS_REG_OFFSET, 23U), /*!< an ECC bit error is detected in OTP flag */ + FMC_FLAG_OB1ECCDET = FMC_REGIDX_BIT(FMC_ECCCS_REG_OFFSET, 26U), /*!< option bytes 1 two bit error detect flag */ + FMC_FLAG_OB0ECCDET = FMC_REGIDX_BIT(FMC_ECCCS_REG_OFFSET, 27U), /*!< option bytes 0 two bit error detect flag */ + FMC_FLAG_EPECCDET = FMC_REGIDX_BIT(FMC_ECCCS_REG_OFFSET, 29U), /*!< EEPROM two bits error detect flag */ + FMC_FLAG_ECCCOR = FMC_REGIDX_BIT(FMC_ECCCS_REG_OFFSET, 30U), /*!< one bit error detected and correct flag */ + FMC_FLAG_ECCDET = FMC_REGIDX_BIT(FMC_ECCCS_REG_OFFSET, 31U), /*!< OTP/data flash/system memory/bank1 two bit error detect flag */ + /* flags in OBSTAT register */ + FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< option bytes 0 error flag */ + /* flags in OB1CS register */ + FMC_FLAG_OB1ERR = FMC_REGIDX_BIT(FMC_OB1CS_REG_OFFSET, 0U) /*!< option bytes 1 read error flag */ +} fmc_flag_enum; + +/* FMC interrupt flags */ +typedef enum { + /* interrupt flags in STAT0 register */ + FMC_BANK0_INT_FLAG_PGSERR = FMC_REGIDX_BIT2(FMC_CTL0_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 1U), /*!< flash bank0 program sequence error interrupt flag */ + FMC_BANK0_INT_FLAG_PGERR = FMC_REGIDX_BIT2(FMC_CTL0_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 2U), /*!< flash bank0 program error interrupt flag */ + FMC_BANK0_INT_FLAG_PGAERR = FMC_REGIDX_BIT2(FMC_CTL0_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 3U), /*!< flash bank0 program alignment error interrupt flag */ + FMC_BANK0_INT_FLAG_WPERR = FMC_REGIDX_BIT2(FMC_CTL0_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 4U), /*!< flash bank0 erase/program protection error interrupt flag */ + FMC_BANK0_INT_FLAG_END = FMC_REGIDX_BIT2(FMC_CTL0_REG_OFFSET, 12U, FMC_STAT0_REG_OFFSET, 5U), /*!< flash bank0 end of operation interrupt flag */ + FMC_BANK0_INT_FLAG_CBCMDERR = FMC_REGIDX_BIT2(FMC_CTL0_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 6U), /*!< flash bank0 checked area by the check blank command is all 0xFF or not interrupt flag */ + FMC_BANK0_INT_FLAG_RSTERR = FMC_REGIDX_BIT2(FMC_CTL0_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 15U), /*!< flash bank0 BOR/POR or system reset during erase/program interrupt flag */ + /* interrupt flags in STAT1 register */ + FMC_BANK1_INT_FLAG_PGSERR = FMC_REGIDX_BIT2(FMC_CTL1_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 1U), /*!< flash bank1 program sequence error interrupt flag */ + FMC_BANK1_INT_FLAG_PGERR = FMC_REGIDX_BIT2(FMC_CTL1_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 2U), /*!< flash bank1 program error interrupt flag */ + FMC_BANK1_INT_FLAG_PGAERR = FMC_REGIDX_BIT2(FMC_CTL1_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 3U), /*!< flash bank1 program alignment error interrupt flag */ + FMC_BANK1_INT_FLAG_WPERR = FMC_REGIDX_BIT2(FMC_CTL1_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 4U), /*!< flash bank1 erase/program protection error interrupt flag */ + FMC_BANK1_INT_FLAG_END = FMC_REGIDX_BIT2(FMC_CTL1_REG_OFFSET, 12U, FMC_STAT0_REG_OFFSET, 5U), /*!< flash bank1 end of operation interrupt flag */ + FMC_BANK1_INT_FLAG_CBCMDERR = FMC_REGIDX_BIT2(FMC_CTL1_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 6U), /*!< flash bank1 checked area by the check blank command is all 0xFF or not interrupt flag */ + FMC_BANK1_INT_FLAG_RSTERR = FMC_REGIDX_BIT2(FMC_CTL1_REG_OFFSET, 10U, FMC_STAT0_REG_OFFSET, 15U), /*!< flash bank1 BOR/POR or system reset during erase/program interrupt flag */ + /* interrupt flags in ECCCS register */ + FMC_INT_FLAG_OB1ECCDET = FMC_REGIDX_BIT2(FMC_ECCCS_REG_OFFSET, 25U, FMC_ECCCS_REG_OFFSET, 26U), /*!< option bytes 1 two bits error detect interrupt flag */ + FMC_INT_FLAG_OB0ECCDET = FMC_REGIDX_BIT2(FMC_ECCCS_REG_OFFSET, 25U, FMC_ECCCS_REG_OFFSET, 27U), /*!< option bytes 0 two bits error detect interrupt flag */ + FMC_INT_FLAG_EPECCDET = FMC_REGIDX_BIT2(FMC_ECCCS_REG_OFFSET, 25U, FMC_ECCCS_REG_OFFSET, 29U), /*!< EEPROM two bits error detect interrupt flag */ + FMC_INT_FLAG_ECCCOR = FMC_REGIDX_BIT2(FMC_ECCCS_REG_OFFSET, 24U, FMC_ECCCS_REG_OFFSET, 30U), /*!< one bit error detected and correct interrupt flag */ + FMC_INT_FLAG_ECCDET = FMC_REGIDX_BIT2(FMC_ECCCS_REG_OFFSET, 25U, FMC_ECCCS_REG_OFFSET, 31U) /*!< two bits error detect interrupt flag */ +} fmc_interrupt_flag_enum; + +/* FMC interrupt */ +typedef enum { + /* interrupt in CTL0 register */ + FMC_BANK0_INT_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< FMC bank0 error interrupt */ + FMC_BANK0_INT_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< FMC bank0 end of operation interrupt */ + /* interrupt in CTL1 register */ + FMC_BANK1_INT_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< FMC bank1 error interrupt */ + FMC_BANK1_INT_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< FMC bank1 end of operation interrupt */ + /* interrupt in ECCCS register */ + FMC_INT_ECCCOR = FMC_REGIDX_BIT(FMC_ECCCS_REG_OFFSET, 24U), /*!< FMC one bit error correct interrupt */ + FMC_INT_ECCDET = FMC_REGIDX_BIT(FMC_ECCCS_REG_OFFSET, 25U) /*!< FMC two bits error interrupt */ +} fmc_interrupt_enum; + +/* unlock key */ +#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ +#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ + +/* wait state counter value */ +#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define WS_WSCNT_0 WS_WSCNT(0) /*!< 0 wait state added */ +#define WS_WSCNT_1 WS_WSCNT(1) /*!< 1 wait state added */ +#define WS_WSCNT_2 WS_WSCNT(2) /*!< 2 wait state added */ +#define WS_WSCNT_3 WS_WSCNT(3) /*!< 3 wait state added */ + +/* shared SRAM command */ +#define CTL1_SRAMCMD(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) +#define FASTPG_SRAM_CMD CTL1_SRAMCMD(1) /*!< set fast PG RAM mode */ +#define BASIC_SRAM_CMD CTL1_SRAMCMD(2) /*!< set basic RAM mode */ +#define EEPROM_SRAM_CMD CTL1_SRAMCMD(3) /*!< set EEPROM RAM mode */ + +/* option bytes security protection level in FMC_OBSTAT register */ +#define OB_OBSTAT_PLEVEL_NO ((uint8_t)0x00U) /*!< no security protection */ +#define OB_OBSTAT_PLEVEL_LOW ((uint8_t)0x01U) /*!< low security protection */ +#define OB_OBSTAT_PLEVEL_HIGH ((uint8_t)0x03U) /*!< high security protection */ + +/* option bytes read protection configuration */ +#define FMC_NSPC ((uint16_t)0x5AA5U) /*!< no security protection */ +#define FMC_LSPC ((uint16_t)0x44BBU) /*!< low security protection, any value except 0xA5 or 0xCC */ +#define FMC_HSPC ((uint16_t)0x33CCU) /*!< high security protection */ + +/* option bytes software/hardware free watchdog timer */ +#define OB_FWDGT_HW ((uint16_t)0x0100U) /*!< hardware free watchdog timer */ +#define OB_FWDGT_SW ((uint16_t)0x0001U) /*!< software free watchdog timer */ + +/* option bytes reset or not entering deep sleep mode */ +#define OB_DEEPSLEEP_RST ((uint16_t)0x0200U) /*!< generate a reset instead of entering deepsleep mode */ +#define OB_DEEPSLEEP_NRST ((uint16_t)0x0002U) /*!< no reset when entering deepsleep mode */ + +/* option bytes reset or not entering standby mode */ +#define OB_STDBY_RST ((uint16_t)0x0400U) /*!< generate a reset instead of entering standby mode */ +#define OB_STDBY_NRST ((uint16_t)0x0004U) /*!< no reset when entering deepsleep mode */ + +/* option bytes boot from bank0 or bank1 when configured boot from main flash */ +#define OB_BOOT_FROM_BANK1 ((uint16_t)0x0800U) /*!< boot from bank1 or bank0 if bank1 is void, when configured boot from main memory */ +#define OB_BOOT_FROM_BANK0 ((uint16_t)0x0008U) /*!< boot from bank0, when configured boot from main memory */ + +/* option bytes OTA configuration */ +#define OB_BOOT_OTA_ENABLE ((uint16_t)0x1000U) /*!< when configured boot from main memory, if the BB is 0, all data will be copied from bank1 to bank0 and then boot from bank0 */ +#define OB_BOOT_OTA_DISABLE ((uint16_t)0x0010U) /*!< no effect */ + +/* option bytes brownout configuration */ +#define OB_BOR_DISABLE ((uint16_t)0x0080U) /*!< disable brown out */ +#define OB_BOR_ENABLE ((uint16_t)0x8000U) /*!< enable brown out, brownout threshold 2.6V */ + +/* option bytes 1 lock value in FMC_OB1CS register */ +#define OB1CS_OB1_LKVAL(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) +#define OB1CS_OB1_LK OB1CS_OB1_LKVAL((uint16_t)0x33CCU) /*!< option byte1 cannot be modified */ +#define OB1CS_OB1_NOT_LK OB1CS_OB1_LKVAL((uint16_t)0x00FFU) /*!< option byte1 is not locked */ + +/* option bytes 1 shared RAM init mode in FMC_OB1CS register */ +#define OB1CS_EPLOAD(regval) (BIT(15) & ((uint32_t)(regval) << 15)) +#define OB1CS_EPLOAD_NOT_LOAD_EPDATA OB1CS_EPLOAD((uint16_t)0x00U) /*!< shared SRAM is not loaded with valid EEPROM data during FMC reset */ +#define OB1CS_EPLOAD_LOAD_EPDATA OB1CS_EPLOAD((uint16_t)0x01U) /*!< shared SRAM is loaded with valid EEPROM data during FMC reset */ + +/* option bytes 1 EEPROM size in FMC_OB1CS register */ +#define OB1CS_EPSIZE(regval) (BITS(8, 11) & ((uint32_t)(regval) << 8)) +#define OB1CS_EPSIZE_NONE OB1CS_EPSIZE((uint8_t)0x0FU) /*!< no EEPROM */ +#define OB1CS_EPSIZE_4K OB1CS_EPSIZE((uint8_t)0x08U) /*!< 4KB EEPROM, 384K flash or 256K flash */ +#define OB1CS_EPSIZE_2K OB1CS_EPSIZE((uint8_t)0x04U) /*!< 2KB EEPROM, 128K flash */ +#define OB1CS_EPSIZE_1K OB1CS_EPSIZE((uint8_t)0x02U) /*!< 1KB EEPROM, 64K flash */ + +/* option bytes 1 extend flash block allocation in FMC_OB1CS register */ +/* 384K flash or 256K flash */ +#define OB1CS_EFALC(regval) (BITS(4, 7) & ((uint32_t)(regval) << 4)) +#define OB1CS_DF_64K_EF_0K OB1CS_EFALC((uint8_t)0x00U) /*!< data flash size is 64KB, EEPROM backup size is 0KB */ +#define OB1CS_DF_48K_EF_16K OB1CS_EFALC((uint8_t)0x03U) /*!< data flash size is 48KB, EEPROM backup size is 16KB */ +#define OB1CS_DF_32K_EF_32K OB1CS_EFALC((uint8_t)0x04U) /*!< data flash size is 32KB, EEPROM backup size is 32KB */ +#define OB1CS_DF_16K_EF_48K OB1CS_EFALC((uint8_t)0x05U) /*!< data flash size is 16KB, EEPROM backup size is 48KB */ +#define OB1CS_DF_0K_EF_64K OB1CS_EFALC((uint8_t)0x08U) /*!< data flash size is 0KB, EEPROM backup size is 64KB */ +#define OB1CS_DF_EF_INVALID OB1CS_EFALC((uint8_t)0x0FU) /*!< data flash and EEPROM backup are invalid */ +/* 128K flash */ +#define OB1CS_DF_32K_EF_0K OB1CS_EFALC((uint8_t)0x01U) /*!< data flash size is 64KB, EEPROM backup size is 0KB */ +#define OB1CS_DF_8K_EF_24K OB1CS_EFALC((uint8_t)0x06U) /*!< data flash size is 48KB, EEPROM backup size is 16KB */ +#define OB1CS_DF_0K_EF_32K OB1CS_EFALC((uint8_t)0x09U) /*!< data flash size is 32KB, EEPROM backup size is 32KB */ +#define OB1CS_DF_16K_EF_16K OB1CS_EFALC((uint8_t)0x0BU) /*!< data flash size is 16KB, EEPROM backup size is 48KB */ +#define OB1CS_DF_24K_EF_8K OB1CS_EFALC((uint8_t)0x0CU) /*!< data flash size is 0KB, EEPROM backup size is 64KB */ +/* 64K flash */ +#define OB1CS_DF_16K_EF_0K OB1CS_EFALC((uint8_t)0x02U) /*!< data flash size is 64KB, EEPROM backup size is 0KB */ +#define OB1CS_DF_4K_EF_12K OB1CS_EFALC((uint8_t)0x07U) /*!< data flash size is 48KB, EEPROM backup size is 16KB */ +#define OB1CS_DF_0K_EF_16K OB1CS_EFALC((uint8_t)0x0AU) /*!< data flash size is 32KB, EEPROM backup size is 32KB */ +#define OB1CS_DF_8K_EF_8K OB1CS_EFALC((uint8_t)0x0DU) /*!< data flash size is 16KB, EEPROM backup size is 48KB */ +#define OB1CS_DF_12K_EF_4K OB1CS_EFALC((uint8_t)0x0EU) /*!< data flash size is 0KB, EEPROM backup size is 64KB */ + +#define BANK0_BASE_ADDRESS ((uint32_t)0x08000000U) /*!< FMC bank0 base address */ +#define BANK0_SIZE ((uint32_t)0x00040000U) /*!< FMC bank0 size */ +#define BANK1_BASE_ADDRESS ((uint32_t)(BANK0_BASE_ADDRESS + BANK0_SIZE)) /*!< FMC bank1 base address */ +#define OB_WORD_CNT ((uint8_t)0x06U) /*!< word count of option bytes */ +#define OB_DOUBLEWORD_CNT ((uint8_t)0x03U) /*!< double-word count of option bytes */ +#define FMC_TIMEOUT_COUNT ((uint32_t)0x00FF0000U) /*!< count to judge of FMC timeout */ +#define DOUBLEWORD_CNT_IN_ROW ((uint8_t)0x20U) /*!< double-word count in one row data */ +#define CBCMDLEN_OF_ONE_ROW ((uint8_t)0x05U) /*!< CBCMD read length of one row data */ + +/* function declarations */ +/* FMC programming functions */ +/* unlock the main flash operation */ +void fmc_unlock(void); +/* unlock the main flash bank0 operation */ +void fmc_bank0_unlock(void); +/* unlock the main flash bank1 operation */ +void fmc_bank1_unlock(void); +/* lock the main flash operation */ +void fmc_lock(void); +/* lock the main flash bank0 operation */ +void fmc_bank0_lock(void); +/* lock the main flash bank1 operation */ +void fmc_bank1_lock(void); + +/* set the wait state counter value */ +void fmc_wscnt_set(uint8_t wscnt); +/* enable pre-fetch */ +void fmc_prefetch_enable(void); +/* disable pre-fetch */ +void fmc_prefetch_disable(void); +/* enable cache */ +void fmc_cache_enable(void); +/* disable cache */ +void fmc_cache_disable(void); +/* enable cache reset if cache is disabled */ +void fmc_cache_reset_enable(void); +/* disable cache reset */ +void fmc_cache_reset_disable(void); +/* flash goto power-down mode when MCU enters deepsleep mode */ +void fmc_powerdown_mode_set(void); +/* flash goto sleep mode when MCU enters deepsleep mode */ +void fmc_sleep_mode_set(void); +/* configure shared SRAM mode */ +void fmc_sram_mode_config(fmc_sram_mode_enum sram_mode); +/* get shared SRAM mode */ +fmc_sram_mode_enum fmc_sram_mode_get(void); + +/* check whether flash page is blank or not by check blank command */ +fmc_state_enum fmc_blank_check(uint32_t address, uint8_t length); +/* erase main flash page */ +fmc_state_enum fmc_page_erase(uint32_t page_address); +/* erase flash bank0 */ +fmc_state_enum fmc_bank0_mass_erase(void); +/* erase flash bank1 */ +fmc_state_enum fmc_bank1_mass_erase(void); +/* erase the data flash */ +fmc_state_enum fmc_dflash_mass_erase(void); +/* erase whole chip */ +fmc_state_enum fmc_mass_erase(void); + +/* program a double word at the corresponding address in main flash */ +fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data); +/* FMC fast program one row data (32 double-word) starting at the corresponding address */ +fmc_state_enum fmc_fast_program(uint32_t address, uint64_t data[]); +/* program a double word at the corresponding address in OTP */ +fmc_state_enum otp_doubleword_program(uint32_t address, uint64_t data); +/* program a word at the corresponding address in EEPROM */ +fmc_state_enum eeprom_word_program(uint32_t address, uint32_t data); +/* read a word at the corresponding address in EEPROM */ +uint32_t eeprom_word_read(uint32_t address); + +/* FMC option bytes 0 functions */ +/* unlock the option bytes 0 operation */ +void ob_unlock(void); +/* lock the option bytes 0 operation */ +void ob_lock(void); +/* force to reload the option bytes 0 */ +void ob_reset(void); +/* erase the option bytes 0 */ +fmc_state_enum ob_erase(void); +/* enable option bytes 0 write protection */ +fmc_state_enum ob_write_protection_enable(fmc_area_enum wp_area, uint32_t ob_wp); +/* configure security protection */ +fmc_state_enum ob_security_protection_config(uint16_t ob_spc); +/* program the FMC user option bytes 0 */ +fmc_state_enum ob_user_write(uint16_t ob_user); +/* program the FMC data option bytes 0 */ +fmc_state_enum ob_data_program(uint16_t ob_data); +/* get the value of FMC option bytes OB_USER in FMC_OBSTAT register */ +uint8_t ob_user_get(void); +/* get the value of FMC option bytes OB_DATA in FMC_OBSTAT register */ +uint16_t ob_data_get(void); +/* get the value of FMC option bytes BK0WP in FMC_WP0 register */ +uint32_t ob_write_protection_get(void); +/* get the value of FMC option bytes BK1WP in FMC_WP1 register */ +uint8_t ob_bk1_write_protection_get(void); +/* get the value of FMC option bytes DFWP in FMC_WP1 register */ +uint8_t ob_df_write_protection_get(void); +/* get the value of FMC option bytes EPWP in FMC_WP1 register */ +uint8_t ob_ep_write_protection_get(void); +/* get the value of FMC option bytes 0 security protection level (PLEVEL) in FMC_OBSTAT register */ +uint8_t ob_plevel_get(void); + +/* FMC option bytes 1 functions */ +/* configure lock value in option bytes 1 */ +fmc_state_enum ob1_lock_config(uint32_t lk_value); +/* configure the EPLOAD value of option bytes 1 loaded after the system reset */ +fmc_state_enum ob1_epload_config(uint32_t epload); +/* configure option bytes 1 EEPROM parameters */ +fmc_state_enum ob1_eeprom_parameter_config(uint32_t efalc, uint32_t epsize); +/* get data flash size in byte unit */ +uint32_t dflash_size_get(void); +/* get EEPROM backup size in byte unit */ +uint32_t eeprom_backup_size_get(void); +/* get EEPROM size in byte unit */ +uint32_t eeprom_size_get(void); + +/* interrupt & flag functions */ +/* get FMC flag status */ +FlagStatus fmc_flag_get(fmc_flag_enum flag); +/* clear FMC flag status */ +void fmc_flag_clear(fmc_flag_enum flag); +/* enable FMC interrupt */ +void fmc_interrupt_enable(fmc_interrupt_enum interrupt); +/* disable FMC interrupt */ +void fmc_interrupt_disable(fmc_interrupt_enum interrupt); +/* get FMC interrupt flag status */ +FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum int_flag); +/* clear FMC interrupt flag status */ +void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum int_flag); + +#endif /* GD32A50X_FMC_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_fwdgt.h b/gd32a50x/standard_peripheral/include/gd32a50x_fwdgt.h new file mode 100644 index 0000000..33e62e4 --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_fwdgt.h @@ -0,0 +1,123 @@ +/*! + \file gd32fxxx_fwdgt.h + \brief definitions for the FWDGT + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32A50X_FWDGT_H +#define GD32A50X_FWDGT_H + +#include "gd32a50x.h" + +/* FWDGT definitions */ +#define FWDGT FWDGT_BASE /*!< FWDGT base address */ + +/* registers definitions */ +#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */ +#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */ +#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */ +#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */ +#define FWDGT_WND REG32((FWDGT) + 0x00000010U) /*!< FWDGT window register */ + +/* bits definitions */ +/* FWDGT_CTL */ +#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ + +/* FWDGT_PSC */ +#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ + +/* FWDGT_RLD */ +#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ + +/* FWDGT_STAT */ +#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ +#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ +#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */ + +/* FWDGT_WND */ +#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */ + +/* constants definitions */ +/* FWDGT_PSC register value */ +#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U)) +#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ +#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ +#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ +#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ +#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ +#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ +#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ + +/* control value */ +#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ +#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ +#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ +#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ + +/* FWDGT timeout value */ +#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */ +#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ +#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ + +/* FWDGT flag definitions */ +#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */ +#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */ +#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */ + +/* write value to FWDGT_RLD_RLD bit field */ +#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_RLD_RLD bit field */ +/* write value to FWDGT_WND_WND bit field */ +#define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_WND_WND bit field */ + +/* function declarations */ +/* enable write access to FWDGT_PSC, FWDGT_RLD and FWDGT_WND */ +void fwdgt_write_enable(void); +/* disable write access to FWDGT_PSC, FWDGT_RLD and FWDGT_WND */ +void fwdgt_write_disable(void); +/* start the FWDGT counter */ +void fwdgt_enable(void); + +/* configure the FWDGT counter prescaler value */ +ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value); +/* configure the FWDGT counter reload value */ +ErrStatus fwdgt_reload_value_config(uint16_t reload_value); +/* configure the FWDGT counter window value */ +ErrStatus fwdgt_window_value_config(uint16_t window_value); +/* reload the counter of FWDGT */ +void fwdgt_counter_reload(void); +/* configure counter reload value, and prescaler divider value */ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); + +/* get flag state of FWDGT */ +FlagStatus fwdgt_flag_get(uint16_t flag); + +#endif /* GD32A50X_FWDGT_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_gpio.h b/gd32a50x/standard_peripheral/include/gd32a50x_gpio.h new file mode 100644 index 0000000..079559d --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_gpio.h @@ -0,0 +1,390 @@ +/*! + \file gd32a50x_gpio.h + \brief definitions for the GPIO + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_GPIO_H +#define GD32A50X_GPIO_H + +#include "gd32a50x.h" + +/* GPIOx(x=A,B,C,D,E,F) definitions */ +#define GPIOA (GPIO_BASE + 0x00000000U) /*!< GPIOA bsae address */ +#define GPIOB (GPIO_BASE + 0x00000400U) /*!< GPIOB bsae address */ +#define GPIOC (GPIO_BASE + 0x00000800U) /*!< GPIOC bsae address */ +#define GPIOD (GPIO_BASE + 0x00000C00U) /*!< GPIOD bsae address */ +#define GPIOE (GPIO_BASE + 0x00001000U) /*!< GPIOE bsae address */ +#define GPIOF (GPIO_BASE + 0x00001400U) /*!< GPIOF bsae address */ + +/* registers definitions */ +#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00000000U) /*!< GPIO port control register */ +#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x00000004U) /*!< GPIO port output mode register */ +#define GPIO_OSPD(gpiox) REG32((gpiox) + 0x00000008U) /*!< GPIO port output speed register */ +#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0000000CU) /*!< GPIO port pull-up/pull-down register */ +#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x00000010U) /*!< GPIO port input status register */ +#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x00000014U) /*!< GPIO port output control register */ +#define GPIO_BOP(gpiox) REG32((gpiox) + 0x00000018U) /*!< GPIO port bit operation register */ +#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x0000001CU) /*!< GPIO port configuration lock register */ +#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x00000020U) /*!< GPIO alternate function selected register 0 */ +#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x00000024U) /*!< GPIO alternate function selected register 1 */ +#define GPIO_BC(gpiox) REG32((gpiox) + 0x00000028U) /*!< GPIO bit clear register */ +#define GPIO_TG(gpiox) REG32((gpiox) + 0x0000002CU) /*!< GPIO port bit toggle register */ + +/* bits definitions */ +/* GPIO_CTL */ +#define GPIO_CTL_CTL0 BITS(0, 1) /*!< pin 0 configuration bits */ +#define GPIO_CTL_CTL1 BITS(2, 3) /*!< pin 1 configuration bits */ +#define GPIO_CTL_CTL2 BITS(4, 5) /*!< pin 2 configuration bits */ +#define GPIO_CTL_CTL3 BITS(6, 7) /*!< pin 3 configuration bits */ +#define GPIO_CTL_CTL4 BITS(8, 9) /*!< pin 4 configuration bits */ +#define GPIO_CTL_CTL5 BITS(10, 11) /*!< pin 5 configuration bits */ +#define GPIO_CTL_CTL6 BITS(12, 13) /*!< pin 6 configuration bits */ +#define GPIO_CTL_CTL7 BITS(14, 15) /*!< pin 7 configuration bits */ +#define GPIO_CTL_CTL8 BITS(16, 17) /*!< pin 8 configuration bits */ +#define GPIO_CTL_CTL9 BITS(18, 19) /*!< pin 9 configuration bits */ +#define GPIO_CTL_CTL10 BITS(20, 21) /*!< pin 10 configuration bits */ +#define GPIO_CTL_CTL11 BITS(22, 23) /*!< pin 11 configuration bits */ +#define GPIO_CTL_CTL12 BITS(24, 25) /*!< pin 12 configuration bits */ +#define GPIO_CTL_CTL13 BITS(26, 27) /*!< pin 13 configuration bits */ +#define GPIO_CTL_CTL14 BITS(28, 29) /*!< pin 14 configuration bits */ +#define GPIO_CTL_CTL15 BITS(30, 31) /*!< pin 15 configuration bits */ + +/* GPIO_OMODE */ +#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */ +#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */ +#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */ +#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */ +#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */ +#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */ +#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */ +#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */ +#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */ +#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */ +#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */ +#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */ +#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */ +#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */ +#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */ +#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */ + +/* GPIO_OSPD */ +#define GPIO_OSPD_OSPD0 BITS(0, 1) /*!< pin 0 output max speed bits */ +#define GPIO_OSPD_OSPD1 BITS(2, 3) /*!< pin 1 output max speed bits */ +#define GPIO_OSPD_OSPD2 BITS(4, 5) /*!< pin 2 output max speed bits */ +#define GPIO_OSPD_OSPD3 BITS(6, 7) /*!< pin 3 output max speed bits */ +#define GPIO_OSPD_OSPD4 BITS(8, 9) /*!< pin 4 output max speed bits */ +#define GPIO_OSPD_OSPD5 BITS(10, 11) /*!< pin 5 output max speed bits */ +#define GPIO_OSPD_OSPD6 BITS(12, 13) /*!< pin 6 output max speed bits */ +#define GPIO_OSPD_OSPD7 BITS(14, 15) /*!< pin 7 output max speed bits */ +#define GPIO_OSPD_OSPD8 BITS(16, 17) /*!< pin 8 output max speed bits */ +#define GPIO_OSPD_OSPD9 BITS(18, 19) /*!< pin 9 output max speed bits */ +#define GPIO_OSPD_OSPD10 BITS(20, 21) /*!< pin 10 output max speed bits */ +#define GPIO_OSPD_OSPD11 BITS(22, 23) /*!< pin 11 output max speed bits */ +#define GPIO_OSPD_OSPD12 BITS(24, 25) /*!< pin 12 output max speed bits */ +#define GPIO_OSPD_OSPD13 BITS(26, 27) /*!< pin 13 output max speed bits */ +#define GPIO_OSPD_OSPD14 BITS(28, 29) /*!< pin 14 output max speed bits */ +#define GPIO_OSPD_OSPD15 BITS(30, 31) /*!< pin 15 output max speed bits */ + +/* GPIO_PUD */ +#define GPIO_PUD_PUD0 BITS(0, 1) /*!< pin 0 pull-up or pull-down bits */ +#define GPIO_PUD_PUD1 BITS(2, 3) /*!< pin 1 pull-up or pull-down bits */ +#define GPIO_PUD_PUD2 BITS(4, 5) /*!< pin 2 pull-up or pull-down bits */ +#define GPIO_PUD_PUD3 BITS(6, 7) /*!< pin 3 pull-up or pull-down bits */ +#define GPIO_PUD_PUD4 BITS(8, 9) /*!< pin 4 pull-up or pull-down bits */ +#define GPIO_PUD_PUD5 BITS(10, 11) /*!< pin 5 pull-up or pull-down bits */ +#define GPIO_PUD_PUD6 BITS(12, 13) /*!< pin 6 pull-up or pull-down bits */ +#define GPIO_PUD_PUD7 BITS(14, 15) /*!< pin 7 pull-up or pull-down bits */ +#define GPIO_PUD_PUD8 BITS(16, 17) /*!< pin 8 pull-up or pull-down bits */ +#define GPIO_PUD_PUD9 BITS(18, 19) /*!< pin 9 pull-up or pull-down bits */ +#define GPIO_PUD_PUD10 BITS(20, 21) /*!< pin 10 pull-up or pull-down bits */ +#define GPIO_PUD_PUD11 BITS(22, 23) /*!< pin 11 pull-up or pull-down bits */ +#define GPIO_PUD_PUD12 BITS(24, 25) /*!< pin 12 pull-up or pull-down bits */ +#define GPIO_PUD_PUD13 BITS(26, 27) /*!< pin 13 pull-up or pull-down bits */ +#define GPIO_PUD_PUD14 BITS(28, 29) /*!< pin 14 pull-up or pull-down bits */ +#define GPIO_PUD_PUD15 BITS(30, 31) /*!< pin 15 pull-up or pull-down bits */ + +/* GPIO_ISTAT */ +#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ +#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ +#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ +#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ +#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ +#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ +#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ +#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ +#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ +#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ +#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ +#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ +#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ +#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ +#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ +#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ + +/* GPIO_OCTL */ +#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ +#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ +#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ +#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ +#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ +#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ +#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ +#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ +#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ +#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ +#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ +#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ +#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ +#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ +#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ +#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ + +/* GPIO_BOP */ +#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ +#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ +#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ +#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ +#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ +#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ +#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ +#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ +#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ +#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ +#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ +#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ +#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ +#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ +#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ +#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ +#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ +#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ +#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ +#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ +#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ +#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ +#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ +#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ +#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ +#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ +#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ +#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ +#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ +#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ +#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ +#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ + +/* GPIO_LOCK */ +#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ +#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ +#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ +#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ +#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ +#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ +#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ +#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ +#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ +#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ +#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ +#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ +#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ +#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ +#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ +#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ +#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ + +/* GPIO_AFSEL0 */ +#define GPIO_AFSEL0_SEL0 BITS(0, 3) /*!< pin 0 alternate function selected */ +#define GPIO_AFSEL0_SEL1 BITS(4, 7) /*!< pin 1 alternate function selected */ +#define GPIO_AFSEL0_SEL2 BITS(8, 11) /*!< pin 2 alternate function selected */ +#define GPIO_AFSEL0_SEL3 BITS(12, 15) /*!< pin 3 alternate function selected */ +#define GPIO_AFSEL0_SEL4 BITS(16, 19) /*!< pin 4 alternate function selected */ +#define GPIO_AFSEL0_SEL5 BITS(20, 23) /*!< pin 5 alternate function selected */ +#define GPIO_AFSEL0_SEL6 BITS(24, 27) /*!< pin 6 alternate function selected */ +#define GPIO_AFSEL0_SEL7 BITS(28, 31) /*!< pin 7 alternate function selected */ + +/* GPIO_AFSEL1 */ +#define GPIO_AFSEL1_SEL8 BITS(0, 3) /*!< pin 8 alternate function selected */ +#define GPIO_AFSEL1_SEL9 BITS(4, 7) /*!< pin 9 alternate function selected */ +#define GPIO_AFSEL1_SEL10 BITS(8, 11) /*!< pin 10 alternate function selected */ +#define GPIO_AFSEL1_SEL11 BITS(12, 15) /*!< pin 11 alternate function selected */ +#define GPIO_AFSEL1_SEL12 BITS(16, 19) /*!< pin 12 alternate function selected */ +#define GPIO_AFSEL1_SEL13 BITS(20, 23) /*!< pin 13 alternate function selected */ +#define GPIO_AFSEL1_SEL14 BITS(24, 27) /*!< pin 14 alternate function selected */ +#define GPIO_AFSEL1_SEL15 BITS(28, 31) /*!< pin 15 alternate function selected */ + +/* GPIO_BC */ +#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ +#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ +#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ +#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ +#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ +#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ +#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ +#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ +#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ +#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ +#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ +#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ +#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ +#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ +#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ +#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ + +/* GPIO_TG */ +#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */ +#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */ +#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */ +#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */ +#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */ +#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */ +#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */ +#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */ +#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */ +#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */ +#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */ +#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */ +#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */ +#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */ +#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */ +#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */ + +/* constants definitions */ +typedef FlagStatus bit_status; + +/* output mode definitions */ +#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */ +#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */ +#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */ +#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */ + +/* pull-up/pull-down definitions */ +#define PUD_PUPD(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0)) +#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */ +#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */ +#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */ + +/* GPIO pin definitions */ +#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ +#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ +#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ +#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ +#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ +#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ +#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ +#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ +#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ +#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ +#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ +#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ +#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ +#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ +#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ +#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +#define GPIO_PIN_ALL BITS(0, 15) /*!< GPIO pin all */ + +/* GPIO mode configuration values */ +#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n)))) +#define GPIO_MODE_MASK(n) ((uint32_t)((uint32_t)0x3U << (2U * (n)))) + +/* GPIO pull-up/pull-down values */ +#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n)))) +#define GPIO_PUPD_MASK(n) ((uint32_t)((uint32_t)(0x3U) << (2U * (n)))) + +/* GPIO output speed values */ +#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n)))) +#define GPIO_OSPEED_MASK(n) ((uint32_t)((uint32_t)(0x3U) << (2U * (n)))) + +/* GPIO output type */ +#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */ +#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */ + +/* GPIO output max speed value */ +#define OSPD_OSPD0(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0)) +#define GPIO_OSPEED_2MHZ OSPD_OSPD0(0) /*!< output max speed 2MHz */ +#define GPIO_OSPEED_10MHZ OSPD_OSPD0(1) /*!< output max speed 10MHz */ +#define GPIO_OSPEED_50MHZ OSPD_OSPD0(3) /*!< output max speed 50MHz */ + +/* GPIO alternate function values */ +#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n)))) +#define GPIO_AFR_MASK(n) ((uint32_t)((uint32_t)(0xFU) << (4U * (n)))) + +/* GPIO alternate function */ +#define AF(regval) (BITS(0, 3) & ((uint32_t)(regval) << 0)) +#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */ +#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */ +#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */ +#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */ +#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected */ +#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected */ +#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected */ +#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected */ +#define GPIO_AF_8 AF(8) /*!< alternate function 8 selected */ +#define GPIO_AF_9 AF(9) /*!< alternate function 9 selected */ + +/* function declarations */ +/* reset GPIO port */ +void gpio_deinit(uint32_t gpio_periph); +/* set GPIO mode */ +void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin); +/* set GPIO output type and speed */ +void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin); + +/* set GPIO pin bit */ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); +/* reset GPIO pin bit */ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); +/* write data to the specified GPIO pin */ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); +/* write data to the specified GPIO port */ +void gpio_port_write(uint32_t gpio_periph, uint16_t data); + +/* get GPIO pin input status */ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port input status */ +uint16_t gpio_input_port_get(uint32_t gpio_periph); +/* get GPIO pin output status */ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port output status */ +uint16_t gpio_output_port_get(uint32_t gpio_periph); + +/* set GPIO alternate function */ +void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin); +/* lock GPIO pin bit */ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); + +/* toggle GPIO pin status */ +void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin); +/* toggle GPIO port status */ +void gpio_port_toggle(uint32_t gpio_periph); + +#endif /* GD32A50X_GPIO_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_i2c.h b/gd32a50x/standard_peripheral/include/gd32a50x_i2c.h new file mode 100644 index 0000000..966399c --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_i2c.h @@ -0,0 +1,406 @@ +/*! + \file gd32a50x_i2c.h + \brief definitions for the I2C + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_I2C_H +#define GD32A50X_I2C_H + +#include "gd32a50x.h" + +/* I2Cx(x=0,1) definitions */ +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE+0x00000400U) /*!< I2C1 base address */ + +/* registers definitions */ +#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */ +#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0*/ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1*/ +#define I2C_TIMING(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C timing register */ +#define I2C_TIMEOUT(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C timeout register */ +#define I2C_STAT(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C status register */ +#define I2C_STATC(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C status clear register */ +#define I2C_PEC(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C PEC register */ +#define I2C_RDATA(i2cx) REG32((i2cx) + 0x00000024U) /*!< I2C receive data register */ +#define I2C_TDATA(i2cx) REG32((i2cx) + 0x00000028U) /*!< I2C transmit data register */ +#define I2C_CTL2(i2cx) REG32((i2cx) + 0x00000090U) /*!< I2C control register 2 */ + +/* bits definitions */ +/* I2Cx_CTL0 */ +#define I2C_CTL0_I2CEN BIT(0) /*!< I2C peripheral enable */ +#define I2C_CTL0_TIE BIT(1) /*!< transmit interrupt enable */ +#define I2C_CTL0_RBNEIE BIT(2) /*!< receive interrupt enable */ +#define I2C_CTL0_ADDMIE BIT(3) /*!< address match interrupt enable in slave mode */ +#define I2C_CTL0_NACKIE BIT(4) /*!< not acknowledge received interrupt enable */ +#define I2C_CTL0_STPDETIE BIT(5) /*!< stop detection interrupt enable */ +#define I2C_CTL0_TCIE BIT(6) /*!< transfer complete interrupt enable */ +#define I2C_CTL0_ERRIE BIT(7) /*!< error interrupt enable */ +#define I2C_CTL0_DNF BITS(8,11) /*!< digital noise filter */ +#define I2C_CTL0_ANOFF BIT(12) /*!< analog noise filter */ +#define I2C_CTL0_DENT BIT(14) /*!< DMA enable for transmission */ +#define I2C_CTL0_DENR BIT(15) /*!< DMA enable for reception */ +#define I2C_CTL0_SBCTL BIT(16) /*!< slave byte control */ +#define I2C_CTL0_SS BIT(17) /*!< whether to stretch SCL low when data is not ready in slave mode */ +#define I2C_CTL0_GCEN BIT(19) /*!< whether or not to response to a general call (0x00) */ +#define I2C_CTL0_SMBHAEN BIT(20) /*!< SMBus host address enable */ +#define I2C_CTL0_SMBDAEN BIT(21) /*!< SMBus device default address enable */ +#define I2C_CTL0_SMBALTEN BIT(22) /*!< SMBus alert enable */ +#define I2C_CTL0_PECEN BIT(23) /*!< PEC calculation switch */ + +/* I2Cx_CTL1 */ +#define I2C_CTL1_SADDRESS BITS(0,9) /*!< received slave address */ +#define I2C_CTL1_TRDIR BIT(10) /*!< transfer direction in master mode */ +#define I2C_CTL1_ADD10EN BIT(11) /*!< 10-bit addressing mode enable in master mode */ +#define I2C_CTL1_HEAD10R BIT(12) /*!< 10-bit address header executes read direction only in master receive mode */ +#define I2C_CTL1_START BIT(13) /*!< generate a START condition on I2C bus */ +#define I2C_CTL1_STOP BIT(14) /*!< generate a STOP condition on I2C bus */ +#define I2C_CTL1_NACKEN BIT(15) /*!< generate NACK in slave mode */ +#define I2C_CTL1_BYTENUM BITS(16,23) /*!< number of bytes to be transferred */ +#define I2C_CTL1_RELOAD BIT(24) /*!< reload mode enable */ +#define I2C_CTL1_AUTOEND BIT(25) /*!< automatic end mode in master mode */ +#define I2C_CTL1_PECTRANS BIT(26) /*!< PEC transfer */ + +/* I2Cx_SADDR0 */ +#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ +#define I2C_SADDR0_ADDFORMAT BIT(10) /*!< address mode for the I2C slave */ +#define I2C_SADDR0_ADDRESSEN BIT(15) /*!< I2C address enable */ + +/* I2Cx_SADDR1 */ +#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave */ +#define I2C_SADDR1_ADDMSK2 BITS(8,10) /*!< ADDRESS2[7:1] mask */ +#define I2C_SADDR1_ADDRESS2EN BIT(15) /*!< second I2C address enable */ + +/* I2Cx_TIMING */ +#define I2C_TIMING_SCLL BITS(0,7) /*!< SCL low period */ +#define I2C_TIMING_SCLH BITS(8,15) /*!< SCL high period */ +#define I2C_TIMING_SDADELY BITS(16,19) /*!< data hold time */ +#define I2C_TIMING_SCLDELY BITS(20,23) /*!< data setup time */ +#define I2C_TIMING_PSC BITS(28,31) /*!< timing prescaler */ + +/* I2Cx_TIMEOUT */ +#define I2C_TIMEOUT_BUSTOA BITS(0,11) /*!< bus timeout A */ +#define I2C_TIMEOUT_TOIDLE BIT(12) /*!< idle clock timeout detection */ +#define I2C_TIMEOUT_TOEN BIT(15) /*!< clock timeout detection enable */ +#define I2C_TIMEOUT_BUSTOB BITS(16,27) /*!< bus timeout B */ +#define I2C_TIMEOUT_EXTOEN BIT(31) /*!< extended clock timeout detection enable */ + +/* I2Cx_STAT */ +#define I2C_STAT_TBE BIT(0) /*!< I2C_TDATA is empty during transmitting */ +#define I2C_STAT_TI BIT(1) /*!< transmit interrupt */ +#define I2C_STAT_RBNE BIT(2) /*!< I2C_RDATA is not empty during receiving */ +#define I2C_STAT_ADDSEND BIT(3) /*!< address received matches in slave mode */ +#define I2C_STAT_NACK BIT(4) /*!< not acknowledge flag */ +#define I2C_STAT_STPDET BIT(5) /*!< STOP condition detected in slave mode */ +#define I2C_STAT_TC BIT(6) /*!< transfer complete in master mode */ +#define I2C_STAT_TCR BIT(7) /*!< transfer complete reload */ +#define I2C_STAT_BERR BIT(8) /*!< bus error */ +#define I2C_STAT_LOSTARB BIT(9) /*!< arbitration lost */ +#define I2C_STAT_OUERR BIT(10) /*!< overrun/underrun error in slave mode */ +#define I2C_STAT_PECERR BIT(11) /*!< PEC error */ +#define I2C_STAT_TIMEOUT BIT(12) /*!< timeout flag */ +#define I2C_STAT_SMBALT BIT(13) /*!< SMBus Alert */ +#define I2C_STAT_I2CBSY BIT(15) /*!< busy flag */ +#define I2C_STAT_TR BIT(16) /*!< whether the I2C is a transmitter or a receiver in slave mode */ +#define I2C_STAT_READDR BITS(17,23) /*!< received match address in slave mode */ + +/* I2Cx_STATC */ +#define I2C_STATC_ADDSENDC BIT(3) /*!< ADDSEND flag clear */ +#define I2C_STATC_NACKC BIT(4) /*!< not acknowledge flag clear */ +#define I2C_STATC_STPDETC BIT(5) /*!< STPDET flag clear */ +#define I2C_STATC_BERRC BIT(8) /*!< bus error flag clear */ +#define I2C_STATC_LOSTARBC BIT(9) /*!< arbitration Lost flag clear */ +#define I2C_STATC_OUERRC BIT(10) /*!< overrun/underrun flag clear */ +#define I2C_STATC_PECERRC BIT(11) /*!< PEC error flag clear */ +#define I2C_STATC_TIMEOUTC BIT(12) /*!< TIMEOUT flag clear */ +#define I2C_STATC_SMBALTC BIT(13) /*!< SMBus Alert flag clear */ + +/* I2Cx_PEC */ +#define I2C_PEC_PECV BITS(0,7) /*!< Packet Error Checking Value that calculated by hardware when PEC is enabled */ + +/* I2Cx_RDATA */ +#define I2C_RDATA_RDATA BITS(0,7) /*!< receive data value */ + +/* I2Cx_TDATA */ +#define I2C_TDATA_TDATA BITS(0,7) /*!< transmit data value */ + +/* I2Cx_CTL2 */ +#define I2C_CTL2_ADDM BITS(9,15) /*!< address bit compare select */ + +/* constants definitions */ +/* define the I2C bit position and its register index offset */ +#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) +#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) +#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) +#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) + +/* register offset */ +#define I2C_CTL0_REG_OFFSET ((uint32_t)0x00000000U) /*!< CTL0 register offset */ +#define I2C_STAT_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT register offset */ + +/* I2C interrupt flags */ +typedef enum { + I2C_INT_FLAG_TI = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 1U, I2C_STAT_REG_OFFSET, 1U), /*!< transmit interrupt flag */ + I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 2U, I2C_STAT_REG_OFFSET, 2U), /*!< I2C_RDATA is not empty during receiving interrupt flag */ + I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 3U, I2C_STAT_REG_OFFSET, 3U), /*!< address received matches in slave mode interrupt flag */ + I2C_INT_FLAG_NACK = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 4U, I2C_STAT_REG_OFFSET, 4U), /*!< not acknowledge interrupt flag */ + I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 5U, I2C_STAT_REG_OFFSET, 5U), /*!< stop condition detected in slave mode interrupt flag */ + I2C_INT_FLAG_TC = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 6U, I2C_STAT_REG_OFFSET, 6U), /*!< transfer complete in master mode interrupt flag */ + I2C_INT_FLAG_TCR = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 6U, I2C_STAT_REG_OFFSET, 7U), /*!< transfer complete reload interrupt flag */ + I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 8U), /*!< bus error interrupt flag */ + I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 9U), /*!< arbitration lost interrupt flag */ + I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 10U), /*!< overrun/underrun error in slave mode interrupt flag */ + I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 11U), /*!< PEC error interrupt flag */ + I2C_INT_FLAG_TIMEOUT = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 12U), /*!< timeout interrupt flag */ + I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 13U) /*!< SMBus Alert interrupt flag */ +} i2c_interrupt_flag_enum; + +/* I2C DMA constants definitions */ +#define I2C_DMA_TRANSMIT ((uint32_t)0x00000000U) /*!< I2C transmit data use DMA */ +#define I2C_DMA_RECEIVE ((uint32_t)0x00000001U) /*!< I2C receive data use DMA */ + +/* I2C interrupt enable or disable */ +#define I2C_INT_ERR I2C_CTL0_ERRIE /*!< error interrupt enable */ +#define I2C_INT_TC I2C_CTL0_TCIE /*!< transfer complete interrupt enable */ +#define I2C_INT_STPDET I2C_CTL0_STPDETIE /*!< stop detection interrupt enable */ +#define I2C_INT_NACK I2C_CTL0_NACKIE /*!< not acknowledge received interrupt enable */ +#define I2C_INT_ADDM I2C_CTL0_ADDMIE /*!< address match interrupt enable */ +#define I2C_INT_RBNE I2C_CTL0_RBNEIE /*!< receive interrupt enable */ +#define I2C_INT_TI I2C_CTL0_TIE /*!< transmit interrupt enable */ + +/* I2C transfer direction in master mode */ +#define I2C_MASTER_TRANSMIT ((uint32_t)0x00000000U) /*!< I2C master transmit */ +#define I2C_MASTER_RECEIVE I2C_CTL1_TRDIR /*!< I2C master receive */ + +/* address mode for the I2C slave */ +#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ +#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ + +/* the length of filter spikes */ +#define FILTER_DISABLE ((uint32_t)0x00000000U) /*!< digital filter is disabled */ +#define FILTER_LENGTH_1 ((uint32_t)0x00000001U) /*!< digital filter is enabled and filter spikes with a length of up to 1 tI2CCLK */ +#define FILTER_LENGTH_2 ((uint32_t)0x00000002U) /*!< digital filter is enabled and filter spikes with a length of up to 2 tI2CCLK */ +#define FILTER_LENGTH_3 ((uint32_t)0x00000003U) /*!< digital filter is enabled and filter spikes with a length of up to 3 tI2CCLK */ +#define FILTER_LENGTH_4 ((uint32_t)0x00000004U) /*!< digital filter is enabled and filter spikes with a length of up to 4 tI2CCLK */ +#define FILTER_LENGTH_5 ((uint32_t)0x00000005U) /*!< digital filter is enabled and filter spikes with a length of up to 5 tI2CCLK */ +#define FILTER_LENGTH_6 ((uint32_t)0x00000006U) /*!< digital filter is enabled and filter spikes with a length of up to 6 tI2CCLK */ +#define FILTER_LENGTH_7 ((uint32_t)0x00000007U) /*!< digital filter is enabled and filter spikes with a length of up to 7 tI2CCLK */ +#define FILTER_LENGTH_8 ((uint32_t)0x00000008U) /*!< digital filter is enabled and filter spikes with a length of up to 8 tI2CCLK */ +#define FILTER_LENGTH_9 ((uint32_t)0x00000009U) /*!< digital filter is enabled and filter spikes with a length of up to 9 tI2CCLK */ +#define FILTER_LENGTH_10 ((uint32_t)0x0000000AU) /*!< digital filter is enabled and filter spikes with a length of up to 10 tI2CCLK */ +#define FILTER_LENGTH_11 ((uint32_t)0x0000000BU) /*!< digital filter is enabled and filter spikes with a length of up to 11 tI2CCLK */ +#define FILTER_LENGTH_12 ((uint32_t)0x0000000CU) /*!< digital filter is enabled and filter spikes with a length of up to 12 tI2CCLK */ +#define FILTER_LENGTH_13 ((uint32_t)0x0000000DU) /*!< digital filter is enabled and filter spikes with a length of up to 13 tI2CCLK */ +#define FILTER_LENGTH_14 ((uint32_t)0x0000000EU) /*!< digital filter is enabled and filter spikes with a length of up to 14 tI2CCLK */ +#define FILTER_LENGTH_15 ((uint32_t)0x0000000FU) /*!< digital filter is enabled and filter spikes with a length of up to 15 tI2CCLK */ + +/* defines which bits of register ADDRESS[7:1] are compared with an incoming address byte */ +#define ADDRESS_BIT1_COMPARE ((uint32_t)0x00000200U) /*!< address bit1 needs compare */ +#define ADDRESS_BIT2_COMPARE ((uint32_t)0x00000400U) /*!< address bit2 needs compare */ +#define ADDRESS_BIT3_COMPARE ((uint32_t)0x00000800U) /*!< address bit3 needs compare */ +#define ADDRESS_BIT4_COMPARE ((uint32_t)0x00001000U) /*!< address bit4 needs compare */ +#define ADDRESS_BIT5_COMPARE ((uint32_t)0x00002000U) /*!< address bit5 needs compare */ +#define ADDRESS_BIT6_COMPARE ((uint32_t)0x00004000U) /*!< address bit6 needs compare */ +#define ADDRESS_BIT7_COMPARE ((uint32_t)0x00008000U) /*!< address bit7 needs compare */ + +/* defines which bits of ADDRESS2[7:1] are compared with an incoming address byte, and which bits are masked (don't care) */ +#define ADDRESS2_NO_MASK ((uint32_t)0x00000000U) /*!< no mask, all the bits must be compared */ +#define ADDRESS2_MASK_BIT1 ((uint32_t)0x00000001U) /*!< ADDRESS2[1] is masked, only ADDRESS2[7:2] are compared */ +#define ADDRESS2_MASK_BIT1_2 ((uint32_t)0x00000002U) /*!< ADDRESS2[2:1] is masked, only ADDRESS2[7:3] are compared */ +#define ADDRESS2_MASK_BIT1_3 ((uint32_t)0x00000003U) /*!< ADDRESS2[3:1] is masked, only ADDRESS2[7:4] are compared */ +#define ADDRESS2_MASK_BIT1_4 ((uint32_t)0x00000004U) /*!< ADDRESS2[4:1] is masked, only ADDRESS2[7:5] are compared */ +#define ADDRESS2_MASK_BIT1_5 ((uint32_t)0x00000005U) /*!< ADDRESS2[5:1] is masked, only ADDRESS2[7:6] are compared */ +#define ADDRESS2_MASK_BIT1_6 ((uint32_t)0x00000006U) /*!< ADDRESS2[6:1] is masked, only ADDRESS2[7] are compared */ +#define ADDRESS2_MASK_ALL ((uint32_t)0x00000007U) /*!< all the ADDRESS2[7:1] bits are masked */ + +/* idle clock timeout detection */ +#define BUSTOA_DETECT_SCL_LOW ((uint32_t)0x00000000U) /*!< BUSTOA is used to detect SCL low timeout */ +#define BUSTOA_DETECT_IDLE I2C_TIMEOUT_TOIDLE /*!< BUSTOA is used to detect both SCL and SDA high timeout when the bus is idle */ + +/* I2C flag definitions */ +#define I2C_FLAG_TBE I2C_STAT_TBE /*!< I2C_TDATA is empty during transmitting */ +#define I2C_FLAG_TI I2C_STAT_TI /*!< transmit interrupt */ +#define I2C_FLAG_RBNE I2C_STAT_RBNE /*!< I2C_RDATA is not empty during receiving */ +#define I2C_FLAG_ADDSEND I2C_STAT_ADDSEND /*!< address received matches in slave mode */ +#define I2C_FLAG_NACK I2C_STAT_NACK /*!< not acknowledge flag */ +#define I2C_FLAG_STPDET I2C_STAT_STPDET /*!< STOP condition detected in slave mode */ +#define I2C_FLAG_TC I2C_STAT_TC /*!< transfer complete in master mode */ +#define I2C_FLAG_TCR I2C_STAT_TCR /*!< transfer complete reload */ +#define I2C_FLAG_BERR I2C_STAT_BERR /*!< bus error */ +#define I2C_FLAG_LOSTARB I2C_STAT_LOSTARB /*!< arbitration lost */ +#define I2C_FLAG_OUERR I2C_STAT_OUERR /*!< overrun/underrun error in slave mode */ +#define I2C_FLAG_PECERR I2C_STAT_PECERR /*!< PEC error */ +#define I2C_FLAG_TIMEOUT I2C_STAT_TIMEOUT /*!< timeout flag */ +#define I2C_FLAG_SMBALT I2C_STAT_SMBALT /*!< SMBus Alert */ +#define I2C_FLAG_I2CBSY I2C_STAT_I2CBSY /*!< busy flag */ +#define I2C_FLAG_TR I2C_STAT_TR /*!< whether the I2C is a transmitter or a receiver in slave mode */ + +#define I2CCLK_MAX ((uint32_t)0x0000003FU)/*!< i2cclk maximum value */ +#define I2CCLK_MIN ((uint32_t)0x00000002U)/*!< i2cclk minimum value for standard mode */ +#define I2CCLK_FM_MIN ((uint32_t)0x00000008U)/*!< i2cclk minimum value for fast mode */ +#define I2CCLK_FM_PLUS_MIN ((uint32_t)0x00000018U)/*!< i2cclk minimum value for fast mode plus */ + +/* function declarations */ +/* initialization functions */ +/* reset I2C */ +void i2c_deinit(uint32_t i2c_periph); +/* configure the timing parameters */ +void i2c_timing_config(uint32_t i2c_periph, uint32_t psc, uint32_t scl_dely, uint32_t sda_dely); +/* configure digital noise filter */ +void i2c_digital_noise_filter_config(uint32_t i2c_periph, uint32_t filter_length); +/* enable analog noise filter */ +void i2c_analog_noise_filter_enable(uint32_t i2c_periph); +/* disable analog noise filter */ +void i2c_analog_noise_filter_disable(uint32_t i2c_periph); +/* configure the SCL high and low period of clock in master mode */ +void i2c_master_clock_config(uint32_t i2c_periph, uint32_t sclh, uint32_t scll); +/* configure i2c slave address and transfer direction in master mode */ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t address, uint32_t trans_direction); + +/* application function declarations */ +/* 10-bit address header executes read direction only in master receive mode */ +void i2c_address10_header_enable(uint32_t i2c_periph); +/* 10-bit address header executes complete sequence in master receive mode */ +void i2c_address10_header_disable(uint32_t i2c_periph); +/* enable 10-bit addressing mode in master mode */ +void i2c_address10_enable(uint32_t i2c_periph); +/* disable 10-bit addressing mode in master mode */ +void i2c_address10_disable(uint32_t i2c_periph); +/* enable I2C automatic end mode in master mode */ +void i2c_automatic_end_enable(uint32_t i2c_periph); +/* disable I2C automatic end mode in master mode */ +void i2c_automatic_end_disable(uint32_t i2c_periph); +/* enable the response to a general call */ +void i2c_slave_response_to_gcall_enable(uint32_t i2c_periph); +/* disable the response to a general call */ +void i2c_slave_response_to_gcall_disable(uint32_t i2c_periph); +/* enable to stretch SCL low when data is not ready in slave mode */ +void i2c_stretch_scl_low_enable(uint32_t i2c_periph); +/* disable to stretch SCL low when data is not ready in slave mode */ +void i2c_stretch_scl_low_disable(uint32_t i2c_periph); +/* configure i2c slave address */ +void i2c_address_config(uint32_t i2c_periph, uint32_t address, uint32_t addr_format); +/* define which bits of ADDRESS[7:1] need to compare with the incoming address byte */ +void i2c_address_bit_compare_config(uint32_t i2c_periph, uint32_t compare_bits); +/* disable i2c address in slave mode */ +void i2c_address_disable(uint32_t i2c_periph); +/* configure i2c second slave address */ +void i2c_second_address_config(uint32_t i2c_periph, uint32_t address, uint32_t addr_mask); +/* disable i2c second address in slave mode */ +void i2c_second_address_disable(uint32_t i2c_periph); +/* get received match address in slave mode */ +uint32_t i2c_recevied_address_get(uint32_t i2c_periph); +/* enable slave byte control */ +void i2c_slave_byte_control_enable(uint32_t i2c_periph); +/* disable slave byte control */ +void i2c_slave_byte_control_disable(uint32_t i2c_periph); +/* generate a NACK in slave mode */ +void i2c_nack_enable(uint32_t i2c_periph); +/* generate an ACK in slave mode */ +void i2c_nack_disable(uint32_t i2c_periph); +/* enable I2C */ +void i2c_enable(uint32_t i2c_periph); +/* disable I2C */ +void i2c_disable(uint32_t i2c_periph); +/* generate a START condition on I2C bus */ +void i2c_start_on_bus(uint32_t i2c_periph); +/* generate a STOP condition on I2C bus */ +void i2c_stop_on_bus(uint32_t i2c_periph); +/* I2C transmit data */ +void i2c_data_transmit(uint32_t i2c_periph, uint32_t data); +/* I2C receive data */ +uint32_t i2c_data_receive(uint32_t i2c_periph); +/* enable I2C reload mode */ +void i2c_reload_enable(uint32_t i2c_periph); +/* disable I2C reload mode */ +void i2c_reload_disable(uint32_t i2c_periph); +/* configure number of bytes to be transferred */ +void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint32_t byte_number); +/* enable I2C DMA for transmission or reception */ +void i2c_dma_enable(uint32_t i2c_periph, uint8_t dma); +/* disable I2C DMA for transmission or reception */ +void i2c_dma_disable(uint32_t i2c_periph, uint8_t dma); +/* I2C transfers PEC value */ +void i2c_pec_transfer(uint32_t i2c_periph); +/* enable I2C PEC calculation */ +void i2c_pec_enable(uint32_t i2c_periph); +/* disable I2C PEC calculation */ +void i2c_pec_disable(uint32_t i2c_periph); +/* get packet error checking value */ +uint32_t i2c_pec_value_get(uint32_t i2c_periph); +/* enable SMBus alert */ +void i2c_smbus_alert_enable(uint32_t i2c_periph); +/* disable SMBus alert */ +void i2c_smbus_alert_disable(uint32_t i2c_periph); +/* enable SMBus device default address */ +void i2c_smbus_default_addr_enable(uint32_t i2c_periph); +/* disable SMBus device default address */ +void i2c_smbus_default_addr_disable(uint32_t i2c_periph); +/* enable SMBus host address */ +void i2c_smbus_host_addr_enable(uint32_t i2c_periph); +/* disable SMBus host address */ +void i2c_smbus_host_addr_disable(uint32_t i2c_periph); +/* enable extended clock timeout detection */ +void i2c_extented_clock_timeout_enable(uint32_t i2c_periph); +/* disable extended clock timeout detection */ +void i2c_extented_clock_timeout_disable(uint32_t i2c_periph); +/* enable clock timeout detection */ +void i2c_clock_timeout_enable(uint32_t i2c_periph); +/* disable clock timeout detection */ +void i2c_clock_timeout_disable(uint32_t i2c_periph); +/* configure bus timeout B */ +void i2c_bus_timeout_b_config(uint32_t i2c_periph, uint32_t timeout); +/* configure bus timeout A */ +void i2c_bus_timeout_a_config(uint32_t i2c_periph, uint32_t timeout); +/* configure idle clock timeout detection */ +void i2c_idle_clock_timeout_config(uint32_t i2c_periph, uint32_t timeout); + +/* interrupt & flag functions */ +/* get I2C flag status */ +FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag); +/* clear I2C flag status */ +void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag); +/* enable I2C interrupt */ +void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t interrupt); +/* disable I2C interrupt */ +void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t interrupt); +/* get I2C interrupt flag status */ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); +/* clear I2C interrupt flag status */ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); + +#endif /* GD32A50X_I2C_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_libopt.h b/gd32a50x/standard_peripheral/include/gd32a50x_libopt.h new file mode 100644 index 0000000..37f6acf --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32a50x_libopt.h + \brief library optional for gd32a50x + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_LIBOPT_H +#define GD32A50X_LIBOPT_H + +#include "gd32a50x_adc.h" +#include "gd32a50x_bkp.h" +#include "gd32a50x_can.h" +#include "gd32a50x_cmp.h" +#include "gd32a50x_crc.h" +#include "gd32a50x_dac.h" +#include "gd32a50x_dbg.h" +#include "gd32a50x_dma.h" +#include "gd32a50x_exti.h" +#include "gd32a50x_fmc.h" +#include "gd32a50x_fwdgt.h" +#include "gd32a50x_gpio.h" +#include "gd32a50x_i2c.h" +#include "gd32a50x_mfcom.h" +#include "gd32a50x_misc.h" +#include "gd32a50x_pmu.h" +#include "gd32a50x_rcu.h" +#include "gd32a50x_spi.h" +#include "gd32a50x_syscfg.h" +#include "gd32a50x_timer.h" +#include "gd32a50x_trigsel.h" +#include "gd32a50x_usart.h" +#include "gd32a50x_wwdgt.h" +#include "gd32a50x_rtc.h" + +#endif /* GD32A50X_LIBOPT_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_mfcom.h b/gd32a50x/standard_peripheral/include/gd32a50x_mfcom.h new file mode 100644 index 0000000..1090ec8 --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_mfcom.h @@ -0,0 +1,452 @@ +/*! + \file gd32a50x_mfcom.h + \brief MFCOM driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50X +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_MFCOM_H +#define GD32A50X_MFCOM_H + +#include "gd32a50x.h" + +/* MFCOM definitions */ +#define MFCOM MFCOM_BASE /*!< MFCOM base address */ + +/* registers definitions */ +#define MFCOM_CTL REG32(MFCOM + 0x00000000U) /*!< MFCOM control register */ +#define MFCOM_PINDATA REG32(MFCOM + 0x00000004U) /*!< MFCOM pin data register */ +#define MFCOM_SSTAT REG32(MFCOM + 0x00000008U) /*!< MFCOM shifter status register */ +#define MFCOM_SERR REG32(MFCOM + 0x0000000CU) /*!< MFCOM shifter error register */ +#define MFCOM_TMSTAT REG32(MFCOM + 0x00000010U) /*!< MFCOM timer status register */ +#define MFCOM_SSIEN REG32(MFCOM + 0x00000018U) /*!< MFCOM shifter status interrupt enable register */ +#define MFCOM_SEIEN REG32(MFCOM + 0x0000001CU) /*!< MFCOM shifter error interrupt enable register */ +#define MFCOM_TMSIEN REG32(MFCOM + 0x00000020U) /*!< MFCOM timer status interrupt enable register */ +#define MFCOM_SSDMAEN REG32(MFCOM + 0x00000028U) /*!< MFCOM shifter status dma enable register */ +#define MFCOM_SCTL(x) REG32(MFCOM + 0x00000080U + (x)*4U) /*!< MFCOM shifter x control register */ +#define MFCOM_SCFG(x) REG32(MFCOM + 0x00000100U + (x)*4U) /*!< MFCOM shifter x configuration register */ +#define MFCOM_SBUF(x) REG32(MFCOM + 0x00000200U + (x)*4U) /*!< MFCOM shifter buffer x register */ +#define MFCOM_SBUFBIS(x) REG32(MFCOM + 0x00000280U + (x)*4U) /*!< MFCOM shifter buffer x bit swapped register */ +#define MFCOM_SBUFBYS(x) REG32(MFCOM + 0x00000300U + (x)*4U) /*!< MFCOM shifter buffer x byte swapped register */ +#define MFCOM_SBUFBBS(x) REG32(MFCOM + 0x00000380U + (x)*4U) /*!< MFCOM shifter buffer x bit byte swapped register */ +#define MFCOM_TMCTL(x) REG32(MFCOM + 0x00000400U + (x)*4U) /*!< MFCOM timer x control register */ +#define MFCOM_TMCFG(x) REG32(MFCOM + 0x00000480U + (x)*4U) /*!< MFCOM timer x configuration register */ +#define MFCOM_TMCMP(x) REG32(MFCOM + 0x00000500U + (x)*4U) /*!< MFCOM timer x compare register */ + +/* bits definitions */ +/* MFCOM_CTL */ +#define MFCOM_CTL_MFCOMEN BIT(0) /*!< MFCOM enable */ +#define MFCOM_CTL_SWRSTEN BIT(1) /*!< software reset enable */ + +/* MFCOM_PINDATA */ +#define MFCOM_PINDATA_PDATA BITS(0,7) /*!< input data of pins */ + +/* MFCOM_SSTAT */ +#define MFCOM_SSTAT_SSTAT BITS(0,3) /*!< shifter x status flag */ + +/* MFCOM_SERR */ +#define MFCOM_SERR_SERR BITS(0,3) /*!< shifter x error flags */ + +/* MFCOM_TMSTAT */ +#define MFCOM_TMSTAT_TMSTAT BITS(0,3) /*!< timer x status flags */ + +/* MFCOM_SSIEN */ +#define MFCOM_SSIEN_SSIEN BITS(0,3) /*!< shifter status interrupt enable */ + +/* MFCOM_TMSIEN */ +#define MFCOM_TMSIEN_TMSIEN BITS(0,3) /*!< timer status interrupt enable */ + +/* MFCOM_SSDMAEN */ +#define MFCOM_SSDMAEN_SSDMAEN BITS(0,3) /*!< shifter status DMA enable */ + +/* MFCOM_SCTLx */ +#define MFCOM_SCTL_SMOD BITS(0,2) /*!< shifter mode */ +#define MFCOM_SCTL_SPPL BIT(7) /*!< shifter pin polarity */ +#define MFCOM_SCTL_SPSEL BITS(8,10) /*!< shifter pin select */ +#define MFCOM_SCTL_SPCFG BITS(16,17) /*!< shifter pin configuration */ +#define MFCOM_SCTL_TMPL BIT(23) /*!< timer polarity */ +#define MFCOM_SCTL_TMSEL BITS(24,25) /*!< timer select */ + +/* MFCOM_SCFGx */ +#define MFCOM_SCFG_SSTART BITS(0,1) /*!< shifter start bit */ +#define MFCOM_SCFG_SSTOP BITS(4,5) /*!< shifter stop bit */ +#define MFCOM_SCFG_INSRC BIT(8) /*!< input source */ + +/* MFCOM_SBUFx */ +#define MFCOM_SBUFx_SBUF BITS(0,31) /*!< shift buffer */ + +/* MFCOM_SBUFBISx */ +#define MFCOM_SBUFBISx_SBUFBIS BITS(0,31) /*!< shift buffer bit swapped */ + +/* MFCOM_SBUFBYSx */ +#define MFCOM_SBUFBYSx_SBUFBYS BITS(0,31) /*!< shift buffer byte swapped */ + +/* MFCOM_SBUFBBSx */ +#define MFCOM_SBUFBBSx_SBUFBBS BITS(0,31) /*!< shift buffer bit byte swapped */ + +/* MFCOM_TMCTLx */ +#define MFCOM_TMCTL_TMMOD BITS(0,1) /*!< timer mode */ +#define MFCOM_TMCTL_TMPPL BIT(7) /*!< timer pin polarity */ +#define MFCOM_TMCTL_TMPSEL BITS(8,10) /*!< timer pin select */ +#define MFCOM_TMCTL_TMPCFG BITS(16,17) /*!< timer pin configuration */ +#define MFCOM_TMCTL_TRIGSRC BIT(22) /*!< trigger source */ +#define MFCOM_TMCTL_TRIGPL BIT(23) /*!< trigger polarity */ +#define MFCOM_TMCTL_TRIGSEL BITS(24,27) /*!< trigger select */ + +/* MFCOM_TMCFGx */ +#define MFCOM_TMCFG_TMSTART BIT(1) /*!< timer start bit */ +#define MFCOM_TMCFG_TMSTOP BITS(4,5) /*!< timer stop bit */ +#define MFCOM_TMCFG_TMEN BITS(8,10) /*!< timer enable source */ +#define MFCOM_TMCFG_TMDIS BITS(12,14) /*!< timer disable source */ +#define MFCOM_TMCFG_TMRST BITS(16,18) /*!< timer reset source */ +#define MFCOM_TMCFG_TMDEC BITS(20,21) /*!< timer decrement source */ +#define MFCOM_TMCFG_TMOUT BITS(24,25) /*!< timer output select */ + +/* MFCOM_TMCMPx */ +#define MFCOM_TMCMPx_TMCVALUE BITS(0,31) /*!< timer compare value */ + +/* constants definitions */ +/* MFCOM timer init parameter struct definitions */ +typedef struct +{ + /* trigger */ + uint32_t trigger_select; /*!< the internal trigger selection */ + uint32_t trigger_polarity; /*!< trigger polarity */ + /* pin */ + uint32_t pin_config; /*!< timer pin configuration */ + uint32_t pin_select; /*!< timer pin number select */ + uint32_t pin_polarity; /*!< timer pin polarity */ + /* timer */ + uint32_t mode; /*!< timer work mode */ + uint32_t output; /*!< configures the initial state of the timer output and + whether it is affected by the timer reset */ + uint32_t decrement; /*!< configures the source of the timer decrement and the + source of the shift clock */ + uint32_t reset; /*!< configures the condition that causes the timer counter + (and optionally the timer output) to be reset */ + uint32_t disable; /*!< configures the condition that causes the timer to be + disabled and stop decrementing */ + uint32_t enable; /*!< configures the condition that causes the timer to be + enabled and start decrementing */ + uint32_t stopbit; /*!< timer stop bit generation */ + uint32_t startbit; /*!< timer start bit generation */ + uint32_t compare; /*!< value for timer compare x register */ +}mfcom_timer_parameter_struct; + +/* MFCOM shifter init parameter struct definitions */ +typedef struct +{ + /* timer */ + uint32_t timer_select; /*!< selects which timer is used for controlling the + logic/shift register and generating the shift clock */ + uint32_t timer_polarity; /*!< timer polarity */ + /* pin */ + uint32_t pin_config; /*!< shifter pin configuration */ + uint32_t pin_select; /*!< shifter pin number select */ + uint32_t pin_polarity; /*!< shifter pin polarity */ + /* shifter */ + uint32_t mode; /*!< configures the mode of the shifter */ + uint32_t input_source; /*!< selects the input source for the shifter */ + uint32_t stopbit; /*!< shifter stop bit */ + uint32_t startbit; /*!< shifter start bit */ +}mfcom_shifter_parameter_struct; + +/* MFCOM timer trigger source */ +#define TMCTL_TRIGSEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) +#define MFCOM_TIMER_TRGSEL_PIN0 (TMCTL_TRIGSEL(0)|MFCOM_TMCTL_TRIGSRC) /*!< pin 0 input selected */ +#define MFCOM_TIMER_TRGSEL_SHIFTER0 (TMCTL_TRIGSEL(1)|MFCOM_TMCTL_TRIGSRC) /*!< shifter 0 status flag selected */ +#define MFCOM_TIMER_TRGSEL_PIN1 (TMCTL_TRIGSEL(2)|MFCOM_TMCTL_TRIGSRC) /*!< pin 1 selected */ +#define MFCOM_TIMER_TRGSEL_TIMER0 (TMCTL_TRIGSEL(3)|MFCOM_TMCTL_TRIGSRC) /*!< timer 0 trigger output selected */ +#define MFCOM_TIMER_TRGSEL_PIN2 (TMCTL_TRIGSEL(4)|MFCOM_TMCTL_TRIGSRC) /*!< pin 2 selected */ +#define MFCOM_TIMER_TRGSEL_SHIFTER1 (TMCTL_TRIGSEL(5)|MFCOM_TMCTL_TRIGSRC) /*!< shifter 1 status flag selected */ +#define MFCOM_TIMER_TRGSEL_PIN3 (TMCTL_TRIGSEL(6)|MFCOM_TMCTL_TRIGSRC) /*!< pin 3 selected */ +#define MFCOM_TIMER_TRGSEL_TIMER1 (TMCTL_TRIGSEL(7)|MFCOM_TMCTL_TRIGSRC) /*!< timer 1 trigger output selected */ +#define MFCOM_TIMER_TRGSEL_PIN4 (TMCTL_TRIGSEL(8)|MFCOM_TMCTL_TRIGSRC) /*!< pin 4 selected */ +#define MFCOM_TIMER_TRGSEL_SHIFTER2 (TMCTL_TRIGSEL(9)|MFCOM_TMCTL_TRIGSRC) /*!< shifter 2 status flag selected */ +#define MFCOM_TIMER_TRGSEL_PIN5 (TMCTL_TRIGSEL(10)|MFCOM_TMCTL_TRIGSRC) /*!< pin 5 selected */ +#define MFCOM_TIMER_TRGSEL_TIMER2 (TMCTL_TRIGSEL(11)|MFCOM_TMCTL_TRIGSRC) /*!< timer 2 trigger output selected */ +#define MFCOM_TIMER_TRGSEL_PIN6 (TMCTL_TRIGSEL(12)|MFCOM_TMCTL_TRIGSRC) /*!< pin 6 selected */ +#define MFCOM_TIMER_TRGSEL_SHIFTER3 (TMCTL_TRIGSEL(13)|MFCOM_TMCTL_TRIGSRC) /*!< shifter 3 status flag selected */ +#define MFCOM_TIMER_TRGSEL_PIN7 (TMCTL_TRIGSEL(14)|MFCOM_TMCTL_TRIGSRC) /*!< pin 7 selected */ +#define MFCOM_TIMER_TRGSEL_TIMER3 (TMCTL_TRIGSEL(15)|MFCOM_TMCTL_TRIGSRC) /*!< timer 3 trigger output selected */ +#define MFCOM_TIMER_TRGSEL_EXTERNAL0 TMCTL_TRIGSEL(0) /*!< external trigger0 selected */ +#define MFCOM_TIMER_TRGSEL_EXTERNAL1 TMCTL_TRIGSEL(1) /*!< external trigger1 selected */ +#define MFCOM_TIMER_TRGSEL_EXTERNAL2 TMCTL_TRIGSEL(2) /*!< external trigger2 selected */ +#define MFCOM_TIMER_TRGSEL_EXTERNAL3 TMCTL_TRIGSEL(3) /*!< external trigger3 selected */ + +/* MFCOM timer trigger polarity */ +#define MFCOM_TIMER_TRGPOL_ACTIVE_HIGH ((uint32_t)0x00000000U) /*!< active high */ +#define MFCOM_TIMER_TRGPOL_ACTIVE_LOW MFCOM_TMCTL_TRIGPL /*!< active low */ + +/* MFCOM timer pin config */ +#define TMCTL_TMPCFG(regval) (BITS(16,17) & ((uint32_t)(regval) << 16U)) +#define MFCOM_TIMER_PINCFG_INPUT TMCTL_TMPCFG(0) /*!< pin input */ +#define MFCOM_TIMER_PINCFG_OPENDRAIN TMCTL_TMPCFG(1) /*!< pin open drain */ +#define MFCOM_TIMER_PINCFG_BIDI TMCTL_TMPCFG(2) /*!< pin cascade input/output */ +#define MFCOM_TIMER_PINCFG_OUTPUT TMCTL_TMPCFG(3) /*!< pin output */ + +/* MFCOM timer pin select */ +#define TMCTL_TMPSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) +#define MFCOM_TIMER_PINSEL_PIN0 TMCTL_TMPSEL(0) /*!< timer Pin 0 selected */ +#define MFCOM_TIMER_PINSEL_PIN1 TMCTL_TMPSEL(1) /*!< timer Pin 1 selected */ +#define MFCOM_TIMER_PINSEL_PIN2 TMCTL_TMPSEL(2) /*!< timer Pin 2 selected */ +#define MFCOM_TIMER_PINSEL_PIN3 TMCTL_TMPSEL(3) /*!< timer Pin 3 selected */ +#define MFCOM_TIMER_PINSEL_PIN4 TMCTL_TMPSEL(4) /*!< timer Pin 4 selected */ +#define MFCOM_TIMER_PINSEL_PIN5 TMCTL_TMPSEL(5) /*!< timer Pin 5 selected */ +#define MFCOM_TIMER_PINSEL_PIN6 TMCTL_TMPSEL(6) /*!< timer Pin 6 selected */ +#define MFCOM_TIMER_PINSEL_PIN7 TMCTL_TMPSEL(7) /*!< timer Pin 7 selected */ + +/* MFCOM timer pin polarity */ +#define MFCOM_TIMER_PINPOL_ACTIVE_HIGH ((uint32_t)0x00000000U) /*!< active high */ +#define MFCOM_TIMER_PINPOL_ACTIVE_LOW MFCOM_TMCTL_TMPPL /*!< active low */ + +/* MFCOM timer mode */ +#define TMCTL_TMMOD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0U)) +#define MFCOM_TIMER_DISABLE TMCTL_TMMOD(0) /*!< timer disabled. */ +#define MFCOM_TIMER_BAUDMODE TMCTL_TMMOD(1) /*!< dual 8-bit counters baud/bit mode */ +#define MFCOM_TIMER_PWMMODE TMCTL_TMMOD(2) /*!< dual 8-bit counters PWM mode */ +#define MFCOM_TIMER_16BITCOUNTER TMCTL_TMMOD(3) /*!< single 16-bit counter mode */ + +/* MFCOM timer output */ +#define TMCFG_TMOUT(regval) (BITS(24,25) & ((uint32_t)(regval) << 24U)) +#define MFCOM_TIMER_OUT_HIGH_EN TMCFG_TMOUT(0) /*!< logic one when enabled and is not affected by timer reset */ +#define MFCOM_TIMER_OUT_LOW_EN TMCFG_TMOUT(1) /*!< logic zero when enabled and is not affected by timer reset */ +#define MFCOM_TIMER_OUT_HIGH_EN_RESET TMCFG_TMOUT(2) /*!< logic one when enabled and on timer reset */ +#define MFCOM_TIMER_OUT_LOW_EN_RESET TMCFG_TMOUT(3) /*!< logic zero when enabled and on timer reset */ + +/* MFCOM timer decrement */ +#define TMCFG_TMDEC(regval) (BITS(20,21) & ((uint32_t)(regval) << 20U)) +#define MFCOM_TIMER_DEC_CLK_SHIFT_OUT TMCFG_TMDEC(0) /*!< decrement counter on MFCOM clock, shift clock equals timer output */ +#define MFCOM_TIMER_DEC_TRIG_SHIFT_OUT TMCFG_TMDEC(1) /*!< decrement counter on trigger input (both edges), shift clock equals timer output */ +#define MFCOM_TIMER_DEC_PIN_SHIFT_PIN TMCFG_TMDEC(2) /*!< decrement counter on pin input (both edges), shift clock equals Pin input */ +#define MFCOM_TIMER_DEC_TRIG_SHIFT_TRIG TMCFG_TMDEC(3) /*!< decrement counter on trigger input (both edges), shift clock equals trigger input */ + +/* MFCOM timer reset */ +#define TMCFG_TMRST(regval) (BITS(16,18) & ((uint32_t)(regval) << 16U)) +#define MFCOM_TIMER_RESET_NEVER TMCFG_TMRST(0) /*!< timer never reset */ +#define MFCOM_TIMER_RESET_PIN_TIMOUT TMCFG_TMRST(2) /*!< timer reset on timer pin equal to timer output */ +#define MFCOM_TIMER_RESET_TRIG_TIMOUT TMCFG_TMRST(3) /*!< timer reset on timer trigger equal to timer output */ +#define MFCOM_TIMER_RESET_PIN_RISING TMCFG_TMRST(4) /*!< timer reset on timer pin rising edge */ +#define MFCOM_TIMER_RESET_TRIG_RISING TMCFG_TMRST(6) /*!< timer reset on trigger rising edge */ +#define MFCOM_TIMER_RESET_TRIG_BOTH TMCFG_TMRST(7) /*!< timer reset on trigger rising or falling edge */ + +/* MFCOM timer disable */ +#define TMCFG_TMDIS(regval) (BITS(12,14) & ((uint32_t)(regval) << 12U)) +#define MFCOM_TIMER_DISMODE_NEVER TMCFG_TMDIS(0) /*!< timer never disabled */ +#define MFCOM_TIMER_DISMODE_PRE_TIMDIS TMCFG_TMDIS(1) /*!< timer disabled on timer x-1 disable */ +#define MFCOM_TIMER_DISMODE_COMPARE TMCFG_TMDIS(2) /*!< timer disabled on timer compare */ +#define MFCOM_TIMER_DISMODE_COMPARE_TRIGLOW TMCFG_TMDIS(3) /*!< timer disabled on timer compare and trigger Low */ +#define MFCOM_TIMER_DISMODE_PINBOTH TMCFG_TMDIS(4) /*!< timer disabled on pin rising or falling edge */ +#define MFCOM_TIMER_DISMODE_PINBOTH_TRIGHIGH TMCFG_TMDIS(5) /*!< timer disabled on pin rising or falling edge provided trigger is high */ +#define MFCOM_TIMER_DISMODE_TRIGFALLING TMCFG_TMDIS(6) /*!< timer disabled on trigger falling edge */ + +/* MFCOM timer enable */ +#define TMCFG_TMEN(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) +#define MFCOM_TIMER_ENMODE_ALWAYS TMCFG_TMEN(0) /*!< timer always enabled */ +#define MFCOM_TIMER_ENMODE_PRE_TIMEN TMCFG_TMEN(1) /*!< timer enabled on timer x-1 enable */ +#define MFCOM_TIMER_ENMODE_TRIGHIGH TMCFG_TMEN(2) /*!< timer enabled on trigger high */ +#define MFCOM_TIMER_ENMODE_TRIGHIGH_PINHIGH TMCFG_TMEN(3) /*!< timer enabled on trigger high and Pin high */ +#define MFCOM_TIMER_ENMODE_PINRISING TMCFG_TMEN(4) /*!< timer enabled on pin rising edge */ +#define MFCOM_TIMER_ENMODE_PINRISING_TRIGHIGH TMCFG_TMEN(5) /*!< timer enabled on pin rising edge and trigger high */ +#define MFCOM_TIMER_ENMODE_TRIGRISING TMCFG_TMEN(6) /*!< timer enabled on trigger rising edge */ +#define MFCOM_TIMER_ENMODE_TRIGBOTH TMCFG_TMEN(7) /*!< timer enabled on trigger rising or falling edge */ + +/* MFCOM timer stopbit */ +#define TMCFG_TMSTOP(regval) (BITS(4,5) & ((uint32_t)(regval) << 4U)) +#define MFCOM_TIMER_STOPBIT_DISABLE TMCFG_TMSTOP(0) /*!< stop bit disabled */ +#define MFCOM_TIMER_STOPBIT_TIMCMP TMCFG_TMSTOP(1) /*!< stop bit is enabled on timer compare */ +#define MFCOM_TIMER_STOPBIT_TIMDIS TMCFG_TMSTOP(2) /*!< stop bit is enabled on timer disable */ +#define MFCOM_TIMER_STOPBIT_TIMCMP_TIMDIS TMCFG_TMSTOP(3) /*!< stop bit is enabled on timer compare and timer disable */ + +/* MFCOM timer startbit */ +#define MFCOM_TIMER_STARTBIT_DISABLE ((uint32_t)0x00000000U) /*!< Start bit disabled */ +#define MFCOM_TIMER_STARTBIT_ENABLE MFCOM_TMCFG_TMSTART /*!< Start bit enabled */ + +/* MFCOM shifter timer select */ +#define SCTL_TMSEL(regval) (BITS(24,25) & ((uint32_t)(regval) << 24U)) +#define MFCOM_SHIFTER_TIMER0 SCTL_TMSEL(0) /*!< timer0 selected */ +#define MFCOM_SHIFTER_TIMER1 SCTL_TMSEL(1) /*!< timer1 selected */ +#define MFCOM_SHIFTER_TIMER2 SCTL_TMSEL(2) /*!< timer2 selected */ +#define MFCOM_SHIFTER_TIMER3 SCTL_TMSEL(3) /*!< timer3 selected */ + +/* type of timer polarity for shifter control */ +#define MFCOM_SHIFTER_TIMPOL_ACTIVE_HIGH ((uint32_t)0x00000000U) /*!< shift on positive edge of shift clock */ +#define MFCOM_SHIFTER_TIMPOL_ACTIVE_LOW MFCOM_SCTL_TMPL /*!< shift on negative edge of shift clock */ + +/* MFCOM shifter pin config */ +#define SCTL_SPCFG(regval) (BITS(16,17) & ((uint32_t)(regval) << 16U)) +#define MFCOM_SHIFTER_PINCFG_INPUT SCTL_SPCFG(0) /*!< pin input */ +#define MFCOM_SHIFTER_PINCFG_OPENDRAIN SCTL_SPCFG(1) /*!< pin open drain */ +#define MFCOM_SHIFTER_PINCFG_BIDI SCTL_SPCFG(2) /*!< pin cascade input/output */ +#define MFCOM_SHIFTER_PINCFG_OUTPUT SCTL_SPCFG(3) /*!< pin output */ + +/* MFCOM shifter pin select */ +#define SCTL_SPSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) +#define MFCOM_SHIFTER_PINSEL_PIN0 SCTL_SPSEL(0) /*!< shifter pin 0 selected */ +#define MFCOM_SHIFTER_PINSEL_PIN1 SCTL_SPSEL(1) /*!< shifter pin 1 selected */ +#define MFCOM_SHIFTER_PINSEL_PIN2 SCTL_SPSEL(2) /*!< shifter pin 2 selected */ +#define MFCOM_SHIFTER_PINSEL_PIN3 SCTL_SPSEL(3) /*!< shifter pin 3 selected */ +#define MFCOM_SHIFTER_PINSEL_PIN4 SCTL_SPSEL(4) /*!< shifter pin 4 selected */ +#define MFCOM_SHIFTER_PINSEL_PIN5 SCTL_SPSEL(5) /*!< shifter pin 5 selected */ +#define MFCOM_SHIFTER_PINSEL_PIN6 SCTL_SPSEL(6) /*!< shifter pin 6 selected */ +#define MFCOM_SHIFTER_PINSEL_PIN7 SCTL_SPSEL(7) /*!< shifter pin 7 selected */ + +/* MFCOM shifter pin polarity */ +#define MFCOM_SHIFTER_PINPOL_ACTIVE_HIGH ((uint32_t)0x00000000U) /*!< active high */ +#define MFCOM_SHIFTER_PINPOL_ACTIVE_LOW MFCOM_SCTL_SPPL /*!< active low */ + +/* MFCOM shifter mode */ +#define SCTL_SMOD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U)) +#define MFCOM_SHIFTER_DISABLE SCTL_SMOD(0) /*!< shifter is disabled */ +#define MFCOM_SHIFTER_RECEIVE SCTL_SMOD(1) /*!< receive mode */ +#define MFCOM_SHIFTER_TRANSMIT SCTL_SMOD(2) /*!< transmit mode */ +#define MFCOM_SHIFTER_MATCH_STORE SCTL_SMOD(4) /*!< match store mode */ +#define MFCOM_SHIFTER_MATCH_CONTINUOUS SCTL_SMOD(5) /*!< match continuous mode */ + +/* MFCOM shifter input source */ +#define MFCOM_SHIFTER_INSRC_PIN ((uint32_t)0x00000000U) /*!< shifter input from pin */ +#define MFCOM_SHIFTER_INSRC_NEXTSHIFTER MFCOM_SCFG_INSRC /*!< shifter input from shifter x+1 */ + +/* MFCOM shifter stopbit */ +#define SCFG_SSTOP(regval) (BITS(4,5) & ((uint32_t)(regval) << 4U)) +#define MFCOM_SHIFTER_STOPBIT_DISABLE SCFG_SSTOP(0) /*!< disable shifter stop bit */ +#define MFCOM_SHIFTER_STOPBIT_LOW SCFG_SSTOP(2) /*!< set shifter stop bit to logic low level */ +#define MFCOM_SHIFTER_STOPBIT_HIGH SCFG_SSTOP(3) /*!< set shifter stop bit to logic high level */ + +/* MFCOM shifter startbit */ +#define SCFG_SSTART(regval) (BITS(0,1) & ((uint32_t)(regval) << 0U)) +#define MFCOM_SHIFTER_STARTBIT_DISABLE SCFG_SSTART(0) /*!< disable shifter start bit, transmitter loads data on enable */ +#define MFCOM_SHIFTER_STARTBIT_DISABLE_TXEN SCFG_SSTART(1) /*!< disable shifter start bit, transmitter loads data on first shift */ +#define MFCOM_SHIFTER_STARTBIT_LOW SCFG_SSTART(2) /*!< set shifter start bit to logic low level */ +#define MFCOM_SHIFTER_STARTBIT_HIGH SCFG_SSTART(3) /*!< set shifter start bit to logic high level */ + +/* MFCOM shifter enum */ +#define MFCOM_SHIFTER_0 ((uint32_t)0x00000000U) /*!< MFCOM shifter0 */ +#define MFCOM_SHIFTER_1 ((uint32_t)0x00000001U) /*!< MFCOM shifter1 */ +#define MFCOM_SHIFTER_2 ((uint32_t)0x00000002U) /*!< MFCOM shifter2 */ +#define MFCOM_SHIFTER_3 ((uint32_t)0x00000003U) /*!< MFCOM shifter3 */ + +/* MFCOM timer enum */ +#define MFCOM_TIMER_0 ((uint32_t)0x00000000U) /*!< MFCOM timer0 */ +#define MFCOM_TIMER_1 ((uint32_t)0x00000001U) /*!< MFCOM timer1 */ +#define MFCOM_TIMER_2 ((uint32_t)0x00000002U) /*!< MFCOM timer2 */ +#define MFCOM_TIMER_3 ((uint32_t)0x00000003U) /*!< MFCOM timer3 */ + +/* MFCOM read write mode enum */ +#define MFCOM_RWMODE_NORMAL ((uint32_t)0x00000000U) /*!< read and write in normal mode */ +#define MFCOM_RWMODE_BITSWAP ((uint32_t)0x00000001U) /*!< read and write in bit swapped mode */ +#define MFCOM_RWMODE_BYTESWAP ((uint32_t)0x00000002U) /*!< read and write in byte swapped mode */ +#define MFCOM_RWMODE_BITBYTESWAP ((uint32_t)0x00000003U) /*!< read and write in bit byte swapped mode */ + +/* function declarations */ +/* reset MFCOM */ +void mfcom_deinit(void); +/* software reset */ +void mfcom_software_reset(void); +/* enable MFCOM function */ +void mfcom_enable(void); +/* disable MFCOM function */ +void mfcom_disable(void); +/* initialize mfcom_timer_parameter_struct with the default values */ +void mfcom_timer_struct_para_init(mfcom_timer_parameter_struct* init_struct); +/* initialize mfcom_shifter_parameter_struct with the default values */ +void mfcom_shifter_struct_para_init(mfcom_shifter_parameter_struct* init_struct); + +/* initialize MFCOM timer */ +void mfcom_timer_init(uint32_t timer, mfcom_timer_parameter_struct* init_struct); +/* initialize MFCOM shifter */ +void mfcom_shifter_init(uint32_t shifter, mfcom_shifter_parameter_struct* init_struct); + +/* configure timer pin mode */ +void mfcom_timer_pin_config(uint32_t timer, uint32_t mode); +/* configure shifter pin mode */ +void mfcom_shifter_pin_config(uint32_t shifter, uint32_t mode); +/* enable MFCOM timer in specific mode */ +void mfcom_timer_enable(uint32_t timer, uint32_t timermode); +/* enable MFCOM shifter in specific mode */ +void mfcom_shifter_enable(uint32_t shifter, uint32_t shiftermode); +/* disable MFCOM timer */ +void mfcom_timer_disable(uint32_t timer); +/* disable MFCOM shifter */ +void mfcom_shifter_disable(uint32_t shifter); + +/* set the timer compare value */ +void mfcom_timer_cmpvalue_set(uint32_t timer, uint32_t compare); +/* get the timer compare value */ +uint32_t mfcom_timer_cmpvalue_get(uint32_t timer); +/* set the timer disable source */ +void mfcom_timer_dismode_set(uint32_t timer, uint32_t dismode); + +/* set the shifter stopbit */ +void mfcom_shifter_stopbit_set(uint32_t shifter, uint32_t stopbit); +/* write MFCOM shifter buffer */ +void mfcom_buffer_write(uint32_t shifter, uint32_t data, uint32_t rwmode); +/* read MFCOM shifter buffer */ +uint32_t mfcom_buffer_read(uint32_t shifter, uint32_t rwmode); +/* get MFCOM shifter flag */ +FlagStatus mfcom_shifter_flag_get(uint32_t shifter); +/* get MFCOM shifter error flag */ +FlagStatus mfcom_shifter_error_flag_get(uint32_t shifter); +/* get MFCOM timer flag */ +FlagStatus mfcom_timer_flag_get(uint32_t timer); + +/* get MFCOM shifter interrupt flag */ +FlagStatus mfcom_shifter_interrupt_flag_get(uint32_t shifter); +/* get MFCOM shifter error interrupt flag */ +FlagStatus mfcom_shifter_error_interrupt_flag_get(uint32_t shifter); +/* get MFCOM timer interrupt flag */ +FlagStatus mfcom_timer_interrupt_flag_get(uint32_t timer); + +/* clear MFCOM shifter flag */ +void mfcom_shifter_flag_clear(uint32_t shifter); +/* clear MFCOM shifter error flag */ +void mfcom_shifter_error_flag_clear(uint32_t shifter); +/* clear MFCOM timer flag */ +void mfcom_timer_flag_clear(uint32_t timer); + +/* enable MFCOM shifter interrupt */ +void mfcom_shifter_interrupt_enable(uint32_t shifter); +/* enable MFCOM shifter error interrupt */ +void mfcom_shifter_error_interrupt_enable(uint32_t shifter); +/* enable MFCOM timer interrupt */ +void mfcom_timer_interrupt_enable(uint32_t timer); +/* enable MFCOM shifter dma */ +void mfcom_shifter_dma_enable(uint32_t shifter); + +/* disable MFCOM shifter interrupt */ +void mfcom_shifter_interrupt_disable(uint32_t shifter); +/* disable MFCOM shifter error interrupt */ +void mfcom_shifter_error_interrupt_disable(uint32_t shifter); +/* disable MFCOM timer interrupt */ +void mfcom_timer_interrupt_disable(uint32_t timer); +/* disable MFCOM shifter dma */ +void mfcom_shifter_dma_disable(uint32_t shifter); + +#endif /* GD32A50X_MFCOM_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_misc.h b/gd32a50x/standard_peripheral/include/gd32a50x_misc.h new file mode 100644 index 0000000..8d6bb15 --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_misc.h @@ -0,0 +1,93 @@ +/*! + \file gd32a50x_misc.h + \brief definitions for the MISC + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_MISC_H +#define GD32A50X_MISC_H + +#include "gd32a50x.h" + +/* constants definitions */ +/* set the RAM and FLASH base address */ +#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ +#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ + +/* set the NVIC vector table offset mask */ +#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) + +/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ +#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +/* priority group - define the pre-emption priority and the subpriority */ +#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ +#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ +#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ +#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ +#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ + +/* choose the method to enter or exit the lowpower mode */ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ + +#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT +#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP +#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND + +/* choose the systick clock source */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ + +/* function declarations */ +/* set the priority group */ +void nvic_priority_group_set(uint32_t nvic_prigroup); + +/* enable NVIC request */ +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); +/* disable NVIC request */ +void nvic_irq_disable(IRQn_Type nvic_irq); +/* initiates a system reset request to reset the MCU */ +void nvic_system_reset(void); + +/* set the NVIC vector table base address */ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); + +/* set the state of the low power mode */ +void system_lowpower_set(uint8_t lowpower_mode); +/* reset the state of the low power mode */ +void system_lowpower_reset(uint8_t lowpower_mode); + +/* set the systick clock source */ +void systick_clksource_set(uint32_t systick_clksource); + +#endif /* GD32A50X_MISC_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_pmu.h b/gd32a50x/standard_peripheral/include/gd32a50x_pmu.h new file mode 100644 index 0000000..5b608b9 --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_pmu.h @@ -0,0 +1,165 @@ +/*! + \file gd32a50x_pmu.h + \brief definitions for the PMU + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_PMU_H +#define GD32A50X_PMU_H + +#include "gd32a50x.h" + +/* PMU definitions */ +#define PMU PMU_BASE /*!< PMU base address */ + +/* registers definitions */ +#define PMU_CTL REG32((PMU) + 0x00000000U) /*!< PMU control register */ +#define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status register */ + +/* bits definitions */ +/* PMU_CTL */ +#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ +#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ +#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ +#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ +#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ +#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ +#define PMU_CTL_OVDEN BIT(14) /*!< over voltage detector enable */ +#define PMU_CTL_OVDT BIT(15) /*!< over voltage detector threshold */ +#define PMU_CTL_LDEN BIT(18) /*!< low-driver mode enable in deep-sleep mode */ +#define PMU_CTL_SRAMSW1 BIT(20) /*!< SRAM1(16KB~32KB) power switch in deep-sleep mode */ +#define PMU_CTL_SRAMSW2 BIT(21) /*!< SRAM2(32KB~48KB) power switch in deep-sleep mode */ + +/* PMU_CS */ +#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ +#define PMU_CS_STBF BIT(1) /*!< standby flag */ +#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ +#define PMU_CS_OVDF BIT(3) /*!< over voltage detector status flag */ +#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin 0 enable */ +#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin 1 enable */ + +/* constants definitions */ +/* PMU ldo definitions */ +#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ +#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ + +/* PMU low voltage detector threshold definitions */ +#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) +#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.9V */ +#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 3.1V */ +#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 3.3V */ +#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 3.5V */ +#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 4.0V */ +#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 4.2V */ +#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 4.4V */ +#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 4.6V */ + +/* PMU over voltage detector threshold definitions */ +#define CTL_OVDT(regval) (BIT(15)&((uint32_t)(regval)<<15)) +#define PMU_OVDT_0 CTL_OVDT(0) /*!< voltage threshold is 5.0V */ +#define PMU_OVDT_1 CTL_OVDT(1) /*!< voltage threshold is 5.5V */ + +/* PMU flag definitions */ +#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ +#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ +#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ +#define PMU_FLAG_OVD PMU_CS_OVDF /*!< ovd flag status */ + +/* PMU WKUP pin definitions */ +#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */ +#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */ + +/* low-driver mode in deep-sleep mode */ +#define PMU_LOWDRIVER_DISABLE ((uint32_t)0x00000000U) /*!< low-driver mode disable in deep-sleep mode */ +#define PMU_LOWDRIVER_ENABLE PMU_CTL_LDEN /*!< low-driver mode enable in deep-sleep mode */ + +/* PMU flag reset definitions */ +#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ +#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ + +/* PMU command constants definitions */ +#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ +#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ + +/* function declarations */ +/* reset PMU registers */ +void pmu_deinit(void); + +/* select low voltage detector threshold */ +void pmu_lvd_select(uint32_t lvdt_n); +/* disable PMU lvd */ +void pmu_lvd_disable(void); +/* select over voltage detector threshold */ +void pmu_ovd_select(uint32_t ovdt_n); +/* disable PMU ovd */ +void pmu_ovd_disable(void); + +/* enable low-driver mode in deep-sleep mode */ +void pmu_lowdriver_mode_enable(void); +/* disable low-driver mode in deep-sleep mode */ +void pmu_lowdriver_mode_disable(void); +/* SRAM1 power off in deep-sleep mode */ +void pmu_sram1_poweroff_mode_enable(void); +/* SRAM1 power on in deep-sleep mode */ +void pmu_sram1_poweroff_mode_disable(void); +/* SRAM2 power off in deep-sleep mode */ +void pmu_sram2_poweroff_mode_enable(void); +/* SRAM2 power on in deep-sleep mode */ +void pmu_sram2_poweroff_mode_disable(void); + +/* set PMU mode */ +/* PMU work in sleep mode */ +void pmu_to_sleepmode(uint8_t sleepmodecmd); +/* PMU work in deepsleep mode */ +void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd); +/* PMU work in standby mode */ +void pmu_to_standbymode(void); + +/* wakeup pin related functions */ +/* enable PMU wakeup pin */ +void pmu_wakeup_pin_enable(uint32_t wakeup_pin); +/* disable PMU wakeup pin */ +void pmu_wakeup_pin_disable(uint32_t wakeup_pin); + +/* backup related functions */ +/* enable write access to the registers in backup domain */ +void pmu_backup_write_enable(void); +/* disable write access to the registers in backup domain */ +void pmu_backup_write_disable(void); + +/* flag functions */ +/* get flag state */ +FlagStatus pmu_flag_get(uint32_t flag); +/* clear flag bit */ +void pmu_flag_clear(uint32_t flag); + +#endif /* GD32A50X_PMU_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_rcu.h b/gd32a50x/standard_peripheral/include/gd32a50x_rcu.h new file mode 100644 index 0000000..2f1903c --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_rcu.h @@ -0,0 +1,761 @@ +/*! + \file gd32a50x_rcu.h + \brief definitions for the RCU + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_RCU_H +#define GD32A50X_RCU_H + +#include "gd32a50x.h" + +/* RCU definitions */ +#define RCU RCU_BASE /*!< RCU base address */ + +/* registers definitions */ +#define RCU_CTL REG32(RCU + 0x00000000U) /*!< control register */ +#define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< clock configuration register 0 */ +#define RCU_INT REG32(RCU + 0x00000008U) /*!< clock interrupt register */ +#define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */ +#define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */ +#define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB1 enable register */ +#define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */ +#define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */ +#define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control register */ +#define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source / clock register */ +#define RCU_AHBRST REG32(RCU + 0x00000028U) /*!< AHB reset register */ +#define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< clock configuration register 1 */ +#define RCU_CFG2 REG32(RCU + 0x00000030U) /*!< clock configuration register 2 */ +#define RCU_VKEY REG32(RCU + 0x00000100U) /*!< voltage key register */ +#define RCU_DSV REG32(RCU + 0x00000134U) /*!< deep-sleep mode voltage register */ + +/* bits definitions */ +/* RCU_CTL */ +#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ +#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< internal 8M RC oscillator clock trim adjust value */ +#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< internal 8M RC oscillator calibration value */ +#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ +#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ +#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ +#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ +#define RCU_CTL_PLLMEN BIT(20) /*!< PLL clock monitor enable */ +#define RCU_CTL_LCKMEN BIT(21) /*!< LXTAL clock monitor enable */ +#define RCU_CTL_HXTALSCAL BIT(22) /*!< HXTAL frequency scale select */ +#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ +#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ + +/* RCU_CFG0 */ +#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ +#define RCU_CFG0_DPLL BIT(17) /*!< double PLL clock */ +#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ +#define RCU_CFG0_CKOUTSEL BITS(24,26) /*!< CKOUT clock source selection */ +#define RCU_CFG0_PLLMF_4 BIT(27) /*!< bit 4 of PLLMF */ +#define RCU_CFG0_CKOUTDIV BITS(28,30) /*!< CK_OUT divider which the CK_OUT frequency can be reduced */ +#define RCU_CFG0_PLLDV BIT(31) /*!< CK_PLL divide by 1 or 2 for CK_OUT */ + +/* RCU_INT */ +#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ +#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ +#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ +#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ +#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ +#define RCU_INT_LCKMIF BIT(5) /*!< LXTAL clock monitor interrupt flag */ +#define RCU_INT_PLLMIF BIT(6) /*!< PLL clock monitor interrupt flag */ +#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ +#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ +#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ +#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ +#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ +#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ +#define RCU_INT_LCKMIE BIT(13) /*!< LXTAL clock monitor interrupt enable */ +#define RCU_INT_PLLMIE BIT(14) /*!< PLL clock monitor interrupt enable */ +#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ +#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ +#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ +#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ +#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ +#define RCU_INT_LCKMIC BIT(21) /*!< LXTAL clock monitor interrupt clear */ +#define RCU_INT_PLLMIC BIT(22) /*!< PLL clock monitor interrupt clear */ +#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ + +/* RCU_APB2RST */ +#define RCU_APB2RST_CFGRST BIT(0) /*!< system configuration reset */ +#define RCU_APB2RST_CMPRST BIT(1) /*!< comparator reset */ +#define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ +#define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ +#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ +#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ +#define RCU_APB2RST_TIMER7RST BIT(13) /*!< TIMER7 reset */ +#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ +#define RCU_APB2RST_TIMER19RST BIT(20) /*!< TIMER19 reset */ +#define RCU_APB2RST_TIMER20RST BIT(21) /*!< TIMER20 reset */ +#define RCU_APB2RST_CAN0RST BIT(30) /*!< CAN0 reset */ +#define RCU_APB2RST_CAN1RST BIT(31) /*!< CAN1 reset */ + +/* RCU_APB1RST */ +#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ +#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ +#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ +#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ +#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ +#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ +#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ +#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ +#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ +#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ +#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ + +/* RCU_AHBEN */ +#define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ +#define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ +#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ +#define RCU_AHBEN_DMAMUXEN BIT(3) /*!< DMAMUX clock enable */ +#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ +#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ +#define RCU_AHBEN_MFCOMEN BIT(14) /*!< MFCOM clock enable */ +#define RCU_AHBEN_PAEN BIT(17) /*!< GPIOA clock enable */ +#define RCU_AHBEN_PBEN BIT(18) /*!< GPIOB clock enable */ +#define RCU_AHBEN_PCEN BIT(19) /*!< GPIOC clock enable */ +#define RCU_AHBEN_PDEN BIT(20) /*!< GPIOD clock enable */ +#define RCU_AHBEN_PEEN BIT(21) /*!< GPIOE clock enable */ +#define RCU_AHBEN_PFEN BIT(22) /*!< GPIOF clock enable */ + +/* RCU_APB2EN */ +#define RCU_APB2EN_CFGEN BIT(0) /*!< System configuration clock enable */ +#define RCU_APB2EN_CMPEN BIT(1) /*!< Comparator clock enable */ +#define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ +#define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ +#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ +#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ +#define RCU_APB2EN_TIMER7EN BIT(13) /*!< TIMER7 clock enable */ +#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ +#define RCU_APB2EN_TIMER19EN BIT(20) /*!< TIMER19 clock enable */ +#define RCU_APB2EN_TIMER20EN BIT(21) /*!< TIMER20 clock enable */ +#define RCU_APB2EN_TRIGSELEN BIT(29) /*!< TRIGSEL clock enable */ +#define RCU_APB2EN_CAN0EN BIT(30) /*!< CAN0 clock enable */ +#define RCU_APB2EN_CAN1EN BIT(31) /*!< CAN1 clock enable */ + +/* RCU_APB1EN */ +#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ +#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ +#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ +#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ +#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ +#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ +#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ +#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ +#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ +#define RCU_APB1EN_BKPEN BIT(27) /*!< Back-up interface clock enable */ +#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ +#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ + +/* RCU_BDCTL */ +#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ +#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ +#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ +#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ +#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ +#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ +#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ + +/* RCU_RSTSCK */ +#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ +#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ +#define RCU_RSTSCK_LOCKUPRSTEN BIT(10) /*!< CPU Lock-Up reset enable */ +#define RCU_RSTSCK_LVDRSTEN BIT(11) /*!< low voltage detection reset enable */ +#define RCU_RSTSCK_ECCRSTEN BIT(12) /*!< ECC 2 bits error reset enable*/ +#define RCU_RSTSCK_LOHRSTEN BIT(13) /*!< lost of HXTAL reset enable */ +#define RCU_RSTSCK_LOPRSTEN BIT(14) /*!< lost of PLL reset enable */ +#define RCU_RSTSCK_BORRSTF BIT(17) /*!< BOR reset flag */ +#define RCU_RSTSCK_LOCKUPRSTF BIT(18) /*!< CPU Lock-Up error reset flag */ +#define RCU_RSTSCK_LVDRSTF BIT(19) /*!< low Voltage detect error reset flag */ +#define RCU_RSTSCK_ECCRSTF BIT(20) /*!< two bit ECC error reset flag */ +#define RCU_RSTSCK_LOHRSTF BIT(21) /*!< lost of HXTAL error reset flag */ +#define RCU_RSTSCK_LOPRSTF BIT(22) /*!< lost of PLL error reset flag */ +#define RCU_RSTSCK_V11RSTF BIT(23) /*!< 1.1V domain power reset flag */ +#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ +#define RCU_RSTSCK_OBLRSTF BIT(25) /*!< option byte loader reset flag */ +#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ +#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ +#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ +#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ +#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ +#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ + +/* RCU_AHBRST */ +#define RCU_AHBRST_DMA0RST BIT(0) /*!< DMA0 reset */ +#define RCU_AHBRST_DMA1RST BIT(1) /*!< DMA1 reset */ +#define RCU_AHBRST_DMAMUXRST BIT(3) /*!< DMAMUX reset */ +#define RCU_AHBRST_CRCRST BIT(6) /*!< CRC reset */ +#define RCU_AHBRST_MFCOMRST BIT(14) /*!< MFCOM reset */ +#define RCU_AHBRST_PARST BIT(17) /*!< GPIO port A reset */ +#define RCU_AHBRST_PBRST BIT(18) /*!< GPIO port B reset */ +#define RCU_AHBRST_PCRST BIT(19) /*!< GPIO port C reset */ +#define RCU_AHBRST_PDRST BIT(20) /*!< GPIO port D reset */ +#define RCU_AHBRST_PERST BIT(21) /*!< GPIO port E reset */ +#define RCU_AHBRST_PFRST BIT(22) /*!< GPIO port F reset */ + +/* RCU_CFG1 */ +#define RCU_CFG1_PREDV BITS(0,3) /*!< CK_HXTAL divider previous PLL */ + +/* RCU_CFG2 */ +#define RCU_CFG2_USART0SEL BITS(0,1) /*!< USART0 clock source selection */ +#define RCU_CFG2_USART1SEL BITS(4,5) /*!< USART1 clock source selection */ +#define RCU_CFG2_USART2SEL BITS(6,7) /*!< USART2 clock source selection */ +#define RCU_CFG2_CAN0SEL BITS(12,13) /*!< CAN0 clock source selection */ +#define RCU_CFG2_CAN1SEL BITS(14,15) /*!< CAN1 clock source selection */ +#define RCU_CFG2_ADCPSC BITS(27,31) /*!< ADC prescaler selection */ + +/* RCU_VKEY */ +#define RCU_VKEY_UNLOCK 0x1A2B3C4DU /*!< the key of RCU_DSV register */ +/* RCU_VKEY */ +#define RCU_VKEY_KEY BITS(0,31) +/* RCU_DSV */ +#define RCU_DSV_DSLPVS BITS(0,1) /*!< Deep-sleep mode voltage selection */ + +/* constants definitions */ +/* define the peripheral clock enable bit position and its register index offset */ +#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) +#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) + +/* register offset */ +/* peripherals enable */ +#define AHBEN_REG_OFFSET 0x00000014U /*!< AHB enable register offset */ +#define APB1EN_REG_OFFSET 0x0000001CU /*!< APB1 enable register offset */ +#define APB2EN_REG_OFFSET 0x00000018U /*!< APB2 enable register offset */ + +/* peripherals reset */ +#define AHBRST_REG_OFFSET 0x00000028U /*!< AHB reset register offset */ +#define APB1RST_REG_OFFSET 0x00000010U /*!< APB1 reset register offset */ +#define APB2RST_REG_OFFSET 0x0000000CU /*!< APB2 reset register offset */ +#define RSTSCK_REG_OFFSET 0x00000024U /*!< reset source/clock register offset */ + +/* clock control */ +#define CTL_REG_OFFSET 0x00000000U /*!< control register offset */ +#define BDCTL_REG_OFFSET 0x00000020U /*!< backup domain control register offset */ + +/* clock stabilization and stuck interrupt */ +#define INT_REG_OFFSET 0x00000008U /*!< clock interrupt register offset */ + +/* configuration register */ +#define CFG0_REG_OFFSET 0x00000004U /*!< clock configuration register 0 offset */ +#define CFG1_REG_OFFSET 0x0000002CU /*!< clock configuration register 1 offset */ + +/* peripheral clock enable */ +typedef enum { + /* AHB peripherals */ + RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ + RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ + RCU_DMAMUX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 3U), /*!< DMAMUX clock */ + RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ + RCU_MFCOM = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U), /*!< MFCOM clock */ + RCU_GPIOA = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 17U), /*!< GPIOA clock */ + RCU_GPIOB = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 18U), /*!< GPIOB clock */ + RCU_GPIOC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 19U), /*!< GPIOC clock */ + RCU_GPIOD = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 20U), /*!< GPIOD clock */ + RCU_GPIOE = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 21U), /*!< GPIOE clock */ + RCU_GPIOF = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 22U), /*!< GPIOF clock */ + /* APB2 peripherals */ + RCU_SYSCFG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< SYSCFG clock */ + RCU_CMP = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 1U), /*!< CMP clock */ + RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ + RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ + RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ + RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ + RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< TIMER7 clock */ + RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ + RCU_TIMER19 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER19 clock */ + RCU_TIMER20 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER20 clock */ + RCU_TRIGSEL = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 29U), /*!< TRIGSEL clock */ + RCU_CAN0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 30U), /*!< CAN0 clock */ + RCU_CAN1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 31U), /*!< CAN1 clock */ + /* APB1 peripherals */ + RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ + RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ + RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ + RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ + RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ + RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ + RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ + RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ + RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ + RCU_BKP = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKP clock */ + RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ + RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ + RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ +} rcu_periph_enum; + + +/* peripherals reset */ +typedef enum { + /* AHB peripherals */ + RCU_DMA0RST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 0U), /*!< DMA0 clock reset */ + RCU_DMA1RST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 1U), /*!< DMA1 clock reset */ + RCU_DMAMUXRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 3U), /*!< DMAMUX clock reset */ + RCU_CRCRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 6U), /*!< CRC clock reset */ + RCU_MFCOMRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< MFCOM clock reset */ + RCU_GPIOARST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 17U), /*!< GPIOA clock reset */ + RCU_GPIOBRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 18U), /*!< GPIOB clock reset */ + RCU_GPIOCRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 19U), /*!< GPIOC clock reset */ + RCU_GPIODRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 20U), /*!< GPIOD clock reset */ + RCU_GPIOERST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 21U), /*!< GPIOE clock reset */ + RCU_GPIOFRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 22U), /*!< GPIOF clock reset */ + /* APB2 peripherals */ + RCU_SYSCFGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< system configuration reset */ + RCU_CMPRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 1U), /*!< Comparator reset */ + RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ + RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ + RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ + RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ + RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< TIMER7 clock reset */ + RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ + RCU_TIMER19RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER19 clock reset */ + RCU_TIMER20RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER20 clock reset */ + RCU_CAN0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 30U), /*!< CAN0 clock reset */ + RCU_CAN1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 31U), /*!< CAN1 clock reset */ + /* APB1 peripherals */ + RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ + RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ + RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ + RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ + RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ + RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ + RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ + RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ + RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ + RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ + RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ +} rcu_periph_reset_enum; + +/* peripheral clock enable when sleep mode*/ +typedef enum { + /* AHB peripherals */ + RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ + RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ +} rcu_periph_sleep_enum; + +/* clock stabilization and peripheral reset flags */ +typedef enum { + /* clock stabilization flags */ + RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flag */ + RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flag */ + RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flag */ + RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flag */ + /* reset source flags */ + RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flag */ + RCU_FLAG_BORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 17U), /*!< BOR reset flag */ + RCU_FLAG_LOCKUPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 18U), /*!< CPU LOCK UP error reset flag */ + RCU_FLAG_LVDRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 19U), /*!< low voltage detect error reset flag */ + RCU_FLAG_ECCRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 20U), /*!< 2 bits ECC error reset flag */ + RCU_FLAG_LOHRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 21U), /*!< lost of HXTAL error reset flag */ + RCU_FLAG_LOPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 22U), /*!< lost of PLL error reset flag */ + RCU_FLAG_V11RST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 23U), /*!< 1.1V domain Power reset flag */ + RCU_FLAG_OBLRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 25U), /*!< option byte loader reset flag */ + RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flag */ + RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flag */ + RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flag */ + RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flag */ + RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flag */ + RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flag */ +} rcu_flag_enum; + +/* clock stabilization and ckm interrupt flags */ +typedef enum { + RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ + RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ + RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ + RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ + RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ + RCU_INT_FLAG_LCKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< LXTAL clock monitor interrupt flag */ + RCU_INT_FLAG_PLLM = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL clock monitor interrupt flag */ + RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ +} rcu_int_flag_enum; + +/* clock stabilization and stuck interrupt flags clear */ +typedef enum { + RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flag clear */ + RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flag clear */ + RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flag clear */ + RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flag clear */ + RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flag clear */ + RCU_INT_FLAG_LCKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< LXTAL clock monitor interrupt clear */ + RCU_INT_FLAG_PLLM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL clock monitor interrupt clear */ + RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flag clear */ +} rcu_int_flag_clear_enum; + +/* clock stabilization interrupt enable or disable */ +typedef enum { + RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt enable */ + RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt enable */ + RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt enable */ + RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt enable */ + RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt enable */ + RCU_INT_LCKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< LXTAL clock monitor interrupt enable */ + RCU_INT_PLLM = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL clock monitor interrupt enable */ +} rcu_int_enum; + +/* oscillator types */ +typedef enum { + RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ + RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ + RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ + RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ + RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ +} rcu_osci_type_enum; + +/* rcu clock frequency */ +typedef enum { + CK_SYS = 0, /*!< system clock */ + CK_AHB, /*!< AHB clock */ + CK_APB1, /*!< APB1 clock */ + CK_APB2, /*!< APB2 clock */ + CK_USART0, /*!< USART0 clock */ + CK_USART1, /*!< USART1 clock */ + CK_USART2, /*!< USART2 clock */ +} rcu_clock_freq_enum; + +/* HXTAL frequency scale select */ +#define HXTAL_SCALE_2M_TO_8M 0x00000000U /*!< HXTAL scale is 2M-8MHz */ +#define HXTAL_SCALE_8M_TO_40M RCU_CTL_HXTALSCAL /*!< HXTAL scale is 8M-40MHz */ + +/* RCU_CFG0 register bit define */ +/* system clock source select */ +#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ +#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ +#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ + +/* system clock source select status */ +#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ +#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ +#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLL */ + +/* AHB prescaler selection */ +#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ +#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ +#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ +#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ +#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ +#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ +#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ +#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ +#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ + +/* APB1 prescaler selection */ +#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) +#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ +#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ +#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ +#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ +#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ + +/* APB2 prescaler selection */ +#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) +#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ +#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ +#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ +#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ +#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ + +/* RCU system reset */ +#define RCU_SYSRST_LOCKUP RCU_RSTSCK_LOCKUPRSTEN /*!< CPU lock-up reset */ +#define RCU_SYSRST_LVD RCU_RSTSCK_LVDRSTEN /*!< low voltage detect reset */ +#define RCU_SYSRST_ECC RCU_RSTSCK_ECCRSTEN /*!< ECC 2 bits error reset */ +#define RCU_SYSRST_LOH RCU_RSTSCK_LOHRSTEN /*!< lost of HXTAL error reset */ +#define RCU_SYSRST_LOP RCU_RSTSCK_LOPRSTEN /*!< lost of PLL reset */ + +/* ADC prescaler select */ +#define CFG2_ADCPSC(regval) (BITS(27,31) & ((uint32_t)(regval) << 27)) +#define RCU_CKADC_CKAHB_DIV2 CFG2_ADCPSC(0) /*!< ADC prescaler select CK_AHB/2 */ +#define RCU_CKADC_CKAHB_DIV3 CFG2_ADCPSC(1) /*!< ADC prescaler select CK_AHB/3 */ +#define RCU_CKADC_CKAHB_DIV4 CFG2_ADCPSC(2) /*!< ADC prescaler select CK_AHB/4 */ +#define RCU_CKADC_CKAHB_DIV5 CFG2_ADCPSC(3) /*!< ADC prescaler select CK_AHB/5 */ +#define RCU_CKADC_CKAHB_DIV6 CFG2_ADCPSC(4) /*!< ADC prescaler select CK_AHB/6 */ +#define RCU_CKADC_CKAHB_DIV7 CFG2_ADCPSC(5) /*!< ADC prescaler select CK_AHB/7 */ +#define RCU_CKADC_CKAHB_DIV8 CFG2_ADCPSC(6) /*!< ADC prescaler select CK_AHB/8 */ +#define RCU_CKADC_CKAHB_DIV9 CFG2_ADCPSC(7) /*!< ADC prescaler select CK_AHB/9 */ +#define RCU_CKADC_CKAHB_DIV10 CFG2_ADCPSC(8) /*!< ADC prescaler select CK_AHB/10 */ +#define RCU_CKADC_CKAHB_DIV11 CFG2_ADCPSC(9) /*!< ADC prescaler select CK_AHB/11 */ +#define RCU_CKADC_CKAHB_DIV12 CFG2_ADCPSC(10) /*!< ADC prescaler select CK_AHB/12 */ +#define RCU_CKADC_CKAHB_DIV13 CFG2_ADCPSC(11) /*!< ADC prescaler select CK_AHB/13 */ +#define RCU_CKADC_CKAHB_DIV14 CFG2_ADCPSC(12) /*!< ADC prescaler select CK_AHB/14 */ +#define RCU_CKADC_CKAHB_DIV15 CFG2_ADCPSC(13) /*!< ADC prescaler select CK_AHB/15 */ +#define RCU_CKADC_CKAHB_DIV16 CFG2_ADCPSC(14) /*!< ADC prescaler select CK_AHB/16 */ +#define RCU_CKADC_CKAHB_DIV17 CFG2_ADCPSC(15) /*!< ADC prescaler select CK_AHB/17 */ +#define RCU_CKADC_CKAHB_DIV18 CFG2_ADCPSC(16) /*!< ADC prescaler select CK_AHB/18 */ +#define RCU_CKADC_CKAHB_DIV19 CFG2_ADCPSC(17) /*!< ADC prescaler select CK_AHB/19 */ +#define RCU_CKADC_CKAHB_DIV20 CFG2_ADCPSC(18) /*!< ADC prescaler select CK_AHB/20 */ +#define RCU_CKADC_CKAHB_DIV21 CFG2_ADCPSC(19) /*!< ADC prescaler select CK_AHB/21 */ +#define RCU_CKADC_CKAHB_DIV22 CFG2_ADCPSC(20) /*!< ADC prescaler select CK_AHB/22 */ +#define RCU_CKADC_CKAHB_DIV23 CFG2_ADCPSC(21) /*!< ADC prescaler select CK_AHB/23 */ +#define RCU_CKADC_CKAHB_DIV24 CFG2_ADCPSC(22) /*!< ADC prescaler select CK_AHB/24 */ +#define RCU_CKADC_CKAHB_DIV25 CFG2_ADCPSC(23) /*!< ADC prescaler select CK_AHB/25 */ +#define RCU_CKADC_CKAHB_DIV26 CFG2_ADCPSC(24) /*!< ADC prescaler select CK_AHB/26 */ +#define RCU_CKADC_CKAHB_DIV27 CFG2_ADCPSC(25) /*!< ADC prescaler select CK_AHB/27 */ +#define RCU_CKADC_CKAHB_DIV28 CFG2_ADCPSC(26) /*!< ADC prescaler select CK_AHB/28 */ +#define RCU_CKADC_CKAHB_DIV29 CFG2_ADCPSC(27) /*!< ADC prescaler select CK_AHB/29 */ +#define RCU_CKADC_CKAHB_DIV30 CFG2_ADCPSC(28) /*!< ADC prescaler select CK_AHB/30 */ +#define RCU_CKADC_CKAHB_DIV31 CFG2_ADCPSC(29) /*!< ADC prescaler select CK_AHB/31 */ +#define RCU_CKADC_CKAHB_DIV32 CFG2_ADCPSC(30) /*!< ADC prescaler select CK_AHB/32 */ + +/* PLL clock source selection */ +#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock is selected as clock source of PLL */ +#define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< HXTAL is selected as clock source of PLL */ + +/* PLL clock multiplication factor */ +#define PLLMF_4 RCU_CFG0_PLLMF_4 /*!< bit 4 of PLLMF */ +#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) +#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL clock source multiply by 2 */ +#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL clock source multiply by 3 */ +#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL clock source multiply by 4 */ +#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL clock source multiply by 5 */ +#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL clock source multiply by 6 */ +#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL clock source multiply by 7 */ +#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL clock source multiply by 8 */ +#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL clock source multiply by 9 */ +#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL clock source multiply by 10 */ +#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL clock source multiply by 11 */ +#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL clock source multiply by 12 */ +#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL clock source multiply by 13 */ +#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL clock source multiply by 14 */ +#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL clock source multiply by 15 */ +#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL clock source multiply by 16 */ +#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL clock source multiply by 17 */ +#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL clock source multiply by 18 */ +#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL clock source multiply by 19 */ +#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL clock source multiply by 20 */ +#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL clock source multiply by 21 */ +#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL clock source multiply by 22 */ +#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL clock source multiply by 23 */ +#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL clock source multiply by 24 */ +#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL clock source multiply by 25 */ +#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL clock source multiply by 26 */ +#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL clock source multiply by 27 */ +#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL clock source multiply by 28 */ +#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL clock source multiply by 29 */ +#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL clock source multiply by 30 */ +#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL clock source multiply by 31 */ + +/* CKOUT Clock source selection */ +#define CFG0_CKOUTSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) +#define RCU_CKOUTSRC_NONE CFG0_CKOUTSEL(0) /*!< no clock is selected */ +#define RCU_CKOUTSRC_IRC40K CFG0_CKOUTSEL(2) /*!< IRC40K is selected as CK_OUT clock source */ +#define RCU_CKOUTSRC_LXTAL CFG0_CKOUTSEL(3) /*!< LXTAL is selected as CK_OUT clock source */ +#define RCU_CKOUTSRC_CKSYS CFG0_CKOUTSEL(4) /*!< system clock is selected as CK_OUT clock source */ +#define RCU_CKOUTSRC_IRC8M CFG0_CKOUTSEL(5) /*!< IRC8M is selected as CK_OUT clock source */ +#define RCU_CKOUTSRC_HXTAL CFG0_CKOUTSEL(6) /*!< HXTAL is selected as CK_OUT clock source */ +#define RCU_CKOUTSRC_CKPLL_DIV1 (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7)) /*!< CK_PLL is selected as CK_OUT clock source */ +#define RCU_CKOUTSRC_CKPLL_DIV2 CFG0_CKOUTSEL(7) /*!< CK_PLL/2 is selected as CK_OUT clock source */ + +/* CK_OUT divider */ +#define CFG0_CKOUTDIV(regval) (BITS(28,30) & ((uint32_t)(regval) << 28)) +#define RCU_CKOUT_DIV1 CFG0_CKOUTDIV(0) /*!< CK_OUT is divided by 1 */ +#define RCU_CKOUT_DIV2 CFG0_CKOUTDIV(1) /*!< CK_OUT is divided by 2 */ +#define RCU_CKOUT_DIV4 CFG0_CKOUTDIV(2) /*!< CK_OUT is divided by 4 */ +#define RCU_CKOUT_DIV8 CFG0_CKOUTDIV(3) /*!< CK_OUT is divided by 8 */ +#define RCU_CKOUT_DIV16 CFG0_CKOUTDIV(4) /*!< CK_OUT is divided by 16 */ +#define RCU_CKOUT_DIV32 CFG0_CKOUTDIV(5) /*!< CK_OUT is divided by 32 */ +#define RCU_CKOUT_DIV64 CFG0_CKOUTDIV(6) /*!< CK_OUT is divided by 64 */ +#define RCU_CKOUT_DIV128 CFG0_CKOUTDIV(7) /*!< CK_OUT is divided by 128 */ + +/* LXTAL drive capability */ +#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) +#define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ +#define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ +#define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ +#define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ + +/* RTC clock entry selection */ +#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock is selected */ +#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< LXTAL is selected as RTC clock source */ +#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< IRC40K is selected as RTC clock source */ +#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< HXTAL/128 is selected as RTC clock source */ + +/* PREDV0 division factor */ +#define CFG1_PREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define RCU_PREDV_DIV1 CFG1_PREDV(0) /*!< PREDV input clock source not divided */ +#define RCU_PREDV_DIV2 CFG1_PREDV(1) /*!< PREDV input clock source divided by 2 */ +#define RCU_PREDV_DIV3 CFG1_PREDV(2) /*!< PREDV input clock source divided by 3 */ +#define RCU_PREDV_DIV4 CFG1_PREDV(3) /*!< PREDV input clock source divided by 4 */ +#define RCU_PREDV_DIV5 CFG1_PREDV(4) /*!< PREDV input clock source divided by 5 */ +#define RCU_PREDV_DIV6 CFG1_PREDV(5) /*!< PREDV input clock source divided by 6 */ +#define RCU_PREDV_DIV7 CFG1_PREDV(6) /*!< PREDV input clock source divided by 7 */ +#define RCU_PREDV_DIV8 CFG1_PREDV(7) /*!< PREDV input clock source divided by 8 */ +#define RCU_PREDV_DIV9 CFG1_PREDV(8) /*!< PREDV input clock source divided by 9 */ +#define RCU_PREDV_DIV10 CFG1_PREDV(9) /*!< PREDV input clock source divided by 10 */ +#define RCU_PREDV_DIV11 CFG1_PREDV(10) /*!< PREDV input clock source divided by 11 */ +#define RCU_PREDV_DIV12 CFG1_PREDV(11) /*!< PREDV input clock source divided by 12 */ +#define RCU_PREDV_DIV13 CFG1_PREDV(12) /*!< PREDV input clock source divided by 13 */ +#define RCU_PREDV_DIV14 CFG1_PREDV(13) /*!< PREDV input clock source divided by 14 */ +#define RCU_PREDV_DIV15 CFG1_PREDV(14) /*!< PREDV input clock source divided by 15 */ +#define RCU_PREDV_DIV16 CFG1_PREDV(15) /*!< PREDV input clock source divided by 16 */ + +/* deep-sleep mode voltage */ +#define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(0) /*!< core voltage is 0.8V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(3) /*!< core voltage is 1.1V in deep-sleep mode */ + +/* USART clock source selection */ +#define CFG2_USART0SRC(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_USARTSRC_HXTAL CFG2_USART0SRC(0) /*!< CK_HXTAL is selected as USART clock source */ +#define RCU_USARTSRC_CKSYS CFG2_USART0SRC(1) /*!< CK_SYS is selected as USART clock source */ +#define RCU_USARTSRC_LXTAL CFG2_USART0SRC(2) /*!< CK_LXTAL is selected as USART clock source */ +#define RCU_USARTSRC_IRC8M CFG2_USART0SRC(3) /*!< CK_IRC8M is selected as USART clock source */ + +/* CAN clock source selection */ +#define CFG2_CAN0SRC(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define RCU_CANSRC_HXTAL CFG2_CAN0SRC(0) /*!< CK_HXTAL is selected as CAN clock source */ +#define RCU_CANSRC_PCLK2 CFG2_CAN0SRC(1) /*!< PCLK2 is selected as CAN clock source */ +#define RCU_CANSRC_PCLK2_DIV_2 CFG2_CAN0SRC(2) /*!< PCLK2/2 is selected as CAN clock source */ +#define RCU_CANSRC_IRC8M CFG2_CAN0SRC(3) /*!< CK_IRC8M is selected as CAN clock source */ + + +/* function declarations */ +/* peripherals clock configure functions */ +/* deinitialize the RCU */ +void rcu_deinit(void); +/* enable the peripherals clock */ +void rcu_periph_clock_enable(rcu_periph_enum periph); +/* disable the peripherals clock */ +void rcu_periph_clock_disable(rcu_periph_enum periph); +/* reset the peripherals */ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); +/* disable reset the peripheral */ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); +/* enable the peripherals clock when in sleep mode */ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); +/* disable the peripherals clock when in sleep mode */ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); +/* reset the BKP domain control register */ +void rcu_bkp_reset_enable(void); +/* disable the BKP domain control register reset */ +void rcu_bkp_reset_disable(void); + +/* system and peripherals clock source, system reset configure functions */ +/* configure the system clock source */ +void rcu_system_clock_source_config(uint32_t ck_sys); +/* get the system clock source */ +uint32_t rcu_system_clock_source_get(void); +/* configure the AHB prescaler selection */ +void rcu_ahb_clock_config(uint32_t ck_ahb); +/* configure the APB1 prescaler selection */ +void rcu_apb1_clock_config(uint32_t ck_apb1); +/* configure the APB2 prescaler selection */ +void rcu_apb2_clock_config(uint32_t ck_apb2); +/* configure the CK_OUT clock source and divider */ +void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div); +/* configure the PLL clock source selection and PLL multiply factor */ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); +/* enable double PLL clock */ +void rcu_double_pll_enable(void); +/* disable double PLL clock */ +void rcu_double_pll_disable(void); +/* enable RCU system reset */ +void rcu_system_reset_enable(uint32_t reset_source); +/* disable RCU system reset */ +void rcu_system_reset_disable(uint32_t reset_source); +/* configure the ADC division factor */ +void rcu_adc_clock_config(uint32_t adc_psc); +/* configure the RTC clock source selection */ +void rcu_rtc_clock_config(uint32_t rtc_clock_source); +/* configure the USART clock source selection */ +void rcu_usart_clock_config(uint32_t usart_periph, uint32_t usart_clock_source); +/* configure the CAN clock source selection */ +void rcu_can_clock_config(uint32_t can_periph, uint32_t can_clock_source); + +/* LXTAL, IRC8M, PLL and other oscillator configure functions */ +/* configure the LXTAL drive capability */ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); +/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); +/* turn on the oscillator */ +void rcu_osci_on(rcu_osci_type_enum osci); +/* turn off the oscillator */ +void rcu_osci_off(rcu_osci_type_enum osci); +/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); +/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); +/* configure the HXTAL frequency scale select */ +void rcu_hxtal_frequency_scale_select(uint32_t hxtal_scal); +/* configure the HXTAL divider used as input of PLL */ +void rcu_hxtal_prediv_config(uint32_t hxtal_prediv); +/* set the IRC8M adjust value */ +void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); + +/* clock monitor configure functions */ +/* enable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_enable(void); +/* disable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_disable(void); +/* enable the LXTAL clock monitor */ +void rcu_lxtal_clock_monitor_enable(void); +/* disable the LXTAL clock monitor */ +void rcu_lxtal_clock_monitor_disable(void); +/* enable the PLL clock monitor */ +void rcu_pll_clock_monitor_enable(void); +/* disable the PLL clock monitor */ +void rcu_pll_clock_monitor_disable(void); + +/* voltage configure and clock frequency get functions */ +/* unlock the voltage key */ +void rcu_voltage_key_unlock(void); +/* set the deep sleep mode voltage */ +void rcu_deepsleep_voltage_set(uint32_t dsvol); +/* get the system clock, bus and peripheral clock frequency */ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); + +/* flag & interrupt functions */ +/* get the clock stabilization and peripheral reset flags */ +FlagStatus rcu_flag_get(rcu_flag_enum flag); +/* clear the reset flag */ +void rcu_all_reset_flag_clear(void); +/* get the clock stabilization interrupt and ckm flags */ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); +/* clear the interrupt flags */ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag); +/* enable the stabilization interrupt */ +void rcu_interrupt_enable(rcu_int_enum interrupt); +/* disable the stabilization interrupt */ +void rcu_interrupt_disable(rcu_int_enum interrupt); +#endif /* GD32A50X_RCU_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_rtc.h b/gd32a50x/standard_peripheral/include/gd32a50x_rtc.h new file mode 100644 index 0000000..a7a9789 --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_rtc.h @@ -0,0 +1,142 @@ +/*! + \file gd32a50x_rtc.h + \brief definitions for the RTC + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_RTC_H +#define GD32A50X_RTC_H + +#include "gd32a50x.h" + +/* RTC definitions */ +#define RTC RTC_BASE + +/* registers definitions */ +#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ +#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ +#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ +#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ +#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ +#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ +#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ +#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ +#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ +#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */ + +/* bits definitions */ +/* RTC_INTEN */ +#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */ +#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */ +#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */ + +/* RTC_CTL */ +#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */ +#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */ +#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */ +#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */ +#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */ +#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ + +/* RTC_PSC */ +#define RTC_PSCH_PSC BITS(0, 3) /*!< prescaler high value */ +#define RTC_PSCL_PSC BITS(0, 15) /*!< prescaler low value */ + +/* RTC_DIV */ +#define RTC_DIVH_DIV BITS(0, 3) /*!< divider high value */ +#define RTC_DIVL_DIV BITS(0, 15) /*!< divider low value */ + +/* RTC_CNT */ +#define RTC_CNTH_CNT BITS(0, 15) /*!< counter high value */ +#define RTC_CNTL_CNT BITS(0, 15) /*!< counter low value */ + +/* RTC_ALRM */ +#define RTC_ALRMH_ALRM BITS(0, 15) /*!< alarm high value */ +#define RTC_ALRML_ALRM BITS(0, 15) /*!< alarm low value */ + +/* constants definitions */ +#define RTC_HIGH_VALUE 0x000F0000U /*!< RTC high value */ +#define RTC_LOW_VALUE 0x0000FFFFU /*!< RTC low value */ + +/* RTC interrupt definitions */ +#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */ +#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */ +#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */ + +/* RTC interrupt flag definitions */ +#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ +#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ +#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ + +/* RTC flag definitions */ +#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ +#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ +#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ +#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */ +#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */ + +/* function declarations */ +/* enter RTC configuration mode */ +void rtc_configuration_mode_enter(void); +/* exit RTC configuration mode */ +void rtc_configuration_mode_exit(void); + +/* wait RTC last write operation finished flag set */ +void rtc_lwoff_wait(void); +/* wait RTC registers synchronized flag set */ +void rtc_register_sync_wait(void); + +/* get RTC counter value */ +uint32_t rtc_counter_get(void); +/* set RTC counter value */ +void rtc_counter_set(uint32_t cnt); + +/* set RTC prescaler value */ +void rtc_prescaler_set(uint32_t psc); +/* set RTC alarm value */ +void rtc_alarm_config(uint32_t alarm); +/* get RTC divider value */ +uint32_t rtc_divider_get(void); + +/* enable RTC interrupt */ +void rtc_interrupt_enable(uint32_t interrupt); +/* disable RTC interrupt */ +void rtc_interrupt_disable(uint32_t interrupt); +/* get RTC flag status */ +FlagStatus rtc_flag_get(uint32_t flag); +/* clear RTC flag status */ +void rtc_flag_clear(uint32_t flag); +/* get RTC interrupt flag status */ +FlagStatus rtc_interrupt_flag_get(uint32_t flag); +/* clear RTC interrupt flag status */ +void rtc_interrupt_flag_clear(uint32_t flag); + +#endif /* GD32A50X_RTC_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_spi.h b/gd32a50x/standard_peripheral/include/gd32a50x_spi.h new file mode 100644 index 0000000..a122fb1 --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_spi.h @@ -0,0 +1,375 @@ +/*! + \file gd32a50x_spi.h + \brief definitions for the SPI + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_SPI_H +#define GD32A50X_SPI_H +#include "gd32a50x.h" + +/* SPIx(x=0,1) definitions */ +#define SPI0 (SPI_BASE + 0x0000F800U) +#define SPI1 SPI_BASE +#define I2S1_ADD I2S_ADD_BASE + +/* registers definitions */ +#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */ +#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/ +#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */ +#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */ +#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */ +#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */ +#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */ +#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */ +#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */ +#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register(only SPI0) */ + +/* I2S_ADD registers definitions */ +#define I2S_ADD_CTL0(i2sx_add) REG32((i2sx_add) + 0x00000000U) /*!< I2S_ADD control register 0 */ +#define I2S_ADD_CTL1(i2sx_add) REG32((i2sx_add) + 0x00000004U) /*!< I2S_ADD control register 1*/ +#define I2S_ADD_STAT(i2sx_add) REG32((i2sx_add) + 0x00000008U) /*!< I2S_ADD status register */ +#define I2S_ADD_DATA(i2sx_add) REG32((i2sx_add) + 0x0000000CU) /*!< I2S_ADD data register */ +#define I2S_ADD_CRCPOLY(i2sx_add) REG32((i2sx_add) + 0x00000010U) /*!< I2S_ADD CRC polynomial register */ +#define I2S_ADD_RCRC(i2sx_add) REG32((i2sx_add) + 0x00000014U) /*!< I2S_ADD receive CRC register */ +#define I2S_ADD_TCRC(i2sx_add) REG32((i2sx_add) + 0x00000018U) /*!< I2S_ADD transmit CRC register */ +#define I2S_ADD_I2SCTL(i2sx_add) REG32((i2sx_add) + 0x0000001CU) /*!< I2S_ADD I2S control register */ +#define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x00000020U) /*!< I2S_ADD I2S clock prescaler register */ + +/* bits definitions */ +/* SPI_CTL0 */ +#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ +#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ +#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ +#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ +#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ +#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ +#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ +#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ +#define SPI_CTL0_RO BIT(10) /*!< receive only */ +#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ +#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ +#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ +#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ +#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ + +/* SPI_CTL1 */ +#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer DMA enable */ +#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer DMA enable */ +#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ +#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */ +#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ +#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ +#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ +#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ + +/* SPI_STAT */ +#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ +#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ +#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ +#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ +#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ +#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ +#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ +#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ +#define SPI_STAT_FERR BIT(8) /*!< format error bit */ + +/* SPI_DATA */ +#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ + +/* SPI_CRCPOLY */ +#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial register */ + +/* SPI_RCRC */ +#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC register */ + +/* SPI_TCRC */ +#define SPI_TCRC_TCR BITS(0,15) /*!< RX CRC register */ + +/* SPI_I2SCTL */ +#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ +#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ +#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ +#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ +#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ +#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ +#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ +#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ + +/* SPI_I2SPSC */ +#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ +#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ +#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ + +/* SPI_QCTL(only available in SPI0) */ +#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ +#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ +#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ + +/* constants definitions */ +/* SPI and I2S parameter struct definitions */ +typedef struct +{ + uint32_t device_mode; /*!< SPI master or slave */ + uint32_t trans_mode; /*!< SPI transtype */ + uint32_t frame_size; /*!< SPI frame size */ + uint32_t nss; /*!< SPI NSS control by handware or software */ + uint32_t endian; /*!< SPI big endian or little endian */ + uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ + uint32_t prescale; /*!< SPI prescale factor */ +}spi_parameter_struct; + +/* SPI mode definitions */ +#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ +#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ + +/* SPI bidirectional transfer direction */ +#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ +#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ + +/* SPI transmit type */ +#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ +#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ +#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ +#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ + +/* SPI frame size */ +#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ +#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ + +/* SPI NSS control mode */ +#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */ +#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ + +/* SPI transmit way */ +#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ +#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ + +/* SPI clock phase and polarity */ +#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ +#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ +#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ +#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ + +/* SPI clock prescaler factor */ +#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescaler factor is 2 */ +#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescaler factor is 4 */ +#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescaler factor is 8 */ +#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescaler factor is 16 */ +#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescaler factor is 32 */ +#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescaler factor is 64 */ +#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescaler factor is 128 */ +#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescaler factor is 256 */ + +/* I2S audio sample rate */ +#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ +#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ +#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ +#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ +#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ +#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ +#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ +#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ +#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ + +/* I2S frame format */ +#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) +#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ +#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ + +/* I2S master clock output */ +#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ +#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ + +/* I2S operation mode */ +#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ +#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ +#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ +#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ + +/* I2S standard */ +#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ +#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ +#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ +#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ +#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ + +/* I2S clock polarity */ +#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ +#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ + +/* SPI DMA constants definitions */ +#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ +#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ + +/* SPI CRC constants definitions */ +#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ +#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ + +/* SPI/I2S interrupt enable/disable constants definitions */ +#define SPI_I2S_INT_TBE SPI_CTL1_TBEIE /*!< transmit buffer empty interrupt */ +#define SPI_I2S_INT_RBNE SPI_CTL1_RBNEIE /*!< receive buffer not empty interrupt */ +#define SPI_I2S_INT_ERR SPI_CTL1_ERRIE /*!< error interrupt */ + +/* SPI/I2S interrupt flag constants definitions */ +#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ +#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ +#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ +#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ +#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ + +/* SPI/I2S flag definitions */ +#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ +#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ +#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ +#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error flag */ + +/* SPI flag definitions */ +#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ +#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ +#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ +#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error flag */ + +/* function declarations */ +/* SPI deinitialization and initialization functions */ +/* reset SPI and I2S */ +void spi_i2s_deinit(uint32_t spi_periph); +/* initialize the parameters of SPI structure with the default values */ +void spi_struct_para_init(spi_parameter_struct *spi_struct); +/* initialize SPI parameters */ +void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct); +/* enable SPI */ +void spi_enable(uint32_t spi_periph); +/* disable SPI */ +void spi_disable(uint32_t spi_periph); + +/* I2S initialization functions */ +/* initialize I2S parameter */ +void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl); +/* configure I2S prescaler */ +void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout); +/* enable I2S */ +void i2s_enable(uint32_t spi_periph); +/* disable I2S */ +void i2s_disable(uint32_t spi_periph); + +/* NSS functions */ +/* enable SPI NSS output */ +void spi_nss_output_enable(uint32_t spi_periph); +/* disable SPI NSS output */ +void spi_nss_output_disable(uint32_t spi_periph); +/* SPI NSS pin high level in software mode */ +void spi_nss_internal_high(uint32_t spi_periph); +/* SPI NSS pin low level in software mode */ +void spi_nss_internal_low(uint32_t spi_periph); + +/* DMA functions */ +/* enable SPI DMA */ +void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma); +/* disable SPI DMA */ +void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma); + +/* communication functions */ +/* configure SPI data frame format */ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); +/* configure SPI bidirectional transfer direction */ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); +/* SPI transmit data */ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); +/* SPI receive data */ +uint16_t spi_i2s_data_receive(uint32_t spi_periph); + +/* SPI CRC functions */ +/* set SPI CRC polynomial */ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); +/* get SPI CRC polynomial */ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph); +/* turn on SPI CRC function */ +void spi_crc_on(uint32_t spi_periph); +/* turn off SPI CRC function */ +void spi_crc_off(uint32_t spi_periph); +/* SPI next data is CRC value */ +void spi_crc_next(uint32_t spi_periph); +/* get SPI CRC send value or receive value */ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); + +/* SPI TI mode functions */ +/* enable SPI TI mode */ +void spi_ti_mode_enable(uint32_t spi_periph); +/* disable SPI TI mode */ +void spi_ti_mode_disable(uint32_t spi_periph); + +/* SPI NSS pulse mode functions */ +/* enable SPI NSS pulse mode */ +void spi_nssp_mode_enable(uint32_t spi_periph); +/* disable SPI NSS pulse mode */ +void spi_nssp_mode_disable(uint32_t spi_periph); + +/* quad wire SPI functions */ +/* enable quad wire SPI */ +void spi_quad_enable(uint32_t spi_periph); +/* disable quad wire SPI */ +void spi_quad_disable(uint32_t spi_periph); +/* enable quad wire SPI write */ +void spi_quad_write_enable(uint32_t spi_periph); +/* enable quad wire SPI read */ +void spi_quad_read_enable(uint32_t spi_periph); +/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ +void spi_quad_io23_output_enable(uint32_t spi_periph); +/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ +void spi_quad_io23_output_disable(uint32_t spi_periph); + +/* flag and interrupt functions */ +/* get SPI and I2S flag status */ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); +/* enable SPI and I2S interrupt */ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); +/* disable SPI and I2S interrupt */ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S interrupt status */ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); +/* clear SPI CRC error flag status */ +void spi_crc_error_clear(uint32_t spi_periph); + +#endif /* GD32A50X_SPI_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_syscfg.h b/gd32a50x/standard_peripheral/include/gd32a50x_syscfg.h new file mode 100644 index 0000000..275a0ee --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_syscfg.h @@ -0,0 +1,301 @@ +/*! + \file gd32a50x_syscfg.h + \brief definitions for the SYSCFG + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_SYSCFG_H +#define GD32A50X_SYSCFG_H + +#include "gd32a50x.h" + +/* SYSCFG definitions */ +#define SYSCFG SYSCFG_BASE + +/* registers definitions */ +#define SYSCFG_CFG0 REG32(SYSCFG + 0x00000000U) /*!< system configuration register 0 */ +#define SYSCFG_CFG1 REG32(SYSCFG + 0x00000004U) /*!< system configuration register 1 */ +#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x00000008U) /*!< EXTI sources selection register 0 */ +#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0000000CU) /*!< EXTI sources selection register 1 */ +#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x00000010U) /*!< EXTI sources selection register 2 */ +#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x00000014U) /*!< EXTI sources selection register 3 */ +#define SYSCFG_CFG2 REG32(SYSCFG + 0x00000018U) /*!< system configuration register 2 */ +#define SYSCFG_STAT REG32(SYSCFG + 0x0000001CU) /*!< system status register */ +#define SYSCFG_CFG3 REG32(SYSCFG + 0x00000028U) /*!< system configuration register 3 */ +#define SYSCFG_TIMERINSEL REG32(SYSCFG + 0x0000002CU) /*!< TIMER input source selection register */ + +/* bits definitions */ +/* SYSCFG_CFG0 */ +#define SYSCFG_CFG0_BOOT_MODE BITS(0,1) /*!< SYSCFG memory remap configuration */ +#define SYSCFG_CFG0_PA9_PA12_RMP BIT(4) /*!< PA9 and PA12 remapping bit for small packages (32 pins) */ +#define SYSCFG_CFG0_BOOT0_PF0_RMP BIT(6) /*!< BOOT0 and PF0 remapping bit */ + +/* SYSCFG_CFG1 */ +#define SYSCFG_CFG1_ADC1CH14RMP BIT(28) /*!< ADC1 channel 14 remapping bit */ +#define SYSCFG_CFG1_ADC1CH15RMP BIT(29) /*!< ADC1 channel 15 remapping bit */ +#define SYSCFG_CFG1_ADC0CH8RMP BIT(30) /*!< ADC0 channel 8 remapping bit */ +#define SYSCFG_CFG1_ADC0CH9RMP BIT(31) /*!< ADC0 channel 9 remapping bit */ + +/* SYSCFG_EXTISS0 */ +#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */ +#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */ +#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */ +#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */ + +/* SYSCFG_EXTISS1 */ +#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */ +#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */ +#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */ +#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */ + +/* SYSCFG_EXTISS2 */ +#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */ +#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */ +#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */ +#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */ + +/* SYSCFG_EXTISS3 */ +#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */ +#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */ +#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */ +#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */ + +/* SSYSCFG_CFG2 */ +#define SYSCFG_CFG2_LOCKUP_LOCK BIT(0) /*!< Cortex-M33 LOCKUP output lock bit */ +#define SYSCFG_CFG2_SRAM_ECC_ERROR_LOCK BIT(1) /*!< SRAM ECC check error lock bit */ +#define SYSCFG_CFG2_LVD_LOCK BIT(2) /*!< LVD lock bit */ + +/* SYSCFG_STAT */ +#define SYSCFG_STAT_SRAMECCMEIF BIT(0) /*!< SRAM multi-bits non-correction event flag */ +#define SYSCFG_STAT_SRAMECCSEIF BIT(1) /*!< SRAM single bit correction event flag */ +#define SYSCFG_STAT_FLASHECCIF BIT(2) /*!< Flash ECC NMI interrupt flag */ +#define SYSCFG_STAT_CKMNMIIF BIT(3) /*!< HXTAL clock moniotor NMI interrupt flag */ +#define SYSCFG_STAT_NMIPINIF BIT(4) /*!< NMI interrupt flag from nmi pin */ + +/* SSYSCFG_CFG3 */ +#define SYSCFG_CFG3_SRAMECCMEIE BIT(0) /*!< SRAM multi-bits non-correction NMI interrupt enable */ +#define SYSCFG_CFG3_SRAMECCSEIE BIT(1) /*!< SRAM single bit correction interrupt enable */ +#define SYSCFG_CFG3_FLASHECCIE BIT(2) /*!< Flash ECC NMI interrupt enable */ +#define SYSCFG_CFG3_CKMNMIIE BIT(3) /*!< HXTAL clock moniotor NMI interrupt enable */ +#define SYSCFG_CFG3_NMIPINIE BIT(4) /*!< NMI pin interrupt enable */ +#define SYSCFG_CFG3_SRAMECCSERRBITS BITS(12,17) /*!< which one bit has an SRAM ECC single-bit correctable error */ +#define SYSCFG_CFG3_SRAMECCEADDR BITS(18,31) /*!< record the faulting system address (Address[15:0] >> 2) where the last SRAM ECC event on SRAM occurred. */ + +/* SYSCFG_TIMERINSEL */ +#define SYSCFG_TIMERINSEL_TIMER7_CH0N_SEL BIT(0) /*!< TIMER7 channel 0 complementary input selection */ +#define SYSCFG_TIMERINSEL_TIMER20_BKIN3_SEL BIT(2) /*!< TIMER20 break input 3 selection */ +#define SYSCFG_TIMERINSEL_TIMER20_BKIN2_SEL BIT(3) /*!< TIMER20 break input 2 selection */ +#define SYSCFG_TIMERINSEL_TIMER20_BKIN1_SEL BIT(4) /*!< TIMER20 break input 1 selection */ +#define SYSCFG_TIMERINSEL_TIMER20_BKIN0_SEL BIT(5) /*!< TIMER20 break input 0 selection */ +#define SYSCFG_TIMERINSEL_TIMER19_BKIN3_SEL BIT(6) /*!< TIMER19 break input 3 selection */ +#define SYSCFG_TIMERINSEL_TIMER19_BKIN2_SEL BIT(7) /*!< TIMER19 break input 2 selection */ +#define SYSCFG_TIMERINSEL_TIMER19_BKIN1_SEL BIT(8) /*!< TIMER19 break input 1 selection */ +#define SYSCFG_TIMERINSEL_TIMER19_BKIN0_SEL BIT(9) /*!< TIMER19 break input 0 selection */ +#define SYSCFG_TIMERINSEL_TIMER7_BKIN3_SEL BIT(14) /*!< TIMER7 break input 3 selection */ +#define SYSCFG_TIMERINSEL_TIMER7_BKIN2_SEL BIT(15) /*!< TIMER7 break input 2 selection */ +#define SYSCFG_TIMERINSEL_TIMER7_BKIN1_SEL BIT(16) /*!< TIMER7 break input 1 selection */ +#define SYSCFG_TIMERINSEL_TIMER7_BKIN0_SEL BIT(17) /*!< TIMER7 break input 0 selection */ +#define SYSCFG_TIMERINSEL_TIMER0_BKIN3_SEL BIT(18) /*!< TIMER0 break input 3 selection */ +#define SYSCFG_TIMERINSEL_TIMER0_BKIN2_SEL BIT(19) /*!< TIMER0 break input 2 selection */ +#define SYSCFG_TIMERINSEL_TIMER0_BKIN1_SEL BIT(20) /*!< TIMER0 break input 1 selection */ +#define SYSCFG_TIMERINSEL_TIMER0_BKIN0_SEL BIT(21) /*!< TIMER0 break input 0 selection */ +#define SYSCFG_TIMERINSEL_TIMER20_ETI_SEL BITS(22,23) /*!< TIMER20 external trigger selection */ +#define SYSCFG_TIMERINSEL_TIMER19_ETI_SEL BITS(24,25) /*!< TIMER19 external trigger selection */ +#define SYSCFG_TIMERINSEL_TIMER7_ETI_SEL BITS(28,29) /*!< TIMER7 external trigger selection */ +#define SYSCFG_TIMERINSEL_TIMER0_ETI_SEL BITS(30,31) /*!< TIMER0 external trigger selection */ + +/* constants definitions */ +/* boot mode definitions */ +#define SYSCFG_BOOTMODE_FLASH ((uint8_t)0x00U) /*!< boot from main flash */ +#define SYSCFG_BOOTMODE_SYSTEM ((uint8_t)0x01U) /*!< boot from system flash memory */ +#define SYSCFG_BOOTMODE_SRAM ((uint8_t)0x03U) /*!< boot from embedded SRAM */ + +/* PA9/PA12 remap definitions */ +#define SYSCFG_PA9_PA12_REMAP SYSCFG_CFG0_PA9_PA12_RMP /*!< PA9/PA12 pins are mapping on PA10/PA11 pins */ + +/* PF0/BOOT0 remap definitions */ +#define SYSCFG_BOOT0_REMAP_PF0 SYSCFG_CFG0_BOOT0_PF0_RMP /*!< PF0 pin is mapping on the BOOT0 pin */ + +/* EXTI source select definition */ +#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select register 0 */ +#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select register 1 */ +#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select register 2 */ +#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select register 3 */ + +/* EXTI source select mask bits definition */ +#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */ + +/* EXTI source select jumping step definition */ +#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */ + +/* EXTI source select moving step definition */ +#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP)) /*!< EXTI source select moving step */ + +/* EXTI source port definitions */ +#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */ +#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */ +#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */ +#define EXTI_SOURCE_GPIOD ((uint8_t)0x03U) /*!< EXTI GPIOD configuration */ +#define EXTI_SOURCE_GPIOE ((uint8_t)0x04U) /*!< EXTI GPIOE configuration */ +#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */ + +/* EXTI source pin definitions */ +#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */ +#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */ +#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */ +#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */ +#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */ +#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */ +#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */ +#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */ +#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */ +#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */ +#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */ +#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */ +#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */ +#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */ +#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */ +#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */ + +/* lock definitions */ +#define SYSCFG_LOCK_LOCKUP SYSCFG_CFG2_LOCKUP_LOCK /*!< LOCKUP output lock */ +#define SYSCFG_LOCK_SRAM_ECC_ERROR SYSCFG_CFG2_SRAM_ECC_ERROR_LOCK /*!< SRAM ECC error lock */ +#define SYSCFG_LOCK_LVD SYSCFG_CFG2_LVD_LOCK /*!< LVD lock */ + +/* TIMER external trigger definitions */ +#define TIMER_ETI_TRG0 ((uint8_t)0x00U) /*!< TIMER external trigger 0 */ +#define TIMER_ETI_TRG1 ((uint8_t)0x01U) /*!< TIMER external trigger 1 */ +#define TIMER_ETI_TRG2 ((uint8_t)0x02U) /*!< TIMER external trigger 2 */ +#define TIMER_ETI_TRG_NONE ((uint8_t)0x03U) /*!< do not seclet TIMER external trigger source */ + +/* TIMERx break input y */ +#define TIMER20_BKIN3_TRIG SYSCFG_TIMERINSEL_TIMER20_BKIN3_SEL /*!< TIMER20 break input 3 selection */ +#define TIMER20_BKIN2_TRIG SYSCFG_TIMERINSEL_TIMER20_BKIN2_SEL /*!< TIMER20 break input 2 selection */ +#define TIMER20_BKIN1_TRIG SYSCFG_TIMERINSEL_TIMER20_BKIN1_SEL /*!< TIMER20 break input 1 selection */ +#define TIMER20_BKIN0_TRIG SYSCFG_TIMERINSEL_TIMER20_BKIN0_SEL /*!< TIMER20 break input 0 selection */ +#define TIMER19_BKIN3_TRIG SYSCFG_TIMERINSEL_TIMER19_BKIN3_SEL /*!< TIMER19 break input 3 selection */ +#define TIMER19_BKIN2_TRIG SYSCFG_TIMERINSEL_TIMER19_BKIN2_SEL /*!< TIMER19 break input 2 selection */ +#define TIMER19_BKIN1_TRIG SYSCFG_TIMERINSEL_TIMER19_BKIN1_SEL /*!< TIMER19 break input 1 selection */ +#define TIMER19_BKIN0_TRIG SYSCFG_TIMERINSEL_TIMER19_BKIN0_SEL /*!< TIMER19 break input 0 selection */ +#define TIMER7_BKIN3_TRIG SYSCFG_TIMERINSEL_TIMER7_BKIN3_SEL /*!< TIMER7 break input 3 selection */ +#define TIMER7_BKIN2_TRIG SYSCFG_TIMERINSEL_TIMER7_BKIN2_SEL /*!< TIMER7 break input 2 selection */ +#define TIMER7_BKIN1_TRIG SYSCFG_TIMERINSEL_TIMER7_BKIN1_SEL /*!< TIMER7 break input 1 selection */ +#define TIMER7_BKIN0_TRIG SYSCFG_TIMERINSEL_TIMER7_BKIN0_SEL /*!< TIMER7 break input 0 selection */ +#define TIMER0_BKIN3_TRIG SYSCFG_TIMERINSEL_TIMER0_BKIN3_SEL /*!< TIMER0 break input 3 selection */ +#define TIMER0_BKIN2_TRIG SYSCFG_TIMERINSEL_TIMER0_BKIN2_SEL /*!< TIMER0 break input 2 selection */ +#define TIMER0_BKIN1_TRIG SYSCFG_TIMERINSEL_TIMER0_BKIN1_SEL /*!< TIMER0 break input 1 selection */ +#define TIMER0_BKIN0_TRIG SYSCFG_TIMERINSEL_TIMER0_BKIN0_SEL /*!< TIMER0 break input 0 selection */ + +/* TIMER7 channel0 complementary input source definitions */ +#define TIMER7CH0N_TIMER7CH0_TIMER0CH0_IN SYSCFG_TIMERINSEL_TIMER7_CH0N_SEL /*!< exclusive or of TIMER7_CH0_IN,TIMER7_CH0N_IN,and TIMER0_CH0_IN */ +#define TIMER7_CH0N_IN (~SYSCFG_TIMERINSEL_TIMER7_CH0N_SEL) /*!< TIMER7_CH0N_IN */ + +/* SYSCFG flag definitions */ +#define SYSCFG_FLAG_SRAMECCMERR SYSCFG_STAT_SRAMECCMEIF /*!< SRAM multi-bits non-correction ECC error flag */ +#define SYSCFG_FLAG_SRAMECCSERR SYSCFG_STAT_SRAMECCSEIF /*!< SRAM single bit correction ECC error flag */ +#define SYSCFG_FLAG_FLASHECCERR SYSCFG_STAT_FLASHECCIF /*!< FLASH ECC NMI error flag */ +#define SYSCFG_FLAG_CKMNMIERR SYSCFG_STAT_CKMNMIIF /*!< HXTAL clock monitor NMI error flag */ +#define SYSCFG_FLAG_NMIPINERR SYSCFG_STAT_NMIPINIF /*!< NMI pin error flag */ + +/* SYSCFG interrupt flag constants definitions */ +#define SYSCFG_INT_FLAG_SRAMECCMERR SYSCFG_STAT_SRAMECCMEIF /*!< SRAM multi-bits non-correction ECC error interrupt flag */ +#define SYSCFG_INT_FLAG_SRAMECCSERR SYSCFG_STAT_SRAMECCSEIF /*!< SRAM single bit correction ECC error interrupt flag */ +#define SYSCFG_INT_FLAG_FLASHECCERR SYSCFG_STAT_FLASHECCIF /*!< FLASH ECC NMI error interrupt flag */ +#define SYSCFG_INT_FLAG_CKMNMIERR SYSCFG_STAT_CKMNMIIF /*!< HXTAL clock monitor NMI error interrupt flag */ +#define SYSCFG_INT_FLAG_NMIPINERR SYSCFG_STAT_NMIPINIF /*!< NMI pin error interrupt flag */ + +/* SYSCFG interrupt enable/disable constants definitions */ +#define SYSCFG_INT_SRAMECCME SYSCFG_CFG3_SRAMECCMEIE /*!< SRAM multi-bits non-correction ECC error */ +#define SYSCFG_INT_SRAMECCSE SYSCFG_CFG3_SRAMECCSEIE /*!< SRAM single bit correction ECC error */ +#define SYSCFG_INT_FLASHECCE SYSCFG_CFG3_FLASHECCIE /*!< FLASH ECC NMI error */ +#define SYSCFG_INT_CKMNMI SYSCFG_CFG3_CKMNMIIE /*!< receive buffer not empty interrupt */ +#define SYSCFG_INT_NMIPIN SYSCFG_CFG3_NMIPINIE /*!< HXTAL clock monitor NMI error */ + +typedef enum { + ADC1_IN14_REMAP = 1, /*!< ADC1 channel 14 remapping */ + ADC1_IN15_REMAP, /*!< ADC1 channel 15 remapping */ + ADC0_IN8_REMAP, /*!< ADC0 channel 8 remapping */ + ADC0_IN9_REMAP /*!< ADC0 channel 9 remapping */ +} syscfg_adcx_chy_enum; + +typedef enum { + TIMER0SEL = 1, /*!< select TIMER0 */ + TIMER7SEL, /*!< select TIMER7 */ + TIMER19SEL, /*!< select TIMER19 */ + TIMER20SEL, /*!< select TIMER20 */ +} syscfg_timersel_enum; + +/* function declarations */ +/* initialization functions */ +/* reset the SYSCFG registers */ +void syscfg_deinit(void); + +/* configure the GPIO pin as EXTI Line */ +void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin); + +/* enable remap pin function */ +void syscfg_pin_remap_enable(uint32_t remap_pin); +/* disable remap pin function */ +void syscfg_pin_remap_disable(uint32_t remap_pin); +/* configure ADC channel GPIO pin remap function */ +void syscfg_adc_ch_remap_config(syscfg_adcx_chy_enum adcx_iny_remap, ControlStatus newvalue); + +/* select TIMER external trigger source */ +void syscfg_timer_eti_sel(syscfg_timersel_enum timer_num, uint32_t eti_num); +/* select TRIGSEL as TIMER break input source */ +void syscfg_timer_bkin_select_trigsel(uint32_t bkin_source); +/* select GPIO as TIMER break input source */ +void syscfg_timer_bkin_select_gpio(uint32_t bkin_source); +/* select TIMER7 channel0 complementary input source */ +void syscfg_timer7_ch0n_select(uint32_t timer7_ch0n_in); + +/* configure TIMER0/7/19/20 break input to the selected parameter connection */ +void syscfg_lock_config(uint32_t syscfg_lock); + +/* flag and interrupt functions */ +/* get SYSCFG flags */ +FlagStatus syscfg_flag_get(uint32_t syscfg_flag); +/* clear SYSCFG flags */ +void syscfg_flag_clear(uint32_t syscfg_flag); +/* enable SYSCFG interrupts */ +void syscfg_interrupt_enable(uint32_t interrupt); +/* disable SYSCFG interrupts */ +void syscfg_interrupt_disable(uint32_t interrupt); +/* get SYSCFG interrupt flag status */ +FlagStatus syscfg_interrupt_flag_get(uint32_t interrupt); +/* get the current boot mode */ +uint8_t syscfg_bootmode_get(void); +/* get the address where SRAM ECC error occur on */ +uint16_t syscfg_sram_ecc_address_get(void); +/* get the bit which has SRAM ECC signle error */ +uint8_t syscfg_sram_ecc_bit_get(void); + +#endif /* GD32A50X_SYSCFG_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_timer.h b/gd32a50x/standard_peripheral/include/gd32a50x_timer.h new file mode 100644 index 0000000..c555a58 --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_timer.h @@ -0,0 +1,1135 @@ +/*! + \file gd32a50x_timer.h + \brief definitions for the TIMER + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_TIMER_H +#define GD32A50X_TIMER_H + +#include "gd32a50x.h" + +/* TIMERx(x=0,1,5,6,7,19,20) definitions */ +#define TIMER0 (TIMER_BASE + 0x00012C00U) /*!< TIMER0 base address */ +#define TIMER1 TIMER_BASE /*!< TIMER1 base address */ +#define TIMER5 (TIMER_BASE + 0x00001000U) /*!< TIMER5 base address */ +#define TIMER6 (TIMER_BASE + 0x00001400U) /*!< TIMER6 base address */ +#define TIMER7 (TIMER_BASE + 0x00013400U) /*!< TIMER7 base address */ +#define TIMER19 (TIMER_BASE + 0x00015000U) /*!< TIMER19 base address */ +#define TIMER20 (TIMER_BASE + 0x00015400U) /*!< TIMER20 base address */ + +/* registers definitions */ +#define TIMER_CTL0(timerx) REG32((timerx) + 0x00000000U) /*!< TIMER control register 0 */ +#define TIMER_CTL1(timerx) REG32((timerx) + 0x00000004U) /*!< TIMER control register 1 */ +#define TIMER_SMCFG(timerx) REG32((timerx) + 0x00000008U) /*!< TIMER slave mode configuration register */ +#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0000000CU) /*!< TIMER DMA and interrupt enable register */ +#define TIMER_INTF(timerx) REG32((timerx) + 0x00000010U) /*!< TIMER interrupt flag register */ +#define TIMER_SWEVG(timerx) REG32((timerx) + 0x00000014U) /*!< TIMER software event generation register */ +#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x00000018U) /*!< TIMER channel control register 0 */ +#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x0000001CU) /*!< TIMER channel control register 1 */ +#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x00000020U) /*!< TIMER channel control register 2 */ +#define TIMER_CNT(timerx) REG32((timerx) + 0x00000024U) /*!< TIMER counter register */ +#define TIMER_PSC(timerx) REG32((timerx) + 0x00000028U) /*!< TIMER prescaler register */ +#define TIMER_CAR(timerx) REG32((timerx) + 0x0000002CU) /*!< TIMER counter auto reload register */ +#define TIMER_CREP(timerx) REG32((timerx) + 0x00000030U) /*!< TIMER counter repetition register */ +#define TIMER_CH0CV(timerx) REG32((timerx) + 0x00000034U) /*!< TIMER channel 0 capture or compare value register */ +#define TIMER_CH1CV(timerx) REG32((timerx) + 0x00000038U) /*!< TIMER channel 1 capture or compare value register */ +#define TIMER_CH2CV(timerx) REG32((timerx) + 0x0000003CU) /*!< TIMER channel 2 capture or compare value register */ +#define TIMER_CH3CV(timerx) REG32((timerx) + 0x00000040U) /*!< TIMER channel 3 capture or compare value register */ +#define TIMER_CCHP(timerx) REG32((timerx) + 0x00000044U) /*!< TIMER channel complementary protection register */ +#define TIMER_MCHCTL0(timerx) REG32((timerx) + 0x00000048U) /*!< TIMER multi mode channel control register 0 */ +#define TIMER_MCHCTL1(timerx) REG32((timerx) + 0x0000004CU) /*!< TIMER multi mode channel control register 1 */ +#define TIMER_MCHCTL2(timerx) REG32((timerx) + 0x00000050U) /*!< TIMER multi mode channel control register 2 */ +#define TIMER_IRMP(timerx) REG32((timerx) + 0x00000050U) /*!< TIMER channel input remap register (only for TIMER1) */ +#define TIMER_MCH0CV(timerx) REG32((timerx) + 0x00000054U) /*!< TIMER multi mode channel 0 capture or compare value register */ +#define TIMER_MCH1CV(timerx) REG32((timerx) + 0x00000058U) /*!< TIMER multi mode channel 1 capture or compare value register */ +#define TIMER_MCH2CV(timerx) REG32((timerx) + 0x0000005CU) /*!< TIMER multi mode channel 2 capture or compare value register */ +#define TIMER_MCH3CV(timerx) REG32((timerx) + 0x00000060U) /*!< TIMER multi mode channel 3 capture or compare value register */ +#define TIMER_CH0COMV_ADD(timerx) REG32((timerx) + 0x00000064U) /*!< TIMER channel 0 additional compare value register */ +#define TIMER_CH1COMV_ADD(timerx) REG32((timerx) + 0x00000068U) /*!< TIMER channel 1 additional compare value register */ +#define TIMER_CH2COMV_ADD(timerx) REG32((timerx) + 0x0000006CU) /*!< TIMER channel 2 additional compare value register */ +#define TIMER_CH3COMV_ADD(timerx) REG32((timerx) + 0x00000070U) /*!< TIMER channel 3 additional compare value register */ +#define TIMER_CTL2(timerx) REG32((timerx) + 0x00000074U) /*!< TIMER control register 2 */ +#define TIMER_BRKCFG(timerx) REG32((timerx) + 0x00000078U) /*!< TIMER break configuration register */ +#define TIMER_FCCHP0(timerx) REG32((timerx) + 0x0000007CU) /*!< TIMER free complementary channel protection register 0 */ +#define TIMER_FCCHP1(timerx) REG32((timerx) + 0x00000080U) /*!< TIMER free complementary channel protection register 1 */ +#define TIMER_FCCHP2(timerx) REG32((timerx) + 0x00000084U) /*!< TIMER free complementary channel protection register 2 */ +#define TIMER_FCCHP3(timerx) REG32((timerx) + 0x00000088U) /*!< TIMER free complementary channel protection register 3 */ +#define TIMER_DMACFG(timerx) REG32((timerx) + 0x000000E0U) /*!< TIMER DMA configuration register */ +#define TIMER_DMATB(timerx) REG32((timerx) + 0x000000E4U) /*!< TIMER DMA transfer buffer register */ +#define TIMER_CFG(timerx) REG32((timerx) + 0x000000FCU) /*!< TIMER configuration register */ + +/* bits definitions */ +/* TIMER_CTL0 */ +#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ +#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ +#define TIMER_CTL0_UPS BIT(2) /*!< update source */ +#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ +#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ +#define TIMER_CTL0_CAM BITS(5,6) /*!< counter aligned mode selection */ +#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ +#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ + +/* TIMER_CTL1 */ +#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ +#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ +#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ +#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ +#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ +#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ +#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ +#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ +#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ +#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ +#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ +#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ +#define TIMER_CTL1_ISO3N BIT(15) /*!< idle state of channel 3 complementary output */ + +/* TIMER_SMCFG */ +#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ +#define TIMER_SMCFG_TRGS (BITS(4,6)| BIT(31)) /*!< trigger selection */ +#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ +#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ +#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ +#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ +#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ +#define TIMER_SMCFG_TRGS_BIT3 BIT(31) /*!< Trigger selection bit 3 */ + +/* TIMER_DMAINTEN */ +#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ +#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture or compare interrupt enable */ +#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture or compare interrupt enable */ +#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture or compare interrupt enable */ +#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture or compare interrupt enable */ +#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ +#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ +#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ +#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ +#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture or compare DMA request enable */ +#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture or compare DMA request enable */ +#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture or compare DMA request enable */ +#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture or compare DMA request enable */ +#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ +#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ +#define TIMER_DMAINTEN_MCH0IE BIT(20) /*!< multi mode channel 0 capture or compare interrupt enable */ +#define TIMER_DMAINTEN_MCH1IE BIT(21) /*!< multi mode channel 1 capture or compare interrupt enable */ +#define TIMER_DMAINTEN_MCH2IE BIT(22) /*!< multi mode channel 2 capture or compare interrupt enable */ +#define TIMER_DMAINTEN_MCH3IE BIT(23) /*!< multi mode channel 3 capture or compare interrupt enable */ +#define TIMER_DMAINTEN_MCH0DEN BIT(24) /*!< multi mode channel 0 capture or compare DMA request enable */ +#define TIMER_DMAINTEN_MCH1DEN BIT(25) /*!< multi mode channel 1 capture or compare DMA request enable */ +#define TIMER_DMAINTEN_MCH2DEN BIT(26) /*!< multi mode channel 2 capture or compare DMA request enable */ +#define TIMER_DMAINTEN_MCH3DEN BIT(27) /*!< multi mode channel 3 capture or compare DMA request enable */ +#define TIMER_DMAINTEN_CH0COMADDIE BIT(28) /*!< channel 0 additional compare interrupt enable */ +#define TIMER_DMAINTEN_CH1COMADDIE BIT(29) /*!< channel 1 additional compare interrupt enable */ +#define TIMER_DMAINTEN_CH2COMADDIE BIT(30) /*!< channel 2 additional compare interrupt enable */ +#define TIMER_DMAINTEN_CH3COMADDIE BIT(31) /*!< channel 3 additional compare interrupt enable */ + +/* TIMER_INTF */ +#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ +#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture or compare interrupt flag */ +#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture or compare interrupt flag */ +#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture or compare interrupt flag */ +#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture or compare interrupt flag */ +#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ +#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ +#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ +#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 over capture flag */ +#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 over capture flag */ +#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 over capture flag */ +#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 over capture flag */ +#define TIMER_INTF_MCH0IF BIT(20) /*!< multi mode channel 0 capture or compare interrupt flag */ +#define TIMER_INTF_MCH1IF BIT(21) /*!< multi mode channel 1 capture or compare interrupt flag */ +#define TIMER_INTF_MCH2IF BIT(22) /*!< multi mode channel 2 capture or compare interrupt flag */ +#define TIMER_INTF_MCH3IF BIT(23) /*!< multi mode channel 3 capture or compare interrupt flag */ +#define TIMER_INTF_MCH0OF BIT(24) /*!< multi mode channel 0 over capture flag */ +#define TIMER_INTF_MCH1OF BIT(25) /*!< multi mode channel 1 over capture flag */ +#define TIMER_INTF_MCH2OF BIT(26) /*!< multi mode channel 2 over capture flag */ +#define TIMER_INTF_MCH3OF BIT(27) /*!< multi mode channel 3 over capture flag */ +#define TIMER_INTF_CH0COMADDIF BIT(28) /*!< channel 0 additional compare interrupt flag */ +#define TIMER_INTF_CH1COMADDIF BIT(29) /*!< channel 1 additional compare interrupt flag */ +#define TIMER_INTF_CH2COMADDIF BIT(30) /*!< channel 2 additional compare interrupt flag */ +#define TIMER_INTF_CH3COMADDIF BIT(31) /*!< channel 3 additional compare interrupt flag */ + +/* TIMER_SWEVG */ +#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ +#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ +#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ +#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ +#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ +#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ +#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ +#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ +#define TIMER_SWEVG_MCH0G BIT(20) /*!< multi mode channel 0 capture or compare event generation */ +#define TIMER_SWEVG_MCH1G BIT(21) /*!< multi mode channel 1 capture or compare event generation */ +#define TIMER_SWEVG_MCH2G BIT(22) /*!< multi mode channel 2 capture or compare event generation */ +#define TIMER_SWEVG_MCH3G BIT(23) /*!< multi mode channel 3 capture or compare event generation */ +#define TIMER_SWEVG_CH0COMADDG BIT(28) /*!< channel 0 additional compare event generation */ +#define TIMER_SWEVG_CH1COMADDG BIT(29) /*!< channel 1 additional compare event generation */ +#define TIMER_SWEVG_CH2COMADDG BIT(30) /*!< channel 2 additional compare event generation */ +#define TIMER_SWEVG_CH3COMADDG BIT(31) /*!< channel 3 additional compare event generation */ + +/* TIMER_CHCTL0 */ +/* output compare mode */ +#define TIMER_CHCTL0_CH0MS (TIMER_CHCTL0_CH0MS_BIT2 | BITS(0,1)) /*!< channel 0 mode selection */ +#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ +#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */ +#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ +#define TIMER_CHCTL0_CH1MS (TIMER_CHCTL0_CH1MS_BIT2 | BITS(8,9)) /*!< channel 1 mode selection */ +#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ +#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */ +#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ +#define TIMER_CHCTL0_CH0COMADDSEN BIT(28) /*!< channel 0 additional compare output shadow enable */ +#define TIMER_CHCTL0_CH1COMADDSEN BIT(29) /*!< channel 1 additional compare output shadow enable */ +#define TIMER_CHCTL0_CH0MS_BIT2 BIT(30) /*!< channel 0 I/O mode selection */ +#define TIMER_CHCTL0_CH1MS_BIT2 BIT(31) /*!< channel 1 I/O mode selection */ +/* input capture mode */ +#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ +#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ +#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ +#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ + +/* TIMER_CHCTL1 */ +/* output compare mode */ +#define TIMER_CHCTL1_CH2MS (TIMER_CHCTL1_CH2MS_BIT2 | BITS(0,1)) /*!< channel 2 mode selection */ +#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ +#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */ +#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ +#define TIMER_CHCTL1_CH3MS (TIMER_CHCTL1_CH3MS_BIT2 | BITS(8,9)) /*!< channel 3 mode selection */ +#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ +#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */ +#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ +#define TIMER_CHCTL1_CH2COMADDSEN BIT(28) /*!< channel 2 additional compare output shadow enable */ +#define TIMER_CHCTL1_CH3COMADDSEN BIT(29) /*!< channel 3 additional compare output shadow enable */ +#define TIMER_CHCTL1_CH2MS_BIT2 BIT(30) /*!< channel 2 I/O mode selection */ +#define TIMER_CHCTL1_CH3MS_BIT2 BIT(31) /*!< channel 3 I/O mode selection */ +/* input capture mode */ +#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ +#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ +#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ +#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ + +/* TIMER_CHCTL2 */ +#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture or compare function enable */ +#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture or compare function polarity */ +#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ +#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ +#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture or compare function enable */ +#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture or compare function polarity */ +#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ +#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ +#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture or compare function enable */ +#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture or compare function polarity */ +#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ +#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ +#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture or compare function enable */ +#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture or compare function polarity */ +#define TIMER_CHCTL2_CH3NEN BIT(14) /*!< channel 3 complementary output enable */ +#define TIMER_CHCTL2_CH3NP BIT(15) /*!< channel 3 complementary output polarity */ + +#define TIMER_CHCTL2_MCH0EN BIT(2) /*!< multi mode channel 0 capture or compare function enable */ +#define TIMER_CHCTL2_MCH0P BIT(3) /*!< multi mode channel 0 complementary output polarity */ +#define TIMER_CHCTL2_MCH1EN BIT(6) /*!< multi mode channel 1 capture or compare function enable */ +#define TIMER_CHCTL2_MCH1P BIT(7) /*!< multi mode channel 1 complementary output polarity */ +#define TIMER_CHCTL2_MCH2EN BIT(10) /*!< multi mode channel 2 capture or compare function enable */ +#define TIMER_CHCTL2_MCH2P BIT(11) /*!< multi mode channel 2 complementary output polarity */ +#define TIMER_CHCTL2_MCH3EN BIT(14) /*!< multi mode channel 3 capture or compare function enable */ +#define TIMER_CHCTL2_MCH3P BIT(15) /*!< multi mode channel 3 complementary output polarity */ + +/* TIMER_CNT */ +#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ + +/* TIMER_PSC */ +#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ + +/* TIMER_CAR */ +#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ + +/* TIMER_CREP */ +#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ + +/* TIMER_CH0CV */ +#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture or compare value of channel 0 */ + +/* TIMER_CH1CV */ +#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture or compare value of channel 1 */ + +/* TIMER_CH2CV */ +#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture or compare value of channel 2 */ + +/* TIMER_CH3CV */ +#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture or compare value of channel 3 */ + +/* TIMER_CCHP */ +#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ +#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ +#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ +#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ +#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ +#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ +#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ +#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ + +/* TIMER_MCHCTL0 */ +/* output compare mode */ +#define TIMER_MCHCTL0_MCH0MS (BITS(0,1) | BIT(30)) /*!< multi mode channel 0 I/O mode selection */ +#define TIMER_MCHCTL0_MCH0COMSEN BIT(3) /*!< multi mode channel 0 output compare shadow enable */ +#define TIMER_MCHCTL0_MCH0COMCTL BITS(4,6) /*!< multi mode channel 0 compare output control */ +#define TIMER_MCHCTL0_MCH0COMCEN BIT(7) /*!< multi mode channel 0 output compare clear enable */ +#define TIMER_MCHCTL0_MCH1MS (BITS(8,9) | BIT(31)) /*!< multi mode channel 1 I/O mode selection */ +#define TIMER_MCHCTL0_MCH1COMSEN BIT(11) /*!< multi mode channel 1 output compare shadow enable */ +#define TIMER_MCHCTL0_MCH1COMCTL BITS(12,14) /*!< multi mode channel 1 compare output control */ +#define TIMER_MCHCTL0_MCH1COMCEN BIT(15) /*!< multi mode channel 1 output compare clear enable */ +/* input capture mode */ +#define TIMER_MCHCTL0_MCH0CAPPSC BITS(2,3) /*!< multi mode channel 0 input capture prescaler */ +#define TIMER_MCHCTL0_MCH0CAPFLT BITS(4,7) /*!< multi mode channel 0 input capture filter control */ +#define TIMER_MCHCTL0_MCH1CAPPSC BITS(10,11) /*!< multi mode channel 1 input capture prescaler */ +#define TIMER_MCHCTL0_MCH1CAPFLT BITS(12,15) /*!< multi mode channel 1 input capture filter control */ + +/* TIMER_MCHCTL1 */ +/* output compare mode */ +#define TIMER_MCHCTL1_MCH2MS (BITS(0,1) | BIT(30)) /*!< multi mode channel 2 I/O mode selection */ +#define TIMER_MCHCTL1_MCH2COMSEN BIT(3) /*!< multi mode channel 2 output compare shadow enable */ +#define TIMER_MCHCTL1_MCH2COMCTL BITS(4,6) /*!< multi mode channel 2 compare output control */ +#define TIMER_MCHCTL1_MCH2COMCEN BIT(7) /*!< multi mode channel 2 output compare clear enable */ +#define TIMER_MCHCTL1_MCH3MS (BITS(8,9) | BIT(31)) /*!< multi mode channel 3 I/O mode selection */ +#define TIMER_MCHCTL1_MCH3COMSEN BIT(11) /*!< multi mode channel 3 output compare shadow enable */ +#define TIMER_MCHCTL1_MCH3COMCTL BITS(12,14) /*!< multi mode channel 3 compare output control */ +#define TIMER_MCHCTL1_MCH3COMCEN BIT(15) /*!< multi mode channel 3 output compare clear enable */ +/* input capture mode */ +#define TIMER_MCHCTL1_MCH2CAPPSC BITS(2,3) /*!< multi mode channel 2 input capture prescaler */ +#define TIMER_MCHCTL1_MCH2CAPFLT BITS(4,7) /*!< multi mode channel 2 input capture filter control */ +#define TIMER_MCHCTL1_MCH3CAPPSC BITS(10,11) /*!< multi mode channel 3 input capture prescaler */ +#define TIMER_MCHCTL1_MCH3CAPFLT BITS(12,15) /*!< multi mode channel 3 input capture filter control */ + +/* TIMER_MCHCTL2 */ +#define TIMER_MCHCTL2_MCH0FP BITS(0,1) /*!< multi mode channel 0 capture or compare function polarity */ +#define TIMER_MCHCTL2_MCH1FP BITS(2,3) /*!< multi mode channel 1 capture or compare function polarity */ +#define TIMER_MCHCTL2_MCH2FP BITS(4,5) /*!< multi mode channel 2 capture or compare function polarity */ +#define TIMER_MCHCTL2_MCH3FP BITS(6,7) /*!< multi mode channel 3 capture or compare function polarity */ + +/* TIMER_IRMP */ +#define TIMER1_IRMP_CI0_RMP BITS(0,1) /*!< TIMER1 channel 0 input remap */ + +/* TIMER_MCH0CV */ +#define TIMER_MCH0CV_MCH0VAL BITS(0,15) /*!< 16 bit capture or compare value of multi mode channel 0 */ + +/* TIMER_MCH1CV */ +#define TIMER_MCH1CV_MCH1VAL BITS(0,15) /*!< 16 bit capture or compare value of multi mode channel 1 */ + +/* TIMER_MCH2CV */ +#define TIMER_MCH2CV_MCH2VAL BITS(0,15) /*!< 16 bit capture or compare value of multi mode channel 2 */ + +/* TIMER_MCH3CV */ +#define TIMER_MCH3CV_MCH3VAL BITS(0,15) /*!< 16 bit capture or compare value of multi mode channel 3 */ + +/* TIMER_CH0COMV_ADD */ +#define TIMER_CH0COMV_ADD_CH0COMVAL BITS(0,15) /*!< additional compare value of channel 0 */ + +/* TIMER_CH1COMV_ADD */ +#define TIMER_CH1COMV_ADD_CH0COMVAL BITS(0,15) /*!< additional compare value of channel 1 */ + +/* TIMER_CH2COMV_ADD */ +#define TIMER_CH2COMV_ADD_CH0COMVAL BITS(0,15) /*!< additional compare value of channel 2 */ + +/* TIMER_CH3COMV_ADD */ +#define TIMER_CH3COMV_ADD_CH0COMVAL BITS(0,15) /*!< additional compare value of channel 3 */ + +/* TIMER_CTL2 */ +#define TIMER_CTL2_DTIENCH0 BIT(0) /*!< dead time inserted enable for channel 0 and channel 0N */ +#define TIMER_CTL2_DTIENCH1 BIT(1) /*!< dead time inserted enable for channel 1 and channel 1N */ +#define TIMER_CTL2_DTIENCH2 BIT(2) /*!< dead time inserted enable for channel 2 and channel 2N */ +#define TIMER_CTL2_DTIENCH3 BIT(3) /*!< dead time inserted enable for channel 3 and channel 3N */ +#define TIMER_CTL2_BRKENCH0 BIT(4) /*!< break control enable for channel 0 and multi mode channel 0 */ +#define TIMER_CTL2_BRKENCH1 BIT(5) /*!< break control enable for channel 1 and multi mode channel 1 */ +#define TIMER_CTL2_BRKENCH2 BIT(6) /*!< break control enable for channel 2 and multi mode channel 2 */ +#define TIMER_CTL2_BRKENCH3 BIT(7) /*!< break control enable for channel 3 and multi mode channel 3 */ +#define TIMER_CTL2_CH0OMPSEL BITS(8,9) /*!< channel 0 output march pulse select */ +#define TIMER_CTL2_CH1OMPSEL BITS(10,11) /*!< channel 1 output march pulse select */ +#define TIMER_CTL2_CH2OMPSEL BITS(12,13) /*!< channel 2 output march pulse select */ +#define TIMER_CTL2_CH3OMPSEL BITS(14,15) /*!< channel 3 output march pulse select */ +#define TIMER_CTL2_MCH0MSEL BITS(20,21) /*!< multi mode channel 0 mode select */ +#define TIMER_CTL2_MCH1MSEL BITS(22,23) /*!< multi mode channel 1 mode select */ +#define TIMER_CTL2_MCH2MSEL BITS(24,25) /*!< multi mode channel 2 mode select */ +#define TIMER_CTL2_MCH3MSEL BITS(26,27) /*!< multi mode channel 3 mode select */ +#define TIMER_CTL2_CH0CPWMEN BIT(28) /*!< channel 0 composite PWM mode enable */ +#define TIMER_CTL2_CH1CPWMEN BIT(29) /*!< channel 1 composite PWM mode enable */ +#define TIMER_CTL2_CH2CPWMEN BIT(30) /*!< channel 2 composite PWM mode enable */ +#define TIMER_CTL2_CH3CPWMEN BIT(31) /*!< channel 3 composite PWM mode enable */ + +/* TIMER_BRKCFG */ +#define TIMER_BRKCFG_BRK0F BITS(0,3) /*!< BRKIN0 input signal filter */ +#define TIMER_BRKCFG_BRK1F BITS(4,7) /*!< BRKIN1 input signal filter */ +#define TIMER_BRKCFG_BRK2F BITS(8,11) /*!< BRKIN2 input signal filter */ +#define TIMER_BRKCFG_BRK3F BITS(12,15) /*!< BRKIN3 input signal filter */ +#define TIMER_BRKCFG_BRK0EN BIT(24) /*!< BRKIN0 input signal enable */ +#define TIMER_BRKCFG_BRK0P BIT(25) /*!< BRKIN0 input signal polarity */ +#define TIMER_BRKCFG_BRK1EN BIT(26) /*!< BRKIN1 input signal enable */ +#define TIMER_BRKCFG_BRK1P BIT(27) /*!< BRKIN1 input signal polarity */ +#define TIMER_BRKCFG_BRK2EN BIT(28) /*!< BRKIN2 input signal enable */ +#define TIMER_BRKCFG_BRK2P BIT(29) /*!< BRKIN2 input signal polarity */ +#define TIMER_BRKCFG_BRK3EN BIT(30) /*!< BRKIN3 input signal enable */ +#define TIMER_BRKCFG_BRK3P BIT(31) /*!< BRKIN3 input signal polarity */ + +/* TIMER_FCCHP0 */ +#define TIMER_FCCHP0_DTCFG BITS(0,7) /*!< dead time configure */ +#define TIMER_FCCHP0_IOS BIT(10) /*!< idle mode off-state configure */ +#define TIMER_FCCHP0_ROS BIT(11) /*!< run mode off-state configure */ +#define TIMER_FCCHP0_FCCHP0EN BIT(31) /*!< free complementary channel protection register 0 enable */ + +/* TIMER_FCCHP1 */ +#define TIMER_FCCHP1_DTCFG BITS(0,7) /*!< dead time configure */ +#define TIMER_FCCHP1_IOS BIT(10) /*!< idle mode off-state configure */ +#define TIMER_FCCHP1_ROS BIT(11) /*!< run mode off-state configure */ +#define TIMER_FCCHP1_FCCHP1EN BIT(31) /*!< free complementary channel protection register 1 enable */ + +/* TIMER_FCCHP2 */ +#define TIMER_FCCHP2_DTCFG BITS(0,7) /*!< dead time configure */ +#define TIMER_FCCHP2_IOS BIT(10) /*!< idle mode off-state configure */ +#define TIMER_FCCHP2_ROS BIT(11) /*!< run mode off-state configure */ +#define TIMER_FCCHP2_FCCHP2EN BIT(31) /*!< free complementary channel protection register 2 enable */ + +/* TIMER_FCCHP3 */ +#define TIMER_FCCHP3_DTCFG BITS(0,7) /*!< dead time configure */ +#define TIMER_FCCHP3_IOS BIT(10) /*!< idle mode off-state configure */ +#define TIMER_FCCHP3_ROS BIT(11) /*!< run mode off-state configure */ +#define TIMER_FCCHP3_FCCHP3EN BIT(31) /*!< free complementary channel protection register 3 enable */ + +/* TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA BITS(0,5) /*!< DMA transfer access start address */ +#define TIMER_DMACFG_DMATC BITS(8,13) /*!< DMA transfer count */ + +/* TIMER_DMATB */ +#define TIMER_DMATB_DMATB BITS(0,31) /*!< DMA transfer buffer address */ + +/* TIMER_CFG */ +#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ +#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ + +/* constants definitions */ +/* TIMER init parameter struct definitions */ +typedef struct { + uint16_t prescaler; /*!< prescaler value */ + uint16_t alignedmode; /*!< aligned mode */ + uint16_t counterdirection; /*!< counter direction */ + uint32_t period; /*!< period value */ + uint16_t clockdivision; /*!< clock division value */ + uint8_t repetitioncounter; /*!< the counter repetition value */ +} timer_parameter_struct; + +/* break parameter struct definitions */ +typedef struct { + uint16_t runoffstate; /*!< run mode off-state */ + uint16_t ideloffstate; /*!< idle mode off-state */ + uint16_t deadtime; /*!< dead time */ + uint16_t breakpolarity; /*!< break polarity */ + uint16_t outputautostate; /*!< output automatic enable */ + uint16_t protectmode; /*!< complementary register protect control */ + uint16_t breakstate; /*!< break enable */ +} timer_break_parameter_struct; + +/* channel output parameter struct definitions */ +typedef struct { + uint16_t outputstate; /*!< channel output state */ + uint16_t outputnstate; /*!< channel complementary output state */ + uint16_t ocpolarity; /*!< channel output polarity */ + uint16_t ocnpolarity; /*!< channel complementary output polarity */ + uint16_t ocidlestate; /*!< idle state of channel output */ + uint16_t ocnidlestate; /*!< idle state of channel complementary output */ +} timer_oc_parameter_struct; + +/* multi mode channel output parameter struct definitions */ +typedef struct { + uint16_t outputmode; /*!< multi mode channel output mode selection */ + uint16_t outputstate; /*!< multi mode channel output state */ + uint16_t ocpolarity; /*!< multi mode channel output polarity */ +} timer_omc_parameter_struct; + +/* channel input parameter struct definitions */ +typedef struct { + uint16_t icpolarity; /*!< channel input polarity */ + uint16_t icselection; /*!< channel input mode selection */ + uint16_t icprescaler; /*!< channel input capture prescaler */ + uint16_t icfilter; /*!< channel input capture filter control */ +} timer_ic_parameter_struct; + +/* break external input parameter struct definitions */ +typedef struct { + uint32_t filter; /*!< break external input filter */ + uint32_t enable; /*!< break external input enable */ + uint32_t polarity; /*!< break external input polarity */ +} timer_break_ext_input_struct; + +/* channel free complementary parameter struct definitions */ +typedef struct { + uint32_t freecomstate; /*!< free complementary channel protection enable */ + uint32_t runoffstate; /*!< run mode off-state */ + uint32_t ideloffstate; /*!< idle mode off-state */ + uint32_t deadtime; /*!< dead time */ +} timer_free_complementary_parameter_struct; + +/* TIMER interrupt enable or disable */ +#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ +#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 capture or compare interrupt */ +#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 capture or compare interrupt */ +#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 capture or compare interrupt */ +#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 capture or compare interrupt */ +#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ +#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ +#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ +#define TIMER_INT_MCH0 TIMER_DMAINTEN_MCH0IE /*!< multi mode channel 0 capture or compare interrupt */ +#define TIMER_INT_MCH1 TIMER_DMAINTEN_MCH1IE /*!< multi mode channel 1 capture or compare interrupt */ +#define TIMER_INT_MCH2 TIMER_DMAINTEN_MCH2IE /*!< multi mode channel 2 capture or compare interrupt */ +#define TIMER_INT_MCH3 TIMER_DMAINTEN_MCH3IE /*!< multi mode channel 3 capture or compare interrupt */ +#define TIMER_INT_CH0COMADD TIMER_DMAINTEN_CH0COMADDIE /*!< channel 0 additional compare interrupt */ +#define TIMER_INT_CH1COMADD TIMER_DMAINTEN_CH1COMADDIE /*!< channel 1 additional compare interrupt */ +#define TIMER_INT_CH2COMADD TIMER_DMAINTEN_CH2COMADDIE /*!< channel 2 additional compare interrupt */ +#define TIMER_INT_CH3COMADD TIMER_DMAINTEN_CH3COMADDIE /*!< channel 3 additional compare interrupt */ + +/* TIMER interrupt flag */ +#define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt flag */ +#define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt flag */ +#define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt flag */ +#define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt flag */ +#define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt flag */ +#define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ +#define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt flag */ +#define TIMER_INT_FLAG_BRK TIMER_INT_BRK /*!< break interrupt flag */ +#define TIMER_INT_FLAG_MCH0 TIMER_INT_MCH0 /*!< multi mode channel 0 capture or compare interrupt flag */ +#define TIMER_INT_FLAG_MCH1 TIMER_INT_MCH1 /*!< multi mode channel 1 capture or compare interrupt flag */ +#define TIMER_INT_FLAG_MCH2 TIMER_INT_MCH2 /*!< multi mode channel 2 capture or compare interrupt flag */ +#define TIMER_INT_FLAG_MCH3 TIMER_INT_MCH3 /*!< multi mode channel 3 capture or compare interrupt flag */ +#define TIMER_INT_FLAG_CH0COMADD TIMER_INT_CH0COMADD /*!< channel 0 additional compare interrupt flag */ +#define TIMER_INT_FLAG_CH1COMADD TIMER_INT_CH1COMADD /*!< channel 1 additional compare interrupt flag */ +#define TIMER_INT_FLAG_CH2COMADD TIMER_INT_CH2COMADD /*!< channel 2 additional compare interrupt flag */ +#define TIMER_INT_FLAG_CH3COMADD TIMER_INT_CH3COMADD /*!< channel 3 additional compare interrupt flag */ + +/* TIMER flag */ +#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ +#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 capture or compare flag */ +#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 capture or compare flag */ +#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 capture or compare flag */ +#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 capture or compare flag */ +#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ +#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ +#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ +#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ +#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ +#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ +#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ +#define TIMER_FLAG_MCH0 TIMER_INTF_MCH0IF /*!< multi mode channel 0 capture or compare flag */ +#define TIMER_FLAG_MCH1 TIMER_INTF_MCH1IF /*!< multi mode channel 1 capture or compare flag */ +#define TIMER_FLAG_MCH2 TIMER_INTF_MCH2IF /*!< multi mode channel 2 capture or compare flag */ +#define TIMER_FLAG_MCH3 TIMER_INTF_MCH3IF /*!< multi mode channel 3 capture or compare flag */ +#define TIMER_FLAG_MCH0O TIMER_INTF_MCH0OF /*!< multi mode channel 0 overcapture flag */ +#define TIMER_FLAG_MCH1O TIMER_INTF_MCH1OF /*!< multi mode channel 1 overcapture flag */ +#define TIMER_FLAG_MCH2O TIMER_INTF_MCH2OF /*!< multi mode channel 2 overcapture flag */ +#define TIMER_FLAG_MCH3O TIMER_INTF_MCH3OF /*!< multi mode channel 3 overcapture flag */ +#define TIMER_FLAG_CH0COMADD TIMER_INTF_CH0COMADDIF /*!< channel 0 additional compare interrupt flag */ +#define TIMER_FLAG_CH1COMADD TIMER_INTF_CH1COMADDIF /*!< channel 1 additional compare interrupt flag */ +#define TIMER_FLAG_CH2COMADD TIMER_INTF_CH2COMADDIF /*!< channel 2 additional compare interrupt flag */ +#define TIMER_FLAG_CH3COMADD TIMER_INTF_CH3COMADDIF /*!< channel 3 additional compare interrupt flag */ + +/* TIMER DMA source */ +#define TIMER_DMA_UPD TIMER_DMAINTEN_UPDEN /*!< update DMA request */ +#define TIMER_DMA_CH0D TIMER_DMAINTEN_CH0DEN /*!< channel 0 capture or compare DMA request */ +#define TIMER_DMA_CH1D TIMER_DMAINTEN_CH1DEN /*!< channel 1 capture or compare DMA request */ +#define TIMER_DMA_CH2D TIMER_DMAINTEN_CH2DEN /*!< channel 2 capture or compare DMA request */ +#define TIMER_DMA_CH3D TIMER_DMAINTEN_CH3DEN /*!< channel 3 capture or compare DMA request */ +#define TIMER_DMA_CMTD TIMER_DMAINTEN_CMTDEN /*!< commutation DMA request */ +#define TIMER_DMA_TRGD TIMER_DMAINTEN_TRGDEN /*!< trigger DMA request */ +#define TIMER_DMA_MCH0D TIMER_DMAINTEN_MCH0DEN /*!< multi mode channel 0 capture or compare DMA request */ +#define TIMER_DMA_MCH1D TIMER_DMAINTEN_MCH1DEN /*!< multi mode channel 1 capture or compare DMA request */ +#define TIMER_DMA_MCH2D TIMER_DMAINTEN_MCH2DEN /*!< multi mode channel 2 capture or compare DMA request */ +#define TIMER_DMA_MCH3D TIMER_DMAINTEN_MCH3DEN /*!< multi mode channel 3 capture or compare DMA request */ + +/* channel DMA request source selection */ +#define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel n is sent when update event occurs */ +#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ + +/* DMA access base address */ +#define DMACFG_DMATA(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) +#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ +#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ +#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ +#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ +#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ +#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ +#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ +#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ +#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ +#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ +#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ +#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ +#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ +#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ +#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ +#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ +#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ +#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ +#define TIMER_DMACFG_DMATA_MCHCTL0 DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_MCHCTL0 */ +#define TIMER_DMACFG_DMATA_MCHCTL1 DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_MCHCTL1 */ +#define TIMER_DMACFG_DMATA_MCHCTL2 DMACFG_DMATA(20) /*!< DMA transfer address is TIMER_MCHCTL2 */ +#define TIMER_DMACFG_DMATA_MCH0CV DMACFG_DMATA(21) /*!< DMA transfer address is TIMER_MCH0CV */ +#define TIMER_DMACFG_DMATA_MCH1CV DMACFG_DMATA(22) /*!< DMA transfer address is TIMER_MCH1CV */ +#define TIMER_DMACFG_DMATA_MCH2CV DMACFG_DMATA(23) /*!< DMA transfer address is TIMER_MCH2CV */ +#define TIMER_DMACFG_DMATA_MCH3CV DMACFG_DMATA(24) /*!< DMA transfer address is TIMER_MCH3CV */ +#define TIMER_DMACFG_DMATA_CH0COMV_ADD DMACFG_DMATA(25) /*!< DMA transfer address is TIMER_CH0COMV_ADD */ +#define TIMER_DMACFG_DMATA_CH1COMV_ADD DMACFG_DMATA(26) /*!< DMA transfer address is TIMER_CH1COMV_ADD */ +#define TIMER_DMACFG_DMATA_CH2COMV_ADD DMACFG_DMATA(27) /*!< DMA transfer address is TIMER_CH2COMV_ADD */ +#define TIMER_DMACFG_DMATA_CH3COMV_ADD DMACFG_DMATA(28) /*!< DMA transfer address is TIMER_CH3COMV_ADD */ +#define TIMER_DMACFG_DMATA_CTL2 DMACFG_DMATA(29) /*!< DMA transfer address is TIMER_CTL2 */ +#define TIMER_DMACFG_DMATA_BRKCFG DMACFG_DMATA(30) /*!< DMA transfer address is TIMER_BRKCFG */ +#define TIMER_DMACFG_DMATA_FCCHP0 DMACFG_DMATA(31) /*!< DMA transfer address is TIMER_FCCHP0 */ +#define TIMER_DMACFG_DMATA_FCCHP1 DMACFG_DMATA(32) /*!< DMA transfer address is TIMER_FCCHP1 */ +#define TIMER_DMACFG_DMATA_FCCHP2 DMACFG_DMATA(33) /*!< DMA transfer address is TIMER_FCCHP2 */ +#define TIMER_DMACFG_DMATA_FCCHP3 DMACFG_DMATA(34) /*!< DMA transfer address is TIMER_FCCHP3 */ + +/* DMA access burst length */ +#define DMACFG_DMATC(regval) (BITS(8,13) & ((uint32_t)(regval) << 8U)) +#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ +#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ +#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ +#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ +#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ +#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ +#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ +#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ +#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ +#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ +#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ +#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ +#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ +#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ +#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ +#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ +#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ +#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ +#define TIMER_DMACFG_DMATC_19TRANSFER DMACFG_DMATC(18) /*!< DMA transfer 19 times */ +#define TIMER_DMACFG_DMATC_20TRANSFER DMACFG_DMATC(19) /*!< DMA transfer 20 times */ +#define TIMER_DMACFG_DMATC_21TRANSFER DMACFG_DMATC(20) /*!< DMA transfer 21 times */ +#define TIMER_DMACFG_DMATC_22TRANSFER DMACFG_DMATC(21) /*!< DMA transfer 22 times */ +#define TIMER_DMACFG_DMATC_23TRANSFER DMACFG_DMATC(22) /*!< DMA transfer 23 times */ +#define TIMER_DMACFG_DMATC_24TRANSFER DMACFG_DMATC(23) /*!< DMA transfer 24 times */ +#define TIMER_DMACFG_DMATC_25TRANSFER DMACFG_DMATC(24) /*!< DMA transfer 25 times */ +#define TIMER_DMACFG_DMATC_26TRANSFER DMACFG_DMATC(25) /*!< DMA transfer 26 times */ +#define TIMER_DMACFG_DMATC_27TRANSFER DMACFG_DMATC(26) /*!< DMA transfer 27 times */ +#define TIMER_DMACFG_DMATC_28TRANSFER DMACFG_DMATC(27) /*!< DMA transfer 28 times */ +#define TIMER_DMACFG_DMATC_29TRANSFER DMACFG_DMATC(28) /*!< DMA transfer 29 times */ +#define TIMER_DMACFG_DMATC_30TRANSFER DMACFG_DMATC(29) /*!< DMA transfer 30 times */ +#define TIMER_DMACFG_DMATC_31TRANSFER DMACFG_DMATC(30) /*!< DMA transfer 31 times */ +#define TIMER_DMACFG_DMATC_32TRANSFER DMACFG_DMATC(31) /*!< DMA transfer 32 times */ +#define TIMER_DMACFG_DMATC_33TRANSFER DMACFG_DMATC(32) /*!< DMA transfer 33 times */ +#define TIMER_DMACFG_DMATC_34TRANSFER DMACFG_DMATC(33) /*!< DMA transfer 34 times */ +#define TIMER_DMACFG_DMATC_35TRANSFER DMACFG_DMATC(34) /*!< DMA transfer 35 times */ + +/* TIMER software event generation source */ +#define TIMER_EVENT_SRC_UPG TIMER_SWEVG_UPG /*!< update event generation */ +#define TIMER_EVENT_SRC_CH0G TIMER_SWEVG_CH0G /*!< channel 0 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH1G TIMER_SWEVG_CH1G /*!< channel 1 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH2G TIMER_SWEVG_CH2G /*!< channel 2 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH3G TIMER_SWEVG_CH3G /*!< channel 3 capture or compare event generation */ +#define TIMER_EVENT_SRC_CMTG TIMER_SWEVG_CMTG /*!< channel commutation event generation */ +#define TIMER_EVENT_SRC_TRGG TIMER_SWEVG_TRGG /*!< trigger event generation */ +#define TIMER_EVENT_SRC_BRKG TIMER_SWEVG_BRKG /*!< break event generation */ +#define TIMER_EVENT_SRC_MCH0G TIMER_SWEVG_MCH0G /*!< multi mode channel 0 capture or compare event generation */ +#define TIMER_EVENT_SRC_MCH1G TIMER_SWEVG_MCH1G /*!< multi mode channel 1 capture or compare event generation */ +#define TIMER_EVENT_SRC_MCH2G TIMER_SWEVG_MCH2G /*!< multi mode channel 2 capture or compare event generation */ +#define TIMER_EVENT_SRC_MCH3G TIMER_SWEVG_MCH3G /*!< multi mode channel 3 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH0COMADDG TIMER_SWEVG_CH0COMADDG /*!< channel 0 additional compare event generation */ +#define TIMER_EVENT_SRC_CH1COMADDG TIMER_SWEVG_CH1COMADDG /*!< channel 1 additional compare event generation */ +#define TIMER_EVENT_SRC_CH2COMADDG TIMER_SWEVG_CH2COMADDG /*!< channel 2 additional compare event generation */ +#define TIMER_EVENT_SRC_CH3COMADDG TIMER_SWEVG_CH3COMADDG /*!< channel 3 additional compare event generation */ + +/* center-aligned mode selection */ +#define CTL0_CAM(regval) ((uint16_t)(BITS(5,6) & ((uint32_t)(regval) << 5U))) +#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ +#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ +#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ +#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ + +/* TIMER prescaler reload mode */ +#define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */ + +/* count direction */ +#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ +#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ + +/* specify division ratio between TIMER clock and dead-time and sampling clock */ +#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8,9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1, fDTS = fTIMER_CK */ +#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2, fDTS = fTIMER_CK/2 */ +#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS = fTIMER_CK/4 */ + +/* single pulse mode */ +#define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */ + +/* update source */ +#define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ + +/* run mode off-state configure */ +#define TIMER_ROS_STATE_ENABLE ((uint32_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/MCHx) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_ROS_STATE_DISABLE ((uint32_t)0x00000000U) /*!< when POEN bit is set, the channel output signals(CHx_O/MCHx) are disabled */ + +/* idle mode off-state configure */ +#define TIMER_IOS_STATE_ENABLE ((uint32_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, the channel output signals(CHx_O/MCHx) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_IOS_STATE_DISABLE ((uint32_t)0x00000000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/MCHx) are disabled */ + +/* break input polarity */ +#define TIMER_BREAK_POLARITY_LOW ((uint32_t)0x00000000U) /*!< break input polarity is low */ +#define TIMER_BREAK_POLARITY_HIGH ((uint32_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ + +/* output automatic enable */ +#define TIMER_OUTAUTO_ENABLE ((uint32_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ +#define TIMER_OUTAUTO_DISABLE ((uint32_t)0x00000000U) /*!< output automatic disable */ + +/* complementary register protect control */ +#define CCHP_PROT(regval) ((uint16_t)(BITS(8,9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ +#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ +#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ +#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ + +/* break input enable */ +#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ +#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ + +/* free complementary channel protection configure */ +#define TIMER_FCCHP_STATE_ENABLE ((uint32_t)TIMER_FCCHP0_FCCHP0EN) /*!< free complementary channel protection enable */ +#define TIMER_FCCHP_STATE_DISABLE ((uint32_t)0x00000000U) /*!< free complementary channel protection disable */ + +/* TIMER external break input source */ +#define TIMER_BREAKINPUT_BRK0 ((uint16_t)0x0000U) /*!< TIMER break external input 0 */ +#define TIMER_BREAKINPUT_BRK1 ((uint16_t)0x0001U) /*!< TIMER break external input 1 */ +#define TIMER_BREAKINPUT_BRK2 ((uint16_t)0x0002U) /*!< TIMER break external input 2 */ +#define TIMER_BREAKINPUT_BRK3 ((uint16_t)0x0003U) /*!< TIMER break external input 3 */ + +/* TIMER Break external input polarity*/ +#define TIMER_BRKIN_POLARITY_LOW ((uint16_t)0x0000U) /*!< TIMER break external input polarity is active low */ +#define TIMER_BRKIN_POLARITY_HIGH ((uint16_t)0x0001U) /*!< TIMER break external input polarity is active high */ + +/* TIMER channel n(n=0,1,2,3) */ +#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0 */ +#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1 */ +#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2 */ +#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3 */ +#define TIMER_CH_0N ((uint16_t)0x0010U) /*!< TIMER complementary output channel 0 */ +#define TIMER_CH_1N ((uint16_t)0x0011U) /*!< TIMER complementary output channel 1 */ +#define TIMER_CH_2N ((uint16_t)0x0012U) /*!< TIMER complementary output channel 2 */ +#define TIMER_CH_3N ((uint16_t)0x0013U) /*!< TIMER complementary output channel 3 */ +#define TIMER_MCH_0 ((uint16_t)0x0010U) /*!< TIMER multi mode channel 0 */ +#define TIMER_MCH_1 ((uint16_t)0x0011U) /*!< TIMER multi mode channel 1 */ +#define TIMER_MCH_2 ((uint16_t)0x0012U) /*!< TIMER multi mode channel 2 */ +#define TIMER_MCH_3 ((uint16_t)0x0013U) /*!< TIMER multi mode channel 3 */ + +/* channel enable state */ +#define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */ +#define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */ + +/* channel complementary output enable state */ +#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ +#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ + +/* multi mode channel enable state */ +#define TIMER_MCCX_ENABLE ((uint16_t)0x0004U) /*!< multi mode channel enable */ +#define TIMER_MCCX_DISABLE ((uint16_t)0x0000U) /*!< multi mode channel disable */ + +/* channel output polarity */ +#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ +#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ + +/* channel complementary output polarity */ +#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ +#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ + +/* multi mode channel output polarity */ +#define TIMER_OMC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< multi mode channel output polarity is high */ +#define TIMER_OMC_POLARITY_LOW ((uint16_t)0x0001U) /*!< multi mode channel output polarity is low */ + +/* idle state of channel output */ +#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100U) /*!< idle state of channel output is high */ +#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel output is low */ + +/* idle state of channel complementary output */ +#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ +#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ + +/* idle state of multi mode channel output */ +#define TIMER_OMC_IDLE_STATE_HIGH ((uint16_t)0x0100U) /*!< idle state of multi mode channel output is high */ +#define TIMER_OMC_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of multi mode channel output is low */ + +/* channel output compare mode */ +#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ +#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ +#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ +#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ +#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ +#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ +#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM mode 0 */ +#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM mode 1 */ + +/* channel output compare shadow enable */ +#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output compare shadow enable */ +#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output compare shadow disable */ + +/* channel output compare clear enable */ +#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ +#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ + +/* channel control shadow register update control */ +#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers update by when CMTG bit is set */ +#define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ + +/* channel input capture polarity */ +#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ +#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge*/ +#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ + +/* TIMER input capture selection */ +#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel n is configured as input and icy is mapped on CIy / CINy */ +#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel n is configured as input and icy is mapped on opposite input */ +#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel n is configured as input and icy is mapped on ITS */ +#define TIMER_IC_SELECTION_PAIR ((uint16_t)0x0004U) /*!< channel n is configured as input and icy is mapped on the other channel of same pair */ + +/* channel input capture prescaler */ +#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ +#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ +#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */ +#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ + +/* trigger selection */ +#define SMCFG_TRGSEL(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4U)) | (BIT(31) & ((uint32_t)(regval) << 28U))) +#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ +#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ +#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ +#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ +#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 edge detector */ +#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered channel 0 input */ +#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered channel 1 input */ +#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< filtered external trigger input */ +#define TIMER_SMCFG_TRGSEL_CI2FE2 SMCFG_TRGSEL(8) /*!< filtered channel 2 input */ +#define TIMER_SMCFG_TRGSEL_CI3FE3 SMCFG_TRGSEL(9) /*!< filtered channel 3 input */ +#define TIMER_SMCFG_TRGSEL_MCI0FEM0 SMCFG_TRGSEL(10) /*!< filtered multi mode channel 0 input */ +#define TIMER_SMCFG_TRGSEL_MCI1FEM1 SMCFG_TRGSEL(11) /*!< filtered multi mode channel 1 input */ +#define TIMER_SMCFG_TRGSEL_MCI2FEM2 SMCFG_TRGSEL(12) /*!< filtered multi mode channel 2 input */ +#define TIMER_SMCFG_TRGSEL_MCI3FEM3 SMCFG_TRGSEL(13) /*!< filtered multi mode channel 3 input */ + +/* master mode control */ +#define CTL1_MMC(regval) (BITS(4,6) & ((uint32_t)(regval) << 4U)) +#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ +#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal as trigger output */ +#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ +#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */ +#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ + +/* slave mode control */ +#define SMCFG_SMC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U)) +#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ +#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ +#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ +#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ +#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ +#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ +#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ +#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ + +/* master slave mode selection */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ + +/* external trigger prescaler */ +#define SMCFG_ETPSC(regval) (BITS(12,13) & ((uint32_t)(regval) << 12U)) +#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ +#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ +#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ +#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ + +/* external trigger polarity */ +#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ +#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ + +/* channel 0 trigger input selection */ +#define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ + +/* TIMER1 channel 0 input remap */ +#define TIMER1_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U)) +#define TIMER1_CI0_RMP_GPIO TIMER1_IRMP(0) /*!< TIMER1 channel 0 input remap to GPIO pin */ +#define TIMER1_CI0_RMP_LXTAL TIMER1_IRMP(1) /*!< TIMER1 channel 0 input remap to LXTAL */ +#define TIMER1_CI0_RMP_HXTAL TIMER1_IRMP(2) /*!< TIMER1 channel 0 input remap to HXTAL/128 */ +#define TIMER1_CI0_RMP_CKOUT0SEL TIMER1_IRMP(3) /*!< TIMER1 channel 0 input remap to CKOUT0SEL */ + +/* TIMER write CHxVAL register selection */ +#define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_CHVSEL) /*!< write CHxVAL register selection enable */ +#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ + +/* TIMER output value selection enable */ +#define TIMER_OUTSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< output value selection enable */ +#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ + +/* channel additional output compare shadow enable */ +#define TIMER_ADD_SHADOW_ENABLE ((uint16_t)0x0001U) /*!< channel additional output shadow state enable */ +#define TIMER_ADD_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel additional output shadow state disable */ + +/* channel output compare shadow enable */ +#define TIMER_OMC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< multi mode channel output shadow state enable */ +#define TIMER_OMC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< multi mode channel output shadow state disable */ + +/* channel output compare clear enable */ +#define TIMER_OMC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< multi mode channel output clear function enable */ +#define TIMER_OMC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< multi mode channel output clear function disable */ + +/* TIMER output value selection */ +#define TIMER_PULSE_OUTPUT_NORMAL ((uint16_t)0x0000U) /*!< channel output normal */ +#define TIMER_PULSE_OUTPUT_CNT_UP ((uint16_t)0x0001U) /*!< pulse output only when counting up */ +#define TIMER_PULSE_OUTPUT_CNT_DOWN ((uint16_t)0x0002U) /*!< pulse output only when counting down */ +#define TIMER_PULSE_OUTPUT_CNT_BOTH ((uint16_t)0x0003U) /*!< pulse output when counting up or down */ +#define TIMER_PULSE_OUTPUT_MASK ((uint16_t)0x0003U) /*!< pulse output mode mask */ + +/* multi mode channel input capture polarity */ +#define TIMER_IMC_POLARITY_RISING ((uint16_t)0x0000U) /*!< multi mode channel input capture rising edge */ +#define TIMER_IMC_POLARITY_FALLING ((uint16_t)0x0001U) /*!< multi mode channel input capture falling edge */ +#define TIMER_IMC_POLARITY_BOTH_EDGE ((uint16_t)0x0003U) /*!< multi mode channel input capture both edge */ + +/* TIMER multi mode channel mode selection */ +#define TIMER_MCH_MODE_INDEPENDENTLY ((uint16_t)0x0000U) /*!< multi mode channel work in independently mode */ +#define TIMER_MCH_MODE_MIRRORED ((uint16_t)0x0001U) /*!< multi mode channel work in mirrored output mode */ +#define TIMER_MCH_MODE_COMPLEMENTARY ((uint16_t)0x0003U) /*!< multi mode channel work in complementary output mode */ +#define TIMER_MCH_MODE_MASK ((uint16_t)0x0003U) /*!< multi mode channel mode mask */ + +/* function declarations */ +/* TIMER timebase */ +/* deinit a TIMER */ +void timer_deinit(uint32_t timer_periph); +/* initialize TIMER init parameter struct */ +void timer_struct_para_init(timer_parameter_struct *initpara); +/* initialize TIMER counter */ +void gd32_timer_init(uint32_t timer_periph, timer_parameter_struct *initpara); +/* enable a TIMER */ +void timer_enable(uint32_t timer_periph); +/* disable a TIMER */ +void timer_disable(uint32_t timer_periph); +/* enable the auto reload shadow function */ +void timer_auto_reload_shadow_enable(uint32_t timer_periph); +/* disable the auto reload shadow function */ +void timer_auto_reload_shadow_disable(uint32_t timer_periph); +/* enable the update event */ +void timer_update_event_enable(uint32_t timer_periph); +/* disable the update event */ +void timer_update_event_disable(uint32_t timer_periph); +/* set TIMER counter alignment mode */ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); +/* set TIMER counter up direction */ +void timer_counter_up_direction(uint32_t timer_periph); +/* set TIMER counter down direction */ +void timer_counter_down_direction(uint32_t timer_periph); + +/* configure TIMER prescaler */ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload); +/* configure TIMER repetition register value */ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); +/* configure TIMER autoreload register value */ +void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload); +/* configure TIMER counter register value */ +void timer_counter_value_config(uint32_t timer_periph, uint16_t counter); +/* read TIMER counter value */ +uint32_t timer_counter_read(uint32_t timer_periph); +/* read TIMER prescaler value */ +uint16_t timer_prescaler_read(uint32_t timer_periph); +/* configure TIMER single pulse mode */ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); +/* configure TIMER update source */ +void timer_update_source_config(uint32_t timer_periph, uint32_t update); +/* configure channel commutation control shadow register */ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); +/* configure TIMER channel control shadow register update control */ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl); + +/* TIMER DMA and event */ +/* enable the TIMER DMA */ +void timer_dma_enable(uint32_t timer_periph, uint32_t dma); +/* disable the TIMER DMA */ +void timer_dma_disable(uint32_t timer_periph, uint32_t dma); +/* channel DMA request source selection */ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request); +/* configure the TIMER DMA transfer */ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); +/* software generate events */ +void timer_event_software_generate(uint32_t timer_periph, uint32_t event); + +/* TIMER channel complementary protection */ +/* initialize TIMER break parameter struct */ +void timer_break_struct_para_init(timer_break_parameter_struct *breakpara); +/* configure TIMER break function */ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara); +/* enable TIMER break function */ +void timer_break_enable(uint32_t timer_periph); +/* disable TIMER break function */ +void timer_break_disable(uint32_t timer_periph); +/* enable TIMER output automatic function */ +void timer_automatic_output_enable(uint32_t timer_periph); +/* disable TIMER output automatic function */ +void timer_automatic_output_disable(uint32_t timer_periph); +/* configure TIMER primary output function */ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); + +/* TIMER channel output */ +/* initialize TIMER channel output parameter struct */ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara); +/* configure TIMER channel output function */ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara); +/* configure TIMER channel output compare mode */ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); +/* configure TIMER channel output pulse value */ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); +/* configure TIMER channel output shadow function */ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); +/* configure TIMER channel output clear function */ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); +/* configure TIMER channel output polarity */ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); +/* configure TIMER channel complementary output polarity */ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); +/* configure TIMER channel enable state */ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); +/* configure TIMER channel complementary output enable state */ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); + +/* TIMER channel input */ +/* initialize TIMER channel input parameter struct */ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara); +/* configure TIMER input capture parameter */ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara); +/* configure TIMER channel input capture prescaler value */ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); +/* read TIMER channel capture compare register value */ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); +/* configure TIMER input pwm capture function */ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm); +/* configure TIMER hall sensor mode */ +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); + +/* TIMER multi mode channel */ +/* initialize TIMER multi mode channel output parameter struct */ +void timer_multi_mode_channel_output_parameter_struct_init(timer_omc_parameter_struct *omcpara); +/* configure TIMER multi mode channel output function */ +void timer_multi_mode_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_omc_parameter_struct *omcpara); +/* multi mode channel mode select */ +void timer_multi_mode_channel_mode_config(uint32_t timer_periph, uint32_t channel, uint32_t multi_mode_sel); + +/* TIMER master and slave mode */ +/* select TIMER input trigger source */ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); +/* select TIMER master mode output trigger source */ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); +/* select TIMER slave mode */ +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); +/* configure TIMER master slave mode */ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); +/* configure TIMER external trigger input */ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER quadrature decoder mode */ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); +/* configure TIMER internal clock mode */ +void timer_internal_clock_config(uint32_t timer_periph); +/* configure TIMER the internal trigger as external clock input */ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); +/* configure TIMER the external trigger as external clock input */ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 0 */ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 1 */ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* disable TIMER the external clock mode 1 */ +void timer_external_clock_mode1_disable(uint32_t timer_periph); + +/* TIMER configure */ +/* configure TIMER channel input remap function */ +void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap); +/* configure TIMER write CHxVAL register selection */ +void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); +/* configure TIMER output value selection */ +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); +/* configure TIMER output match pulse selection */ +void timer_output_match_pulse_select(uint32_t timer_periph, uint32_t channel, uint16_t pulsesel); + +/* TIMER composite PWM mode */ +/* configure the TIMER composite PWM mode */ +void timer_channel_composite_pwm_mode_config(uint32_t timer_periph, uint32_t channel, ControlStatus newvalue); +/* configure the TIMER composite PWM mode output pulse value */ +void timer_channel_composite_pwm_mode_output_pulse_value_config(uint32_t timer_periph, uint32_t channel, uint32_t pulse, uint32_t add_pulse); +/* configure TIMER channel additional compare value */ +void timer_channel_additional_compare_value_config(uint32_t timer_periph, uint16_t channel, uint32_t value); +/* configure TIMER channel additional output shadow function */ +void timer_channel_additional_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t aocshadow); + +/* TIMER break external inputs */ +/* initialize TIMER break external input parameter struct */ +void timer_break_external_input_struct_para_init(timer_break_ext_input_struct *breakinpara); +/* configure TIMER break external input polarity */ +void timer_break_external_input_config(uint32_t timer_periph, uint32_t break_input, timer_break_ext_input_struct *breakinpara); +/* break external input enable */ +void timer_break_external_input_enable(uint32_t timer_periph, uint32_t break_input); +/* break external input disable */ +void timer_break_external_input_disable(uint32_t timer_periph, uint32_t break_input); +/* configure TIMER break external input polarity */ +void timer_break_external_input_polarity_config(uint32_t timer_periph, uint32_t break_input, uint32_t polarity); + +/* TIMER channel free complementary protection */ +/* configure the TIMER channel break function */ +void timer_channel_break_control_config(uint32_t timer_periph, uint32_t channel, ControlStatus newvalue); +/* configure the TIMER channel dead time function */ +void timer_channel_dead_time_config(uint32_t timer_periph, uint32_t channel, ControlStatus newvalue); +/* initialize TIMER channel free complementary parameter struct with a default value */ +void timer_free_complementary_struct_para_init(timer_free_complementary_parameter_struct *freecompara); +/* configure channel free complementary protection */ +void timer_channel_free_complementary_config(uint32_t timer_periph, uint16_t channel, timer_free_complementary_parameter_struct *fcpara); + +/* TIMER interrupt and flag */ +/* get TIMER flags */ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); +/* clear TIMER flags */ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); +/* enable the TIMER interrupt */ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); +/* disable the TIMER interrupt */ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); +/* get TIMER interrupt flags */ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t int_flag); +/* clear TIMER interrupt flags */ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t int_flag); + +#endif /* GD32A50X_TIMER_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_trigsel.h b/gd32a50x/standard_peripheral/include/gd32a50x_trigsel.h new file mode 100644 index 0000000..f6dff24 --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_trigsel.h @@ -0,0 +1,210 @@ +/*! + \file gd32a50x_trigsel.h + \brief definitions for the TRIGSEL + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_TRIGSEL_H +#define GD32A50X_TRIGSEL_H + +#include "gd32a50x.h" + +/* TRIGSEL definitions */ +#define TRIGSEL TRIGSEL_BASE /*!< TRIGSEL base address */ + +/* register definitions */ +#define TRIGSEL_EXTOUT0 REG32((TRIGSEL) + 0x00000000U) /*!< TRIGSEL trigger selection for EXTOUT0 register */ +#define TRIGSEL_EXTOUT1 REG32((TRIGSEL) + 0x00000004U) /*!< TRIGSEL trigger selection for EXTOUT1 register */ +#define TRIGSEL_ADC0 REG32((TRIGSEL) + 0x00000008U) /*!< TRIGSEL trigger selection for ADC0 register */ +#define TRIGSEL_ADC1 REG32((TRIGSEL) + 0x0000000CU) /*!< TRIGSEL trigger selection for ADC1 register */ +#define TRIGSEL_DAC REG32((TRIGSEL) + 0x00000010U) /*!< TRIGSEL trigger selection for DAC register */ +#define TRIGSEL_TIMER0IN REG32((TRIGSEL) + 0x00000014U) /*!< TRIGSEL trigger selection for TIMER0_ITI register */ +#define TRIGSEL_TIMER0BRKIN REG32((TRIGSEL) + 0x00000018U) /*!< TRIGSEL trigger selection for TIMER0_BRKIN register */ +#define TRIGSEL_TIMER7IN REG32((TRIGSEL) + 0x0000001CU) /*!< TRIGSEL trigger selection for TIMER7_ITI register */ +#define TRIGSEL_TIMER7BRKIN REG32((TRIGSEL) + 0x00000020U) /*!< TRIGSEL trigger selection for TIMER7_BRKIN register */ +#define TRIGSEL_TIMER19IN REG32((TRIGSEL) + 0x00000024U) /*!< TRIGSEL trigger selection for TIMER19_ITI register */ +#define TRIGSEL_TIMER19BRKIN REG32((TRIGSEL) + 0x00000028U) /*!< TRIGSEL trigger selection for TIMER19_BRKIN register */ +#define TRIGSEL_TIMER20IN REG32((TRIGSEL) + 0x0000002CU) /*!< TRIGSEL trigger selection for TIMER20_ITI register */ +#define TRIGSEL_TIMER20BRKIN REG32((TRIGSEL) + 0x00000030U) /*!< TRIGSEL trigger selection for TIMER20_BRKIN register */ +#define TRIGSEL_TIMER1IN REG32((TRIGSEL) + 0x00000034U) /*!< TRIGSEL trigger selection for TIMER1_ITI register */ +#define TRIGSEL_MFCOM REG32((TRIGSEL) + 0x00000038U) /*!< TRIGSEL trigger selection for MFCOM register */ +#define TRIGSEL_CAN0 REG32((TRIGSEL) + 0x0000003CU) /*!< TRIGSEL trigger selection for CAN0 register */ +#define TRIGSEL_CAN1 REG32((TRIGSEL) + 0x00000040U) /*!< TRIGSEL trigger selection for CAN1 register */ + +/* bits definitions */ +#define TRIGSEL_TARGET_INSEL0 BITS(0, 6) /*!< trigger input source selection for output0 */ +#define TRIGSEL_TARGET_INSEL1 BITS(8, 14) /*!< trigger input source selection for output1 */ +#define TRIGSEL_TARGET_INSEL2 BITS(16, 22) /*!< trigger input source selection for output2 */ +#define TRIGSEL_TARGET_INSEL3 BITS(24, 30) /*!< trigger input source selection for output3 */ +#define TRIGSEL_TARGET_LK BIT(31) /*!< TRIGSEL register lock */ + +/* constants definitions */ +/* trigger source definitions */ +typedef enum +{ + TRIGSEL_INPUT_0 = ((uint8_t)0x00U), /*!< trigger input source 0 */ + TRIGSEL_INPUT_1 = ((uint8_t)0x01U), /*!< trigger input source 1 */ + TRIGSEL_INPUT_TRIGSEL_IN0 = ((uint8_t)0x02U), /*!< trigger input source TRIGSEL_IN0 pin */ + TRIGSEL_INPUT_TRIGSEL_IN1 = ((uint8_t)0x03U), /*!< trigger input source TRIGSEL_IN1 pin */ + TRIGSEL_INPUT_TRIGSEL_IN2 = ((uint8_t)0x04U), /*!< trigger input source TRIGSEL_IN2 pin */ + TRIGSEL_INPUT_TRIGSEL_IN3 = ((uint8_t)0x05U), /*!< trigger input source TRIGSEL_IN3 pin */ + TRIGSEL_INPUT_TRIGSEL_IN4 = ((uint8_t)0x06U), /*!< trigger input source TRIGSEL_IN4 pin */ + TRIGSEL_INPUT_TRIGSEL_IN5 = ((uint8_t)0x07U), /*!< trigger input source TRIGSEL_IN5 pin */ + TRIGSEL_INPUT_TRIGSEL_IN6 = ((uint8_t)0x08U), /*!< trigger input source TRIGSEL_IN6 pin */ + TRIGSEL_INPUT_TRIGSEL_IN7 = ((uint8_t)0x09U), /*!< trigger input source TRIGSEL_IN7 pin */ + TRIGSEL_INPUT_TRIGSEL_IN8 = ((uint8_t)0x0AU), /*!< trigger input source TRIGSEL_IN8 pin */ + TRIGSEL_INPUT_TRIGSEL_IN9 = ((uint8_t)0x0BU), /*!< trigger input source TRIGSEL_IN9 pin */ + TRIGSEL_INPUT_TRIGSEL_IN10 = ((uint8_t)0x0CU), /*!< trigger input source TRIGSEL_IN10 pin */ + TRIGSEL_INPUT_TRIGSEL_IN11 = ((uint8_t)0x0DU), /*!< trigger input source TRIGSEL_IN11 pin */ + TRIGSEL_INPUT_CMP_OUT = ((uint8_t)0x0EU), /*!< trigger input source CMP_OUT */ + TRIGSEL_INPUT_LXTAL_TRG = ((uint8_t)0x10U), /*!< trigger input source LXTAL_TRG */ + TRIGSEL_INPUT_TIMER1_CH0 = ((uint8_t)0x11U), /*!< trigger input source timer1 channel 0 */ + TRIGSEL_INPUT_TIMER1_CH1 = ((uint8_t)0x12U), /*!< trigger input source timer1 channel 1 */ + TRIGSEL_INPUT_TIMER1_CH2 = ((uint8_t)0x13U), /*!< trigger input source timer1 channel 2 */ + TRIGSEL_INPUT_TIMER1_CH3 = ((uint8_t)0x14U), /*!< trigger input source timer1 channel 3 */ + TRIGSEL_INPUT_TIMER1_TRGO = ((uint8_t)0x15U), /*!< trigger input source timer1 TRGO */ + TRIGSEL_INPUT_TIMER0_CH0 = ((uint8_t)0x16U), /*!< trigger input source timer0 channel 0 */ + TRIGSEL_INPUT_TIMER0_CH1 = ((uint8_t)0x17U), /*!< trigger input source timer0 channel 1 */ + TRIGSEL_INPUT_TIMER0_CH2 = ((uint8_t)0x18U), /*!< trigger input source timer0 channel 2 */ + TRIGSEL_INPUT_TIMER0_CH3 = ((uint8_t)0x19U), /*!< trigger input source timer0 channel 3 */ + TRIGSEL_INPUT_TIMER0_MCH0 = ((uint8_t)0x1AU), /*!< trigger input source timer0 multi mode channel 0 */ + TRIGSEL_INPUT_TIMER0_MCH1 = ((uint8_t)0x1BU), /*!< trigger input source timer0 multi mode channel 1 */ + TRIGSEL_INPUT_TIMER0_MCH2 = ((uint8_t)0x1CU), /*!< trigger input source timer0 multi mode channel 2 */ + TRIGSEL_INPUT_TIMER0_MCH3 = ((uint8_t)0x1DU), /*!< trigger input source timer0 multi mode channel 3 */ + TRIGSEL_INPUT_TIMER0_TRGO = ((uint8_t)0x1EU), /*!< trigger input source timer0 TRGO */ + TRIGSEL_INPUT_TIMER7_CH0 = ((uint8_t)0x1FU), /*!< trigger input source timer7 channel 0 */ + TRIGSEL_INPUT_TIMER7_CH1 = ((uint8_t)0x20U), /*!< trigger input source timer7 channel 1 */ + TRIGSEL_INPUT_TIMER7_CH2 = ((uint8_t)0x21U), /*!< trigger input source timer7 channel 2 */ + TRIGSEL_INPUT_TIMER7_CH3 = ((uint8_t)0x22U), /*!< trigger input source timer7 channel 3 */ + TRIGSEL_INPUT_TIMER7_MCH0 = ((uint8_t)0x23U), /*!< trigger input source timer7 multi mode channel 0 */ + TRIGSEL_INPUT_TIMER7_MCH1 = ((uint8_t)0x24U), /*!< trigger input source timer7 multi mode channel 1 */ + TRIGSEL_INPUT_TIMER7_MCH2 = ((uint8_t)0x25U), /*!< trigger input source timer7 multi mode channel 2 */ + TRIGSEL_INPUT_TIMER7_MCH3 = ((uint8_t)0x26U), /*!< trigger input source timer7 multi mode channel 3 */ + TRIGSEL_INPUT_TIMER7_TRGO = ((uint8_t)0x27U), /*!< trigger input source timer7 TRGO */ + TRIGSEL_INPUT_TIMER19_CH0 = ((uint8_t)0x28U), /*!< trigger input source timer19 channel 0 */ + TRIGSEL_INPUT_TIMER19_CH1 = ((uint8_t)0x29U), /*!< trigger input source timer19 channel 1 */ + TRIGSEL_INPUT_TIMER19_CH2 = ((uint8_t)0x2AU), /*!< trigger input source timer19 channel 2 */ + TRIGSEL_INPUT_TIMER19_CH3 = ((uint8_t)0x2BU), /*!< trigger input source timer19 channel 3 */ + TRIGSEL_INPUT_TIMER19_MCH0 = ((uint8_t)0x2CU), /*!< trigger input source timer19 multi mode channel 0 */ + TRIGSEL_INPUT_TIMER19_MCH1 = ((uint8_t)0x2DU), /*!< trigger input source timer19 multi mode channel 1 */ + TRIGSEL_INPUT_TIMER19_MCH2 = ((uint8_t)0x2EU), /*!< trigger input source timer19 multi mode channel 2 */ + TRIGSEL_INPUT_TIMER19_MCH3 = ((uint8_t)0x2FU), /*!< trigger input source timer19 multi mode channel 3 */ + TRIGSEL_INPUT_TIMER19_TRGO = ((uint8_t)0x30U), /*!< trigger input source timer19 TRGO */ + TRIGSEL_INPUT_TIMER20_CH0 = ((uint8_t)0x31U), /*!< trigger input source timer20 channel 0 */ + TRIGSEL_INPUT_TIMER20_CH1 = ((uint8_t)0x32U), /*!< trigger input source timer20 channel 1 */ + TRIGSEL_INPUT_TIMER20_CH2 = ((uint8_t)0x33U), /*!< trigger input source timer20 channel 2 */ + TRIGSEL_INPUT_TIMER20_CH3 = ((uint8_t)0x34U), /*!< trigger input source timer20 channel 3 */ + TRIGSEL_INPUT_TIMER20_MCH0 = ((uint8_t)0x35U), /*!< trigger input source timer20 multi mode channel 0 */ + TRIGSEL_INPUT_TIMER20_MCH1 = ((uint8_t)0x36U), /*!< trigger input source timer20 multi mode channel 1 */ + TRIGSEL_INPUT_TIMER20_MCH2 = ((uint8_t)0x37U), /*!< trigger input source timer20 multi mode channel 2 */ + TRIGSEL_INPUT_TIMER20_MCH3 = ((uint8_t)0x38U), /*!< trigger input source timer20 multi mode channel 3 */ + TRIGSEL_INPUT_TIMER20_TRGO = ((uint8_t)0x39U), /*!< trigger input source timer20 TRGO */ + TRIGSEL_INPUT_TIMER5_TRGO = ((uint8_t)0x3AU), /*!< trigger input source timer5 TRGO */ + TRIGSEL_INPUT_TIMER6_TRGO = ((uint8_t)0x3BU), /*!< trigger input source timer6 TRGO */ + TRIGSEL_INPUT_MFCOM_TRIG0 = ((uint8_t)0x3CU), /*!< trigger input source MFCOM TRIG0 */ + TRIGSEL_INPUT_MFCOM_TRIG1 = ((uint8_t)0x3DU), /*!< trigger input source MFCOM TRIG1 */ + TRIGSEL_INPUT_MFCOM_TRIG2 = ((uint8_t)0x3EU), /*!< trigger input source MFCOM TRIG2 */ + TRIGSEL_INPUT_MFCOM_TRIG3 = ((uint8_t)0x3FU), /*!< trigger input source MFCOM TRIG3 */ + TRIGSEL_INPUT_RTC_ALARM = ((uint8_t)0x40U), /*!< trigger input source RTC alarm */ + TRIGSEL_INPUT_RTC_SECOND = ((uint8_t)0x41U), /*!< trigger input source RTC second */ + TRIGSEL_INPUT_TRIGSEL_IN12 = ((uint8_t)0x42U), /*!< trigger input source TRIGSEL_IN12 pin */ + TRIGSEL_INPUT_TRIGSEL_IN13 = ((uint8_t)0x43U), /*!< trigger input source TRIGSEL_IN13 pin */ +}trigsel_source_enum; + +/* target peripheral definitions */ +typedef enum +{ + TRIGSEL_OUTPUT_TRIGSEL_OUT0 = ((uint8_t)0x00U), /*!< output target peripheral TRIGSEL_OUT0 pin */ + TRIGSEL_OUTPUT_TRIGSEL_OUT1 = ((uint8_t)0x01U), /*!< output target peripheral TRIGSEL_OUT1 pin */ + TRIGSEL_OUTPUT_TRIGSEL_OUT2 = ((uint8_t)0x02U), /*!< output target peripheral TRIGSEL_OUT2 pin */ + TRIGSEL_OUTPUT_TRIGSEL_OUT3 = ((uint8_t)0x03U), /*!< output target peripheral TRIGSEL_OUT3 pin */ + TRIGSEL_OUTPUT_TRIGSEL_OUT4 = ((uint8_t)0x04U), /*!< output target peripheral TRIGSEL_OUT4 pin */ + TRIGSEL_OUTPUT_TRIGSEL_OUT5 = ((uint8_t)0x05U), /*!< output target peripheral TRIGSEL_OUT5 pin */ + TRIGSEL_OUTPUT_TRIGSEL_OUT6 = ((uint8_t)0x06U), /*!< output target peripheral TRIGSEL_OUT6 pin */ + TRIGSEL_OUTPUT_TRIGSEL_OUT7 = ((uint8_t)0x07U), /*!< output target peripheral TRIGSEL_OUT7 pin */ + TRIGSEL_OUTPUT_ADC0_RTTRG = ((uint8_t)0x08U), /*!< output target peripheral ADC0_RTTRG */ + TRIGSEL_OUTPUT_ADC1_RTTRG = ((uint8_t)0x0CU), /*!< output target peripheral ADC1_RTTRG */ + TRIGSEL_OUTPUT_DAC_EXTRIG = ((uint8_t)0x10U), /*!< output target peripheral DAC_EXTRIG */ + TRIGSEL_OUTPUT_TIMER0_ITI0 = ((uint8_t)0x14U), /*!< output target peripheral TIMER0_ITI0 */ + TRIGSEL_OUTPUT_TIMER0_ITI1 = ((uint8_t)0x15U), /*!< output target peripheral TIMER0_ITI1 */ + TRIGSEL_OUTPUT_TIMER0_ITI2 = ((uint8_t)0x16U), /*!< output target peripheral TIMER0_ITI2 */ + TRIGSEL_OUTPUT_TIMER0_ITI3 = ((uint8_t)0x17U), /*!< output target peripheral TIMER0_ITI3 */ + TRIGSEL_OUTPUT_TIMER0_BRKIN0 = ((uint8_t)0x18U), /*!< output target peripheral TIMER0_BRKIN0 */ + TRIGSEL_OUTPUT_TIMER0_BRKIN1 = ((uint8_t)0x19U), /*!< output target peripheral TIMER0_BRKIN1 */ + TRIGSEL_OUTPUT_TIMER0_BRKIN2 = ((uint8_t)0x1AU), /*!< output target peripheral TIMER0_BRKIN2 */ + TRIGSEL_OUTPUT_TIMER0_BRKIN3 = ((uint8_t)0x1BU), /*!< output target peripheral TIMER0_BRKIN3 */ + TRIGSEL_OUTPUT_TIMER7_ITI0 = ((uint8_t)0x1CU), /*!< output target peripheral TIMER7_ITI0 */ + TRIGSEL_OUTPUT_TIMER7_ITI1 = ((uint8_t)0x1DU), /*!< output target peripheral TIMER7_ITI1 */ + TRIGSEL_OUTPUT_TIMER7_ITI2 = ((uint8_t)0x1EU), /*!< output target peripheral TIMER7_ITI2 */ + TRIGSEL_OUTPUT_TIMER7_ITI3 = ((uint8_t)0x1FU), /*!< output target peripheral TIMER7_ITI3 */ + TRIGSEL_OUTPUT_TIMER7_BRKIN0 = ((uint8_t)0x20U), /*!< output target peripheral TIMER7_BRKIN0 */ + TRIGSEL_OUTPUT_TIMER7_BRKIN1 = ((uint8_t)0x21U), /*!< output target peripheral TIMER7_BRKIN1 */ + TRIGSEL_OUTPUT_TIMER7_BRKIN2 = ((uint8_t)0x22U), /*!< output target peripheral TIMER7_BRKIN2 */ + TRIGSEL_OUTPUT_TIMER7_BRKIN3 = ((uint8_t)0x23U), /*!< output target peripheral TIMER7_BRKIN3 */ + TRIGSEL_OUTPUT_TIMER19_ITI0 = ((uint8_t)0x24U), /*!< output target peripheral TIMER19_ITI0 */ + TRIGSEL_OUTPUT_TIMER19_ITI1 = ((uint8_t)0x25U), /*!< output target peripheral TIMER19_ITI1 */ + TRIGSEL_OUTPUT_TIMER19_ITI2 = ((uint8_t)0x26U), /*!< output target peripheral TIMER19_ITI2 */ + TRIGSEL_OUTPUT_TIMER19_ITI3 = ((uint8_t)0x27U), /*!< output target peripheral TIMER19_ITI3 */ + TRIGSEL_OUTPUT_TIMER19_BRKIN0 = ((uint8_t)0x28U), /*!< output target peripheral TIMER19_BRKIN0 */ + TRIGSEL_OUTPUT_TIMER19_BRKIN1 = ((uint8_t)0x29U), /*!< output target peripheral TIMER19_BRKIN1 */ + TRIGSEL_OUTPUT_TIMER19_BRKIN2 = ((uint8_t)0x2AU), /*!< output target peripheral TIMER19_BRKIN2 */ + TRIGSEL_OUTPUT_TIMER19_BRKIN3 = ((uint8_t)0x2BU), /*!< output target peripheral TIMER19_BRKIN3 */ + TRIGSEL_OUTPUT_TIMER20_ITI0 = ((uint8_t)0x2CU), /*!< output target peripheral TIMER20_ITI0 */ + TRIGSEL_OUTPUT_TIMER20_ITI1 = ((uint8_t)0x2DU), /*!< output target peripheral TIMER20_ITI1 */ + TRIGSEL_OUTPUT_TIMER20_ITI2 = ((uint8_t)0x2EU), /*!< output target peripheral TIMER20_ITI2 */ + TRIGSEL_OUTPUT_TIMER20_ITI3 = ((uint8_t)0x2FU), /*!< output target peripheral TIMER20_ITI3 */ + TRIGSEL_OUTPUT_TIMER20_BRKIN0 = ((uint8_t)0x30U), /*!< output target peripheral TIMER20_BRKIN0 */ + TRIGSEL_OUTPUT_TIMER20_BRKIN1 = ((uint8_t)0x31U), /*!< output target peripheral TIMER20_BRKIN1 */ + TRIGSEL_OUTPUT_TIMER20_BRKIN2 = ((uint8_t)0x32U), /*!< output target peripheral TIMER20_BRKIN2 */ + TRIGSEL_OUTPUT_TIMER20_BRKIN3 = ((uint8_t)0x33U), /*!< output target peripheral TIMER20_BRKIN3 */ + TRIGSEL_OUTPUT_TIMER1_ITI0 = ((uint8_t)0x34U), /*!< output target peripheral TIMER1_ITI0 */ + TRIGSEL_OUTPUT_TIMER1_ITI1 = ((uint8_t)0x35U), /*!< output target peripheral TIMER1_ITI1 */ + TRIGSEL_OUTPUT_TIMER1_ITI2 = ((uint8_t)0x36U), /*!< output target peripheral TIMER1_ITI2 */ + TRIGSEL_OUTPUT_TIMER1_ITI3 = ((uint8_t)0x37U), /*!< output target peripheral TIMER1_ITI3 */ + TRIGSEL_OUTPUT_MFCOM_TRG_TIMER0 = ((uint8_t)0x38U), /*!< output target peripheral MFCOM_TRG_TIMER0 */ + TRIGSEL_OUTPUT_MFCOM_TRG_TIMER1 = ((uint8_t)0x39U), /*!< output target peripheral MFCOM_TRG_TIMER1 */ + TRIGSEL_OUTPUT_MFCOM_TRG_TIMER2 = ((uint8_t)0x3AU), /*!< output target peripheral MFCOM_TRG_TIMER2 */ + TRIGSEL_OUTPUT_MFCOM_TRG_TIMER3 = ((uint8_t)0x3BU), /*!< output target peripheral MFCOM_TRG_TIMER3 */ + TRIGSEL_OUTPUT_CAN0_EX_TIME_TICK = ((uint8_t)0x3CU), /*!< output target peripheral CAN0_EX_TIME_TICK */ + TRIGSEL_OUTPUT_CAN1_EX_TIME_TICK = ((uint8_t)0x40U), /*!< output target peripheral CAN1_EX_TIME_TICK */ +}trigsel_periph_enum; + +/* function declarations */ +/* set the trigger input signal for target peripheral */ +void trigsel_init(trigsel_periph_enum target_periph, trigsel_source_enum trigger_source); +/* get the trigger input signal for target peripheral */ +uint8_t trigsel_trigger_source_get(trigsel_periph_enum target_periph); +/* lock the trigger register */ +void trigsel_register_lock_set(trigsel_periph_enum target_periph); +/* get the trigger register lock status */ +FlagStatus trigsel_register_lock_get(trigsel_periph_enum target_periph); + +#endif /* GD32A50X_TRIGSEL_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_usart.h b/gd32a50x/standard_peripheral/include/gd32a50x_usart.h new file mode 100644 index 0000000..9df7f98 --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_usart.h @@ -0,0 +1,593 @@ +/*! + \file gd32a50x_usart.h + \brief definitions for the USART + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_USART_H +#define GD32A50X_USART_H + +#include "gd32a50x.h" + +#define USART1 USART_BASE +#define USART2 (USART_BASE + 0x00000400U) +#define USART0 (USART_BASE + 0x0000F400U) + +/* registers definitions */ +#define USART_CTL0(usartx) REG32((usartx) + 0x00000000U) /*!< USART control register 0 */ +#define USART_CTL1(usartx) REG32((usartx) + 0x00000004U) /*!< USART control register 1 */ +#define USART_CTL2(usartx) REG32((usartx) + 0x00000008U) /*!< USART control register 2 */ +#define USART_BAUD(usartx) REG32((usartx) + 0x0000000CU) /*!< USART baud rate register */ +#define USART_GP(usartx) REG32((usartx) + 0x00000010U) /*!< USART guard time and prescaler register */ +#define USART_RT(usartx) REG32((usartx) + 0x00000014U) /*!< USART receiver timeout register */ +#define USART_CMD(usartx) REG32((usartx) + 0x00000018U) /*!< USART command register */ +#define USART_STAT(usartx) REG32((usartx) + 0x0000001CU) /*!< USART status register */ +#define USART_INTC(usartx) REG32((usartx) + 0x00000020U) /*!< USART status clear register */ +#define USART_RDATA(usartx) REG32((usartx) + 0x00000024U) /*!< USART receive data register */ +#define USART_TDATA(usartx) REG32((usartx) + 0x00000028U) /*!< USART transmit data register */ +#define USART_CHC(usartx) REG32((usartx) + 0x000000C0U) /*!< USART coherence control register */ +#define USART_RFCS(usartx) REG32((usartx) + 0x000000D0U) /*!< USART receive FIFO control and status register */ + +/* bits definitions */ +/* USARTx_CTL0 */ +#define USART_CTL0_UEN BIT(0) /*!< enable USART */ +#define USART_CTL0_UESM BIT(1) /*!< enable USART in deep-sleep mode */ +#define USART_CTL0_REN BIT(2) /*!< enable receiver */ +#define USART_CTL0_TEN BIT(3) /*!< enable transmitter */ +#define USART_CTL0_IDLEIE BIT(4) /*!< enable idle line detected interrupt */ +#define USART_CTL0_RBNEIE BIT(5) /*!< renable ead data buffer not empty interrupt and overrun error interrupt */ +#define USART_CTL0_TCIE BIT(6) /*!< enable transmission complete interrupt */ +#define USART_CTL0_TBEIE BIT(7) /*!< enable transmitter register empty interrupt */ +#define USART_CTL0_PERRIE BIT(8) /*!< enable parity error interrupt */ +#define USART_CTL0_PM BIT(9) /*!< parity mode */ +#define USART_CTL0_PCEN BIT(10) /*!< enable parity control */ +#define USART_CTL0_WM0 BIT(11) /*!< wakeup method in mute mode */ +#define USART_CTL0_WL BIT(12) /*!< word length */ +#define USART_CTL0_MEN BIT(13) /*!< enable mute mode */ +#define USART_CTL0_AMIE BIT(14) /*!< enable address match interrupt */ +#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ +#define USART_CTL0_DED BITS(16,20) /*!< enable driver deassertion time */ +#define USART_CTL0_DEA BITS(21,25) /*!< enable driver assertion time */ +#define USART_CTL0_RTIE BIT(26) /*!< enable receiver timeout interrupt */ +#define USART_CTL0_EBIE BIT(27) /*!< enable end of block interrupt */ +#define USART_CTL0_WM1 BIT(28) /*!< enable driver assertion time */ + +/* USARTx_CTL1 */ +#define USART_CTL1_ADDM BIT(4) /*!< address detection mode */ +#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ +#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detection interrupt enable */ +#define USART_CTL1_CLEN BIT(8) /*!< last bit clock pulse */ +#define USART_CTL1_CPH BIT(9) /*!< clock phase */ +#define USART_CTL1_CPL BIT(10) /*!< clock polarity */ +#define USART_CTL1_CKEN BIT(11) /*!< ck pin enable */ +#define USART_CTL1_STB BITS(12,13) /*!< stop bits length */ +#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ +#define USART_CTL1_STRP BIT(15) /*!< swap TX/RX pins */ +#define USART_CTL1_RINV BIT(16) /*!< RX pin level inversion */ +#define USART_CTL1_TINV BIT(17) /*!< TX pin level inversion */ +#define USART_CTL1_DINV BIT(18) /*!< data bit level inversion */ +#define USART_CTL1_MSBF BIT(19) /*!< most significant bit first */ +#define USART_CTL1_RTEN BIT(23) /*!< receiver timeout enable */ +#define USART_CTL1_ADDR_DATA BITS(24,31) /*!< address of the USART terminal */ + +/* USARTx_CTL2 */ +#define USART_CTL2_ERRIE BIT(0) /*!< enable error interrupt in multibuffer communication */ +#define USART_CTL2_IREN BIT(1) /*!< enable IrDA mode */ +#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ +#define USART_CTL2_HDEN BIT(3) /*!< enable half-duplex */ +#define USART_CTL2_NKEN BIT(4) /*!< enable NACK in smartcard mode */ +#define USART_CTL2_SCEN BIT(5) /*!< enable smartcard mode */ +#define USART_CTL2_DENR BIT(6) /*!< enable DMA for reception */ +#define USART_CTL2_DENT BIT(7) /*!< enable DMA for transmission */ +#define USART_CTL2_RTSEN BIT(8) /*!< enable RTS */ +#define USART_CTL2_CTSEN BIT(9) /*!< enable CTS */ +#define USART_CTL2_CTSIE BIT(10) /*!< enable CTS interrupt */ +#define USART_CTL2_OSB BIT(11) /*!< one sample bit mode */ +#define USART_CTL2_OVRD BIT(12) /*!< disable overrun */ +#define USART_CTL2_DDRE BIT(13) /*!< disable DMA on reception error */ +#define USART_CTL2_DEM BIT(14) /*!< enable driver mode */ +#define USART_CTL2_DEP BIT(15) /*!< enable driver polarity mode */ +#define USART_CTL2_SCRTNUM BITS(17,19) /*!< smartcard auto-retry number */ +#define USART_CTL2_WUM BITS(20,21) /*!< wakeup mode from deep-sleep mode */ +#define USART_CTL2_WUIE BIT(22) /*!< enable wakeup from deep-sleep mode interrupt */ + +/* USARTx_BAUD */ +#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction of baud-rate divider */ +#define USART_BAUD_INTDIV BITS(4,15) /*!< integer of baud-rate divider */ + +/* USARTx_GP */ +#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ + +/* USARTx_RT */ +#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ +#define USART_RT_BL BITS(24,31) /*!< block length */ + +/* USARTx_CMD */ +#define USART_CMD_SBKCMD BIT(1) /*!< send break command */ +#define USART_CMD_MMCMD BIT(2) /*!< mute mode command */ +#define USART_CMD_RXFCMD BIT(3) /*!< receive data flush command */ +#define USART_CMD_TXFCMD BIT(4) /*!< transmit data flush request */ + +/* USARTx_STAT */ +#define USART_STAT_PERR BIT(0) /*!< parity error flag */ +#define USART_STAT_FERR BIT(1) /*!< frame error flag */ +#define USART_STAT_NERR BIT(2) /*!< noise error flag */ +#define USART_STAT_ORERR BIT(3) /*!< overrun error */ +#define USART_STAT_IDLEF BIT(4) /*!< idle line detected flag */ +#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ +#define USART_STAT_TC BIT(6) /*!< transmission completed */ +#define USART_STAT_TBE BIT(7) /*!< transmit data register empty */ +#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ +#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ +#define USART_STAT_CTS BIT(10) /*!< CTS level */ +#define USART_STAT_RTF BIT(11) /*!< receiver timeout flag */ +#define USART_STAT_EBF BIT(12) /*!< end of block flag */ +#define USART_STAT_BSY BIT(16) /*!< busy flag */ +#define USART_STAT_AMF BIT(17) /*!< address match flag */ +#define USART_STAT_SBF BIT(18) /*!< send break flag */ +#define USART_STAT_RWU BIT(19) /*!< receiver wakeup from mute mode */ +#define USART_STAT_WUF BIT(20) /*!< wakeup from deep-sleep mode flag */ +#define USART_STAT_TEA BIT(21) /*!< transmit enable acknowledge flag */ +#define USART_STAT_REA BIT(22) /*!< receive enable acknowledge flag */ + +/* USARTx_INTC */ +#define USART_INTC_PEC BIT(0) /*!< clear parity error */ +#define USART_INTC_FEC BIT(1) /*!< clear frame error flag */ +#define USART_INTC_NEC BIT(2) /*!< clear noise detected */ +#define USART_INTC_OREC BIT(3) /*!< clear overrun error */ +#define USART_INTC_IDLEC BIT(4) /*!< clear idle line detected */ +#define USART_INTC_TCC BIT(6) /*!< clear transmission complete */ +#define USART_INTC_LBDC BIT(8) /*!< clear LIN break detected */ +#define USART_INTC_CTSC BIT(9) /*!< clear CTS change */ +#define USART_INTC_RTC BIT(11) /*!< clear receiver timeout */ +#define USART_INTC_EBC BIT(12) /*!< clear end of timeout */ +#define USART_INTC_AMC BIT(17) /*!< clear address match */ +#define USART_INTC_WUC BIT(20) /*!< clear wakeup from deep-sleep mode */ + +/* USARTx_RDATA */ +#define USART_RDATA_RDATA BITS(0,8) /*!< receive data value */ + +/* USARTx_TDATA */ +#define USART_TDATA_TDATA BITS(0,8) /*!< transmit data value */ + +/* USARTx_CHC */ +#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ +#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ + +/* USARTx_RFCS */ +#define USART_RFCS_ELNACK BIT(0) /*!< early NACK */ +#define USART_RFCS_RFEN BIT(8) /*!< enable receive FIFO */ +#define USART_RFCS_RFFIE BIT(9) /*!< enable receive FIFO full interrupt */ +#define USART_RFCS_RFE BIT(10) /*!< receive FIFO empty flag */ +#define USART_RFCS_RFF BIT(11) /*!< receive FIFO full flag */ +#define USART_RFCS_RFCNT BITS(12,14) /*!< receive FIFO counter number */ +#define USART_RFCS_RFFINT BIT(15) /*!< receive FIFO full interrupt flag */ + +/* constants definitions */ +/* define the USART bit position and its register index offset */ +#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) +#define USART_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) +#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) +#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) + +/* register offset */ +#define USART_CTL0_REG_OFFSET 0x00000000U /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET 0x00000004U /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET 0x00000008U /*!< CTL2 register offset */ +#define USART_STAT_REG_OFFSET 0x0000001CU /*!< STAT register offset */ +#define USART_CHC_REG_OFFSET 0x000000C0U /*!< CHC register offset */ +#define USART_RFCS_REG_OFFSET 0x000000D0U /*!< RFCS register offset */ + +/* USART flags */ +typedef enum{ + /* flags in STAT register */ + USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U), /*!< receive enable acknowledge flag */ + USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U), /*!< transmit enable acknowledge flag */ + USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode flag */ + USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U), /*!< receiver wakeup from mute mode */ + USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U), /*!< send break flag */ + USART_FLAG_AM = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U), /*!< ADDR match flag */ + USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 16U), /*!< busy flag */ + USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 12U), /*!< end of block flag */ + USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout flag */ + USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 10U), /*!< CTS level */ + USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ + USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ + USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ + USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ + USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ + USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected flag */ + USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ + USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ + USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ + USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ + /* flags in CHC register */ + USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ + /* flags in RFCS register */ + USART_FLAG_RFFINT = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt flag */ + USART_FLAG_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 11U), /*!< receive FIFO full flag */ + USART_FLAG_RFE = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 10U), /*!< receive FIFO empty flag */ +}usart_flag_enum; + +/* USART interrupt flags */ +typedef enum +{ + /* interrupt flags in CTL0 register */ + USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U), /*!< end of block interrupt and flag */ + USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout interrupt and flag */ + USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U), /*!< address match interrupt and flag */ + USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ + USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ + USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ + USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ + USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ + USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ + /* interrupt flags in CTL1 register */ + USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ + /* interrupt flags in CTL2 register */ + USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode interrupt and flag */ + USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ + USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ + USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ + USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ + /* interrupt flags in RFCS register */ + USART_INT_FLAG_RFF = USART_REGIDX_BIT2(USART_RFCS_REG_OFFSET, 9U, USART_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt and flag */ +}usart_interrupt_flag_enum; + +/* enable or disable USART interrupt */ +typedef enum +{ + /* interrupt in CTL0 register */ + USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U), /*!< end of block interrupt */ + USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U), /*!< receiver timeout interrupt */ + USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U), /*!< address match interrupt */ + USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ + USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ + USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ + USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ + USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ + /* interrupt in CTL1 register */ + USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ + /* interrupt in CTL2 register */ + USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U), /*!< wakeup from deep-sleep mode interrupt */ + USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ + USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ + /* interrupt in RFCS register */ + USART_INT_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 9U), /*!< receive FIFO full interrupt */ +}usart_interrupt_enum; + +/* configure USART invert */ +typedef enum { + /* data bit level inversion */ + USART_DINV_ENABLE, /*!< data bit level inversion */ + USART_DINV_DISABLE, /*!< data bit level not inversion */ + /* TX pin level inversion */ + USART_TXPIN_ENABLE, /*!< TX pin level inversion */ + USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ + /* RX pin level inversion */ + USART_RXPIN_ENABLE, /*!< RX pin level inversion */ + USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ + /* swap TX/RX pins */ + USART_SWAP_ENABLE, /*!< swap TX/RX pins */ + USART_SWAP_DISABLE, /*!< not swap TX/RX pins */ +}usart_invert_enum; + +/* configure USART receiver */ +#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ +#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ + +/* configure USART transmitter */ +#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) +#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ +#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ + +/* USART parity bits definitions */ +#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) +#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ +#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ +#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ + +/* USART wakeup method in mute mode */ +#define CTL0_WM(regval1, regval2) ((BIT(11) & ((uint32_t)(regval1) << 11)) | (BIT(28) & ((uint32_t)(regval2) << 28))) +#define USART_WM_IDLE CTL0_WM(0, 0) /*!< idle line */ +#define USART_WM_ADDR CTL0_WM(1, 0) /*!< address match */ +#define USART_WM_DATA CTL0_WM(1, 1) /*!< data match */ + +/* USART word length definitions */ +#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) +#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ +#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ + +/* USART oversample mode */ +#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15)) +#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< oversampling by 8 */ +#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< oversampling by 16 */ + +/* USART address detection mode */ +#define CTL1_ADDM(regval) (BIT(4) & ((uint32_t)(regval) << 4)) +#define USART_ADDM_4BIT CTL1_ADDM(0) /*!< 4-bit address detection */ +#define USART_ADDM_FULLBIT CTL1_ADDM(1) /*!< full-bit address detection */ + +/* USART LIN break frame length */ +#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) +#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits break detection */ +#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits break detection */ + +/* USART last bit clock pulse */ +#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_CLEN_NONE CTL1_CLEN(0) /*!< clock pulse of the last data bit (MSB) is not output to the CK pin */ +#define USART_CLEN_EN CTL1_CLEN(1) /*!< clock pulse of the last data bit (MSB) is output to the CK pin */ + +/* USART clock phase */ +#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ +#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ + +/* USART clock polarity */ +#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) +#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ +#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ + +/* USART stop bits definitions */ +#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ +#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ +#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ +#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ + +/* USART data is transmitted/received with the LSB/MSB first */ +#define CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19)) +#define USART_MSBF_LSB CTL1_MSBF(0) /*!< LSB first */ +#define USART_MSBF_MSB CTL1_MSBF(1) /*!< MSB first */ + +/* enable USART IrDA low-power */ +#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ +#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ + +/* configure USART DMA */ +#define CTL2_RECEIVE_DMAEN(regval) (BIT(6) & ((uint32_t)(regval) << 6)) +#define CTL2_TRANSMIT_DMAEN(regval) (BIT(7) & ((uint32_t)(regval) << 7)) +#define USART_RECEIVE_DMA_ENABLE CTL2_RECEIVE_DMAEN(1) /*!< enable DMA request for reception */ +#define USART_RECEIVE_DMA_DISABLE CTL2_RECEIVE_DMAEN(0) /*!< disable DMA request for reception */ +#define USART_TRANSMIT_DMA_ENABLE CTL2_TRANSMIT_DMAEN(1) /*!< enable DMA request for transmission */ +#define USART_TRANSMIT_DMA_DISABLE CTL2_TRANSMIT_DMAEN(0) /*!< disable DMA request for transmission */ + +/* configure USART RTS hardware flow control */ +#define CTL2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_RTS_ENABLE CTL2_RTSEN(1) /*!< enable RTS hardware flow control */ +#define USART_RTS_DISABLE CTL2_RTSEN(0) /*!< disable RTS hardware flow control */ + +/* configure USART CTS hardware flow control */ +#define CTL2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CTS_ENABLE CTL2_CTSEN(1) /*!< enable CTS hardware flow control */ +#define USART_CTS_DISABLE CTL2_CTSEN(0) /*!< disable CTS hardware flow control */ + +/* configure USART one sample bit method */ +#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_OSB_1BIT CTL2_OSB(1) /*!< 1 sample bit */ +#define USART_OSB_3BIT CTL2_OSB(0) /*!< 3 sample bits */ + +/* USART driver enable polarity mode */ +#define CTL2_DEP(regval) (BIT(15) & ((uint32_t)(regval) << 15)) +#define USART_DEP_HIGH CTL2_DEP(0) /*!< DE signal is active high */ +#define USART_DEP_LOW CTL2_DEP(1) /*!< DE signal is active low */ + +/* USART wakeup mode from deep-sleep mode */ +#define CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) +#define USART_WUM_ADDR CTL2_WUM(0) /*!< WUF active on address match */ +#define USART_WUM_STARTB CTL2_WUM(2) /*!< WUF active on start bit */ +#define USART_WUM_RBNE CTL2_WUM(3) /*!< WUF active on RBNE */ + +/* USART hardware flow control coherence mode */ +#define CHC_HCM(regval) (BIT(0) & ((uint32_t)(regval) << 0)) +#define USART_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */ +#define USART_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */ + +/* function declarations */ +/* initialization functions */ +/* reset USART */ +void usart_deinit(uint32_t usart_periph); +/* configure USART baud rate value */ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); +/* configure USART parity function */ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); +/* configure USART word length */ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); +/* configure USART stop bit length */ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); +/* enable USART */ +void usart_enable(uint32_t usart_periph); +/* disable USART */ +void usart_disable(uint32_t usart_periph); +/* configure USART transmitter */ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); +/* configure USART receiver */ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); + +/* USART normal mode communication */ +/* data is transmitted/received with the LSB/MSB first */ +void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); +/* configure USART inverted */ +void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); +/* enable the USART overrun function */ +void usart_overrun_enable(uint32_t usart_periph); +/* disable the USART overrun function */ +void usart_overrun_disable(uint32_t usart_periph); +/* configure the USART oversample mode */ +void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp); +/* configure sample bit method */ +void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb); +/* enable receiver timeout */ +void usart_receiver_timeout_enable(uint32_t usart_periph); +/* disable receiver timeout */ +void usart_receiver_timeout_disable(uint32_t usart_periph); +/* configure receiver timeout threshold */ +void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); +/* USART transmit data function */ +void usart_data_transmit(uint32_t usart_periph, uint16_t data); +/* USART receive data function */ +uint16_t usart_data_receive(uint32_t usart_periph); +/* enable USART command */ +void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype); + +/* multi-processor communication */ +/* configure address of the USART */ +void usart_address_config(uint32_t usart_periph, uint8_t addr); +/* configure address detection mode */ +void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod); +/* enable mute mode */ +void usart_mute_mode_enable(uint32_t usart_periph); +/* disable mute mode */ +void usart_mute_mode_disable(uint32_t usart_periph); +/* configure wakeup method in mute mode */ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); + +/* LIN mode communication */ +/* enable LIN mode */ +void usart_lin_mode_enable(uint32_t usart_periph); +/* disable LIN mode */ +void usart_lin_mode_disable(uint32_t usart_periph); +/* LIN break detection length */ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); + +/* half-duplex communication */ +/* enable half-duplex mode */ +void usart_halfduplex_enable(uint32_t usart_periph); +/* disable half-duplex mode */ +void usart_halfduplex_disable(uint32_t usart_periph); + +/* synchronous communication */ +/* enable clock */ +void usart_clock_enable(uint32_t usart_periph); +/* disable clock */ +void usart_clock_disable(uint32_t usart_periph); +/* configure USART synchronous mode parameters */ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); + +/* smartcard communication */ +/* configure guard time value in smartcard mode */ +void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); +/* enable smartcard mode */ +void usart_smartcard_mode_enable(uint32_t usart_periph); +/* disable smartcard mode */ +void usart_smartcard_mode_disable(uint32_t usart_periph); +/* enable NACK in smartcard mode */ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph); +/* disable NACK in smartcard mode */ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph); +/* enable early NACK in smartcard mode */ +void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph); +/* disable early NACK in smartcard mode */ +void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph); +/* configure smartcard auto-retry number */ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); +/* configure block length */ +void usart_block_length_config(uint32_t usart_periph, uint32_t bl); + +/* IrDA communication */ +/* enable IrDA mode */ +void usart_irda_mode_enable(uint32_t usart_periph); +/* disable IrDA mode */ +void usart_irda_mode_disable(uint32_t usart_periph); +/* configure the peripheral clock prescaler in USART IrDA low-power or smartcard mode */ +void usart_prescaler_config(uint32_t usart_periph, uint32_t psc); +/* configure IrDA low-power */ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); + +/* hardware flow communication */ +/* configure hardware flow control RTS */ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); +/* configure hardware flow control CTS */ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); + +/* coherence control */ +/* configure hardware flow control coherence mode */ +void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm); + +/* enable RS485 driver */ +void usart_rs485_driver_enable(uint32_t usart_periph); +/* disable RS485 driver */ +void usart_rs485_driver_disable(uint32_t usart_periph); +/* configure driver enable assertion time */ +void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime); +/* configure driver enable de-assertion time */ +void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime); +/* configure driver enable polarity mode */ +void usart_depolarity_config(uint32_t usart_periph, uint32_t dep); + +/* USART DMA */ +/* configure USART DMA reception */ +void usart_dma_receive_config(uint32_t usart_periph, uint8_t dmaconfig); +/* configure USART DMA transmission */ +void usart_dma_transmit_config(uint32_t usart_periph, uint8_t dmaconfig); +/* disable DMA on reception error */ +void usart_reception_error_dma_disable(uint32_t usart_periph); +/* enable DMA on reception error */ +void usart_reception_error_dma_enable(uint32_t usart_periph); + +/* enable USART to wakeup the MCU from deep-sleep mode */ +void usart_wakeup_enable(uint32_t usart_periph); +/* disable USART to wakeup the MCU from deep-sleep mode */ +void usart_wakeup_disable(uint32_t usart_periph); +/* configure the USART wakeup mode from deep-sleep mode */ +void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum); + +/* USART receive FIFO */ +/* enable receive FIFO */ +void usart_receive_fifo_enable(uint32_t usart_periph); +/* disable receive FIFO */ +void usart_receive_fifo_disable(uint32_t usart_periph); +/* read receive FIFO counter number */ +uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph); + +/* flag & interrupt functions */ +/* get USART status */ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); +/* clear USART status */ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); +/* enable USART interrupt */ +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); +/* disable USART interrupt */ +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); + +/* get USART interrupt and flag status */ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); +/* clear USART interrupt flag */ +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); + + +#endif /* GD32A50X_USART_H */ diff --git a/gd32a50x/standard_peripheral/include/gd32a50x_wwdgt.h b/gd32a50x/standard_peripheral/include/gd32a50x_wwdgt.h new file mode 100644 index 0000000..7224669 --- /dev/null +++ b/gd32a50x/standard_peripheral/include/gd32a50x_wwdgt.h @@ -0,0 +1,91 @@ +/*! + \file gd32fxxx_wwdgt.h + \brief definitions for the WWDGT + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32A50X_WWDGT_H +#define GD32A50X_WWDGT_H + +#include "gd32a50x.h" + +/* WWDGT definitions */ +#define WWDGT WWDGT_BASE /*!< WWDGT base address */ + +/* registers definitions */ +#define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */ +#define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */ +#define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */ + +/* bits definitions */ +/* WWDGT_CTL */ +#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ +#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ + +/* WWDGT_CFG */ +#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ +#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ +#define WWDGT_CFG_EWIE BIT(9) /*!< WWDGT early wakeup interrupt enable */ + +/* WWDGT_STAT */ +#define WWDGT_STAT_EWIF BIT(0) /*!< WWDGT early wakeup interrupt flag */ + +/* constants definitions */ +#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U)) /*!< write value to WWDGT_CFG_PSC bit field */ +#define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0)) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ +#define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1)) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ +#define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2)) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ +#define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3)) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ + +/* WWDGT_CTL register value */ +#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to WWDGT_CTL_CNT bit field */ +/* WWDGT_CFG register value */ +#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to WWDGT_CFG_WIN bit field */ + +/* function declarations */ +/* reset the WWDGT configuration */ +void wwdgt_deinit(void); +/* start the WWDGT counter */ +void wwdgt_enable(void); + +/* configure the WWDGT counter value */ +void wwdgt_counter_update(uint16_t counter_value); +/* configure counter value, window value, and prescaler divider value */ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); + +/* check early wakeup interrupt state of WWDGT */ +FlagStatus wwdgt_flag_get(void); +/* clear early wakeup interrupt state of WWDGT */ +void wwdgt_flag_clear(void); +/* enable early wakeup interrupt of WWDGT */ +void wwdgt_interrupt_enable(void); + +#endif /* GD32A50X_WWDGT_H */ diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_adc.c b/gd32a50x/standard_peripheral/source/gd32a50x_adc.c new file mode 100644 index 0000000..329a922 --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_adc.c @@ -0,0 +1,987 @@ +/*! + \file gd32a50x_adc.c + \brief ADC driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_adc.h" + +/*! + \brief reset ADC + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_deinit(uint32_t adc_periph) +{ + switch(adc_periph){ + case ADC0: + rcu_periph_reset_enable(RCU_ADC0RST); + rcu_periph_reset_disable(RCU_ADC0RST); + break; + case ADC1: + rcu_periph_reset_enable(RCU_ADC1RST); + rcu_periph_reset_disable(RCU_ADC1RST); + break; + default: + break; + } +} + +/*! + \brief enable ADC interface + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_enable(uint32_t adc_periph) +{ + if(0U == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; + } +} + +/*! + \brief disable ADC interface + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_disable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); +} + +/*! + \brief ADC calibration and reset calibration + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_calibration_enable(uint32_t adc_periph) +{ + /* reset the selected ADC calibration registers */ + ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; + /* check the RSTCLB bit state */ + while((ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ + } + /* enable ADC calibration process */ + ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; + /* check the CLB bit state */ + while((ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ + } +} + +/*! + \brief enable DMA request + \param[in] adc_periph: ADCx, x=0 + \param[out] none + \retval none +*/ +void adc_dma_mode_enable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); +} + +/*! + \brief disable DMA request + \param[in] adc_periph: ADCx,x=0 + \param[out] none + \retval none +*/ +void adc_dma_mode_disable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); +} + +/*! + \brief enable the temperature sensor channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_enable(void) +{ + /* enable the temperature sensor and vrefint channel */ + ADC_CTL1(ADC0) |= ADC_CTL1_TSVEN; +} + +/*! + \brief disable the temperature sensor channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_disable(void) +{ + /* disable the temperature sensor and vrefint channel */ + ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVEN; +} + +/*! + \brief enable vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_vrefint_enable(void) +{ + ADC_CTL1(ADC0) |= ADC_CTL1_INREFEN; +} + +/*! + \brief disable vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_vrefint_disable(void) +{ + ADC_CTL1(ADC0) &= ~ADC_CTL1_INREFEN; +} + +/*! + \brief configure ADC discontinuous mode + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular and inserted channel + \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 + for regular channel, the number has no effect for inserted channel + \param[out] none + \retval none +*/ +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length) +{ + ADC_CTL0(adc_periph) &= ~((uint32_t)( ADC_CTL0_DISRC | ADC_CTL0_DISIC )); + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* configure the number of conversions in discontinuous mode */ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); + ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - 1U)); + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; + break; + case ADC_INSERTED_CHANNEL: + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; + break; + case ADC_CHANNEL_DISCON_DISABLE: + default: + break; + } +} + +/*! + \brief configure the ADC0 sync mode + \param[in] mode: ADC0 mode + only one parameter can be selected which is shown as below: + \arg ADC_MODE_FREE: all the ADCs work independently + \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode + \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode + \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode + \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode + \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only + \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only + \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only + \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only + \arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only + \param[out] none + \retval none +*/ +void adc_mode_config(uint32_t mode) +{ + ADC_CTL0(ADC0) &= ~((uint32_t)ADC_CTL0_SYNCM); + ADC_CTL0(ADC0) |= mode; +} + +/*! + \brief configure ADC special function + \param[in] adc_periph: ADCx, x=0,1 + \param[in] function: the function to configure + one or more parameters can be selected which is shown as below: + \arg ADC_SCAN_MODE: scan mode select + \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically + \arg ADC_CONTINUOUS_MODE: continuous mode select + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue) +{ + if(newvalue){ + /* enable ADC scan mode */ + if(0U != (function & ADC_SCAN_MODE)){ + ADC_CTL0(adc_periph) |= (uint32_t)ADC_SCAN_MODE; + } + /* enable ADC inserted channel group convert automatically */ + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ + ADC_CTL0(adc_periph) |= (uint32_t)ADC_INSERTED_CHANNEL_AUTO; + } + /* enable ADC continuous mode */ + if(0U != (function & ADC_CONTINUOUS_MODE)){ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CONTINUOUS_MODE; + } + }else{ + /* disable ADC scan mode */ + if(0U != (function & ADC_SCAN_MODE)){ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_SCAN_MODE); + } + /* disable ADC inserted channel group convert automatically */ + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_INSERTED_CHANNEL_AUTO); + } + /* disable ADC continuous mode */ + if(0U != (function & ADC_CONTINUOUS_MODE)){ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CONTINUOUS_MODE); + } + } +} + +/*! + \brief configure ADC data alignment + \param[in] adc_periph: ADCx, x=0,1 + \param[in] data_alignment: data alignment select + only one parameter can be selected which is shown as below: + \arg ADC_DATAALIGN_RIGHT: right alignment + \arg ADC_DATAALIGN_LEFT: left alignment + \param[out] none + \retval none +*/ +void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment) +{ + if(ADC_DATAALIGN_RIGHT != data_alignment){ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_DAL; + }else{ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); + } +} + +/*! + \brief configure the length of regular channel group or inserted channel group + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] length: the length of the channel + regular channel 1-16 + inserted channel 1-4 + \param[out] none + \retval none +*/ +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) +{ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* configure the length of regular channel group */ + ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); + ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-1U)); + break; + case ADC_INSERTED_CHANNEL: + /* configure the length of inserted channel group */ + ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); + ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-1U)); + break; + default: + break; + } +} + +/*! + \brief configure ADC regular channel + \param[in] adc_periph: ADCx, x=0,1 + \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx + \param[in] sample_time: the sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_2POINT5: 2.5 cycles + \arg ADC_SAMPLETIME_14POINT5: 14.5 cycles + \arg ADC_SAMPLETIME_27POINT5: 27.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_83POINT5: 83.5 cycles + \arg ADC_SAMPLETIME_111POINT5: 111.5 cycles + \arg ADC_SAMPLETIME_143POINT5: 143.5 cycles + \arg ADC_SAMPLETIME_479POINT5: 479.5 cycles + \param[out] none + \retval none +*/ +void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) +{ + uint32_t rsq,sampt; + + /* configure ADC regular sequence */ + if(rank < 6U){ + rsq = ADC_RSQ2(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank))); + rsq |= ((uint32_t)adc_channel << (5U*rank)); + ADC_RSQ2(adc_periph) = rsq; + }else if(rank < 12U){ + rsq = ADC_RSQ1(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U)))); + rsq |= ((uint32_t)adc_channel << (5U*(rank-6U))); + ADC_RSQ1(adc_periph) = rsq; + }else if(rank < 16U){ + rsq = ADC_RSQ0(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U)))); + rsq |= ((uint32_t)adc_channel << (5U*(rank-12U))); + ADC_RSQ0(adc_periph) = rsq; + }else{ + } + + /* configure ADC sampling time */ + if(adc_channel < 10U){ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel))); + sampt |= (uint32_t)(sample_time << (3U*adc_channel)); + ADC_SAMPT1(adc_periph) = sampt; + }else if(adc_channel < 18U){ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U)))); + sampt |= (uint32_t)(sample_time << (3U*(adc_channel-10U))); + ADC_SAMPT0(adc_periph) = sampt; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure ADC inserted channel + \param[in] adc_periph: ADCx, x=0,1 + \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx + \param[in] sample_time: The sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_2POINT5: 2.5 cycles + \arg ADC_SAMPLETIME_14POINT5: 14.5 cycles + \arg ADC_SAMPLETIME_27POINT5: 27.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_83POINT5: 83.5 cycles + \arg ADC_SAMPLETIME_111POINT5: 111.5 cycles + \arg ADC_SAMPLETIME_143POINT5: 143.5 cycles + \arg ADC_SAMPLETIME_479POINT5: 479.5 cycles + \param[out] none + \retval none +*/ +void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) +{ + uint8_t inserted_length; + uint32_t isq, sampt; + + /* get inserted channel group length */ + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); + + /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */ + isq = ADC_ISQ(adc_periph); + isq &= ~((uint32_t)(ADC_ISQ_ISQN << (5U * ((3U + rank) - inserted_length)))); + isq |= ((uint32_t)adc_channel << (5U * ((3U + rank) - inserted_length))); + ADC_ISQ(adc_periph) = isq; + + /* ADC sampling time config */ + if(adc_channel < 10U){ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel))); + sampt |= (uint32_t) sample_time << (3U*adc_channel); + ADC_SAMPT1(adc_periph) = sampt; + }else if(adc_channel < 18U){ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U)))); + sampt |= ((uint32_t)sample_time << (3U*(adc_channel-10U))); + ADC_SAMPT0(adc_periph) = sampt; + }else{ + } +} + +/*! + \brief configure ADC inserted channel offset + \param[in] adc_periph: ADCx, x=0,1 + \param[in] inserted_channel : insert channel select + only one parameter can be selected which is shown as below: + \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel3 + \param[in] offset : the offset data + \param[out] none + \retval none +*/ +void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset) +{ + uint8_t inserted_length; + uint32_t num = 0U; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); + num = (uint32_t)3U - ((uint32_t)inserted_length - (uint32_t)inserted_channel); + + if(num <= 3U){ + /* calculate the offset of the register */ + num = num * 4U; + /* configure the offset of the selected channels */ + REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); + } +} + +/*! + \brief configure ADC external trigger + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue) +{ + if(newvalue){ + /* external trigger enable for regular channel */ + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ETERC; + } + /* external trigger enable for inserted channel */ + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ETEIC; + } + }else{ + /* external trigger disable for regular channel */ + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETERC); + } + /* external trigger disable for inserted channel */ + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETEIC); + } + } +} + +/*! + \brief configure ADC external trigger source + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] external_trigger_source: regular or inserted group trigger source + only one parameter can be selected which is shown as below: + for regular channel: + \arg ADC0_1_EXTTRIG_REGULAR_TRIGSEL: TRIGSEL select + \arg ADC0_1_EXTTRIG_REGULAR_NONE: software trigger + for inserted channel: + \arg ADC0_1_EXTTRIG_INSERTED_TRIGSEL: TRIGSEL select + \arg ADC0_1_EXTTRIG_INSERTED_NONE: software trigger + \param[out] none + \retval none +*/ +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) +{ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* external trigger select for regular channel */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + case ADC_INSERTED_CHANNEL: + /* external trigger select for inserted channel */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + default: + break; + } +} + +/*! + \brief enable ADC software trigger + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[out] none + \retval none +*/ +void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group) +{ + /* enable regular group channel software trigger */ + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWRCST; + } + /* enable inserted channel group software trigger */ + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWICST; + } +} + +/*! + \brief read ADC regular group data register + \param[in] adc_periph: ADCx, x=0,1 + \param[in] none + \param[out] none + \retval the conversion value: 0~0xFFFF +*/ +uint16_t adc_regular_data_read(uint32_t adc_periph) +{ + return (uint16_t)(ADC_RDATA(adc_periph)); +} + +/*! + \brief read ADC inserted group data register + \param[in] adc_periph: ADCx, x=0,1 + \param[in] inserted_channel: inserted channel select + only one parameter can be selected which is shown as below: + \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel3 + \param[out] none + \retval the conversion value: 0~0xFFFF +*/ +uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel) +{ + uint32_t idata; + /* read the data of the selected channel */ + switch(inserted_channel){ + case ADC_INSERTED_CHANNEL_0: + idata = ADC_IDATA0(adc_periph); + break; + case ADC_INSERTED_CHANNEL_1: + idata = ADC_IDATA1(adc_periph); + break; + case ADC_INSERTED_CHANNEL_2: + idata = ADC_IDATA2(adc_periph); + break; + case ADC_INSERTED_CHANNEL_3: + idata = ADC_IDATA3(adc_periph); + break; + default: + idata = 0U; + break; + } + return (uint16_t)idata; +} + +/*! + \brief read the last ADC0 and ADC1 conversion result data in sync mode + \param[in] none + \param[out] none + \retval the conversion value: 0~0xFFFFFFFF +*/ +uint32_t adc_sync_mode_convert_value_read(void) +{ + /* return conversion value */ + return ADC_RDATA(ADC0); +} + +/*! + \brief configure ADC analog watchdog 0 single channel + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0) + \param[out] none + \retval none +*/ +void adc_watchdog0_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWD0EN | ADC_CTL0_IWD0EN | ADC_CTL0_WD0SC | ADC_CTL0_WD0CHSEL); + + ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; + ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWD0EN | ADC_CTL0_IWD0EN | ADC_CTL0_WD0SC); +} + +/*! + \brief configure ADC analog watchdog 0 group channel + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_channel_group: the channel group use analog watchdog 0 + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \param[out] none + \retval none +*/ +void adc_watchdog0_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWD0EN | ADC_CTL0_IWD0EN | ADC_CTL0_WD0SC); + /* select the group */ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_RWD0EN; + break; + case ADC_INSERTED_CHANNEL: + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_IWD0EN; + break; + case ADC_REGULAR_INSERTED_CHANNEL: + ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWD0EN | ADC_CTL0_IWD0EN); + break; + default: + break; + } +} + +/*! + \brief disable ADC analog watchdog 0 + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_watchdog0_disable(uint32_t adc_periph) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWD0EN | ADC_CTL0_IWD0EN | ADC_CTL0_WD0SC | ADC_CTL0_WD0CHSEL); +} + +/*! + \brief configure ADC analog watchdog 1 channel + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_channel: the channel use analog watchdog 1 + one or more parameters can be selected which is shown as below: + \arg ADC_AWD1_SELECTION_CHANNEL_x, ADC_AWD1_SELECTION_CHANNEL_ALL: ADC channel analog watchdog 1/2 selection + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_watchdog1_channel_config(uint32_t adc_periph, uint32_t adc_channel, ControlStatus newvalue) +{ + if(ENABLE == newvalue){ + ADC_WD1SR(adc_periph) |= (uint32_t)adc_channel; + }else{ + ADC_WD1SR(adc_periph) &= ~((uint32_t)adc_channel); + } +} + +/*! + \brief disable ADC analog watchdog 1 + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_watchdog1_disable(uint32_t adc_periph) +{ + ADC_WD1SR(adc_periph) &= (uint32_t)~(ADC_WD1SR_AWD1CS); +} + +/*! + \brief configure ADC analog watchdog 0 threshold + \param[in] adc_periph: ADCx, x=0,1 + \param[in] low_threshold: analog watchdog 0 low threshold, 0..4095 + \param[in] high_threshold: analog watchdog 0 high threshold, 0..4095 + \param[out] none + \retval none +*/ +void adc_watchdog0_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold) +{ + ADC_WDLT0(adc_periph) = (uint32_t)WDLT0_WDLT0(low_threshold); + ADC_WDHT0(adc_periph) = (uint32_t)WDHT0_WDHT0(high_threshold); +} + +/*! + \brief configure ADC analog watchdog 1 threshold + \param[in] adc_periph: ADCx, x=0,1 + \param[in] low_threshold: analog watchdog 1 low threshold, 0..255 + \param[in] high_threshold: analog watchdog 1 high threshold, 0..255 + \param[out] none + \retval none +*/ +void adc_watchdog1_threshold_config(uint32_t adc_periph, uint8_t low_threshold, uint8_t high_threshold) +{ + ADC_WDT1(adc_periph) &= ~((uint32_t)(ADC_WDT1_WDLT1 | ADC_WDT1_WDHT1)); + /* configure ADC analog watchdog 1 threshold */ + ADC_WDT1(adc_periph) |= (uint32_t)WDT1_WDLT1(low_threshold); + ADC_WDT1(adc_periph) |= (uint32_t)WDT1_WDHT1(high_threshold); +} + +/*! + \brief configure ADC resolution + \param[in] adc_periph: ADCx, x=0,1 + \param[in] resolution: ADC resolution + only one parameter can be selected which is shown as below: + \arg ADC_RESOLUTION_12B: 12-bit ADC resolution + \arg ADC_RESOLUTION_10B: 10-bit ADC resolution + \arg ADC_RESOLUTION_8B: 8-bit ADC resolution + \arg ADC_RESOLUTION_6B: 6-bit ADC resolution + \param[out] none + \retval none +*/ +void adc_resolution_config(uint32_t adc_periph, uint32_t resolution) +{ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_DRES); + ADC_OVSAMPCTL(adc_periph) |= (uint32_t)resolution; +} + +/*! + \brief configure ADC oversample mode + \param[in] adc_periph: ADCx, x=0,1 + \param[in] mode: ADC oversampling mode + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger + \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger + \param[in] shift: ADC oversampling shift + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift + \param[in] ratio: ADC oversampling ratio + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 + \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 + \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 + \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 + \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 + \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 + \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 + \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 + \param[out] none + \retval none +*/ +void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio) +{ + /* configure ADC oversampling mode */ + if(ADC_OVERSAMPLING_ONE_CONVERT == mode){ + ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; + }else{ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); + } + /* configure the shift and ratio */ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); + ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); +} + +/*! + \brief enable ADC oversample mode + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_oversample_mode_enable(uint32_t adc_periph) +{ + ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_OVSEN; +} + +/*! + \brief disable ADC oversample mode + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_oversample_mode_disable(uint32_t adc_periph) +{ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); +} + +/*! + \brief get the ADC flag + \param[in] adc_periph: ADCx, x=0,1 + \param[in] flag: the ADC flag bits + only one parameter can be selected which is shown as below: + \arg ADC_FLAG_WDE0: analog watchdog 0 event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \arg ADC_FLAG_WDE1: analog watchdog 1 event flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t flag) +{ + FlagStatus reval = RESET; + if(ADC_STAT(adc_periph) & flag){ + reval = SET; + } + return reval; +} + +/*! + \brief clear the ADC flag + \param[in] adc_periph: ADCx, x=0,1 + \param[in] flag: the ADC flag + one or more parameters can be selected which is shown as below: + \arg ADC_FLAG_WDE0: analog watchdog 0 event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \arg ADC_FLAG_WDE1: analog watchdog 1 event flag + \param[out] none + \retval none +*/ +void adc_flag_clear(uint32_t adc_periph , uint32_t flag) +{ + ADC_STAT(adc_periph) = ~((uint32_t)flag); +} + +/*! + \brief enable ADC interrupt + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] interrupt: the ADC interrupt + one or more parameters can be selected which is shown as below: + \arg ADC_INT_WDE0: analog watchdog 0 interrupt flag + \arg ADC_INT_EOC: end of group conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag + \arg ADC_INT_WDE1: analog watchdog 1 interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_enable(uint32_t adc_periph , uint32_t interrupt) +{ + switch(interrupt){ + /* enable analog watchdog 0 interrupt */ + case ADC_INT_WDE0: + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_WDE0IE; + break; + /* enable end of group conversion interrupt */ + case ADC_INT_EOC: + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_EOCIE; + break; + /* enable end of inserted group conversion interrupt */ + case ADC_INT_EOIC: + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_EOICIE; + break; + /* enable analog watchdog 1 interrupt */ + case ADC_INT_WDE1: + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_WDE1IE; + break; + default: + break; + } +} + +/*! + \brief disable ADC interrupt + \param[in] adc_periph: ADCx, x=0,1 + \param[in] interrupt: the ADC interrupt flag + one or more parameters can be selected which is shown as below: + \arg ADC_INT_WDE0: analog watchdog 0 interrupt flag + \arg ADC_INT_EOC: end of group conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag + \arg ADC_INT_WDE1: analog watchdog 1 interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_disable(uint32_t adc_periph, uint32_t interrupt) +{ + switch(interrupt){ + /* disable analog watchdog 0 interrupt */ + case ADC_INT_WDE0: + ADC_CTL0(adc_periph) &= ~(uint32_t)ADC_CTL0_WDE0IE; + break; + /* disable end of group conversion interrupt */ + case ADC_INT_EOC: + ADC_CTL0(adc_periph) &= ~(uint32_t)ADC_CTL0_EOCIE; + break; + /* disable end of inserted group conversion interrupt */ + case ADC_INT_EOIC: + ADC_CTL0(adc_periph) &= ~(uint32_t)ADC_CTL0_EOICIE; + break; + /* disable analog watchdog 1 interrupt */ + case ADC_INT_WDE1: + ADC_CTL0(adc_periph) &= ~(uint32_t)ADC_CTL0_WDE1IE; + break; + default: + break; + } +} + +/*! + \brief get ADC interrupt flag + \param[in] adc_periph: ADCx, x=0,1 + \param[in] int_flag: the ADC interrupt + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE0: analog watchdog 0 interrupt flag + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \arg ADC_INT_FLAG_WDE1: analog watchdog 1 interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t int_flag) +{ + FlagStatus interrupt_flag = RESET; + uint32_t state; + /* check the interrupt bits */ + switch(int_flag){ + case ADC_INT_FLAG_WDE0: + state = ADC_STAT(adc_periph) & ADC_STAT_WDE0; + if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE0IE) && state){ + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOC: + state = ADC_STAT(adc_periph) & ADC_STAT_EOC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOIC: + state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_WDE1: + state = ADC_STAT(adc_periph) & ADC_STAT_WDE1; + if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE1IE) && state){ + interrupt_flag = SET; + } + break; + default: + break; + } + return interrupt_flag; +} + +/*! + \brief clear ADC interrupt flag + \param[in] adc_periph: ADCx, x=0,1 + \param[in] int_flag: the ADC interrupt flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE0: analog watchdog 0 interrupt flag + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag + \arg ADC_INT_FLAG_WDE1: analog watchdog 1 interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t int_flag) +{ + ADC_STAT(adc_periph) = ~((uint32_t)int_flag); +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_bkp.c b/gd32a50x/standard_peripheral/source/gd32a50x_bkp.c new file mode 100644 index 0000000..139c8ab --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_bkp.c @@ -0,0 +1,346 @@ +/*! + \file gd32a50x_bkp.c + \brief BKP driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_bkp.h" + +#define TAMPER_FLAG_SHIFT ((uint8_t)0x08U) + +/*! + \brief reset BKP registers + \param[in] none + \param[out] none + \retval none +*/ +void bkp_deinit(void) +{ + /* reset BKP domain register */ + rcu_bkp_reset_enable(); + rcu_bkp_reset_disable(); +} + +/*! + \brief write BKP data register + \param[in] register_number: refer to bkp_data_register_enum + only one parameter can be selected which is shown as below: + \arg BKP_DATA_x(x = 0..9): BKP data register number x + \param[in] data: the data to be write in BKP data register + \param[out] none + \retval none +*/ +void bkp_data_write(bkp_data_register_enum register_number, uint16_t data) +{ + if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ + BKP_DATA0_9(register_number-1U) = data; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief read BKP data register + \param[in] register_number: refer to bkp_data_register_enum + only one parameter can be selected which is shown as below: + \arg BKP_DATA_x(x = 0..9): BKP data register number x + \param[out] none + \retval data of BKP data register +*/ +uint16_t bkp_data_read(bkp_data_register_enum register_number) +{ + uint16_t data = 0U; + + /* get the data from the BKP data register */ + if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ + data = BKP_DATA0_9(register_number-1U); + }else{ + /* illegal parameters */ + } + return data; +} + +/*! + \brief enable RTC clock calibration output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_output_enable(void) +{ + BKP_OCTL |= (uint16_t)BKP_OCTL_COEN; +} + +/*! + \brief disable RTC clock calibration output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_output_disable(void) +{ + BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN; +} + +/*! + \brief enable RTC alarm or second signal output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_signal_output_enable(void) +{ + BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN; +} + +/*! + \brief disable RTC alarm or second signal output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_signal_output_disable(void) +{ + BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN; +} + +/*! + \brief select RTC output + \param[in] outputsel: RTC output selection + only one parameter can be selected which is shown as below: + \arg RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output + \arg RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output + \param[out] none + \retval none +*/ +void bkp_rtc_output_select(uint16_t outputsel) +{ + uint16_t ctl = 0U; + + ctl = BKP_OCTL; + ctl &= (uint16_t)~BKP_OCTL_ROSEL; + ctl |= outputsel; + BKP_OCTL = ctl; +} + +/*! + \brief select RTC clock output + \param[in] clocksel: RTC clock output selection + only one parameter can be selected which is shown as below: + \arg RTC_CLOCK_DIV_64: RTC clock div 64 + \arg RTC_CLOCK_DIV_1: RTC clock + \param[out] none + \retval none +*/ +void bkp_rtc_clock_output_select(uint16_t clocksel) +{ + uint16_t ctl = 0U; + + ctl = BKP_OCTL; + ctl &= (uint16_t)~BKP_OCTL_CCOSEL; + ctl |= clocksel; + BKP_OCTL = ctl; +} + +/*! + \brief RTC clock calibration direction + \param[in] direction: RTC clock calibration direction + only one parameter can be selected which is shown as below: + \arg RTC_CLOCK_SLOWED_DOWN: RTC clock slow down + \arg RTC_CLOCK_SPEED_UP: RTC clock speed up + \param[out] none + \retval none +*/ +void bkp_rtc_clock_calibration_direction(uint16_t direction) +{ + uint16_t ctl = 0U; + + ctl = BKP_OCTL; + ctl &= (uint16_t)~BKP_OCTL_CALDIR; + ctl |= direction; + BKP_OCTL = ctl; +} + +/*! + \brief set RTC clock calibration value + \param[in] value: RTC clock calibration value + only one parameter can be selected which is shown as below: + \arg 0x00 - 0x7F + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_value_set(uint8_t value) +{ + uint16_t ctl; + + ctl = BKP_OCTL; + ctl &= (uint16_t)~BKP_OCTL_RCCV; + ctl |= (uint16_t)OCTL_RCCV(value); + BKP_OCTL = ctl; +} + +/*! + \brief select OSC32IN pin + \param[in] inputpin: OSC32IN pin selection + only one parameter can be selected which is shown as below: + \arg OSC32IN_PC13: OSC32IN pin is PC13 + \arg OSC32IN_PC14: OSC32IN pin is PC14 + \param[out] none + \retval none +*/ +void bkp_osc32in_pin_select(uint16_t inputpin) +{ + uint16_t ctl = 0U; + + ctl = BKP_TPCTL; + ctl &= (uint16_t)~BKP_TPCTL_PCSEL; + ctl |= inputpin; + BKP_TPCTL = ctl; +} + +/*! + \brief enable tamper pin detection + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_detection_enable(void) +{ + BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN; +} + +/*! + \brief disable tamper pin detection + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_detection_disable(void) +{ + BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN; +} + +/*! + \brief set tamper pin active level + \param[in] level: tamper active level + only one parameter can be selected which is shown as below: + \arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high + \arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low + \param[out] none + \retval none +*/ +void bkp_tamper_active_level_set(uint16_t level) +{ + uint16_t ctl = 0U; + + ctl = BKP_TPCTL; + ctl &= (uint16_t)~BKP_TPCTL_TPAL; + ctl |= level; + BKP_TPCTL = ctl; +} + +/*! + \brief enable tamper pin interrupt + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_interrupt_enable(void) +{ + BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE; +} + +/*! + \brief disable tamper pin interrupt + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_interrupt_disable(void) +{ + BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE; +} + +/*! + \brief get bkp flag state + \param[in] flag: + \arg BKP_FLAG_TAMPER: tamper event flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus bkp_flag_get(uint16_t flag) +{ + if(0U != (BKP_TPCS & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear BKP flag state + \param[in] flag: + \arg BKP_FLAG_TAMPER: tamper event flag + \param[out] none + \retval none +*/ +void bkp_flag_clear(uint16_t flag) +{ + BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT); +} + +/*! + \brief get BKP interrupt flag state + \param[in] flag + \arg BKP_INT_FLAG_TAMPER: tamper interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus bkp_interrupt_flag_get(uint16_t flag) +{ + if(0U != (BKP_TPCS & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear BKP interrupt flag state + \param[in] flag: + \arg BKP_INT_FLAG_TAMPER: tamper interrupt flag + \param[out] none + \retval none +*/ +void bkp_interrupt_flag_clear(uint16_t flag) +{ + BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT); +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_can.c b/gd32a50x/standard_peripheral/source/gd32a50x_can.c new file mode 100644 index 0000000..ffd89bb --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_can.c @@ -0,0 +1,1844 @@ +/*! + \file gd32a50x_can.c + \brief CAN driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_can.h" + +/* DLC to data size in bytes definitions */ +static const uint8_t dlc_to_databytes[16] = {0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 12U, 16U, 20U, 24U, 32U, 48U, 64U}; + +/* computes the maximum payload size (in bytes), given a dlc */ +static uint32_t can_payload_size_compute(uint32_t dlc_value); +/* swap data to little endian */ +static void can_data_to_little_endian_swap(uint32_t dest[], uint32_t src[], uint32_t len); +/* swap data to big endian */ +static void can_data_to_big_endian_swap(uint32_t dest[], uint32_t src[], uint32_t len); +/* computes the dlc field value, given a payload size (in bytes) */ +static uint32_t can_dlc_value_compute(uint32_t payload_size); + +/*! + \brief deinitialize CAN + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_deinit(uint32_t can_periph) +{ + if(CAN0 == can_periph) { + /* reset CAN0 */ + rcu_periph_reset_enable(RCU_CAN0RST); + rcu_periph_reset_disable(RCU_CAN0RST); + } + if(CAN1 == can_periph) { + /* reset CAN1 */ + rcu_periph_reset_enable(RCU_CAN1RST); + rcu_periph_reset_disable(RCU_CAN1RST); + } +} + +/*! + \brief reset CAN internal state machines and CAN registers + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval ERROR or SUCCESS +*/ +ErrStatus can_software_reset(uint32_t can_periph) +{ + uint32_t timeout = CAN_DELAY; + + /* reset internal state machines and CAN registers */ + CAN_CTL0(can_periph) |= CAN_CTL0_SWRST; + /* wait reset complete */ + while((CAN_CTL0(can_periph) & CAN_CTL0_SWRST) && (timeout)) { + timeout--; + } + if(CAN_CTL0(can_periph) & CAN_CTL0_SWRST) { + return ERROR; + } + return SUCCESS; +} + +/*! + \brief CAN module initialization + \param[in] can_periph: CANx(x=0,1) + \param[in] can_parameter_init: can parameter struct + internal_counter_source: CAN_TIMER_SOURCE_BIT_CLOCK, CAN_TIMER_SOURCE_EXTERNAL_TIME_TICK + self_reception: ENABLE, DISABLE + mb_tx_order: CAN_TX_HIGH_PRIORITY_MB_FIRST, CAN_TX_LOW_NUM_MB_FIRST + mb_tx_abort_enable: ENABLE, DISABLE + local_priority_enable: ENABLE, DISABLE + mb_rx_ide_rtr_type: CAN_IDE_RTR_COMPARED, CAN_IDE_RTR_FILTERED + mb_remote_frame: CAN_GEN_REMOTE_RESPONSE_FRAME, CAN_STORE_REMOTE_REQUEST_FRAME + rx_private_filter_queue_enable: ENABLE, DISABLE + edge_filter_enable: ENABLE, DISABLE + protocol_exception_enable: ENABLE, DISABLE + rx_filter_order: CAN_RX_FILTER_ORDER_FIFO_FIRST, CAN_RX_FILTER_ORDER_MAILBOX_FIRST + memory_size: CAN_MEMSIZE_1_UNIT, CAN_MEMSIZE_2_UNIT, CAN_MEMSIZE_3_UNIT, CAN_MEMSIZE_4_UNIT, + CAN_MEMSIZE_5_UNIT, CAN_MEMSIZE_6_UNIT, CAN_MEMSIZE_7_UNIT, CAN_MEMSIZE_8_UNIT, + CAN_MEMSIZE_9_UNIT, CAN_MEMSIZE_10_UNIT, CAN_MEMSIZE_11_UNIT, CAN_MEMSIZE_12_UNIT, + CAN_MEMSIZE_13_UNIT, CAN_MEMSIZE_14_UNIT, CAN_MEMSIZE_15_UNIT, CAN_MEMSIZE_16_UNIT, + CAN_MEMSIZE_17_UNIT, CAN_MEMSIZE_18_UNIT, CAN_MEMSIZE_19_UNIT, CAN_MEMSIZE_20_UNIT, + CAN_MEMSIZE_21_UNIT, CAN_MEMSIZE_22_UNIT, CAN_MEMSIZE_23_UNIT, CAN_MEMSIZE_24_UNIT, + CAN_MEMSIZE_25_UNIT, CAN_MEMSIZE_26_UNIT, CAN_MEMSIZE_27_UNIT, CAN_MEMSIZE_28_UNIT, + CAN_MEMSIZE_29_UNIT, CAN_MEMSIZE_30_UNIT, CAN_MEMSIZE_31_UNIT, CAN_MEMSIZE_32_UNIT + mb_public_filter: 0x00000000 ~ 0xFFFFFFFF + prescaler: 1~1024 + resync_jump_width: 1~32 + prop_time_segment: 1~64 + time_segment_1: 1~32 + time_segment_2: 1~32 + \param[out] none + \retval ERROR or SUCCESS +*/ +ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init) +{ + uint32_t i; + uint32_t *canram = (uint32_t *)(CAN_RAM(can_periph)); + + /* clear CAN RAM */ + for(i = 0U; i < CAN_MAX_RAM_SIZE; i++) { + canram[i] = 0U; + } + /* reset CAN_RFIFOMPFx */ + for(i = 0U; i < CAN_MAX_MAILBOX_NUM; i++) { + CAN_RFIFOMPF(can_periph, i) = 0x00000000U; + } + + /* reset internal state machines and CAN registers */ + if(ERROR == can_software_reset(can_periph)) { + return ERROR; + } + + /* reset CAN_INTEN */ + CAN_INTEN(can_periph) = 0U; + /* reset CAN_STAT */ + CAN_STAT(can_periph) = (uint32_t)0xFFFFFFFFU; + CAN_TIMER(can_periph); + while(CAN_STAT(can_periph) & CAN_STAT_MS5_RFNE) { + CAN_STAT(can_periph) = CAN_STAT_MS5_RFNE; + } + + /* clear register bits */ + CAN_CTL0(can_periph) &= ~(CAN_CTL0_RFEN | CAN_CTL0_FDEN | CAN_CTL0_SRDIS | CAN_CTL0_LAPRIOEN | CAN_CTL0_MST | CAN_CTL0_RPFQEN | CAN_CTL0_MSZ); + CAN_CTL2(can_periph) &= ~(CAN_CTL2_ITSRC | CAN_CTL2_IDERTR_RMF | CAN_CTL2_RRFRMS | CAN_CTL2_RFO | CAN_CTL2_EFDIS | CAN_CTL2_PREEN); + CAN_CTL1(can_periph) &= ~CAN_CTL1_MTO; + CAN_BT(can_periph) &= ~(CAN_BT_BAUDPSC | CAN_BT_SJW | CAN_BT_PTS | CAN_BT_PBS1 | CAN_BT_PBS2); + + /* set self reception */ + if((uint8_t)DISABLE == can_parameter_init->self_reception) { + CAN_CTL0(can_periph) |= CAN_CTL0_SRDIS; + } + /* enable local arbitration priority */ + if((uint8_t)ENABLE == can_parameter_init->local_priority_enable) { + CAN_CTL0(can_periph) |= CAN_CTL0_LAPRIOEN; + } + /* set rx private filters and mailbox queue */ + if((uint8_t)ENABLE == can_parameter_init->rx_private_filter_queue_enable) { + CAN_CTL0(can_periph) |= CAN_CTL0_RPFQEN; + } + /* configure edge filtering */ + if((uint32_t)DISABLE == can_parameter_init->edge_filter_enable) { + CAN_CTL2(can_periph) |= CAN_CTL2_EFDIS; + } + /* configure protocol exception */ + if((uint32_t)ENABLE == can_parameter_init->protocol_exception_enable) { + CAN_CTL2(can_periph) |= CAN_CTL2_PREEN; + } + /* set mailbox stop transmission */ + if((uint8_t)ENABLE == can_parameter_init->mb_tx_abort_enable) { + CAN_CTL0(can_periph) |= CAN_CTL0_MST; + } + + /* set internal counter source */ + CAN_CTL2(can_periph) |= can_parameter_init->internal_counter_source; + /* set mailbox arbitration process order */ + CAN_CTL1(can_periph) |= can_parameter_init->mb_tx_order; + /* set IDE and RTR field filter type */ + CAN_CTL2(can_periph) |= can_parameter_init->mb_rx_ide_rtr_type; + /* configure remote request frame */ + CAN_CTL2(can_periph) |= can_parameter_init->mb_remote_frame; + /* set mailbox public filter */ + CAN_RMPUBF(can_periph) = can_parameter_init->mb_public_filter; + /* configure receive filter order */ + CAN_CTL2(can_periph) |= can_parameter_init->rx_filter_order; + /* set memory size */ + CAN_CTL0(can_periph) |= can_parameter_init->memory_size; + /* set time segment */ + CAN_BT(can_periph) |= (uint32_t)(BT_BAUDPSC(can_parameter_init->prescaler - 1U) | + BT_SJW((uint32_t)can_parameter_init->resync_jump_width - 1U) | + BT_PTS((uint32_t)can_parameter_init->prop_time_segment - 1U) | + BT_PBS1((uint32_t)can_parameter_init->time_segment_1 - 1U) | + BT_PBS2((uint32_t)can_parameter_init->time_segment_2 - 1U)); + + return SUCCESS; +} + +/*! + \brief initialize CAN parameter structure with a default value + \param[in] type: the type of CAN parameter struct + only one parameter can be selected which is shown as below: + \arg CAN_INIT_STRUCT: the CAN initial struct + \arg CAN_FD_INIT_STRUCT: the CAN FD initial struct + \arg CAN_FIFO_INIT_STRUCT: the CAN FIFO initial struct + \arg CAN_PN_MODE_INIT_STRUCT: the CAN Pretended Networking mode initial struct + \arg CAN_PN_MODE_FILTER_STRUCT: the CAN Pretended Networking mode filter struct + \arg CAN_MDSC_STRUCT: mailbox descriptor strcut + \arg CAN_FDES_STRUCT: Rx fifo descriptor strcut + \arg CAN_FIFO_ID_FILTER_STRUCT: Rx fifo id filter strcut + \arg CAN_CRC_STRUCT: CRC strcut + \arg CAN_ERRCNT_STRUCT: error counter strcut + \param[in] p_struct: the pointer of the specific struct + \param[out] none + \retval none +*/ +void can_struct_para_init(can_struct_type_enum type, void *p_struct) +{ + /* get type of the struct */ + switch(type) { + /* used for initialize can_parameter_struct */ + case CAN_INIT_STRUCT: + ((can_parameter_struct *)p_struct)->self_reception = (uint8_t)DISABLE; + ((can_parameter_struct *)p_struct)->internal_counter_source = CAN_TIMER_SOURCE_BIT_CLOCK; + ((can_parameter_struct *)p_struct)->mb_tx_order = CAN_TX_HIGH_PRIORITY_MB_FIRST; + ((can_parameter_struct *)p_struct)->mb_tx_abort_enable = (uint8_t)ENABLE; + ((can_parameter_struct *)p_struct)->local_priority_enable = (uint8_t)DISABLE; + ((can_parameter_struct *)p_struct)->mb_rx_ide_rtr_type = CAN_IDE_RTR_COMPARED; + ((can_parameter_struct *)p_struct)->mb_remote_frame = CAN_STORE_REMOTE_REQUEST_FRAME; + ((can_parameter_struct *)p_struct)->rx_private_filter_queue_enable = (uint8_t)DISABLE; + ((can_parameter_struct *)p_struct)->edge_filter_enable = (uint32_t)DISABLE; + ((can_parameter_struct *)p_struct)->protocol_exception_enable = (uint32_t)DISABLE; + ((can_parameter_struct *)p_struct)->rx_filter_order = CAN_RX_FILTER_ORDER_FIFO_FIRST; + ((can_parameter_struct *)p_struct)->memory_size = CAN_MEMSIZE_32_UNIT; + ((can_parameter_struct *)p_struct)->mb_public_filter = 0xFFFFFFFFU; + ((can_parameter_struct *)p_struct)->prescaler = 0x00000001U; + ((can_parameter_struct *)p_struct)->resync_jump_width = 0x01U; + ((can_parameter_struct *)p_struct)->prop_time_segment = 0x01U; + ((can_parameter_struct *)p_struct)->time_segment_1 = 0x01U; + ((can_parameter_struct *)p_struct)->time_segment_2 = 0x01U; + break; + /* used for initialize can_fd_parameter_struct */ + case CAN_FD_INIT_STRUCT: + ((can_fd_parameter_struct *)p_struct)->iso_can_fd_enable = (uint32_t)DISABLE; + ((can_fd_parameter_struct *)p_struct)->bitrate_switch_enable = (uint32_t)ENABLE; + ((can_fd_parameter_struct *)p_struct)->mailbox_data_size = CAN_MAILBOX_DATA_SIZE_8_BYTES; + ((can_fd_parameter_struct *)p_struct)->tdc_enable = (uint32_t)DISABLE; + ((can_fd_parameter_struct *)p_struct)->tdc_offset = 0x00U; + ((can_fd_parameter_struct *)p_struct)->prescaler = 0x00000001U; + ((can_fd_parameter_struct *)p_struct)->resync_jump_width = 0x01U; + ((can_fd_parameter_struct *)p_struct)->prop_time_segment = 0x00U; + ((can_fd_parameter_struct *)p_struct)->time_segment_1 = 0x01U; + ((can_fd_parameter_struct *)p_struct)->time_segment_2 = 0x01U; + break; + /* used for initialize can_fifo_parameter_struct */ + case CAN_FIFO_INIT_STRUCT: + ((can_fifo_parameter_struct *)p_struct)->dma_enable = (uint8_t)DISABLE; + ((can_fifo_parameter_struct *)p_struct)->filter_format_and_number = CAN_RXFIFO_FILTER_A_NUM_8; + ((can_fifo_parameter_struct *)p_struct)->fifo_public_filter = 0xFFFFFFFFU; + break; + /* used for initialize can_pn_mode_config_struct */ + case CAN_PN_MODE_INIT_STRUCT: + ((can_pn_mode_config_struct *)p_struct)->timeout_int = (uint32_t)DISABLE; + ((can_pn_mode_config_struct *)p_struct)->match_int = (uint32_t)DISABLE; + ((can_pn_mode_config_struct *)p_struct)->num_matches = 0x01U; + ((can_pn_mode_config_struct *)p_struct)->match_timeout = 0x0000U; + ((can_pn_mode_config_struct *)p_struct)->frame_filter = CAN_PN_FRAME_FILTERING_ID; + ((can_pn_mode_config_struct *)p_struct)->id_filter = CAN_PN_ID_FILTERING_EXACT; + ((can_pn_mode_config_struct *)p_struct)->data_filter = CAN_PN_DATA_FILTERING_EXACT; + break; + /* used for initialize can_pn_mode_filter_struct */ + case CAN_PN_MODE_FILTER_STRUCT: + ((can_pn_mode_filter_struct *)p_struct)->remote_frame = (uint32_t)RESET; + ((can_pn_mode_filter_struct *)p_struct)->extended_frame = (uint32_t)RESET; + ((can_pn_mode_filter_struct *)p_struct)->id = 0x00000000U; + ((can_pn_mode_filter_struct *)p_struct)->dlc_high_threshold = 0x00000000U; + ((can_pn_mode_filter_struct *)p_struct)->dlc_low_threshold = 0x00000000U; + ((can_pn_mode_filter_struct *)p_struct)->payload[0] = 0x00000000U; + ((can_pn_mode_filter_struct *)p_struct)->payload[1] = 0x00000000U; + break; + /* used for initialize can_mailbox_descriptor_struct */ + case CAN_MDSC_STRUCT: + ((can_mailbox_descriptor_struct *)p_struct)->timestamp = 0x00000000U; + ((can_mailbox_descriptor_struct *)p_struct)->dlc = 0x00000000U; + ((can_mailbox_descriptor_struct *)p_struct)->rtr = 0x00000000U; + ((can_mailbox_descriptor_struct *)p_struct)->ide = 0x00000000U; + ((can_mailbox_descriptor_struct *)p_struct)->srr = 0x00000000U; + ((can_mailbox_descriptor_struct *)p_struct)->reserve1 = 0x00000000U; + ((can_mailbox_descriptor_struct *)p_struct)->code = 0x00000000U; + ((can_mailbox_descriptor_struct *)p_struct)->reserve2 = 0x00000000U; + ((can_mailbox_descriptor_struct *)p_struct)->esi = 0x00000000U; + ((can_mailbox_descriptor_struct *)p_struct)->brs = 0x00000000U; + ((can_mailbox_descriptor_struct *)p_struct)->fdf = 0x00000000U; + ((can_mailbox_descriptor_struct *)p_struct)->id = 0x00000000U; + ((can_mailbox_descriptor_struct *)p_struct)->prio = 0x00000000U; + ((can_mailbox_descriptor_struct *)p_struct)->data = (void *)0x00000000U; + ((can_mailbox_descriptor_struct *)p_struct)->data_bytes = 0x00000000U; + ((can_mailbox_descriptor_struct *)p_struct)->padding = 0x0000U; + break; + /* used for initialize can_rx_fifo_struct */ + case CAN_FDES_STRUCT: + ((can_rx_fifo_struct *)p_struct)->timestamp = 0x00000000U; + ((can_rx_fifo_struct *)p_struct)->dlc = 0x00000000U; + ((can_rx_fifo_struct *)p_struct)->rtr = 0x00000000U; + ((can_rx_fifo_struct *)p_struct)->ide = 0x00000000U; + ((can_rx_fifo_struct *)p_struct)->srr = 0x00000000U; + ((can_rx_fifo_struct *)p_struct)->idhit = 0x00000000U; + ((can_rx_fifo_struct *)p_struct)->id = 0x00000000U; + ((can_rx_fifo_struct *)p_struct)->data[0] = 0x00000000U; + ((can_rx_fifo_struct *)p_struct)->data[1] = 0x00000000U; + break; + /* used for initialize can_rx_fifo_id_filter_struct */ + case CAN_FIFO_ID_FILTER_STRUCT: + ((can_rx_fifo_id_filter_struct *)p_struct)->remote_frame = 0x00000000U; + ((can_rx_fifo_id_filter_struct *)p_struct)->extended_frame = 0x00000000U; + ((can_rx_fifo_id_filter_struct *)p_struct)->id = 0x00000000U; + break; + /* used for initialize can_crc_struct */ + case CAN_CRC_STRUCT: + ((can_crc_struct *)p_struct)->classical_frm_mb_number = 0x00000000U; + ((can_crc_struct *)p_struct)->classical_frm_transmitted_crc = 0x00000000U; + ((can_crc_struct *)p_struct)->classical_fd_frm_mb_number = 0x00000000U; + ((can_crc_struct *)p_struct)->classical_fd_frm_transmitted_crc = 0x00000000U; + break; + /* used for initialize can_crc_struct */ + case CAN_ERRCNT_STRUCT: + ((can_error_counter_struct *)p_struct)->fd_data_phase_rx_errcnt = 0x00U; + ((can_error_counter_struct *)p_struct)->fd_data_phase_tx_errcnt = 0x00U; + ((can_error_counter_struct *)p_struct)->rx_errcnt = 0x00U; + ((can_error_counter_struct *)p_struct)->tx_errcnt = 0x00U; + break; + default: + break; + } +} + +/*! + \brief configure receive fifo/mailbox private filter + \param[in] can_periph: CANx(x=0,1) + \param[in] index: mailbox index + \param[in] filter_data: filter data to configure + \param[out] none + \retval none +*/ +void can_private_filter_config(uint32_t can_periph, uint32_t index, uint32_t filter_data) +{ + CAN_RFIFOMPF(can_periph, index) = filter_data; +} + +/*! + \brief enter the corresponding mode + \param[in] can_periph: CANx(x=0,1) + \param[in] mode: the mode to enter + only one parameter can be selected which is shown as below: + \arg GD32_CAN_NORMAL_MODE: normal mode + \arg GD32_CAN_MONITOR_MODE: monitor mode + \arg GD32_CAN_LOOPBACK_SILENT_MODE: loopback mode + \arg GD32_CAN_INACTIVE_MODE: inactive mode + \arg GD32_CAN_DISABLE_MODE: disable mode + \arg GD32_CAN_PN_MODE: Pretended Networking mode + \param[out] none + \retval ERROR or SUCCESS +*/ +ErrStatus can_operation_mode_enter(uint32_t can_periph, can_operation_modes_enum mode) +{ + uint32_t timeout; + ErrStatus ret = SUCCESS; + + /* enter INACTIVE mode */ + /* exit can_disable mode */ + CAN_CTL0(can_periph) &= ~CAN_CTL0_CANDIS; + /* enter inactive mode */ + CAN_CTL0(can_periph) |= CAN_CTL0_HALT | CAN_CTL0_INAMOD; + /* exit Pretended Networking mode */ + CAN_CTL0(can_periph) &= ~(CAN_CTL0_PNEN | CAN_CTL0_PNMOD); + timeout = CAN_DELAY; + /* wait for inactive mode state */ + while(((CAN_CTL0_NRDY | CAN_CTL0_INAS) != (CAN_CTL0(can_periph) & (CAN_CTL0_NRDY | CAN_CTL0_INAS))) && (timeout)) { + timeout--; + } + if((CAN_CTL0_NRDY | CAN_CTL0_INAS) != (CAN_CTL0(can_periph) & (CAN_CTL0_NRDY | CAN_CTL0_INAS))) { + return ERROR; + } + + /* configure the modes */ + switch(mode) { + case GD32_CAN_NORMAL_MODE: + CAN_CTL1(can_periph) &= ~(CAN_CTL1_LSCMOD | CAN_CTL1_MMOD); + break; + case GD32_CAN_MONITOR_MODE: + CAN_CTL1(can_periph) &= ~CAN_CTL1_LSCMOD; + CAN_CTL1(can_periph) |= CAN_CTL1_MMOD; + break; + case GD32_CAN_LOOPBACK_SILENT_MODE: + CAN_CTL1(can_periph) &= ~CAN_CTL1_MMOD; + CAN_CTL0(can_periph) &= ~CAN_CTL0_SRDIS; + CAN_FDCTL(can_periph) &= ~CAN_FDCTL_TDCEN; + CAN_CTL1(can_periph) |= CAN_CTL1_LSCMOD; + break; + case GD32_CAN_INACTIVE_MODE: + break; + case GD32_CAN_DISABLE_MODE: + CAN_CTL0(can_periph) |= CAN_CTL0_CANDIS; + break; + case GD32_CAN_PN_MODE: + CAN_CTL0(can_periph) |= (CAN_CTL0_PNEN | CAN_CTL0_PNMOD); + break; + default: + break; + } + + /* exit INACTIVE mode */ + if(GD32_CAN_INACTIVE_MODE != mode) { + /* exit inactive mode */ + CAN_CTL0(can_periph) &= ~(CAN_CTL0_HALT | CAN_CTL0_INAMOD); + timeout = CAN_DELAY; + while((CAN_CTL0(can_periph) & CAN_CTL0_INAS) && (timeout)) { + timeout--; + } + if(CAN_CTL0(can_periph) & CAN_CTL0_INAS) { + return ERROR; + } + } + + if(GD32_CAN_PN_MODE == mode) { + timeout = CAN_DELAY; + while((0U == (CAN_CTL0(can_periph) & CAN_CTL0_PNS)) && (timeout)) { + timeout--; + } + if(0U == (CAN_CTL0(can_periph) & CAN_CTL0_PNS)) { + return ERROR; + } + } + return ret; +} + +/*! + \brief get operation mode + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval can_operation_modes_enum +*/ +can_operation_modes_enum can_operation_mode_get(uint32_t can_periph) +{ + uint32_t reg; + can_operation_modes_enum state = GD32_CAN_NORMAL_MODE; + + reg = CAN_CTL0(can_periph); + reg &= (CAN_CTL0_NRDY | CAN_CTL0_INAS | CAN_CTL0_PNS | CAN_CTL0_LPS); + + if((CAN_CTL0_NRDY | CAN_CTL0_LPS) == reg) { + state = GD32_CAN_DISABLE_MODE; + } else if((CAN_CTL0_NRDY | CAN_CTL0_INAS) == reg) { + state = GD32_CAN_INACTIVE_MODE; + } else if(0U == reg) { + if(CAN_CTL1(can_periph)&CAN_CTL1_MMOD) { + state = GD32_CAN_MONITOR_MODE; + } else if(CAN_CTL1(can_periph)&CAN_CTL1_LSCMOD) { + state = GD32_CAN_LOOPBACK_SILENT_MODE; + } else { + state = GD32_CAN_NORMAL_MODE; + } + } else if(CAN_CTL0_PNS == reg) { + state = GD32_CAN_PN_MODE; + } else { + /* should not get here */ + } + + return state; +} + +/*! + \brief exit inactive mode + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval ERROR or SUCCESS +*/ +ErrStatus can_inactive_mode_exit(uint32_t can_periph) +{ + uint32_t timeout; + + /* exit inactive mode */ + CAN_CTL0(can_periph) &= ~CAN_CTL0_HALT; + timeout = CAN_DELAY; + while((CAN_CTL0(can_periph) & CAN_CTL0_INAS) && (timeout)) { + timeout--; + } + if(CAN_CTL0(can_periph) & CAN_CTL0_INAS) { + return ERROR; + } else { + return SUCCESS; + } +} + +/*! + \brief exit Pretended Networking mode + \param[in] can_periph: CANx(x=0,1) + \param[in] none + \param[out] none + \retval ERROR or SUCCESS +*/ +ErrStatus can_pn_mode_exit(uint32_t can_periph) +{ + uint32_t timeout; + + CAN_CTL0(can_periph) &= ~(CAN_CTL0_PNEN | CAN_CTL0_PNMOD); + timeout = CAN_DELAY; + while((CAN_CTL0(can_periph) & CAN_CTL0_PNS) && (timeout)) { + timeout--; + } + if(CAN_CTL0(can_periph) & CAN_CTL0_PNS) { + return ERROR; + } else { + return SUCCESS; + } +} + +/*! + \brief can FD initialize + \param[in] can_periph: CANx(x=0,1) + \param[in] can_fd_para_init: can fd parameter struct + iso_can_fd_enable: ENABLE, DISABLE + bitrate_switch_enable: ENABLE, DISABLE + mailbox_data_size: CAN_MAILBOX_DATA_SIZE_8_BYTES, CAN_MAILBOX_DATA_SIZE_16_BYTES, + CAN_MAILBOX_DATA_SIZE_32_BYTES, CAN_MAILBOX_DATA_SIZE_64_BYTES + tdc_enable: ENABLE, DISABLE + tdc_offset: 0 ~ 31 + prescaler: 1~1024 + resync_jump_width: 1~8 + prop_time_segment: 0~31 + time_segment_1: 1~8 + time_segment_2: 2~8 + \param[out] none + \retval none +*/ +void can_fd_config(uint32_t can_periph, can_fd_parameter_struct *can_fd_para_init) +{ + /* clear register bits, then enable FD mode */ + CAN_CTL0(can_periph) &= ~CAN_CTL0_RFEN; + CAN_CTL1(can_periph) &= ~CAN_CTL1_BSPMOD; + CAN_CTL2(can_periph) &= ~CAN_CTL2_ISO; + CAN_FDCTL(can_periph) &= ~(CAN_FDCTL_BRSEN | CAN_FDCTL_MDSZ | CAN_FDCTL_TDCEN | CAN_FDCTL_TDCO); + CAN_FDBT(can_periph) &= ~(CAN_FDBT_DBAUDPSC | CAN_FDBT_DSJW | CAN_FDBT_DPTS | CAN_FDBT_DPBS1 | CAN_FDBT_DPBS2); + CAN_CTL0(can_periph) |= CAN_CTL0_FDEN; + + /* support ISO or non-ISO mode */ + if((uint32_t)ENABLE == can_fd_para_init->iso_can_fd_enable) { + CAN_CTL2(can_periph) |= CAN_CTL2_ISO; + } + /* set TDC parameter */ + if((uint32_t)ENABLE == can_fd_para_init->tdc_enable) { + CAN_FDCTL(can_periph) |= CAN_FDCTL_TDCEN; + } + /* set data bit rate */ + if((uint32_t)ENABLE == can_fd_para_init->bitrate_switch_enable) { + CAN_FDCTL(can_periph) |= CAN_FDCTL_BRSEN; + } + + /* set mailbox data size */ + CAN_FDCTL(can_periph) |= can_fd_para_init->mailbox_data_size; + /* configure FD bit timing */ + CAN_FDBT(can_periph) |= (uint32_t)(FDBT_DBAUDPSC(can_fd_para_init->prescaler - 1U) | + FDBT_DSJW((uint32_t)can_fd_para_init->resync_jump_width - 1U) | + FDBT_DPTS(can_fd_para_init->prop_time_segment) | + FDBT_DPBS1((uint32_t)can_fd_para_init->time_segment_1 - 1U) | + FDBT_DPBS2((uint32_t)can_fd_para_init->time_segment_2 - 1U)); + /* configure transmitter delay compensation offset */ + CAN_FDCTL(can_periph) |= FDCTL_TDCO(can_fd_para_init->tdc_offset); +} + +/*! + \brief enable bit rate switching + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_bitrate_switch_enable(uint32_t can_periph) +{ + CAN_FDCTL(can_periph) |= CAN_FDCTL_BRSEN; +} + +/*! + \brief disable bit rate switching + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_bitrate_switch_disable(uint32_t can_periph) +{ + CAN_FDCTL(can_periph) &= ~CAN_FDCTL_BRSEN; +} + +/*! + \brief get transmitter delay compensation value + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval 0 - 0x3F +*/ +uint32_t can_tdc_get(uint32_t can_periph) +{ + uint32_t reg = 0U; + + reg = CAN_FDCTL(can_periph); + + return GET_FDCTL_TDCV(reg); +} + +/*! + \brief enable transmitter delay compensation + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_tdc_enable(uint32_t can_periph) +{ + CAN_FDCTL(can_periph) |= CAN_FDCTL_TDCEN; +} + +/*! + \brief disable transmitter delay compensation + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_tdc_disable(uint32_t can_periph) +{ + CAN_FDCTL(can_periph) &= ~CAN_FDCTL_TDCEN; +} + +/*! + \brief configure rx FIFO + \param[in] can_periph: CANx(x=0,1) + \param[in] can_fifo_para_init: fifo parameter struct + dma_enable: ENABLE, DISABLE + filter_format_and_number: CAN_RXFIFO_FILTER_A_NUM_8, CAN_RXFIFO_FILTER_A_NUM_16, CAN_RXFIFO_FILTER_A_NUM_24, CAN_RXFIFO_FILTER_A_NUM_32, + CAN_RXFIFO_FILTER_A_NUM_40, CAN_RXFIFO_FILTER_A_NUM_48, CAN_RXFIFO_FILTER_A_NUM_56, CAN_RXFIFO_FILTER_A_NUM_64, + CAN_RXFIFO_FILTER_A_NUM_72, CAN_RXFIFO_FILTER_A_NUM_80, CAN_RXFIFO_FILTER_A_NUM_88, CAN_RXFIFO_FILTER_A_NUM_96, CAN_RXFIFO_FILTER_A_NUM_104, + CAN_RXFIFO_FILTER_B_NUM_16, CAN_RXFIFO_FILTER_B_NUM_32, CAN_RXFIFO_FILTER_B_NUM_48, CAN_RXFIFO_FILTER_B_NUM_64, + CAN_RXFIFO_FILTER_B_NUM_80, CAN_RXFIFO_FILTER_B_NUM_96, CAN_RXFIFO_FILTER_B_NUM_112, CAN_RXFIFO_FILTER_B_NUM_128, + CAN_RXFIFO_FILTER_B_NUM_144, CAN_RXFIFO_FILTER_B_NUM_160, CAN_RXFIFO_FILTER_B_NUM_176, CAN_RXFIFO_FILTER_B_NUM_192, CAN_RXFIFO_FILTER_B_NUM_208, + CAN_RXFIFO_FILTER_C_NUM_32, CAN_RXFIFO_FILTER_C_NUM_64, CAN_RXFIFO_FILTER_C_NUM_96, CAN_RXFIFO_FILTER_C_NUM_128, + CAN_RXFIFO_FILTER_C_NUM_160, CAN_RXFIFO_FILTER_C_NUM_192, CAN_RXFIFO_FILTER_C_NUM_224, CAN_RXFIFO_FILTER_C_NUM_256, + CAN_RXFIFO_FILTER_C_NUM_288, CAN_RXFIFO_FILTER_C_NUM_320, CAN_RXFIFO_FILTER_C_NUM_352, CAN_RXFIFO_FILTER_C_NUM_384, CAN_RXFIFO_FILTER_C_NUM_416, + CAN_RXFIFO_FILTER_D + fifo_public_filter: 0x00000000 ~ 0xFFFFFFFF + \param[out] none + \retval none +*/ +void can_rx_fifo_config(uint32_t can_periph, can_fifo_parameter_struct *can_fifo_para_init) +{ + uint32_t num; + + /* clear register bits, disable FD mode, then enable rx FIFO mode */ + CAN_CTL0(can_periph) &= ~(CAN_CTL0_FDEN | CAN_CTL0_DMAEN | CAN_CTL0_FS); + CAN_CTL2(can_periph) &= ~CAN_CTL2_RFFN; + CAN_CTL0(can_periph) |= CAN_CTL0_RFEN; + + /* clear FIFO status */ + CAN_STAT(can_periph) = (uint32_t)0xFFFFFFFFU; + while(CAN_STAT(can_periph) & CAN_STAT_MS5_RFNE) { + CAN_STAT(can_periph) = CAN_STAT_MS5_RFNE; + } + + /* set DMA mode */ + if((uint8_t)ENABLE == can_fifo_para_init->dma_enable) { + CAN_CTL0(can_periph) |= CAN_CTL0_DMAEN; + } + + /* configure filter format */ + CAN_CTL0(can_periph) |= (can_fifo_para_init->filter_format_and_number & CAN_CTL0_FS); + /* configure filter number */ + CAN_CTL2(can_periph) |= (can_fifo_para_init->filter_format_and_number & CAN_CTL2_RFFN); + /* configure fifo public fiter */ + CAN_RFIFOPUBF(can_periph) = can_fifo_para_init->fifo_public_filter; + /* configure fifo private fiter */ + if(!(CAN_CTL0(can_periph) & CAN_CTL0_RPFQEN)) { + for(num = 0U; num < CAN_MAX_MAILBOX_NUM; num++) { + CAN_RFIFOMPF(can_periph, num) = can_fifo_para_init->fifo_public_filter; + } + } +} + +/*! + \brief configure rx FIFO filter table + \param[in] can_periph: CANx(x=0,1) + \param[in] id_filter_table: id filter table struct + remote_frame: CAN_DATA_FRAME_ACCEPTED, CAN_REMOTE_FRAME_ACCEPTED + extended_frame: CAN_STANDARD_FRAME_ACCEPTED, CAN_EXTENDED_FRAME_ACCEPTED + id: 11 bits for standard frame, 29 bits for extended frame + \param[out] none + \retval none +*/ +void can_rx_fifo_filter_table_config(uint32_t can_periph, can_rx_fifo_id_filter_struct id_filter_table[]) +{ + /* set rx FIFO ID filter table elements */ + uint32_t i = 0U, j = 0U, num_of_filters = 0U; + uint32_t val = 0U; + uint32_t id_format = 0U; + uint32_t *filter_table = (uint32_t *)(uint32_t)(CAN_RAM(can_periph) + 0x00000060U); + + num_of_filters = (GET_CTL2_RFFN(CAN_CTL2(can_periph)) + 1U) * 8U; + id_format = CAN_CTL0(can_periph) & CAN_CTL0_FS; + + switch(id_format) { + case(CAN_FIFO_FILTER_FORMAT_A): + /* one full id (standard and extended) per id filter table element */ + for(i = 0U; i < num_of_filters; i++) { + val = 0U; + + if(CAN_REMOTE_FRAME_ACCEPTED == id_filter_table[i].remote_frame) { + val |= CAN_FDESX_RTR_A; + } + if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[i].extended_frame) { + val |= CAN_FDESX_IDE_A; + val |= (uint32_t)FIFO_FILTER_ID_EXD_A(id_filter_table[i].id); + } else { + val |= (uint32_t)FIFO_FILTER_ID_STD_A(id_filter_table[i].id); + } + filter_table[i] = val; + } + break; + case(CAN_FIFO_FILTER_FORMAT_B): + /* two full standard id or two partial 14-bit (standard and extended) id */ + j = 0U; + for(i = 0U; i < num_of_filters; i++) { + val = 0U; + + if(CAN_REMOTE_FRAME_ACCEPTED == id_filter_table[j].remote_frame) { + val |= CAN_FDESX_RTR_B0; + } + if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) { + val |= CAN_FDESX_IDE_B0; + val |= (uint32_t)FIFO_FILTER_ID_EXD_B0(id_filter_table[j].id); + } else { + val |= (uint32_t)FIFO_FILTER_ID_STD_B0(id_filter_table[j].id); + } + j++; + + if(CAN_REMOTE_FRAME_ACCEPTED == id_filter_table[j].remote_frame) { + val |= CAN_FDESX_RTR_B1; + } + if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) { + val |= CAN_FDESX_IDE_B1; + val |= (uint32_t)FIFO_FILTER_ID_EXD_B1(id_filter_table[j].id); + } else { + val |= (uint32_t)FIFO_FILTER_ID_STD_B1(id_filter_table[j].id); + } + j++; + + filter_table[i] = val; + } + break; + case(CAN_FIFO_FILTER_FORMAT_C): + /* four partial 8-bit standard id per id filter table element */ + j = 0U; + for(i = 0U; i < num_of_filters; i++) { + val = 0U; + if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) { + val |= (uint32_t)FIFO_FILTER_ID_EXD_C0(id_filter_table[j].id); + } else { + val |= (uint32_t)FIFO_FILTER_ID_STD_C0(id_filter_table[j].id); + } + j++; + if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) { + val |= (uint32_t)FIFO_FILTER_ID_EXD_C1(id_filter_table[j].id); + } else { + val |= (uint32_t)FIFO_FILTER_ID_STD_C1(id_filter_table[j].id); + } + j++; + if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) { + val |= (uint32_t)FIFO_FILTER_ID_EXD_C2(id_filter_table[j].id); + } else { + val |= (uint32_t)FIFO_FILTER_ID_STD_C2(id_filter_table[j].id); + } + j++; + if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) { + val |= (uint32_t)FIFO_FILTER_ID_EXD_C3(id_filter_table[j].id); + } else { + val |= (uint32_t)FIFO_FILTER_ID_STD_C3(id_filter_table[j].id); + } + j++; + + filter_table[i] = val; + } + break; + case(CAN_FIFO_FILTER_FORMAT_D): + /* all frames rejected */ + break; + default: + /* should not get here */ + break; + } +} + +/*! + \brief read rx FIFO data + \param[in] can_periph: CANx(x=0,1) + \param[out] rx_fifo: rx FIFO struct + \retval none +*/ +void can_rx_fifo_read(uint32_t can_periph, can_rx_fifo_struct *rx_fifo) +{ + uint32_t *rx_fifo_addr = (uint32_t *)rx_fifo; + uint32_t *can_mb = (uint32_t *)CAN_RAM(can_periph); + + /* read FIFO descriptor 0 */ + rx_fifo_addr[0] = can_mb[0]; + rx_fifo_addr[1] = can_mb[1]; + rx_fifo->data[0] = can_mb[2]; + rx_fifo->data[1] = can_mb[3]; + + /* clear FIFO status */ + CAN_STAT(can_periph) = CAN_STAT_MS5_RFNE; + + /* read FIFO id field */ + if(rx_fifo->ide) { + rx_fifo->id = GET_FDES1_ID_EXD(rx_fifo->id); + } else { + rx_fifo->id = GET_FDES1_ID_STD(rx_fifo->id); + } + + /* read FIFO data */ + can_data_to_little_endian_swap(rx_fifo->data, rx_fifo->data, rx_fifo->dlc); +} + +/*! + \brief get rx FIFO filter matching number + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval filter number +*/ +uint32_t can_rx_fifo_filter_matching_number_get(uint32_t can_periph) +{ + return GET_RFIFOIFMN_IDFMN(CAN_RFIFOIFMN(can_periph)); +} + +/*! + \brief clear rx FIFO + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_rx_fifo_clear(uint32_t can_periph) +{ + CAN_STAT(can_periph) = CAN_STAT_MS0_RFC; +} + +/*! + \brief get mailbox RAM address + \param[in] can_periph: CANx(x=0,1) + \param[in] index: mailbox index, 0-31 + \param[out] none + \retval pointer to the mailbox address +*/ +uint32_t *can_ram_address_get(uint32_t can_periph, uint32_t index) +{ + uint32_t payload_size; + uint32_t *address; + + /* if CAN FD mode is enabled */ + if(CAN_CTL0(can_periph) & CAN_CTL0_FDEN) { + payload_size = (uint32_t)1U << (GET_FDCTL_MDSZ(CAN_FDCTL(can_periph)) + 3U); + } else { + payload_size = 8U; + } + address = (uint32_t *)(uint32_t)(CAN_RAM(can_periph) + (payload_size + 8U) * index); + + return address; +} + +/*! + \brief configure mailbox + \param[in] can_periph: CANx(x=0,1) + \param[in] index: mailbox index + only one parameter can be selected which is shown as below: + \arg 0 - 31 + \param[in] mdpara: mailbox descriptor struct + rtr: 0, 1 + ide: 0, 1 + id: 0 - 0x1FFFFFFF + code: CAN_MB_RX_STATUS_INACTIVE, CAN_MB_RX_STATUS_FULL, CAN_MB_RX_STATUS_EMPTY, + CAN_MB_RX_STATUS_OVERRUN, CAN_MB_RX_STATUS_RANSWER, CAN_MB_RX_STATUS_BUSY, + CAN_MB_TX_STATUS_INACTIVE, CAN_MB_TX_STATUS_ABORT, CAN_MB_TX_STATUS_DATA + data_bytes: 0 - 64 + data: point to the data + esi: 0, 1 + fdf: 0, 1 + brs: 0, 1 + prio: 0 - 7 + \param[out] none + \retval none +*/ +void can_mailbox_config(uint32_t can_periph, uint32_t index, can_mailbox_descriptor_struct *mdpara) +{ + uint32_t dlc; + uint32_t mdes0 = 0U; + uint32_t length; + uint32_t *mdes; + + /* clear mailbox status */ + CAN_STAT(can_periph) = STAT_MS(index); + + /* get mailbox base address */ + mdes = can_ram_address_get(can_periph, index); + mdes[0] = 0U; + mdes[1] = 0U; + mdes[2] = 0U; + mdes[3] = 0U; + + /* set RTR bit */ + if(mdpara->rtr) { + mdes0 |= CAN_MDES0_RTR; + } + + /* set IDE bit and ID field */ + if(mdpara->ide) { + mdes0 |= CAN_MDES0_IDE; + mdes0 |= CAN_MDES0_SRR; + mdes[1] |= MDES1_ID_EXD(mdpara->id); + } else { + mdes[1] |= MDES1_ID_STD(mdpara->id); + } + + /* set CODE field */ + mdes0 |= MDES0_CODE(mdpara->code); + + if(mdpara->code != CAN_MB_RX_STATUS_EMPTY) { + /* copy user's buffer into the mailbox data area */ + if(mdpara->data_bytes) { + dlc = can_dlc_value_compute(mdpara->data_bytes); + mdes0 |= MDES0_DLC(dlc); + length = (uint32_t)1U << (GET_FDCTL_MDSZ(CAN_FDCTL(can_periph)) + 3U); + if(mdpara->data_bytes < length) { + length = mdpara->data_bytes; + } + can_data_to_big_endian_swap(&mdes[2], mdpara->data, length); + } + + /* prepare mailbox for transmission */ + if(CAN_MB_TX_STATUS_DATA == mdpara->code) { + /* set ESI bit */ + if(mdpara->esi) { + mdes0 |= CAN_MDES0_ESI; + } + /* set FDF and BRS bit */ + if(mdpara->fdf) { + mdes0 |= CAN_MDES0_FDF; + if(mdpara->brs) { + mdes0 |= CAN_MDES0_BRS; + } + mdes0 &= ~CAN_MDES0_RTR; + } + } + + /* set PRIO field */ + mdes[1] |= MDES1_PRIO(mdpara->prio); + } + + /* set mailbox descriptor 0 */ + mdes[0] = mdes0; +} + +/*! + \brief abort mailbox transmit + \param[in] can_periph: CANx(x=0,1) + \param[in] index: mailbox index + only one parameter can be selected which is shown as below: + \arg 0 - 31 + \param[out] none + \retval none +*/ +void can_mailbox_transmit_abort(uint32_t can_periph, uint32_t index) +{ + uint32_t mdes0; + uint32_t *mdes; + + /* abort transmit mailbox */ + mdes = can_ram_address_get(can_periph, index); + mdes0 = mdes[0]; + mdes0 &= ~CAN_MDES0_CODE; + mdes0 |= MDES0_CODE(CAN_MB_TX_STATUS_ABORT); + mdes[0] = mdes0; +} + +/*! + \brief inactive transmit mailbox + \param[in] can_periph: CANx(x=0,1) + \param[in] index: mailbox index + only one parameter can be selected which is shown as below: + \arg 0 - 31 + \param[out] none + \retval none +*/ +void can_mailbox_transmit_inactive(uint32_t can_periph, uint32_t index) +{ + uint32_t mdes0; + uint32_t *mdes; + + /* inactive transmit mailbox */ + mdes = can_ram_address_get(can_periph, index); + mdes0 = mdes[0]; + mdes0 &= ~CAN_MDES0_CODE; + mdes0 |= MDES0_CODE(CAN_MB_TX_STATUS_INACTIVE); + mdes[0] = mdes0; +} + +/*! + \brief read receive mailbox data + \param[in] can_periph: CANx(x=0,1) + \param[in] index: mailbox index + only one parameter can be selected which is shown as below: + \arg 0 - 31 + \param[out] mdpara: mailbox descriptor struct + \retval ERROR or SUCCESS +*/ +ErrStatus can_mailbox_receive_data_read(uint32_t can_periph, uint32_t index, can_mailbox_descriptor_struct *mdpara) +{ + uint32_t i; + uint32_t cnt; + uint32_t timeout; + uint32_t *mdes = can_ram_address_get(can_periph, index); + uint32_t *mdaddr = (uint32_t *)mdpara; + + /* wait mailbox data ready */ + timeout = CAN_DELAY; + while((mdes[0] & MDES0_CODE(CAN_MB_RX_STATUS_BUSY)) && (timeout)) { + timeout--; + } + if(mdes[0] & MDES0_CODE(CAN_MB_RX_STATUS_BUSY)) { + return ERROR; + } + + /* get mailbox descriptor 0 */ + mdaddr[0] = mdes[0]; + mdaddr[1] = mdes[1]; + mdpara->data_bytes = can_payload_size_compute(mdpara->dlc); + cnt = (mdpara->data_bytes + 3U) / 4U; + mdaddr = mdpara->data; + mdes += 2U; + for(i = 0U; i < cnt; i++) { + mdaddr[i] = mdes[i]; + } + + /* clear mailbox status */ + CAN_STAT(can_periph) = STAT_MS(index); + /* unlock mailbox */ + CAN_TIMER(can_periph); + + /* get mailbox ID */ + if(mdpara->ide) { + mdpara->id = GET_MDES1_ID_EXD(mdpara->id); + } else { + mdpara->id = GET_MDES1_ID_STD(mdpara->id); + } + + /* get mailbox data */ + if(mdpara->data_bytes) { + can_data_to_little_endian_swap(mdpara->data, mdpara->data, mdpara->data_bytes); + } + + return SUCCESS; +} + +/*! + \brief lock the receive mailbox + \param[in] can_periph: CANx(x=0,1) + \param[in] index: mailbox index + only one parameter can be selected which is shown as below: + \arg 0 - 31 + \param[out] none + \retval none +*/ +void can_mailbox_receive_lock(uint32_t can_periph, uint32_t index) +{ + uint32_t *mdes; + + mdes = can_ram_address_get(can_periph, index); + REG32((uint32_t)mdes); +} + +/*! + \brief unlock the receive mailbox + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_mailbox_receive_unlock(uint32_t can_periph) +{ + CAN_TIMER(can_periph); +} + +/*! + \brief inactive the receive mailbox + \param[in] can_periph: CANx(x=0,1) + \param[in] index: mailbox index + only one parameter can be selected which is shown as below: + \arg 0 - 31 + \param[out] none + \retval none +*/ +void can_mailbox_receive_inactive(uint32_t can_periph, uint32_t index) +{ + uint32_t mdes0; + uint32_t *mdes; + + /* inactive receive mailbox */ + mdes = can_ram_address_get(can_periph, index); + mdes0 = mdes[0]; + mdes0 &= ~CAN_MDES0_CODE; + mdes0 |= MDES0_CODE(CAN_MB_RX_STATUS_INACTIVE); + mdes[0] = mdes0; +} + +/*! + \brief get mailbox code value + \param[in] can_periph: CANx(x=0,1) + \param[in] index: mailbox index(0~31) + only one parameter can be selected which is shown as below: + \arg 0 - 31 + \param[out] none + \retval mailbox code +*/ +uint32_t can_mailbox_code_get(uint32_t can_periph, uint32_t index) +{ + uint32_t code; + uint32_t *mdes; + + mdes = can_ram_address_get(can_periph, index); + code = GET_MDES0_CODE(mdes[0]); + + return code; +} + +/*! + \brief configure error counter + \param[in] can_periph: CANx(x=0,1) + \param[in] errcnt_struct + fd_data_phase_rx_errcnt: 0-255 + fd_data_phase_tx_errcnt: 0-255 + rx_errcnt: 0-255 + tx_errcnt: 0-255 + \retval none +*/ +void can_error_counter_config(uint32_t can_periph, can_error_counter_struct *errcnt_struct) +{ + CAN_ERR0(can_periph) = ERR0_REFCNT(errcnt_struct->fd_data_phase_rx_errcnt) | ERR0_TEFCNT(errcnt_struct->fd_data_phase_tx_errcnt) | \ + ERR0_RECNT(errcnt_struct->rx_errcnt) | ERR0_TECNT(errcnt_struct->tx_errcnt); +} + +/*! + \brief get error counter + \param[in] can_periph: CANx(x=0,1) + \param[out] errcnt_struct + fd_data_phase_rx_errcnt: 0-255 + fd_data_phase_tx_errcnt: 0-255 + rx_errcnt: 0-255 + tx_errcnt: 0-255 + \retval none +*/ +void can_error_counter_get(uint32_t can_periph, can_error_counter_struct *errcnt_struct) +{ + uint32_t reg = 0U; + + reg = CAN_ERR0(can_periph); + errcnt_struct->fd_data_phase_rx_errcnt = (uint8_t)GET_ERR0_REFCNT(reg); + errcnt_struct->fd_data_phase_tx_errcnt = (uint8_t)GET_ERR0_TEFCNT(reg); + errcnt_struct->rx_errcnt = (uint8_t)GET_ERR0_RECNT(reg); + errcnt_struct->tx_errcnt = (uint8_t)GET_ERR0_TECNT(reg); +} + +/*! + \brief get error state indicator + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval CAN_ERROR_STATE_ACTIVE, CAN_ERROR_STATE_PASSIVE or CAN_ERROR_STATE_BUS_OFF +*/ +can_error_state_enum can_error_state_get(uint32_t can_periph) +{ + uint32_t reg; + + reg = GET_ERR1_ERRSI(CAN_ERR1(can_periph)); + if(reg >= (uint32_t)CAN_ERROR_STATE_BUS_OFF) { + reg = (uint32_t)CAN_ERROR_STATE_BUS_OFF; + } + + return (can_error_state_enum)reg; +} + +/*! + \brief get mailbox CRC value + \param[in] can_periph: CANx(x=0,1) + \param[out] crc_struct: + classical_frm_mb_number: 0 - 0x1F + classical_frm_transmitted_crc: 0 - 0x7FFF + classical_fd_frm_mb_number: 0 - 0x1F + classical_fd_frm_transmitted_crc: 0 - 0x1FFFFF + \retval none +*/ +void can_crc_get(uint32_t can_periph, can_crc_struct *crc_struct) +{ + uint32_t reg1 = 0U, reg2 = 0U; + + reg1 = CAN_CRCC(can_periph); + reg2 = CAN_CRCCFD(can_periph); + crc_struct->classical_frm_mb_number = GET_CRCC_ANTM(reg1); + crc_struct->classical_frm_transmitted_crc = GET_CRCC_CRCTC(reg1); + crc_struct->classical_fd_frm_mb_number = GET_CRCCFD_ANTM(reg2); + crc_struct->classical_fd_frm_transmitted_crc = GET_CRCCFD_CRCTCI(reg2); +} + +/*! + \brief configure Pretended Networking mode parameter + \param[in] can_periph: CANx(x=0,1) + \param[in] pnmod_config: Pretended Networking mode config struct + timeout_int: ENABLE, DISABLE + match_int: ENABLE, DISABLE + num_matches: 1 ~ 255 + match_timeout: 0 ~ 0xFFFF + frame_filter: CAN_PN_FRAME_FILTERING_ID, CAN_PN_FRAME_FILTERING_ID_DATA + CAN_PN_FRAME_FILTERING_ID_NMM, CAN_PN_FRAME_FILTERING_ID_DATA_NMM + id_filter: CAN_PN_ID_FILTERING_EXACT, CAN_PN_ID_FILTERING_GREATER + CAN_PN_ID_FILTERING_SMALLER, CAN_PN_ID_FILTERING_RANGE + data_filter: CAN_PN_DATA_FILTERING_EXACT, CAN_PN_DATA_FILTERING_GREATER + CAN_PN_DATA_FILTERING_SMALLER, CAN_PN_DATA_FILTERING_RANGE + \param[out] none + \retval none +*/ +void can_pn_mode_config(uint32_t can_periph, can_pn_mode_config_struct *pnmod_config) +{ + uint32_t tmp; + + /* configure specific Pretended Networking mode settings */ + tmp = CAN_PN_CTL0(can_periph); + tmp &= ~(CAN_PN_CTL0_FFT | CAN_PN_CTL0_IDFT | CAN_PN_CTL0_DATAFT | + CAN_PN_CTL0_NMM | CAN_PN_CTL0_WMIE | CAN_PN_CTL0_WTOIE); + tmp |= (uint32_t)PN_CTL0_WTOIE(pnmod_config->timeout_int) | PN_CTL0_WMIE(pnmod_config->match_int) | \ + PN_CTL0_NMM(pnmod_config->num_matches) | PN_CTL0_DATAFT(pnmod_config->data_filter) | \ + PN_CTL0_IDFT(pnmod_config->id_filter) | PN_CTL0_FFT(pnmod_config->frame_filter); + + CAN_PN_CTL0(can_periph) = tmp; + + /* set timeout value */ + CAN_PN_TO(can_periph) &= ~CAN_PN_TO_WTO; + CAN_PN_TO(can_periph) |= (uint32_t)PN_TO_WTO(pnmod_config->match_timeout); + + /* enable Pretended Networking mode */ + CAN_CTL0(can_periph) |= CAN_CTL0_PNMOD; +} + +/*! + \brief configure Pretended Networking mode filter + \param[in] can_periph: CANx(x=0,1) + \param[in] expect: Pretended Networking mode struct of expected wakeup frame + remote_frame: SET, RESET + extended_frame: SET, RESET + id: 0x00000000~0x1FFFFFFF + dlc_high_threshold: 0~8 + dlc_low_threshold: 0~8 + payload[0]: 0x00000000~0xFFFFFFFF + payload[1]: 0x00000000~0xFFFFFFFF + \param[in] filter: Pretended Networking mode struct of filter data + remote_frame: SET, RESET + extended_frame: SET, RESET + id: 0x00000000~0x1FFFFFFF + dlc_high_threshold: 0~8 + dlc_low_threshold: 0~8 + payload[0]: 0x00000000~0xFFFFFFFF + payload[1]: 0x00000000~0xFFFFFFFF + \param[out] none + \retval none +*/ +void can_pn_mode_filter_config(uint32_t can_periph, can_pn_mode_filter_struct *expect, can_pn_mode_filter_struct *filter) +{ + uint32_t reg, temp; + + /* set filter identifier 0 */ + reg = 0U; + if((uint32_t)SET == expect->extended_frame) { + reg |= CAN_PN_EID0_EIDE; + reg |= (uint32_t)PN_EID0_EIDF_ELT_EXD(expect->id); + } else { + reg |= (uint32_t)PN_EID0_EIDF_ELT_STD(expect->id); + } + if((uint32_t)SET == expect->remote_frame) { + reg |= CAN_PN_EID0_ERTR; + } + CAN_PN_EID0(can_periph) = reg; + + temp = CAN_PN_CTL0(can_periph); + /* ID field 1 is used when ID filtering type is EXACT or RANGE */ + if(((temp & CAN_PN_CTL0_IDFT) == CAN_PN_ID_FILTERING_EXACT) || + ((temp & CAN_PN_CTL0_IDFT) == CAN_PN_ID_FILTERING_RANGE)) { + /* set filter identifier 1 */ + reg = 0U; + if((uint32_t)SET == filter->extended_frame) { + reg |= CAN_PN_IFEID1_IDEFD; + reg |= (uint32_t)PN_IFEID1_IDEFD_EXD(filter->id); + } else { + reg |= (uint32_t)PN_IFEID1_IDEFD_STD(filter->id); + } + if((uint32_t)SET == filter->remote_frame) { + reg |= CAN_PN_IFEID1_RTRFD; + } + CAN_PN_IFEID1(can_periph) = reg; + } + + /* data field is used when frame filtering type is not MATCH or MATCH NMM */ + if(((temp & CAN_PN_CTL0_FFT) == CAN_PN_FRAME_FILTERING_ID_DATA) || + ((temp & CAN_PN_CTL0_FFT) == CAN_PN_FRAME_FILTERING_ID_DATA_NMM)) { + /* set filter data payload 0 */ + CAN_PN_EDLC(can_periph) = PN_EDLC_DLCEHT(expect->dlc_high_threshold) | PN_EDLC_DLCELT(expect->dlc_low_threshold); + CAN_PN_EDL0(can_periph) = ((expect->payload[0] << 24U) & CAN_PN_EDL0_DB0ELT) | + ((expect->payload[0] << 8U) & CAN_PN_EDL0_DB1ELT) | + ((expect->payload[0] >> 8U) & CAN_PN_EDL0_DB2ELT) | + ((expect->payload[0] >> 24U) & CAN_PN_EDL0_DB3ELT); + CAN_PN_EDL1(can_periph) = ((expect->payload[1] << 24U) & CAN_PN_EDL1_DB4ELT) | + ((expect->payload[1] << 8U) & CAN_PN_EDL1_DB5ELT) | + ((expect->payload[1] >> 8U) & CAN_PN_EDL1_DB6ELT) | + ((expect->payload[1] >> 24U) & CAN_PN_EDL1_DB7ELT); + + /* data field 1 is used when data filtering type is EXACT or RANGE */ + if(((temp & CAN_PN_CTL0_DATAFT) == CAN_PN_DATA_FILTERING_EXACT) + || ((temp & CAN_PN_CTL0_DATAFT) == CAN_PN_DATA_FILTERING_RANGE)) { + /* set filter data payload 1 */ + CAN_PN_DF0EDH0(can_periph) = ((filter->payload[0] << 24U) & CAN_PN_DF0EDH0_DB0FD_EHT) | + ((filter->payload[0] << 8U) & CAN_PN_DF0EDH0_DB1FD_EHT) | + ((filter->payload[0] >> 8U) & CAN_PN_DF0EDH0_DB2FD_EHT) | + ((filter->payload[0] >> 24U) & CAN_PN_DF0EDH0_DB3FD_EHT); + CAN_PN_DF1EDH1(can_periph) = ((filter->payload[1] << 24U) & CAN_PN_DF1EDH1_DB4FD_EHT) | + ((filter->payload[1] << 8U) & CAN_PN_DF1EDH1_DB5FD_EHT) | + ((filter->payload[1] >> 8U) & CAN_PN_DF1EDH1_DB6FD_EHT) | + ((filter->payload[1] >> 24U) & CAN_PN_DF1EDH1_DB7FD_EHT); + } + } +} + + +/*! + \brief get matching message counter of Pretended Networking mode + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval 0~255 or -1 +*/ +int32_t can_pn_mode_num_of_match_get(uint32_t can_periph) +{ + int32_t ret = 0; + uint32_t reg = 0U; + + reg = CAN_PN_STAT(can_periph); + if(0U != (reg & CAN_PN_STAT_MMCNTS)) { + ret = (int32_t)(uint32_t)GET_PN_STAT_MMCNT(reg); + } else { + ret = -1; + } + return ret; +} + +/*! + \brief get matching message + \param[in] can_periph: CANx(x=0,1) + \param[in] index: Pretended Networking mailbox index + only one parameter can be selected which is shown as below: + \arg 0 - 31 + \param[out] mdpara: wakeup message information + \retval none +*/ +void can_pn_mode_data_read(uint32_t can_periph, uint32_t index, can_mailbox_descriptor_struct *mdpara) +{ + uint32_t *mdaddr = (uint32_t *)mdpara; + uint32_t *pnram = (uint32_t *)(uint32_t)(CAN_PN_RAM(can_periph) + index * 16U); + + mdaddr[0] = pnram[0]; + mdaddr[1] = pnram[1]; + /* get mailbox ID */ + if(0U != mdpara->ide) { + mdpara->id = GET_MDES1_ID_EXD(mdpara->id); + } else { + mdpara->id = GET_MDES1_ID_STD(mdpara->id); + } + mdpara->data_bytes = mdpara->dlc; + if(mdpara->data_bytes) { + can_data_to_little_endian_swap(mdpara->data, &pnram[2], mdpara->data_bytes); + } +} + +/*! + \brief enable self reception + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_self_reception_enable(uint32_t can_periph) +{ + CAN_CTL0(can_periph) &= ~CAN_CTL0_SRDIS; +} + +/*! + \brief disable self reception + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_self_reception_disable(uint32_t can_periph) +{ + CAN_CTL0(can_periph) |= CAN_CTL0_SRDIS; +} + +/*! + \brief enable transmit abort + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_transmit_abort_enable(uint32_t can_periph) +{ + CAN_CTL0(can_periph) |= CAN_CTL0_MST; +} + +/*! + \brief disable transmit abort + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_transmit_abort_disable(uint32_t can_periph) +{ + CAN_CTL0(can_periph) &= ~CAN_CTL0_MST; +} + +/*! + \brief enable auto bus off recovery mode + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_auto_busoff_recovery_enable(uint32_t can_periph) +{ + CAN_CTL1(can_periph) &= ~CAN_CTL1_ABORDIS; +} + +/*! + \brief disable auto bus off recovery mode + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_auto_busoff_recovery_disable(uint32_t can_periph) +{ + CAN_CTL1(can_periph) |= CAN_CTL1_ABORDIS; +} + +/*! + \brief enable time sync mode + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_time_sync_enable(uint32_t can_periph) +{ + CAN_CTL1(can_periph) |= CAN_CTL1_TSYNC; +} + +/*! + \brief disable time sync mode + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_time_sync_disable(uint32_t can_periph) +{ + CAN_CTL1(can_periph) &= ~CAN_CTL1_TSYNC; +} + +/*! + \brief enable edge filter mode + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_edge_filter_mode_enable(uint32_t can_periph) +{ + CAN_CTL2(can_periph) &= ~CAN_CTL2_EFDIS; +} + +/*! + \brief disable edge filter mode + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_edge_filter_mode_disable(uint32_t can_periph) +{ + CAN_CTL2(can_periph) |= CAN_CTL2_EFDIS; +} + +/*! + \brief enable protocol exception detection mode + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_ped_mode_enable(uint32_t can_periph) +{ + CAN_CTL2(can_periph) |= CAN_CTL2_PREEN; +} + +/*! + \brief disable protocol exception detection mode + \param[in] can_periph: CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_ped_mode_disable(uint32_t can_periph) +{ + CAN_CTL2(can_periph) &= ~CAN_CTL2_PREEN; +} + +/*! + \brief configure arbitation delay bits + \param[in] can_periph: CANx(x=0,1) + \param[in] delay_bits: delay bits + only one parameter can be selected which is shown as below: + \arg 0 - 31 + \param[out] none + \retval none +*/ +void can_arbitation_delay_bits_config(uint32_t can_periph, uint32_t delay_bits) +{ + CAN_CTL2(can_periph) &= ~CAN_CTL2_ASD; + CAN_CTL2(can_periph) |= (uint32_t)CTL2_ASD(delay_bits); +} + +/*! + \brief configure bit sampling mode + \param[in] can_periph: CANx(x=0,1) + \param[in] sampling_mode: bit sampling mode + only one parameter can be selected which is shown as below: + \arg CAN_BSP_MODE_ONE_SAMPLE: one sample for received bit + \arg CAN_BSP_MODE_TRHEE_SAMPLES: three samples for received bit + \param[out] none + \retval none +*/ +void can_bsp_mode_config(uint32_t can_periph, uint32_t sampling_mode) +{ + if(CAN_BSP_MODE_ONE_SAMPLE == sampling_mode) { + CAN_CTL1(can_periph) &= ~CAN_CTL1_BSPMOD; + } else { + CAN_CTL1(can_periph) |= CAN_CTL1_BSPMOD; + } +} + +/*! + \brief get CAN flag + \param[in] can_periph: CANx(x=0,1) + \param[in] flag: CAN flags, refer to can_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_FLAG_CAN_PN: Pretended Networking state flag + \arg CAN_FLAG_SOFT_RST: software reset flag + \arg CAN_FLAG_ERR_SUMMARY: error summary flag + \arg CAN_FLAG_BUSOFF: bus off flag + \arg CAN_FLAG_RECEIVING: receiving state flag + \arg CAN_FLAG_TRANSMITTING: transmitting state flag + \arg CAN_FLAG_IDLE: IDLE state flag + \arg CAN_FLAG_RX_WARNING: receive warning flag + \arg CAN_FLAG_TX_WARNING: transmit warning flag + \arg CAN_FLAG_STUFF_ERR: stuff error flag + \arg CAN_FLAG_FORM_ERR: form error flag + \arg CAN_FLAG_CRC_ERR: CRC error flag + \arg CAN_FLAG_ACK_ERR: ACK error flag + \arg CAN_FLAG_BIT_DOMINANT_ERR: bit dominant error flag + \arg CAN_FLAG_BIT_RECESSIVE_ERR: bit recessive error flag + \arg CAN_FLAG_SYNC_ERR: synchronization flag + \arg CAN_FLAG_BUSOFF_RECOVERY: bus off recovery flag + \arg CAN_FLAG_ERR_SUMMARY_FD: fd error summary flag + \arg CAN_FLAG_ERR_OVERRUN: error overrun flag + \arg CAN_FLAG_STUFF_ERR_FD: stuff error in FD data phase flag + \arg CAN_FLAG_FORM_ERR_FD: form error in FD data phase flag + \arg CAN_FLAG_CRC_ERR_FD: CRC error in FD data phase flag + \arg CAN_FLAG_BIT_DOMINANT_ERR_FD: bit dominant error in FD data phase flag + \arg CAN_FLAG_BIT_RECESSIVE_ERR_FD: bit recessive error in FD data phase flag + \arg CAN_FLAG_MBx(x=0~31): mailbox x flag + \arg CAN_FLAG_FIFO_AVAILABLE: fifo available flag + \arg CAN_FLAG_FIFO_WARNING: fifo warning flag + \arg CAN_FLAG_FIFO_OVERFLOW: fifo overflow flag + \arg CAN_FLAG_WAKEUP_MATCH: Pretended Networking match flag + \arg CAN_FLAG_WAKEUP_TIMEOUT: Pretended Networking timeout wakeup flag + \arg CAN_FLAG_TDC_OUT_OF_RANGE: transmitter delay is out of compensation range flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) +{ + if(CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear CAN flag + \param[in] can_periph: CANx(x=0,1) + \param[in] flag: CAN flags, refer to can_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_FLAG_ERR_SUMMARY: error summary flag + \arg CAN_FLAG_BUSOFF: bus off flag + \arg CAN_FLAG_BUSOFF_RECOVERY: bus off recovery flag + \arg CAN_FLAG_ERR_SUMMARY_FD: fd error summary flag + \arg CAN_FLAG_ERR_OVERRUN: error overrun flag + \arg CAN_FLAG_MBx(x=0~31): mailbox x flag + \arg CAN_FLAG_FIFO_AVAILABLE: fifo available flag + \arg CAN_FLAG_FIFO_WARNING: fifo warning flag + \arg CAN_FLAG_FIFO_OVERFLOW: fifo overflow flag + \arg CAN_FLAG_WAKEUP_MATCH: Pretended Networking match flag + \arg CAN_FLAG_WAKEUP_TIMEOUT: Pretended Networking timeout wakeup flag + \arg CAN_FLAG_TDC_OUT_OF_RANGE: transmitter delay is out of compensation range flag + \param[out] none + \retval none +*/ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag) +{ + if(CAN_FLAG_TDC_OUT_OF_RANGE == flag) { + CAN_FDCTL(can_periph) |= CAN_FDCTL_TDCS; + } else { + CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag)); + } +} + +/*! + \brief enable CAN interrupt + \param[in] can_periph: CANx(x=0,1) + \param[in] interrupt: CAN interrupt, refer to can_interrupt_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_ERR_SUMMARY: error interrupt + \arg CAN_INT_RX_WARNING: receive warning interrupt + \arg CAN_INT_TX_WARNING: transmit warning interrupt + \arg CAN_INT_BUSOFF: bus off interrupt + \arg CAN_INT_BUSOFF_RECOVERY: bus off recovery interrupt + \arg CAN_INT_ERR_SUMMARY_FD: fd error interrupt + \arg CAN_INT_MBx(x=0~31): mailbox x interrupt + \arg CAN_INT_FIFO_AVAILABLE: fifo availabe interrupt + \arg CAN_INT_FIFO_WARNING: fifo warning interrupt + \arg CAN_INT_FIFO_OVERFLOW: fifo overflow interrupt + \arg CAN_INT_WAKEUP_MATCH: Pretended Networking match interrupt + \arg CAN_INT_WAKEUP_TIMEOUT: Pretended Networking timeout wakeup interrupt + \param[out] none + \retval none +*/ +void can_interrupt_enable(uint32_t can_periph, can_interrupt_enum interrupt) +{ + /* enable receive or transmit warning error interrupt should enable error warning in CTL0 register */ + if((CAN_INT_RX_WARNING == interrupt) + || (CAN_INT_TX_WARNING == interrupt)) { + CAN_CTL0(can_periph) |= CAN_CTL0_WERREN; + } + + CAN_REG_VAL(can_periph, interrupt) |= BIT(CAN_BIT_POS(interrupt)); +} + +/*! + \brief disable CAN interrupt + \param[in] can_periph: CANx(x=0,1) + \param[in] interrupt: CAN interrupt, refer to can_interrupt_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_ERR_SUMMARY: error interrupt + \arg CAN_INT_RX_WARNING: receive warning interrupt + \arg CAN_INT_TX_WARNING: transmit warning interrupt + \arg CAN_INT_BUSOFF: bus off interrupt + \arg CAN_INT_BUSOFF_RECOVERY: bus off recovery interrupt + \arg CAN_INT_ERR_SUMMARY_FD: fd error interrupt + \arg CAN_INT_MBx(x=0~31): mailbox x interrupt + \arg CAN_INT_FIFO_AVAILABLE: fifo available interrupt + \arg CAN_INT_FIFO_WARNING: fifo warning interrupt + \arg CAN_INT_FIFO_OVERFLOW: fifo overflow interrupt + \arg CAN_INT_WAKEUP_MATCH: Pretended Networking match interrupt + \arg CAN_INT_WAKEUP_TIMEOUT: Pretended Networking timeout wakeup interrupt + \param[out] none + \retval none +*/ +void can_interrupt_disable(uint32_t can_periph, can_interrupt_enum interrupt) +{ + CAN_REG_VAL(can_periph, interrupt) &= ~BIT(CAN_BIT_POS(interrupt)); +} + +/*! + \brief get CAN interrupt flag + \param[in] can_periph: CANx(x=0,1) + \param[in] int_flag: CAN interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_FLAG_ERR_SUMMARY: error summary interrupt flag + \arg CAN_INT_FLAG_BUSOFF: bus off interrupt flag + \arg CAN_INT_FLAG_RX_WARNING: receive warning interrupt flag + \arg CAN_INT_FLAG_TX_WARNING: transmit warning interrupt flag + \arg CAN_INT_FLAG_BUSOFF_RECOVERY: bus off recovery interrupt flag + \arg CAN_INT_FLAG_ERR_SUMMARY_FD: fd error summary interrupt flag + \arg CAN_INT_FLAG_MBx(x=0~31): mailbox x interrupt flag + \arg CAN_INT_FLAG_FIFO_AVAILABLE: fifo available interrupt flag + \arg CAN_INT_FLAG_FIFO_WARNING: fifo warning interrupt flag + \arg CAN_INT_FLAG_FIFO_OVERFLOW: fifo overflow interrupt flag + \arg CAN_INT_FLAG_WAKEUP_MATCH: Pretended Networking match interrupt flag + \arg CAN_INT_FLAG_WAKEUP_TIMEOUT: Pretended Networking timeout wakeup interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum int_flag) +{ + if(CAN_REG_VAL(can_periph, int_flag) & BIT(CAN_BIT_POS(int_flag))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear CAN interrupt flag + \param[in] can_periph: CANx(x=0,1) + \param[in] int_flag: CAN interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_FLAG_ERR_SUMMARY: error summary interrupt flag + \arg CAN_INT_FLAG_BUSOFF: bus off interrupt flag + \arg CAN_INT_FLAG_RX_WARNING: receive warning interrupt flag + \arg CAN_INT_FLAG_TX_WARNING: transmit warning interrupt flag + \arg CAN_INT_FLAG_BUSOFF_RECOVERY: bus off recovery interrupt flag + \arg CAN_INT_FLAG_ERR_SUMMARY_FD: fd error summary interrupt flag + \arg CAN_INT_FLAG_MBx(x=0~31): mailbox x interrupt flag + \arg CAN_INT_FLAG_FIFO_AVAILABLE: fifo availabe interrupt flag + \arg CAN_INT_FLAG_FIFO_WARNING: fifo warning interrupt flag + \arg CAN_INT_FLAG_FIFO_OVERFLOW: fifo overflow interrupt flag + \arg CAN_INT_FLAG_WAKEUP_MATCH: Pretended Networking match interrupt flag + \arg CAN_INT_FLAG_WAKEUP_TIMEOUT: Pretended Networking timeout wakeup interrupt flag + \param[out] none + \retval none +*/ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum int_flag) +{ + CAN_REG_VAL(can_periph, int_flag) = BIT(CAN_BIT_POS(int_flag)); +} + +/*! + \brief computes the maximum payload size (in bytes), given a dlc + \param[in] dlc_value: dlc value + \param[out] none + \retval payload_size +*/ +static uint32_t can_payload_size_compute(uint32_t dlc_value) +{ + uint8_t ret = 0U; + + if(dlc_value <= 15U) { + ret = dlc_to_databytes[dlc_value]; + } + + return (uint32_t)ret; +} + +/*! + \brief swap data to little endian + \param[in] src: data source address + \param[in] len: data length be byte + \param[out] dest: data destination address + \retval none +*/ +static void can_data_to_little_endian_swap(uint32_t dest[], uint32_t src[], uint32_t len) +{ + volatile uint32_t i = 0U; + uint32_t cnt; + uint32_t temp_src = 0U; + + /* get the word length of the data */ + cnt = (len + 3U) / 4U; + /* change each word from big endian to little endian */ + for(i = 0U; i < cnt; i++) { + temp_src = src[i]; + dest[i] = ((uint32_t)(temp_src >> 24U) & 0x000000FFU) | + ((uint32_t)(temp_src >> 8U) & 0x0000FF00U) | + ((uint32_t)(temp_src << 8U) & 0x00FF0000U) | + ((uint32_t)(temp_src << 24U) & 0xFF000000U); + } + + cnt = len % 4U; + if(cnt) { + dest[i - 1U] &= ((uint32_t)1U << (cnt * 8U)) - 1U; + } +} + +/*! + \brief swap data to big endian + \param[in] src: data source address + \param[in] len: data length be byte + \param[out] dest: data destination address + \retval none +*/ +static void can_data_to_big_endian_swap(uint32_t dest[], uint32_t src[], uint32_t len) +{ + volatile uint32_t i = 0U; + uint32_t cnt; + uint32_t temp_src = 0U; + + /* get the word length of the data */ + cnt = (len + 3U) / 4U; + for(i = 0U; i < cnt; i++) { + /* change each word from little endian to big endian */ + temp_src = src[i]; + dest[i] = ((uint32_t)(temp_src >> 24U) & 0x000000FFU) | + ((uint32_t)(temp_src >> 8U) & 0x0000FF00U) | + ((uint32_t)(temp_src << 8U) & 0x00FF0000U) | + ((uint32_t)(temp_src << 24U) & 0xFF000000U); + } + + cnt = len % 4U; + if(cnt) { + dest[i - 1U] &= ~(((uint32_t)1U << ((4U - cnt) * 8U)) - 1U); + } +} + +/*! + \brief computes the DLC field value, given a payload size (in bytes) + \param[in] payload_size: payload size + \param[out] none + \retval DLC value +*/ +static uint32_t can_dlc_value_compute(uint32_t payload_size) +{ + uint32_t ret = 8U; + + if(payload_size <= 8U) { + ret = payload_size; + } else if(payload_size <= 24U) { + ret = (payload_size - 9U) / 4U + 9U; + } else if(payload_size <= 64U) { + ret = (payload_size - 17U) / 16U + 13U; + } else { + ret = 8U; + } + + return ret; +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_cmp.c b/gd32a50x/standard_peripheral/source/gd32a50x_cmp.c new file mode 100644 index 0000000..fe6f197 --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_cmp.c @@ -0,0 +1,238 @@ +/*! + \file gd32a50x_cmp.c + \brief CMP driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_cmp.h" + +/*! + \brief deinitialize comparator + \param[in] none + \param[out] none + \retval none +*/ +void cmp_deinit(void) +{ + rcu_periph_reset_enable(RCU_CMPRST); + rcu_periph_reset_disable(RCU_CMPRST); +} + +/*! + \brief initialize comparator mode + \param[in] operating_mode + \arg CMP_HIGHSPEED: high speed mode + \arg CMP_MIDDLESPEED: medium speed mode + \arg CMP_LOWSPEED: low speed mode + \param[in] inverting_input + \arg CMP_1_4VREFINT: CMP inverting input VREFINT *1/4 + \arg CMP_1_2VREFINT: CMP inverting input VREFINT *1/2 + \arg CMP_3_4VREFINT: CMP inverting input VREFINT *3/4 + \arg CMP_VREFINT: CMP inverting input VREFINT + \arg CMP_DAC_OUT: CMP inverting input DAC_OUT(PA4¡¢PA5) + \arg CMP_IM_PC11: CMP inverting input PC11 + \arg CMP_IM_PC10: CMP inverting input PC10 + \arg CMP_IM_PB8: CMP inverting input PB8 + \arg CMP_IM_PA0: CMP inverting input PA0 + \arg CMP_IM_PA3: CMP inverting input PA3 + \arg CMP_IM_PA4: CMP inverting input PA4 + \arg CMP_IM_PA5: CMP inverting input PA5 + \arg CMP_IM_PA6: CMP inverting input PA6 + \param[in] plus_input + \arg CMP_IP_PC11: CMP plus input PC11 + \arg CMP_IP_PC10: CMP plus input PC10 + \arg CMP_IP_PB8: CMP plus input PB8 + \arg CMP_IP_PA0: CMP plus input PA0 + \arg CMP_IP_PA3: CMP plus input PA3 + \arg CMP_IP_PA4: CMP plus input PA4 + \arg CMP_IP_PA5: CMP plus input PA5 + \arg CMP_IP_PA6: CMP plus input PA6 + \param[in] output_hysteresis + \arg CMP_HYSTERESIS_NO: output no hysteresis + \arg CMP_HYSTERESIS_LOW: output low hysteresis + \arg CMP_HYSTERESIS_MIDDLE: output middle hysteresis + \arg CMP_HYSTERESIS_HIGH: output high hysteresis + \param[out] none + \retval none +*/ +void cmp_mode_init(operating_mode_enum operating_mode, cmp_inverting_input_enum inverting_input, cmp_plus_input_enum plus_input, + cmp_hysteresis_enum output_hysteresis) +{ + uint32_t cmp_cs = 0U; + cmp_cs = CMP_CS; + /* initialize comparator mode */ + cmp_cs &= ~(uint32_t)(CMP_CS_PM | CMP_CS_MESEL | CMP_CS_MISEL | CMP_CS_PSEL | CMP_CS_HST); + cmp_cs |= (uint32_t)(CS_CMPPM(operating_mode) | CS_CMPMSEL(inverting_input) | CS_CMPPSEL(plus_input) | CS_CMPHST(output_hysteresis)); + CMP_CS = cmp_cs; +} + +/*! + \brief initialize comparator output + \param[in] none + \param[in] output_selection + \arg CMP_OUTPUT_NONE: output no selection + \arg CMP_OUTPUT_TIMER0IC0: TIMER 0 channel0 input capture + \arg CMP_OUTPUT_TIMER7IC0: TIMER 7 channel0 input capture + \param[in] output_polarity + \arg CMP_OUTPUT_POLARITY_INVERTED: output is inverted + \arg CMP_OUTPUT_POLARITY_NOINVERTED: output is not inverted + \param[out] none + \retval none +*/ +void cmp_output_init(cmp_output_enum output_selection, cmp_output_inv_enum output_polarity) +{ + uint32_t cmp_cs = 0U; + cmp_cs = CMP_CS; + /* initialize comparator output */ + cmp_cs &= ~(uint32_t)CMP_CS_OSEL; + cmp_cs |= (uint32_t)CS_CMPOSEL(output_selection); + /* output polarity */ + if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity) { + cmp_cs |= (uint32_t)CMP_CS_PL; + } else { + cmp_cs &= ~(uint32_t)CMP_CS_PL; + } + CMP_CS = cmp_cs; +} + +/*! + \brief initialize comparator blanking function + \param[in] none + \param[in] blanking_source_selection + \arg CMP_BLANKING_NONE: output no selection + \arg CMP_BLANKING_TIMER0_OC1: TIMER 0 output channel1 + \arg CMP_BLANKING_TIMER7_OC1: TIMER 7 output channel1 + \arg CMP_BLANKING_TIMER1_OC1: TIMER 1 output channel1 + \param[out] none + \retval none +*/ +void cmp_outputblank_init(blanking_source_enum blanking_source_selection) +{ + uint32_t cmp_cs = 0U; + cmp_cs = CMP_CS; + cmp_cs &= ~(uint32_t)CMP_CS_BLK; + cmp_cs |= (uint32_t)CS_CMPBLK(blanking_source_selection); + CMP_CS = cmp_cs; +} + +/*! + \brief enable comparator + \param[in] none + \param[out] none + \retval none +*/ +void cmp_enable(void) +{ + CMP_CS |= (uint32_t)CMP_CS_EN; +} + +/*! + \brief disable comparator + \param[in] none + \param[out] none + \retval none +*/ +void cmp_disable(void) +{ + CMP_CS &= ~(uint32_t)CMP_CS_EN; +} + +/*! + \brief enable the voltage scaler + \param[in] none + \param[out] none + \retval none +*/ +void cmp_voltage_scaler_enable(void) +{ + CMP_CS |= (uint32_t)CMP_CS_SEN; +} + +/*! + \brief disable the voltage scaler + \param[in] none + \param[out] none + \retval none +*/ +void cmp_voltage_scaler_disable(void) +{ + CMP_CS &= ~(uint32_t)CMP_CS_SEN; +} + +/*! + \brief enable the scaler bridge + \param[in] none + \param[out] none + \retval none +*/ +void cmp_scaler_bridge_enable(void) +{ + CMP_CS |= (uint32_t)CMP_CS_BEN; +} + +/*! + \brief disable the scaler bridge + \param[in] none + \param[out] none + \retval none +*/ +void cmp_scaler_bridge_disable(void) +{ + CMP_CS &= ~(uint32_t)CMP_CS_BEN; +} + +/*! + \brief lock the comparator + \param[in] none + \param[out] none + \retval none +*/ +void cmp_lock_enable(void) +{ + /* lock CMP */ + CMP_CS |= (uint32_t)CMP_CS_LK; +} + +/*! + \brief get output level + \param[in] none + \param[out] none + \retval the output level +*/ +cmp_output_state_enum cmp_output_level_get(void) +{ + /* get output level of CMP */ + if(CMP_CS & CMP_CS_OT) { + return CMP_OUTPUTLEVEL_HIGH; + } else { + return CMP_OUTPUTLEVEL_LOW; + } +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_crc.c b/gd32a50x/standard_peripheral/source/gd32a50x_crc.c new file mode 100644 index 0000000..5535c74 --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_crc.c @@ -0,0 +1,241 @@ +/*! + \file gd32a50x_crc.c + \brief CRC driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_crc.h" + +/*! + \brief deinit CRC calculation unit + \param[in] none + \param[out] none + \retval none +*/ +void crc_deinit(void) +{ + CRC_IDATA = (uint32_t)0xFFFFFFFFU; + CRC_DATA = (uint32_t)0xFFFFFFFFU; + CRC_FDATA = (uint32_t)0x00000000U; + CRC_POLY = (uint32_t)0x04C11DB7U; + CRC_CTL = CRC_CTL_RST; +} + +/*! + \brief enable the reverse operation of output data + \param[in] none + \param[out] none + \retval none +*/ +void crc_reverse_output_data_enable(void) +{ + CRC_CTL &= (uint32_t)(~CRC_CTL_REV_O); + CRC_CTL |= (uint32_t)CRC_CTL_REV_O; +} + +/*! + \brief disable the reverse operation of output data + \param[in] none + \param[out] none + \retval none +*/ +void crc_reverse_output_data_disable(void) +{ + CRC_CTL &= (uint32_t)(~CRC_CTL_REV_O); +} + +/*! + \brief reset data register to the value of initialization data register + \param[in] none + \param[out] none + \retval none +*/ +void crc_data_register_reset(void) +{ + CRC_CTL |= (uint32_t)CRC_CTL_RST; +} + +/*! + \brief read the data register + \param[in] none + \param[out] none + \retval 32-bit value of the data register +*/ +uint32_t crc_data_register_read(void) +{ + uint32_t data; + data = CRC_DATA; + return (data); +} + +/*! + \brief read the free data register + \param[in] none + \param[out] none + \retval 8-bit value of the free data register +*/ +uint8_t crc_free_data_register_read(void) +{ + uint8_t fdata; + fdata = (uint8_t)CRC_FDATA; + return (fdata); +} + +/*! + \brief write the free data register + \param[in] free_data: specify 8-bit data + \param[out] none + \retval none +*/ +void crc_free_data_register_write(uint8_t free_data) +{ + CRC_FDATA = (uint32_t)free_data; +} + +/*! + \brief write the initialization data register + \param[in] init_data:specify 32-bit data + \param[out] none + \retval none +*/ +void crc_init_data_register_write(uint32_t init_data) +{ + CRC_IDATA = (uint32_t)init_data; +} + +/*! + \brief configure the CRC input data function + \param[in] data_reverse: specify input data reverse function + only one parameter can be selected which is shown as below: + \arg CRC_INPUT_DATA_NOT: input data is not reversed + \arg CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits + \arg CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits + \arg CRC_INPUT_DATA_WORD: input data is reversed on 32 bits + \param[out] none + \retval none +*/ +void crc_input_data_reverse_config(uint32_t data_reverse) +{ + CRC_CTL &= (uint32_t)(~CRC_CTL_REV_I); + CRC_CTL |= (uint32_t)data_reverse; +} + +/*! + \brief configure the CRC size of polynomial function + \param[in] poly_size: size of polynomial + only one parameter can be selected which is shown as below: + \arg CRC_CTL_PS_32: 32-bit polynomial for CRC calculation + \arg CRC_CTL_PS_16: 16-bit polynomial for CRC calculation + \arg CRC_CTL_PS_8: 8-bit polynomial for CRC calculation + \arg CRC_CTL_PS_7: 7-bit polynomial for CRC calculation + \param[out] none + \retval none +*/ +void crc_polynomial_size_set(uint32_t poly_size) +{ + CRC_CTL &= (uint32_t)(~CRC_CTL_PS); + CRC_CTL |= (uint32_t)poly_size; +} + +/*! + \brief configure the CRC polynomial value function + \param[in] poly: configurable polynomial value + \param[out] none + \retval none +*/ +void crc_polynomial_set(uint32_t poly) +{ + CRC_POLY &= (uint32_t)(~CRC_POLY_POLY); + CRC_POLY = poly; +} + +/*! + \brief CRC calculate single data + \param[in] sdata: specify input data + \param[in] data_format: input data format + only one parameter can be selected which is shown as below: + \arg INPUT_FORMAT_WORD: input data in word format + \arg INPUT_FORMAT_HALFWORD: input data in half-word format + \arg INPUT_FORMAT_BYTE: input data in byte format + \param[out] none + \retval CRC calculate value +*/ +uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format) +{ + if(INPUT_FORMAT_WORD == data_format) { + REG32(CRC) = sdata; + } else if(INPUT_FORMAT_HALFWORD == data_format) { + REG16(CRC) = (uint16_t)sdata; + } else { + REG8(CRC) = (uint8_t)sdata; + } + + return(CRC_DATA); +} + +/*! + \brief CRC calculate a data array + \param[in] array: pointer to the input data array + \param[in] size: size of the array + \param[in] data_format: input data format + only one parameter can be selected which is shown as below: + \arg INPUT_FORMAT_WORD: input data in word format + \arg INPUT_FORMAT_HALFWORD: input data in half-word format + \arg INPUT_FORMAT_BYTE: input data in byte format + \param[out] none + \retval CRC calculate value +*/ +uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format) +{ + uint8_t *data8; + uint16_t *data16; + uint32_t *data32; + uint32_t index; + + if(INPUT_FORMAT_WORD == data_format) { + data32 = (uint32_t *)array; + for(index = 0U; index < size; index++) { + REG32(CRC) = data32[index]; + } + } else if(INPUT_FORMAT_HALFWORD == data_format) { + data16 = (uint16_t *)array; + for(index = 0U; index < size; index++) { + REG16(CRC) = data16[index]; + } + } else { + data8 = (uint8_t *)array; + for(index = 0U; index < size; index++) { + REG8(CRC) = data8[index]; + } + } + + return (CRC_DATA); +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_dac.c b/gd32a50x/standard_peripheral/source/gd32a50x_dac.c new file mode 100644 index 0000000..fa79d7f --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_dac.c @@ -0,0 +1,426 @@ +/*! + \file gd32fxxx_dac.c + \brief DAC driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_dac.h" + +/* DAC register bit offset */ +#define OUT1_REG_OFFSET ((uint32_t)0x00000010U) +#define DH_12BIT_OFFSET ((uint32_t)0x00000010U) +#define DH_8BIT_OFFSET ((uint32_t)0x00000008U) + +/*! + \brief deinitialize DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_deinit(void) +{ + rcu_periph_reset_enable(RCU_DACRST); + rcu_periph_reset_disable(RCU_DACRST); +} + +/*! + \brief enable DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_enable(void) +{ + DAC_CTL |= DAC_CTL_DEN; +} + +/*! + \brief disable DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_disable(void) +{ + DAC_CTL &= ~DAC_CTL_DEN; +} + +/*! + \brief enable DAC DMA function + \param[in] none + \param[out] none + \retval none +*/ +void dac_dma_enable(void) +{ + DAC_CTL |= DAC_CTL_DDMAEN; +} + +/*! + \brief disable DAC DMA function + \param[in] none + \param[out] none + \retval none +*/ +void dac_dma_disable(void) +{ + DAC_CTL &= ~DAC_CTL_DDMAEN; +} + +/*! + \brief enable DAC output buffer + \param[in] none + \param[out] none + \retval none +*/ +void dac_output_buffer_enable(void) +{ + DAC_CTL &= ~DAC_CTL_DBOFF; +} + +/*! + \brief disable DAC output buffer + \param[in] none + \param[out] none + \retval none +*/ +void dac_output_buffer_disable(void) +{ + DAC_CTL |= DAC_CTL_DBOFF; +} + +/*! + \brief get DAC output value + \param[in] none + \param[out] none + \retval DAC output data: 0~4095 +*/ +uint16_t dac_output_value_get(void) +{ + uint16_t data = 0U; + data = (uint16_t)OUT_DO; + + return data; +} + +/*! + \brief set DAC data holding register value + \param[in] dac_align: DAC data alignment mode + only one parameter can be selected which is shown as below: + \arg DAC_ALIGN_12B_R: 12-bit right-aligned data + \arg DAC_ALIGN_12B_L: 12-bit left-aligned data + \arg DAC_ALIGN_8B_R: 8-bit right-aligned data + \param[in] data: data to be loaded, 0~4095 + \param[out] none + \retval none +*/ +void dac_data_set(uint32_t dac_align, uint16_t data) +{ + switch(dac_align){ + /* 12-bit right-aligned data */ + case DAC_ALIGN_12B_R: + OUT_R12DH = data; + break; + /* 12-bit left-aligned data */ + case DAC_ALIGN_12B_L: + OUT_L12DH = data; + break; + /* 8-bit right-aligned data */ + case DAC_ALIGN_8B_R: + OUT_R8DH = data; + break; + default: + break; + } +} + +/*! + \brief enable DAC trigger + \param[in] none + \param[out] none + \retval none +*/ +void dac_trigger_enable(void) +{ + DAC_CTL |= DAC_CTL_DTEN; +} + +/*! + \brief disable DAC trigger + \param[in] none + \param[out] none + \retval none +*/ +void dac_trigger_disable(void) +{ + DAC_CTL &= ~DAC_CTL_DTEN; +} + +/*! + \brief configure DAC trigger source + \param[in] triggersource: external triggers of DAC + only one parameter can be selected which is shown as below: + \arg DAC_TRIGGER_EXTRIG: TRIGSEL trigger + \arg DAC_TRIGGER_SOFTWARE: software trigger + \param[out] none + \retval none +*/ +void dac_trigger_source_config(uint32_t triggersource) +{ + /* configure DAC trigger source */ + DAC_CTL &= (uint32_t)(~DAC_CTL_DTSEL); + DAC_CTL |= triggersource; +} + +/*! + \brief enable DAC software trigger + \param[in] none + \retval none +*/ +void dac_software_trigger_enable(void) +{ + DAC_SWT |= DAC_SWT_SWTR; +} + +/*! + \brief disable DAC software trigger + \param[in] none + \param[out] none + \retval none +*/ +void dac_software_trigger_disable(void) +{ + DAC_SWT &= ~DAC_SWT_SWTR; +} + +/*! + \brief configure DAC wave mode + \param[in] wave_mode: DAC wave mode + only one parameter can be selected which is shown as below: + \arg DAC_WAVE_DISABLE: wave mode disable + \arg DAC_WAVE_MODE_LFSR: LFSR noise mode + \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode + \param[out] none + \retval none +*/ +void dac_wave_mode_config(uint32_t wave_mode) +{ + /* configure DAC wave mode */ + DAC_CTL &= ~DAC_CTL_DWM; + DAC_CTL |= wave_mode; +} + +/*! + \brief configure DAC wave bit width + \param[in] bit_width: DAC noise wave bit width + only one parameter can be selected which is shown as below: + \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 + \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 + \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 + \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 + \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 + \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 + \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 + \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 + \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 + \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 + \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 + \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 + \param[out] none + \retval none +*/ +void dac_wave_bit_width_config(uint32_t bit_width) +{ + /* configure DAC wave bit width */ + DAC_CTL &= ~DAC_CTL_DWBW; + DAC_CTL |= bit_width; +} + +/*! + \brief configure DAC LFSR noise mode + \param[in] unmask_bits: LFSR noise unmask bits + only one parameter can be selected which is shown as below: + \arg DAC_LFSR_BIT0: unmask the LFSR bit0 + \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] + \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] + \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] + \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] + \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] + \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] + \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] + \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] + \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] + \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] + \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] + \param[out] none + \retval none +*/ +void dac_lfsr_noise_config(uint32_t unmask_bits) +{ + /* configure DAC LFSR noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW; + DAC_CTL |= unmask_bits; +} + +/*! + \brief configure DAC triangle noise mode + \param[in] amplitude: the amplitude of the triangle + only one parameter can be selected which is shown as below: + \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 + \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 + \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 + \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 + \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 + \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 + \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 + \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 + \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 + \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 + \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 + \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 + \param[out] none + \retval none +*/ +void dac_triangle_noise_config(uint32_t amplitude) +{ + /* configure DAC triangle noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW; + DAC_CTL |= amplitude; +} + +/*! + \brief get DAC flag + \param[in] dac_flag: DAC flag + only one parameter can be selected which is shown as below: + \arg DAC_FLAG_DDUDR: DMA underrun flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dac_flag_get(uint32_t flag) +{ + /* check DAC flag */ + if(DAC_FLAG_DDUDR == flag){ + if(0U != (DAC_STAT & DAC_STAT_DDUDR)){ + return SET; + } + } + return RESET; +} + +/*! + \brief clear DAC flag + \param[in] flag: DAC flag + only one parameter can be selected which is shown as below: + \arg DAC_FLAG_DDUDR: DMA underrun flag + \param[out] none + \retval none +*/ +void dac_flag_clear(uint32_t flag) +{ + /* clear DAC_OUT0 flag */ + if(DAC_FLAG_DDUDR == flag){ + DAC_STAT |= (uint32_t)DAC_STAT_DDUDR; + } +} + +/*! + \brief enable DAC interrupt + \param[in] interrupt: the DAC interrupt + only one parameter can be selected which is shown as below: + \arg DAC_INT_DDUDRIE: DMA underrun interrupt enable + \param[out] none + \retval none +*/ +void dac_interrupt_enable(uint32_t interrupt) +{ + /* enable DAC interrupt */ + if(DAC_INT_DDUDRIE == interrupt){ + DAC_CTL |= (uint32_t)DAC_CTL_DDUDRIE; + } +} + +/*! + \brief disable DAC interrupt + \param[in] interrupt: the DAC interrupt + only one parameter can be selected which is shown as below: + \arg DAC_INT_DDUDRIE: DMA underrun interrupt disable + \param[out] none + \retval none +*/ +void dac_interrupt_disable(uint32_t interrupt) +{ + /* disable DAC interrupt */ + if(DAC_INT_DDUDRIE == interrupt){ + DAC_CTL &= (uint32_t)(~DAC_CTL_DDUDRIE); + } +} + +/*! + \brief get DAC interrupt flag + \param[in] int_flag: DAC interrupt flag + only one parameter can be selected which is shown as below: + \arg DAC_INT_FLAG_DDUDR: DMA underrun interrupt flag + \param[out] none + \retval the state of DAC interrupt flag(SET or RESET) +*/ +FlagStatus dac_interrupt_flag_get(uint32_t int_flag) +{ + uint32_t reg1 = 0U, reg2 = 0U; + + /* check DAC interrupt flag */ + if(DAC_INT_FLAG_DDUDR == int_flag){ + reg1 = DAC_STAT & DAC_STAT_DDUDR; + reg2 = DAC_CTL & DAC_CTL_DDUDRIE; + } + + /*get DAC interrupt flag status */ + if((0U != reg1) && (0U != reg2)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear DAC interrupt flag + \param[in] int_flag: DAC interrupt flag + only one parameter can be selected which is shown as below: + \arg DAC_INT_FLAG_DDUDR: DMA underrun interrupt flag + \param[out] none + \retval none +*/ +void dac_interrupt_flag_clear(uint32_t int_flag) +{ + /* clear DAC interrupt flag */ + if(DAC_INT_FLAG_DDUDR == int_flag){ + DAC_STAT |= (uint32_t)DAC_STAT_DDUDR; + } +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_dbg.c b/gd32a50x/standard_peripheral/source/gd32a50x_dbg.c new file mode 100644 index 0000000..4d0fda1 --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_dbg.c @@ -0,0 +1,126 @@ +/*! + \file gd32a50x_dbg.c + \brief DBG driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_dbg.h" + +#define DBG_RESET_VAL ((uint32_t)0x00000000U) /*!< DBG reset value */ + +/*! + \brief deinitialize the DBG + \param[in] none + \param[out] none + \retval none +*/ +void dbg_deinit(void) +{ + DBG_CTL = DBG_RESET_VAL; +} + +/*! + \brief read DBG_ID code register + \param[in] none + \param[out] none + \retval DBG_ID code +*/ +uint32_t dbg_id_get(void) +{ + return DBG_ID; +} + +/*! + \brief enable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + one or more parameters can be selected which are shown as below: + \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_enable(uint32_t dbg_low_power) +{ + DBG_CTL |= dbg_low_power; +} + +/*! + \brief disable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + one or more parameters can be selected which are shown as below: + \arg DBG_LOW_POWER_SLEEP: do not keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: do not keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: do not keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_disable(uint32_t dbg_low_power) +{ + DBG_CTL &= ~dbg_low_power; +} + +/*! + \brief enable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: refer to dbg_periph_enum + only one parameter can be selected which is shown as below: + \arg DBG_FWDGT_HOLD : hold FWDGT counter when core is halted + \arg DBG_WWDGT_HOLD : hold WWDGT counter when core is halted + \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus timeout when core is halted + \arg DBG_TIMERx_HOLD (x=0,1,5,6,7,19,20): hold TIMERx counter when core is halted + \arg DBG_MFCOM_HOLD : hold MFCOM counter when core is halted + \arg DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_enable(dbg_periph_enum dbg_periph) +{ + DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph)); +} + +/*! + \brief disable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: refer to dbg_periph_enum + only one parameter can be selected which is shown as below: + \arg DBG_FWDGT_HOLD : hold FWDGT counter when core is halted + \arg DBG_WWDGT_HOLD : hold WWDGT counter when core is halted + \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus timeout when core is halted + \arg DBG_TIMERx_HOLD (x=0,1,5,6,7,19,20): hold TIMERx counter when core is halted + \arg DBG_MFCOM_HOLD : hold MFCOM counter when core is halted + \arg DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_disable(dbg_periph_enum dbg_periph) +{ + DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph)); +} + diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_dma.c b/gd32a50x/standard_peripheral/source/gd32a50x_dma.c new file mode 100644 index 0000000..75e4346 --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_dma.c @@ -0,0 +1,1245 @@ +/*! + \file gd32a50x_dma.c + \brief DMA driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_dma.h" +#include + +#define DMA_WRONG_HANDLE while(1){} + +/* DMA functions */ +/*! + \brief deinitialize DMA channel registers + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is deinitialized + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[out] none + \retval none +*/ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) +{ + /* disable DMA a channel */ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; + /* reset DMA channel registers */ + DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; + DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; + DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; + DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); +} + +/*! + \brief initialize the parameters of DMA struct with the default values + \param[in] init_struct: the initialization data needed to initialize DMA channel + \param[out] none + \retval none +*/ +void dma_struct_para_init(dma_parameter_struct* init_struct) +{ + if(NULL == init_struct) { + DMA_WRONG_HANDLE + } + + /* set the DMA struct with the default values */ + init_struct->periph_addr = 0U; + init_struct->periph_width = 0U; + init_struct->periph_inc = (uint8_t)DMA_PERIPH_INCREASE_DISABLE; + init_struct->memory_addr = 0U; + init_struct->memory_width = 0U; + init_struct->memory_inc = (uint8_t)DMA_MEMORY_INCREASE_DISABLE; + init_struct->number = 0U; + init_struct->direction = (uint8_t)DMA_PERIPHERAL_TO_MEMORY; + init_struct->priority = (uint32_t)DMA_PRIORITY_LOW; + init_struct->request = DMA_REQUEST_M2M; +} + +/*! + \brief initialize DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is initialized + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[in] init_struct: the data needed to initialize DMA channel + periph_addr: peripheral base address + periph_width: DMA_PERIPHERAL_WIDTH_8BIT,DMA_PERIPHERAL_WIDTH_16BIT,DMA_PERIPHERAL_WIDTH_32BIT + periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE + memory_addr: memory base address + memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT + memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE + direction: DMA_PERIPHERAL_TO_MEMORY,DMA_MEMORY_TO_PERIPHERAL + number: the number of remaining data to be transferred by the DMA + priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH + request: DMA_REQUEST_M2M, DMA_REQUEST_GENERATOR0, DMA_REQUEST_GENERATOR1, DMA_REQUEST_GENERATOR2 + DMA_REQUEST_GENERATOR3, DMA_REQUEST_ADC, DMA_REQUEST_DAC_CH0, DMA_REQUEST_I2C1_RX + DMA_REQUEST_I2C1_TX, DMA_REQUEST_I2C0_RX, DMA_REQUEST_I2C0_TX, DMA_REQUESR_SSTAT0 + DMA_REQUESR_SSTAT1, DMA_REQUESR_SSTAT2, DMA_REQUESR_SSTAT3, DMA_REQUEST_SPI0_RX + DMA_REQUEST_SPI0_TX, DMA_REQUEST_SPI1_RX, DMA_REQUEST_SPI1_TX, DMA_REQUEST_TIMER0_CH0 + DMA_REQUEST_TIMER0_CH1, DMA_REQUEST_TIMER0_CH2, DMA_REQUEST_TIMER0_CH3, DMA_REQUEST_TIMER0_TI + DMA_REQUEST_TIMER0_UP, DMA_REQUEST_TIMER0_CO, DMA_REQUEST_TIMER0_MCH0, DMA_REQUEST_TIMER0_MCH1 + DMA_REQUEST_TIMER0_MCH2, DMA_REQUEST_TIMER0_MCH3, DMA_REQUEST_TIMER1_CH0, DMA_REQUEST_TIMER1_CH1 + DMA_REQUEST_TIMER1_CH2, DMA_REQUEST_TIMER1_CH3, DMA_REQUEST_TIMER1_TI, DMA_REQUEST_TIMER1_UP + DMA_REQUEST_TIMER7_CH0, DMA_REQUEST_TIMER7_CH1, DMA_REQUEST_TIMER7_CH2, DMA_REQUEST_TIMER7_CH3 + DMA_REQUEST_TIMER7_TI, DMA_REQUEST_TIMER7_UP, DMA_REQUEST_TIMER7_CO, DMA_REQUEST_TIMER7_MCH0 + DMA_REQUEST_TIMER7_MCH1, DMA_REQUEST_TIMER7_MCH2, DMA_REQUEST_TIMER7_MCH3, DMA_REQUEST_CAN1 + DMA_REQUEST_CAN0, DMA_REQUEST_USART0_RX, DMA_REQUEST_USART0_TX, DMA_REQUEST_USART1_RX + DMA_REQUEST_USART1_TX, DMA_REQUEST_USART2_RX, DMA_REQUEST_USART2_TX, DMA_REQUEST_TIMER5_UP + DMA_REQUEST_TIMER6_UP, DMA_REQUEST_TIMER19_CH0, DMA_REQUEST_TIMER19_CH1, DMA_REQUEST_TIMER19_CH2 + DMA_REQUEST_TIMER19_CH3, DMA_REQUEST_TIMER19_TI, DMA_REQUEST_TIMER19_UP, DMA_REQUEST_TIMER19_CO + DMA_REQUEST_TIMER19_MCH0, DMA_REQUEST_TIMER19_MCH1, DMA_REQUEST_TIMER19_MCH2, DMA_REQUEST_TIMER19_MCH3 + DMA_REQUEST_TIMER20_CH0, DMA_REQUEST_TIMER20_CH1, DMA_REQUEST_TIMER20_CH2, DMA_REQUEST_TIMER20_CH3 + DMA_REQUEST_TIMER20_TI, DMA_REQUEST_TIMER20_UP, DMA_REQUEST_TIMER20_CO, DMA_REQUEST_TIMER20_MCH0 + DMA_REQUEST_TIMER20_MCH1, DMA_REQUEST_TIMER20_MCH2, DMA_REQUEST_TIMER20_MCH3 + \param[out] none + \retval none +*/ +void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct* init_struct) +{ + uint32_t ctl; + + if(NULL == init_struct) { + DMA_WRONG_HANDLE + } + + dma_channel_disable(dma_periph, channelx); + + /* configure peripheral base address */ + DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; + + /* configure memory base address */ + DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr; + + /* configure the number of remaining data to be transferred */ + DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); + + /* configure peripheral transfer width, memory transfer width, channel priotity */ + ctl = DMA_CHCTL(dma_periph, channelx); + ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); + ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority); + DMA_CHCTL(dma_periph, channelx) = ctl; + + /* configure peripheral increasing mode */ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } + + /* configure memory increasing mode */ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; + } + + /* configure the direction of data transfer */ + if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; + } + + if(DMA0 == dma_periph) { + DMAMUX_RM_CHXCFG((uint32_t)channelx) &= ~DMAMUX_RM_CHXCFG_MUXID; + DMAMUX_RM_CHXCFG((uint32_t)channelx) |= init_struct->request; + } else { + DMAMUX_RM_CHXCFG((uint32_t)channelx + 7U ) &= ~DMAMUX_RM_CHXCFG_MUXID; + DMAMUX_RM_CHXCFG((uint32_t)channelx + 7U ) |= init_struct->request; + } +} + +/*! + \brief enable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[out] none + \retval none +*/ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; +} + +/*! + \brief disable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[out] none + \retval none +*/ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; +} + +/*! + \brief enable memory to memory mode + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; +} + +/*! + \brief disable memory to memory mode + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; +} + +/*! + \brief enable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[out] none + \retval none +*/ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; +} + +/*! + \brief disable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[out] none + \retval none +*/ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; +} + +/*! + \brief set DMA peripheral base address + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set peripheral base address + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[in] address: peripheral base address + \param[out] none + \retval none +*/ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) +{ + DMA_CHPADDR(dma_periph, channelx) = address; +} + +/*! + \brief set DMA memory base address + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set memory base address + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[in] address: memory base address + \param[out] none + \retval none +*/ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) +{ + DMA_CHMADDR(dma_periph, channelx) = address; +} + +/*! + \brief set the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[in] number: the number of remaining data to be transferred by the DMA + \param[out] none + \retval none +*/ +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) +{ + DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); +} + +/*! + \brief get the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[out] none + \retval the number of remaining data to be transferred by the DMA +*/ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) +{ + return (uint32_t)DMA_CHCNT(dma_periph, channelx); +} + +/*! + \brief configure priority level of DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[in] priority: priority level of this channel + only one parameter can be selected which is shown as below: + \arg DMA_PRIORITY_LOW: low priority + \arg DMA_PRIORITY_MEDIUM: medium priority + \arg DMA_PRIORITY_HIGH: high priority + \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority + \param[out] none + \retval none +*/ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) +{ + uint32_t ctl; + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PRIO; + ctl |= priority; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer data width of memory + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[in] mwidth: transfer data width of memory + only one parameter can be selected which is shown as below: + \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit + \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit + \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit + \param[out] none + \retval none +*/ +void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth) +{ + uint32_t ctl; + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_MWIDTH; + ctl |= mwidth; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer data width of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[in] pwidth: transfer data width of peripheral + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit + \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit + \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit + \param[out] none + \retval none +*/ +void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth) +{ + uint32_t ctl; + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PWIDTH; + ctl |= pwidth; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief enable next address increasement algorithm of memory + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[out] none + \retval none +*/ +void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; +} + +/*! + \brief disable next address increasement algorithm of memory + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[out] none + \retval none +*/ +void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; +} + +/*! + \brief enable next address increasement algorithm of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[out] none + \retval none +*/ +void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; +} + +/*! + \brief disable next address increasement algorithm of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[out] none + \retval none +*/ +void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; +} + +/*! + \brief configure the direction of data transfer on the channel + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[in] direction: specify the direction of data transfer + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory + \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral + \param[out] none + \retval none +*/ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction) +{ + if(DMA_PERIPHERAL_TO_MEMORY == direction) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief check DMA flag is set or not + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + FlagStatus reval; + + if(0U != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))) { + reval = SET; + } else { + reval = RESET; + } + + return reval; +} + +/*! + \brief clear a DMA channel flag + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to clear flag + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval none +*/ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); +} + +/*! + \brief enable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[in] source: specify which interrupt to enable + only one parameter can be selected which is shown as below: + \arg DMA_INT_ERR: channel error interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_FTF: channel full transfer finish interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + DMA_CHCTL(dma_periph, channelx) |= source; +} + +/*! + \brief disable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[in] source: specify which interrupt to disable + only one parameter can be selected which is shown as below: + \arg DMA_INT_ERR: channel error interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_FTF: channel full transfer finish interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + DMA_CHCTL(dma_periph, channelx) &= ~source; +} + +/*! + \brief check DMA flag and interrupt enable bit is set or not + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FTF: transfer finish flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish flag of channel + \arg DMA_INT_FLAG_ERR: error flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t int_flag) +{ + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; + + switch(int_flag) { + case DMA_INT_FLAG_FTF: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(int_flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; + break; + case DMA_INT_FLAG_HTF: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(int_flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INT_FLAG_ERR: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(int_flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE; + break; + default: + break; + } + + if(interrupt_flag && interrupt_enable) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear a DMA channel interrupt flag + \param[in] dma_periph: DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to clear flag + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_G: global interrupt flag of channel + \arg DMA_INT_FLAG_FTF: transfer finish flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish flag of channel + \arg DMA_INT_FLAG_ERR: error flag of channel + \param[out] none + \retval none +*/ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t int_flag) +{ + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(int_flag, channelx); +} + +/* DMAMUX functions */ +/*! + \brief initialize the parameters of DMAMUX synchronization mode structure with the default values + \param[in] none + \param[out] init_struct: the initialization data needed to initialize DMAMUX request multiplexer channel synchronization mode + \retval none +*/ +void dmamux_sync_struct_para_init(dmamux_sync_parameter_struct *init_struct) +{ + if(NULL == init_struct) { + DMA_WRONG_HANDLE + } + + /* set the DMAMUX synchronization struct with the default values */ + init_struct->sync_id = DMAMUX_SYNC_EVTX_OUT0; + init_struct->sync_polarity = DMAMUX_SYNC_RISING; + init_struct->request_number = 1U; +} + +/*! + \brief initialize DMAMUX request multiplexer channel synchronization mode + \param[in] channelx: specify which DMAMUX request multiplexer channel is initialized + only one parameter can be selected which is shown as below: + \arg DMAMUX_MULTIPLEXER_CHx(x=0..11) + \param[in] init_struct: the data needed to initialize DMAMUX request multiplexer channel + sync_id: DMAMUX_SYNC_EXTI0, DMAMUX_SYNC_EXTI1, DMAMUX_SYNC_EXTI2, DMAMUX_SYNC_EXTI3, + DMAMUX_SYNC_EXTI4, DMAMUX_SYNC_EXTI5, DMAMUX_SYNC_EXTI6, DMAMUX_SYNC_EXTI7, + DMAMUX_SYNC_EXTI8, DMAMUX_SYNC_EXTI9, DMAMUX_SYNC_EXTI10, DMAMUX_SYNC_EXTI11, + DMAMUX_SYNC_EXTI12, DMAMUX_SYNC_EXTI13, DMAMUX_SYNC_EXTI14, DMAMUX_SYNC_EXTI15, + DMAMUX_SYNC_EVTX_OUT0, DMAMUX_SYNC_EVTX_OUT1, DMAMUX_SYNC_EVTX_OUT2, DMAMUX_SYNC_EVTX_OUT3, + DMAMUX_SYNC_TIMER20_CH0_O + sync_polarity: DMAMUX_SYNC_NO_EVENT, DMAMUX_SYNC_RISING, DMAMUX_SYNC_FALLING, DMAMUX_SYNC_RISING_FALLING + request_number: the number of DMA request that will be authorized after a sync event, from 1 to 32 + \param[out] none + \retval none +*/ +void dmamux_synchronization_init(dmamux_multiplexer_channel_enum channelx, dmamux_sync_parameter_struct *init_struct) +{ + uint32_t cfg; + + if(NULL == init_struct) { + DMA_WRONG_HANDLE + } + + /* disable synchronization mode and event generation for DMA request forward number configuration */ + DMAMUX_RM_CHXCFG(channelx) &= ~(DMAMUX_RM_CHXCFG_SYNCEN | DMAMUX_RM_CHXCFG_EVGEN); + + /* configure synchronization input identification, synchronization input polarity, number of DMA requests to forward */ + cfg = DMAMUX_RM_CHXCFG(channelx); + cfg &= ~(DMAMUX_RM_CHXCFG_SYNCID | DMAMUX_RM_CHXCFG_NBR | DMAMUX_RM_CHXCFG_SYNCP); + cfg |= (init_struct->sync_polarity | (init_struct->sync_id) | RM_CHXCFG_NBR(init_struct->request_number - 1U)); + DMAMUX_RM_CHXCFG(channelx) = cfg; +} + +/*! + \brief enable synchronization mode + \param[in] channelx: specify which DMAMUX request multiplexer channel is configured + only one parameter can be selected which is shown as below: + \arg DMAMUX_MULTIPLEXER_CHx(x=0..11) + \param[out] none + \retval none +*/ +void dmamux_synchronization_enable(dmamux_multiplexer_channel_enum channelx) +{ + DMAMUX_RM_CHXCFG(channelx) |= DMAMUX_RM_CHXCFG_SYNCEN; +} + +/*! + \brief disable synchronization mode + \param[in] channelx: specify which DMAMUX request multiplexer channel is configured + only one parameter can be selected which is shown as below: + \arg DMAMUX_MULTIPLEXER_CHx(x=0..11) + \param[out] none + \retval none +*/ +void dmamux_synchronization_disable(dmamux_multiplexer_channel_enum channelx) +{ + DMAMUX_RM_CHXCFG(channelx) &= (~DMAMUX_RM_CHXCFG_SYNCEN); +} + +/*! + \brief enable event generation + \param[in] channelx: specify which DMAMUX request multiplexer channel is configured + only one parameter can be selected which is shown as below: + \arg DMAMUX_MULTIPLEXER_CHx(x=0..11) + \param[out] none + \retval none +*/ +void dmamux_event_generation_enable(dmamux_multiplexer_channel_enum channelx) +{ + DMAMUX_RM_CHXCFG(channelx) |= DMAMUX_RM_CHXCFG_EVGEN; +} + +/*! + \brief disable event generation + \param[in] channelx: specify which DMAMUX request multiplexer channel is configured + only one parameter can be selected which is shown as below: + \arg DMAMUX_MULTIPLEXER_CHx(x=0..11) + \param[out] none + \retval none +*/ +void dmamux_event_generation_disable(dmamux_multiplexer_channel_enum channelx) +{ + DMAMUX_RM_CHXCFG(channelx) &= (~DMAMUX_RM_CHXCFG_EVGEN); +} + +/*! + \brief initialize the parameters of DMAMUX request generator structure with the default values + \param[in] init_struct: the initialization data needed to initialize DMAMUX request generator channel + \param[out] none + \retval none +*/ +void dmamux_gen_struct_para_init(dmamux_gen_parameter_struct *init_struct) +{ + if(NULL == init_struct) { + DMA_WRONG_HANDLE + } + + /* set the DMAMUX request generator structure with the default values */ + init_struct->trigger_id = DMAMUX_TRIGGER_EVTX_OUT0; + init_struct->trigger_polarity = DMAMUX_GEN_RISING; + init_struct->request_number = 1U; +} + +/*! + \brief initialize DMAMUX request generator channel + \param[in] channelx: specify which DMAMUX request generator channel is initialized + only one parameter can be selected which is shown as below: + \arg DMAMUX_GENCHx(x=0..3) + \param[in] init_struct: the data needed to initialize DMAMUX request generator channel + trigger_id: DMAMUX_TRIGGER_EXTI0, DMAMUX_TRIGGER_EXTI1, DMAMUX_TRIGGER_EXTI2, DMAMUX_TRIGGER_EXTI3, + DMAMUX_TRIGGER_EXTI4, DMAMUX_TRIGGER_EXTI5, DMAMUX_TRIGGER_EXTI6, DMAMUX_TRIGGER_EXTI7, + DMAMUX_TRIGGER_EXTI8, DMAMUX_TRIGGER_EXTI9, DMAMUX_TRIGGER_EXTI10, DMAMUX_TRIGGER_EXTI11, + DMAMUX_TRIGGER_EXTI12, DMAMUX_TRIGGER_EXTI13, DMAMUX_TRIGGER_EXTI14, DMAMUX_TRIGGER_EXTI15, + DMAMUX_TRIGGER_EVTX_OUT0, DMAMUX_TRIGGER_EVTX_OUT0, DMAMUX_TRIGGER_EVTX_OUT0, DMAMUX_TRIGGER_EVTX_OUT0, + DMAMUX_TRIGGER_TIMER20_CH0_O + trigger_polarity: DMAMUX_GEN_NO_EVENT, DMAMUX_GEN_RISING, DMAMUX_GEN_FALLING, DMAMUX_GEN_RISING_FALLING + request_number: the number of DMA request that will be generated after a signal event, from 1 to 32 + \param[out] none + \retval none +*/ +void dmamux_request_generator_init(dmamux_generator_channel_enum channelx, dmamux_gen_parameter_struct *init_struct) +{ + uint32_t cfg; + + if(NULL == init_struct) { + DMA_WRONG_HANDLE + } + + /* disable DMAMUX request generator channel for DMA request generation number configuration */ + DMAMUX_RG_CHXCFG(channelx) &= ~(DMAMUX_RG_CHXCFG_RGEN); + + /* configure trigger input identification, trigger polarity, number of DMA requests to be generated */ + cfg = DMAMUX_RG_CHXCFG(channelx); + cfg &= ~(DMAMUX_RG_CHXCFG_TID | DMAMUX_RG_CHXCFG_NBRG | DMAMUX_RG_CHXCFG_RGTP); + cfg |= (RG_CHXCFG_NBRG(init_struct->request_number - 1U) | init_struct->trigger_id | init_struct->trigger_polarity); + DMAMUX_RG_CHXCFG(channelx) = cfg; +} + +/*! + \brief enable DMAMUX request generator channel + \param[in] channelx: specify which DMAMUX request generator channel is configured + only one parameter can be selected which is shown as below: + \arg DMAMUX_GENCHx(x=0..3) + \param[out] none + \retval none +*/ +void dmamux_request_generator_channel_enable(dmamux_generator_channel_enum channelx) +{ + DMAMUX_RG_CHXCFG(channelx) |= DMAMUX_RG_CHXCFG_RGEN; +} + +/*! + \brief disable DMAMUX request generator channel + \param[in] channelx: specify which DMAMUX request generator channel is configured + only one parameter can be selected which is shown as below: + \arg DMAMUX_GENCHx(x=0..3) + \param[out] none + \retval none +*/ +void dmamux_request_generator_channel_disable(dmamux_generator_channel_enum channelx) +{ + DMAMUX_RG_CHXCFG(channelx) &= (~DMAMUX_RG_CHXCFG_RGEN); +} + +/*! + \brief configure synchronization input polarity + \param[in] channelx: specify which DMAMUX request multiplexer channel is configured + only one parameter can be selected which is shown as below: + \arg DMAMUX_MUXCHx(x=0..11) + \param[in] polarity: synchronization input polarity + only one parameter can be selected which is shown as below: + \arg DMAMUX_SYNC_NO_EVENT: no event detection + \arg DMAMUX_SYNC_RISING: rising edge + \arg DMAMUX_SYNC_FALLING: falling edge + \arg DMAMUX_SYNC_RISING_FALLING: rising and falling edges + \param[out] none + \retval none +*/ +void dmamux_synchronization_polarity_config(dmamux_multiplexer_channel_enum channelx, uint32_t polarity) +{ + DMAMUX_RM_CHXCFG(channelx) &= ~DMAMUX_RM_CHXCFG_SYNCP; + DMAMUX_RM_CHXCFG(channelx) |= polarity; +} + +/*! + \brief configure number of DMA requests to forward + \param[in] channelx: specify which DMAMUX request multiplexer channel is configured + only one parameter can be selected which is shown as below: + \arg DMAMUX_MUXCHx(x=0..6) + \param[in] number: DMA requests number to forward + only one parameter can be selected which is shown as below: + \arg 1 - 32 + \param[out] none + \retval none +*/ +void dmamux_request_forward_number_config(dmamux_multiplexer_channel_enum channelx, uint32_t number) +{ + DMAMUX_RM_CHXCFG(channelx) &= ~DMAMUX_RM_CHXCFG_NBR; + DMAMUX_RM_CHXCFG(channelx) |= RM_CHXCFG_NBR(number - 1U); +} + +/*! + \brief configure synchronization input identification + \param[in] channelx: specify which DMAMUX request multiplexer channel is configured + only one parameter can be selected which is shown as below: + \arg DMAMUX_MUXCHx(x=0..11) + \param[in] id: synchronization input identification + only one parameter can be selected which is shown as below: + \arg DMAMUX_SYNC_EXTI0: synchronization input is EXTI0 + \arg DMAMUX_SYNC_EXTI1: synchronization input is EXTI1 + \arg DMAMUX_SYNC_EXTI2: synchronization input is EXTI2 + \arg DMAMUX_SYNC_EXTI3: synchronization input is EXTI3 + \arg DMAMUX_SYNC_EXTI4: synchronization input is EXTI4 + \arg DMAMUX_SYNC_EXTI5: synchronization input is EXTI5 + \arg DMAMUX_SYNC_EXTI6: synchronization input is EXTI6 + \arg DMAMUX_SYNC_EXTI7: synchronization input is EXTI7 + \arg DMAMUX_SYNC_EXTI8: synchronization input is EXTI8 + \arg DMAMUX_SYNC_EXTI9: synchronization input is EXTI9 + \arg DMAMUX_SYNC_EXTI10: synchronization input is EXTI10 + \arg DMAMUX_SYNC_EXTI11: synchronization input is EXTI11 + \arg DMAMUX_SYNC_EXTI12: synchronization input is EXTI12 + \arg DMAMUX_SYNC_EXTI13: synchronization input is EXTI13 + \arg DMAMUX_SYNC_EXTI14: synchronization input is EXTI14 + \arg DMAMUX_SYNC_EXTI15: synchronization input is EXTI15 + \arg DMAMUX_SYNC_EVTX_OUT0: synchronization input is Evtx_out0 + \arg DMAMUX_SYNC_EVTX_OUT1: synchronization input is Evtx_out1 + \arg DMAMUX_SYNC_EVTX_OUT2: synchronization input is Evtx_out2 + \arg DMAMUX_SYNC_EVTX_OUT3: synchronization input is Evtx_out3 + \arg DMAMUX_SYNC_TIMER20_CH0_O: synchronization input is TIMER20_CH0_O + \param[out] none + \retval none +*/ +void dmamux_sync_id_config(dmamux_multiplexer_channel_enum channelx, uint32_t id) +{ + DMAMUX_RM_CHXCFG(channelx) &= ~DMAMUX_RM_CHXCFG_SYNCID; + DMAMUX_RM_CHXCFG(channelx) |= id; +} + +/*! + \brief configure multiplexer input identification + \param[in] channelx: specify which DMAMUX request multiplexer channel is configured + only one parameter can be selected which is shown as below: + \arg DMAMUX_MUXCHx(x=0..11) + \param[in] id: input DMA request identification + only one parameter can be selected which is shown as below: + \arg DMA_REQUEST_M2M: memory to memory transfer + \arg DMA_REQUEST_GENERATOR0: DMAMUX request generator 0 + \arg DMA_REQUEST_GENERATOR1: DMAMUX request generator 1 + \arg DMA_REQUEST_GENERATOR2: DMAMUX request generator 2 + \arg DMA_REQUEST_GENERATOR3: DMAMUX request generator 3 + \arg DMA_REQUEST_ADC: DMAMUX ADC request + \arg DMA_REQUEST_DAC_CH0: DMAMUX DAC_CH0 request + \arg DMA_REQUEST_I2C1_RX: DMAMUX I2C1 RX request + \arg DMA_REQUEST_I2C1_TX: DMAMUX I2C1 TX request + \arg DMA_REQUEST_I2C0_RX: DMAMUX I2C0 RX request + \arg DMA_REQUEST_I2C0_TX: DMAMUX I2C0 TX request + \arg DMA_REQUESR_SSTAT0: DMAMUX SSTAT0 request + \arg DMA_REQUESR_SSTAT1: DMAMUX SSTAT1 request + \arg DMA_REQUESR_SSTAT2: DMAMUX SSTAT2 request + \arg DMA_REQUESR_SSTAT3: DMAMUX SSTAT3 request + \arg DMA_REQUEST_SPI0_RX DMAMUX SPI0 RX request + \arg DMA_REQUEST_SPI0_TX: DMAMUX SPI0 TX request + \arg DMA_REQUEST_SPI1_RX: DMAMUX SPI1 RX request + \arg DMA_REQUEST_SPI1_TX: DMAMUX SPI1 TX request + \arg DMA_REQUEST_TIMER0_CH0: DMAMUX TIMER0 CH0 request + \arg DMA_REQUEST_TIMER0_CH1: DMAMUX TIMER0 CH1 request + \arg DMA_REQUEST_TIMER0_CH2: DMAMUX TIMER0 CH2 request + \arg DMA_REQUEST_TIMER0_CH3: DMAMUX TIMER0 CH3 request + \arg DMA_REQUEST_TIMER0_TI: DMAMUX TIMER0 TI request + \arg DMA_REQUEST_TIMER0_UP: DMAMUX TIMER0 UP request + \arg DMA_REQUEST_TIMER0_CO: DMAMUX TIMER0 CO request + \arg DMA_REQUEST_TIMER0_MCH0: DMAMUX TIMER0 MCH0 request + \arg DMA_REQUEST_TIMER0_MCH1: DMAMUX TIMER0 MCH1 request + \arg DMA_REQUEST_TIMER0_MCH2: DMAMUX TIMER0 MCH2 request + \arg DMA_REQUEST_TIMER0_MCH3: DMAMUX TIMER0 MCH3 request + \arg DMA_REQUEST_TIMER1_CH0: DMAMUX TIMER1 CH0 request + \arg DMA_REQUEST_TIMER1_CH1: DMAMUX TIMER1 CH1 request + \arg DMA_REQUEST_TIMER1_CH2: DMAMUX TIMER1 CH2 request + \arg DMA_REQUEST_TIMER1_CH3: DMAMUX TIMER1 CH3 request + \arg DMA_REQUEST_TIMER1_TI: DMAMUX TIMER1 TI request + \arg DMA_REQUEST_TIMER1_UP: DMAMUX TIMER1 UP request + \arg DMA_REQUEST_TIMER7_CH0: DMAMUX TIMER7 CH0 request + \arg DMA_REQUEST_TIMER7_CH1: DMAMUX TIMER7 CH1 request + \arg DMA_REQUEST_TIMER7_CH2: DMAMUX TIMER7 CH2 request + \arg DMA_REQUEST_TIMER7_CH3: DMAMUX TIMER7 CH3 request + \arg DMA_REQUEST_TIMER7_TI: DMAMUX TIMER7 TI request + \arg DMA_REQUEST_TIMER7_UP: DMAMUX TIMER7 UP request + \arg DMA_REQUEST_TIMER7_CO: DMAMUX TIMER7 CO request + \arg DMA_REQUEST_TIMER7_MCH0: DMAMUX TIMER7 MCH0 request + \arg DMA_REQUEST_TIMER7_MCH1: DMAMUX TIMER7 MCH1 request + \arg DMA_REQUEST_TIMER7_MCH2: DMAMUX TIMER7 MCH2 request + \arg DMA_REQUEST_TIMER7_MCH3: DMAMUX TIMER7 MCH3 request + \arg DMA_REQUEST_CAN1: DMAMUX CAN1 request + \arg DMA_REQUEST_CAN0: DMAMUX CAN0 request + \arg DMA_REQUEST_USART0_RX: DMAMUX USART0 RX request + \arg DMA_REQUEST_USART0_TX: DMAMUX USART0 TX request + \arg DMA_REQUEST_USART1_RX: DMAMUX USART1 RX request + \arg DMA_REQUEST_USART1_TX: DMAMUX USART1 TX request + \arg DMA_REQUEST_USART2_RX: DMAMUX USART2 RX request + \arg DMA_REQUEST_USART2_TX: DMAMUX USART2 TX request + \arg DMA_REQUEST_TIMER5_UP: DMAMUX TIMER5 UP request + \arg DMA_REQUEST_TIMER6_UP: DMAMUX TIMER6 UP request + \arg DMA_REQUEST_TIMER19_CH0: DMAMUX TIMER19 CH0 request + \arg DMA_REQUEST_TIMER19_CH1: DMAMUX TIMER19 CH1 request + \arg DMA_REQUEST_TIMER19_CH2: DMAMUX TIMER19 CH2 request + \arg DMA_REQUEST_TIMER19_CH3: DMAMUX TIMER19 CH3 request + \arg DMA_REQUEST_TIMER19_TI: DMAMUX TIMER19 TI request + \arg DMA_REQUEST_TIMER19_UP: DMAMUX TIMER19 UP request + \arg DMA_REQUEST_TIMER19_CO: DMAMUX TIMER19 CO request + \arg DMA_REQUEST_TIMER19_MCH0: DMAMUX TIMER19 MCH0 request + \arg DMA_REQUEST_TIMER19_MCH1: DMAMUX TIMER19 MCH1 request + \arg DMA_REQUEST_TIMER19_MCH2: DMAMUX TIMER19 MCH2 request + \arg DMA_REQUEST_TIMER19_MCH3: DMAMUX TIMER19 MCH3 request + \arg DMA_REQUEST_TIMER20_CH0: DMAMUX TIMER20 CH0 request + \arg DMA_REQUEST_TIMER20_CH1: DMAMUX TIMER20 CH1 request + \arg DMA_REQUEST_TIMER20_CH2: DMAMUX TIMER20 CH2 request + \arg DMA_REQUEST_TIMER20_CH3: DMAMUX TIMER20 CH3 request + \arg DMA_REQUEST_TIMER20_TI: DMAMUX TIMER20 TI request + \arg DMA_REQUEST_TIMER20_UP: DMAMUX TIMER20 UP request + \arg DMA_REQUEST_TIMER20_CO: DMAMUX TIMER20 CO request + \arg DMA_REQUEST_TIMER20_MCH0: DMAMUX TIMER20 MCH0 request + \arg DMA_REQUEST_TIMER20_MCH1: DMAMUX TIMER20 MCH1 request + \arg DMA_REQUEST_TIMER20_MCH2: DMAMUX TIMER20 MCH2 request + \arg DMA_REQUEST_TIMER20_MCH3: DMAMUX TIMER20 MCH3 request + \param[out] none + \retval none +*/ +void dmamux_request_id_config(dmamux_multiplexer_channel_enum channelx, uint32_t id) +{ + DMAMUX_RM_CHXCFG(channelx) &= ~DMAMUX_RM_CHXCFG_MUXID; + DMAMUX_RM_CHXCFG(channelx) |= id; +} + +/*! + \brief configure trigger input polarity + \param[in] channelx: specify which DMAMUX request generator channel is configured + only one parameter can be selected which is shown as below: + \arg DMAMUX_GENCHx(x=0..3) + \param[in] polarity: trigger input polarity + only one parameter can be selected which is shown as below: + \arg DMAMUX_GEN_NO_EVENT: no event detection + \arg DMAMUX_GEN_RISING: rising edge + \arg DMAMUX_GEN_FALLING: falling edge + \arg DMAMUX_GEN_RISING_FALLING: rising and falling edges + \param[out] none + \retval none +*/ +void dmamux_trigger_polarity_config(dmamux_generator_channel_enum channelx, uint32_t polarity) +{ + DMAMUX_RG_CHXCFG(channelx) &= ~DMAMUX_RG_CHXCFG_RGTP; + DMAMUX_RG_CHXCFG(channelx) |= polarity; +} + +/*! + \brief configure number of DMA requests to be generated + \param[in] channelx: specify which DMAMUX request generator channel is configured + only one parameter can be selected which is shown as below: + \arg DMAMUX_GENCHx(x=0..3) + \param[in] number: DMA requests number to be generated + only one parameter can be selected which is shown as below: + \arg 1 - 32 + \param[out] none + \retval none +*/ +void dmamux_request_generate_number_config(dmamux_generator_channel_enum channelx, uint32_t number) +{ + DMAMUX_RG_CHXCFG(channelx) &= ~DMAMUX_RG_CHXCFG_NBRG; + DMAMUX_RG_CHXCFG(channelx) |= (number - 1U); +} + +/*! + \brief configure trigger input identification + \param[in] channelx: specify which DMAMUX request generator channel is configured + only one parameter can be selected which is shown as below: + \arg DMAMUX_GENCHx(x=0..3) + \param[in] id: trigger input identification + only one parameter can be selected which is shown as below: + \arg DMAMUX_TRIGGER_EXTI0: trigger input is EXTI0 + \arg DMAMUX_TRIGGER_EXTI1: trigger input is EXTI1 + \arg DMAMUX_TRIGGER_EXTI2: trigger input is EXTI2 + \arg DMAMUX_TRIGGER_EXTI3: trigger input is EXTI3 + \arg DMAMUX_TRIGGER_EXTI4: trigger input is EXTI4 + \arg DMAMUX_TRIGGER_EXTI5: trigger input is EXTI5 + \arg DMAMUX_TRIGGER_EXTI6: trigger input is EXTI6 + \arg DMAMUX_TRIGGER_EXTI7: trigger input is EXTI7 + \arg DMAMUX_TRIGGER_EXTI8: trigger input is EXTI8 + \arg DMAMUX_TRIGGER_EXTI9: trigger input is EXTI9 + \arg DMAMUX_TRIGGER_EXTI10: trigger input is EXTI10 + \arg DMAMUX_TRIGGER_EXTI11: trigger input is EXTI11 + \arg DMAMUX_TRIGGER_EXTI12: trigger input is EXTI12 + \arg DMAMUX_TRIGGER_EXTI13: trigger input is EXTI13 + \arg DMAMUX_TRIGGER_EXTI14: trigger input is EXTI14 + \arg DMAMUX_TRIGGER_EXTI15: trigger input is EXTI15 + \arg DMAMUX_TRIGGER_EVTX_OUT0: trigger input is Evtx_out0 + \arg DMAMUX_TRIGGER_EVTX_OUT0: trigger input is Evtx_out1 + \arg DMAMUX_TRIGGER_EVTX_OUT0: trigger input is Evtx_out2 + \arg DMAMUX_TRIGGER_EVTX_OUT0: trigger input is Evtx_out3 + \arg DMAMUX_TRIGGER_TIMER20_CH0_O: trigger input is TIMER20_CH0_O + \param[out] none + \retval none +*/ +void dmamux_trigger_id_config(dmamux_generator_channel_enum channelx, uint32_t id) +{ + DMAMUX_RG_CHXCFG(channelx) &= ~DMAMUX_RG_CHXCFG_TID; + DMAMUX_RG_CHXCFG(channelx) |= id; +} + +/*! + \brief get DMAMUX flag + \param[in] flag: flag type + only one parameter can be selected which is shown as below: + \arg DMAMUX_FLAG_MUXCH0_SO: DMAMUX request multiplexer channel 0 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH1_SO: DMAMUX request multiplexer channel 1 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH2_SO: DMAMUX request multiplexer channel 2 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH3_SO: DMAMUX request multiplexer channel 3 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH4_SO: DMAMUX request multiplexer channel 4 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH5_SO: DMAMUX request multiplexer channel 5 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH6_SO: DMAMUX request multiplexer channel 6 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH7_SO: DMAMUX request multiplexer channel 7 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH8_SO: DMAMUX request multiplexer channel 8 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH9_SO: DMAMUX request multiplexer channel 9 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH10_SO: DMAMUX request multiplexer channel 10 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH11_SO: DMAMUX request multiplexer channel 11 synchronization overrun flag + \arg DMAMUX_FLAG_GENCH0_TO: DMAMUX request generator channel 0 trigger overrun flag + \arg DMAMUX_FLAG_GENCH1_TO: DMAMUX request generator channel 1 trigger overrun flag + \arg DMAMUX_FLAG_GENCH2_TO: DMAMUX request generator channel 2 trigger overrun flag + \arg DMAMUX_FLAG_GENCH3_TO: DMAMUX request generator channel 3 trigger overrun flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dmamux_flag_get(dmamux_flag_enum flag) +{ + FlagStatus reval; + + if(0U != (DMAMUX_REG_VAL(flag) & BIT(DMAMUX_BIT_POS(flag)))) { + reval = SET; + } else { + reval = RESET; + } + + return reval; +} + +/*! + \brief clear DMAMUX flag + \param[in] flag: flag type + only one parameter can be selected which is shown as below: + \arg DMAMUX_FLAG_MUXCH0_SO: DMAMUX request multiplexer channel 0 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH1_SO: DMAMUX request multiplexer channel 1 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH2_SO: DMAMUX request multiplexer channel 2 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH3_SO: DMAMUX request multiplexer channel 3 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH4_SO: DMAMUX request multiplexer channel 4 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH5_SO: DMAMUX request multiplexer channel 5 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH6_SO: DMAMUX request multiplexer channel 6 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH7_SO: DMAMUX request multiplexer channel 7 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH8_SO: DMAMUX request multiplexer channel 8 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH9_SO: DMAMUX request multiplexer channel 9 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH10_SO: DMAMUX request multiplexer channel 10 synchronization overrun flag + \arg DMAMUX_FLAG_MUXCH11_SO: DMAMUX request multiplexer channel 11 synchronization overrun flag + \arg DMAMUX_FLAG_GENCH0_TO: DMAMUX request generator channel 0 trigger overrun flag + \arg DMAMUX_FLAG_GENCH1_TO: DMAMUX request generator channel 1 trigger overrun flag + \arg DMAMUX_FLAG_GENCH2_TO: DMAMUX request generator channel 2 trigger overrun flag + \arg DMAMUX_FLAG_GENCH3_TO: DMAMUX request generator channel 3 trigger overrun flag + \param[out] none + \retval none +*/ +void dmamux_flag_clear(dmamux_flag_enum flag) +{ + DMAMUX_REG_VAL3(flag) = BIT(DMAMUX_BIT_POS(flag)); +} + +/*! + \brief enable DMAMUX interrupt + \param[in] interrupt: specify which interrupt to enable + only one parameter can be selected which is shown as below: + \arg DMAMUX_INT_MUXCH0_SO: DMAMUX request multiplexer channel 0 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH1_SO: DMAMUX request multiplexer channel 1 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH2_SO: DMAMUX request multiplexer channel 2 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH3_SO: DMAMUX request multiplexer channel 3 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH4_SO: DMAMUX request multiplexer channel 4 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH5_SO: DMAMUX request multiplexer channel 5 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH6_SO: DMAMUX request multiplexer channel 6 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH7_SO: DMAMUX request multiplexer channel 7 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH8_SO: DMAMUX request multiplexer channel 8 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH9_SO: DMAMUX request multiplexer channel 9 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH10_SO: DMAMUX request multiplexer channel 10 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH11_SO: DMAMUX request multiplexer channel 11 synchronization overrun interrupt + \arg DMAMUX_INT_GENCH0_TO: DMAMUX request generator channel 0 trigger overrun interrupt + \arg DMAMUX_INT_GENCH1_TO: DMAMUX request generator channel 1 trigger overrun interrupt + \arg DMAMUX_INT_GENCH2_TO: DMAMUX request generator channel 2 trigger overrun interrupt + \arg DMAMUX_INT_GENCH3_TO: DMAMUX request generator channel 3 trigger overrun interrupt + \param[out] none + \retval none +*/ +void dmamux_interrupt_enable(dmamux_interrupt_enum interrupt) +{ + DMAMUX_REG_VAL(interrupt) |= BIT(DMAMUX_BIT_POS(interrupt)); +} + +/*! + \brief disable DMAMUX interrupt + \param[in] interrupt: specify which interrupt to disable + only one parameter can be selected which is shown as below: + \arg DMAMUX_INT_MUXCH0_SO: DMAMUX request multiplexer channel 0 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH1_SO: DMAMUX request multiplexer channel 1 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH2_SO: DMAMUX request multiplexer channel 2 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH3_SO: DMAMUX request multiplexer channel 3 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH4_SO: DMAMUX request multiplexer channel 4 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH5_SO: DMAMUX request multiplexer channel 5 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH6_SO: DMAMUX request multiplexer channel 6 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH7_SO: DMAMUX request multiplexer channel 7 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH8_SO: DMAMUX request multiplexer channel 8 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH9_SO: DMAMUX request multiplexer channel 9 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH10_SO: DMAMUX request multiplexer channel 10 synchronization overrun interrupt + \arg DMAMUX_INT_MUXCH11_SO: DMAMUX request multiplexer channel 11 synchronization overrun interrupt + \arg DMAMUX_INT_GENCH0_TO: DMAMUX request generator channel 0 trigger overrun interrupt + \arg DMAMUX_INT_GENCH1_TO: DMAMUX request generator channel 1 trigger overrun interrupt + \arg DMAMUX_INT_GENCH2_TO: DMAMUX request generator channel 2 trigger overrun interrupt + \arg DMAMUX_INT_GENCH3_TO: DMAMUX request generator channel 3 trigger overrun interrupt + \param[out] none + \retval none +*/ +void dmamux_interrupt_disable(dmamux_interrupt_enum interrupt) +{ + DMAMUX_REG_VAL(interrupt) &= ~BIT(DMAMUX_BIT_POS(interrupt)); +} + +/*! + \brief get DMAMUX interrupt flag + \param[in] int_flag: flag type + only one parameter can be selected which is shown as below: + \arg DMAMUX_INT_FLAG_MUXCH0_SO: DMAMUX request multiplexer channel 0 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH1_SO: DMAMUX request multiplexer channel 1 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH2_SO: DMAMUX request multiplexer channel 2 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH3_SO: DMAMUX request multiplexer channel 3 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH4_SO: DMAMUX request multiplexer channel 4 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH5_SO: DMAMUX request multiplexer channel 5 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH6_SO: DMAMUX request multiplexer channel 6 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH7_SO: DMAMUX request multiplexer channel 7 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH8_SO: DMAMUX request multiplexer channel 8 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH9_SO: DMAMUX request multiplexer channel 9 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH10_SO: DMAMUX request multiplexer channel 10 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH11_SO: DMAMUX request multiplexer channel 11 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_GENCH0_TO: DMAMUX request generator channel 0 trigger overrun interrupt flag + \arg DMAMUX_INT_FLAG_GENCH1_TO: DMAMUX request generator channel 1 trigger overrun interrupt flag + \arg DMAMUX_INT_FLAG_GENCH2_TO: DMAMUX request generator channel 2 trigger overrun interrupt flag + \arg DMAMUX_INT_FLAG_GENCH3_TO: DMAMUX request generator channel 3 trigger overrun interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dmamux_interrupt_flag_get(dmamux_interrupt_flag_enum int_flag) +{ + FlagStatus reval; + uint32_t intenable = 0U, flagstatus = 0U; + + /* get the interrupt enable bit status */ + intenable = (DMAMUX_REG_VAL2(int_flag) & BIT(DMAMUX_BIT_POS2(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (DMAMUX_REG_VAL(int_flag) & BIT(DMAMUX_BIT_POS(int_flag))); + + if(flagstatus && intenable) { + reval = SET; + } else { + reval = RESET; + } + + return reval; +} + +/*! + \brief clear DMAMUX interrupt flag + \param[in] int_flag: flag type + only one parameter can be selected which is shown as below: + \arg DMAMUX_INT_FLAG_MUXCH0_SO: DMAMUX request multiplexer channel 0 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH1_SO: DMAMUX request multiplexer channel 1 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH2_SO: DMAMUX request multiplexer channel 2 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH3_SO: DMAMUX request multiplexer channel 3 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH4_SO: DMAMUX request multiplexer channel 4 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH5_SO: DMAMUX request multiplexer channel 5 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH6_SO: DMAMUX request multiplexer channel 6 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH7_SO: DMAMUX request multiplexer channel 7 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH8_SO: DMAMUX request multiplexer channel 8 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH9_SO: DMAMUX request multiplexer channel 9 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH10_SO: DMAMUX request multiplexer channel 10 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_MUXCH11_SO: DMAMUX request multiplexer channel 11 synchronization overrun interrupt flag + \arg DMAMUX_INT_FLAG_GENCH0_TO: DMAMUX request generator channel 0 trigger overrun interrupt flag + \arg DMAMUX_INT_FLAG_GENCH1_TO: DMAMUX request generator channel 1 trigger overrun interrupt flag + \arg DMAMUX_INT_FLAG_GENCH2_TO: DMAMUX request generator channel 2 trigger overrun interrupt flag + \arg DMAMUX_INT_FLAG_GENCH3_TO: DMAMUX request generator channel 3 trigger overrun interrupt flag + \param[out] none + \retval none +*/ +void dmamux_interrupt_flag_clear(dmamux_interrupt_flag_enum int_flag) +{ + DMAMUX_REG_VAL3(int_flag) = BIT(DMAMUX_BIT_POS(int_flag)); +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_exti.c b/gd32a50x/standard_peripheral/source/gd32a50x_exti.c new file mode 100644 index 0000000..42f8108 --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_exti.c @@ -0,0 +1,252 @@ +/*! + \file gd32a50x_exti.c + \brief EXTI driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_exti.h" + +/*! + \brief deinitialize the EXTI + \param[in] none + \param[out] none + \retval none +*/ +void exti_deinit(void) +{ + /* reset the value of all the EXTI registers */ + EXTI_INTEN = (uint32_t)0x00000000U; + EXTI_EVEN = (uint32_t)0x00000000U; + EXTI_RTEN = (uint32_t)0x00000000U; + EXTI_FTEN = (uint32_t)0x00000000U; + EXTI_SWIEV = (uint32_t)0x00000000U; +} + +/*! + \brief initialize the EXTI + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..24): EXTI line x + \param[in] mode: interrupt or event mode, refer to exti_mode_enum + only one parameter can be selected which is shown as below: + \arg EXTI_INTERRUPT: interrupt mode + \arg EXTI_EVENT: event mode + \param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum + only one parameter can be selected which is shown as below: + \arg EXTI_TRIG_RISING: rising edge trigger + \arg EXTI_TRIG_FALLING: falling trigger + \arg EXTI_TRIG_BOTH: rising and falling trigger + \arg EXTI_TRIG_NONE: without rising edge or falling edge trigger + \param[out] none + \retval none +*/ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type) +{ + /* reset the EXTI line x */ + EXTI_INTEN &= ~(uint32_t)linex; + EXTI_EVEN &= ~(uint32_t)linex; + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + + /* set the EXTI mode and enable the interrupts or events from EXTI line x */ + switch(mode){ + case EXTI_INTERRUPT: + EXTI_INTEN |= (uint32_t)linex; + break; + case EXTI_EVENT: + EXTI_EVEN |= (uint32_t)linex; + break; + default: + break; + } + + /* set the EXTI trigger type */ + switch(trig_type){ + case EXTI_TRIG_RISING: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + break; + case EXTI_TRIG_FALLING: + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + case EXTI_TRIG_BOTH: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + case EXTI_TRIG_NONE: + default: + break; + } +} + +/*! + \brief enable the interrupts from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..24): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_enable(exti_line_enum linex) +{ + EXTI_INTEN |= (uint32_t)linex; +} + +/*! + \brief disable the interrupt from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..24): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_disable(exti_line_enum linex) +{ + EXTI_INTEN &= ~(uint32_t)linex; +} + +/*! + \brief enable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..24): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_enable(exti_line_enum linex) +{ + EXTI_EVEN |= (uint32_t)linex; +} + +/*! + \brief disable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..24): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_disable(exti_line_enum linex) +{ + EXTI_EVEN &= ~(uint32_t)linex; +} + +/*! + \brief enable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..24): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_enable(exti_line_enum linex) +{ + EXTI_SWIEV |= (uint32_t)linex; +} + +/*! + \brief disable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..24): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_disable(exti_line_enum linex) +{ + EXTI_SWIEV &= ~(uint32_t)linex; +} + +/*! + \brief get EXTI line x pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..24): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_flag_get(exti_line_enum linex) +{ + if(0U != (EXTI_PD & (uint32_t)linex)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear EXTI line x pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..24): EXTI line x + \param[out] none + \retval none +*/ +void exti_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} + +/*! + \brief get EXTI line x flag when the interrupt flag is set + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..24): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex) +{ + uint32_t flag_left, flag_right; + + flag_left = EXTI_PD & (uint32_t)linex; + flag_right = EXTI_INTEN & (uint32_t)linex; + + if((0U != flag_left) && (0U != flag_right)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear EXTI line x pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..24): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_fmc.c b/gd32a50x/standard_peripheral/source/gd32a50x_fmc.c new file mode 100644 index 0000000..0c78d0d --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_fmc.c @@ -0,0 +1,2175 @@ +/*! + \file gd32a50x_fmc.c + \brief FMC driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_fmc.h" + +/* FMC mask */ +#define LOW_8BITS_MASK ((uint32_t)0x000000FFU) /*!< the 0-7 bits mask of a word */ +#define HIGH_8BITS_MASK ((uint32_t)0x0000FF00U) /*!< the 8-15 bits mask of a word */ +#define LOW_8BITS_MASK1 ((uint32_t)0x00FF0000U) /*!< the 16-23 bits mask of a word */ +#define HIGH_8BITS_MASK1 ((uint32_t)0xFF000000U) /*!< the 24-31 bits mask of a word */ +#define LOW_16BITS_MASK ((uint32_t)0x0000FFFFU) /*!< the 0-15 bits mask of a word */ +#define HIGH_16BITS_MASK ((uint32_t)0xFFFF0000U) /*!< the 16-31 bits mask of a word */ +#define ECCCS_FLAG_MASK ((uint32_t)0xEC000000U) /*!< flag mask in ECCCS register */ +#define ECCCS_ERROR_MASK ((uint32_t)0x00F10000U) /*!< error flag mask in ECCCS register */ + +/* FMC register bit offset */ +#define CTL_CBCMDLEN_OFFSET ((uint32_t)0x0000001DU) /*!< CBCMDLEN offset in FMC_CTL register */ +#define OBSTAT_PLEVEL_OFFSET ((uint32_t)0x00000001U) /*!< PLEVEL offset in FMC_OBSTAT register */ +#define OBSTAT_USER_OFFSET ((uint32_t)0x00000008U) /*!< USER offset in FMC_OBSTAT register */ +#define OBSTAT_DATA_OFFSET ((uint32_t)0x00000010U) /*!< DATA offset in FMC_OBSTAT register */ +#define WP1_BK1WP_OFFSET ((uint32_t)0x00000000U) /*!< BK1WP offset in FMC_WP1 register */ +#define WP1_DFWP_OFFSET ((uint32_t)0x00000008U) /*!< DFWP offset in FMC_WP1 register */ +#define WP1_EPWP_OFFSET ((uint32_t)0x00000010U) /*!< EPWP offset in FMC_WP1 register */ +#define ECCCS_REG_OFFSET ((uint32_t)0x00000004U) /*!< ECCCS register offset */ + +/* return the FMC bank0 state */ +static fmc_state_enum fmc_bank0_state_get(void); +/* return the FMC bank1 state */ +static fmc_state_enum fmc_bank1_state_get(void); +/* check FMC bank0 ready or not */ +static fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout); +/* check FMC bank1 ready or not */ +static fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout); +/* wait shared SRAM mode to be ready */ +static void fmc_sram_mode_ready_wait(uint32_t ready_flag); + +/*! + \brief unlock the main flash operation + it is better to used in pairs with fmc_lock + \param[in] none + \param[out] none + \retval none +*/ +void fmc_unlock(void) +{ + if((0U != (FMC_CTL0 & FMC_CTL0_LK))) { + /* write the FMC bank0 key */ + FMC_KEY0 = UNLOCK_KEY0; + FMC_KEY0 = UNLOCK_KEY1; + } + + if((0U != (FMC_CTL1 & FMC_CTL1_LK))) { + /* write the FMC bank1 key */ + FMC_KEY1 = UNLOCK_KEY0; + FMC_KEY1 = UNLOCK_KEY1; + } +} + +/*! + \brief unlock the main flash bank0 operation + it is better to used in pairs with fmc_bank0_lock + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank0_unlock(void) +{ + if((0U != (FMC_CTL0 & FMC_CTL0_LK))) { + /* write the FMC bank0 key */ + FMC_KEY0 = UNLOCK_KEY0; + FMC_KEY0 = UNLOCK_KEY1; + } +} + +/*! + \brief unlock the main flash bank1 operation + it is better to used in pairs with fmc_bank1_lock + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank1_unlock(void) +{ + if((0U != (FMC_CTL1 & FMC_CTL1_LK))) { + /* write the FMC bank1 key */ + FMC_KEY1 = UNLOCK_KEY0; + FMC_KEY1 = UNLOCK_KEY1; + } +} + +/*! + \brief lock the main flash operation + it is better to used in pairs with fmc_unlock after an operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_lock(void) +{ + /* set the bank0 LK bit*/ + FMC_CTL0 |= FMC_CTL0_LK; + + /* set the bank1 LK bit*/ + FMC_CTL1 |= FMC_CTL1_LK; +} + +/*! + \brief lock the main flash bank0 operation + it is better to used in pairs with fmc_bank0_unlock after an operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank0_lock(void) +{ + /* set the LK bit*/ + FMC_CTL0 |= FMC_CTL0_LK; +} + +/*! + \brief lock the main flash bank1 operation + it is better to used in pairs with fmc_bank1_unlock after an operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank1_lock(void) +{ + /* set the LK bit*/ + FMC_CTL1 |= FMC_CTL1_LK; +} + +/*! + \brief set the wait state counter value + \param[in] wscnt: wait state counter value + only one parameter can be selected which is shown as below: + \arg WS_WSCNT_0: 0 wait state added + \arg WS_WSCNT_1: 1 wait state added + \arg WS_WSCNT_2: 2 wait state added + \arg WS_WSCNT_3: 3 wait state added + \param[out] none + \retval none +*/ +void fmc_wscnt_set(uint8_t wscnt) +{ + uint32_t reg; + + reg = FMC_WS; + /* set the wait state counter value */ + reg &= ~FMC_WS_WSCNT; + FMC_WS = (reg | wscnt); +} + +/*! + \brief enable pre-fetch + \param[in] none + \param[out] none + \retval none +*/ +void fmc_prefetch_enable(void) +{ + FMC_WS |= FMC_WS_PFEN; +} + +/*! + \brief disable pre-fetch + \param[in] none + \param[out] none + \retval none +*/ +void fmc_prefetch_disable(void) +{ + FMC_WS &= ~FMC_WS_PFEN; +} + +/*! + \brief enable cache + \param[in] none + \param[out] none + \retval none +*/ +void fmc_cache_enable(void) +{ + FMC_WS |= FMC_WS_IDCEN; +} + +/*! + \brief disable cache + \param[in] none + \param[out] none + \retval none +*/ +void fmc_cache_disable(void) +{ + FMC_WS &= ~FMC_WS_IDCEN; +} + +/*! + \brief enable cache reset if cache is disabled + \param[in] none + \param[out] none + \retval none +*/ +void fmc_cache_reset_enable(void) +{ + FMC_WS |= FMC_WS_IDRST; +} + +/*! + \brief disable cache reset + \param[in] none + \param[out] none + \retval none +*/ +void fmc_cache_reset_disable(void) +{ + FMC_WS &= ~FMC_WS_IDRST; +} + +/*! + \brief flash goto power-down mode when MCU enters deepsleep mode + \param[in] none + \param[out] none + \retval none +*/ +void fmc_powerdown_mode_set(void) +{ + FMC_WS &= ~FMC_WS_SLEEP_SLP; +} + +/*! + \brief flash goto sleep mode when MCU enters deepsleep mode + \param[in] none + \param[out] none + \retval none +*/ +void fmc_sleep_mode_set(void) +{ + FMC_WS |= FMC_WS_SLEEP_SLP; +} + +/*! + \brief configure shared SRAM mode + \param[in] sram_mode: shared SRAM mode + only one parameter can be selected which is shown as below: + \arg FASTPG_SRAM_MODE: fast program SRAM mode + \arg BASIC_SRAM_MODE: basic SRAM mode + \arg EEPROM_SRAM_MODE: EEPROM SRAM mode + \param[out] none + \retval none +*/ +void fmc_sram_mode_config(fmc_sram_mode_enum sram_mode) +{ + fmc_sram_mode_enum curr_mode; + + curr_mode = fmc_sram_mode_get(); + FMC_CTL1 &= ~FMC_CTL1_SRAMCMD; + if((EEPROM_SRAM_MODE == sram_mode) && (EEPROM_SRAM_MODE != curr_mode)) { + /* set shared SRAM to EEPROM SRAM mode*/ + FMC_CTL1 |= EEPROM_SRAM_CMD; + fmc_sram_mode_ready_wait(FMC_WS_ERAMRDY); + } else if((BASIC_SRAM_MODE == sram_mode) && (BASIC_SRAM_MODE != curr_mode)) { + /* set shared SRAM to basic SRAM mode*/ + FMC_CTL1 |= BASIC_SRAM_CMD; + fmc_sram_mode_ready_wait(FMC_WS_BRAMRDY); + } else if((FASTPG_SRAM_MODE == sram_mode) && (FASTPG_SRAM_MODE != curr_mode)) { + /* set shared SRAM to fast program SRAM mode*/ + FMC_CTL1 |= FASTPG_SRAM_CMD; + fmc_sram_mode_ready_wait(FMC_WS_PRAMRDY); + } else { + /* illegal parameters */ + } +} + +/*! + \brief get shared SRAM mode + \param[in] none + \param[out] none + \retval sram_mode: shared SRAM mode + \arg NO_SRAM_MODE: SRAM mode is not configured + \arg FASTPG_SRAM_MODE: fast PG SRAM mode + \arg BASIC_SRAM_MODE: basic SRAM mode + \arg EEPROM_SRAM_MODE: EEPROM SRAM mode +*/ +fmc_sram_mode_enum fmc_sram_mode_get(void) +{ + fmc_sram_mode_enum sram_mode; + + if(0U != (FMC_WS & FMC_WS_ERAMRDY)) { + /* SRAM is in EEPROM SRAM mode*/ + sram_mode = EEPROM_SRAM_MODE; + } else if(0U != (FMC_WS & FMC_WS_BRAMRDY)) { + /* SRAM is in basic SRAM mode*/ + sram_mode = BASIC_SRAM_MODE; + } else if(0U != (FMC_WS & FMC_WS_PRAMRDY)) { + /* SRAM is in fast program SRAM mode*/ + sram_mode = FASTPG_SRAM_MODE; + } else { + sram_mode = NO_SRAM_MODE; + } + + return sram_mode; +} + +/*! + \brief check whether flash page is blank or not by check blank command + \param[in] address: start address to check + \param[in] length: the read length is 2^length double words, the flash area to be checked must be in one page and should not exceed 1KB boundary + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error +*/ +fmc_state_enum fmc_blank_check(uint32_t address, uint8_t length) +{ + fmc_state_enum fmc_state; + + if((address >= BANK0_BASE_ADDRESS) && (address < BANK1_BASE_ADDRESS)) { + /* start check blank command */ + FMC_ADDR0 = address; + FMC_CTL0 &= ~FMC_CTL0_CBCMDLEN; + FMC_CTL0 |= (uint32_t)length << CTL_CBCMDLEN_OFFSET; + FMC_CTL0 |= FMC_CTL0_CBCMD; + FMC_CTL0 |= FMC_CTL0_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the CBCMD bit */ + FMC_CTL0 &= ~FMC_CTL0_CBCMD; + } else { + /* start check blank command */ + FMC_ADDR1 = address; + FMC_CTL1 &= ~FMC_CTL1_CBCMDLEN; + FMC_CTL1 |= (uint32_t)length << CTL_CBCMDLEN_OFFSET; + FMC_CTL1 |= FMC_CTL1_CBCMD; + FMC_CTL1 |= FMC_CTL1_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the CBCMD bit */ + FMC_CTL1 &= ~FMC_CTL1_CBCMD; + } + + return fmc_state; +} + +/*! + \brief erase main flash page + \param[in] page_address: target page start address + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error +*/ +fmc_state_enum fmc_page_erase(uint32_t page_address) +{ + fmc_state_enum fmc_state = FMC_READY; + + if((page_address >= BANK0_BASE_ADDRESS) && (page_address < BANK1_BASE_ADDRESS)) { + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start page erase */ + FMC_CTL0 |= FMC_CTL0_PER; + FMC_ADDR0 = page_address; + FMC_CTL0 |= FMC_CTL0_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PER bit */ + FMC_CTL0 &= ~FMC_CTL0_PER; + } + } else { + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + if(FMC_READY == fmc_state) { + /* start page erase */ + FMC_CTL1 |= FMC_CTL1_PER; + FMC_ADDR1 = page_address; + FMC_CTL1 |= FMC_CTL1_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PER bit */ + FMC_CTL1 &= ~FMC_CTL1_PER; + } + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief erase flash bank0 + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error +*/ +fmc_state_enum fmc_bank0_mass_erase(void) +{ + fmc_state_enum fmc_state; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start chip erase */ + FMC_CTL0 |= FMC_CTL0_MER; + FMC_CTL0 |= FMC_CTL0_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the MER bit */ + FMC_CTL0 &= ~FMC_CTL0_MER; + } + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief erase flash bank1 + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error +*/ +fmc_state_enum fmc_bank1_mass_erase(void) +{ + fmc_state_enum fmc_state; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start chip erase */ + FMC_CTL1 |= FMC_CTL1_MER; + FMC_CTL1 |= FMC_CTL1_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the MER bit */ + FMC_CTL1 &= ~FMC_CTL1_MER; + } + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief erase the data flash + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error +*/ +fmc_state_enum fmc_dflash_mass_erase(void) +{ + fmc_state_enum fmc_state; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start data flash erase */ + FMC_CTL1 |= FMC_CTL1_MERDF; + FMC_CTL1 |= FMC_CTL1_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the MERDF bit */ + FMC_CTL1 &= ~FMC_CTL1_MERDF; + } + + return fmc_state; +} + +/*! + \brief erase whole chip + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error +*/ +fmc_state_enum fmc_mass_erase(void) +{ + fmc_state_enum fmc_state; + + /* mass erase flash bank0 */ + fmc_state = fmc_bank0_mass_erase(); + + /* return the bank0 abnormal state */ + if(FMC_READY != fmc_state) { + return fmc_state; + } + + /* mass erase flash bank1 */ + fmc_state = fmc_bank1_mass_erase(); + + /* return the bank1 abnormal state */ + if(FMC_READY != fmc_state) { + return fmc_state; + } + + /* mass erase data flash */ + fmc_state = fmc_dflash_mass_erase(); + + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief program a double word at the corresponding address in main flash + \param[in] address: address to program, apply to bank0, bank1 and data flash + \param[in] data: double word to program + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error +*/ +fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data) +{ + uint32_t data0, data1; + fmc_state_enum fmc_state; + + if((address >= BANK0_BASE_ADDRESS) && (address < BANK1_BASE_ADDRESS)) { + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + data0 = (uint32_t)(data & 0xFFFFFFFFU); + data1 = (uint32_t)((data >> 32U) & 0xFFFFFFFFU); + + if(FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG32(address) = data0; + REG32(address + 4U) = data1; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + } else { + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + data0 = (uint32_t)(data & 0xFFFFFFFFU); + data1 = (uint32_t)((data >> 32U) & 0xFFFFFFFFU); + + if(FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL1 |= FMC_CTL1_PG; + REG32(address) = data0; + REG32(address + 4U) = data1; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL1 &= ~FMC_CTL1_PG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief FMC fast program one row data (32 double-word) starting at the corresponding address + \param[in] address: address to program + \param[in] data: data buffer to program + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error +*/ +fmc_state_enum fmc_fast_program(uint32_t address, uint64_t data[]) +{ + uint8_t index; + fmc_state_enum fmc_state; + fmc_sram_mode_enum sram_mode; + uint8_t cache_en = 0U; + + /* get shared SRAM mode */ + sram_mode = fmc_sram_mode_get(); + + /* set shared SRAM to fast program mode */ + if(FASTPG_SRAM_MODE != sram_mode) { + fmc_sram_mode_config(FASTPG_SRAM_MODE); + } + + /* check the row (32 double-word) in flash to confirm all data in flash is all 0xFF */ + fmc_state = fmc_blank_check(address, CBCMDLEN_OF_ONE_ROW); + if(FMC_CBCMDERR == fmc_state) { + /* flash is not erased */ + return FMC_PGERR; + } + /* flush the cache if it is enabled */ + if(FMC_WS & FMC_WS_IDCEN) { + cache_en = 1U; + fmc_cache_disable(); + } + fmc_cache_reset_enable(); + fmc_cache_reset_disable(); + + if((address >= BANK0_BASE_ADDRESS) && (address < BANK1_BASE_ADDRESS)) { + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* set the FSTPG bit to start program */ + FMC_CTL0 |= FMC_CTL0_FSTPG; + + /* program the row data */ + for(index = 0U; index < DOUBLEWORD_CNT_IN_ROW; index++) { + REG32(address) = (uint32_t)(data[index] & 0x00000000FFFFFFFFU); + REG32(address + 4U) = (uint32_t)(data[index] >> 32U); + address += 8U; + } + /* set START bit to launch fast program operation to flash */ + FMC_CTL0 |= FMC_CTL0_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the FSTPG bit */ + FMC_CTL0 &= ~FMC_CTL0_FSTPG; + } + } else { + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* set the FSTPG bit to start program */ + FMC_CTL1 |= FMC_CTL1_FSTPG; + + /* program the row data */ + for(index = 0U; index < DOUBLEWORD_CNT_IN_ROW; index++) { + REG32(address) = (uint32_t)(data[index] & 0x00000000FFFFFFFFU); + REG32(address + 4U) = (uint32_t)(data[index] >> 32U); + address += 8U; + } + + /* set START bit to launch fast program operation to flash */ + FMC_CTL1 |= FMC_CTL1_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the FSTPG bit */ + FMC_CTL1 &= ~FMC_CTL1_FSTPG; + } + } + if(1U == cache_en) { + fmc_cache_enable(); + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program a double word at the corresponding address in OTP + \param[in] address: address to program + \param[in] data: double word to write + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error +*/ +fmc_state_enum otp_doubleword_program(uint32_t address, uint64_t data) +{ + uint32_t data0, data1; + fmc_state_enum fmc_state; + + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + data0 = (uint32_t)(data & 0xFFFFFFFFU); + data1 = (uint32_t)((data >> 32U) & 0xFFFFFFFFU); + + /* configure program width */ + if(FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL1 |= FMC_CTL1_PG; + REG32(address) = data0; + REG32(address + 4U) = data1; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL1 &= ~FMC_CTL1_PG; + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program a word at the corresponding address in EEPROM + \param[in] address: address to program + \param[in] data: word to write + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error +*/ +fmc_state_enum eeprom_word_program(uint32_t address, uint32_t data) +{ + fmc_sram_mode_enum sram_mode; + fmc_state_enum fmc_state; + + /* get shared SRAM mode */ + sram_mode = fmc_sram_mode_get(); + + /* set Shared SRAM to EEPROM RAM mode */ + if(EEPROM_SRAM_MODE != sram_mode) { + fmc_sram_mode_config(EEPROM_SRAM_MODE); + } + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + /* configure program width */ + if(FMC_READY == fmc_state) { + REG32(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief read a word at the corresponding address in EEPROM + \param[in] address: address to read + \param[in] none + \param[out] none + \retval word data readout +*/ +uint32_t eeprom_word_read(uint32_t address) +{ + uint32_t data; + fmc_sram_mode_enum sram_mode; + + /* get shared SRAM mode */ + sram_mode = fmc_sram_mode_get(); + + /* set shared SRAM to EEPROM RAM mode */ + if(EEPROM_SRAM_MODE != sram_mode) { + fmc_sram_mode_config(EEPROM_SRAM_MODE); + } + + data = REG32(address); + + /* return data */ + return data; +} + +/*! + \brief unlock the option bytes 0 operation + it is better to used in pairs with ob_lock + \param[in] none + \param[out] none + \retval none +*/ +void ob_unlock(void) +{ + if(0U == (FMC_CTL1 & FMC_CTL1_OBWEN)) { + /* write the FMC key */ + FMC_OBKEY = UNLOCK_KEY0; + FMC_OBKEY = UNLOCK_KEY1; + } + + /* wait until OBWEN bit is set by hardware */ + while(0U == (FMC_CTL1 & FMC_CTL1_OBWEN)) { + } +} + +/*! + \brief lock the option bytes 0 operation + it is better to used in pairs with ob_unlock after an operation + \param[in] none + \param[out] none + \retval none +*/ +void ob_lock(void) +{ + /* reset the OBWEN bit */ + FMC_CTL1 &= ~FMC_CTL1_OBWEN; +} + +/*! + \brief force to reload the option bytes 0 + \param[in] none + \param[out] none + \retval none +*/ +void ob_reset(void) +{ + /* set the OBRLD bit */ + FMC_CTL1 |= FMC_CTL1_OBRLD; +} + +/*! + \brief erase the option bytes 0 + programmer must ensure FMC & option bytes are both unlocked before calling this function + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error + \arg FMC_OB_HSPC: FMC is under high security protection +*/ +fmc_state_enum ob_erase(void) +{ + uint32_t temp_spc_user; + fmc_state_enum fmc_state; + + temp_spc_user = OB_SPC_USER; + + /* check the option bytes security protection value */ + if(OB_OBSTAT_PLEVEL_HIGH == ob_plevel_get()) { + return FMC_OB_HSPC; + } + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start erase the option bytes */ + FMC_CTL1 |= FMC_CTL1_OB0ER; + FMC_CTL1 |= FMC_CTL1_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* reset the OB0ER bit */ + FMC_CTL1 &= ~FMC_CTL1_OB0ER; + + /* set the OB0PG bit */ + FMC_CTL1 |= FMC_CTL1_OB0PG; + + /* restore the previous security protection configuration */ + OB_SPC_USER = (temp_spc_user & LOW_8BITS_MASK) | LOW_8BITS_MASK1; + OB_DATA = 0xFFFFFFFFU; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the OB0PG bit */ + FMC_CTL1 &= ~FMC_CTL1_OB0PG; + } else { + /* reset the OB0ER bit */ + FMC_CTL1 &= ~FMC_CTL1_OB0ER; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief enable option bytes 0 write protection + \param[in] wp_area: write protection area + only one parameter can be selected which is shown as below: + \arg BANK0_AREA: main flash bank0 write protection area + \arg BANK1_AREA: main flash bank1 write protection area + \arg DATA_FLASH_AREA: data flash write protection area + \arg EEPROM_AREA: EEPROM write protection area + \param[in] ob_wp: write protection configuration data. Notice that set the bit to 1 if you want to protect + the corresponding pages. The lowest 8 bits is valid in area except bank0. + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error + \arg FMC_OB_HSPC: FMC is under high security protection +*/ +fmc_state_enum ob_write_protection_enable(fmc_area_enum wp_area, uint32_t ob_wp) +{ + uint32_t i; + uint32_t op_byte[OB_WORD_CNT] = {0U}; + fmc_state_enum fmc_state; + + /* check the option bytes security protection value */ + if(OB_OBSTAT_PLEVEL_HIGH == ob_plevel_get()) { + return FMC_OB_HSPC; + } + + /* read option bytes */ + for(i = 0U; i < OB_WORD_CNT; i++) { + op_byte[i] = OP_BYTE(i); + } + + ob_wp = (uint32_t)(~ob_wp); + if(BANK0_AREA == wp_area) { + /* configure write protection to main flash bank0 area */ + op_byte[2] &= (ob_wp & LOW_8BITS_MASK) | ((ob_wp & HIGH_8BITS_MASK) << 8); + op_byte[3] &= ((ob_wp & LOW_8BITS_MASK1) >> 16) | ((ob_wp & HIGH_8BITS_MASK1) >> 8); + } else if(BANK1_AREA == wp_area) { + /* configure write protection to main flash bank1 area */ + op_byte[4] &= (uint32_t)((ob_wp & LOW_8BITS_MASK) | HIGH_16BITS_MASK); + } else if(DATA_FLASH_AREA == wp_area) { + /* configure write protection to data flash area */ + op_byte[4] &= (uint32_t)(((ob_wp & LOW_8BITS_MASK) << 16U) | LOW_16BITS_MASK); + } else if(EEPROM_AREA == wp_area) { + /* configure write protection to EEPROM area */ + op_byte[5] &= (uint32_t)(ob_wp & LOW_8BITS_MASK); + } else { + /* illegal parameters */ + } + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start erase the option bytes */ + FMC_CTL1 |= FMC_CTL1_OB0ER; + FMC_CTL1 |= FMC_CTL1_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* reset the OB0ER bit */ + FMC_CTL1 &= ~FMC_CTL1_OB0ER; + + /* enable the option bytes programming */ + FMC_CTL1 |= FMC_CTL1_OB0PG; + + /* write option bytes */ + for(i = 0U; i < OB_DOUBLEWORD_CNT; i++) { + OP_BYTE(i * 2U) = op_byte[i * 2U]; + OP_BYTE(i * 2U + 1U) = op_byte[i * 2U + 1U]; + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + if(FMC_READY != fmc_state) { + break; + } + } + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the OB0PG bit */ + FMC_CTL1 &= ~FMC_CTL1_OB0PG; + } else { + /* reset the OB0ER bit */ + FMC_CTL1 &= ~FMC_CTL1_OB0ER; + } + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief configure security protection + \param[in] ob_spc: specify security protection code + only one parameter can be selected which is shown as below: + \arg FMC_NSPC: no security protection + \arg FMC_LSPC: low security protection + \arg FMC_HSPC: high security protection + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error + \arg FMC_OB_HSPC: FMC is under high security protection +*/ +fmc_state_enum ob_security_protection_config(uint16_t ob_spc) +{ + uint32_t i; + uint32_t op_byte[OB_WORD_CNT] = {0U}; + fmc_state_enum fmc_state; + + /* check the option bytes security protection value */ + if(OB_OBSTAT_PLEVEL_HIGH == ob_plevel_get()) { + return FMC_OB_HSPC; + } + /* read option bytes */ + for(i = 0U; i < OB_WORD_CNT; i++) { + op_byte[i] = OP_BYTE(i); + } + + op_byte[0] = ((uint32_t)(ob_spc)) | ((op_byte[0] & HIGH_16BITS_MASK)); + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start erase the option bytes */ + FMC_CTL1 |= FMC_CTL1_OB0ER; + FMC_CTL1 |= FMC_CTL1_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + + /* reset the OB0ER bit */ + FMC_CTL1 &= ~FMC_CTL1_OB0ER; + + /* enable the option bytes programming */ + FMC_CTL1 |= FMC_CTL1_OB0PG; + + /* write option bytes */ + for(i = 0U; i < OB_DOUBLEWORD_CNT; i++) { + OP_BYTE(i * 2U) = op_byte[i * 2U]; + OP_BYTE(i * 2U + 1U) = op_byte[i * 2U + 1U]; + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + if(FMC_READY != fmc_state) { + break; + } + } + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the OB0PG bit */ + FMC_CTL1 &= ~FMC_CTL1_OB0PG; + } else { + /* reset the OB0ER bit */ + FMC_CTL1 &= ~FMC_CTL1_OB0ER; + } + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program the FMC user option bytes 0 + programmer must ensure FMC & option bytes are both unlocked before calling this function + this function can only clear the corresponding bits to be 0 rather than 1. + the function ob_erase is used to set all the bits to be 1. + \param[in] ob_user: user option bytes + one or more (bitwise OR) parameters can be selected which are shown as below: + \arg OB_FWDGT_HW/OB_FWDGT_SW: free watchdog mode + \arg OB_DEEPSLEEP_RST/OB_DEEPSLEEP_NRST: generate a reset or enter deep-sleep mode + \arg OB_STDBY_RST/OB_STDBY_NRST: generate a reset or enter standby mode + \arg OB_BOOT_FROM_BANK1/OB_BOOT_FROM_BANK0: boot mdoe + \arg OB_BOOT_OTA_ENABLE/OB_BOOT_OTA_DISABLE: OTA mdoe + \arg OB_BOR_DISABLE/OB_BOR_ENABLE: BOR on/off + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error + \arg FMC_OB_HSPC: FMC is under high security protection +*/ +fmc_state_enum ob_user_write(uint16_t ob_user) +{ + uint32_t i; + uint32_t op_byte[OB_WORD_CNT] = {0U}; + uint8_t ob_user_0, ob_user_1, ob_user_temp; + + /* check the option bytes security protection value */ + if(OB_OBSTAT_PLEVEL_HIGH == ob_plevel_get()) { + return FMC_OB_HSPC; + } + + ob_user_0 = (uint8_t)(ob_user >> 8U); + ob_user_1 = (uint8_t)(ob_user & 0xFFU); + + /* read option bytes */ + for(i = 0U; i < OB_WORD_CNT; i++) { + op_byte[i] = OP_BYTE(i); + } + + ob_user_temp = (uint8_t)(op_byte[0] >> 16U); + ob_user_temp |= ob_user_1; + ob_user_temp &= (uint8_t)(~ob_user_0); + + op_byte[0] = ((uint32_t)ob_user_temp << 16U) | ((op_byte[0] & LOW_16BITS_MASK)); + + /* check whether FMC is ready or not */ + fmc_state_enum fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start erase the option bytes */ + FMC_CTL1 |= FMC_CTL1_OB0ER; + FMC_CTL1 |= FMC_CTL1_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + + /* reset the OB0ER bit */ + FMC_CTL1 &= ~FMC_CTL1_OB0ER; + + /* enable the option bytes programming */ + FMC_CTL1 |= FMC_CTL1_OB0PG; + + /* write option bytes */ + for(i = 0U; i < OB_DOUBLEWORD_CNT; i++) { + OP_BYTE(i * 2U) = op_byte[i * 2U]; + OP_BYTE(i * 2U + 1U) = op_byte[i * 2U + 1U]; + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + if(FMC_READY != fmc_state) { + break; + } + } + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the OB0PG bit */ + FMC_CTL1 &= ~FMC_CTL1_OB0PG; + } else { + /* reset the OB0ER bit */ + FMC_CTL1 &= ~FMC_CTL1_OB0ER; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program the FMC data option bytes 0 + programmer must ensure FMC & option bytes are both unlocked before calling this function + \param[in] ob_data: the data to be programmed, OB_DATA[0:15] + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error + \arg FMC_OB_HSPC: FMC is under high security protection +*/ +fmc_state_enum ob_data_program(uint16_t ob_data) +{ + uint32_t i; + uint32_t val; + uint32_t op_byte[OB_WORD_CNT] = {0U}; + fmc_state_enum fmc_state = FMC_READY; + + val = OB_SPC; + /* check the option bytes security protection value */ + if(OB_OBSTAT_PLEVEL_HIGH == ob_plevel_get()) { + return FMC_OB_HSPC; + } + + /* read option bytes */ + for(i = 0U; i < OB_WORD_CNT; i++) { + op_byte[i] = OP_BYTE(i); + } + + val = (uint32_t)(ob_data & LOW_8BITS_MASK); + val |= ((uint32_t)ob_data & HIGH_8BITS_MASK) << 8U; + op_byte[1] = val; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start erase the option bytes */ + FMC_CTL1 |= FMC_CTL1_OB0ER; + FMC_CTL1 |= FMC_CTL1_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* reset the OB0ER bit */ + FMC_CTL1 &= ~FMC_CTL1_OB0ER; + /* set the OB0PG bit */ + FMC_CTL1 |= FMC_CTL1_OB0PG; + + /* write option bytes */ + for(i = 0U; i < OB_DOUBLEWORD_CNT; i++) { + OP_BYTE(i * 2U) = op_byte[i * 2U]; + OP_BYTE(i * 2U + 1U) = op_byte[i * 2U + 1U]; + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + if(FMC_READY != fmc_state) { + break; + } + } + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the OB0PG bit */ + FMC_CTL1 &= ~FMC_CTL1_OB0PG; + } else { + /* reset the OB0ER bit */ + FMC_CTL1 &= ~FMC_CTL1_OB0ER; + } + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get the value of FMC option bytes OB_USER in FMC_OBSTAT register + \param[in] none + \param[out] none + \retval the option bytes USER value +*/ +uint8_t ob_user_get(void) +{ + return (uint8_t)((FMC_OBSTAT & FMC_OBSTAT_USER) >> OBSTAT_USER_OFFSET); +} + +/*! + \brief get the value of FMC option bytes OB_DATA in FMC_OBSTAT register + \param[in] none + \param[out] none + \retval the option bytes DATA value +*/ +uint16_t ob_data_get(void) +{ + return (uint16_t)((FMC_OBSTAT & FMC_OBSTAT_DATA) >> OBSTAT_DATA_OFFSET); +} + +/*! + \brief get the value of FMC option bytes BK0WP in FMC_WP0 register + \param[in] none + \param[out] none + \retval the option bytes BK0WP value +*/ +uint32_t ob_write_protection_get(void) +{ + return (uint32_t)(FMC_WP0); +} + +/*! + \brief get the value of FMC option bytes BK1WP in FMC_WP1 register + \param[in] none + \param[out] none + \retval the option bytes BK1WP value +*/ +uint8_t ob_bk1_write_protection_get(void) +{ + return (uint8_t)((FMC_WP1 & FMC_WP1_BK1WP) >> WP1_BK1WP_OFFSET); +} + +/*! + \brief get the value of FMC option bytes DFWP in FMC_WP1 register + \param[in] none + \param[out] none + \retval the option bytes DFWP value +*/ +uint8_t ob_df_write_protection_get(void) +{ + return (uint8_t)((FMC_WP1 & FMC_WP1_DFWP) >> WP1_DFWP_OFFSET); +} + +/*! + \brief get the value of FMC option bytes EPWP in FMC_WP1 register + \param[in] none + \param[out] none + \retval the option bytes EPWP value +*/ +uint8_t ob_ep_write_protection_get(void) +{ + return (uint8_t)((FMC_WP1 & FMC_WP1_EPWP) >> WP1_EPWP_OFFSET); +} + +/*! + \brief get the value of FMC option bytes 0 security protection level (PLEVEL) in FMC_OBSTAT register + \param[in] none + \param[out] none + \retval the value of PLEVEL + \arg OB_OBSTAT_PLEVEL_NO: no security protection + \arg OB_OBSTAT_PLEVEL_LOW: low security protection + \arg OB_OBSTAT_PLEVEL_HIGH: high security protection +*/ +uint8_t ob_plevel_get(void) +{ + return (uint8_t)((FMC_OBSTAT & FMC_OBSTAT_PLEVEL) >> OBSTAT_PLEVEL_OFFSET); +} + +/*! + \brief configure lock value in option bytes 1 + programmer must ensure FMC & option bytes are both unlocked before calling this function + \param[in] lk_value: the LK value to be programmed (OB1_LK_VALUE) + only one parameter can be selected which is shown as below: + \arg OB1CS_OB1_LK: when configured as OB1CS_OB1_LK, the option bytes 1 cannot be modified any more + \arg OB1CS_OB1_NOT_LK: option bytes 1 is not locked + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error + \arg FMC_OB1_LK: option bytes 1 is locked +*/ +fmc_state_enum ob1_lock_config(uint32_t lk_value) +{ + uint32_t reg; + + /* check the option bytes 1 lock status */ + if(0U != (FMC_OB1CS & FMC_OB1CS_OB1LK)) { + return FMC_OB1_LK; + } + + reg = FMC_OB1CS; + reg &= ~FMC_OB1CS_LKVAL; + reg |= lk_value; + + /* wait for the FMC ready */ + fmc_state_enum fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* write the value to LKVAL in FMC_OB1CS register */ + FMC_OB1CS = reg; + + /* set the OB1START bit */ + FMC_OB1CS |= FMC_OB1CS_OB1START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief configure the EPLOAD value of option bytes 1 loaded after the system reset + programmer must ensure FMC & option bytes are both unlocked before calling this function + \param[in] epload: EPLOAD value to be programmed + only one parameter can be selected which is shown as below: + \arg OB1CS_EPLOAD_NOT_LOAD_EPDATA: shared SRAM is not loaded with valid EEPROM data during FMC reset + \arg OB1CS_EPLOAD_LOAD_EPDATA: shared SRAM is loaded with valid EEPROM data during FMC reset + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error + \arg FMC_OB1_LK: option bytes 1 is locked +*/ +fmc_state_enum ob1_epload_config(uint32_t epload) +{ + uint32_t reg; + fmc_state_enum fmc_state = FMC_READY; + + /* check the option bytes 1 lock status */ + if(0U != (FMC_OB1CS & FMC_OB1CS_OB1LK)) { + return FMC_OB1_LK; + } + + reg = FMC_OB1CS; + reg &= ~FMC_OB1CS_EPLOAD; + reg |= epload; + + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* write the value to EPLOAD in FMC_OB1CS register */ + FMC_OB1CS = reg; + + /* set the OB1START bit */ + FMC_OB1CS |= FMC_OB1CS_OB1START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the OB1START bit */ + FMC_OB1CS &= ~FMC_OB1CS_OB1START; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief configure option bytes 1 EEPROM parameters + programmer must ensure FMC & option bytes are both unlocked before calling this function + \param[in] efalc: EFALC value to be programmed + only one parameter can be selected which is shown as below: + \arg OB1CS_DF_64K_EF_0K: data flash size is 64KB, EEPROM backup size is 0KB + \arg OB1CS_DF_48K_EF_16K: data flash size is 48KB, EEPROM backup size is 16KB + \arg OB1CS_DF_32K_EF_32K: data flash size is 32KB, EEPROM backup size is 32KB + \arg OB1CS_DF_16K_EF_48K: data flash size is 16KB, EEPROM backup size is 48KB + \arg OB1CS_DF_0K_EF_64K: data flash size is 0KB, EEPROM backup size is 64KB + \arg OB1CS_DF_EF_INVALID: data flash and EEPROM backup are invalid + \arg OB1CS_DF_32K_EF_0K: data flash size is 32KB, EEPROM backup size is 0KB + \arg OB1CS_DF_8K_EF_24K: data flash size is 8KB, EEPROM backup size is 24KB + \arg OB1CS_DF_0K_EF_32K: data flash size is 0KB, EEPROM backup size is 32KB + \arg OB1CS_DF_16K_EF_16K: data flash size is 16KB, EEPROM backup size is 16KB + \arg OB1CS_DF_24K_EF_8K: data flash size is 24KB, EEPROM backup size is 8KB + \arg OB1CS_DF_16K_EF_0K: data flash size is 16KB, EEPROM backup size is 0KB + \arg OB1CS_DF_4K_EF_12K: data flash size is 4KB, EEPROM backup size is 12KB + \arg OB1CS_DF_0K_EF_16K: data flash size is 0KB, EEPROM backup size is 16KB + \arg OB1CS_DF_8K_EF_8K: data flash size is 8KB, EEPROM backup size is 8KB + \arg OB1CS_DF_12K_EF_4K: data flash size is 12KB, EEPROM backup size is 4KB + \param[in] epsize: EPSIZE value to be programmed + only one parameter can be selected which is shown as below: + \arg OB1CS_EPSIZE_NONE: no EEPROM + \arg OB1CS_EPSIZE_4K: 4KB EEPROM + \arg OB1CS_EPSIZE_2K: 2KB EEPROM + \arg OB1CS_EPSIZE_1K: 1KB EEPROM + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error + \arg FMC_OB1_LK: option bytes 1 is locked +*/ +fmc_state_enum ob1_eeprom_parameter_config(uint32_t efalc, uint32_t epsize) +{ + uint32_t reg; + fmc_state_enum fmc_state; + + /* check the option bytes security protection value */ + if(0U != (FMC_OB1CS & FMC_OB1CS_OB1LK)) { + return FMC_OB1_LK; + } + /* configure the EFALC and EPSIZE */ + reg = FMC_OB1CS; + reg &= ~FMC_OB1CS_EFALC; + reg |= efalc; + reg &= ~FMC_OB1CS_EPSIZE; + reg |= epsize; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* write the value to EPSIZE and EFALC in FMC_OB1CS register */ + FMC_OB1CS = reg; + + /* set the OB1START bit */ + FMC_OB1CS |= FMC_OB1CS_OB1START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the OB1START bit */ + FMC_OB1CS &= ~FMC_OB1CS_OB1START; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get data flash size in byte unit + \param[in] none + \param[out] none + \retval data flash byte count +*/ +uint32_t dflash_size_get(void) +{ + uint32_t efalc_value; + uint32_t dflash_size = 0U; + + /* get EFALC value in option bytes 1 */ + efalc_value = FMC_OB1CS & FMC_OB1CS_EFALC; + + switch(efalc_value) { + case OB1CS_DF_64K_EF_0K: + dflash_size = 64U * 0x400U; + break; + case OB1CS_DF_48K_EF_16K: + dflash_size = 48U * 0x400U; + break; + case OB1CS_DF_32K_EF_32K: + dflash_size = 32U * 0x400U; + break; + case OB1CS_DF_16K_EF_48K: + dflash_size = 16U * 0x400U; + break; + case OB1CS_DF_0K_EF_64K: + dflash_size = 0x00000000U; + break; + case OB1CS_DF_EF_INVALID: + dflash_size = 0x00000000U; + break; + case OB1CS_DF_32K_EF_0K: + dflash_size = 32U * 0x400U; + break; + case OB1CS_DF_8K_EF_24K: + dflash_size = 8U * 0x400U; + break; + case OB1CS_DF_0K_EF_32K: + dflash_size = 0x00000000U; + break; + case OB1CS_DF_16K_EF_16K: + dflash_size = 16U * 0x400U; + break; + case OB1CS_DF_24K_EF_8K: + dflash_size = 24U * 0x400U; + break; + case OB1CS_DF_16K_EF_0K: + dflash_size = 16U * 0x400U; + break; + case OB1CS_DF_4K_EF_12K: + dflash_size = 4U * 0x400U; + break; + case OB1CS_DF_0K_EF_16K: + dflash_size = 0x00000000U; + break; + case OB1CS_DF_8K_EF_8K: + dflash_size = 8U * 0x400U; + break; + case OB1CS_DF_12K_EF_4K: + dflash_size = 12U * 0x400U; + break; + default: + break; + } + + return dflash_size; +} + +/*! + \brief get EEPROM backup size in byte unit + \param[in] none + \param[out] none + \retval EEPROM backup byte count +*/ +uint32_t eeprom_backup_size_get(void) +{ + uint32_t efalc_value; + uint32_t eeprom_backup_size = 0U; + + /* get EFALC value in option bytes 1 */ + efalc_value = FMC_OB1CS & FMC_OB1CS_EFALC; + + switch(efalc_value) { + case OB1CS_DF_64K_EF_0K: + eeprom_backup_size = 0x00000000U; + break; + case OB1CS_DF_48K_EF_16K: + eeprom_backup_size = 16U * 0x400U; + break; + case OB1CS_DF_32K_EF_32K: + eeprom_backup_size = 32U * 0x400U; + break; + case OB1CS_DF_16K_EF_48K: + eeprom_backup_size = 48U * 0x400U; + break; + case OB1CS_DF_0K_EF_64K: + eeprom_backup_size = 64U * 0x400U; + break; + case OB1CS_DF_EF_INVALID: + eeprom_backup_size = 0x00000000U; + break; + case OB1CS_DF_32K_EF_0K: + eeprom_backup_size = 0x00000000U; + break; + case OB1CS_DF_8K_EF_24K: + eeprom_backup_size = 24U * 0x400U; + break; + case OB1CS_DF_0K_EF_32K: + eeprom_backup_size = 0x00000000U; + break; + case OB1CS_DF_16K_EF_16K: + eeprom_backup_size = 16U * 0x400U; + break; + case OB1CS_DF_24K_EF_8K: + eeprom_backup_size = 8U * 0x400U; + break; + case OB1CS_DF_16K_EF_0K: + eeprom_backup_size = 0x00000000U; + break; + case OB1CS_DF_4K_EF_12K: + eeprom_backup_size = 12U * 0x400U; + break; + case OB1CS_DF_0K_EF_16K: + eeprom_backup_size = 16U * 0x400U; + break; + case OB1CS_DF_8K_EF_8K: + eeprom_backup_size = 8U * 0x400U; + break; + case OB1CS_DF_12K_EF_4K: + eeprom_backup_size = 4U * 0x400U; + break; + default: + break; + } + + return eeprom_backup_size; +} + +/*! + \brief get EEPROM size in byte unit + \param[in] none + \param[out] none + \retval EEPROM byte count +*/ +uint32_t eeprom_size_get(void) +{ + uint32_t epsize_value; + uint32_t eeprom_size = 0U; + + /* get EPSIZE value in option bytes 1 */ + epsize_value = FMC_OB1CS & FMC_OB1CS_EPSIZE; + + switch(epsize_value) { + case OB1CS_EPSIZE_NONE: + eeprom_size = 0x000000000U; + break; + case OB1CS_EPSIZE_4K: + eeprom_size = 4U * 0x400U; + break; + case OB1CS_EPSIZE_2K: + eeprom_size = 2U * 0x400U; + break; + case OB1CS_EPSIZE_1K: + eeprom_size = 0x400U; + break; + default: + break; + } + + return eeprom_size; +} + +/*! + \brief get FMC flag status + \param[in] flag: FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_BANK0_FLAG_BUSY: flash bank0 busy flag + \arg FMC_BANK0_FLAG_PGSERR: flash bank0 program sequence error flag + \arg FMC_BANK0_FLAG_PGERR: flash bank0 program error flag + \arg FMC_BANK0_FLAG_PGAERR: flash bank0 program alignment error flag + \arg FMC_BANK0_FLAG_WPERR: flash bank0 erase/program protection error flag + \arg FMC_BANK0_FLAG_END: flash bank0 end of operation flag + \arg FMC_BANK0_FLAG_CBCMDERR: flash bank0 checked area by the check blank command is all 0xFF or not flag + \arg FMC_BANK0_FLAG_RSTERR: flash bank0 BOR/POR or system reset during erase/program flag + \arg FMC_BANK1_FLAG_BUSY: flash bank1 busy flag + \arg FMC_BANK1_FLAG_PGSERR: flash bank1 program sequence error flag + \arg FMC_BANK1_FLAG_PGERR: flash bank1 program error flag + \arg FMC_BANK1_FLAG_PGAERR: flash bank1 program alignment error flag + \arg FMC_BANK1_FLAG_WPERR: flash bank1 erase/program protection error flag + \arg FMC_BANK1_FLAG_END: flash bank1 end of operation flag + \arg FMC_BANK1_FLAG_CBCMDERR: flash bank1 checked area by the check blank command is all 0xFF or not flag + \arg FMC_BANK1_FLAG_RSTERR: flash bank1 BOR/POR or system reset during erase/program flag + \arg FMC_FLAG_BK0ECC: an ECC bit error is detected in bank 0 flag + \arg FMC_FLAG_OB0ECC: an ECC bit error is detected in option byte 0 flag + \arg FMC_FLAG_BK1ECC: an ECC bit error is detected in bank 1 flag + \arg FMC_FLAG_SYSECC: an ECC bit error is detected in system memory flag + \arg FMC_FLAG_DFECC: an ECC bit error is detected in data flash flag + \arg FMC_FLAG_OTPECC: an ECC bit error is detected in OTP flag + \arg FMC_FLAG_OB1ECCDET: option bytes 1 two bit error detect flag + \arg FMC_FLAG_OB0ECCDET: option bytes 0 two bit error detect flag + \arg FMC_FLAG_EPECCDET: EEPROM two bits error detect flag + \arg FMC_FLAG_ECCCOR: one bit error detected and correct flag + \arg FMC_FLAG_ECCDET: OTP/data flash/system memory/bank1 two bit error detect flag + \arg FMC_FLAG_OBERR: option bytes 0 error flag + \arg FMC_FLAG_OB1ERR: option bytes 1 read error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_flag_get(fmc_flag_enum flag) +{ + /* check if an ECC bit error is detected in bank 0 */ + if(FMC_FLAG_BK0ECC == flag) { + if(0U != (FMC_REG_VAL(flag) & ECCCS_ERROR_MASK)) { + return RESET; + } else { + return SET; + } + } else { + /* get other flag */ + if(0U != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } + } +} + +/*! + \brief clear FMC flag status + \param[in] flag: FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_BANK0_FLAG_PGSERR: flash bank0 program sequence error flag + \arg FMC_BANK0_FLAG_PGERR: flash bank0 program error flag + \arg FMC_BANK0_FLAG_PGAERR: flash bank0 program alignment error flag + \arg FMC_BANK0_FLAG_WPERR: flash bank0 erase/program protection error flag + \arg FMC_BANK0_FLAG_END: flash bank0 end of operation flag + \arg FMC_BANK0_FLAG_CBCMDERR: flash bank0 checked area by the check blank command is all 0xFF or not flag + \arg FMC_BANK0_FLAG_RSTERR: flash bank0 BOR/POR or system reset during erase/program flag + \arg FMC_BANK1_FLAG_PGSERR: flash bank1 program sequence error flag + \arg FMC_BANK1_FLAG_PGERR: flash bank1 program error flag + \arg FMC_BANK1_FLAG_PGAERR: flash bank1 program alignment error flag + \arg FMC_BANK1_FLAG_WPERR: flash bank1 erase/program protection error flag + \arg FMC_BANK1_FLAG_END: flash bank1 end of operation flag + \arg FMC_BANK1_FLAG_CBCMDERR: flash bank1 checked area by the check blank command is all 0xFF or not flag + \arg FMC_BANK1_FLAG_RSTERR: flash bank1 BOR/POR or system reset during erase/program flag + \arg FMC_FLAG_OB1ECCDET: option bytes 1 two bit error detect flag + \arg FMC_FLAG_OB0ECCDET: option bytes 0 two bit error detect flag + \arg FMC_FLAG_EPECCDET: EEPROM two bits error detect flag + \arg FMC_FLAG_ECCCOR: one bit error detected and correct flag + \arg FMC_FLAG_ECCDET: OTP/data flash/system memory/bank1 two bit error detect flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +void fmc_flag_clear(fmc_flag_enum flag) +{ + uint32_t reg_offset, reg; + + reg_offset = ((uint32_t)(flag) & 0x0000FFFFU) >> 6U; + /* clear the flags in ECCCS register */ + if(ECCCS_REG_OFFSET == reg_offset) { + reg = FMC_REG_VAL(flag); + reg &= ~ECCCS_FLAG_MASK; + reg |= BIT(FMC_BIT_POS(flag)); + FMC_REG_VAL(flag) = reg; + } else { + /* clear the flags in STAT0/STAT1 register */ + FMC_REG_VAL(flag) = BIT(FMC_BIT_POS(flag)); + } +} + +/*! + \brief enable FMC interrupt + \param[in] interrupt: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_BANK0_INT_ERR: FMC bank0 error interrupt + \arg FMC_BANK0_INT_END: FMC bank0 end of operation interrupt + \arg FMC_BANK1_INT_ERR: FMC bank1 error interrupt + \arg FMC_BANK1_INT_END: FMC bank1 end of operation interrupt + \arg FMC_INT_ECCCOR: FMC one bit error correct interrupt + \arg FMC_INT_ECCDET: FMC two bits error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_enable(fmc_interrupt_enum interrupt) +{ + uint32_t reg_offset, reg; + + reg_offset = ((uint32_t)(interrupt) & 0x0000FFFFU) >> 6U; + /* enable interrupt in ECCCS register */ + if(ECCCS_REG_OFFSET == reg_offset) { + reg = FMC_REG_VAL(interrupt); + reg &= ~ECCCS_FLAG_MASK; + reg |= BIT(FMC_BIT_POS(interrupt)); + FMC_REG_VAL(interrupt) = reg; + } else { + /* enable interrupt in CTL0/CTL1 register */ + FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt)); + } +} + +/*! + \brief disable FMC interrupt + \param[in] interrupt: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_BANK0_INT_ERR: FMC bank0 error interrupt + \arg FMC_BANK0_INT_END: FMC bank0 end of operation interrupt + \arg FMC_BANK1_INT_ERR: FMC bank1 error interrupt + \arg FMC_BANK1_INT_END: FMC bank1 end of operation interrupt + \arg FMC_INT_ECCCOR: FMC one bit error correct interrupt + \arg FMC_INT_ECCDET: FMC two bits error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_disable(fmc_interrupt_enum interrupt) +{ + uint32_t reg_offset, reg; + + reg_offset = ((uint32_t)(interrupt) & 0x0000FFFFU) >> 6U; + /* disable interrupt in ECCCS register */ + if(ECCCS_REG_OFFSET == reg_offset) { + reg = FMC_REG_VAL(interrupt); + reg &= ~ECCCS_FLAG_MASK; + reg &= ~BIT(FMC_BIT_POS(interrupt)); + FMC_REG_VAL(interrupt) = reg; + } else { + /* disable interrupt in CTL0/CTL1 register */ + FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt)); + } +} + +/*! + \brief get FMC interrupt flag status + \param[in] flag: FMC interrupt flag + only one parameter can be selected which is shown as below: + \arg FMC_BANK0_INT_FLAG_PGSERR: flash bank0 program sequence error intrrupt flag + \arg FMC_BANK0_INT_FLAG_PGERR: flash bank0 program error intrrupt flag + \arg FMC_BANK0_INT_FLAG_PGAERR: flash bank0 program alignment error intrrupt flag + \arg FMC_BANK0_INT_FLAG_WPERR: flash bank0 erase/program protection error intrrupt flag + \arg FMC_BANK0_INT_FLAG_END: flash bank0 end of operation intrrupt flag + \arg FMC_BANK0_INT_FLAG_CBCMDERR: flash bank0 checked area by the check blank command is all 0xFF or not intrrupt flag + \arg FMC_BANK0_INT_FLAG_RSTERR: flash bank0 BOR/POR or system reset during erase/program intrrupt flag + \arg FMC_BANK1_INT_FLAG_PGSERR: flash bank1 program sequence error intrrupt flag + \arg FMC_BANK1_INT_FLAG_PGERR: flash bank1 program error intrrupt flag + \arg FMC_BANK1_INT_FLAG_PGAERR: flash bank1 program alignment error intrrupt flag + \arg FMC_BANK1_INT_FLAG_WPERR: flash bank1 erase/program protection error intrrupt flag + \arg FMC_BANK1_INT_FLAG_END: flash bank1 end of operation intrrupt flag + \arg FMC_BANK1_INT_FLAG_CBCMDERR: flash bank1 checked area by the check blank command is all 0xFF or not intrrupt flag + \arg FMC_BANK1_INT_FLAG_RSTERR: flash bank1 BOR/POR or system reset during erase/program intrrupt flag + \arg FMC_INT_FLAG_OB1ECCDET: option bytes 1 two bit error detect intrrupt flag + \arg FMC_INT_FLAG_OB0ECCDET: option bytes 0 two bit error detect intrrupt flag + \arg FMC_INT_FLAG_EPECCDET: EEPROM two bits error detect intrrupt flag + \arg FMC_INT_FLAG_ECCCOR: one bit error detected and correct intrrupt flag + \arg FMC_INT_FLAG_ECCDET: OTP/data flash/system memory/bank1 two bit error detect intrrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U; + /* get the interrupt enable bit status */ + intenable = (FMC_REG_VAL(int_flag) & BIT(FMC_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (FMC_REG_VAL2(int_flag) & BIT(FMC_BIT_POS2(int_flag))); + + if(flagstatus && intenable) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear FMC interrupt flag status + \param[in] flag: FMC interrupt flag + only one parameter can be selected which is shown as below: + \arg FMC_BANK0_INT_FLAG_PGSERR: flash bank0 program sequence error intrrupt flag + \arg FMC_BANK0_INT_FLAG_PGERR: flash bank0 program error intrrupt flag + \arg FMC_BANK0_INT_FLAG_PGAERR: flash bank0 program alignment error intrrupt flag + \arg FMC_BANK0_INT_FLAG_WPERR: flash bank0 erase/program protection error intrrupt flag + \arg FMC_BANK0_INT_FLAG_END: flash bank0 end of operation intrrupt flag + \arg FMC_BANK0_INT_FLAG_CBCMDERR: flash bank0 checked area by the check blank command is all 0xFF or not intrrupt flag + \arg FMC_BANK0_INT_FLAG_RSTERR: flash bank0 BOR/POR or system reset during erase/program intrrupt flag + \arg FMC_BANK1_INT_FLAG_PGSERR: flash bank1 program sequence error intrrupt flag + \arg FMC_BANK1_INT_FLAG_PGERR: flash bank1 program error intrrupt flag + \arg FMC_BANK1_INT_FLAG_PGAERR: flash bank1 program alignment error intrrupt flag + \arg FMC_BANK1_INT_FLAG_WPERR: flash bank1 erase/program protection error intrrupt flag + \arg FMC_BANK1_INT_FLAG_END: flash bank1 end of operation intrrupt flag + \arg FMC_BANK1_INT_FLAG_CBCMDERR: flash bank1 checked area by the check blank command is all 0xFF or not intrrupt flag + \arg FMC_BANK1_INT_FLAG_RSTERR: flash bank1 BOR/POR or system reset during erase/program intrrupt flag + \arg FMC_INT_FLAG_OB1ECCDET: option bytes 1 two bit error detect intrrupt flag + \arg FMC_INT_FLAG_OB0ECCDET: option bytes 0 two bit error detect intrrupt flag + \arg FMC_INT_FLAG_EPECCDET: EEPROM two bits error detect intrrupt flag + \arg FMC_INT_FLAG_ECCCOR: one bit error detected and correct intrrupt flag + \arg FMC_INT_FLAG_ECCDET: OTP/data flash/system memory/bank1 two bit error detect intrrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum int_flag) +{ + uint32_t reg_offset, reg; + + reg_offset = (uint32_t)(int_flag) >> 22U; + /* clear the intrrupt flag in ECCCS register */ + if(ECCCS_REG_OFFSET == reg_offset) { + reg = FMC_REG_VAL2(int_flag); + reg &= ~ECCCS_FLAG_MASK; + reg |= BIT(FMC_BIT_POS2(int_flag)); + FMC_REG_VAL2(int_flag) = reg; + } else { + /* clear the intrrupt flag in STAT0/STAT1 register */ + FMC_REG_VAL2(int_flag) = BIT(FMC_BIT_POS2(int_flag)); + } +} + +/*! + \brief get FMC bank0 state + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error +*/ +static fmc_state_enum fmc_bank0_state_get(void) +{ + fmc_state_enum fmc_state = FMC_READY; + + if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)) { + fmc_state = FMC_BUSY; + } else { + if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)) { + fmc_state = FMC_WPERR; + } else if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_PGERR)) { + fmc_state = FMC_PGERR; + } else if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_PGSERR)) { + fmc_state = FMC_PGSERR; + } else if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_PGAERR)) { + fmc_state = FMC_PGAERR; + } else if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_CBCMDERR)) { + fmc_state = FMC_CBCMDERR; + } else if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_RSTERR)) { + fmc_state = FMC_RSTERR; + } else { + /* illegal parameters */ + } + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get FMC bank1 state + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error +*/ +static fmc_state_enum fmc_bank1_state_get(void) +{ + fmc_state_enum fmc_state = FMC_READY; + + if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)) { + fmc_state = FMC_BUSY; + } else { + if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)) { + fmc_state = FMC_WPERR; + } else if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)) { + fmc_state = FMC_PGERR; + } else if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGSERR)) { + fmc_state = FMC_PGSERR; + } else if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGAERR)) { + fmc_state = FMC_PGAERR; + } else if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_CBCMDERR)) { + fmc_state = FMC_CBCMDERR; + } else if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_RSTERR)) { + fmc_state = FMC_RSTERR; + } else { + /* illegal parameters */ + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief check whether FMC bank0 is ready or not + \param[in] timeout: timeout count + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error +*/ +static fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout) +{ + fmc_state_enum fmc_state = FMC_BUSY; + + /* wait for FMC ready */ + do { + /* get FMC state */ + fmc_state = fmc_bank0_state_get(); + timeout--; + } while((FMC_BUSY == fmc_state) && (0U != timeout)); + + if(FMC_BUSY == fmc_state) { + fmc_state = FMC_TOERR; + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief check whether FMC bank1 is ready or not + \param[in] timeout: timeout count + \param[out] none + \retval state of FMC, refer to fmc_state_enum + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGSERR: program sequence error + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_CBCMDERR: the checked area not blank error + \arg FMC_RSTERR: BOR/POR or system reset during flash erase/program error +*/ +static fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout) +{ + fmc_state_enum fmc_state = FMC_BUSY; + + /* wait for FMC ready */ + do { + /* get FMC state */ + fmc_state = fmc_bank1_state_get(); + timeout--; + } while((FMC_BUSY == fmc_state) && (0U != timeout)); + + if(FMC_BUSY == fmc_state) { + fmc_state = FMC_TOERR; + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief wait shared SRAM mode to be ready + \param[in] ready_flag: sram mode ready bit + \arg FMC_WS_ERAMRDY: EEPROM SRAM ready bit + \arg FMC_WS_BRAMRDY: basic SRAM ready bit + \arg FMC_WS_PRAMRDY: fast PG SRAM ready bit + \param[out] none + \retval none +*/ +static void fmc_sram_mode_ready_wait(uint32_t ready_flag) +{ + while(1) { + if(0U != (FMC_WS & ready_flag)) { + break; + } + } +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_fwdgt.c b/gd32a50x/standard_peripheral/source/gd32a50x_fwdgt.c new file mode 100644 index 0000000..d3045c4 --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_fwdgt.c @@ -0,0 +1,243 @@ +/*! + \file gd32fxxx_fwdgt.c + \brief FWDGT driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_fwdgt.h" + +/*! + \brief enable write access to FWDGT_PSC, FWDGT_RLD and FWDGT_WND + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_enable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; +} + +/*! + \brief disable write access to FWDGT_PSC, FWDGT_RLD and FWDGT_WND + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_disable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; +} + +/*! + \brief start the FWDGT counter + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_enable(void) +{ + FWDGT_CTL = FWDGT_KEY_ENABLE; +} + +/*! + \brief configure the FWDGT counter prescaler value + \param[in] prescaler_value: specify prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = 0U; + + /* enable write access to FWDGT_PSC */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the PUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + } while((--timeout > (uint32_t)0) && (0U != flag_status)); + + if(0U != flag_status){ + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_value; + + return SUCCESS; +} + +/*! + \brief configure the FWDGT counter reload value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_reload_value_config(uint16_t reload_value) +{ + uint32_t timeout = FWDGT_RLD_TIMEOUT; + uint32_t flag_status = 0U; + + /* enable write access to FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the RUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + }while((--timeout > 0U) && (0U != flag_status)); + + if (0U != flag_status){ + return ERROR; + } + + FWDGT_RLD = RLD_RLD(reload_value); + + return SUCCESS; +} + +/*! + \brief configure the FWDGT counter window value + \param[in] window_value: specify window value(0x0000 - 0x0FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_window_value_config(uint16_t window_value) +{ + uint32_t time_index = FWDGT_WND_TIMEOUT; + uint32_t flag_status = 0U; + + /* enable write access to FWDGT_WND */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the WUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_WUD; + }while((--time_index > 0U) && (0U != flag_status)); + + if (0U != flag_status){ + return ERROR; + } + + FWDGT_WND = WND_WND(window_value); + + return SUCCESS; +} + +/*! + \brief reload the counter of FWDGT + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_counter_reload(void) +{ + FWDGT_CTL = FWDGT_KEY_RELOAD; +} + +/*! + \brief configure counter reload value, and prescaler divider value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[in] prescaler_div: FWDGT prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = 0U; + + /* enable write access to FWDGT_PSC,and FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the PUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + }while((--timeout > 0U) && (0U != flag_status)); + + if (0U != flag_status){ + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_div; + + timeout = FWDGT_RLD_TIMEOUT; + /* wait until the RUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + }while((--timeout > 0U) && (0U != flag_status)); + + if (0U != flag_status){ + return ERROR; + } + + FWDGT_RLD = RLD_RLD(reload_value); + + /* reload the counter */ + FWDGT_CTL = FWDGT_KEY_RELOAD; + + return SUCCESS; +} + +/*! + \brief get flag state of FWDGT + \param[in] flag: flag to get + only one parameter can be selected which is shown as below: + \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going + \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going + \arg FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fwdgt_flag_get(uint16_t flag) +{ + if (0U != (FWDGT_STAT & flag)){ + return SET; + } + return RESET; +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_gpio.c b/gd32a50x/standard_peripheral/source/gd32a50x_gpio.c new file mode 100644 index 0000000..3afdec6 --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_gpio.c @@ -0,0 +1,414 @@ +/*! + \file gd32a50x_gpio.c + \brief GPIO driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_gpio.h" + +/*! + \brief reset GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F) + \param[out] none + \retval none +*/ +void gpio_deinit(uint32_t gpio_periph) +{ + switch(gpio_periph){ + case GPIOA: + /* reset GPIOA */ + rcu_periph_reset_enable(RCU_GPIOARST); + rcu_periph_reset_disable(RCU_GPIOARST); + break; + case GPIOB: + /* reset GPIOB */ + rcu_periph_reset_enable(RCU_GPIOBRST); + rcu_periph_reset_disable(RCU_GPIOBRST); + break; + case GPIOC: + /* reset GPIOC */ + rcu_periph_reset_enable(RCU_GPIOCRST); + rcu_periph_reset_disable(RCU_GPIOCRST); + break; + case GPIOD: + /* reset GPIOD */ + rcu_periph_reset_enable(RCU_GPIODRST); + rcu_periph_reset_disable(RCU_GPIODRST); + break; + case GPIOE: + /* reset GPIOE */ + rcu_periph_reset_enable(RCU_GPIOERST); + rcu_periph_reset_disable(RCU_GPIOERST); + break; + case GPIOF: + /* reset GPIOF */ + rcu_periph_reset_enable(RCU_GPIOFRST); + rcu_periph_reset_disable(RCU_GPIOFRST); + break; + default: + break; + } +} + +/*! + \brief set GPIO mode + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F) + \param[in] mode: gpio pin mode + only one parameter can be selected which is shown as below: + \arg GPIO_MODE_INPUT: input mode + \arg GPIO_MODE_OUTPUT: output mode + \arg GPIO_MODE_AF: alternate function mode + \arg GPIO_MODE_ANALOG: analog mode + \param[in] pull_up_down: gpio pin with pull-up or pull-down resistor + only one parameter can be selected which is shown as below: + \arg GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors + \arg GPIO_PUPD_PULLUP: with pull-up resistor + \arg GPIO_PUPD_PULLDOWN:with pull-down resistor + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin) +{ + uint16_t i; + uint32_t ctl, pupd; + + ctl = GPIO_CTL(gpio_periph); + pupd = GPIO_PUD(gpio_periph); + + for(i = 0U;i < 16U;i++){ + if((((uint32_t)1U << i)) & pin){ + /* clear the specified pin mode bits */ + ctl &= ~GPIO_MODE_MASK(i); + /* set the specified pin mode bits */ + ctl |= GPIO_MODE_SET(i, mode); + + /* clear the specified pin pupd bits */ + pupd &= ~GPIO_PUPD_MASK(i); + /* set the specified pin pupd bits */ + pupd |= GPIO_PUPD_SET(i, pull_up_down); + } + } + + GPIO_CTL(gpio_periph) = ctl; + GPIO_PUD(gpio_periph) = pupd; +} + +/*! + \brief set GPIO output type and speed + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F) + \param[in] otype: gpio pin output mode + only one parameter can be selected which is shown as below: + \arg GPIO_OTYPE_PP: push pull mode + \arg GPIO_OTYPE_OD: open drain mode + \param[in] speed: gpio pin output max speed + only one parameter can be selected which is shown as below: + \arg GPIO_OSPEED_2MHZ: output max speed 2MHz + \arg GPIO_OSPEED_10MHZ: output max speed 10MHz + \arg GPIO_OSPEED_50MHZ: output max speed 50MHz + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin) +{ + uint16_t i; + uint32_t ospeed; + + if(GPIO_OTYPE_OD == otype){ + GPIO_OMODE(gpio_periph) |= (uint32_t)pin; + }else{ + GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin); + } + + /* get the specified pin output speed bits value */ + ospeed = GPIO_OSPD(gpio_periph); + + for(i = 0U;i < 16U;i++){ + if(((uint32_t)1U << i) & pin){ + /* clear the specified pin output speed bits */ + ospeed &= ~GPIO_OSPEED_MASK(i); + /* set the specified pin output speed bits */ + ospeed |= GPIO_OSPEED_SET(i,speed); + } + } + GPIO_OSPD(gpio_periph) = ospeed; +} + +/*! + \brief set GPIO pin bit + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BOP(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief reset GPIO pin bit + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BC(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief write data to the specified GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] bit_value: SET or RESET + only one parameter can be selected which is shown as below: + \arg RESET: clear the port pin + \arg SET: set the port pin + \param[out] none + \retval none +*/ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) +{ + if(RESET != bit_value){ + GPIO_BOP(gpio_periph) = (uint32_t)pin; + }else{ + GPIO_BC(gpio_periph) = (uint32_t)pin; + } +} + +/*! + \brief write data to the specified GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F) + \param[in] data: specify the value to be written to the port output control register + \param[out] none + \retval none +*/ +void gpio_port_write(uint32_t gpio_periph, uint16_t data) +{ + GPIO_OCTL(gpio_periph) = (uint32_t)data; +} + +/*! + \brief get GPIO pin input status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval SET or RESET +*/ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get GPIO port input status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F) + \param[out] none + \retval state of GPIO all pins +*/ +uint16_t gpio_input_port_get(uint32_t gpio_periph) +{ + return ((uint16_t)GPIO_ISTAT(gpio_periph)); +} + +/*! + \brief get GPIO pin output status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval SET or RESET +*/ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if((uint32_t)RESET != (GPIO_OCTL(gpio_periph)&(pin))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get GPIO port output status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F) + \param[out] none + \retval state of GPIO all pins +*/ +uint16_t gpio_output_port_get(uint32_t gpio_periph) +{ + return ((uint16_t)GPIO_OCTL(gpio_periph)); +} + +/*! + \brief set GPIO alternate function + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F) + \param[in] alt_func_num: GPIO pin af function, please refer to specific device datasheet + only one parameter can be selected which is shown as below: + \arg GPIO_AF_0: SYSTEM + \arg GPIO_AF_1: TIMER0, TIMER1, TIMER7, TIMER19, TIMER20 + \arg GPIO_AF_2: TIMER0, TIMER1, TIMER7, TIMER19, TIMER20 + \arg GPIO_AF_3: TIMER7, TIMER19, I2C0 + \arg GPIO_AF_4: SPI0, SPI1, I2S1, USART1 + \arg GPIO_AF_5: USART0, USART2, MFCOM, SPI1, I2C1 + \arg GPIO_AF_6: CAN0, CAN1, MFCOM, TRIGSEL + \arg GPIO_AF_7: TRIGSEL, CMP, MFCOM + \arg GPIO_AF_8: + \arg GPIO_AF_9: EVENTOUT + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin) +{ + uint16_t i; + uint32_t afrl, afrh; + + afrl = GPIO_AFSEL0(gpio_periph); + afrh = GPIO_AFSEL1(gpio_periph); + + for(i = 0U;i < 8U;i++){ + if(((uint32_t)1U << i) & pin){ + /* clear the specified pin alternate function bits */ + afrl &= ~GPIO_AFR_MASK(i); + afrl |= GPIO_AFR_SET(i,alt_func_num); + } + } + + for(i = 8U;i < 16U;i++){ + if(((uint32_t)1U << i) & pin){ + /* clear the specified pin alternate function bits */ + afrh &= ~GPIO_AFR_MASK(i - 8U); + afrh |= GPIO_AFR_SET(i - 8U,alt_func_num); + } + } + + GPIO_AFSEL0(gpio_periph) = afrl; + GPIO_AFSEL1(gpio_periph) = afrh; +} + +/*! + \brief lock GPIO pin bit + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) +{ + uint32_t lock = 0x00010000U; + lock |= pin; + + /* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */ + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + GPIO_LOCK(gpio_periph) = (uint32_t)pin; + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + lock = GPIO_LOCK(gpio_periph); + lock = GPIO_LOCK(gpio_periph); +} + +/*! + \brief toggle GPIO pin status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_TG(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief toggle GPIO port status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F) + \param[out] none + \retval none +*/ +void gpio_port_toggle(uint32_t gpio_periph) +{ + GPIO_TG(gpio_periph) = 0x0000FFFFU; +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_i2c.c b/gd32a50x/standard_peripheral/source/gd32a50x_i2c.c new file mode 100644 index 0000000..22bc8d9 --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_i2c.c @@ -0,0 +1,949 @@ +/*! + \file gd32a50x_i2c.c + \brief I2C driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_i2c.h" + +/* I2C register bit mask */ +#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ +#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ + +/* I2C register bit offset */ +#define CTL0_DNF_OFFSET ((uint32_t)0x00000008U) /*!< bit offset of DNF in I2C_CTL0 */ +#define CTL1_BYTENUM_OFFSET ((uint32_t)0x00000010U) /*!< bit offset of BYTENUM in I2C_CTL1 */ +#define STAT_READDR_OFFSET ((uint32_t)0x00000011U) /*!< bit offset of READDR in I2C_STAT */ +#define TIMING_SCLL_OFFSET ((uint32_t)0x00000000U) /*!< bit offset of SCLL in I2C_TIMING */ +#define TIMING_SCLH_OFFSET ((uint32_t)0x00000008U) /*!< bit offset of SCLH in I2C_TIMING */ +#define TIMING_SDADELY_OFFSET ((uint32_t)0x00000010U) /*!< bit offset of SDADELY in I2C_TIMING */ +#define TIMING_SCLDELY_OFFSET ((uint32_t)0x00000014U) /*!< bit offset of SCLDELY in I2C_TIMING */ +#define TIMING_PSC_OFFSET ((uint32_t)0x0000001CU) /*!< bit offset of PSC in I2C_TIMING */ +#define SADDR1_ADDMSK_OFFSET ((uint32_t)0x00000008U) /*!< bit offset of ADDMSK in I2C_SADDR1 */ +#define TIMEOUT_BUSTOB_OFFSET ((uint32_t)0x00000010U) /*!< bit offset of BUSTOB in I2C_TIMEOUT */ + +/*! + \brief reset I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_deinit(uint32_t i2c_periph) +{ + switch(i2c_periph) { + case I2C0: + /* reset I2C0 */ + rcu_periph_reset_enable(RCU_I2C0RST); + rcu_periph_reset_disable(RCU_I2C0RST); + break; + case I2C1: + /* reset I2C1 */ + rcu_periph_reset_enable(RCU_I2C1RST); + rcu_periph_reset_disable(RCU_I2C1RST); + break; + default: + break; + } +} + +/*! + \brief configure the timing parameters + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] psc: 0-0x0000000F, timing prescaler + \param[in] scl_dely: 0-0x0000000F, data setup time + \param[in] sda_dely: 0-0x0000000F, data hold time + \param[out] none + \retval none +*/ +void i2c_timing_config(uint32_t i2c_periph, uint32_t psc, uint32_t scl_dely, uint32_t sda_dely) +{ + /* clear PSC, SCLDELY, SDADELY bits in I2C_TIMING register */ + I2C_TIMING(i2c_periph) &= ~I2C_TIMING_PSC; + I2C_TIMING(i2c_periph) &= ~I2C_TIMING_SCLDELY; + I2C_TIMING(i2c_periph) &= ~I2C_TIMING_SDADELY; + /* mask PSC, SCLDELY, SDADELY bits in I2C_TIMING register */ + psc = (uint32_t)(psc << TIMING_PSC_OFFSET) & I2C_TIMING_PSC; + scl_dely = (uint32_t)(scl_dely << TIMING_SCLDELY_OFFSET) & I2C_TIMING_SCLDELY; + sda_dely = (uint32_t)(sda_dely << TIMING_SDADELY_OFFSET) & I2C_TIMING_SDADELY; + /* write PSC, SCLDELY, SDADELY bits in I2C_TIMING register */ + I2C_TIMING(i2c_periph) |= (psc | scl_dely | sda_dely); +} + +/*! + \brief configure digital noise filter + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] filter_length: the length of filter spikes + only one parameter can be selected which is shown as below: + \arg FILTER_DISABLE: digital filter is disabled + \arg FILTER_LENGTH_1: digital filter is enabled and filter spikes with a length of up to 1 tI2CCLK + \arg FILTER_LENGTH_2: digital filter is enabled and filter spikes with a length of up to 2 tI2CCLK + \arg FILTER_LENGTH_3: digital filter is enabled and filter spikes with a length of up to 3 tI2CCLK + \arg FILTER_LENGTH_4: digital filter is enabled and filter spikes with a length of up to 4 tI2CCLK + \arg FILTER_LENGTH_5: digital filter is enabled and filter spikes with a length of up to 5 tI2CCLK + \arg FILTER_LENGTH_6: digital filter is enabled and filter spikes with a length of up to 6 tI2CCLK + \arg FILTER_LENGTH_7: digital filter is enabled and filter spikes with a length of up to 7 tI2CCLK + \arg FILTER_LENGTH_8: digital filter is enabled and filter spikes with a length of up to 8 tI2CCLK + \arg FILTER_LENGTH_9: digital filter is enabled and filter spikes with a length of up to 9 tI2CCLK + \arg FILTER_LENGTH_10: digital filter is enabled and filter spikes with a length of up to 10 tI2CCLK + \arg FILTER_LENGTH_11: digital filter is enabled and filter spikes with a length of up to 11 tI2CCLK + \arg FILTER_LENGTH_12: digital filter is enabled and filter spikes with a length of up to 12 tI2CCLK + \arg FILTER_LENGTH_13: digital filter is enabled and filter spikes with a length of up to 13 tI2CCLK + \arg FILTER_LENGTH_14: digital filter is enabled and filter spikes with a length of up to 14 tI2CCLK + \arg FILTER_LENGTH_15: digital filter is enabled and filter spikes with a length of up to 15 tI2CCLK + \param[out] none + \retval none +*/ +void i2c_digital_noise_filter_config(uint32_t i2c_periph, uint32_t filter_length) +{ + I2C_CTL0(i2c_periph) &= (uint32_t)(~I2C_CTL0_DNF); + I2C_CTL0(i2c_periph) |= (uint32_t)(filter_length << CTL0_DNF_OFFSET); +} + +/*! + \brief enable analog noise filter + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_analog_noise_filter_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~I2C_CTL0_ANOFF; +} + +/*! + \brief disable analog noise filter + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_analog_noise_filter_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_ANOFF; +} + +/*! + \brief configure the SCL high and low period of clock in master mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] sclh: 0-0x000000FF, SCL high period + \param[in] scll: 0-0x000000FF, SCL low period + \param[out] none + \retval none +*/ +void i2c_master_clock_config(uint32_t i2c_periph, uint32_t sclh, uint32_t scll) +{ + /* clear SCLH, SCLL bits in I2C_TIMING register */ + I2C_TIMING(i2c_periph) &= ~I2C_TIMING_SCLH; + I2C_TIMING(i2c_periph) &= ~I2C_TIMING_SCLL; + /* mask SCLH, SCLL bits in I2C_TIMING register */ + sclh = (uint32_t)(sclh << TIMING_SCLH_OFFSET) & I2C_TIMING_SCLH; + scll = (uint32_t)(scll << TIMING_SCLL_OFFSET) & I2C_TIMING_SCLL; + /* write SCLH, SCLL bits in I2C_TIMING register */ + I2C_TIMING(i2c_periph) |= (sclh | scll); +} + +/*! + \brief configure i2c slave address and transfer direction in master mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] address: 0-0x3FF except reserved address, I2C slave address to be sent + \param[in] trans_direction: I2C transfer direction in master mode + only one parameter can be selected which is shown as below: + \arg I2C_MASTER_TRANSMIT: master transmit + \arg I2C_MASTER_RECEIVE: master receive + \param[out] none + \retval none +*/ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t address, uint32_t trans_direction) +{ + /* configure slave address */ + I2C_CTL1(i2c_periph) &= ~I2C_CTL1_SADDRESS; + I2C_CTL1(i2c_periph) |= address; + /* configure transfer direction */ + I2C_CTL1(i2c_periph) &= ~I2C_CTL1_TRDIR; + I2C_CTL1(i2c_periph) |= trans_direction; +} + +/*! + \brief 10-bit address header executes read direction only in master receive mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_address10_header_enable(uint32_t i2c_periph) +{ + I2C_CTL1(i2c_periph) |= I2C_CTL1_HEAD10R; +} + +/*! + \brief 10-bit address header executes complete sequence in master receive mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_address10_header_disable(uint32_t i2c_periph) +{ + I2C_CTL1(i2c_periph) &= ~I2C_CTL1_HEAD10R; +} + +/*! + \brief enable 10-bit addressing mode in master mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_address10_enable(uint32_t i2c_periph) +{ + I2C_CTL1(i2c_periph) |= I2C_CTL1_ADD10EN; +} + +/*! + \brief disable 10-bit addressing mode in master mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_address10_disable(uint32_t i2c_periph) +{ + I2C_CTL1(i2c_periph) &= ~I2C_CTL1_ADD10EN; +} + +/*! + \brief enable I2C automatic end mode in master mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_automatic_end_enable(uint32_t i2c_periph) +{ + I2C_CTL1(i2c_periph) |= I2C_CTL1_AUTOEND; +} + +/*! + \brief disable I2C automatic end mode in master mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_automatic_end_disable(uint32_t i2c_periph) +{ + I2C_CTL1(i2c_periph) &= ~I2C_CTL1_AUTOEND; +} + +/*! + \brief enable the response to a general call + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_slave_response_to_gcall_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_GCEN; +} + +/*! + \brief disable the response to a general call + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_slave_response_to_gcall_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~I2C_CTL0_GCEN; +} + +/*! + \brief enable to stretch SCL low when data is not ready in slave mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] none + \param[out] none + \retval none +*/ +void i2c_stretch_scl_low_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~I2C_CTL0_SS; +} + +/*! + \brief disable to stretch SCL low when data is not ready in slave mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] none + \param[out] none + \retval none +*/ +void i2c_stretch_scl_low_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_SS; +} + +/*! + \brief configure i2c slave address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] address: I2C address + \param[in] addr_format: 7bits or 10bits + only one parameter can be selected which is shown as below: + \arg I2C_ADDFORMAT_7BITS: 7bits + \arg I2C_ADDFORMAT_10BITS: 10bits + \param[out] none + \retval none +*/ +void i2c_address_config(uint32_t i2c_periph, uint32_t address, uint32_t addr_format) +{ + /* configure ADDRESS[7:1] and address format */ + address = address & I2C_ADDRESS_MASK; + I2C_SADDR0(i2c_periph) = (addr_format | address); + /* enable i2c address in slave mode */ + I2C_SADDR0(i2c_periph) |= I2C_SADDR0_ADDRESSEN; +} + +/*! + \brief define which bits of ADDRESS[7:1] need to compare with the incoming address byte + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] compare_bits: the bits need to compare + one or more parameters can be selected which are shown as below: + ADDRESS_BIT1_COMPARE: address bit1 needs compare + ADDRESS_BIT2_COMPARE: address bit2 needs compare + ADDRESS_BIT3_COMPARE: address bit3 needs compare + ADDRESS_BIT4_COMPARE: address bit4 needs compare + ADDRESS_BIT5_COMPARE: address bit5 needs compare + ADDRESS_BIT6_COMPARE: address bit6 needs compare + ADDRESS_BIT7_COMPARE: address bit7 needs compare + \param[out] none + \retval none +*/ +void i2c_address_bit_compare_config(uint32_t i2c_periph, uint32_t compare_bits) +{ + I2C_CTL2(i2c_periph) &= ~I2C_CTL2_ADDM; + I2C_CTL2(i2c_periph) |= compare_bits; +} + +/*! + \brief disable i2c address in slave mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_address_disable(uint32_t i2c_periph) +{ + I2C_SADDR0(i2c_periph) &= ~I2C_SADDR0_ADDRESSEN; +} + +/*! + \brief configure i2c second slave address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] address: I2C address + \param[in] addr_mask: the bits not need to compare + one or more parameters can be selected which are shown as below: + \arg ADDRESS2_NO_MASK: no mask, all the bits must be compared + \arg ADDRESS2_MASK_BIT1: ADDRESS2[1] is masked, only ADDRESS2[7:2] are compared + \arg ADDRESS2_MASK_BIT1_2: ADDRESS2[2:1] is masked, only ADDRESS2[7:3] are compared + \arg ADDRESS2_MASK_BIT1_3: ADDRESS2[3:1] is masked, only ADDRESS2[7:4] are compared + \arg ADDRESS2_MASK_BIT1_4: ADDRESS2[4:1] is masked, only ADDRESS2[7:5] are compared + \arg ADDRESS2_MASK_BIT1_5: ADDRESS2[5:1] is masked, only ADDRESS2[7:6] are compared + \arg ADDRESS2_MASK_BIT1_6: ADDRESS2[6:1] is masked, only ADDRESS2[7] are compared + \arg ADDRESS2_MASK_ALL: all the ADDRESS2[7:1] bits are masked + \param[out] none + \retval none +*/ +void i2c_second_address_config(uint32_t i2c_periph, uint32_t address, uint32_t addr_mask) +{ + /* configure ADDRESS2[7:1] */ + address = address & I2C_ADDRESS2_MASK; + I2C_SADDR1(i2c_periph) |= address; + /* configure ADDRESS2[7:1] mask */ + I2C_SADDR1(i2c_periph) &= ~I2C_SADDR1_ADDMSK2; + I2C_SADDR1(i2c_periph) |= (uint32_t)(addr_mask << SADDR1_ADDMSK_OFFSET); + /* enable i2c second address in slave mode */ + I2C_SADDR1(i2c_periph) |= I2C_SADDR1_ADDRESS2EN; +} + +/*! + \brief disable i2c second address in slave mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_second_address_disable(uint32_t i2c_periph) +{ + I2C_SADDR1(i2c_periph) &= ~I2C_SADDR1_ADDRESS2EN; +} + +/*! + \brief get received match address in slave mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval received match address +*/ +uint32_t i2c_recevied_address_get(uint32_t i2c_periph) +{ + return (uint32_t)((I2C_STAT(i2c_periph) & I2C_STAT_READDR) >> STAT_READDR_OFFSET); +} + +/*! + \brief enable slave byte control + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] none + \param[out] none + \retval none +*/ +void i2c_slave_byte_control_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_SBCTL; +} + +/*! + \brief disable slave byte control + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] none + \param[out] none + \retval none +*/ +void i2c_slave_byte_control_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~I2C_CTL0_SBCTL; +} + +/*! + \brief generate a NACK in slave mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_nack_enable(uint32_t i2c_periph) +{ + I2C_CTL1(i2c_periph) |= I2C_CTL1_NACKEN; +} + +/*! + \brief generate an ACK in slave mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_nack_disable(uint32_t i2c_periph) +{ + I2C_CTL1(i2c_periph) &= ~I2C_CTL1_NACKEN; +} + +/*! + \brief enable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; +} + +/*! + \brief disable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~I2C_CTL0_I2CEN; +} + +/*! + \brief generate a START condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_start_on_bus(uint32_t i2c_periph) +{ + I2C_CTL1(i2c_periph) |= I2C_CTL1_START; +} + +/*! + \brief generate a STOP condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_stop_on_bus(uint32_t i2c_periph) +{ + I2C_CTL1(i2c_periph) |= I2C_CTL1_STOP; +} + +/*! + \brief I2C transmit data + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] data: data to be transmitted + \param[out] none + \retval none +*/ +void i2c_data_transmit(uint32_t i2c_periph, uint32_t data) +{ + I2C_TDATA(i2c_periph) = (I2C_TDATA_TDATA & data); +} + +/*! + \brief I2C receive data + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval received data +*/ +uint32_t i2c_data_receive(uint32_t i2c_periph) +{ + return (I2C_RDATA(i2c_periph) & I2C_RDATA_RDATA); +} + +/*! + \brief enable I2C reload mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_reload_enable(uint32_t i2c_periph) +{ + I2C_CTL1(i2c_periph) |= I2C_CTL1_RELOAD; +} + +/*! + \brief disable I2C reload mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_reload_disable(uint32_t i2c_periph) +{ + I2C_CTL1(i2c_periph) &= ~I2C_CTL1_RELOAD; +} + +/*! + \brief configure number of bytes to be transferred + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] byte_number: 0x0-0xFF, number of bytes to be transferred + \param[out] none + \retval none +*/ +void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint32_t byte_number) +{ + I2C_CTL1(i2c_periph) &= (uint32_t)(~I2C_CTL1_BYTENUM); + I2C_CTL1(i2c_periph) |= (uint32_t)(byte_number << CTL1_BYTENUM_OFFSET); +} + +/*! + \brief enable I2C DMA for transmission or reception + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dma: I2C DMA + only one parameter can be selected which is shown as below: + \arg I2C_DMA_TRANSMIT: transmit data using DMA + \arg I2C_DMA_RECEIVE: receive data using DMA + \param[out] none + \retval none +*/ +void i2c_dma_enable(uint32_t i2c_periph, uint8_t dma) +{ + if(I2C_DMA_TRANSMIT == dma) { + I2C_CTL0(i2c_periph) |= I2C_CTL0_DENT; + } else { + I2C_CTL0(i2c_periph) |= I2C_CTL0_DENR; + } +} + +/*! + \brief disable I2C DMA for transmission or reception + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dma: I2C DMA + only one parameter can be selected which is shown as below: + \arg I2C_DMA_TRANSMIT: transmit data using DMA + \arg I2C_DMA_RECEIVE: receive data using DMA + \param[out] none + \retval none +*/ +void i2c_dma_disable(uint32_t i2c_periph, uint8_t dma) +{ + if(I2C_DMA_TRANSMIT == dma) { + I2C_CTL0(i2c_periph) &= ~I2C_CTL0_DENT; + } else { + I2C_CTL0(i2c_periph) &= ~I2C_CTL0_DENR; + } +} + +/*! + \brief I2C transfers PEC value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_pec_transfer(uint32_t i2c_periph) +{ + I2C_CTL1(i2c_periph) |= I2C_CTL1_PECTRANS; +} + +/*! + \brief enable I2C PEC calculation + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] none + \param[out] none + \retval none +*/ +void i2c_pec_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_PECEN; +} + +/*! + \brief disable I2C PEC calculation + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] none + \param[out] none + \retval none +*/ +void i2c_pec_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~I2C_CTL0_PECEN; +} + +/*! + \brief get packet error checking value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval PEC value +*/ +uint32_t i2c_pec_value_get(uint32_t i2c_periph) +{ + return (I2C_PEC(i2c_periph) & I2C_PEC_PECV); +} + +/*! + \brief enable SMBus alert + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] none + \param[out] none + \retval none +*/ +void i2c_smbus_alert_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBALTEN; +} + +/*! + \brief disable SMBus alert + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] none + \param[out] none + \retval none +*/ +void i2c_smbus_alert_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~I2C_CTL0_SMBALTEN; +} + +/*! + \brief enable SMBus device default address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] none + \param[out] none + \retval none +*/ +void i2c_smbus_default_addr_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBDAEN; +} + +/*! + \brief disable SMBus device default address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] none + \param[out] none + \retval none +*/ +void i2c_smbus_default_addr_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~I2C_CTL0_SMBDAEN; +} + +/*! + \brief enable SMBus Host address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] none + \param[out] none + \retval none +*/ +void i2c_smbus_host_addr_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBHAEN; +} + +/*! + \brief disable SMBus Host address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] none + \param[out] none + \retval none +*/ +void i2c_smbus_host_addr_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~I2C_CTL0_SMBHAEN; +} + +/*! + \brief enable extended clock timeout detection + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_extented_clock_timeout_enable(uint32_t i2c_periph) +{ + I2C_TIMEOUT(i2c_periph) |= I2C_TIMEOUT_EXTOEN; +} + +/*! + \brief disable extended clock timeout detection + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_extented_clock_timeout_disable(uint32_t i2c_periph) +{ + I2C_TIMEOUT(i2c_periph) &= ~I2C_TIMEOUT_EXTOEN; +} + +/*! + \brief enable clock timeout detection + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_clock_timeout_enable(uint32_t i2c_periph) +{ + I2C_TIMEOUT(i2c_periph) |= I2C_TIMEOUT_TOEN; +} + +/*! + \brief disable clock timeout detection + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_clock_timeout_disable(uint32_t i2c_periph) +{ + I2C_TIMEOUT(i2c_periph) &= ~I2C_TIMEOUT_TOEN; +} + +/*! + \brief configure bus timeout B + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] timeout: bus timeout B + \param[out] none + \retval none +*/ +void i2c_bus_timeout_b_config(uint32_t i2c_periph, uint32_t timeout) +{ + I2C_TIMEOUT(i2c_periph) &= ~I2C_TIMEOUT_BUSTOB; + I2C_TIMEOUT(i2c_periph) |= (uint32_t)(timeout << TIMEOUT_BUSTOB_OFFSET); +} + +/*! + \brief configure bus timeout A + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] timeout: bus timeout A + \param[out] none + \retval none +*/ +void i2c_bus_timeout_a_config(uint32_t i2c_periph, uint32_t timeout) +{ + I2C_TIMEOUT(i2c_periph) &= ~I2C_TIMEOUT_BUSTOA; + I2C_TIMEOUT(i2c_periph) |= timeout; +} + +/*! + \brief configure idle clock timeout detection + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] timeout: bus timeout A + \arg BUSTOA_DETECT_SCL_LOW: BUSTOA is used to detect SCL low timeout + \arg BUSTOA_DETECT_IDLE: BUSTOA is used to detect both SCL and SDA high timeout when the bus is idle + \param[out] none + \retval none +*/ +void i2c_idle_clock_timeout_config(uint32_t i2c_periph, uint32_t timeout) +{ + I2C_TIMEOUT(i2c_periph) &= ~I2C_TIMEOUT_TOIDLE; + I2C_TIMEOUT(i2c_periph) |= timeout; +} + +/*! + \brief get I2C flag status + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: I2C flags + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_TBE: I2C_TDATA is empty during transmitting + \arg I2C_FLAG_TI: transmit interrupt + \arg I2C_FLAG_RBNE: I2C_RDATA is not empty during receiving + \arg I2C_FLAG_ADDSEND: address received matches in slave mode + \arg I2C_FLAG_NACK: not acknowledge flag + \arg I2C_FLAG_STPDET: STOP condition detected in slave mode + \arg I2C_FLAG_TC: transfer complete in master mode + \arg I2C_FLAG_TCR: transfer complete reload + \arg I2C_FLAG_BERR: bus error + \arg I2C_FLAG_LOSTARB: arbitration Lost + \arg I2C_FLAG_OUERR: overrun/underrun error in slave mode + \arg I2C_FLAG_PECERR: PEC error + \arg I2C_FLAG_TIMEOUT: timeout flag + \arg I2C_FLAG_SMBALT: SMBus Alert + \arg I2C_FLAG_I2CBSY: busy flag + \arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver in slave mode + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag) +{ + if(0U != (I2C_STAT(i2c_periph) & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear I2C flag status + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: I2C flags + one or more parameters can be selected which are shown as below: + \arg I2C_FLAG_ADDSEND: address received matches in slave mode + \arg I2C_FLAG_NACK: not acknowledge flag + \arg I2C_FLAG_STPDET: STOP condition detected in slave mode + \arg I2C_FLAG_BERR: bus error + \arg I2C_FLAG_LOSTARB: arbitration Lost + \arg I2C_FLAG_OUERR: overrun/underrun error in slave mode + \arg I2C_FLAG_PECERR: PEC error + \arg I2C_FLAG_TIMEOUT: timeout flag + \arg I2C_FLAG_SMBALT: SMBus Alert + \param[out] none + \retval none +*/ +void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag) +{ + I2C_STATC(i2c_periph) |= flag; +} + +/*! + \brief enable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] interrupt: I2C interrupts + one or more parameters can be selected which are shown as below: + \arg I2C_INT_ERR: error interrupt + \arg I2C_INT_TC: transfer complete interrupt + \arg I2C_INT_STPDET: stop detection interrupt + \arg I2C_INT_NACK: not acknowledge received interrupt + \arg I2C_INT_ADDM: address match interrupt + \arg I2C_INT_RBNE: receive interrupt + \arg I2C_INT_TI: transmit interrupt + \param[out] none + \retval none +*/ +void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t interrupt) +{ + I2C_CTL0(i2c_periph) |= interrupt; +} + +/*! + \brief disable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] interrupt: I2C interrupts + one or more parameters can be selected which are shown as below: + \arg I2C_INT_ERR: error interrupt + \arg I2C_INT_TC: transfer complete interrupt + \arg I2C_INT_STPDET: stop detection interrupt + \arg I2C_INT_NACK: not acknowledge received interrupt + \arg I2C_INT_ADDM: address match interrupt + \arg I2C_INT_RBNE: receive interrupt + \arg I2C_INT_TI: transmit interrupt + \param[out] none + \retval none +*/ +void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t interrupt) +{ + I2C_CTL0(i2c_periph) &= ~interrupt; +} + +/*! + \brief get I2C interrupt flag status + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_TI: transmit interrupt flag + \arg I2C_INT_FLAG_RBNE: I2C_RDATA is not empty during receiving interrupt flag + \arg I2C_INT_FLAG_ADDSEND: address received matches in slave mode interrupt flag + \arg I2C_INT_FLAG_NACK: not acknowledge interrupt flag + \arg I2C_INT_FLAG_STPDET: stop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_TC: transfer complete in master mode interrupt flag + \arg I2C_INT_FLAG_TCR: transfer complete reload interrupt flag + \arg I2C_INT_FLAG_BERR: bus error interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost interrupt flag + \arg I2C_INT_FLAG_OUERR: overrun/underrun error in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error interrupt flag + \arg I2C_INT_FLAG_TIMEOUT: timeout interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + uint32_t ret1 = 0U; + uint32_t ret2 = 0U; + + /* get the status of interrupt enable bit */ + ret1 = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); + /* get the status of interrupt flag */ + ret2 = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); + if(ret1 && ret2) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear I2C interrupt flag status + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_ADDSEND: address received matches in slave mode interrupt flag + \arg I2C_INT_FLAG_NACK: not acknowledge interrupt flag + \arg I2C_INT_FLAG_STPDET: stop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_BERR: bus error interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost interrupt flag + \arg I2C_INT_FLAG_OUERR: overrun/underrun error in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error interrupt flag + \arg I2C_INT_FLAG_TIMEOUT: timeout interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert interrupt flag + \param[out] none + \retval none +*/ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + I2C_STATC(i2c_periph) |= BIT(I2C_BIT_POS2(int_flag)); +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_mfcom.c b/gd32a50x/standard_peripheral/source/gd32a50x_mfcom.c new file mode 100644 index 0000000..29e5e81 --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_mfcom.c @@ -0,0 +1,772 @@ +/*! + \file gd32a50x_mfcom.c + \brief MFCOM driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50X +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_mfcom.h" + +/*! + \brief reset MFCOM + \param[in] none + \param[out] none + \retval none +*/ +void mfcom_deinit(void) +{ + /* reset MFCOM */ + rcu_periph_reset_enable(RCU_MFCOMRST); + rcu_periph_reset_disable(RCU_MFCOMRST); +} + +/*! + \brief software reset + \param[in] none + \param[out] none + \retval none +*/ +void mfcom_software_reset(void) +{ + MFCOM_CTL |= MFCOM_CTL_SWRSTEN; + MFCOM_CTL &= ~MFCOM_CTL_SWRSTEN; +} + + +/*! + \brief enable MFCOM function + \param[in] none + \param[out] none + \retval none +*/ +void mfcom_enable(void) +{ + MFCOM_CTL |= MFCOM_CTL_MFCOMEN; +} + +/*! + \brief disable MFCOM function + \param[in] none + \param[out] none + \retval none +*/ +void mfcom_disable(void) +{ + MFCOM_CTL &= ~MFCOM_CTL_MFCOMEN; +} + +/*! + \brief initialize mfcom_timer_parameter_struct with the default values + \param[in] init_struct: the initialization timer parameter need + \param[out] none + \retval none +*/ +void mfcom_timer_struct_para_init(mfcom_timer_parameter_struct* init_struct) +{ + /* set the mfcom_timer_parameter_struct with the default values */ + init_struct->trigger_select = MFCOM_TIMER_TRGSEL_PIN0; + init_struct->trigger_polarity = MFCOM_TIMER_TRGPOL_ACTIVE_HIGH; + init_struct->pin_config = MFCOM_TIMER_PINCFG_INPUT; + init_struct->pin_select = MFCOM_TIMER_PINSEL_PIN0; + init_struct->pin_polarity = MFCOM_TIMER_PINPOL_ACTIVE_HIGH; + init_struct->mode = MFCOM_TIMER_DISABLE; + init_struct->output = MFCOM_TIMER_OUT_HIGH_EN; + init_struct->decrement = MFCOM_TIMER_DEC_CLK_SHIFT_OUT; + init_struct->reset = MFCOM_TIMER_RESET_NEVER; + init_struct->disable = MFCOM_TIMER_DISMODE_NEVER; + init_struct->enable = MFCOM_TIMER_ENMODE_ALWAYS; + init_struct->stopbit = MFCOM_TIMER_STOPBIT_DISABLE; + init_struct->startbit = MFCOM_TIMER_STARTBIT_DISABLE; + init_struct->compare = 0U; +} + +/*! + \brief initialize mfcom_shifter_parameter_struct with the default values + \param[in] init_struct: the initialization shifter parameter need + \param[out] none + \retval none +*/ +void mfcom_shifter_struct_para_init(mfcom_shifter_parameter_struct* init_struct) +{ + /* set the mfcom_shifter_parameter_struct with the default values */ + init_struct->timer_select = MFCOM_SHIFTER_TIMER0; + init_struct->timer_polarity = MFCOM_SHIFTER_TIMPOL_ACTIVE_HIGH; + init_struct->pin_config = MFCOM_SHIFTER_PINCFG_INPUT; + init_struct->pin_select = MFCOM_SHIFTER_PINSEL_PIN0; + init_struct->pin_polarity = MFCOM_SHIFTER_PINPOL_ACTIVE_HIGH; + init_struct->mode = MFCOM_SHIFTER_DISABLE; + init_struct->input_source = MFCOM_SHIFTER_INSRC_PIN; + init_struct->stopbit = MFCOM_SHIFTER_STOPBIT_DISABLE; + init_struct->startbit = MFCOM_SHIFTER_STARTBIT_DISABLE; +} + +/*! + \brief initialize MFCOM timer parameter + \param[in] timer: MFCOM timer number + \arg MFCOM_TIMER_x(x=0..3) + \param[in] init_struct: the initialization timer parameter need + \arg trigger_select: MFCOM_TIMER_TRGSEL_PIN0 MFCOM_TIMER_TRGSEL_SHIFTER0 + MFCOM_TIMER_TRGSEL_PIN1 MFCOM_TIMER_TRGSEL_TIMER0 + MFCOM_TIMER_TRGSEL_PIN2 MFCOM_TIMER_TRGSEL_SHIFTER1 + MFCOM_TIMER_TRGSEL_PIN3 MFCOM_TIMER_TRGSEL_TIMER1 + MFCOM_TIMER_TRGSEL_PIN4 MFCOM_TIMER_TRGSEL_SHIFTER2 + MFCOM_TIMER_TRGSEL_PIN5 MFCOM_TIMER_TRGSEL_TIMER2 + MFCOM_TIMER_TRGSEL_PIN6 MFCOM_TIMER_TRGSEL_SHIFTER3 + MFCOM_TIMER_TRGSEL_PIN7 MFCOM_TIMER_TRGSEL_TIMER3 + MFCOM_TIMER_TRGSEL_EXTERNAL0 MFCOM_TIMER_TRGSEL_EXTERNAL1 + MFCOM_TIMER_TRGSEL_EXTERNAL2 MFCOM_TIMER_TRGSEL_EXTERNAL3 + + trigger_polarity: MFCOM_TIMER_TRGPOL_ACTIVE_HIGH + MFCOM_TIMER_TRGPOL_ACTIVE_LOW + + pin_config: MFCOM_TIMER_PINCFG_INPUT MFCOM_TIMER_PINCFG_OPENDRAIN + MFCOM_TIMER_PINCFG_BIDI MFCOM_TIMER_PINCFG_OUTPUT + + pin_select: MFCOM_TIMER_PINSEL_PIN0 MFCOM_TIMER_PINSEL_PIN1 + MFCOM_TIMER_PINSEL_PIN2 MFCOM_TIMER_PINSEL_PIN3 + MFCOM_TIMER_PINSEL_PIN4 MFCOM_TIMER_PINSEL_PIN5 + MFCOM_TIMER_PINSEL_PIN6 MFCOM_TIMER_PINSEL_PIN7 + + pin_polarity: MFCOM_TIMER_PINPOL_ACTIVE_HIGH + MFCOM_TIMER_PINPOL_ACTIVE_LOW + + mode: MFCOM_TIMER_DISABLE MFCOM_TIMER_BAUDMODE + MFCOM_TIMER_PWMMODE MFCOM_TIMER_16BITCOUNTER + + output: MFCOM_TIMER_OUT_HIGH_EN MFCOM_TIMER_OUT_LOW_EN + MFCOM_TIMER_OUT_HIGH_EN_RESET MFCOM_TIMER_OUT_LOW_EN_RESET + + decrement: MFCOM_TIMER_DEC_CLK_SHIFT_OUT MFCOM_TIMER_DEC_TRIG_SHIFT_OUT + MFCOM_TIMER_DEC_PIN_SHIFT_PIN MFCOM_TIMER_DEC_TRIG_SHIFT_TRIG + + reset: MFCOM_TIMER_RESET_NEVER MFCOM_TIMER_RESET_PIN_TIMOUT + MFCOM_TIMER_RESET_TRIG_TIMOUT MFCOM_TIMER_RESET_PIN_RISING + MFCOM_TIMER_RESET_TRIG_RISING MFCOM_TIMER_RESET_TRIG_BOTH + + disable: MFCOM_TIMER_DISMODE_NEVER MFCOM_TIMER_DISMODE_PRE_TIMDIS + MFCOM_TIMER_DISMODE_COMPARE MFCOM_TIMER_DISMODE_COMPARE_TRIGLOW + MFCOM_TIMER_DISMODE_PINBOTH MFCOM_TIMER_DISMODE_PINBOTH_TRIGHIGH + MFCOM_TIMER_DISMODE_TRIGFALLING + + enable: MFCOM_TIMER_ENMODE_ALWAYS MFCOM_TIMER_ENMODE_PRE_TIMEN + MFCOM_TIMER_ENMODE_TRIGHIGH MFCOM_TIMER_ENMODE_TRIGHIGH_PINHIGH + MFCOM_TIMER_ENMODE_PINRISING MFCOM_TIMER_ENMODE_PINRISING_TRIGHIGH + MFCOM_TIMER_ENMODE_TRIGRISING MFCOM_TIMER_ENMODE_TRIGBOTH + + stopbit: MFCOM_TIMER_STOPBIT_DISABLE MFCOM_TIMER_STOPBIT_TIMCMP + MFCOM_TIMER_STOPBIT_TIMDIS MFCOM_TIMER_STOPBIT_TIMCMP_TIMDIS + + startbit: MFCOM_TIMER_STARTBIT_DISABLE + MFCOM_TIMER_STARTBIT_ENABLE + + compare: compare value + \param[out] none + \retval none +*/ +void mfcom_timer_init(uint32_t timer, mfcom_timer_parameter_struct* init_struct) +{ + /* configure compare value */ + MFCOM_TMCMP(timer) = (uint32_t)init_struct->compare; + /* configure timer output/decrement/reset/disable/enable/stopbit/startbit */ + MFCOM_TMCFG(timer) = init_struct->output | init_struct->decrement | init_struct->reset | init_struct->disable | init_struct->enable | init_struct->stopbit | init_struct->startbit; + + /* configure pin trigger_select/trigger_polarity/pin_config/pin_select/pin_polarity/mode */ + MFCOM_TMCTL(timer) = init_struct->trigger_select | init_struct->trigger_polarity | init_struct->pin_config | init_struct->pin_select | init_struct->pin_polarity | init_struct->mode; +} + +/*! + \brief initialize MFCOM shifter parameter + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[in] init_struct: the initialization shifter parameter need + \arg timer_select: MFCOM_SHIFTER_TIMER0 MFCOM_SHIFTER_TIMER1 + MFCOM_SHIFTER_TIMER2 MFCOM_SHIFTER_TIMER3 + + timer_polarity: MFCOM_SHIFTER_TIMPOL_ACTIVE_HIGH + MFCOM_SHIFTER_TIMPOL_ACTIVE_LOW + + pin_config: MFCOM_SHIFTER_PINCFG_INPUT MFCOM_SHIFTER_PINCFG_OPENDRAIN + MFCOM_SHIFTER_PINCFG_BIDI MFCOM_SHIFTER_PINCFG_OUTPUT + + pin_select: MFCOM_SHIFTER_PINSEL_PIN0 MFCOM_SHIFTER_PINSEL_PIN1 + MFCOM_SHIFTER_PINSEL_PIN2 MFCOM_SHIFTER_PINSEL_PIN3 + MFCOM_SHIFTER_PINSEL_PIN4 MFCOM_SHIFTER_PINSEL_PIN5 + MFCOM_SHIFTER_PINSEL_PIN6 MFCOM_SHIFTER_PINSEL_PIN7 + + pin_polarity: MFCOM_SHIFTER_PINPOL_ACTIVE_HIGH + MFCOM_SHIFTER_PINPOL_ACTIVE_LOW + + mode: MFCOM_SHIFTER_DISABLE MFCOM_SHIFTER_RECEIVE + MFCOM_SHIFTER_TRANSMIT MFCOM_SHIFTER_MATCH_STORE + MFCOM_SHIFTER_MATCH_CONTINUOUS + + input_source: MFCOM_SHIFTER_INSRC_PIN + MFCOM_SHIFTER_INSRC_NEXTSHIFTER + + stopbit: MFCOM_SHIFTER_STOPBIT_DISABLE MFCOM_SHIFTER_STOPBIT_LOW + MFCOM_SHIFTER_STOPBIT_HIGH + + startbit: MFCOM_SHIFTER_STARTBIT_DISABLE MFCOM_SHIFTER_STARTBIT_DISABLE_TXEN + MFCOM_SHIFTER_STARTBIT_LOW MFCOM_SHIFTER_STARTBIT_HIGH + \param[out] none + \retval none +*/ +void mfcom_shifter_init(uint32_t shifter, mfcom_shifter_parameter_struct* init_struct) +{ + /* configure shifter input_source/stopbit/startbit */ + MFCOM_SCFG(shifter) = init_struct->input_source | init_struct->stopbit | init_struct->startbit; + + /* configure shifter timer_select/timer_polarity/pin_config/pin_select/pin_polarity/mode */ + MFCOM_SCTL(shifter) = init_struct->timer_select | init_struct->timer_polarity | init_struct->pin_config | init_struct->pin_select | init_struct->pin_polarity | init_struct->mode; +} + +/*! + \brief configure timer pin mode + \param[in] timer: MFCOM timer number + \arg MFCOM_TIMER_x(x=0..3) + \param[in] outputmode: + \arg MFCOM_TIMER_PINCFG_INPUT: pin input + \arg MFCOM_TIMER_PINCFG_OPENDRAIN: pin open drain or bidirectional output enable + \arg MFCOM_TIMER_PINCFG_BIDI: pin bidirectional output data + \arg MFCOM_TIMER_PINCFG_OUTPUT: pin output + \param[out] none + \retval none +*/ +void mfcom_timer_pin_config(uint32_t timer, uint32_t mode) +{ + uint32_t temp; + temp = MFCOM_TMCTL(timer); + + /* clear timer pin configuration bits */ + temp &= ~MFCOM_TMCTL_TMPCFG; + + /* set timer pin outputmode */ + temp |= mode; + MFCOM_TMCTL(timer) = temp; +} + +/*! + \brief configure shifter pin mode + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[in] outputmode: + \arg MFCOM_SHIFTER_PINCFG_INPUT: pin input + \arg MFCOM_SHIFTER_PINCFG_OPENDRAIN: pin open drain or bidirectional output enable + \arg MFCOM_SHIFTER_PINCFG_BIDI: pin bidirectional output data + \arg MFCOM_SHIFTER_PINCFG_OUTPUT: pin output + \param[out] none + \retval none +*/ +void mfcom_shifter_pin_config(uint32_t shifter, uint32_t mode) +{ + uint32_t temp; + temp = MFCOM_SCTL(shifter); + + /* clear shifter pin configuration bits */ + temp &= ~MFCOM_SCTL_SPCFG; + + /* set shifter pin outputmode */ + temp |= mode; + MFCOM_SCTL(shifter) = temp; +} + +/*! + \brief enable MFCOM timer in specific mode + \param[in] timer: MFCOM timer number + \arg MFCOM_TIMER_x(x=0..3) + \param[in] timermode: + \arg MFCOM_TIMER_DISABLE: timer disabled + \arg MFCOM_TIMER_BAUDMODE: dual 8-bit counters baud/bit mode + \arg MFCOM_TIMER_PWMMODE: dual 8-bit counters PWM mode + \arg MFCOM_TIMER_16BITCOUNTER: single 16-bit counter mode + \param[out] none + \retval none +*/ +void mfcom_timer_enable(uint32_t timer, uint32_t timermode) +{ + uint32_t temp; + temp = MFCOM_TMCTL(timer); + + /* clear timer mode bits */ + temp &= ~MFCOM_TMCTL_TMMOD; + + /* set timer mode */ + temp |= timermode; + MFCOM_TMCTL(timer) = temp; +} + +/*! + \brief enable MFCOM shifter in specific mode + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[in] shiftermode: + \arg MFCOM_SHIFTER_DISABLE: shifter is disabled + \arg MFCOM_SHIFTER_RECEIVE: receive mode + \arg MFCOM_SHIFTER_TRANSMIT: transmit mode + \arg MFCOM_SHIFTER_MATCH_STORE: match store mode + \arg MFCOM_SHIFTER_MATCH_CONTINUOUS: match continuous mode + \param[out] none + \retval none +*/ +void mfcom_shifter_enable(uint32_t shifter, uint32_t shiftermode) +{ + uint32_t temp; + temp = MFCOM_SCTL(shifter); + + /* clear shifter mode bits */ + temp &= ~MFCOM_SCTL_SMOD; + + /* set shifter mode */ + temp |= shiftermode; + MFCOM_SCTL(shifter) = temp; +} + +/*! + \brief disable MFCOM timer + \param[in] timer: MFCOM timer number + \arg MFCOM_TIMER_x(x=0..3) + \param[out] none + \retval none +*/ +void mfcom_timer_disable(uint32_t timer) +{ + MFCOM_TMCTL(timer) &= ~MFCOM_TMCTL_TMMOD; +} + +/*! + \brief disable MFCOM shifter + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[out] none + \retval none +*/ +void mfcom_shifter_disable(uint32_t shifter) +{ + MFCOM_SCTL(shifter) &= ~MFCOM_SCTL_SMOD; +} + +/*! + \brief set MFCOM timer compare value + \param[in] timer: MFCOM timer number + \arg MFCOM_TIMER_x(x=0..3) + \param[in] compare: timer compare value + \param[out] none + \retval none +*/ +void mfcom_timer_cmpvalue_set(uint32_t timer, uint32_t compare) +{ + MFCOM_TMCMP(timer) = compare; +} + +/*! + \brief get MFCOM timer compare value + \param[in] timer: MFCOM timer number + \arg MFCOM_TIMER_x(x=0..3) + \param[out] timer compare value + \retval none +*/ +uint32_t mfcom_timer_cmpvalue_get(uint32_t timer) +{ + return MFCOM_TMCMP(timer); +} + +/*! + \brief set MFCOM timer disable mode + \param[in] timer: MFCOM timer number + \arg MFCOM_TIMER_x(x=0..3) + \param[in] dismode: configure conditions that can disable timers and stop decrement. + \arg MFCOM_TIMER_DISMODE_NEVER: timer never disabled + \arg MFCOM_TIMER_DISMODE_PRE_TIMDIS: timer disabled on timer x-1 disable + \arg MFCOM_TIMER_DISMODE_COMPARE: timer disabled on timer compare + \arg MFCOM_TIMER_DISMODE_COMPARE_TRIGLOW: timer disabled on timer compare and trigger Low + \arg MFCOM_TIMER_DISMODE_PINBOTH: timer disabled on pin rising or falling edge + \arg MFCOM_TIMER_DISMODE_PINBOTH_TRIGHIGH timer disabled on pin rising or falling edge provided trigger is high + \arg MFCOM_TIMER_DISMODE_TRIGFALLING timer disabled on trigger falling edge + \param[out] none + \retval none +*/ +void mfcom_timer_dismode_set(uint32_t timer, uint32_t dismode) +{ + uint32_t temp; + temp = MFCOM_TMCFG(timer); + + /* clear timer disable bits */ + temp &= ~MFCOM_TMCFG_TMDIS; + + /* set timer disable mode */ + temp |= dismode; + MFCOM_TMCFG(timer) = temp; +} + +/*! + \brief set MFCOM shifter stopbit + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[in] stopbit: shifter stop bit + \arg MFCOM_SHIFTER_STOPBIT_DISABLE: disable shifter stop bit + \arg MFCOM_SHIFTER_STOPBIT_LOW: set shifter stop bit to logic low level + \arg MFCOM_SHIFTER_STOPBIT_HIGH: set shifter stop bit to logic high level + \param[out] none + \retval none +*/ +void mfcom_shifter_stopbit_set(uint32_t shifter, uint32_t stopbit) +{ + uint32_t temp; + temp = MFCOM_SCFG(shifter); + + /* clear shifter stop bit */ + temp &= ~MFCOM_SCFG_SSTOP; + + /* set shifter stop bit */ + temp |= stopbit; + MFCOM_SCFG(shifter) = temp; +} + +/*! + \brief write MFCOM shifter buffer + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[in] data: 32-bit data + \param[in] rwmode: MFCOM read write mode + \arg MFCOM_RWMODE_NORMAL: read and write in normal mode + \arg MFCOM_RWMODE_BITSWAP: read and write in bit swapped mode + \arg MFCOM_RWMODE_BYTESWAP: read and write in byte swapped mode + \arg MFCOM_RWMODE_BITBYTESWAP: read and write in bit byte swapped mode + \param[out] none + \retval none +*/ +void mfcom_buffer_write(uint32_t shifter, uint32_t data, uint32_t rwmode) +{ + switch (rwmode){ + case MFCOM_RWMODE_NORMAL: + /* write MFCOM shift buffer in MFCOM_RWMODE_NORMAL mode */ + MFCOM_SBUF(shifter) = data; + break; + case MFCOM_RWMODE_BITSWAP: + /* write MFCOM shift buffer in MFCOM_RWMODE_BITSWAP mode */ + MFCOM_SBUFBIS(shifter) = data; + break; + case MFCOM_RWMODE_BYTESWAP: + /* write MFCOM shift buffer in MFCOM_RWMODE_BYTESWAP mode */ + MFCOM_SBUFBYS(shifter) = data; + break; + case MFCOM_RWMODE_BITBYTESWAP: + /* write MFCOM shift buffer in MFCOM_RWMODE_BITBYTESWAP mode */ + MFCOM_SBUFBBS(shifter) = data; + break; + default: + break; + } +} + +/*! + \brief read MFCOM shifter buffer + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[in] rwmode: MFCOM read write mode + \arg MFCOM_RWMODE_NORMAL: read and write in normal mode + \arg MFCOM_RWMODE_BITSWAP: read and write in bit swapped mode + \arg MFCOM_RWMODE_BYTESWAP: read and write in byte swapped mode + \arg MFCOM_RWMODE_BITBYTESWAP: read and write in bit byte swapped mode + \param[out] none + \retval data: 32-bit data +*/ +uint32_t mfcom_buffer_read(uint32_t shifter, uint32_t rwmode) +{ + uint32_t data; + switch (rwmode){ + case MFCOM_RWMODE_NORMAL: + /* read MFCOM shift buffer in MFCOM_RWMODE_NORMAL mode */ + data = MFCOM_SBUF(shifter); + break; + case MFCOM_RWMODE_BITSWAP: + /* read MFCOM shift buffer in MFCOM_RWMODE_BITSWAP mode */ + data = MFCOM_SBUFBIS(shifter); + break; + case MFCOM_RWMODE_BYTESWAP: + /* read MFCOM shift buffer in MFCOM_RWMODE_BYTESWAP mode */ + data = MFCOM_SBUFBYS(shifter); + break; + case MFCOM_RWMODE_BITBYTESWAP: + /* read MFCOM shift buffer in MFCOM_RWMODE_BITBYTESWAP mode */ + data = MFCOM_SBUFBBS(shifter); + break; + default: + data = 0U; + break; + } + return data; +} + +/*! + \brief get MFCOM shifter flag + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus mfcom_shifter_flag_get(uint32_t shifter) +{ + if(0U != (MFCOM_SSTAT & ((uint32_t)1U << shifter))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get MFCOM shifter error flag + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus mfcom_shifter_error_flag_get(uint32_t shifter) +{ + if(0U != (MFCOM_SERR & ((uint32_t)1U << shifter))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get MFCOM timer flag + \param[in] timer: MFCOM timer number + \arg MFCOM_TIMER_x(x=0..3) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus mfcom_timer_flag_get(uint32_t timer) +{ + if(0U != (MFCOM_TMSTAT & ((uint32_t)1U << timer))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get MFCOM shifter interrupt flag + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus mfcom_shifter_interrupt_flag_get(uint32_t shifter) +{ + uint32_t interrupt_flag, interrupt_enable; + + interrupt_flag = MFCOM_SSTAT & ((uint32_t)1U << shifter); + interrupt_enable = MFCOM_SSIEN & ((uint32_t)1U << shifter); + + /* judge shifter interrupt flag state */ + if(interrupt_flag & interrupt_enable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get MFCOM shifter error interrupt flag + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus mfcom_shifter_error_interrupt_flag_get(uint32_t shifter) +{ + uint32_t interrupt_flag, interrupt_enable; + + interrupt_flag = MFCOM_SERR & ((uint32_t)1U << shifter); + interrupt_enable = MFCOM_SEIEN & ((uint32_t)1U << shifter); + + /* judge shifter error interrupt flag state */ + if(interrupt_flag & interrupt_enable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get MFCOM timer interrupt flag + \param[in] timer: MFCOM timer number + \arg MFCOM_TIMER_x(x=0..3) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus mfcom_timer_interrupt_flag_get(uint32_t timer) +{ + uint32_t interrupt_flag, interrupt_enable; + + interrupt_flag = MFCOM_TMSTAT & ((uint32_t)1U << timer); + interrupt_enable = MFCOM_TMSIEN & ((uint32_t)1U << timer); + + /* judge timer interrupt flag state */ + if(interrupt_flag & interrupt_enable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear MFCOM shifter flag + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[out] none + \retval none +*/ +void mfcom_shifter_flag_clear(uint32_t shifter) +{ + MFCOM_SSTAT = ((uint32_t)1U << shifter); +} + +/*! + \brief clear MFCOM shifter error flag + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[out] none + \retval none +*/ +void mfcom_shifter_error_flag_clear(uint32_t shifter) +{ + MFCOM_SERR = ((uint32_t)1U << shifter); +} + +/*! + \brief clear MFCOM timer flag + \param[in] timer: MFCOM timer number + \arg MFCOM_TIMER_x(x=0..3) + \param[out] none + \retval none +*/ +void mfcom_timer_flag_clear(uint32_t timer) +{ + MFCOM_TMSTAT = ((uint32_t)1U << timer); +} + +/*! + \brief enable MFCOM shifter interrupt + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[out] none + \retval none +*/ +void mfcom_shifter_interrupt_enable(uint32_t shifter) +{ + MFCOM_SSIEN |= ((uint32_t)1U << shifter); +} + +/*! + \brief enable MFCOM shifter error interrupt + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[out] none + \retval none +*/ +void mfcom_shifter_error_interrupt_enable(uint32_t shifter) +{ + MFCOM_SEIEN |= ((uint32_t)1U << shifter); +} + +/*! + \brief enable MFCOM timer interrupt + \param[in] timer: MFCOM timer number + \arg MFCOM_TIMER_x(x=0..3) + \param[out] none + \retval none +*/ +void mfcom_timer_interrupt_enable(uint32_t timer) +{ + MFCOM_TMSIEN |= ((uint32_t)1U << timer); +} + +/*! + \brief enable MFCOM shifter dma + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[out] none + \retval none +*/ +void mfcom_shifter_dma_enable(uint32_t shifter) +{ + MFCOM_SSDMAEN |= ((uint32_t)1U << shifter); +} + +/*! + \brief disable MFCOM shifter interrupt + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[out] none + \retval none +*/ +void mfcom_shifter_interrupt_disable(uint32_t shifter) +{ + MFCOM_SSIEN &= ~((uint32_t)1U << shifter); +} + +/*! + \brief disable MFCOM shifter error interrupt + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[out] none + \retval none +*/ +void mfcom_shifter_error_interrupt_disable(uint32_t shifter) +{ + MFCOM_SEIEN &= ~((uint32_t)1U << shifter); +} + +/*! + \brief disable MFCOM timer interrupt + \param[in] timer: MFCOM timer number + \arg MFCOM_TIMER_x(x=0..3) + \param[out] none + \retval none +*/ +void mfcom_timer_interrupt_disable(uint32_t timer) +{ + MFCOM_TMSIEN &= ~((uint32_t)1U << timer); +} + +/*! + \brief disable MFCOM shifter dma + \param[in] shifter: MFCOM shifter number + \arg MFCOM_SHIFTER_x(x=0..3) + \param[out] none + \retval none +*/ +void mfcom_shifter_dma_disable(uint32_t shifter) +{ + MFCOM_SSDMAEN &= ~((uint32_t)1U << shifter); +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_misc.c b/gd32a50x/standard_peripheral/source/gd32a50x_misc.c new file mode 100644 index 0000000..84298d0 --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_misc.c @@ -0,0 +1,183 @@ +/*! + \file gd32a50x_misc.c + \brief MISC driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_misc.h" + +/*! + \brief set the priority group + \param[in] nvic_prigroup: the NVIC priority group + \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority + \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority + \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority + \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority + \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority + \param[out] none + \retval none +*/ +void nvic_priority_group_set(uint32_t nvic_prigroup) +{ + /* set the priority group value */ + SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup; +} + +/*! + \brief enable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set + \param[in] nvic_irq_sub_priority: the subpriority needed to set + \param[out] none + \retval none +*/ +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, + uint8_t nvic_irq_sub_priority) +{ + uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; + /* use the priority group value to get the temp_pre and the temp_sub */ + if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){ + temp_pre=0U; + temp_sub=0x4U; + }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){ + temp_pre=1U; + temp_sub=0x3U; + }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){ + temp_pre=2U; + temp_sub=0x2U; + }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){ + temp_pre=3U; + temp_sub=0x1U; + }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){ + temp_pre=4U; + temp_sub=0x0U; + }else{ + nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); + temp_pre=2U; + temp_sub=0x2U; + } + /* get the temp_priority to fill the NVIC->IP register */ + temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); + temp_priority |= (uint32_t)nvic_irq_sub_priority &((uint32_t)0x0FU >> (0x4U - temp_sub)); + temp_priority = temp_priority << 0x04U; + NVIC->IPR[nvic_irq] = (uint8_t)temp_priority; + /* enable the selected IRQ */ + NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); +} + +/*! + \brief disable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[out] none + \retval none +*/ +void nvic_irq_disable(IRQn_Type nvic_irq) +{ + /* disable the selected IRQ.*/ + NVIC_DisableIRQ(nvic_irq); +} + +/*! + \brief initiates a system reset request to reset the MCU + \param[in] none + \param[out] none + \retval none +*/ +void nvic_system_reset(void) +{ + NVIC_SystemReset(); +} + +/*! + \brief set the NVIC vector table base address + \param[in] nvic_vict_tab: the RAM or FLASH base address + \arg NVIC_VECTTAB_RAM: RAM base address + \are NVIC_VECTTAB_FLASH: Flash base address + \param[in] offset: Vector Table offset + \param[out] none + \retval none +*/ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) +{ + SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); + __DSB(); +} + +/*! + \brief set the state of the low power mode + \param[in] lowpower_mode: the low power mode state + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up + by all the enable and disable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_set(uint8_t lowpower_mode) +{ + SCB->SCR |= (uint32_t)lowpower_mode; +} + +/*! + \brief reset the state of the low power mode + \param[in] lowpower_mode: the low power mode state + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be + woke up by the enable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_reset(uint8_t lowpower_mode) +{ + SCB->SCR &= (~(uint32_t)lowpower_mode); +} + +/*! + \brief set the systick clock source + \param[in] systick_clksource: the systick clock source needed to choose + \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK + \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 + \param[out] none + \retval none +*/ +void systick_clksource_set(uint32_t systick_clksource) +{ + if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){ + /* set the systick clock source from HCLK */ + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + }else{ + /* set the systick clock source from HCLK/8 */ + SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; + } +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_pmu.c b/gd32a50x/standard_peripheral/source/gd32a50x_pmu.c new file mode 100644 index 0000000..c40340c --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_pmu.c @@ -0,0 +1,375 @@ +/*! + \file gd32a50x_pmu.c + \brief PMU driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_pmu.h" + +/*! + \brief reset PMU register + \param[in] none + \param[out] none + \retval none +*/ +void pmu_deinit(void) +{ + /* reset PMU */ + rcu_periph_reset_enable(RCU_PMURST); + rcu_periph_reset_disable(RCU_PMURST); +} + +/*! + \brief select low voltage detector threshold + \param[in] lvdt_n: + only one parameter can be selected which is shown as below: + \arg PMU_LVDT_0: voltage threshold is 2.9V + \arg PMU_LVDT_1: voltage threshold is 3.1V + \arg PMU_LVDT_2: voltage threshold is 3.3V + \arg PMU_LVDT_3: voltage threshold is 3.5V + \arg PMU_LVDT_4: voltage threshold is 4.0V + \arg PMU_LVDT_5: voltage threshold is 4.2V + \arg PMU_LVDT_6: voltage threshold is 4.4V + \arg PMU_LVDT_7: voltage threshold is 4.6V + \param[out] none + \retval none +*/ +void pmu_lvd_select(uint32_t lvdt_n) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; + /* clear LVDT bits */ + PMU_CTL &= ~PMU_CTL_LVDT; + /* set LVDT bits according to lvdt_n */ + PMU_CTL |= lvdt_n; + /* enable LVD */ + PMU_CTL |= PMU_CTL_LVDEN; +} + +/*! + \brief disable PMU lvd + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lvd_disable(void) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; +} + +/*! + \brief select over voltage detector threshold + \param[in] ovdt_n: + only one parameter can be selected which is shown as below: + \arg PMU_OVDT_0: voltage threshold is 5.0V + \arg PMU_OVDT_1: voltage threshold is 5.5V + \param[out] none + \retval none +*/ +void pmu_ovd_select(uint32_t ovdt_n) +{ + /* disable OVD */ + PMU_CTL &= ~PMU_CTL_OVDEN; + /* clear OVDT bits */ + PMU_CTL &= ~PMU_CTL_OVDT; + /* set OVDT bits according to ovdt_n */ + PMU_CTL |= ovdt_n; + /* enable OVD */ + PMU_CTL |= PMU_CTL_OVDEN; +} + +/*! + \brief disable PMU ovd + \param[in] none + \param[out] none + \retval none +*/ +void pmu_ovd_disable(void) +{ + /* disable OVD */ + PMU_CTL &= ~PMU_CTL_OVDEN; +} + +/*! + \brief enable low-driver mode in deep-sleep mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lowdriver_mode_enable(void) +{ + PMU_CTL |= PMU_CTL_LDEN; +} + +/*! + \brief disable low-driver mode in deep-sleep mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lowdriver_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_LDEN; +} + +/*! + \brief SRAM1 power off in deep-sleep mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_sram1_poweroff_mode_enable(void) +{ + PMU_CTL |= PMU_CTL_SRAMSW1; +} + +/*! + \brief SRAM1 power on in deep-sleep mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_sram1_poweroff_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_SRAMSW1; +} + +/*! + \brief SRAM2 power off in deep-sleep mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_sram2_poweroff_mode_enable(void) +{ + PMU_CTL |= PMU_CTL_SRAMSW2; +} + +/*! + \brief SRAM2 power on in deep-sleep mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_sram2_poweroff_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_SRAMSW2; +} + +/*! + \brief PMU work in sleep mode + \param[in] sleepmodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_sleepmode(uint8_t sleepmodecmd) +{ + /* clear sleepdeep bit of Cortex-M33 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* select WFI or WFE command to enter sleep mode */ + if(WFI_CMD == sleepmodecmd) { + __WFI(); + } else { + __SEV(); + __WFE(); + __WFE(); + } +} + +/*! + \brief PMU work in deepsleep mode + \param[in] ldo: + only one parameter can be selected which is shown as below: + \arg PMU_LDO_NORMAL: LDO work in normal power mode when pmu enter deepsleep mode + \arg PMU_LDO_LOWPOWER: LDO work in low power mode when pmu enter deepsleep mode + \param[in] lowdrive: + only one parameter can be selected which is shown as below: + \arg PMU_LOWDRIVER_ENABLE: low-driver mode enable in deep-sleep mode + \arg PMU_LOWDRIVER_DISABLE: low-driver mode disable in deep-sleep mode + \param[in] deepsleepmodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd) +{ + /* flash goto sleep mode when MCU enters deepsleep mode */ + REG32(0x40022000) |= (uint32_t)(1<<14); + + /* clear stbmod and ldolp bits */ + PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP | PMU_CTL_LDEN)); + + /* set ldolp bit according to pmu_ldo */ + PMU_CTL |= (ldo | lowdrive); + + /* set sleepdeep bit of Cortex-M33 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* select WFI or WFE command to enter deepsleep mode */ + if(WFI_CMD == deepsleepmodecmd) { + __WFI(); + } else { + __SEV(); + __WFE(); + __WFE(); + } + + /* reset sleepdeep bit of Cortex-M33 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/*! + \brief pmu work in standby mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_to_standbymode(void) +{ + /* set stbmod bit */ + PMU_CTL |= PMU_CTL_STBMOD; + + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + + /* set sleepdeep bit of Cortex-M33 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + REG32(0xE000E010U) &= 0x00010004U; + REG32(0xE000E180U) = 0XFFFFFFF7U; + REG32(0xE000E184U) = 0XFFFFFFFFU; + REG32(0xE000E188U) = 0xFFFFFFFFU; + + /* select WFI or WFE command to enter standby mode */ + __WFI(); +} + +/*! + \brief enable wakeup pin + \param[in] wakeup_pin: + one or more parameters can be selected which are shown as below: + \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) + \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_enable(uint32_t wakeup_pin) +{ + PMU_CS |= wakeup_pin; +} + +/*! + \brief disable wakeup pin + \param[in] wakeup_pin: + one or more parameters can be selected which are shown as below: + \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) + \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_disable(uint32_t wakeup_pin) +{ + PMU_CS &= ~(wakeup_pin); +} + +/*! + \brief enable write access to the registers in backup domain + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_enable(void) +{ + PMU_CTL |= PMU_CTL_BKPWEN; +} + +/*! + \brief disable write access to the registers in backup domain + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_disable(void) +{ + PMU_CTL &= ~PMU_CTL_BKPWEN; +} + +/*! + \brief get flag state + \param[in] flag: + only one parameter can be selected which is shown as below: + \arg PMU_FLAG_WAKEUP: wakeup flag + \arg PMU_FLAG_STANDBY: standby flag + \arg PMU_FLAG_LVD: lvd flag + \arg PMU_FLAG_OVD: ovd flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus pmu_flag_get(uint32_t flag) +{ + if(0U != (PMU_CS & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear flag bit + \param[in] flag: + only one parameter can be selected which is shown as below: + \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag + \arg PMU_FLAG_RESET_STANDBY: reset standby flag + \param[out] none + \retval none +*/ +void pmu_flag_clear(uint32_t flag) +{ + switch(flag) { + case PMU_FLAG_RESET_WAKEUP: + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + break; + case PMU_FLAG_RESET_STANDBY: + /* reset standby flag */ + PMU_CTL |= PMU_CTL_STBRST; + break; + default: + break; + } +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_rcu.c b/gd32a50x/standard_peripheral/source/gd32a50x_rcu.c new file mode 100644 index 0000000..0c3a242 --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_rcu.c @@ -0,0 +1,1151 @@ +/*! + \file gd32a50x_rcu.c + \brief RCU driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_rcu.h" + +/* define startup timeout count */ +#define OSC_STARTUP_TIMEOUT ((uint32_t)0x000FFFFFU) +#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x03FFFFFFU) + +/* RCU IRC8M adjust value mask and offset*/ +#define RCU_IRC8M_ADJUST_MASK ((uint8_t)0x1FU) +#define RCU_IRC8M_ADJUST_OFFSET ((uint32_t)3U) + +/*! + \brief deinitialize the RCU + \param[in] none + \param[out] none + \retval none +*/ +void rcu_deinit(void) +{ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + if(ERROR == rcu_osci_stab_wait(RCU_IRC8M)) { + while(1) { + } + } + + RCU_CFG0 &= ~RCU_CFG0_SCS; + while((RCU_CFG0 & RCU_CFG0_SCSS) != RCU_SCSS_IRC8M) { + } + /* reset CTL register */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN | RCU_CTL_HXTALSCAL | RCU_CTL_LCKMEN | RCU_CTL_PLLMEN); + RCU_CTL &= ~RCU_CTL_HXTALBPS; + /* reset CFG0 register */ + RCU_CFG0 = 0x00020000U; + /* reset INT and CFG1 and CFG2 register */ + RCU_INT = 0x00FF0000U; + RCU_CFG1 = 0x00000000U; + RCU_CFG2 = 0x00000000U; +} + +/*! + \brief enable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_DMAx (x=0,1): DMA clock + \arg RCU_DMAMUX: DMAMUX clock + \arg RCU_CRC: CRC clock + \arg RCU_GPIOx (x=A,B,C,D,E,F): GPIO ports clock + \arg RCU_SYSCFG: SYSCFG clock + \arg RCU_CMP: CMP clock + \arg RCU_ADCx (x=0,1): ADCx clock + \arg RCU_TIMERx (x=0,1,5,6,7,19,20): TIMER clock + \arg RCU_SPIx (x=0,1): SPIx clock + \arg RCU_USARTx (x=0,1,2): USARTx clock + \arg RCU_MFCOM: MFCOM clock + \arg RCU_TRIGSEL: TRIGSEL clock + \arg RCU_CANx (x=0,1): CANx clock + \arg RCU_I2Cx (x=0,1): I2Cx clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_BKP: BKP clock + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock + \arg RCU_RTC: RTC clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_enable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_DMAx (x=0,1): DMA clock + \arg RCU_DMAMUX: DMAMUX clock + \arg RCU_CRC: CRC clock + \arg RCU_GPIOx (x=A,B,C,D,E,F): GPIO ports clock + \arg RCU_SYSCFG: SYSCFG clock + \arg RCU_CMP: CMP clock + \arg RCU_ADCx (x=0,1): ADCx clock + \arg RCU_TIMERx (x=0,1,5,6,7,19,20): TIMER clock + \arg RCU_SPIx (x=0,1): SPIx clock + \arg RCU_USARTx (x=0,1,2): USARTx clock + \arg RCU_MFCOM: MFCOM clock + \arg RCU_TRIGSEL: TRIGSEL clock + \arg RCU_CANx (x=0,1): CANx clock + \arg RCU_I2Cx (x=0,1): I2Cx clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_BKP: BKP clock + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock + \arg RCU_RTC: RTC clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_disable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief reset the peripherals + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_DMAxRST (x=0,1): DMA reset enable + \arg RCU_DMAMUXRST: DMAMUX reset enable + \arg RCU_MFCOMRST: MFCOM reset enable + \arg RCU_CRCRST: CRC reset enable + \arg RCU_GPIOxRST (x=A,B,C,D,E,F): GPIO ports reset enable + \arg RCU_SYSCFGRST: SYSCFG reset enable + \arg RCU_CMPRST: CMP reset enable + \arg RCU_ADCxRST (x=0,1): ADCx reset enable + \arg RCU_TIMERxRST (x=0,1,5,6,7,19,20): TIMER reset enable + \arg RCU_SPIxRST (x=0,1): SPIx reset enable + \arg RCU_USARTxRST (x=0,1,2): USARTx reset enable + \arg RCU_CANxRST (x=0,1): CANx reset enable + \arg RCU_I2CxRST(x=0,1): I2Cx reset enable + \arg RCU_WWDGTRST: WWDGT reset enable + \arg RCU_PMURST: PMU reset enable + \arg RCU_DACRST: DAC reset enable + \param[out] none + \retval none +*/ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief disable reset the peripheral + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_DMAxRST (x=0,1): DMA reset enable + \arg RCU_DMAMUXRST: DMAMUX reset enable + \arg RCU_MFCOMRST: MFCOM reset enable + \arg RCU_CRCRST: CRC reset enable + \arg RCU_GPIOxRST (x=A,B,C,D,E,F): GPIO ports reset enable + \arg RCU_SYSCFGRST: SYSCFG reset enable + \arg RCU_CMPRST: CMP reset enable + \arg RCU_ADCxRST (x=0,1): ADCx reset enable + \arg RCU_TIMERxRST (x=0,1,5,6,7,19,20): TIMER reset enable + \arg RCU_SPIxRST (x=0,1): SPIx reset enable + \arg RCU_USARTxRST (x=0,1,2): USARTx reset enable + \arg RCU_CANxRST (x=0,1): CANx reset enable + \arg RCU_I2CxRST(x=0,1): I2Cx reset enable + \arg RCU_WWDGTRST: WWDGT reset enable + \arg RCU_PMURST: PMU reset enable + \arg RCU_DACRST: DAC reset enable + \param[out] none + \retval none +*/ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief enable the peripherals clock when in sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock when in sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief reset the BKP domain control register + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_enable(void) +{ + RCU_BDCTL |= RCU_BDCTL_BKPRST; +} + +/*! + \brief disable the BKP domain control register reset + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_disable(void) +{ + RCU_BDCTL &= ~RCU_BDCTL_BKPRST; +} + +/*! + \brief configure the system clock source + \param[in] ck_sys: system clock source select + only one parameter can be selected which is shown as below: + \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source + \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source + \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source + \param[out] none + \retval none +*/ +void rcu_system_clock_source_config(uint32_t ck_sys) +{ + uint32_t reg; + reg = RCU_CFG0; + /* reset the SCS bits and set according to ck_sys */ + reg &= ~RCU_CFG0_SCS; + RCU_CFG0 = (reg | ck_sys); +} + +/*! + \brief get the system clock source + \param[in] none + \param[out] none + \retval which clock is selected as CK_SYS source + \arg RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source + \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source + \arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source +*/ +uint32_t rcu_system_clock_source_get(void) +{ + return (RCU_CFG0 & RCU_CFG0_SCSS); +} + +/*! + \brief configure the AHB clock prescaler selection + \param[in] ck_ahb: AHB clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 + \param[out] none + \retval none +*/ +void rcu_ahb_clock_config(uint32_t ck_ahb) +{ + uint32_t reg; + reg = RCU_CFG0; + /* reset the AHBPSC bits and set according to ck_ahb */ + reg &= ~RCU_CFG0_AHBPSC; + RCU_CFG0 = (reg | ck_ahb); +} + +/*! + \brief configure the APB1 clock prescaler selection + \param[in] ck_apb1: APB1 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 + \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 + \param[out] none + \retval none +*/ +void rcu_apb1_clock_config(uint32_t ck_apb1) +{ + uint32_t reg; + reg = RCU_CFG0; + /* reset the APB1PSC and set according to ck_apb1 */ + reg &= ~RCU_CFG0_APB1PSC; + RCU_CFG0 = (reg | ck_apb1); +} + +/*! + \brief configure the APB2 clock prescaler selection + \param[in] ck_apb2: APB2 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 + \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 + \param[out] none + \retval none +*/ +void rcu_apb2_clock_config(uint32_t ck_apb2) +{ + uint32_t reg; + reg = RCU_CFG0; + /* reset the APB2PSC and set according to ck_apb2 */ + reg &= ~RCU_CFG0_APB2PSC; + RCU_CFG0 = (reg | ck_apb2); +} + +/*! + \brief configure the CK_OUT clock source + \param[in] ckout0_src: CK_OUT clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CKOUTSRC_NONE: no clock selected + \arg RCU_CKOUTSRC_IRC40K£ºIRC40K selected + \arg RCU_CKOUTSRC_LXTAL£º LXTAL selected + \arg RCU_CKOUTSRC_CKSYS: system clock selected + \arg RCU_CKOUTSRC_IRC8M: high speed 8M internal oscillator clock selected + \arg RCU_CKOUTSRC_HXTAL: HXTAL selected + \arg RCU_CKOUTSRC_CKPLL_DIV1: CK_PLL selected + \arg RCU_CKOUTSRC_CKPLL_DIV2: CK_PLL/2 selected + \param[in] ckout_div: CK_OUT divider + \arg RCU_CKOUT_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT is divided by x + \param[out] none + \retval none +*/ +void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div) +{ + uint32_t ckout = 0U; + ckout = RCU_CFG0; + /* reset the CKOUTSEL, CKOUTDIV and PLLDV bits and set according to ckout_src and ckout_div */ + ckout &= ~(RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); + RCU_CFG0 = (ckout | ckout_src | ckout_div); +} + +/*! + \brief configure the PLL clock source selection and PLL multiply factor + \param[in] pll_src: PLL clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_PLLSRC_IRC8M_DIV2: select CK_IRC8M/2 as PLL source clock + \arg RCU_PLLSRC_HXTAL: select HXTAL as PLL source clock + \param[in] pll_mul: PLL multiply factor + only one parameter can be selected which is shown as below: + \arg RCU_PLL_MULx(x=2..32): PLL source clock * x + \param[out] none + \retval none +*/ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) +{ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (pll_src | pll_mul); +} + +/*! + \brief enable double PLL clock + \param[in] none + \param[out] none + \retval none +*/ +void rcu_double_pll_enable(void) +{ + RCU_CFG0 &= ~RCU_CFG0_DPLL; +} + +/*! + \brief disable double PLL clock + \param[in] none + \param[out] none + \retval none +*/ +void rcu_double_pll_disable(void) +{ + RCU_CFG0 |= RCU_CFG0_DPLL; +} + +/*! + \brief enable RCU system reset + \param[in] reset_source: reset source + one or more parameters can be selected which is shown as below: + \arg RCU_SYSRST_LOCKUP: CPU lock-up reset + \arg RCU_SYSRST_LVD: low voltage detection reset + \arg RCU_SYSRST_ECC: ECC 2 bits error reset + \arg RCU_SYSRST_LOH: lost of HXTAL reset + \arg RCU_SYSRST_LOP: lost of PLL reset + \param[out] none + \retval none +*/ +void rcu_system_reset_enable(uint32_t reset_source) +{ + RCU_RSTSCK |= reset_source; +} + +/*! + \brief disable RCU system reset + \param[in] reset_source: reset source + one or more parameters can be selected which is shown as below: + \arg RCU_SYSRST_LOCKUP: CPU lock-up reset + \arg RCU_SYSRST_LVD: low voltage detection reset + \arg RCU_SYSRST_ECC: ECC 2 bits error reset + \arg RCU_SYSRST_LOH: lost of HXTAL reset + \arg RCU_SYSRST_LOP: lost of PLL reset + \param[out] none + \retval none +*/ +void rcu_system_reset_disable(uint32_t reset_source) +{ + RCU_RSTSCK &= ~reset_source; +} + +/*! + \brief configure the ADC prescaler factor + \param[in] adc_psc: ADC prescaler factor + only one parameter can be selected which is shown as below: + \arg RCU_CKADC_CKAHB_DIVx (x=2,3,...,32): ADC prescaler select CK_AHB/(x) + \param[out] none + \retval none +*/ +void rcu_adc_clock_config(uint32_t adc_psc) +{ + uint32_t reg; + /* reset the ADCPSC bits */ + reg = RCU_CFG2; + reg &= ~RCU_CFG2_ADCPSC; + /* set the ADC prescaler factor */ + reg |= adc_psc & RCU_CFG2_ADCPSC; + /* set the register */ + RCU_CFG2 = reg; +} + +/*! + \brief configure the RTC clock source selection + \param[in] rtc_clock_source: RTC clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_RTCSRC_NONE: no clock selected + \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock + \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock + \arg RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock + \param[out] none + \retval none +*/ +void rcu_rtc_clock_config(uint32_t rtc_clock_source) +{ + uint32_t reg; + reg = RCU_BDCTL; + /* reset the RTCSRC bits and set according to rtc_clock_source */ + reg &= ~RCU_BDCTL_RTCSRC; + RCU_BDCTL = (reg | rtc_clock_source); +} + +/*! + \brief configure the USART clock source selection + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] usart_clock_source: USART clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_USARTSRC_HXTAL: HXTAL clock selected as USART source clock + \arg RCU_USARTSRC_CKSYS: system clock selected as USART source clock + \arg RCU_USARTSRC_LXTAL: LXTAL clock selected as USART source clock + \arg RCU_USARTSRC_IRC8M: IRC8M clock selected as USART source clock + \param[out] none + \retval none +*/ +void rcu_usart_clock_config(uint32_t usart_periph, uint32_t usart_clock_source) +{ + uint32_t reg; + reg = RCU_CFG2; + switch(usart_periph) { + case USART0: + /* reset the USART0SEL bit and set according to usart_clock_source */ + reg &= ~RCU_CFG2_USART0SEL; + RCU_CFG2 = (reg | usart_clock_source); + break; + case USART1: + /* reset the USART1SEL bit and set according to usart_clock_source */ + reg &= ~RCU_CFG2_USART1SEL; + RCU_CFG2 = (reg | (uint32_t)(usart_clock_source << 4U)); + break; + case USART2: + /* reset the USART2SEL bit and set according to usart_clock_source */ + reg &= ~RCU_CFG2_USART2SEL; + RCU_CFG2 = (reg | (uint32_t)(usart_clock_source << 6U)); + break; + default: + break; + } +} + +/*! + \brief configure the CAN clock source selection + \param[in] can_periph: CANx(x=0,1) + \param[in] can_clock_source: CAN clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CANSRC_HXTAL: HXTAL clock selected as CAN source clock + \arg RCU_CANSRC_PCLK2: PCLK2 clock selected as CAN source clock + \arg RCU_CANSRC_PCLK2_DIV_2: PCLK2/2 clock selected as CAN source clock + \arg RCU_CANSRC_IRC8M: IRC8M clock selected as CAN source clock + \param[out] none + \retval none +*/ +void rcu_can_clock_config(uint32_t can_periph, uint32_t can_clock_source) +{ + uint32_t reg; + reg = RCU_CFG2; + switch(can_periph) { + case CAN0: + /* reset the CAN0SEL bits and set according to can_clock_source */ + reg &= ~RCU_CFG2_CAN0SEL; + RCU_CFG2 = (reg | can_clock_source); + break; + case CAN1: + /* reset the CAN1SEL bits and set according to can_clock_source */ + reg &= ~RCU_CFG2_CAN1SEL; + RCU_CFG2 = (reg | (uint32_t)(can_clock_source << 2U)); + break; + default: + break; + } +} + +/*! + \brief configure the LXTAL drive capability + \param[in] lxtal_dricap: drive capability of LXTAL + only one parameter can be selected which is shown as below: + \arg RCU_LXTAL_LOWDRI: lower driving capability + \arg RCU_LXTAL_MED_LOWDRI: medium low driving capability + \arg RCU_LXTAL_MED_HIGHDRI: medium high driving capability + \arg RCU_LXTAL_HIGHDRI: higher driving capability + \param[out] none + \retval none +*/ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) +{ + uint32_t reg; + reg = RCU_BDCTL; + /* reset the LXTALDRI bits and set according to lxtal_dricap */ + reg &= ~RCU_BDCTL_LXTALDRI; + RCU_BDCTL = (reg | lxtal_dricap); +} + +/*! + \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) +{ + uint32_t stb_cnt = 0U; + ErrStatus reval = ERROR; + FlagStatus osci_stat = RESET; + + switch(osci) { + /* wait HXTAL stable */ + case RCU_HXTAL: + while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); + stb_cnt++; + } + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) { + reval = SUCCESS; + } + break; + /* wait LXTAL stable */ + case RCU_LXTAL: + while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); + stb_cnt++; + } + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) { + reval = SUCCESS; + } + break; + /* wait IRC8M stable */ + case RCU_IRC8M: + while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); + stb_cnt++; + } + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)) { + reval = SUCCESS; + } + break; + /* wait IRC40K stable */ + case RCU_IRC40K: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); + stb_cnt++; + } + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)) { + reval = SUCCESS; + } + break; + /* wait PLL stable */ + case RCU_PLL_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); + stb_cnt++; + } + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) { + reval = SUCCESS; + } + break; + default: + break; + } + /* return value */ + return reval; +} + +/*! + \brief turn on the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \param[out] none + \retval none +*/ +void rcu_osci_on(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief turn off the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \param[out] none + \retval none +*/ +void rcu_osci_off(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) +{ + uint32_t reg; + + switch(osci) { + /* enable HXTAL to bypass mode */ + case RCU_HXTAL: + reg = RCU_CTL; + RCU_CTL &= ~RCU_CTL_HXTALEN; + RCU_CTL = (reg | RCU_CTL_HXTALBPS); + break; + /* enable LXTAL to bypass mode */ + case RCU_LXTAL: + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); + break; + default: + break; + } +} + +/*! + \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) +{ + uint32_t reg; + + switch(osci) { + /* disable HXTAL to bypass mode */ + case RCU_HXTAL: + reg = RCU_CTL; + RCU_CTL &= ~RCU_CTL_HXTALEN; + RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); + break; + /* disable LXTAL to bypass mode */ + case RCU_LXTAL: + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); + break; + default: + break; + } +} + +/*! + \brief HXTAL frequency scale select + \param[in] hxtal_scal: HXTAL frequency scale + only one parameter can be selected which is shown as below: + \arg HXTAL_SCALE_2M_TO_8M: HXTAL scale is 2-8MHz + \arg HXTAL_SCALE_8M_TO_40M: HXTAL scale is 8-40MHz + \param[out] none + \retval none +*/ +void rcu_hxtal_frequency_scale_select(uint32_t hxtal_scal) +{ + if(HXTAL_SCALE_2M_TO_8M == hxtal_scal) { + RCU_CTL &= ~RCU_CTL_HXTALSCAL; + } else { + RCU_CTL |= RCU_CTL_HXTALSCAL; + } +} + +/*! + \brief configure the HXTAL divider used as input of PLL + \param[in] hxtal_prediv: HXTAL previous PLL + only one parameter can be selected which is shown as below: + \arg RCU_PREDV_DIVx(x=1..16): HXTAL divided x used as input of PLL + \param[out] none + \retval none +*/ +void rcu_hxtal_prediv_config(uint32_t hxtal_prediv) +{ + uint32_t prediv = 0U; + prediv = RCU_CFG1; + /* reset the PREDV bits and set according to hxtal_prediv */ + prediv &= ~RCU_CFG1_PREDV; + RCU_CFG1 = (prediv | hxtal_prediv); +} + +/*! + \brief set the IRC8M adjust value + \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F + \arg 0x00 - 0x1F + \param[out] none + \retval none +*/ +void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval) +{ + uint32_t reg; + reg = RCU_CTL; + /* reset the IRC8MADJ bits and set according to irc8m_adjval */ + reg &= ~RCU_CTL_IRC8MADJ; + RCU_CTL = (reg | ((irc8m_adjval & RCU_IRC8M_ADJUST_MASK) << RCU_IRC8M_ADJUST_OFFSET)); +} + +/*! + \brief enable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_enable(void) +{ + RCU_CTL |= RCU_CTL_CKMEN; +} + +/*! + \brief disable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_disable(void) +{ + RCU_CTL &= ~RCU_CTL_CKMEN; +} + +/*! + \brief enable the LXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_lxtal_clock_monitor_enable(void) +{ + RCU_CTL |= RCU_CTL_LCKMEN; +} + +/*! + \brief disable the LXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_lxtal_clock_monitor_disable(void) +{ + RCU_CTL &= ~RCU_CTL_LCKMEN; +} + +/*! + \brief enable the PLL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_pll_clock_monitor_enable(void) +{ + RCU_CTL |= RCU_CTL_PLLMEN; +} + +/*! + \brief disable the PLL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_pll_clock_monitor_disable(void) +{ + RCU_CTL &= ~RCU_CTL_PLLMEN; +} + +/*! + \brief unlock the voltage key + \param[in] none + \param[out] none + \retval none +*/ +void rcu_voltage_key_unlock(void) +{ + /* reset the KEY bits and set 0x1A2B3C4D */ + RCU_VKEY = ~RCU_VKEY_KEY; + RCU_VKEY = RCU_VKEY_UNLOCK; +} + +/*! + \brief deep-sleep mode voltage select + \param[in] dsvol: deep sleep mode voltage + only one parameter can be selected which is shown as below: + \arg RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V + \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V + \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V + \arg RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V + \param[out] none + \retval none +*/ +void rcu_deepsleep_voltage_set(uint32_t dsvol) +{ + /* reset the DSLPVS bits and set according to dsvol */ + RCU_DSV &= ~RCU_DSV_DSLPVS; + RCU_DSV |= dsvol; +} + +/*! + \brief get the system clock, bus and peripheral clock frequency + \param[in] clock: the clock frequency which to get + only one parameter can be selected which is shown as below: + \arg CK_SYS: system clock frequency + \arg CK_AHB: AHB clock frequency + \arg CK_APB1: APB1 clock frequency + \arg CK_APB2: APB2 clock frequency + \arg CK_USART0: USART0 clock frequency + \arg CK_USART1: USART1 clock frequency + \arg CK_USART2: USART2 clock frequency + \param[out] none + \retval clock frequency of system, AHB, APB1, APB2, USART +*/ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) +{ + uint32_t sws, ck_freq = 0U; + uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; + uint32_t usart_freq = 0U; + uint32_t pllsel, pllmf, ck_src, idx, clk_exp; + uint32_t predv0; + + /* exponent of AHB, APB1 and APB2 clock divider */ + uint8_t ahb_exp[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + uint8_t apb1_exp[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + uint8_t apb2_exp[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + + sws = RCU_CFG0 & RCU_CFG0_SCSS; + switch(sws) { + /* IRC8M is selected as CK_SYS */ + case RCU_SCSS_IRC8M: + cksys_freq = IRC8M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case RCU_SCSS_HXTAL: + cksys_freq = HXTAL_VALUE; + break; + /* PLL is selected as CK_SYS */ + case RCU_SCSS_PLL: + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + if(RCU_PLLSRC_HXTAL == pllsel) { + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV) + 1U; + ck_src /= predv0; + } else { + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE / 2U; + } + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + pllmf += ((RCU_CFG0 & RCU_CFG0_PLLMF_4) ? 15U : 0U); + pllmf += ((RCU_CFG0_PLLMF == (RCU_CFG0 & RCU_CFG0_PLLMF)) ? 1U : 2U); + cksys_freq = ck_src * pllmf; + break; + /* IRC8M is selected as CK_SYS */ + default: + cksys_freq = IRC8M_VALUE; + break; + } + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + ahb_freq = cksys_freq >> clk_exp; + /* calculate APB1 clock frequency */ + idx = GET_BITS(RCU_CFG0, 8, 10); + clk_exp = apb1_exp[idx]; + apb1_freq = ahb_freq >> clk_exp; + /* calculate APB2 clock frequency */ + idx = GET_BITS(RCU_CFG0, 11, 13); + clk_exp = apb2_exp[idx]; + apb2_freq = ahb_freq >> clk_exp; + /* return the clocks frequency */ + switch(clock) { + case CK_SYS: + ck_freq = cksys_freq; + break; + case CK_AHB: + ck_freq = ahb_freq; + break; + case CK_APB1: + ck_freq = apb1_freq; + break; + case CK_APB2: + ck_freq = apb2_freq; + break; + case CK_USART0: + /* calculate USART0 clock frequency */ + if(RCU_USARTSRC_HXTAL == (RCU_CFG2 & RCU_CFG2_USART0SEL)) { + usart_freq = HXTAL_VALUE; + } else if(RCU_USARTSRC_CKSYS == (RCU_CFG2 & RCU_CFG2_USART0SEL)) { + usart_freq = cksys_freq; + } else if(RCU_USARTSRC_LXTAL == (RCU_CFG2 & RCU_CFG2_USART0SEL)) { + usart_freq = LXTAL_VALUE; + } else if(RCU_USARTSRC_IRC8M == (RCU_CFG2 & RCU_CFG2_USART0SEL)) { + usart_freq = IRC8M_VALUE; + } else { + } + ck_freq = usart_freq; + break; + case CK_USART1: + /* calculate USART1 clock frequency */ + if(RCU_USARTSRC_HXTAL == (uint32_t)((uint32_t)(RCU_CFG2 & RCU_CFG2_USART1SEL) >> 4U)) { + usart_freq = HXTAL_VALUE; + } else if(RCU_USARTSRC_CKSYS == (uint32_t)((uint32_t)(RCU_CFG2 & RCU_CFG2_USART1SEL) >> 4U)) { + usart_freq = cksys_freq; + } else if(RCU_USARTSRC_LXTAL == (uint32_t)((uint32_t)(RCU_CFG2 & RCU_CFG2_USART1SEL) >> 4U)) { + usart_freq = LXTAL_VALUE; + } else if(RCU_USARTSRC_IRC8M == (uint32_t)((uint32_t)(RCU_CFG2 & RCU_CFG2_USART1SEL) >> 4U)) { + usart_freq = IRC8M_VALUE; + } else { + } + ck_freq = usart_freq; + break; + case CK_USART2: + /* calculate USART2 clock frequency */ + if(RCU_USARTSRC_HXTAL == (uint32_t)((uint32_t)(RCU_CFG2 & RCU_CFG2_USART2SEL) >> 6U)) { + usart_freq = HXTAL_VALUE; + } else if(RCU_USARTSRC_CKSYS == (uint32_t)((uint32_t)(RCU_CFG2 & RCU_CFG2_USART2SEL) >> 6U)) { + usart_freq = cksys_freq; + } else if(RCU_USARTSRC_LXTAL == (uint32_t)((uint32_t)(RCU_CFG2 & RCU_CFG2_USART2SEL) >> 6U)) { + usart_freq = LXTAL_VALUE; + } else if(RCU_USARTSRC_IRC8M == (uint32_t)((uint32_t)(RCU_CFG2 & RCU_CFG2_USART2SEL) >> 6U)) { + usart_freq = IRC8M_VALUE; + } else { + } + ck_freq = usart_freq; + break; + default: + break; + } + return ck_freq; +} + +/*! + \brief get the clock stabilization and peripheral reset flags + \param[in] flag: the clock stabilization and peripheral reset flags, refer to rcu_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag + \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag + \arg RCU_FLAG_PLLSTB: PLL stabilization flag + \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag + \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag + \arg RCU_FLAG_BORRST: BOR reset flag + \arg RCU_FLAG_LOCKUPRST: CPU LOCK UP error reset flag + \arg RCU_FLAG_LVDRST: low voltage detect error reset flag + \arg RCU_FLAG_ECCRST: 2 bits ECC error reset flag + \arg RCU_FLAG_LOHRST: lost of HXTAL error reset flag + \arg RCU_FLAG_LOPRST: lost of PLL error reset flag + \arg RCU_FLAG_V11RST: 1.1V domain Power reset flag + \arg RCU_FLAG_OBLRST: option byte loader reset flag + \arg RCU_FLAG_EPRST: external PIN reset flags + \arg RCU_FLAG_PORRST: power reset flag + \arg RCU_FLAG_SWRST: software reset flag + \arg RCU_FLAG_FWDGTRST: FWDGT reset flag + \arg RCU_FLAG_WWDGTRST: WWDGT reset flag + \arg RCU_FLAG_LPRST: low-power reset flag + \param[out] none + \retval none +*/ +FlagStatus rcu_flag_get(rcu_flag_enum flag) +{ + /* get the rcu flag */ + if(0U != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear all the reset flag + \param[in] none + \param[out] none + \retval none +*/ +void rcu_all_reset_flag_clear(void) +{ + RCU_RSTSCK |= RCU_RSTSCK_RSTFC; +} + +/*! + \brief get the clock stabilization interrupt and ckm flags + \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag + \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag + \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag + \arg RCU_INT_FLAG_LCKM: LXTAL clock monitor interrupt flag + \arg RCU_INT_FLAG_PLLM: PLL clock monitor interrupt flag + \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) +{ + /* get the rcu interrupt flag */ + if(0U != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the interrupt flags + \param[in] int_flag: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear + \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear + \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear + \arg RCU_INT_FLAG_LCKM_CLR: LXTAL clock monitor interrupt flag clear + \arg RCU_INT_FLAG_PLLM_CLR: PLL clock monitor interrupt flag clear + \arg RCU_INT_FLAG_CKM_CLR: HXTAL clock monitor interrupt flag clear + \param[out] none + \retval none +*/ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag) +{ + RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag)); +} + +/*! + \brief enable the stabilization interrupt + \param[in] interrupt clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt + \arg RCU_INT_PLLSTB: PLL stabilization interrupt + \arg RCU_INT_LCKM: LXTAL clock monitor interrupt + \arg RCU_INT_PLLM: PLL clock monitor interrupt + \param[out] none + \retval none +*/ +void rcu_interrupt_enable(rcu_int_enum interrupt) +{ + RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt)); +} + +/*! + \brief disable the stabilization interrupt + \param[in] interrupt clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt + \arg RCU_INT_PLLSTB: PLL stabilization interrupt + \arg RCU_INT_LCKM: LXTAL clock monitor interrupt + \arg RCU_INT_PLLM: PLL clock monitor interrupt + \param[out] none + \retval none +*/ +void rcu_interrupt_disable(rcu_int_enum interrupt) +{ + RCU_REG_VAL(interrupt) &= ~BIT(RCU_BIT_POS(interrupt)); +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_rtc.c b/gd32a50x/standard_peripheral/source/gd32a50x_rtc.c new file mode 100644 index 0000000..254ce9a --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_rtc.c @@ -0,0 +1,260 @@ +/*! + \file gd32a50x_rtc.c + \brief RTC driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_rtc.h" + +/*! + \brief enter RTC configuration mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_configuration_mode_enter(void) +{ + RTC_CTL |= RTC_CTL_CMF; +} + +/*! + \brief exit RTC configuration mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_configuration_mode_exit(void) +{ + RTC_CTL &= ~RTC_CTL_CMF; +} + +/*! + \brief wait RTC last write operation finished flag set + \param[in] none + \param[out] none + \retval none +*/ +void rtc_lwoff_wait(void) +{ + /* loop until LWOFF flag is set */ + while (0U == (RTC_CTL & RTC_CTL_LWOFF)){ + } +} + +/*! + \brief wait RTC registers synchronized flag set + \param[in] none + \param[out] none + \retval none +*/ +void rtc_register_sync_wait(void) +{ + /* clear RSYNF flag */ + RTC_CTL &= ~RTC_CTL_RSYNF; + /* loop until RSYNF flag is set */ + while (0U == (RTC_CTL & RTC_CTL_RSYNF)){ + } +} + +/*! + \brief get RTC counter value + \param[in] none + \param[out] none + \retval RTC counter value +*/ +uint32_t rtc_counter_get(void) +{ + uint32_t temp = 0x0U; + temp = RTC_CNTL; + temp |= (RTC_CNTH << 16); + return temp; +} + +/*! + \brief set RTC counter value + \param[in] cnt: RTC counter value + \param[out] none + \retval none +*/ +void rtc_counter_set(uint32_t cnt) +{ + rtc_configuration_mode_enter(); + /* set the RTC counter high bits */ + RTC_CNTH = cnt >> 16; + /* set the RTC counter low bits */ + RTC_CNTL = (cnt & RTC_LOW_VALUE); + rtc_configuration_mode_exit(); +} + +/*! + \brief set RTC prescaler value + \param[in] psc: RTC prescaler value + \param[out] none + \retval none +*/ +void rtc_prescaler_set(uint32_t psc) +{ + rtc_configuration_mode_enter(); + /* set the RTC prescaler high bits */ + RTC_PSCH = (psc & RTC_HIGH_VALUE) >> 16; + /* set the RTC prescaler low bits */ + RTC_PSCL = (psc & RTC_LOW_VALUE); + rtc_configuration_mode_exit(); +} + +/*! + \brief set RTC alarm value + \param[in] alarm: RTC alarm value + \param[out] none + \retval none +*/ +void rtc_alarm_config(uint32_t alarm) +{ + rtc_configuration_mode_enter(); + /* set the alarm high bits */ + RTC_ALRMH = alarm >> 16; + /* set the alarm low bits */ + RTC_ALRML = (alarm & RTC_LOW_VALUE); + rtc_configuration_mode_exit(); +} + +/*! + \brief get RTC divider value + \param[in] none + \param[out] none + \retval RTC divider value +*/ +uint32_t rtc_divider_get(void) +{ + uint32_t temp = 0x00U; + temp = (RTC_DIVH & RTC_DIVH_DIV) << 16; + temp |= RTC_DIVL; + return temp; +} + +/*! + \brief enable RTC interrupt + \param[in] interrupt: specify which interrupt to enbale + \arg RTC_INT_SECOND: second interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_OVERFLOW: overflow interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_enable(uint32_t interrupt) +{ + RTC_INTEN |= interrupt; +} + +/*! + \brief disable RTC interrupt + \param[in] interrupt: specify which interrupt to disbale + \arg RTC_INT_SECOND: second interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_OVERFLOW: overflow interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_disable(uint32_t interrupt) +{ + RTC_INTEN &= ~interrupt; +} + +/*! + \brief get RTC flag status + \param[in] flag: specify which flag status to get + \arg RTC_FLAG_SECOND: second interrupt flag + \arg RTC_FLAG_ALARM: alarm interrupt flag + \arg RTC_FLAG_OVERFLOW: overflow interrupt flag + \arg RTC_FLAG_RSYN: registers synchronized flag + \arg RTC_FLAG_LWOF: last write operation finished flag + \param[out] none + \retval SET or RESET +*/ +FlagStatus rtc_flag_get(uint32_t flag) +{ + if(0U != (RTC_CTL & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear RTC flag status + \param[in] flag: specify which flag status to clear + \arg RTC_FLAG_SECOND: second interrupt flag + \arg RTC_FLAG_ALARM: alarm interrupt flag + \arg RTC_FLAG_OVERFLOW: overflow interrupt flag + \arg RTC_FLAG_RSYN: registers synchronized flag + \param[out] none + \retval none +*/ +void rtc_flag_clear(uint32_t flag) +{ + /* clear RTC flag */ + RTC_CTL &= ~flag; +} + +/*! + \brief get RTC interrupt flag status + \param[in] flag: specify which flag status to get + only one parameter can be selected which is shown as below: + \arg RTC_INT_FLAG_SECOND: second interrupt flag + \arg RTC_INT_FLAG_ALARM: alarm interrupt flag + \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag + \param[out] none + \retval SET or RESET +*/ +FlagStatus rtc_interrupt_flag_get(uint32_t flag) +{ + if(0U != (RTC_CTL & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear RTC interrupt flag status + \param[in] flag: specify which flag status to clear + one or more parameters can be selected which are shown as below: + \arg RTC_INT_FLAG_SECOND: second interrupt flag + \arg RTC_INT_FLAG_ALARM: alarm interrupt flag + \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag + \param[out] none + \retval none +*/ +void rtc_interrupt_flag_clear(uint32_t flag) +{ + /* clear RTC interrupt flag */ + RTC_CTL &= ~flag; +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_spi.c b/gd32a50x/standard_peripheral/source/gd32a50x_spi.c new file mode 100644 index 0000000..4507677 --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_spi.c @@ -0,0 +1,803 @@ +/*! + \file gd32fa50x_spi.c + \brief SPI driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_spi.h" + +#define SPI_ERROR_HANDLE(s) do{}while(1) + +/* SPI/I2S parameter initialization mask */ +#define SPI_INIT_MASK ((uint32_t)0x00003040U) +#define I2S_INIT_MASK ((uint32_t)0x0000F047U) +#define I2S_FULL_DUPLEX_MASK ((uint32_t)0x0000F040U) + +/* default value */ +#define SPI_I2SPSC_RESET ((uint32_t)0x00000002U) /*!< default value of SPI_I2SPSC register */ + +/* I2S clock source selection, multiplication and division mask */ +#define I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /*!< I2S1 clock source selection */ +#define I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /*!< I2S2 clock source selection */ +#define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /*!< I2S clock multiplication mask */ +#define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /*!< I2S clock division mask */ + +/*! + \brief reset SPI and I2S + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_i2s_deinit(uint32_t spi_periph) +{ + switch(spi_periph){ + case SPI0: + /* reset SPI0 */ + rcu_periph_reset_enable(RCU_SPI0RST); + rcu_periph_reset_disable(RCU_SPI0RST); + break; + case SPI1: + /* reset SPI1 and I2S1 */ + rcu_periph_reset_enable(RCU_SPI1RST); + rcu_periph_reset_disable(RCU_SPI1RST); + break; + default : + break; + } +} + +/*! + \brief initialize the parameters of SPI structure with the default values + \param[in] none + \param[out] spi_struct: the initialized structure spi_parameter_struct pointer + \retval none +*/ +void spi_struct_para_init(spi_parameter_struct *spi_struct) +{ + /* configure the SPI structure with the default values */ + spi_struct->device_mode = SPI_SLAVE; + spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_struct->frame_size = SPI_FRAMESIZE_8BIT; + spi_struct->nss = SPI_NSS_HARD; + spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + spi_struct->prescale = SPI_PSC_2; + spi_struct->endian = SPI_ENDIAN_MSB; +} + +/*! + \brief initialize SPI parameter + \param[in] spi_periph: SPIx(x=0,1) + \param[in] spi_struct: SPI parameter initialization stuct members of the structure + and the member values are shown as below: + device_mode: SPI_MASTER, SPI_SLAVE + trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, + SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT + frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT + nss: SPI_NSS_SOFT, SPI_NSS_HARD + endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB + clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE + SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE + prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) + \param[out] none + \retval none +*/ +void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) +{ + uint32_t reg = 0U; + reg = SPI_CTL0(spi_periph); + reg &= SPI_INIT_MASK; + + /* select SPI as master or slave */ + reg |= spi_struct->device_mode; + /* select SPI transfer mode */ + reg |= spi_struct->trans_mode; + /* select SPI frame size */ + reg |= spi_struct->frame_size; + /* select SPI NSS use hardware or software */ + reg |= spi_struct->nss; + /* select SPI LSB or MSB */ + reg |= spi_struct->endian; + /* select SPI polarity and phase */ + reg |= spi_struct->clock_polarity_phase; + /* select SPI prescale to adjust transmit speed */ + reg |= spi_struct->prescale; + + /* write to SPI_CTL0 register */ + SPI_CTL0(spi_periph) = (uint32_t)reg; + + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); +} + +/*! + \brief enable SPI + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_enable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; +} + +/*! + \brief disable SPI + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_disable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); +} + +/*! + \brief initialize I2S parameter + \param[in] spi_periph: SPI1 + \param[in] i2s_mode: I2S operation mode + only one parameter can be selected which is shown as below: + \arg I2S_MODE_SLAVETX: I2S slave transmit mode + \arg I2S_MODE_SLAVERX: I2S slave receive mode + \arg I2S_MODE_MASTERTX: I2S master transmit mode + \arg I2S_MODE_MASTERRX: I2S master receive mode + \param[in] i2s_standard: I2S standard + only one parameter can be selected which is shown as below: + \arg I2S_STD_PHILLIPS: I2S phillips standard + \arg I2S_STD_MSB: I2S MSB standard + \arg I2S_STD_LSB: I2S LSB standard + \arg I2S_STD_PCMSHORT: I2S PCM short standard + \arg I2S_STD_PCMLONG: I2S PCM long standard + \param[in] i2s_ckpl: I2S idle state clock polarity + only one parameter can be selected which is shown as below: + \arg I2S_CKPL_LOW: I2S clock polarity low level + \arg I2S_CKPL_HIGH: I2S clock polarity high level + \param[out] none + \retval none +*/ +void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl) +{ + uint32_t reg= 0U; + reg = SPI_I2SCTL(spi_periph); + reg &= I2S_INIT_MASK; + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)i2s_mode; + /* select I2S standard */ + reg |= (uint32_t)i2s_standard; + /* select I2S polarity */ + reg |= (uint32_t)i2s_ckpl; + + /* write to SPI_I2SCTL register */ + SPI_I2SCTL(spi_periph) = (uint32_t)reg; +} + +/*! + \brief configure I2S prescaler + \param[in] spi_periph: SPI1 + \param[in] i2s_audiosample: I2S audio sample rate + only one parameter can be selected which is shown as below: + \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz + \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz + \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz + \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz + \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz + \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz + \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz + \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz + \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz + \param[in] i2s_frameformat: I2S data length and channel length + only one parameter can be selected which is shown as below: + \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit + \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \param[in] i2s_mckout: I2S master clock output + only one parameter can be selected which is shown as below: + \arg I2S_MCKOUT_ENABLE: I2S master clock output enable + \arg I2S_MCKOUT_DISABLE: I2S master clock output disable + \param[out] none + \retval none +*/ +void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout) +{ + uint32_t i2sdiv = 2U, i2sof = 0U; + uint32_t clks = 0U; + uint32_t i2sclock = 0U; + + /* judge whether the audiosample is 0 */ + if(0U == i2s_audiosample){ + SPI_ERROR_HANDLE("the parameter can not be 0 \r\n"); + } + + /* deinitialize SPI_I2SPSC register */ + SPI_I2SPSC(spi_periph) = SPI_I2SPSC_RESET; + + /* get the I2S clock source */ + if(SPI1 == ((uint32_t)spi_periph)) { + /* I2S1 clock source selection */ + clks = I2S1_CLOCK_SEL; + }else{ + /* I2S2 clock source selection */ + clks = I2S2_CLOCK_SEL; + } + + if(0U != (RCU_CFG1 & clks)){ + /* get RCU PLL2 clock multiplication factor */ + clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> 12U); + + if((clks > 5U) && (clks < 15U)){ + /* multiplier is between 8 and 14 */ + clks += 2U; + }else{ + if(15U == clks){ + /* multiplier is 20 */ + clks = 20U; + } + } + + /* get the PREDV1 value */ + i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> 4U) + 1U); + /*calculate I2S clock based on PLL2 and PREDV1 */ + i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U); + }else{ + /* get system clock */ + i2sclock = rcu_clock_freq_get(CK_SYS); + } + + /* configure the prescaler depending on the mclk output state, the frame format and audio sample rate */ + if(I2S_MCKOUT_ENABLE == i2s_mckout){ + clks = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample); + }else{ + if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat){ + clks = (uint32_t)(((i2sclock / 32U) *10U ) / i2s_audiosample); + }else{ + clks = (uint32_t)(((i2sclock / 64U) *10U ) / i2s_audiosample); + } + } + + /* remove the floating point */ + clks = (clks + 5U) / 10U; + i2sof = (clks & 0x00000001U); + i2sdiv = ((clks - i2sof) / 2U); + i2sof = (i2sof << 8U); + + /* set the default values */ + if((i2sdiv < 2U) || (i2sdiv > 255U)){ + i2sdiv = 2U; + i2sof = 0U; + } + + /* configure SPI_I2SPSC */ + SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | i2s_mckout); + + /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); + + /* configure data frame format */ + SPI_I2SCTL(spi_periph) |= (uint32_t)i2s_frameformat; +} + +/*! + \brief enable I2S + \param[in] spi_periph: SPI1 + \param[out] none + \retval none +*/ +void i2s_enable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; +} + +/*! + \brief disable I2S + \param[in] spi_periph: SPI1 + \param[out] none + \retval none +*/ +void i2s_disable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); +} + +/*! + \brief enable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nss_output_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; +} + +/*! + \brief disable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nss_output_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); +} + +/*! + \brief SPI NSS pin high level in software mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nss_internal_high(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; +} + +/*! + \brief SPI NSS pin low level in software mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nss_internal_low(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); +} + +/*! + \brief enable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1) + \param[in] spi_dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA + \arg SPI_DMA_RECEIVE: SPI receive data using DMA + \param[out] none + \retval none +*/ +void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma) +{ + if(SPI_DMA_TRANSMIT == spi_dma){ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; + }else{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; + } +} + +/*! + \brief disable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1) + \param[in] spi_dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA + \arg SPI_DMA_RECEIVE: SPI receive data using DMA + \param[out] none + \retval none +*/ +void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma) +{ + if(SPI_DMA_TRANSMIT == spi_dma){ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); + }else{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); + } +} + +/*! + \brief configure SPI data frame format + \param[in] spi_periph: SPIx(x=0,1) + \param[in] frame_format: SPI frame size + only one parameter can be selected which is shown as below: + \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits + \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits + \param[out] none + \retval none +*/ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) +{ + /* clear SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); + /* confige SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) |= (uint32_t)frame_format; +} + +/*! + \brief configure SPI bidirectional transfer direction + \param[in] spi_periph: SPIx(x=0,1) + \param[in] transfer_direction: SPI transfer direction + only one parameter can be selected which is shown as below: + \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode + \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode + \param[out] none + \retval none +*/ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) +{ + if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ + /* set the transmit only mode */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; + }else{ + /* set the receive only mode */ + SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; + } +} + +/*! + \brief SPI transmit data + \param[in] spi_periph: SPIx(x=0,1) + \param[in] data: 16-bit data + \param[out] none + \retval none +*/ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) +{ + SPI_DATA(spi_periph) = (uint32_t)data; +} + +/*! + \brief SPI receive data + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval 16-bit data +*/ +uint16_t spi_i2s_data_receive(uint32_t spi_periph) +{ + return ((uint16_t)SPI_DATA(spi_periph)); +} +/*! + \brief set SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1) + \param[in] crc_poly: CRC polynomial value + \param[out] none + \retval none +*/ +void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly) +{ + /* enable SPI CRC */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; + + /* set SPI CRC polynomial */ + SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; +} + +/*! + \brief get SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval 16-bit CRC polynomial +*/ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph) +{ + return ((uint16_t)SPI_CRCPOLY(spi_periph)); +} + +/*! + \brief turn on CRC function + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_crc_on(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; +} + +/*! + \brief turn off CRC function + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_crc_off(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); +} + +/*! + \brief SPI next data is CRC value + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_crc_next(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; +} + +/*! + \brief get SPI CRC send value or receive value + \param[in] spi_periph: SPIx(x=0,1) + \param[in] crc: SPI crc value + only one parameter can be selected which is shown as below: + \arg SPI_CRC_TX: get transmit crc value + \arg SPI_CRC_RX: get receive crc value + \param[out] none + \retval 16-bit CRC value +*/ +uint16_t spi_crc_get(uint32_t spi_periph,uint8_t crc) +{ + if(SPI_CRC_TX == crc){ + return ((uint16_t)(SPI_TCRC(spi_periph))); + }else{ + return ((uint16_t)(SPI_RCRC(spi_periph))); + } +} + +/*! + \brief enable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_ti_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; +} + +/*! + \brief disable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_ti_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); +} + +/*! + \brief enable SPI NSS pulse mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nssp_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; +} + +/*! + \brief disable SPI NSS pulse mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nssp_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); +} + +/*! + \brief enable quad wire SPI + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void spi_quad_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; +} + +/*! + \brief disable quad wire SPI + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void spi_quad_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); +} + +/*! + \brief enable quad wire SPI write + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void spi_quad_write_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); +} + +/*! + \brief enable quad wire SPI read + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void spi_quad_read_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; +} + +/*! + \brief enable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void spi_quad_io23_output_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; +} + + /*! + \brief disable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ + void spi_quad_io23_output_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); +} + +/*! + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1) + \param[in] flag: SPI/I2S flag status + only one parameter can be selected which is shown as below: + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg SPI_FLAG_FERR: format error flag + \arg I2S_FLAG_TBE: transmit buffer empty flag + \arg I2S_FLAG_RBNE: receive buffer not empty flag + \arg I2S_FLAG_TRANS: transmit on-going flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \arg I2S_FLAG_FERR: format error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) +{ + if(RESET != (SPI_STAT(spi_periph) & flag)) { + return SET; + }else{ + return RESET; + } +} +/*! + \brief enable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1) + \param[in] interrupt: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) +{ + SPI_CTL1(spi_periph) |= (uint32_t)interrupt; +} + +/*! + \brief disable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1) + \param[in] interrupt: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) +{ + SPI_CTL1(spi_periph) &= ~(uint32_t)interrupt; +} + +/*! + \brief get SPI and I2S interrupt flag status + \param[in] spi_periph: SPIx(x=0,1) + \param[in] interrupt: SPI/I2S interrupt flag status + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag + \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag + \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag + \arg SPI_INT_FLAG_CONFERR: config error interrupt flag + \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag + \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag + \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) +{ + uint32_t reg1 = SPI_STAT(spi_periph); + uint32_t reg2 = SPI_CTL1(spi_periph); + + switch(interrupt){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_FLAG_TBE: + reg1 = reg1 & SPI_STAT_TBE; + reg2 = reg2 & SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_FLAG_RBNE: + reg1 = reg1 & SPI_STAT_RBNE; + reg2 = reg2 & SPI_CTL1_RBNEIE; + break; + /* SPI/I2S overrun interrupt */ + case SPI_I2S_INT_FLAG_RXORERR: + reg1 = reg1 & SPI_STAT_RXORERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI config error interrupt */ + case SPI_INT_FLAG_CONFERR: + reg1 = reg1 & SPI_STAT_CONFERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI CRC error interrupt */ + case SPI_INT_FLAG_CRCERR: + reg1 = reg1 & SPI_STAT_CRCERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* I2S underrun error interrupt */ + case I2S_INT_FLAG_TXURERR: + reg1 = reg1 & SPI_STAT_TXURERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI/I2S format error interrupt */ + case SPI_I2S_INT_FLAG_FERR: + reg1 = reg1 & SPI_STAT_FERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + default : + break; + } + /*get SPI/I2S interrupt flag status */ + if((0U != reg1) && (0U != reg2)) { + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear SPI CRC error flag status + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_crc_error_clear(uint32_t spi_periph) +{ + SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_syscfg.c b/gd32a50x/standard_peripheral/source/gd32a50x_syscfg.c new file mode 100644 index 0000000..58fa05a --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_syscfg.c @@ -0,0 +1,453 @@ +/*! + \file gd32a50x_syscfg.c + \brief SYSCFG driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_syscfg.h" + +/* SYSCFG parameter mask */ +#define SYSCFG_TIMER0_ETI_SEL_MASK (uint32_t)0x3FFFFFFFU /*!< mask value of SYSCFG_TIMER0_ETI_SEL bits */ +#define SYSCFG_TIMER7_ETI_SEL_MASK (uint32_t)0xCFFFFFFFU /*!< mask value of SYSCFG_TIMER7_ETI_SEL bits */ +#define SYSCFG_TIMER19_ETI_SEL_MASK (uint32_t)0xFCFFFFFFU /*!< mask value of SYSCFG_TIMER19_ETI_SEL bits */ +#define SYSCFG_TIMER20_ETI_SEL_MASK (uint32_t)0xFF3FFFFFU /*!< mask value of SYSCFG_TIMER20_ETI_SEL bits */ +#define SYSCFG_CFG0_BOOTMODE_MASK (uint8_t)0x03U /*!< mask value of SYSCFG_CFG0_BOOT_MODE bits */ + +/* SYSCFG parameter offset */ +#define SYSCFG_TIMER0_ETI_SEL_OFFSET (uint32_t)30U /*!< offset value of SYSCFG_TIMER0_ETI_SEL bits */ +#define SYSCFG_TIMER7_ETI_SEL_OFFSET (uint32_t)28U /*!< offset value of SYSCFG_TIMER7_ETI_SEL bits */ +#define SYSCFG_TIMER19_ETI_SEL_OFFSET (uint32_t)24U /*!< offset value of SYSCFG_TIMER19_ETI_SEL bits */ +#define SYSCFG_TIMER20_ETI_SEL_OFFSET (uint32_t)22U /*!< offset value of SYSCFG_TIMER20_ETI_SEL bits */ +#define SYSCFG_CFG3_SRAMECCEADDR_OFFSET (uint8_t)18U /*!< offset value of SYSCFG_CFG3_SRAMECCEADDR bits */ +#define SYSCFG_CFG3_SRAMECCSERRBIT_OFFSET (uint8_t)12U /*!< offset value of SYSCFG_CFG3_SRAMECCSERRBITS bits */ + +/*! + \brief reset the SYSCFG registers + \param[in] none + \param[out] none + \retval none +*/ +void syscfg_deinit(void) +{ + rcu_periph_reset_enable(RCU_SYSCFGRST); + rcu_periph_reset_disable(RCU_SYSCFGRST); +} + +/*! + \brief configure the GPIO pin as EXTI Line + \param[in] exti_port: specify the gpio port used in EXTI + only one parameter can be selected which is shown as below: + \arg EXTI_SOURCE_GPIOx(x = A,B,C,D,E,F): EXTI gpio port + \param[in] exti_pin: specify the EXTI line + only one parameter can be selected which is shown as below: + \arg EXTI_SOURCE_PINx(for GPIOA\GPIOB\GPIOC\GPIOD\GPIOE, x = 0..15, for GPIOF, x = 0..7): EXTI GPIO pin + \param[out] none + \retval none +*/ +void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin) +{ + uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin))); + uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin)); + + switch(exti_pin / EXTI_SS_JSTEP) { + case EXTISS0: + /* clear EXTI source line(0..3) */ + SYSCFG_EXTISS0 &= clear_exti_mask; + /* configure EXTI soure line(0..3) */ + SYSCFG_EXTISS0 |= config_exti_mask; + break; + case EXTISS1: + /* clear EXTI soure line(4..7) */ + SYSCFG_EXTISS1 &= clear_exti_mask; + /* configure EXTI soure line(4..7) */ + SYSCFG_EXTISS1 |= config_exti_mask; + break; + case EXTISS2: + /* clear EXTI soure line(8..11) */ + SYSCFG_EXTISS2 &= clear_exti_mask; + /* configure EXTI soure line(8..11) */ + SYSCFG_EXTISS2 |= config_exti_mask; + break; + case EXTISS3: + /* clear EXTI soure line(12..15) */ + SYSCFG_EXTISS3 &= clear_exti_mask; + /* configure EXTI soure line(12..15) */ + SYSCFG_EXTISS3 |= config_exti_mask; + break; + default: + break; + } +} + +/*! + \brief enable remap pin function + \param[in] remap_pin: specify pin + only one parameter can be selected which are shown as below: + \arg SYSCFG_PA9_PA12_REMAP: PA9/PA12 pins are mapping on PA10/PA11 pins + \arg SYSCFG_BOOT0_REMAP_PF0: PF0 pin is mapping on the BOOT0 pin + \param[out] none + \retval none +*/ +void syscfg_pin_remap_enable(uint32_t remap_pin) +{ + SYSCFG_CFG0 |= remap_pin; +} + +/*! + \brief disable remap pin function + \param[in] remap_pin: specify pin + only one parameter can be selected which are shown as below: + \arg SYSCFG_PA9_PA12_REMAP: PA9/PA12 pins are mapping on PA10/PA11 pins + \arg SYSCFG_BOOT0_REMAP_PF0: PF0 pin is mapping on the BOOT0 pin + \param[out] none + \retval none +*/ +void syscfg_pin_remap_disable(uint32_t remap_pin) +{ + SYSCFG_CFG0 &= ~remap_pin; +} + +/*! + \brief configure ADC channel GPIO pin remap function + \param[in] adcx_iny_remap: specify ADC channel + only one parameter can be returned which is shown as below: + \arg ADC1_IN14_REMAP: ADC1 channel 14 GPIO pin remap + \arg ADC1_IN15_REMAP: ADC1 channel 15 GPIO pin remap + \arg ADC0_IN8_REMAP: ADC0 channel 8 GPIO pin remap + \arg ADC0_IN9_REMAP: ADC0 channel 9 GPIO pin remap + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void syscfg_adc_ch_remap_config(syscfg_adcx_chy_enum adcx_iny_remap, ControlStatus newvalue) +{ + switch(adcx_iny_remap) { + case ADC1_IN14_REMAP: + /* configure ADC1 channel 14 pin remap function */ + if(ENABLE == newvalue) { + SYSCFG_CFG1 |= SYSCFG_CFG1_ADC1CH14RMP; + } else { + SYSCFG_CFG1 &= (~SYSCFG_CFG1_ADC1CH14RMP); + } + break; + case ADC1_IN15_REMAP: + /* configure ADC1 channel 15 pin remap function */ + if(ENABLE == newvalue) { + SYSCFG_CFG1 |= SYSCFG_CFG1_ADC1CH15RMP; + } else { + SYSCFG_CFG1 &= (~SYSCFG_CFG1_ADC1CH15RMP); + } + break; + case ADC0_IN8_REMAP: + /* configure ADC0 channel 8 pin remap function */ + if(ENABLE == newvalue) { + SYSCFG_CFG1 |= SYSCFG_CFG1_ADC0CH8RMP; + } else { + SYSCFG_CFG1 &= (~SYSCFG_CFG1_ADC0CH8RMP); + } + break; + case ADC0_IN9_REMAP: + /* configure ADC0 channel 9 pin remap function */ + if(ENABLE == newvalue) { + SYSCFG_CFG1 |= SYSCFG_CFG1_ADC0CH9RMP; + } else { + SYSCFG_CFG1 &= (~SYSCFG_CFG1_ADC0CH9RMP); + } + break; + default: + break; + } +} + +/*! + \brief select TIMER external trigger source + \param[in] timer_num: specify TIMER + only one parameter can be returned which is shown as below: + \arg TIMER0SEL: select TIMER0 + \arg TIMER7SEL: select TIMER7 + \arg TIMER19SEL: select TIMER19 + \arg TIMER20SEL: select TIMER20 + \param[in] etr_num: specify external trigger source + only one parameter can be returned which is shown as below: + \arg TIMER_ETI_TRGx (x = 0,1,2,3): TIMER external trigger source x + \arg TIMER_ETI_TRG_NONE: do not seclet TIMER external trigger source + \param[out] none + \retval none +*/ +void syscfg_timer_eti_sel(syscfg_timersel_enum timer_num, uint32_t eti_num) +{ + switch(timer_num) { + case TIMER0SEL: + /* select TIMER0 external trigger source */ + SYSCFG_TIMERINSEL &= SYSCFG_TIMER0_ETI_SEL_MASK; + SYSCFG_TIMERINSEL |= (eti_num << SYSCFG_TIMER0_ETI_SEL_OFFSET); + break; + case TIMER7SEL: + /* select TIMER7 external trigger source */ + SYSCFG_TIMERINSEL &= SYSCFG_TIMER7_ETI_SEL_MASK; + SYSCFG_TIMERINSEL |= (eti_num << SYSCFG_TIMER7_ETI_SEL_OFFSET); + break; + case TIMER19SEL: + /* select TIMER19 external trigger source */ + SYSCFG_TIMERINSEL &= SYSCFG_TIMER19_ETI_SEL_MASK; + SYSCFG_TIMERINSEL |= (eti_num << SYSCFG_TIMER19_ETI_SEL_OFFSET); + break; + case TIMER20SEL: + /* select TIMER20 external trigger source */ + SYSCFG_TIMERINSEL &= SYSCFG_TIMER20_ETI_SEL_MASK; + SYSCFG_TIMERINSEL |= (eti_num << SYSCFG_TIMER20_ETI_SEL_OFFSET); + break; + default: + break; + } +} + +/*! + \brief select TRIGSEL as TIMER break input source + \param[in] bkin_source: specify TIMER break input source + only one parameter can be selected which are shown as below: + \arg TIMERx_BKINy_TRIG (x=0,7,19,20 y=0,1,2,3):TIMERx break input y source select from TRIGSEL + \param[out] none + \retval none +*/ +void syscfg_timer_bkin_select_trigsel(uint32_t bkin_source) +{ + SYSCFG_TIMERINSEL |= (uint32_t)bkin_source; +} + +/*! + \brief select GPIO as TIMER break input source + \param[in] bkin_source: specify TIMER break input source + only one parameter can be selected which are shown as below: + \arg TIMERx_BKINy_TRIG (x=0,7,19,,20 y=0,1,2,3): TIMERx break input y source select from TRIGSEL + \param[out] none + \retval none +*/ +void syscfg_timer_bkin_select_gpio(uint32_t bkin_source) +{ + SYSCFG_TIMERINSEL &= ~(uint32_t)bkin_source; +} + +/*! + \brief select TIMER7 channel0 complementary input source + \param[in] timer7_ch0n_in: specify TIMER7 channel0 complementary input source + only one parameter can be returned which is shown as below: + \arg TIMER7CH0N_TIMER7CH0_TIMER0CH0_IN : select exclusive or of TIMER7_CH0_IN, TIMER7_CH0N_IN, and TIMER0_CH0_IN + \arg TIMER7_CH0N_IN : select TIMER7_CH0N_IN + \param[out] none + \retval none +*/ +void syscfg_timer7_ch0n_select(uint32_t timer7_ch0n_in) +{ + if(TIMER7CH0N_TIMER7CH0_TIMER0CH0_IN == timer7_ch0n_in) { + /* select exclusive or of TIMER7_CH0_IN, TIMER7_CH0N_IN, and TIMER0_CH0_IN */ + SYSCFG_TIMERINSEL |= SYSCFG_TIMERINSEL_TIMER7_CH0N_SEL; + } else { + /* select TIMER7_CH0N_IN */ + SYSCFG_TIMERINSEL &= TIMER7_CH0N_IN; + } +} + +/*! + \brief configure TIMER0/7/19/20 break input to the selected parameter connection + \param[in] syscfg_lock: specify the parameter to be connected + only one parameter can be selected which is shown as below: + \arg SYSCFG_LOCK_LOCKUP: Cortex-M33 lockup output connected to the break input + \arg SYSCFG_LOCK_SRAM_ECC_ERROR: SRAM ECC check error connected to the break input + \arg SYSCFG_LOCK_LVD: LVD interrupt connected to the break input + \param[out] none + \retval none +*/ +void syscfg_lock_config(uint32_t syscfg_lock) +{ + SYSCFG_CFG2 |= syscfg_lock; +} + +/*! + \brief get SYSCFG flags + \param[in] syscfg_flag: specify the flag in SYSCFG_STAT to check + only one parameter can be selected which is shown as below: + \arg SYSCFG_FLAG_SRAMECCMERR: SRAM multi-bits non-correction ECC error flag + \arg SYSCFG_FLAG_SRAMECCSERR: SRAM single bit correction ECC error flag + \arg SYSCFG_FLAG_FLASHECCERR: FLASH ECC NMI error flag + \arg SYSCFG_FLAG_CKMNMIERR: HXTAL clock monitor NMI error flag + \arg SYSCFG_FLAG_NMIPINERR: NMI pin error flag + \param[out] none + \retval the syscfg_flag state returned (SET or RESET) + */ +FlagStatus syscfg_flag_get(uint32_t syscfg_flag) +{ + if(SYSCFG_STAT & syscfg_flag) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear SYSCFG flags + \param[in] syscfg_flag: specify the flag in SYSCFG_STAT to check + only one parameter can be selected which is shown as below: + \arg SYSCFG_FLAG_SRAMECCMERR: SRAM multi-bits non-correction ECC error flag + \arg SYSCFG_FLAG_SRAMECCSERR: SRAM single bit correction ECC error flag + \arg SYSCFG_FLAG_FLASHECCERR: FLASH ECC NMI error flag + \arg SYSCFG_FLAG_CKMNMIERR: HXTAL clock monitor NMI error flag + \param[out] none + \retval none +*/ +void syscfg_flag_clear(uint32_t syscfg_flag) +{ + SYSCFG_STAT |= (uint32_t) syscfg_flag; +} + +/*! + \brief enable SYSCFG interrupts + \param[in] interrupt: specify the interrupt in SYSCFG_CFG3 + only one parameter can be selected which is shown as below: + \arg SYSCFG_INT_SRAMECCME: SRAM multi-bits non-correction ECC error interrupt + \arg SYSCFG_INT_SRAMECCSE: SRAM single bit correction ECC error interrupt + \arg SYSCFG_INT_FLASHECCE: FLASH ECC NMI error interrupt + \arg SYSCFG_INT_CKMNMI: HXTAL clock monitor NMI error interrupt + \arg SYSCFG_INT_NMIPIN: NMI pin error interrupt + \param[out] none + \retval none +*/ +void syscfg_interrupt_enable(uint32_t interrupt) +{ + SYSCFG_CFG3 |= (uint32_t)interrupt; +} + +/*! + \brief disable SYSCFG interrupts + \param[in] interrupt: specify the interrupt in SYSCFG_CFG3 + only one parameter can be selected which is shown as below: + \arg SYSCFG_INT_SRAMECCME: SRAM multi-bits non-correction ECC error interrupt + \arg SYSCFG_INT_SRAMECCSE: SRAM single bit correction ECC error interrupt + \arg SYSCFG_INT_FLASHECCE: FLASH ECC NMI error interrupt + \arg SYSCFG_INT_CKMNMI: HXTAL clock monitor NMI error interrupt + \arg SYSCFG_INT_NMIPIN: NMI pin error interrupt + \param[out] none + \retval none +*/ +void syscfg_interrupt_disable(uint32_t interrupt) +{ + SYSCFG_CFG3 &= (uint32_t)(~interrupt); +} + +/*! + \brief get SYSCFG interrupt flag status + \param[in] interrupt: specify the interrupt flag status + only one parameter can be selected which is shown as below: + \arg SYSCFG_INT_FLAG_SRAMECCMERR: SRAM multi-bits non-correction ECC error interrupt flag + \arg SYSCFG_INT_FLAG_SRAMECCSERR: SRAM single bit correction ECC error interrupt flag + \arg SYSCFG_INT_FLAG_FLASHECCERR: FLASH ECC NMI error interrupt flag + \arg SYSCFG_INT_FLAG_CKMNMIERR: HXTAL clock monitor NMI error interrupt flag + \arg SYSCFG_INT_FLAG_NMIPINERR: NMI pin error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus syscfg_interrupt_flag_get(uint32_t interrupt) +{ + uint32_t reg1 = SYSCFG_STAT; + uint32_t reg2 = SYSCFG_CFG3; + + switch(interrupt) { + /* SRAM multi-bits non-correction ECC error interrupt */ + case SYSCFG_INT_FLAG_SRAMECCMERR: + reg1 = reg1 & SYSCFG_STAT_SRAMECCMEIF; + reg2 = reg2 & SYSCFG_CFG3_SRAMECCMEIE; + break; + /* SRAM single bit correction ECC error interrupt */ + case SYSCFG_INT_FLAG_SRAMECCSERR: + reg1 = reg1 & SYSCFG_STAT_SRAMECCSEIF; + reg2 = reg2 & SYSCFG_CFG3_SRAMECCSEIE; + break; + /* FLASH ECC NMI error interrupt */ + case SYSCFG_INT_FLAG_FLASHECCERR: + reg1 = reg1 & SYSCFG_STAT_FLASHECCIF; + reg2 = reg2 & SYSCFG_CFG3_FLASHECCIE; + break; + /* HXTAL clock monitor NMI error interrupt */ + case SYSCFG_INT_FLAG_CKMNMIERR: + reg1 = reg1 & SYSCFG_STAT_CKMNMIIF; + reg2 = reg2 & SYSCFG_CFG3_CKMNMIIE; + break; + /* NMI pin error interrupt */ + case SYSCFG_INT_FLAG_NMIPINERR: + reg1 = reg1 & SYSCFG_STAT_NMIPINIF; + reg2 = reg2 & SYSCFG_CFG3_NMIPINIE; + break; + default : + break; + } + /*get SYSCFG interrupt flag status */ + if(reg1 && reg2) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get the current boot mode + \param[in] none + \param[out] none + \retval the boot mode + \arg SYSCFG_BOOTMODE_FLASH: boot from the main flash + \arg SYSCFG_BOOTMODE_SYSTEM: boot from the system flash memory + \arg SYSCFG_BOOTMODE_SRAM: boot from the embedded SRAM +*/ +uint8_t syscfg_bootmode_get(void) +{ + return (uint8_t)(SYSCFG_CFG0 & SYSCFG_CFG0_BOOTMODE_MASK); +} + +/*! + \brief get the address where SRAM ECC error occur on + \param[in] none + \param[out] none + \retval uint16_t: the address where SRAM ECC error occur on +*/ +uint16_t syscfg_sram_ecc_address_get(void) +{ + return (uint16_t)(SYSCFG_CFG3 >> SYSCFG_CFG3_SRAMECCEADDR_OFFSET); +} + +/*! + \brief get the bit which has SRAM ECC signle error + \param[in] none + \param[out] none + \retval uint8_t: which bit has SRAM ECC signle error +*/ +uint8_t syscfg_sram_ecc_bit_get(void) +{ + return (uint8_t)((SYSCFG_CFG3 & SYSCFG_CFG3_SRAMECCSERRBITS) >> SYSCFG_CFG3_SRAMECCSERRBIT_OFFSET); +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_timer.c b/gd32a50x/standard_peripheral/source/gd32a50x_timer.c new file mode 100644 index 0000000..22fe6f5 --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_timer.c @@ -0,0 +1,3035 @@ +/*! + \file gd32a50x_timer.c + \brief TIMER driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_timer.h" + +/* TIMER init parameter mask */ +#define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */ +#define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */ +#define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */ + +/*! + \brief deinit a TIMER + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[out] none + \retval none +*/ +void timer_deinit(uint32_t timer_periph) +{ + switch(timer_periph) { + case TIMER0: + /* reset TIMER0 */ + rcu_periph_reset_enable(RCU_TIMER0RST); + rcu_periph_reset_disable(RCU_TIMER0RST); + break; + case TIMER1: + /* reset TIMER1 */ + rcu_periph_reset_enable(RCU_TIMER1RST); + rcu_periph_reset_disable(RCU_TIMER1RST); + break; + case TIMER5: + /* reset TIMER5 */ + rcu_periph_reset_enable(RCU_TIMER5RST); + rcu_periph_reset_disable(RCU_TIMER5RST); + break; + case TIMER6: + /* reset TIMER6 */ + rcu_periph_reset_enable(RCU_TIMER6RST); + rcu_periph_reset_disable(RCU_TIMER6RST); + break; + case TIMER7: + /* reset TIMER7 */ + rcu_periph_reset_enable(RCU_TIMER7RST); + rcu_periph_reset_disable(RCU_TIMER7RST); + break; + case TIMER19: + /* reset TIMER19 */ + rcu_periph_reset_enable(RCU_TIMER19RST); + rcu_periph_reset_disable(RCU_TIMER19RST); + break; + case TIMER20: + /* reset TIMER20 */ + rcu_periph_reset_enable(RCU_TIMER20RST); + rcu_periph_reset_disable(RCU_TIMER20RST); + break; + default: + break; + } +} + +/*! + \brief initialize TIMER init parameter struct with a default value + \param[in] initpara: init parameter struct + \param[out] none + \retval none +*/ +void timer_struct_para_init(timer_parameter_struct *initpara) +{ + /* initialize the init parameter struct member with the default value */ + initpara->prescaler = 0U; + initpara->alignedmode = TIMER_COUNTER_EDGE; + initpara->counterdirection = TIMER_COUNTER_UP; + initpara->period = 65535U; + initpara->clockdivision = TIMER_CKDIV_DIV1; + initpara->repetitioncounter = 0U; +} + +/*! + \brief initialize TIMER counter + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[in] initpara: init parameter struct + prescaler: prescaler value of the counter clock, 0~65535 + alignedmode: TIMER_COUNTER_EDGE, TIMER_COUNTER_CENTER_DOWN, TIMER_COUNTER_CENTER_UP, TIMER_COUNTER_CENTER_BOTH + counterdirection: TIMER_COUNTER_UP, TIMER_COUNTER_DOWN + period: counter auto reload value, 0~65535 + clockdivision: TIMER_CKDIV_DIV1, TIMER_CKDIV_DIV2, TIMER_CKDIV_DIV4 + repetitioncounter: counter repetition value, 0~255 + \param[out] none + \retval none +*/ +void gd32_timer_init(uint32_t timer_periph, timer_parameter_struct *initpara) +{ + /* configure the counter prescaler value */ + TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; + + /* configure the counter direction and aligned mode */ + if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER7 == timer_periph) + || (TIMER19 == timer_periph) || (TIMER20 == timer_periph)) { + TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM)); + TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK); + TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK); + } + + /* configure the autoreload value */ + TIMER_CAR(timer_periph) = (uint32_t)initpara->period; + + /* configure the clock division value */ + if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)) { + /* reset the CKDIV bit */ + TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV); + TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK); + } + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph) || + (TIMER19 == timer_periph) || (TIMER20 == timer_periph)) { + /* configure the repetition counter value */ + TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; + } + + /* generate an update event */ + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; +} + +/*! + \brief enable a TIMER + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[out] none + \retval none +*/ +void timer_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief disable a TIMER + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[out] none + \retval none +*/ +void timer_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief enable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief disable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief enable the update event + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[out] none + \retval none +*/ +void timer_update_event_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; +} + +/*! + \brief disable the update event + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[out] none + \retval none +*/ +void timer_update_event_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; +} + +/*! + \brief set TIMER counter alignment mode + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] aligned: aligned mode + only one parameter can be selected which is shown as below: + \arg TIMER_COUNTER_EDGE: edge-aligned mode + \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode + \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode + \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode + \param[out] none + \retval none +*/ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) +{ + TIMER_CTL0(timer_periph) &= (uint32_t)(~TIMER_CTL0_CAM); + TIMER_CTL0(timer_periph) |= (uint32_t)aligned; +} + +/*! + \brief set TIMER counter up direction + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[out] none + \retval none +*/ +void timer_counter_up_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief set TIMER counter down direction + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[out] none + \retval none +*/ +void timer_counter_down_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief configure TIMER prescaler + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[in] prescaler: prescaler value, 0~65535 + \param[in] pscreload: prescaler reload mode + only one parameter can be selected which is shown as below: + \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now + \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event + \param[out] none + \retval none +*/ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload) +{ + TIMER_PSC(timer_periph) = (uint32_t)prescaler; + + if(TIMER_PSC_RELOAD_NOW == pscreload) { + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; + } +} + +/*! + \brief configure TIMER repetition register value + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] repetition: the counter repetition value, 0~255 + \param[out] none + \retval none +*/ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) +{ + TIMER_CREP(timer_periph) = (uint32_t)repetition; +} + +/*! + \brief configure TIMER autoreload register value + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[in] autoreload: the counter auto-reload value, 0~65535 + \param[out] none + \retval none +*/ +void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload) +{ + TIMER_CAR(timer_periph) = (uint32_t)autoreload; +} + +/*! + \brief configure TIMER counter register value + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[in] counter: the counter value, 0~65535 + \param[out] none + \retval none +*/ +void timer_counter_value_config(uint32_t timer_periph, uint16_t counter) +{ + TIMER_CNT(timer_periph) = (uint32_t)counter; +} + +/*! + \brief read TIMER counter value + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[out] none + \retval counter value, 0~65535 +*/ +uint32_t timer_counter_read(uint32_t timer_periph) +{ + uint32_t count_value = 0U; + count_value = TIMER_CNT(timer_periph); + return (count_value); +} + +/*! + \brief read TIMER prescaler value + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[out] none + \retval prescaler register value, 0~65535 +*/ +uint16_t timer_prescaler_read(uint32_t timer_periph) +{ + uint16_t prescaler_value = 0U; + prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); + return (prescaler_value); +} + +/*! + \brief configure TIMER single pulse mode + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[in] spmode: single pulse mode + only one parameter can be selected which is shown as below: + \arg TIMER_SP_MODE_SINGLE: single pulse mode + \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode + \param[out] none + \retval none +*/ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) +{ + if(TIMER_SP_MODE_SINGLE == spmode) { + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; + } else if(TIMER_SP_MODE_REPETITIVE == spmode) { + TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER update source + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[in] update: update source + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow, + or the slave mode controller trigger + \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow + \param[out] none + \retval none +*/ +void timer_update_source_config(uint32_t timer_periph, uint32_t update) +{ + if(TIMER_UPDATE_SRC_REGULAR == update) { + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; + } else if(TIMER_UPDATE_SRC_GLOBAL == update) { + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure channel commutation control shadow register + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; + } else { + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); + } +} + +/*! + \brief configure TIMER channel control shadow register update control + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] ccuctl: channel control shadow register update control + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set + \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl) +{ + if(TIMER_UPDATECTL_CCU == ccuctl) { + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); + } else if(TIMER_UPDATECTL_CCUTRI == ccuctl) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; + } else { + /* illegal parameters */ + } +} + +/*! + \brief enable the TIMER DMA + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[in] dma: specify which DMA to enable + one or more parameters can be selected which are shown as below: + \arg TIMER_DMA_UPD: update DMA request, TIMERx(x=0,1,5,6,7,19,20) + \arg TIMER_DMA_CH0D: channel 0 DMA request , TIMERx(x=0,1,7,19,20) + \arg TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMA_CMTD: channel commutation DMA request, TIMERx(x=0,7,19,20) + \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0,1,7,19,20) + \arg TIMER_DMA_MCH0D: multi mode channel 0 DMA request, TIMERx(x=0,7,19,20) + \arg TIMER_DMA_MCH1D: multi mode channel 1 DMA request, TIMERx(x=0,7,19,20) + \arg TIMER_DMA_MCH2D: multi mode channel 2 DMA request, TIMERx(x=0,7,19,20) + \arg TIMER_DMA_MCH3D: multi mode channel 3 DMA request, TIMERx(x=0,7,19,20) + \param[out] none + \retval none +*/ +void timer_dma_enable(uint32_t timer_periph, uint32_t dma) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; +} + +/*! + \brief disable the TIMER DMA + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[in] dma: specify which DMA to disbale + one or more parameters can be selected which are shown as below: + \arg TIMER_DMA_UPD: update DMA request, TIMERx(x=0,1,5,6,7,19,20) + \arg TIMER_DMA_CH0D: channel 0 DMA request , TIMERx(x=0,1,7,19,20) + \arg TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMA_CMTD: channel commutation DMA request, TIMERx(x=0,7,19,20) + \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0,1,7,19,20) + \arg TIMER_DMA_MCH0D: multi mode channel 0 DMA request, TIMERx(x=0,7,19,20) + \arg TIMER_DMA_MCH1D: multi mode channel 1 DMA request, TIMERx(x=0,7,19,20) + \arg TIMER_DMA_MCH2D: multi mode channel 2 DMA request, TIMERx(x=0,7,19,20) + \arg TIMER_DMA_MCH3D: multi mode channel 3 DMA request, TIMERx(x=0,7,19,20) + \param[out] none + \retval none +*/ +void timer_dma_disable(uint32_t timer_periph, uint32_t dma) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); +} + +/*! + \brief channel DMA request source selection + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[in] dma_request: channel DMA request source selection + only one parameter can be selected which is shown as below: + \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel n is sent when channel n event occurs + \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel n is sent when update event occurs + \param[out] none + \retval none +*/ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request) +{ + if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; + } else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request) { + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure the TIMER DMA transfer + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] dma_baseaddr: DMA access base address + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0,1,7,19,20) + \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_MCHCTL0: DMA transfer address is TIMER_MCHCTL0, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_MCHCTL1: DMA transfer address is TIMER_MCHCTL1, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_MCHCTL2: DMA transfer address is TIMER_MCHCTL2, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_MCH0CV: DMA transfer address is TIMER_MCH0CV, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_MCH1CV: DMA transfer address is TIMER_MCH1CV, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_MCH2CV: DMA transfer address is TIMER_MCH2CV, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_MCH3CV: DMA transfer address is TIMER_MCH3CV, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_CH0COMV_ADD: DMA transfer address is TIMER_CH0COMV_ADD, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_CH1COMV_ADD: DMA transfer address is TIMER_CH1COMV_ADD, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_CH2COMV_ADD: DMA transfer address is TIMER_CH2COMV_ADD, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_CH3COMV_ADD: DMA transfer address is TIMER_CH3COMV_ADD, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_CTL2: DMA transfer address is TIMER_CTL2, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_BRKCFG: DMA transfer address is TIMER_BRKCFG, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_FCCHP0: DMA transfer address is TIMER_FCCHP0, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_FCCHP1: DMA transfer address is TIMER_FCCHP1, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_FCCHP2: DMA transfer address is TIMER_FCCHP2, TIMERx(x=0,7,19,20) + \arg TIMER_DMACFG_DMATA_FCCHP3: DMA transfer address is TIMER_FCCHP3, TIMERx(x=0,7,19,20) + \param[in] dma_lenth: access burst length + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1~35): DMA transfer x time + \param[out] none + \retval none +*/ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) +{ + TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); + TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); +} + +/*! + \brief software generate events + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] event: the timer software event generation sources + one or more parameters can be selected which are shown as below: + \arg TIMER_EVENT_SRC_UPG: update event generation, TIMERx(x=0,1,5,6,7,19,20) + \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0,1,7,19,20) + \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0,1,7,19,20) + \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0,1,7,19,20) + \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0,1,7,19,20) + \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,7,19,20) + \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0,1,7,19,20) + \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,7,19,20) + \arg TIMER_EVENT_SRC_MCH0G: multi mode channel 0 capture or compare event generation, TIMERx(x=0,7,19,20) + \arg TIMER_EVENT_SRC_MCH1G: multi mode channel 1 capture or compare event generation, TIMERx(x=0,7,19,20) + \arg TIMER_EVENT_SRC_MCH2G: multi mode channel 2 capture or compare event generation, TIMERx(x=0,7,19,20) + \arg TIMER_EVENT_SRC_MCH3G: multi mode channel 3 capture or compare event generation, TIMERx(x=0,7,19,20) + \arg TIMER_EVENT_SRC_CH0COMADDG: channel 0 additional compare event generation, TIMERx(x=0,7,19,20) + \arg TIMER_EVENT_SRC_CH1COMADDG: channel 1 additional compare event generation, TIMERx(x=0,7,19,20) + \arg TIMER_EVENT_SRC_CH2COMADDG: channel 2 additional compare event generation, TIMERx(x=0,7,19,20) + \arg TIMER_EVENT_SRC_CH3COMADDG: channel 3 additional compare event generation, TIMERx(x=0,7,19,20) + \param[out] none + \retval none +*/ +void timer_event_software_generate(uint32_t timer_periph, uint32_t event) +{ + TIMER_SWEVG(timer_periph) |= (uint32_t)event; +} + +/*! + \brief initialize TIMER break parameter struct with a default value + \param[in] breakpara: TIMER break parameter struct + \param[out] none + \retval none +*/ +void timer_break_struct_para_init(timer_break_parameter_struct *breakpara) +{ + /* initialize the break parameter struct member with the default value */ + breakpara->runoffstate = (uint16_t)TIMER_ROS_STATE_DISABLE; + breakpara->ideloffstate = (uint16_t)TIMER_IOS_STATE_DISABLE; + breakpara->deadtime = 0U; + breakpara->breakpolarity = (uint16_t)TIMER_BREAK_POLARITY_LOW; + breakpara->outputautostate = (uint16_t)TIMER_OUTAUTO_DISABLE; + breakpara->protectmode = (uint16_t)TIMER_CCHP_PROT_OFF; + breakpara->breakstate = (uint16_t)TIMER_BREAK_DISABLE; +} + +/*! + \brief configure TIMER break function + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] breakpara: TIMER break parameter struct + runoffstate: TIMER_ROS_STATE_ENABLE, TIMER_ROS_STATE_DISABLE + ideloffstate: TIMER_IOS_STATE_ENABLE, TIMER_IOS_STATE_DISABLE + deadtime: 0~255 + breakpolarity: TIMER_BREAK_POLARITY_LOW, TIMER_BREAK_POLARITY_HIGH + outputautostate: TIMER_OUTAUTO_ENABLE, TIMER_OUTAUTO_DISABLE + protectmode: TIMER_CCHP_PROT_OFF, TIMER_CCHP_PROT_0, TIMER_CCHP_PROT_1, TIMER_CCHP_PROT_2 + breakstate: TIMER_BREAK_ENABLE, TIMER_BREAK_DISABLE + \param[out] none + \retval none +*/ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara) +{ + TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | + ((uint32_t)(breakpara->ideloffstate)) | + ((uint32_t)(breakpara->deadtime)) | + ((uint32_t)(breakpara->breakpolarity)) | + ((uint32_t)(breakpara->outputautostate)) | + ((uint32_t)(breakpara->protectmode)) | + ((uint32_t)(breakpara->breakstate))); +} + +/*! + \brief enable TIMER break function + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[out] none + \retval none +*/ +void timer_break_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief disable TIMER break function + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[out] none + \retval none +*/ +void timer_break_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief enable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[out] none + \retval none +*/ +void timer_automatic_output_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief disable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[out] none + \retval none +*/ +void timer_automatic_output_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief configure TIMER primary output function + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; + } else { + TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); + } +} + +/*! + \brief initialize TIMER channel output parameter struct with a default value + \param[in] ocpara: TIMER channel n output parameter struct + \param[out] none + \retval none +*/ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara) +{ + /* initialize the channel output parameter struct member with the default value */ + ocpara->outputstate = TIMER_CCX_DISABLE; + ocpara->outputnstate = TIMER_CCXN_DISABLE; + ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; + ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; + ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; + ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; +} + +/*! + \brief configure TIMER channel output function + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20)) + \param[in] ocpara: TIMER channel output parameter struct + outputstate: TIMER_CCX_ENABLE, TIMER_CCX_DISABLE + outputnstate: TIMER_CCXN_ENABLE, TIMER_CCXN_DISABLE + ocpolarity: TIMER_OC_POLARITY_HIGH, TIMER_OC_POLARITY_LOW + ocnpolarity: TIMER_OCN_POLARITY_HIGH, TIMER_OCN_POLARITY_LOW + ocidlestate: TIMER_OC_IDLE_STATE_LOW, TIMER_OC_IDLE_STATE_HIGH + ocnidlestate: TIMER_OCN_IDLE_STATE_LOW, TIMER_OCN_IDLE_STATE_HIGH + \param[out] none + \retval none +*/ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; + /* reset the CH0P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + /* set the CH0P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph) || + (TIMER19 == timer_periph) || (TIMER20 == timer_periph)) { + /* reset the MCH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH0EN); + /* set the MCH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; + + /* reset the MCH0P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH0P); + /* set the MCH0P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; + + /* reset the ISO0 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); + /* set the ISO0 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; + + /* reset the ISO0N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); + /* set the ISO0N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; + } + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 4U); + /* reset the CH1P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + /* set the CH1P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph) || + (TIMER19 == timer_periph) || (TIMER20 == timer_periph)) { + /* reset the MCH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH1EN); + /* set the MCH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); + /* reset the MCH1P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH1P); + /* set the MCH1P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); + /* reset the ISO1 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); + /* set the ISO1 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); + /* reset the ISO1N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); + /* set the ISO1N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); + } + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 8U); + /* reset the CH2P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + /* set the CH2P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph) || + (TIMER19 == timer_periph) || (TIMER20 == timer_periph)) { + /* reset the MCH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH2EN); + /* set the MCH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); + /* reset the MCH2P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH2P); + /* set the MCH2P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); + /* reset the ISO2 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); + /* set the ISO2 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); + /* reset the ISO2N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); + /* set the ISO2N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); + } + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U); + /* reset the CH3P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + /* set the CH3P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph) || + (TIMER19 == timer_periph) || (TIMER20 == timer_periph)) { + /* reset the MCH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH3EN); + /* set the MCH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 12U); + /* reset the MCH3P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH3P); + /* set the MCH3P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 12U); + /* reset the ISO3 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); + /* set the ISO3 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); + /* reset the ISO3N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3N); + /* set the ISO3N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 6U); + } + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output compare mode + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20)) + \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20)) + \param[in] ocmode: channel output compare mode + only one parameter can be selected which is shown as below: + \arg TIMER_OC_MODE_TIMING: timing mode + \arg TIMER_OC_MODE_ACTIVE: active mode + \arg TIMER_OC_MODE_INACTIVE: inactive mode + \arg TIMER_OC_MODE_TOGGLE: toggle mode + \arg TIMER_OC_MODE_LOW: force low mode + \arg TIMER_OC_MODE_HIGH: force high mode + \arg TIMER_OC_MODE_PWM0: PWM mode 0 + \arg TIMER_OC_MODE_PWM1: PWM mode 1 + \param[out] none + \retval none +*/ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + /* configure TIMER_MCH_0 */ + case TIMER_MCH_0: + TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH0COMCTL); + TIMER_MCHCTL0(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_MCH_1 */ + case TIMER_MCH_1: + TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH1COMCTL); + TIMER_MCHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + /* configure TIMER_MCH_2 */ + case TIMER_MCH_2: + TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH2COMCTL); + TIMER_MCHCTL1(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_MCH_3 */ + case TIMER_MCH_3: + TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH3COMCTL); + TIMER_MCHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output pulse value + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20)) + \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20)) + \param[in] pulse: channel output pulse value + \param[out] none + \retval none +*/ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CH0CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CH1CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CH2CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_MCH_0 */ + case TIMER_MCH_0: + TIMER_MCH0CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_MCH_1 */ + case TIMER_MCH_1: + TIMER_MCH1CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_MCH_2 */ + case TIMER_MCH_2: + TIMER_MCH2CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_MCH_3 */ + case TIMER_MCH_3: + TIMER_MCH3CV(timer_periph) = (uint32_t)pulse; + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output shadow function + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20)) + \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20)) + \param[in] ocshadow: channel output compare shadow + only one parameter can be selected which is shown as below: + \arg TIMER_OC_SHADOW_ENABLE: channel output compare shadow enable + \arg TIMER_OC_SHADOW_DISABLE: channel output compare shadow disable + \arg TIMER_OMC_SHADOW_ENABLE: multi mode channel output compare shadow enable + \arg TIMER_OMC_SHADOW_DISABLE: multi mode channel output compare shadow disable + \param[out] none + \retval none +*/ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + /* configure TIMER_MCH_0 */ + case TIMER_MCH_0: + TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH0COMSEN); + TIMER_MCHCTL0(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_MCH_1 */ + case TIMER_MCH_1: + TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH1COMSEN); + TIMER_MCHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + /* configure TIMER_MCH_2 */ + case TIMER_MCH_2: + TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH2COMSEN); + TIMER_MCHCTL1(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_MCH_3 */ + case TIMER_MCH_3: + TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH3COMSEN); + TIMER_MCHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output clear function + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20)) + \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20)) + \param[in] occlear: channel output clear function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable + \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable + \arg TIMER_OMC_CLEAR_ENABLE: multi mode channel output clear function enable + \arg TIMER_OMC_CLEAR_DISABLE: multi mode channel output clear function disable + \param[out] none + \retval none +*/ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + /* configure TIMER_MCH_0 */ + case TIMER_MCH_0: + TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH0COMCEN); + TIMER_MCHCTL0(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_MCH_1 */ + case TIMER_MCH_1: + TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH1COMCEN); + TIMER_MCHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + /* configure TIMER_MCH_2 */ + case TIMER_MCH_2: + TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH2COMCEN); + TIMER_MCHCTL1(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_MCH_3 */ + case TIMER_MCH_3: + TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH3COMCEN); + TIMER_MCHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output polarity + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20)) + \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20)) + \param[in] ocpolarity: channel output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high + \arg TIMER_OC_POLARITY_LOW: channel output polarity is low + \arg TIMER_OMC_POLARITY_HIGH: multi mode channel output polarity is high + \arg TIMER_OMC_POLARITY_LOW: multi mode channel output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); + break; + /* configure TIMER_MCH_0 */ + case TIMER_MCH_0: + TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)TIMER_MCHCTL2_MCH0FP); + TIMER_MCHCTL2(timer_periph) |= (uint32_t)ocpolarity; + break; + /* configure TIMER_MCH_1 */ + case TIMER_MCH_1: + TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)TIMER_MCHCTL2_MCH1FP); + TIMER_MCHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 2U); + break; + /* configure TIMER_MCH_2 */ + case TIMER_MCH_2: + TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)TIMER_MCHCTL2_MCH2FP); + TIMER_MCHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); + break; + /* configure TIMER_MCH_3 */ + case TIMER_MCH_3: + TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)TIMER_MCHCTL2_MCH3FP); + TIMER_MCHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 6U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output polarity + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,7,19,20)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,7,19,20)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,7,19,20)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,7,19,20)) + \param[in] ocnpolarity: channel complementary output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high + \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH0P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH1P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH2P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH3P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel enable state + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20)) + \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20)) + \param[in] state: TIMER channel enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCX_ENABLE: channel enable + \arg TIMER_CCX_DISABLE: channel disable + \arg TIMER_MCCX_ENABLE: multi mode channel enable + \arg TIMER_MCCX_DISABLE: multi mode channel disable + \param[out] none + \retval none +*/ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)state; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); + break; + /* configure TIMER_MCH_0 */ + case TIMER_MCH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH0EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state); + break; + /* configure TIMER_MCH_1 */ + case TIMER_MCH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH1EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(state << 4U)); + break; + /* configure TIMER_MCH_2 */ + case TIMER_MCH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH2EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(state << 8U)); + break; + /* configure TIMER_MCH_3 */ + case TIMER_MCH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH3EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(state << 12U)); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output enable state + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,7,19,20)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,7,19,20)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,7,19,20)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,7,19,20)) + \param[in] ocnstate: TIMER channel complementary output enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCXN_ENABLE: channel complementary enable + \arg TIMER_CCXN_DISABLE: channel complementary disable + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH0EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH1EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH2EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH3EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 12U); + break; + default: + break; + } +} + +/*! + \brief initialize TIMER channel input parameter struct with a default value + \param[in] icpara: TIMER channel input parameter struct + \param[out] none + \retval none +*/ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara) +{ + /* initialize the channel input parameter struct member with the default value */ + icpara->icpolarity = TIMER_IC_POLARITY_RISING; + icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; + icpara->icprescaler = TIMER_IC_PSC_DIV1; + icpara->icfilter = 0U; +} + +/*! + \brief configure TIMER input capture parameter + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20)) + \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20)) + \param[in] icpara: TIMER channel input parameter struct + icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING, TIMER_IC_POLARITY_BOTH_EDGE + icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI, TIMER_IC_SELECTION_ITS, TIMER_IC_SELECTION_PAIR + icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + + /* reset the CH0P and MCH0P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_MCH0P)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); + + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + if(TIMER_IC_SELECTION_PAIR == icpara->icselection) { + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 28U); + } else { + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); + } + + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + break; + + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + + /* reset the CH1P and MCH1P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_MCH1P)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); + + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + if(TIMER_IC_SELECTION_PAIR == icpara->icselection) { + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 29U); + } else { + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + } + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + + /* reset the CH2P and MCH2P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_MCH2P)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); + + /* reset the CH2MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); + if(TIMER_IC_SELECTION_PAIR == icpara->icselection) { + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 28U); + } else { + TIMER_CHCTL1(timer_periph) |= (uint32_t)(icpara->icselection); + } + + /* reset the CH2CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + + /* reset the CH3P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P | TIMER_CHCTL2_MCH3P)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); + + /* reset the CH3MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); + if(TIMER_IC_SELECTION_PAIR == icpara->icselection) { + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 29U); + } else { + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + } + + /* reset the CH3CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; + break; + + /* configure TIMER_MCH_0 */ + case TIMER_MCH_0: + /* reset the MCH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH0EN); + + /* reset the MCH0FP bits */ + TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)(TIMER_MCHCTL2_MCH0FP)); + switch(icpara->icpolarity) { + case TIMER_IC_POLARITY_RISING: + TIMER_MCHCTL2(timer_periph) |= TIMER_IMC_POLARITY_RISING; + break; + case TIMER_IC_POLARITY_FALLING: + TIMER_MCHCTL2(timer_periph) |= TIMER_IMC_POLARITY_FALLING; + break; + case TIMER_IC_POLARITY_BOTH_EDGE: + TIMER_MCHCTL2(timer_periph) |= TIMER_IMC_POLARITY_BOTH_EDGE; + break; + default: + break; + } + + /* reset the MCH0MS bit */ + TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH0MS); + if(TIMER_IC_SELECTION_PAIR == icpara->icselection) { + TIMER_MCHCTL0(timer_periph) |= ((uint32_t)icpara->icselection << 28U); + } else { + TIMER_MCHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); + } + + /* reset the MCH0CAPFLT bit */ + TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH0CAPFLT); + TIMER_MCHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the MCH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_MCH0EN; + break; + + /* configure TIMER_MCH_1 */ + case TIMER_MCH_1: + /* reset the MCH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH1EN); + + /* reset the MCH1FP bits */ + TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)(TIMER_MCHCTL2_MCH1FP)); + switch(icpara->icpolarity) { + case TIMER_IC_POLARITY_RISING: + TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_RISING << 2U); + break; + case TIMER_IC_POLARITY_FALLING: + TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_FALLING << 2U); + break; + case TIMER_IC_POLARITY_BOTH_EDGE: + TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_BOTH_EDGE << 2U); + break; + default: + break; + } + /* reset the MCH1MS bit */ + TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH1MS); + if(TIMER_IC_SELECTION_PAIR == icpara->icselection) { + TIMER_MCHCTL0(timer_periph) |= ((uint32_t)icpara->icselection << 29U); + } else { + TIMER_MCHCTL0(timer_periph) |= ((uint32_t)(icpara->icselection) << 8U); + } + + /* reset the MCH1CAPFLT bit */ + TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH1CAPFLT); + TIMER_MCHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the MCH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_MCH1EN; + break; + /* configure TIMER_MCH_2 */ + case TIMER_MCH_2: + /* reset the MCH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH2EN); + + /* reset the MCH2FP bits */ + TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)(TIMER_MCHCTL2_MCH2FP)); + switch(icpara->icpolarity) { + case TIMER_IC_POLARITY_RISING: + TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_RISING << 4U); + break; + case TIMER_IC_POLARITY_FALLING: + TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_FALLING << 4U); + break; + case TIMER_IC_POLARITY_BOTH_EDGE: + TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_BOTH_EDGE << 4U); + break; + default: + break; + } + /* reset the MCH2MS bit */ + TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH2MS); + if(TIMER_IC_SELECTION_PAIR == icpara->icselection) { + TIMER_MCHCTL1(timer_periph) |= ((uint32_t)icpara->icselection << 28U); + } else { + TIMER_MCHCTL1(timer_periph) |= ((uint32_t)(icpara->icselection)); + } + + /* reset the MCH2CAPFLT bit */ + TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH2CAPFLT); + TIMER_MCHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the MCH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_MCH2EN; + break; + /* configure TIMER_MCH_3 */ + case TIMER_MCH_3: + /* reset the MCH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH3EN); + + /* reset the MCH3FP bits */ + TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)(TIMER_MCHCTL2_MCH3FP)); + switch(icpara->icpolarity) { + case TIMER_IC_POLARITY_RISING: + TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_RISING << 6U); + break; + case TIMER_IC_POLARITY_FALLING: + TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_FALLING << 6U); + break; + case TIMER_IC_POLARITY_BOTH_EDGE: + TIMER_MCHCTL2(timer_periph) |= ((uint32_t)TIMER_IMC_POLARITY_BOTH_EDGE << 6U); + break; + default: + break; + } + /* reset the MCH3MS bit */ + TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH3MS); + if(TIMER_IC_SELECTION_PAIR == icpara->icselection) { + TIMER_MCHCTL1(timer_periph) |= ((uint32_t)icpara->icselection << 29U); + } else { + TIMER_MCHCTL1(timer_periph) |= ((uint32_t)(icpara->icselection) << 8U); + } + + /* reset the MCH3CAPFLT bit */ + TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH3CAPFLT); + TIMER_MCHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the MCH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_MCH3EN; + break; + default: + break; + } + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); +} + +/*! + \brief configure TIMER channel input capture prescaler value + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20)) + \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20)) + \param[in] prescaler: channel input capture prescaler value + only one parameter can be selected which is shown as below: + \arg TIMER_IC_PSC_DIV1: no prescaler + \arg TIMER_IC_PSC_DIV2: divided by 2 + \arg TIMER_IC_PSC_DIV4: divided by 4 + \arg TIMER_IC_PSC_DIV8: divided by 8 + \param[out] none + \retval none +*/ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); + TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); + TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); + TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + /* configure TIMER_MCH_0 */ + case TIMER_MCH_0: + TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH0CAPPSC); + TIMER_MCHCTL0(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_MCH_1 */ + case TIMER_MCH_1: + TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH1CAPPSC); + TIMER_MCHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + /* configure TIMER_MCH_2 */ + case TIMER_MCH_2: + TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH2CAPPSC); + TIMER_MCHCTL1(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_MCH_3 */ + case TIMER_MCH_3: + TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH3CAPPSC); + TIMER_MCHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + default: + break; + } +} + +/*! + \brief read TIMER channel capture compare register value + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20)) + \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20)) + \param[out] none + \retval channel capture compare register value(0~65535) +*/ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) +{ + uint32_t count_value = 0U; + + switch(channel) { + case TIMER_CH_0: + /* read TIMER_CH_0 capture compare register value */ + count_value = TIMER_CH0CV(timer_periph); + break; + case TIMER_CH_1: + /* read TIMER_CH_1 capture compare register value */ + count_value = TIMER_CH1CV(timer_periph); + break; + case TIMER_CH_2: + /* read TIMER_CH_2 capture compare register value */ + count_value = TIMER_CH2CV(timer_periph); + break; + case TIMER_CH_3: + /* read TIMER_CH_3 capture compare register value */ + count_value = TIMER_CH3CV(timer_periph); + break; + case TIMER_MCH_0: + /* read TIMER_MCH_0 capture compare register value */ + count_value = TIMER_MCH0CV(timer_periph); + break; + case TIMER_MCH_1: + /* read TIMER_MCH_1 capture compare register value */ + count_value = TIMER_MCH1CV(timer_periph); + break; + case TIMER_MCH_2: + /* read TIMER_MCH_2 capture compare register value */ + count_value = TIMER_MCH2CV(timer_periph); + break; + case TIMER_MCH_3: + /* read TIMER_MCH_3 capture compare register value */ + count_value = TIMER_MCH3CV(timer_periph); + break; + default: + break; + } + return (count_value); +} + +/*! + \brief configure TIMER input pwm capture function + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0 + \arg TIMER_CH_1: TIMER channel 1 + \param[in] icpwm: TIMER channel input pwm parameter struct + icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING + icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI + icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm) +{ + uint16_t icpolarity = 0U; + uint16_t icselection = 0U; + + /* set channel input polarity */ + if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity) { + icpolarity = TIMER_IC_POLARITY_FALLING; + } else { + icpolarity = TIMER_IC_POLARITY_RISING; + } + /* set channel input mode selection */ + if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection) { + icselection = TIMER_IC_SELECTION_INDIRECTTI; + } else { + icselection = TIMER_IC_SELECTION_DIRECTTI; + } + + if(TIMER_CH_0 == channel) { + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and MCH0P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_MCH0P)); + /* set the CH0P and MCH0P bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); + + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and MCH1P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_MCH1P)); + /* set the CH1P and MCH1P bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + } else { + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and MCH1P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_MCH1P)); + /* set the CH1P and MCH1P bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and MCH0P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_MCH0P)); + /* set the CH0P and MCH0P bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); + } +} + +/*! + \brief configure TIMER hall sensor mode + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] hallmode: + only one parameter can be selected which is shown as below: + \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable + \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable + \param[out] none + \retval none +*/ +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) +{ + if(TIMER_HALLINTERFACE_ENABLE == hallmode) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; + } else if(TIMER_HALLINTERFACE_DISABLE == hallmode) { + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; + } else { + /* illegal parameters */ + } +} + +/*! + \brief initialize TIMER multi mode channel output parameter struct + \param[in] omcpara: TIMER multi mode channel output parameter struct + \param[out] none + \retval none +*/ +void timer_multi_mode_channel_output_parameter_struct_init(timer_omc_parameter_struct *omcpara) +{ + /* initialize the multi mode channel output parameter struct with the default value */ + omcpara->outputmode = TIMER_MCH_MODE_COMPLEMENTARY; + omcpara->outputstate = TIMER_MCCX_DISABLE; + omcpara->ocpolarity = TIMER_OMC_POLARITY_LOW; +} + +/*! + \brief configure TIMER multi mode channel output function + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20)) + \param[in] omcpara: TIMER multi mode channel output parameter struct + outputmode: TIMER_MCH_MODE_INDEPENDENTLY, TIMER_MCH_MODE_MIRRORED, TIMER_MCH_MODE_COMPLEMENTARY + outputstate: TIMER_MCCX_ENABLE, TIMER_MCCX_DISABLE + ocpolarity: TIMER_OMC_POLARITY_HIGH, TIMER_OMC_POLARITY_LOW + \param[out] none + \retval none +*/ +void timer_multi_mode_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_omc_parameter_struct *omcpara) +{ + switch(channel) { + /* configure TIMER_MCH_0 */ + case TIMER_MCH_0: + TIMER_CTL2(timer_periph) &= (~(uint32_t)((uint32_t)TIMER_MCH_MODE_MASK << 20U)); + TIMER_CTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->outputmode) << 20U); + /* reset the MCH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH0EN); + /* set the MCH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->outputstate)); + + /* reset the MCH0FP bit */ + TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)TIMER_MCHCTL2_MCH0FP); + /* set the MCH0FP bit */ + TIMER_MCHCTL2(timer_periph) |= (uint32_t)omcpara->ocpolarity; + + TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH0MS); + break; + /* configure TIMER_MCH_1 */ + case TIMER_MCH_1: + TIMER_CTL2(timer_periph) &= (~(uint32_t)((uint32_t)TIMER_MCH_MODE_MASK << 22U)); + TIMER_CTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->outputmode) << 22U); + /* reset the MCH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH1EN); + /* set the MCH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->outputstate) << 4U); + + /* reset the MCH1FP bit */ + TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)TIMER_MCHCTL2_MCH1FP); + /* set the MCH1FP bit */ + TIMER_MCHCTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->ocpolarity) << 2U); + + TIMER_MCHCTL0(timer_periph) &= (~(uint32_t)TIMER_MCHCTL0_MCH1MS); + break; + + /* configure TIMER_MCH_2 */ + case TIMER_MCH_2: + TIMER_CTL2(timer_periph) &= (~(uint32_t)((uint32_t)TIMER_MCH_MODE_MASK << 24U)); + TIMER_CTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->outputmode) << 24U); + /* reset the MCH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH2EN); + /* set the MCH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->outputstate) << 8U); + + /* reset the MCH2FP bit */ + TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)TIMER_MCHCTL2_MCH2FP); + /* set the MCH2FP bit */ + TIMER_MCHCTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->ocpolarity) << 4U); + + TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH2MS); + break; + + /* configure TIMER_MCH_3 */ + case TIMER_MCH_3: + TIMER_CTL2(timer_periph) &= (~(uint32_t)((uint32_t)TIMER_MCH_MODE_MASK << 26U)); + TIMER_CTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->outputmode) << 26U); + /* reset the MCH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_MCH3EN); + /* set the MCH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->outputstate) << 12U); + + /* reset the MCH3FP bit */ + TIMER_MCHCTL2(timer_periph) &= (~(uint32_t)TIMER_MCHCTL2_MCH3FP); + /* set the MCH3FP bit */ + TIMER_MCHCTL2(timer_periph) |= (uint32_t)((uint32_t)(omcpara->ocpolarity) << 6U); + + TIMER_MCHCTL1(timer_periph) &= (~(uint32_t)TIMER_MCHCTL1_MCH3MS); + + break; + default: + break; + } +} + +/*! + \brief multi mode channel mode select + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_MCH_0: TIMER multi mode channel 0(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_1: TIMER multi mode channel 1(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_2: TIMER multi mode channel 2(TIMERx(x=0,7,19,20)) + \arg TIMER_MCH_3: TIMER multi mode channel 3(TIMERx(x=0,7,19,20)) + \param[in] multi_mode_sel: multi mode channel mode selection + only one parameter can be selected which is shown as below: + \arg TIMER_MCH_MODE_INDEPENDENTLY: multi mode channel work in independently mode + \arg TIMER_MCH_MODE_MIRRORED: multi mode channel work in mirrored output mode + \arg TIMER_MCH_MODE_COMPLEMENTARY: multi mode channel work in complementary output mode + \param[out] none + \retval none +*/ +void timer_multi_mode_channel_mode_config(uint32_t timer_periph, uint32_t channel, uint32_t multi_mode_sel) +{ + uint32_t reg = TIMER_CTL2(timer_periph); + switch(channel) { + /* configure TIMER_MCH_0 */ + case TIMER_MCH_0: + reg &= (~(uint32_t)((uint32_t)TIMER_MCH_MODE_MASK << 20U)); + reg |= (uint32_t)(multi_mode_sel << 20U); + break; + /* configure TIMER_MCH_1 */ + case TIMER_MCH_1: + reg &= (~(uint32_t)((uint32_t)TIMER_MCH_MODE_MASK << 22U)); + reg |= (uint32_t)(multi_mode_sel << 22U); + break; + /* configure TIMER_MCH_2 */ + case TIMER_MCH_2: + reg &= (~(uint32_t)((uint32_t)TIMER_MCH_MODE_MASK << 24U)); + reg |= (uint32_t)(multi_mode_sel << 24U); + break; + /* configure TIMER_MCH_3 */ + case TIMER_MCH_3: + reg &= (~(uint32_t)((uint32_t)TIMER_MCH_MODE_MASK << 26U)); + reg |= (uint32_t)(multi_mode_sel << 26U); + break; + default: + break; + } + TIMER_CTL2(timer_periph) = reg; +} + + +/*! + \brief select TIMER input trigger source + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] intrigger: input trigger source + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0,1,7,19,20)) + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0,1,7,19,20)) + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0,1,7,19,20)) + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3(TIMERx(x=0,1,7,19,20)) + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0,1,7,19,20)) + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered channel 0 input(TIMERx(x=0,1,7,19,20)) + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered channel 1 input(TIMERx(x=0,1,7,19,20)) + \arg TIMER_SMCFG_TRGSEL_ETIFP: filtered external trigger input(TIMERx(x=0,1,7,19,20)) + \arg TIMER_SMCFG_TRGSEL_CI2FE2: filtered channel 2 input(TIMERx(x=0,7,19,20)) + \arg TIMER_SMCFG_TRGSEL_CI3FE3: filtered channel 3 input(TIMERx(x=0,7,19,20)) + \arg TIMER_SMCFG_TRGSEL_MCI0FEM0: filtered multi mode channel 0 input(TIMERx(x=0,7,19,20)) + \arg TIMER_SMCFG_TRGSEL_MCI1FEM1: filtered multi mode channel 1 input(TIMERx(x=0,7,19,20)) + \arg TIMER_SMCFG_TRGSEL_MCI2FEM2: filtered multi mode channel 2 input(TIMERx(x=0,7,19,20)) + \arg TIMER_SMCFG_TRGSEL_MCI3FEM3: filtered multi mode channel 3 input(TIMERx(x=0,7,19,20)) + \param[out] none + \retval none +*/ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) +{ + uint32_t reg; + + reg = TIMER_SMCFG(timer_periph); + reg &= (~(uint32_t)TIMER_SMCFG_TRGS); + reg |= (uint32_t)intrigger; + TIMER_SMCFG(timer_periph) = reg; +} + +/*! + \brief select TIMER master mode output trigger source + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[in] outrigger: trigger output source + only one parameter can be selected which is shown as below: + \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0,1,5,6,7,19,20)) + \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal as trigger output(TIMERx(x=0,1,5,6,7,19,20)) + \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0,1,5,6,7,19,20)) + \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channel 0 as trigger output TRGO(TIMERx(x=0,1,7,19,20)) + \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0,1,7,19,20)) + \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0,1,7,19,20)) + \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0,1,7,19,20)) + \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0,1,7,19,20)) + \param[out] none + \retval none +*/ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) +{ + uint32_t reg; + + reg = TIMER_CTL1(timer_periph); + reg &= (~(uint32_t)TIMER_CTL1_MMC); + reg |= (uint32_t)outrigger; + TIMER_CTL1(timer_periph) = reg; +} + +/*! + \brief select TIMER slave mode + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] slavemode: slave mode + only one parameter can be selected which is shown as below: + \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable + \arg TIMER_ENCODER_MODE0: encoder mode 0 + \arg TIMER_ENCODER_MODE1: encoder mode 1 + \arg TIMER_ENCODER_MODE2: encoder mode 2 + \arg TIMER_SLAVE_MODE_RESTART: restart mode + \arg TIMER_SLAVE_MODE_PAUSE: pause mode + \arg TIMER_SLAVE_MODE_EVENT: event mode + \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0 + \param[out] none + \retval none +*/ + +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) +{ + uint32_t reg; + + reg = TIMER_SMCFG(timer_periph); + reg &= (~(uint32_t)TIMER_SMCFG_SMC); + reg |= (uint32_t)slavemode; + TIMER_SMCFG(timer_periph) = reg; +} + +/*! + \brief configure TIMER master slave mode + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] masterslave: master slave mode + only one parameter can be selected which is shown as below: + \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable + \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable + \param[out] none + \retval none +*/ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) +{ + if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave) { + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; + } else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave) { + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER external trigger input + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] extprescaler: external trigger prescaler + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: external trigger polarity + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); +} + +/*! + \brief configure TIMER quadrature decoder mode + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] decomode: quadrature decoder mode + only one parameter can be selected which is shown as below: + \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level + \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level + \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input + \param[in] ic0polarity: input capture polarity + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \arg TIMER_IC_POLARITY_BOTH_EDGE: active both edge + \param[in] ic1polarity: input capture polarity + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \arg TIMER_IC_POLARITY_BOTH_EDGE: active both edge + \param[out] none + \retval none +*/ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity) +{ + /* configure the quadrature decoder mode */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; + /* configure input capture selection */ + TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); + /* configure channel input capture polarity */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_MCH0P)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_MCH1P)); + TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); +} + +/*! + \brief configure TIMER internal clock mode + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[out] none + \retval none +*/ +void timer_internal_clock_config(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; +} + +/*! + \brief configure TIMER the internal trigger as external clock input + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] intrigger: internal trigger selection + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 + \param[out] none + \retval none +*/ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) +{ + timer_input_trigger_source_select(timer_periph, intrigger); + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external trigger as external clock input + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] extrigger: external trigger selection + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered channel 0 input + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered channel 1 input + \param[in] extpolarity: external input capture polarity + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: active high or rising edge active + \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active + \arg TIMER_IC_POLARITY_BOTH_EDGE: active both edge + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter) +{ + if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger) { + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and MCH1P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_MCH1P)); + /* set the CH1P and MCH1P bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + } else { + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and MCH0P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_MCH0P)); + /* set the CH0P and MCH0P bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + } + /* select TIMER input trigger source */ + timer_input_trigger_source_select(timer_periph, extrigger); + /* reset the SMC bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + /* set the SMC bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external clock mode0 + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] extprescaler: external trigger prescaler + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: external input capture polarity + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + /* reset the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); + /* set the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); +} + +/*! + \brief configure TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] extprescaler: external trigger prescaler + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: external input capture polarity + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief disable TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_disable(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief configure TIMER channel input remap function + \param[in] timer_periph: TIMERx(x=1) + \param[in] remap: TIMER channel input remap + only one parameter can be selected which is shown as below: + \arg TIMER1_CI0_RMP_GPIO: TIMER1 channel 0 input remap to GPIO pin + \arg TIMER1_CI0_RMP_LXTAL: TIMER1 channel 0 input remap to LXTAL + \arg TIMER1_CI0_RMP_HXTAL: TIMER1 channel 0 input remap to HXTAL/128 + \arg TIMER1_CI0_RMP_CKOUT0SEL: TIMER1 channel 0 input remap to CKOUT0SEL + \param[out] none + \retval none +*/ +void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap) +{ + TIMER_IRMP(timer_periph) = (uint32_t)remap; +} + +/*! + \brief configure TIMER write CHxVAL register selection + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] ccsel: write CHxVAL register selection + only one parameter can be selected which is shown as below: + \arg TIMER_CHVSEL_DISABLE: no effect + \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored + \param[out] none + \retval none +*/ +void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) +{ + if(TIMER_CHVSEL_ENABLE == ccsel) { + TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; + } else if(TIMER_CHVSEL_DISABLE == ccsel) { + TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER output value selection + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] outsel: output value selection + only one parameter can be selected which is shown as below: + \arg TIMER_OUTSEL_DISABLE: no effect + \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled + \param[out] none + \retval none +*/ +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) +{ + if(TIMER_OUTSEL_ENABLE == outsel) { + TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; + } else if(TIMER_OUTSEL_DISABLE == outsel) { + TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER output match pulse selection + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(x=0,7,19,20) + \arg TIMER_CH_1: TIMER channel 1(x=0,7,19,20) + \arg TIMER_CH_2: TIMER channel 2(x=0,7,19,20) + \arg TIMER_CH_3: TIMER channel 3(x=0,7,19,20) + \param[in] pulsesel: output match pulse selection + only one parameter can be selected which is shown as below: + \arg TIMER_PULSE_OUTPUT_NORMAL: channel output normal + \arg TIMER_PULSE_OUTPUT_CNT_UP: pulse output only when counting up + \arg TIMER_PULSE_OUTPUT_CNT_DOWN: pulse output only when counting down + \arg TIMER_PULSE_OUTPUT_CNT_BOTH: pulse output when counting up or down + \param[out] none + \retval none +*/ +void timer_output_match_pulse_select(uint32_t timer_periph, uint32_t channel, uint16_t pulsesel) +{ + uint32_t reg; + reg = TIMER_CTL2(timer_periph); + + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + reg &= (~(uint32_t)((uint32_t)TIMER_PULSE_OUTPUT_MASK << 8U)); + reg |= (uint32_t)((uint32_t)pulsesel << 8U); + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + reg &= (~(uint32_t)((uint32_t)TIMER_PULSE_OUTPUT_MASK << 10U)); + reg |= (uint32_t)((uint32_t)pulsesel << 10U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + reg &= (~(uint32_t)((uint32_t)TIMER_PULSE_OUTPUT_MASK << 12U)); + reg |= (uint32_t)((uint32_t)pulsesel << 12U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + reg &= (~(uint32_t)((uint32_t)TIMER_PULSE_OUTPUT_MASK << 14U)); + reg |= (uint32_t)((uint32_t)pulsesel << 14U); + break; + default: + break; + } + TIMER_CTL2(timer_periph) = reg; +} + +/*! + \brief configure the TIMER composite PWM mode + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(x=0,7,19,20) + \arg TIMER_CH_1: TIMER channel 1(x=0,7,19,20) + \arg TIMER_CH_2: TIMER channel 2(x=0,7,19,20) + \arg TIMER_CH_3: TIMER channel 3(x=0,7,19,20) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_channel_composite_pwm_mode_config(uint32_t timer_periph, uint32_t channel, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + TIMER_CTL2(timer_periph) |= (uint32_t)(TIMER_CTL2_CH0CPWMEN << channel); + } else { + TIMER_CTL2(timer_periph) &= (~(uint32_t)(TIMER_CTL2_CH0CPWMEN << channel)); + } +} + +/*! + \brief configure the TIMER composite PWM mode output pulse value + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(x=0,7,19,20) + \arg TIMER_CH_1: TIMER channel 1(x=0,7,19,20) + \arg TIMER_CH_2: TIMER channel 2(x=0,7,19,20) + \arg TIMER_CH_3: TIMER channel 3(x=0,7,19,20) + \param[in] pulse: channel compare value, 0~65535 + \param[in] add_pulse: channel additional compare value, 0~65535 + \param[out] none + \retval none +*/ +void timer_channel_composite_pwm_mode_output_pulse_value_config(uint32_t timer_periph, uint32_t channel, uint32_t pulse, uint32_t add_pulse) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CH0CV(timer_periph) = (uint32_t)pulse; + TIMER_CH0COMV_ADD(timer_periph) = (uint32_t)add_pulse; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CH1CV(timer_periph) = (uint32_t)pulse; + TIMER_CH1COMV_ADD(timer_periph) = (uint32_t)add_pulse; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CH2CV(timer_periph) = (uint32_t)pulse; + TIMER_CH2COMV_ADD(timer_periph) = (uint32_t)add_pulse; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; + TIMER_CH3COMV_ADD(timer_periph) = (uint32_t)add_pulse; + break; + default: + break; + } +} + + +/*! + \brief configure TIMER channel additional compare value + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(x=0,7,19,20) + \arg TIMER_CH_1: TIMER channel 1(x=0,7,19,20) + \arg TIMER_CH_2: TIMER channel 2(x=0,7,19,20) + \arg TIMER_CH_3: TIMER channel 3(x=0,7,19,20) + \param[in] value: channel additional compare value, 0~65535 + \param[out] none + \retval none +*/ +void timer_channel_additional_compare_value_config(uint32_t timer_periph, uint16_t channel, uint32_t value) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CH0COMV_ADD(timer_periph) = (uint32_t)value; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CH1COMV_ADD(timer_periph) = (uint32_t)value; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CH2COMV_ADD(timer_periph) = (uint32_t)value; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CH3COMV_ADD(timer_periph) = (uint32_t)value; + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel additional output shadow function + \param[in] timer_periph: TIMERx(x=0,1,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,1,7,19,20)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,1,7,19,20)) + \param[in] aocshadow: channel additional output compare shadow + only one parameter can be selected which is shown as below: + \arg TIMER_ADD_SHADOW_ENABLE: channel additional output compare shadow enable + \arg TIMER_ADD_SHADOW_DISABLE: channel additional output compare shadow disable + \param[out] none + \retval none +*/ +void timer_channel_additional_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t aocshadow) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMADDSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)aocshadow << 28U); + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMADDSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)aocshadow << 29U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMADDSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)aocshadow << 28U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMADDSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)aocshadow << 29U); + break; + default: + break; + } +} + +/*! + \brief initialize TIMER break external input parameter struct with a default value + \param[in] breakinpara: TIMER break external input parameter struct + \param[out] none + \retval none +*/ +void timer_break_external_input_struct_para_init(timer_break_ext_input_struct *breakinpara) +{ + /* initialize the break parameter struct member with the default value */ + breakinpara->filter = 0U; + breakinpara->enable = TIMER_IOS_STATE_DISABLE; + breakinpara->polarity = TIMER_BRKIN_POLARITY_LOW; +} + +/*! + \brief configure break external input + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] break_input: break external input + only one parameter can be selected which is shown as below: + \arg TIMER_BREAKINPUT_BRK0: TIMER break external input 0 + \arg TIMER_BREAKINPUT_BRK1: TIMER break external input 1 + \arg TIMER_BREAKINPUT_BRK2: TIMER break external input 2 + \arg TIMER_BREAKINPUT_BRK3: TIMER break external input 3 + \param[in] breakinpara: break external input parameter struct + filter:: 0~15 + enable: ENABLE or DISABLE + polarity: TIMER_BRKIN_POLARITY_HIGH, TIMER_BRKIN_POLARITY_LOW + \param[out] none + \retval none +*/ +void timer_break_external_input_config(uint32_t timer_periph, uint32_t break_input, timer_break_ext_input_struct *breakinpara) +{ + uint32_t reg = 0U; + reg = TIMER_BRKCFG(timer_periph); + reg &= (~(uint32_t)((0x03000000U << (break_input << 1U) | ((uint32_t)0x0000000FU << (break_input << 2U))))); + + reg |= ((breakinpara->filter << (break_input << 2U)) | + (breakinpara->enable << ((break_input << 1U) + 24U)) | + (breakinpara->polarity << ((break_input << 1U) + 25U))); + + TIMER_BRKCFG(timer_periph) = reg; +} + +/*! + \brief break external input enable + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] break_input: break external input + only one parameter can be selected which is shown as below: + \arg TIMER_BREAKINPUT_BRK0: TIMER break external input 0 + \arg TIMER_BREAKINPUT_BRK1: TIMER break external input 1 + \arg TIMER_BREAKINPUT_BRK2: TIMER break external input 2 + \arg TIMER_BREAKINPUT_BRK3: TIMER break external input 3 + \param[out] none + \retval none +*/ +void timer_break_external_input_enable(uint32_t timer_periph, uint32_t break_input) +{ + TIMER_BRKCFG(timer_periph) |= (uint32_t)(TIMER_BRKCFG_BRK0EN << (break_input << 1U)); +} + +/*! + \brief break external input disable + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] break_input: break external input + only one parameter can be selected which is shown as below: + \arg TIMER_BREAKINPUT_BRK0: TIMER break external input 0 + \arg TIMER_BREAKINPUT_BRK1: TIMER break external input 1 + \arg TIMER_BREAKINPUT_BRK2: TIMER break external input 2 + \arg TIMER_BREAKINPUT_BRK3: TIMER break external input 3 + \param[out] none + \retval none +*/ +void timer_break_external_input_disable(uint32_t timer_periph, uint32_t break_input) +{ + TIMER_BRKCFG(timer_periph) &= (~(uint32_t)(TIMER_BRKCFG_BRK0EN << (break_input << 1U))); +} + +/*! + \brief configure TIMER break external input polarity + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] break_input: break external input + only one parameter can be selected which is shown as below: + \arg TIMER_BREAKINPUT_BRK0: TIMER break external input 0(TIMERx(x=0,7,19,20) + \arg TIMER_BREAKINPUT_BRK1: TIMER break external input 1(TIMERx(x=0,7,19,20) + \arg TIMER_BREAKINPUT_BRK2: TIMER break external input 2(TIMERx(x=0,7,19,20) + \arg TIMER_BREAKINPUT_BRK3: TIMER break external input 3(TIMERx(x=0,7,19,20) + \param[in] polarity: break external input polarity + only one parameter can be selected which is shown as below: + \arg TIMER_BRKIN_POLARITY_HIGH: break external input polarity is high + \arg TIMER_BRKIN_POLARITY_LOW: break external input polarity is low + \param[out] none + \retval none +*/ +void timer_break_external_input_polarity_config(uint32_t timer_periph, uint32_t break_input, uint32_t polarity) +{ + if(polarity == TIMER_BRKIN_POLARITY_HIGH) { + TIMER_BRKCFG(timer_periph) |= (uint32_t)(TIMER_BRKCFG_BRK0P << (break_input << 1U)); + } else { + TIMER_BRKCFG(timer_periph) &= (~(uint32_t)(TIMER_BRKCFG_BRK0P << (break_input << 1U))); + } +} + +/*! + \brief configure the TIMER channel break function + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0 + \arg TIMER_CH_1: TIMER channel 1 + \arg TIMER_CH_2: TIMER channel 2 + \arg TIMER_CH_3: TIMER channel 3 + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_channel_break_control_config(uint32_t timer_periph, uint32_t channel, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + TIMER_CTL2(timer_periph) |= (uint32_t)(TIMER_CTL2_BRKENCH0 << channel); + } else { + TIMER_CTL2(timer_periph) &= (~(uint32_t)(TIMER_CTL2_BRKENCH0 << channel)); + } +} + +/*! + \brief configure the TIMER channel free dead time function + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0 + \arg TIMER_CH_1: TIMER channel 1 + \arg TIMER_CH_2: TIMER channel 2 + \arg TIMER_CH_3: TIMER channel 3 + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_channel_dead_time_config(uint32_t timer_periph, uint32_t channel, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + TIMER_CTL2(timer_periph) |= (uint32_t)(TIMER_CTL2_DTIENCH0 << channel); + } else { + TIMER_CTL2(timer_periph) &= (~(uint32_t)(TIMER_CTL2_DTIENCH0 << channel)); + } +} + +/*! + \brief initialize TIMER channel free complementary parameter struct with a default value + \param[in] none + \param[out] freecompara: TIMER channel free complementary parameter struct + \retval none +*/ +void timer_free_complementary_struct_para_init(timer_free_complementary_parameter_struct *freecompara) +{ + /* initialize the channel free complementary parameter struct member with the default value */ + freecompara->freecomstate = TIMER_FCCHP_STATE_DISABLE; + freecompara->runoffstate = TIMER_ROS_STATE_DISABLE; + freecompara->ideloffstate = TIMER_IOS_STATE_DISABLE; + freecompara->deadtime = 0U; +} + +/*! + \brief configure channel free complementary protection + \param[in] timer_periph: TIMERx(x=0,7,19,20) + \param[in] channel: TIMER channel + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0 + \arg TIMER_CH_1: TIMER channel 1 + \arg TIMER_CH_2: TIMER channel 2 + \arg TIMER_CH_3: TIMER channel 3 + \param[in] fcpara: TIMER channel free complementary parameter struct + freecomstate: TIMER_FCCHP_STATE_ENABLE, TIMER_FCCHP_STATE_DISABLE + runoffstate: TIMER_ROS_STATE_ENABLE, TIMER_ROS_STATE_DISABLE + ideloffstate: TIMER_IOS_STATE_ENABLE, TIMER_IOS_STATE_DISABLE + deadtime: 0~255 + \param[out] none + \retval none +*/ +void timer_channel_free_complementary_config(uint32_t timer_periph, uint16_t channel, timer_free_complementary_parameter_struct *fcpara) +{ + switch(channel) { + case TIMER_CH_0: + TIMER_FCCHP0(timer_periph) &= (~(uint32_t)(TIMER_FCCHP0_DTCFG | TIMER_FCCHP0_IOS | TIMER_FCCHP0_ROS | TIMER_FCCHP0_FCCHP0EN)); + TIMER_FCCHP0(timer_periph) |= fcpara->deadtime; + TIMER_FCCHP0(timer_periph) |= fcpara->ideloffstate; + TIMER_FCCHP0(timer_periph) |= fcpara->runoffstate; + TIMER_FCCHP0(timer_periph) |= fcpara->freecomstate; + break; + case TIMER_CH_1: + TIMER_FCCHP1(timer_periph) &= (~(uint32_t)(TIMER_FCCHP1_DTCFG | TIMER_FCCHP1_IOS | TIMER_FCCHP1_ROS | TIMER_FCCHP1_FCCHP1EN)); + TIMER_FCCHP1(timer_periph) |= fcpara->deadtime; + TIMER_FCCHP1(timer_periph) |= fcpara->ideloffstate; + TIMER_FCCHP1(timer_periph) |= fcpara->runoffstate; + TIMER_FCCHP1(timer_periph) |= fcpara->freecomstate; + break; + case TIMER_CH_2: + TIMER_FCCHP2(timer_periph) &= (~(uint32_t)(TIMER_FCCHP2_DTCFG | TIMER_FCCHP2_IOS | TIMER_FCCHP2_ROS | TIMER_FCCHP2_FCCHP2EN)); + TIMER_FCCHP2(timer_periph) |= fcpara->deadtime; + TIMER_FCCHP2(timer_periph) |= fcpara->ideloffstate; + TIMER_FCCHP2(timer_periph) |= fcpara->runoffstate; + TIMER_FCCHP2(timer_periph) |= fcpara->freecomstate; + break; + case TIMER_CH_3: + TIMER_FCCHP3(timer_periph) &= (~(uint32_t)(TIMER_FCCHP3_DTCFG | TIMER_FCCHP3_IOS | TIMER_FCCHP3_ROS | TIMER_FCCHP3_FCCHP3EN)); + TIMER_FCCHP3(timer_periph) |= fcpara->deadtime; + TIMER_FCCHP3(timer_periph) |= fcpara->ideloffstate; + TIMER_FCCHP3(timer_periph) |= fcpara->runoffstate; + TIMER_FCCHP3(timer_periph) |= fcpara->freecomstate; + break; + default: + break; + } +} + +/*! + \brief get TIMER flags + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[in] flag: the TIMER flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag, TIMERx(x=0,1,5,6,7,19,20) + \arg TIMER_FLAG_CH0: channel 0 capture or compare flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_CH1: channel 1 capture or compare flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_CH2: channel 2 capture or compare flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_CH3: channel 3 capture or compare flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_BRK: break flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_MCH0: multi mode channel 0 capture or compare flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_MCH1: multi mode channel 1 capture or compare flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_MCH2: multi mode channel 2 capture or compare flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_MCH3: multi mode channel 3 capture or compare flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_MCH0O: multi mode channel 0 overcapture flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_MCH1O: multi mode channel 1 overcapture flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_MCH2O: multi mode channel 2 overcapture flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_MCH3O: multi mode channel 3 overcapture flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_CH0COMADD: channel 0 additional compare flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_CH1COMADD: channel 1 additional compare flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_CH2COMADD: channel 2 additional compare flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_CH3COMADD: channel 3 additional compare flag, TIMERx(x=0,7,19,20) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) +{ + if((uint32_t)RESET != (TIMER_INTF(timer_periph) & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER flags + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[in] flag: the TIMER flags + one or more parameters can be selected which are shown as below: + \arg TIMER_FLAG_UP: update flag, TIMERx(x=0,1,5,6,7,19,20) + \arg TIMER_FLAG_CH0: channel 0 capture or compare flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_CH1: channel 1 capture or compare flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_CH2: channel 2 capture or compare flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_CH3: channel 3 capture or compare flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_BRK: break flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_FLAG_MCH0: multi mode channel 0 capture or compare flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_MCH1: multi mode channel 1 capture or compare flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_MCH2: multi mode channel 2 capture or compare flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_MCH3: multi mode channel 3 capture or compare flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_MCH0O: multi mode channel 0 overcapture flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_MCH1O: multi mode channel 1 overcapture flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_MCH2O: multi mode channel 2 overcapture flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_MCH3O: multi mode channel 3 overcapture flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_CH0COMADD: channel 0 additional compare flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_CH1COMADD: channel 1 additional compare flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_CH2COMADD: channel 2 additional compare flag, TIMERx(x=0,7,19,20) + \arg TIMER_FLAG_CH3COMADD: channel 3 additional compare flag, TIMERx(x=0,7,19,20) + \param[out] none + \retval none +*/ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag) +{ + TIMER_INTF(timer_periph) &= (~(uint32_t)flag); +} + +/*! + \brief enable the TIMER interrupt + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[in] interrupt: timer interrupt source + one or more parameters can be selected which are shown as below: + \arg TIMER_INT_UP: update interrupt, TIMERx(x=0,1,5,6,7,19,20) + \arg TIMER_INT_CH0: channel 0 capture or compare interrupt, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_CH1: channel 1 capture or compare interrupt, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_CH2: channel 2 capture or compare interrupt, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_CH3: channel 3 capture or compare interrupt, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_CMT: commutation interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_TRG: trigger interrupt, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_BRK: break interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_MCH0: multi mode channel 0 capture or compare interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_MCH1: multi mode channel 1 capture or compare interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_MCH2: multi mode channel 2 capture or compare interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_MCH3: multi mode channel 3 capture or compare interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_CH0COMADD: channel 0 additional compare interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_CH1COMADD: channel 1 additional compare interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_CH2COMADD: channel 2 additional compare interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_CH3COMADD: channel 3 additional compare interrupt, TIMERx(x=0,7,19,20) + \param[out] none + \retval none +*/ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; +} + +/*! + \brief disable the TIMER interrupt + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[in] interrupt: timer interrupt source + one or more parameters can be selected which are shown as below: + \arg TIMER_INT_UP: update interrupt, TIMERx(x=0,1,5,6,7,19,20) + \arg TIMER_INT_CH0: channel 0 capture or compare interrupt, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_CH1: channel 1 capture or compare interrupt, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_CH2: channel 2 capture or compare interrupt, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_CH3: channel 3 capture or compare interrupt, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_CMT: commutation interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_TRG: trigger interrupt, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_BRK: break interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_MCH0: multi mode channel 0 capture or compare interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_MCH1: multi mode channel 1 capture or compare interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_MCH2: multi mode channel 2 capture or compare interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_MCH3: multi mode channel 3 capture or compare interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_CH0COMADD: channel 0 additional compare interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_CH1COMADD: channel 1 additional compare interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_CH2COMADD: channel 2 additional compare interrupt, TIMERx(x=0,7,19,20) + \arg TIMER_INT_CH3COMADD: channel 3 additional compare interrupt, TIMERx(x=0,7,19,20) + \param[out] none + \retval none +*/ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get timer interrupt flags + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[in] int_flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0,1,5,6,7,19,20) + \arg TIMER_INT_FLAG_CH0: channel 0 capture or compare interrupt flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_FLAG_CH1: channel 1 capture or compare interrupt flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_FLAG_CH2: channel 2 capture or compare interrupt flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_FLAG_CH3: channel 3 capture or compare interrupt flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_MCH0: multi mode channel 0 capture or compare interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_MCH1: multi mode channel 1 capture or compare interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_MCH2: multi mode channel 2 capture or compare interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_MCH3: multi mode channel 3 capture or compare interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_CH0COMADD: channel 0 additional compare interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_CH1COMADD: channel 1 additional compare interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_CH2COMADD: channel 2 additional compare interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_CH3COMADD: channel 3 additional compare interrupt flag, TIMERx(x=0,7,19,20) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t int_flag) +{ + uint32_t val; + val = (TIMER_DMAINTEN(timer_periph) & int_flag); + if(((uint32_t)RESET != (TIMER_INTF(timer_periph) & int_flag)) && ((uint32_t)RESET != val)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER interrupt flags + \param[in] timer_periph: TIMERx(x=0,1,5,6,7,19,20) + \param[in] int_flag: the timer interrupt flags + one or more parameters can be selected which are shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0,1,5,6,7,19,20) + \arg TIMER_INT_FLAG_CH0: channel 0 capture or compare interrupt flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_FLAG_CH1: channel 1 capture or compare interrupt flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_FLAG_CH2: channel 2 capture or compare interrupt flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_FLAG_CH3: channel 3 capture or compare interrupt flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0,1,7,19,20) + \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_MCH0: multi mode channel 0 capture or compare interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_MCH1: multi mode channel 1 capture or compare interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_MCH2: multi mode channel 2 capture or compare interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_MCH3: multi mode channel 3 capture or compare interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_CH0COMADD: channel 0 additional compare interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_CH1COMADD: channel 1 additional compare interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_CH2COMADD: channel 2 additional compare interrupt flag, TIMERx(x=0,7,19,20) + \arg TIMER_INT_FLAG_CH3COMADD: channel 3 additional compare interrupt flag, TIMERx(x=0,7,19,20) + \param[out] none + \retval none +*/ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t int_flag) +{ + TIMER_INTF(timer_periph) &= (~(uint32_t)int_flag); +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_trigsel.c b/gd32a50x/standard_peripheral/source/gd32a50x_trigsel.c new file mode 100644 index 0000000..5d2e3df --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_trigsel.c @@ -0,0 +1,382 @@ +/*! + \file gd32a50x_trigsel.c + \brief TRIGSEL driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_trigsel.h" + +/* TRIGSEL target register redefine */ +#define TRIGSEL_TARGET_REG(target_periph) REG32(TRIGSEL + ((uint8_t)(target_periph) & BITS(2, 7))) /*!< target peripheral register */ +#define TRIGSEL_TARGET_PERIPH_SHIFT(target_periph) (((uint8_t)(target_periph) & BITS(0, 1)) << 3) /*!< bit shift in target peripheral register */ +#define TRIGSEL_TARGET_PERIPH_MASK(target_periph) ((uint32_t)(TRIGSEL_TARGET_INSEL0 << TRIGSEL_TARGET_PERIPH_SHIFT(target_periph))) /*!< bit mask in target peripheral register */ + +/*! + \brief set the trigger input signal for target peripheral + \param[in] target_periph: target peripheral value + only one parameter can be selected which is shown as below: + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT0: output target peripheral TRIGSEL_OUT0 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT1: output target peripheral TRIGSEL_OUT1 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT2: output target peripheral TRIGSEL_OUT2 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT3: output target peripheral TRIGSEL_OUT3 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT4: output target peripheral TRIGSEL_OUT4 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT5: output target peripheral TRIGSEL_OUT5 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT6: output target peripheral TRIGSEL_OUT6 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT7: output target peripheral TRIGSEL_OUT7 pin + \arg TRIGSEL_OUTPUT_ADC0_RTTRG: output target peripheral ADC0_RTTRG + \arg TRIGSEL_OUTPUT_ADC1_RTTRG: output target peripheral ADC1_RTTRG + \arg TRIGSEL_OUTPUT_DAC_EXTRIG: output target peripheral DAC_EXTRIG + \arg TRIGSEL_OUTPUT_TIMER0_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER0_ITI1: output target peripheral TIMER0_ITI1 + \arg TRIGSEL_OUTPUT_TIMER0_ITI2: output target peripheral TIMER0_ITI2 + \arg TRIGSEL_OUTPUT_TIMER0_ITI3: output target peripheral TIMER0_ITI3 + \arg TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN0 + \arg TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN1 + \arg TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN2 + \arg TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN3 + \arg TRIGSEL_OUTPUT_TIMER7_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER7_ITI1: output target peripheral TIMER0_ITI1 + \arg TRIGSEL_OUTPUT_TIMER7_ITI2: output target peripheral TIMER0_ITI2 + \arg TRIGSEL_OUTPUT_TIMER7_ITI3: output target peripheral TIMER0_ITI3 + \arg TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN0 + \arg TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN1 + \arg TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN2 + \arg TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN3 + \arg TRIGSEL_OUTPUT_TIMER1_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER1_ITI1: output target peripheral TIMER0_ITI1 + \arg TRIGSEL_OUTPUT_TIMER1_ITI2: output target peripheral TIMER0_ITI2 + \arg TRIGSEL_OUTPUT_TIMER1_ITI3: output target peripheral TIMER0_ITI3 + \arg TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN0 + \arg TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN1 + \arg TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN2 + \arg TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN3 + \arg TRIGSEL_OUTPUT_TIMER20_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER20_ITI1: output target peripheral TIMER0_ITI1 + \arg TRIGSEL_OUTPUT_TIMER20_ITI2: output target peripheral TIMER0_ITI2 + \arg TRIGSEL_OUTPUT_TIMER20_ITI3: output target peripheral TIMER0_ITI3 + \arg TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN0 + \arg TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN1 + \arg TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN2 + \arg TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN3 + \arg TRIGSEL_OUTPUT_TIMER1_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER1_ITI1: output target peripheral TIMER1_ITI1 + \arg TRIGSEL_OUTPUT_TIMER1_ITI2: output target peripheral TIMER1_ITI2 + \arg TRIGSEL_OUTPUT_TIMER1_ITI3: output target peripheral TIMER1_ITI3 + \arg TRIGSEL_OUTPUT_MFCOM_TRG_TIMER0 output target peripheral MFCOM_TRG_TIMER0 + \arg TRIGSEL_OUTPUT_MFCOM_TRG_TIMER1 output target peripheral MFCOM_TRG_TIMER1 + \arg TRIGSEL_OUTPUT_MFCOM_TRG_TIMER2 output target peripheral MFCOM_TRG_TIMER2 + \arg TRIGSEL_OUTPUT_MFCOM_TRG_TIMER3 output target peripheral MFCOM_TRG_TIMER3 + \arg TRIGSEL_OUTPUT_CAN0_EX_TIME_TICK output target peripheral CAN0_EX_TIME_TICK + \arg TRIGSEL_OUTPUT_CAN1_EX_TIME_TICK output target peripheral CAN1_EX_TIME_TICK + \param[in] trigger_source: trigger source value + only one parameter can be selected which is shown as below: + \arg TRIGSEL_INPUT_0: trigger input source 0 + \arg TRIGSEL_INPUT_1: trigger input source 1 + \arg TRIGSEL_INPUT_TRIGSEL_IN0: trigger input source TRIGSEL_IN0 pin + \arg TRIGSEL_INPUT_TRIGSEL_IN1: trigger input source TRIGSEL_IN1 pin + \arg TRIGSEL_INPUT_TRIGSEL_IN2: trigger input source TRIGSEL_IN2 pin + \arg TRIGSEL_INPUT_TRIGSEL_IN3: trigger input source TRIGSEL_IN3 pin + \arg TRIGSEL_INPUT_TRIGSEL_IN4: trigger input source TRIGSEL_IN4 pin + \arg TRIGSEL_INPUT_TRIGSEL_IN5: trigger input source TRIGSEL_IN5 pin + \arg TRIGSEL_INPUT_TRIGSEL_IN6: trigger input source TRIGSEL_IN6 pin + \arg TRIGSEL_INPUT_TRIGSEL_IN7: trigger input source TRIGSEL_IN7 pin + \arg TRIGSEL_INPUT_TRIGSEL_IN8: trigger input source TRIGSEL_IN8 pin + \arg TRIGSEL_INPUT_TRIGSEL_IN9: trigger input source TRIGSEL_IN9 pin + \arg TRIGSEL_INPUT_TRIGSEL_IN10: trigger input source TRIGSEL_IN10 pin + \arg TRIGSEL_INPUT_TRIGSEL_IN11: trigger input source TRIGSEL_IN11 pin + \arg TRIGSEL_INPUT_CMP_OUT: trigger input source CMP_OUT + \arg TRIGSEL_INPUT_LXTAL_TRG: trigger input source LSE_TRG + \arg TRIGSEL_INPUT_TIMER1_CH0: trigger input source timer1 channel 0 + \arg TRIGSEL_INPUT_TIMER1_CH1: trigger input source timer1 channel 1 + \arg TRIGSEL_INPUT_TIMER1_CH2: trigger input source timer1 channel 2 + \arg TRIGSEL_INPUT_TIMER1_CH3: trigger input source timer1 channel 3 + \arg TRIGSEL_INPUT_TIMER1_TRGO: trigger input source timer1 TRGO + \arg TRIGSEL_INPUT_TIMER0_CH0: trigger input source timer0 channel 0 + \arg TRIGSEL_INPUT_TIMER0_CH1: trigger input source timer0 channel 1 + \arg TRIGSEL_INPUT_TIMER0_CH2: trigger input source timer0 channel 2 + \arg TRIGSEL_INPUT_TIMER0_CH3: trigger input source timer0 channel 3 + \arg TRIGSEL_INPUT_TIMER0_MCH0: trigger input source timer0 channel 0N + \arg TRIGSEL_INPUT_TIMER0_MCH1: trigger input source timer0 channel 1N + \arg TRIGSEL_INPUT_TIMER0_MCH2: trigger input source timer0 channel 2N + \arg TRIGSEL_INPUT_TIMER0_MCH3: trigger input source timer0 channel 3N + \arg TRIGSEL_INPUT_TIMER0_TRGO: trigger input source timer0 TRGO + \arg TRIGSEL_INPUT_TIMER7_CH0: trigger input source timer7 channel 0 + \arg TRIGSEL_INPUT_TIMER7_CH1: trigger input source timer7 channel 1 + \arg TRIGSEL_INPUT_TIMER7_CH2: trigger input source timer7 channel 2 + \arg TRIGSEL_INPUT_TIMER7_CH3: trigger input source timer7 channel 3 + \arg TRIGSEL_INPUT_TIMER7_MCH0: trigger input source timer7 channel 0N + \arg TRIGSEL_INPUT_TIMER7_MCH1: trigger input source timer7 channel 1N + \arg TRIGSEL_INPUT_TIMER7_MCH2: trigger input source timer7 channel 2N + \arg TRIGSEL_INPUT_TIMER7_MCH3: trigger input source timer7 channel 3N + \arg TRIGSEL_INPUT_TIMER7_TRGO: trigger input source timer7 TRGO + \arg TRIGSEL_INPUT_TIMER19_CH0: trigger input source timer19 channel 0 + \arg TRIGSEL_INPUT_TIMER19_CH1: trigger input source timer19 channel 1 + \arg TRIGSEL_INPUT_TIMER19_CH2: trigger input source timer19 channel 2 + \arg TRIGSEL_INPUT_TIMER19_CH3: trigger input source timer19 channel 3 + \arg TRIGSEL_INPUT_TIMER19_MCH0: trigger input source timer19 channel 0N + \arg TRIGSEL_INPUT_TIMER19_MCH1: trigger input source timer19 channel 1N + \arg TRIGSEL_INPUT_TIMER19_MCH2: trigger input source timer19 channel 2N + \arg TRIGSEL_INPUT_TIMER19_MCH3: trigger input source timer19 channel 3N + \arg TRIGSEL_INPUT_TIMER19_TRGO: trigger input source timer19 TRGO + \arg TRIGSEL_INPUT_TIMER20_CH0: trigger input source timer20 channel 0 + \arg TRIGSEL_INPUT_TIMER20_CH1: trigger input source timer20 channel 1 + \arg TRIGSEL_INPUT_TIMER20_CH2: trigger input source timer20 channel 2 + \arg TRIGSEL_INPUT_TIMER20_CH3: trigger input source timer20 channel 3 + \arg TRIGSEL_INPUT_TIMER20_MCH0: trigger input source timer20 channel 0N + \arg TRIGSEL_INPUT_TIMER20_MCH1: trigger input source timer20 channel 1N + \arg TRIGSEL_INPUT_TIMER20_MCH2: trigger input source timer20 channel 2N + \arg TRIGSEL_INPUT_TIMER20_MCH3: trigger input source timer20 channel 3N + \arg TRIGSEL_INPUT_TIMER20_TRGO: trigger input source timer20 TRGO + \arg TRIGSEL_INPUT_TIMER5_TRGO: trigger input source timer5 TRGO + \arg TRIGSEL_INPUT_TIMER6_TRGO: trigger input source timer6 TRGO + \arg TRIGSEL_INPUT_MFCOM_TRIG0: trigger input source MFCOM TRIG0 + \arg TRIGSEL_INPUT_MFCOM_TRIG1: trigger input source MFCOM TRIG1 + \arg TRIGSEL_INPUT_MFCOM_TRIG2: trigger input source MFCOM TRIG2 + \arg TRIGSEL_INPUT_MFCOM_TRIG3: trigger input source MFCOM TRIG3 + \arg TRIGSEL_INPUT_RTC_ALARM: trigger input source RTC alarm + \arg TRIGSEL_INPUT_RTC_SECOND: trigger input source RTC second + \arg TRIGSEL_INPUT_TRIGSEL_IN12: trigger input source TRIGSEL_IN12 pin + \arg TRIGSEL_INPUT_TRIGSEL_IN13: trigger input source TRIGSEL_IN13 pin + \param[out] none + \retval none +*/ +void trigsel_init(trigsel_periph_enum target_periph, trigsel_source_enum trigger_source) +{ + /* if register write is enabled, set trigger source to target peripheral */ + if (RESET == trigsel_register_lock_get(target_periph)){ + TRIGSEL_TARGET_REG(target_periph) &= ~TRIGSEL_TARGET_PERIPH_MASK(target_periph); + TRIGSEL_TARGET_REG(target_periph) |= ((uint32_t)trigger_source << TRIGSEL_TARGET_PERIPH_SHIFT(target_periph)) & TRIGSEL_TARGET_PERIPH_MASK(target_periph); + } +} + +/*! + \brief get the trigger input signal for target peripheral + \param[in] target_periph: target peripheral value + only one parameter can be selected which is shown as below: + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT0: output target peripheral TRIGSEL_OUT0 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT1: output target peripheral TRIGSEL_OUT1 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT2: output target peripheral TRIGSEL_OUT2 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT3: output target peripheral TRIGSEL_OUT3 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT4: output target peripheral TRIGSEL_OUT4 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT5: output target peripheral TRIGSEL_OUT5 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT6: output target peripheral TRIGSEL_OUT6 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT7: output target peripheral TRIGSEL_OUT7 pin + \arg TRIGSEL_OUTPUT_ADC0_RTTRG: output target peripheral ADC0_RTTRG + \arg TRIGSEL_OUTPUT_ADC1_RTTRG: output target peripheral ADC1_RTTRG + \arg TRIGSEL_OUTPUT_DAC_EXTRIG: output target peripheral DAC_EXTRIG + \arg TRIGSEL_OUTPUT_TIMER0_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER0_ITI1: output target peripheral TIMER0_ITI1 + \arg TRIGSEL_OUTPUT_TIMER0_ITI2: output target peripheral TIMER0_ITI2 + \arg TRIGSEL_OUTPUT_TIMER0_ITI3: output target peripheral TIMER0_ITI3 + \arg TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN0 + \arg TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN1 + \arg TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN2 + \arg TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN3 + \arg TRIGSEL_OUTPUT_TIMER7_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER7_ITI1: output target peripheral TIMER0_ITI1 + \arg TRIGSEL_OUTPUT_TIMER7_ITI2: output target peripheral TIMER0_ITI2 + \arg TRIGSEL_OUTPUT_TIMER7_ITI3: output target peripheral TIMER0_ITI3 + \arg TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN0 + \arg TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN1 + \arg TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN2 + \arg TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN3 + \arg TRIGSEL_OUTPUT_TIMER1_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER1_ITI1: output target peripheral TIMER0_ITI1 + \arg TRIGSEL_OUTPUT_TIMER1_ITI2: output target peripheral TIMER0_ITI2 + \arg TRIGSEL_OUTPUT_TIMER1_ITI3: output target peripheral TIMER0_ITI3 + \arg TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN0 + \arg TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN1 + \arg TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN2 + \arg TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN3 + \arg TRIGSEL_OUTPUT_TIMER20_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER20_ITI1: output target peripheral TIMER0_ITI1 + \arg TRIGSEL_OUTPUT_TIMER20_ITI2: output target peripheral TIMER0_ITI2 + \arg TRIGSEL_OUTPUT_TIMER20_ITI3: output target peripheral TIMER0_ITI3 + \arg TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN0 + \arg TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN1 + \arg TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN2 + \arg TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN3 + \arg TRIGSEL_OUTPUT_TIMER1_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER1_ITI1: output target peripheral TIMER1_ITI1 + \arg TRIGSEL_OUTPUT_TIMER1_ITI2: output target peripheral TIMER1_ITI2 + \arg TRIGSEL_OUTPUT_TIMER1_ITI3: output target peripheral TIMER1_ITI3 + \arg TRIGSEL_OUTPUT_MFCOM_TRG_TIMER0 output target peripheral MFCOM_TRG_TIMER0 + \arg TRIGSEL_OUTPUT_MFCOM_TRG_TIMER1 output target peripheral MFCOM_TRG_TIMER1 + \arg TRIGSEL_OUTPUT_MFCOM_TRG_TIMER2 output target peripheral MFCOM_TRG_TIMER2 + \arg TRIGSEL_OUTPUT_MFCOM_TRG_TIMER3 output target peripheral MFCOM_TRG_TIMER3 + \arg TRIGSEL_OUTPUT_CAN0_EX_TIME_TICK output target peripheral CAN0_EX_TIME_TICK + \arg TRIGSEL_OUTPUT_CAN1_EX_TIME_TICK output target peripheral CAN1_EX_TIME_TICK + \param[out] none + \retval trigger_source: trigger source value(0~67) +*/ +uint8_t trigsel_trigger_source_get(trigsel_periph_enum target_periph) +{ + uint8_t trigger_source; + + trigger_source = (uint8_t)((TRIGSEL_TARGET_REG(target_periph) & TRIGSEL_TARGET_PERIPH_MASK(target_periph)) >> TRIGSEL_TARGET_PERIPH_SHIFT(target_periph)); + + return trigger_source; +} + +/*! + \brief lock the trigger register + \param[in] target_periph: target peripheral value + only one parameter can be selected which is shown as below: + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT0: output target peripheral TRIGSEL_OUT0 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT1: output target peripheral TRIGSEL_OUT1 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT2: output target peripheral TRIGSEL_OUT2 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT3: output target peripheral TRIGSEL_OUT3 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT4: output target peripheral TRIGSEL_OUT4 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT5: output target peripheral TRIGSEL_OUT5 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT6: output target peripheral TRIGSEL_OUT6 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT7: output target peripheral TRIGSEL_OUT7 pin + \arg TRIGSEL_OUTPUT_ADC0_RTTRG: output target peripheral ADC0_RTTRG + \arg TRIGSEL_OUTPUT_ADC1_RTTRG: output target peripheral ADC1_RTTRG + \arg TRIGSEL_OUTPUT_DAC_EXTRIG: output target peripheral DAC_EXTRIG + \arg TRIGSEL_OUTPUT_TIMER0_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER0_ITI1: output target peripheral TIMER0_ITI1 + \arg TRIGSEL_OUTPUT_TIMER0_ITI2: output target peripheral TIMER0_ITI2 + \arg TRIGSEL_OUTPUT_TIMER0_ITI3: output target peripheral TIMER0_ITI3 + \arg TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN0 + \arg TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN1 + \arg TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN2 + \arg TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN3 + \arg TRIGSEL_OUTPUT_TIMER7_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER7_ITI1: output target peripheral TIMER0_ITI1 + \arg TRIGSEL_OUTPUT_TIMER7_ITI2: output target peripheral TIMER0_ITI2 + \arg TRIGSEL_OUTPUT_TIMER7_ITI3: output target peripheral TIMER0_ITI3 + \arg TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN0 + \arg TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN1 + \arg TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN2 + \arg TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN3 + \arg TRIGSEL_OUTPUT_TIMER1_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER1_ITI1: output target peripheral TIMER0_ITI1 + \arg TRIGSEL_OUTPUT_TIMER1_ITI2: output target peripheral TIMER0_ITI2 + \arg TRIGSEL_OUTPUT_TIMER1_ITI3: output target peripheral TIMER0_ITI3 + \arg TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN0 + \arg TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN1 + \arg TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN2 + \arg TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN3 + \arg TRIGSEL_OUTPUT_TIMER20_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER20_ITI1: output target peripheral TIMER0_ITI1 + \arg TRIGSEL_OUTPUT_TIMER20_ITI2: output target peripheral TIMER0_ITI2 + \arg TRIGSEL_OUTPUT_TIMER20_ITI3: output target peripheral TIMER0_ITI3 + \arg TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN0 + \arg TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN1 + \arg TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN2 + \arg TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN3 + \arg TRIGSEL_OUTPUT_TIMER1_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER1_ITI1: output target peripheral TIMER1_ITI1 + \arg TRIGSEL_OUTPUT_TIMER1_ITI2: output target peripheral TIMER1_ITI2 + \arg TRIGSEL_OUTPUT_TIMER1_ITI3: output target peripheral TIMER1_ITI3 + \arg TRIGSEL_OUTPUT_MFCOM_TRG_TIMER0 output target peripheral MFCOM_TRG_TIMER0 + \arg TRIGSEL_OUTPUT_MFCOM_TRG_TIMER1 output target peripheral MFCOM_TRG_TIMER1 + \arg TRIGSEL_OUTPUT_MFCOM_TRG_TIMER2 output target peripheral MFCOM_TRG_TIMER2 + \arg TRIGSEL_OUTPUT_MFCOM_TRG_TIMER3 output target peripheral MFCOM_TRG_TIMER3 + \arg TRIGSEL_OUTPUT_CAN0_EX_TIME_TICK output target peripheral CAN0_EX_TIME_TICK + \arg TRIGSEL_OUTPUT_CAN1_EX_TIME_TICK output target peripheral CAN1_EX_TIME_TICK + \param[out] none + \retval none +*/ +void trigsel_register_lock_set(trigsel_periph_enum target_periph) +{ + /*!< lock target peripheral register */ + TRIGSEL_TARGET_REG(target_periph) |= TRIGSEL_TARGET_LK; +} + +/*! + \brief get the trigger register lock status + \param[in] target_periph: target peripheral value + only one parameter can be selected which is shown as below: + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT0: output target peripheral TRIGSEL_OUT0 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT1: output target peripheral TRIGSEL_OUT1 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT2: output target peripheral TRIGSEL_OUT2 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT3: output target peripheral TRIGSEL_OUT3 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT4: output target peripheral TRIGSEL_OUT4 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT5: output target peripheral TRIGSEL_OUT5 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT6: output target peripheral TRIGSEL_OUT6 pin + \arg TRIGSEL_OUTPUT_TRIGSEL_OUT7: output target peripheral TRIGSEL_OUT7 pin + \arg TRIGSEL_OUTPUT_ADC0_RTTRG: output target peripheral ADC0_RTTRG + \arg TRIGSEL_OUTPUT_ADC1_RTTRG: output target peripheral ADC1_RTTRG + \arg TRIGSEL_OUTPUT_DAC_EXTRIG: output target peripheral DAC_EXTRIG + \arg TRIGSEL_OUTPUT_TIMER0_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER0_ITI1: output target peripheral TIMER0_ITI1 + \arg TRIGSEL_OUTPUT_TIMER0_ITI2: output target peripheral TIMER0_ITI2 + \arg TRIGSEL_OUTPUT_TIMER0_ITI3: output target peripheral TIMER0_ITI3 + \arg TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN0 + \arg TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN1 + \arg TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN2 + \arg TRIGSEL_OUTPUT_TIMER0_BRKIN0: output target peripheral TIMER0_BRKIN3 + \arg TRIGSEL_OUTPUT_TIMER7_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER7_ITI1: output target peripheral TIMER0_ITI1 + \arg TRIGSEL_OUTPUT_TIMER7_ITI2: output target peripheral TIMER0_ITI2 + \arg TRIGSEL_OUTPUT_TIMER7_ITI3: output target peripheral TIMER0_ITI3 + \arg TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN0 + \arg TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN1 + \arg TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN2 + \arg TRIGSEL_OUTPUT_TIMER7_BRKIN0: output target peripheral TIMER0_BRKIN3 + \arg TRIGSEL_OUTPUT_TIMER1_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER1_ITI1: output target peripheral TIMER0_ITI1 + \arg TRIGSEL_OUTPUT_TIMER1_ITI2: output target peripheral TIMER0_ITI2 + \arg TRIGSEL_OUTPUT_TIMER1_ITI3: output target peripheral TIMER0_ITI3 + \arg TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN0 + \arg TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN1 + \arg TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN2 + \arg TRIGSEL_OUTPUT_TIMER19_BRKIN0: output target peripheral TIMER0_BRKIN3 + \arg TRIGSEL_OUTPUT_TIMER20_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER20_ITI1: output target peripheral TIMER0_ITI1 + \arg TRIGSEL_OUTPUT_TIMER20_ITI2: output target peripheral TIMER0_ITI2 + \arg TRIGSEL_OUTPUT_TIMER20_ITI3: output target peripheral TIMER0_ITI3 + \arg TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN0 + \arg TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN1 + \arg TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN2 + \arg TRIGSEL_OUTPUT_TIMER20_BRKIN0: output target peripheral TIMER0_BRKIN3 + \arg TRIGSEL_OUTPUT_TIMER1_ITI0: output target peripheral TIMER0_ITI0 + \arg TRIGSEL_OUTPUT_TIMER1_ITI1: output target peripheral TIMER1_ITI1 + \arg TRIGSEL_OUTPUT_TIMER1_ITI2: output target peripheral TIMER1_ITI2 + \arg TRIGSEL_OUTPUT_TIMER1_ITI3: output target peripheral TIMER1_ITI3 + \arg TRIGSEL_OUTPUT_MFCOM_TRG_TIMER0 output target peripheral MFCOM_TRG_TIMER0 + \arg TRIGSEL_OUTPUT_MFCOM_TRG_TIMER1 output target peripheral MFCOM_TRG_TIMER1 + \arg TRIGSEL_OUTPUT_MFCOM_TRG_TIMER2 output target peripheral MFCOM_TRG_TIMER2 + \arg TRIGSEL_OUTPUT_MFCOM_TRG_TIMER3 output target peripheral MFCOM_TRG_TIMER3 + \arg TRIGSEL_OUTPUT_CAN0_EX_TIME_TICK output target peripheral CAN0_EX_TIME_TICK + \arg TRIGSEL_OUTPUT_CAN1_EX_TIME_TICK output target peripheral CAN1_EX_TIME_TICK + \param[out] none + \retval SET or RESET +*/ +FlagStatus trigsel_register_lock_get(trigsel_periph_enum target_periph) +{ + if(0U != (TRIGSEL_TARGET_REG(target_periph) & TRIGSEL_TARGET_LK)){ + return SET; + }else{ + return RESET; + } +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_usart.c b/gd32a50x/standard_peripheral/source/gd32a50x_usart.c new file mode 100644 index 0000000..69c4f15 --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_usart.c @@ -0,0 +1,1291 @@ +/*! + \file gd32a50x_usart.c + \brief USART driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#include "gd32a50x_usart.h" + +/*! + \brief reset USART + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_deinit(uint32_t usart_periph) +{ + switch(usart_periph){ + case USART0: + /* reset USART0 */ + rcu_periph_reset_enable(RCU_USART0RST); + rcu_periph_reset_disable(RCU_USART0RST); + break; + case USART1: + /* reset USART1 */ + rcu_periph_reset_enable(RCU_USART1RST); + rcu_periph_reset_disable(RCU_USART1RST); + break; + case USART2: + /* reset USART2 */ + rcu_periph_reset_enable(RCU_USART2RST); + rcu_periph_reset_disable(RCU_USART2RST); + break; + default: + break; + } +} + +/*! + \brief configure USART baud rate value + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] baudval: baud rate value + \param[out] none + \retval none +*/ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) +{ + uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U; + switch(usart_periph){ + /* get clock frequency */ + case USART0: + /* get USART0 clock */ + uclk = rcu_clock_freq_get(CK_USART0); + break; + case USART1: + /* get USART1 clock */ + uclk = rcu_clock_freq_get(CK_USART1); + break; + case USART2: + /* get USART2 clock */ + uclk = rcu_clock_freq_get(CK_USART2); + break; + default: + break; + } + if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD){ + /* oversampling by 8, configure the value of USART_BAUD */ + udiv = ((2U * uclk) + (baudval / 2U)) / baudval; + intdiv = udiv & 0x0000fff0U; + fradiv = (udiv >> 1U) & 0x00000007U; + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); + }else{ + /* oversampling by 16, configure the value of USART_BAUD */ + udiv = (uclk + (baudval / 2U)) / baudval; + intdiv = udiv & 0x0000fff0U; + fradiv = udiv & 0x0000000fU; + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); + } +} + +/*! + \brief configure USART parity + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] paritycfg: USART parity configure + only one parameter can be selected which is shown as below: + \arg USART_PM_NONE: no parity + \arg USART_PM_ODD: odd parity + \arg USART_PM_EVEN: even parity + \param[out] none + \retval none +*/ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* clear USART_CTL0 PM,PCEN bits */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); + /* configure USART parity mode */ + USART_CTL0(usart_periph) |= paritycfg; +} + +/*! + \brief configure USART word length + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] wlen: USART word length configure + only one parameter can be selected which is shown as below: + \arg USART_WL_8BIT: 8 bits + \arg USART_WL_9BIT: 9 bits + \param[out] none + \retval none +*/ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* clear USART_CTL0 WL bit */ + USART_CTL0(usart_periph) &= ~USART_CTL0_WL; + /* configure USART word length */ + USART_CTL0(usart_periph) |= wlen; +} + +/*! + \brief configure USART stop bit length + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] stblen: USART stop bit configure + only one parameter can be selected which is shown as below: + \arg USART_STB_1BIT: 1 bit + \arg USART_STB_0_5BIT: 0.5bit + \arg USART_STB_2BIT: 2 bits + \arg USART_STB_1_5BIT: 1.5bit + \param[out] none + \retval none +*/ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* clear USART_CTL1 STB bits */ + USART_CTL1(usart_periph) &= ~USART_CTL1_STB; + USART_CTL1(usart_periph) |= stblen; +} + +/*! + \brief enable USART + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_UEN; +} + +/*! + \brief disable USART + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); +} + +/*! + \brief configure USART transmitter + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] txconfig: enable or disable USART transmitter + only one parameter can be selected which is shown as below: + \arg USART_TRANSMIT_ENABLE: enable USART transmission + \arg USART_TRANSMIT_DISABLE: enable USART transmission + \param[out] none + \retval none +*/ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) +{ + USART_CTL0(usart_periph) &= ~USART_CTL0_TEN; + /* configure transfer mode */ + USART_CTL0(usart_periph) |= txconfig; +} + +/*! + \brief configure USART receiver + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] rxconfig: enable or disable USART receiver + only one parameter can be selected which is shown as below: + \arg USART_RECEIVE_ENABLE: enable USART reception + \arg USART_RECEIVE_DISABLE: disable USART reception + \param[out] none + \retval none +*/ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) +{ + USART_CTL0(usart_periph) &= ~USART_CTL0_REN; + /* configure receiver mode */ + USART_CTL0(usart_periph) |= rxconfig; +} + +/*! + \brief data is transmitted/received with the LSB/MSB first + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] msbf: LSB/MSB + only one parameter can be selected which is shown as below: + \arg USART_MSBF_LSB: LSB first + \arg USART_MSBF_MSB: MSB first + \param[out] none + \retval none +*/ +void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* configure LSB or MSB first */ + USART_CTL1(usart_periph) &= ~(USART_CTL1_MSBF); + USART_CTL1(usart_periph) |= msbf; +} + +/*! + \brief configure USART inverted + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] invertpara: refer to usart_invert_enum + only one parameter can be selected which is shown as below: + \arg USART_DINV_ENABLE: data bit level inversion + \arg USART_DINV_DISABLE: data bit level not inversion + \arg USART_TXPIN_ENABLE: TX pin level inversion + \arg USART_TXPIN_DISABLE: TX pin level not inversion + \arg USART_RXPIN_ENABLE: RX pin level inversion + \arg USART_RXPIN_DISABLE: RX pin level not inversion + \arg USART_SWAP_ENABLE: swap TX/RX pins + \arg USART_SWAP_DISABLE: not swap TX/RX pins + \param[out] none + \retval none +*/ +void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* inverted or not the specified signal */ + switch(invertpara){ + case USART_DINV_ENABLE: + USART_CTL1(usart_periph) |= USART_CTL1_DINV; + break; + case USART_DINV_DISABLE: + USART_CTL1(usart_periph) &= ~(USART_CTL1_DINV); + break; + case USART_TXPIN_ENABLE: + USART_CTL1(usart_periph) |= USART_CTL1_TINV; + break; + case USART_TXPIN_DISABLE: + USART_CTL1(usart_periph) &= ~(USART_CTL1_TINV); + break; + case USART_RXPIN_ENABLE: + USART_CTL1(usart_periph) |= USART_CTL1_RINV; + break; + case USART_RXPIN_DISABLE: + USART_CTL1(usart_periph) &= ~(USART_CTL1_RINV); + break; + case USART_SWAP_ENABLE: + USART_CTL1(usart_periph) |= USART_CTL1_STRP; + break; + case USART_SWAP_DISABLE: + USART_CTL1(usart_periph) &= ~(USART_CTL1_STRP); + break; + default: + break; + } +} + +/*! + \brief enable the USART overrun function + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_overrun_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* enable overrun function */ + USART_CTL2(usart_periph) &= ~(USART_CTL2_OVRD); +} + +/*! + \brief disable the USART overrun function + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_overrun_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* disable overrun function */ + USART_CTL2(usart_periph) |= USART_CTL2_OVRD; +} + +/*! + \brief configure the USART oversample mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] oversamp: oversample value + only one parameter can be selected which is shown as below: + \arg USART_OVSMOD_8: oversampling by 8 + \arg USART_OVSMOD_16: oversampling by 16 + \param[out] none + \retval none +*/ +void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* clear OVSMOD bit */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_OVSMOD); + USART_CTL0(usart_periph) |= oversamp; +} + +/*! + \brief configure the sample bit method + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] osb: sample bit + only one parameter can be selected which is shown as below: + \arg USART_OSB_1BIT: 1 bit + \arg USART_OSB_3BIT: 3 bits + \param[out] none + \retval none +*/ +void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB); + USART_CTL2(usart_periph) |= osb; +} + +/*! + \brief enable receiver timeout + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_receiver_timeout_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_RTEN; +} + +/*! + \brief disable receiver timeout + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_receiver_timeout_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_RTEN); +} + +/*! + \brief configure receiver timeout threshold + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] rtimeout: 0x00000000-0x00FFFFFF, receiver timeout value in terms of number of baud clocks + \param[out] none + \retval none +*/ +void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout) +{ + USART_RT(usart_periph) &= ~(USART_RT_RT); + USART_RT(usart_periph) |= rtimeout; +} + +/*! + \brief USART transmit data function + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void usart_data_transmit(uint32_t usart_periph, uint16_t data) +{ + USART_TDATA(usart_periph) = (USART_TDATA_TDATA & (uint32_t)data); +} + +/*! + \brief USART receive data function + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval data of received +*/ +uint16_t usart_data_receive(uint32_t usart_periph) +{ + return (uint16_t)(GET_BITS(USART_RDATA(usart_periph), 0U, 8U)); +} + +/*! + \brief enable USART command + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] cmdtype: command type + only one parameter can be selected which is shown as below: + \arg USART_CMD_SBKCMD: send break command + \arg USART_CMD_MMCMD: mute mode command + \arg USART_CMD_RXFCMD: receive data flush command + \arg USART_CMD_TXFCMD: transmit data flush request + \param[out] none + \retval none +*/ +void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype) +{ + USART_CMD(usart_periph) |= (cmdtype); +} + +/*! + \brief address of the USART terminal + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] addr: 0x00-0xFF, address of USART terminal + \param[out] none + \retval none +*/ +void usart_address_config(uint32_t usart_periph, uint8_t addr) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR_DATA); + USART_CTL1(usart_periph) |= (USART_CTL1_ADDR_DATA & (((uint32_t)addr) << 24)); +} + +/*! + \brief configure address detection mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] addmod: address detection mode + only one parameter can be selected which is shown as below: + \arg USART_ADDM_4BIT: 4 bits + \arg USART_ADDM_FULLBIT: full bits + \param[out] none + \retval none +*/ +void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDM); + USART_CTL1(usart_periph) |= USART_CTL1_ADDM & (addmod); +} + +/*! + \brief enable mute mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_mute_mode_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_MEN; +} + +/*! + \brief disable mute mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_mute_mode_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_MEN); +} + +/*! + \brief configure wakeup method in mute mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] wmethod: two methods be used to enter or exit the mute mode + only one parameter can be selected which is shown as below: + \arg USART_WM_IDLE: idle line + \arg USART_WM_ADDR: address match + \arg USART_WM_DATA: data match + \param[out] none + \retval none +*/ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL0(usart_periph) &= ~(USART_CTL0_WM0 | USART_CTL0_WM1); + USART_CTL0(usart_periph) |= wmethod; +} + +/*! + \brief enable LIN mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_lin_mode_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) |= USART_CTL1_LMEN; +} + +/*! + \brief disable LIN mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_lin_mode_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); +} + +/*! + \brief LIN break detection length + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] lblen: LIN break detection length + only one parameter can be selected which is shown as below: + \arg USART_LBLEN_10B: 10 bits break detection + \arg USART_LBLEN_11B: 11 bits break detection + \param[out] none + \retval none +*/ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); + USART_CTL1(usart_periph) |= USART_CTL1_LBLEN & (lblen); +} + +/*! + \brief enable half-duplex mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_halfduplex_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_HDEN; +} + +/*! + \brief disable half-duplex mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_halfduplex_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); +} + +/*! + \brief enable clock + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_clock_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) |= USART_CTL1_CKEN; +} + +/*! + \brief disable clock + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_clock_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); +} + +/*! + \brief configure USART synchronous mode parameters + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] clen: last bit clock pulse + only one parameter can be selected which is shown as below: + \arg USART_CLEN_NONE: clock pulse of the last data bit (MSB) is not output to the CK pin + \arg USART_CLEN_EN: clock pulse of the last data bit (MSB) is output to the CK pin + \param[in] cph: clock phase + only one parameter can be selected which is shown as below: + \arg USART_CPH_1CK: first clock transition is the first data capture edge + \arg USART_CPH_2CK: second clock transition is the first data capture edge + \param[in] cpl: clock polarity + only one parameter can be selected which is shown as below: + \arg USART_CPL_LOW: steady low value on CK pin + \arg USART_CPL_HIGH: steady high value on CK pin + \param[out] none + \retval none +*/ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* reset USART_CTL1 CLEN,CPH,CPL bits */ + USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); + + USART_CTL1(usart_periph) |= (USART_CTL1_CLEN & clen); + USART_CTL1(usart_periph) |= (USART_CTL1_CPH & cph); + USART_CTL1(usart_periph) |= (USART_CTL1_CPL & cpl); +} + +/*! + \brief configure guard time value in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] guat: 0x00-0xFF + \param[out] none + \retval none +*/ +void usart_guard_time_config(uint32_t usart_periph, uint32_t guat) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_GP(usart_periph) &= ~(USART_GP_GUAT); + USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << 8)); +} + +/*! + \brief enable smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_SCEN; +} + +/*! + \brief disable smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); +} + +/*! + \brief enable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_NKEN; +} + +/*! + \brief disable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); +} + +/*! + \brief enable early NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph) +{ + USART_RFCS(usart_periph) |= USART_RFCS_ELNACK; +} + +/*! + \brief disable early NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph) +{ + USART_RFCS(usart_periph) &= ~USART_RFCS_ELNACK; +} + +/*! + \brief configure smartcard auto-retry number + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] scrtnum: 0x00000000-0x00000007, smartcard auto-retry number + \param[out] none + \retval none +*/ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + USART_CTL2(usart_periph) &= ~(USART_CTL2_SCRTNUM); + USART_CTL2(usart_periph) |= (USART_CTL2_SCRTNUM & (scrtnum << 17)); +} + +/*! + \brief configure block length + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] bl: 0x00000000-0x000000FF + \param[out] none + \retval none +*/ +void usart_block_length_config(uint32_t usart_periph, uint32_t bl) +{ + USART_RT(usart_periph) &= ~(USART_RT_BL); + USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << 24)); +} + +/*! + \brief enable IrDA mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_irda_mode_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_IREN; +} + +/*! + \brief disable IrDA mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_irda_mode_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); +} + +/*! + \brief configure the peripheral clock prescaler in USART IrDA low-power or smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] psc: 0x00000000-0x000000FF + \param[out] none + \retval none +*/ +void usart_prescaler_config(uint32_t usart_periph, uint32_t psc) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + USART_GP(usart_periph) &= ~(USART_GP_PSC); + USART_GP(usart_periph) |= psc; +} + +/*! + \brief configure IrDA low-power + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] irlp: IrDA low-power or normal + only one parameter can be selected which is shown as below: + \arg USART_IRLP_LOW: low-power + \arg USART_IRLP_NORMAL: normal + \param[out] none + \retval none +*/ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); + USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); +} + +/*! + \brief configure hardware flow control RTS + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] rtsconfig: enable or disable RTS + only one parameter can be selected which is shown as below: + \arg USART_RTS_ENABLE: enable RTS + \arg USART_RTS_DISABLE: disable RTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN); + USART_CTL2(usart_periph) |= rtsconfig; +} + +/*! + \brief configure hardware flow control CTS + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] ctsconfig: enable or disable CTS + only one parameter can be selected which is shown as below: + \arg USART_CTS_ENABLE: enable CTS + \arg USART_CTS_DISABLE: disable CTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_CTSEN); + USART_CTL2(usart_periph) |= ctsconfig; +} + + /*! + \brief configure hardware flow control coherence mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] hcm: + only one parameter can be selected which is shown as below: + \arg USART_HCM_NONE: nRTS signal equals to the rbne status register + \arg USART_HCM_EN: nRTS signal is set when the last data bit has been sampled + \param[out] none + \retval none +*/ +void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm) +{ + USART_CHC(usart_periph) &= ~(USART_CHC_HCM); + USART_CHC(usart_periph) |= hcm; +} + +/*! + \brief enable RS485 driver + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_rs485_driver_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_DEM; +} + +/*! + \brief disable RS485 driver + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_rs485_driver_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_DEM); +} + +/*! + \brief configure driver enable assertion time + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] deatime: 0x00000000-0x0000001F + \param[out] none + \retval none +*/ +void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL0(usart_periph) &= ~(USART_CTL0_DEA); + USART_CTL0(usart_periph) |= (USART_CTL0_DEA & ((deatime) << 21)); +} + +/*! + \brief configure driver enable de-assertion time + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] dedtime: 0x00000000-0x0000001F + \param[out] none + \retval none +*/ +void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL0(usart_periph) &= ~(USART_CTL0_DED); + USART_CTL0(usart_periph) |= (USART_CTL0_DED & ((dedtime) << 16)); +} + +/*! + \brief configure driver enable polarity mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] dep: DE signal + only one parameter can be selected which is shown as below: + \arg USART_DEP_HIGH: DE signal is active high + \arg USART_DEP_LOW: DE signal is active low + \param[out] none + \retval none +*/ +void usart_depolarity_config(uint32_t usart_periph, uint32_t dep) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* reset DEP bit */ + USART_CTL2(usart_periph) &= ~(USART_CTL2_DEP); + USART_CTL2(usart_periph) |= (USART_CTL2_DEP & dep); +} + +/*! + \brief configure USART DMA reception + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] dmaconfig: USART DMA mode + only one parameter can be selected which is shown as below: + \arg USART_RECEIVE_DMA_ENABLE: enable USART DMA for reception + \arg USART_RECEIVE_DMA_DISABLE: disable USART DMA for reception + \param[out] none + \retval none +*/ +void usart_dma_receive_config(uint32_t usart_periph, uint8_t dmaconfig) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_DENR); + USART_CTL2(usart_periph) |= (USART_CTL2_DENR & dmaconfig); +} + +/*! + \brief configure USART DMA transmission + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] dmaconfig: USART DMA mode + only one parameter can be selected which is shown as below: + \arg USART_TRANSMIT_DMA_ENABLE: enable USART DMA for transmission + \arg USART_TRANSMIT_DMA_DISABLE: disable USART DMA for transmission + \param[out] none + \retval none +*/ +void usart_dma_transmit_config(uint32_t usart_periph, uint8_t dmaconfig) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_DENT); + USART_CTL2(usart_periph) |= (USART_CTL2_DENT & dmaconfig); +} + +/*! + \brief disable DMA on reception error + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_reception_error_dma_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_DDRE; +} + +/*! + \brief enable DMA on reception error + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_reception_error_dma_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_DDRE); +} + +/*! + \brief enable USART to wakeup the MCU from deep-sleep mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_wakeup_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_UESM; +} + +/*! + \brief disable USART to wakeup the MCU from deep-sleep mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_wakeup_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UESM); +} + +/*! + \brief configure the USART wakeup mode from deep-sleep mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] wum: wakeup mode + only one parameter can be selected which is shown as below: + \arg USART_WUM_ADDR: WUF active on address match + \arg USART_WUM_STARTB: WUF active on start bit + \arg USART_WUM_RBNE: WUF active on RBNE + \param[out] none + \retval none +*/ +void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* reset WUM bit */ + USART_CTL2(usart_periph) &= ~(USART_CTL2_WUM); + USART_CTL2(usart_periph) |= USART_CTL2_WUM & (wum); +} + +/*! + \brief enable receive FIFO + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_receive_fifo_enable(uint32_t usart_periph) +{ + USART_RFCS(usart_periph) |= USART_RFCS_RFEN; +} + +/*! + \brief disable receive FIFO + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_receive_fifo_disable(uint32_t usart_periph) +{ + USART_RFCS(usart_periph) &= ~(USART_RFCS_RFEN); +} + +/*! + \brief read receive FIFO counter number + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval receive FIFO counter number +*/ +uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph) +{ + return (uint8_t)(GET_BITS(USART_RFCS(usart_periph), 12U, 14U)); +} + +/*! + \brief get USART status + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] flag: flag type + only one parameter can be selected which is shown as below: + \arg USART_FLAG_REA: receive enable acknowledge flag + \arg USART_FLAG_TEA: transmit enable acknowledge flag + \arg USART_FLAG_WU: wakeup from deep-sleep mode flag + \arg USART_FLAG_RWU: receiver wakeup from mute mode + \arg USART_FLAG_SB: send break flag + \arg USART_FLAG_AM: address match flag + \arg USART_FLAG_BSY: busy flag + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_RT: receiver timeout flag + \arg USART_FLAG_CTS: CTS level + \arg USART_FLAG_CTSF: CTS change flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_TBE: transmit data register empty + \arg USART_FLAG_TC: transmission completed + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_IDLE: idle line detected flag + \arg USART_FLAG_ORERR: overrun error + \arg USART_FLAG_NERR: noise error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_PERR: parity error flag + \arg USART_FLAG_EPERR: early parity error flag + \arg USART_FLAG_RFFINT: receive FIFO full interrupt flag + \arg USART_FLAG_RFF: receive FIFO full flag + \arg USART_FLAG_RFE: receive FIFO empty flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) +{ + if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear USART status + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] flag: flag type + only one parameter can be selected which is shown as below: + \arg USART_FLAG_WU: wakeup from deep-sleep mode flag + \arg USART_FLAG_AM: address match flag + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_RT: receiver timeout flag + \arg USART_FLAG_CTSF: CTS change flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_TC: transmission complete flag + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_IDLE: idle line detected flag + \arg USART_FLAG_ORERR: overrun error flag + \arg USART_FLAG_NERR: noise detected flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_PERR: parity error flag + \arg USART_FLAG_EPERR: early parity error flag + \param[out] none + \retval none +*/ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) +{ + if(flag == USART_FLAG_RBNE){ + USART_CMD(usart_periph) |= USART_CMD_RXFCMD; + }else if(flag == USART_FLAG_EPERR){ + USART_CHC(usart_periph) &= ~USART_CHC_EPERR; + }else{ + USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag)); + } + +} + +/*! + \brief enable USART interrupt + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] interrupt: interrupt type + only one parameter can be selected which is shown as below: + \arg USART_INT_EB: end of block interrupt + \arg USART_INT_RT: receiver timeout interrupt + \arg USART_INT_AM: address match interrupt + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmit data register empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and + overrun error interrupt enable interrupt + \arg USART_INT_IDLE: idle interrupt + \arg USART_INT_LBD: LIN break detection interrupt + \arg USART_INT_WU: wakeup from deep-sleep mode interrupt + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_ERR: error interrupt enable in multibuffer communication + \arg USART_INT_RFF: receive FIFO full interrupt enable + \param[out] none + \retval none +*/ +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt) +{ + USART_REG_VAL(usart_periph, interrupt) |= BIT(USART_BIT_POS(interrupt)); +} + +/*! + \brief disable USART interrupt + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] interrupt: interrupt type + only one parameter can be selected which is shown as below: + \arg USART_INT_EB: end of block interrupt + \arg USART_INT_RT: receiver timeout interrupt + \arg USART_INT_AM: address match interrupt + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmit data register empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and + overrun error interrupt enable interrupt + \arg USART_INT_IDLE: idle interrupt + \arg USART_INT_LBD: LIN break detection interrupt + \arg USART_INT_WU: wakeup from deep-sleep mode interrupt + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_ERR: error interrupt enable in multibuffer communication + \arg USART_INT_RFF: receive FIFO full interrupt enable + \param[out] none + \retval none +*/ +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt) +{ + USART_REG_VAL(usart_periph, interrupt) &= ~BIT(USART_BIT_POS(interrupt)); +} + +/*! + \brief get USART interrupt and flag status + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] int_flag: interrupt and flag type, refer to usart_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_EB: end of block interrupt and flag + \arg USART_INT_FLAG_RT: receiver timeout interrupt and flag + \arg USART_INT_FLAG_AM: address match interrupt and flag + \arg USART_INT_FLAG_PERR: parity error interrupt and flag + \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag + \arg USART_INT_FLAG_TC: transmission complete interrupt and flag + \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag + \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag + \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag + \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag + \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode interrupt and flag + \arg USART_INT_FLAG_CTS: CTS interrupt and flag + \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag + \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error + \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag + \arg USART_INT_FLAG_RFF: receive FIFO full interrupt and flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U; + /* get the interrupt enable bit status */ + intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); + + if(flagstatus && intenable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear USART interrupt flag + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] int_flag: USART interrupt flag + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_EB: end of block flag + \arg USART_INT_FLAG_RT: receiver timeout flag + \arg USART_INT_FLAG_AM: address match flag + \arg USART_INT_FLAG_PERR: parity error flag + \arg USART_INT_FLAG_TC: transmission complete flag + \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag + \arg USART_INT_FLAG_IDLE: idle line detected flag + \arg USART_INT_FLAG_LBD: LIN break detected flag + \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode flag + \arg USART_INT_FLAG_CTS: CTS change flag + \arg USART_INT_FLAG_ERR_NERR: noise detected flag + \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error + \arg USART_INT_FLAG_ERR_FERR: frame error flag + \arg USART_INT_FLAG_RFF: receive FIFO full interrupt and flag + \param[out] none + \retval none +*/ +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) +{ + if(USART_INT_FLAG_RFF == int_flag){ + USART_RFCS(usart_periph) &= (uint32_t)(~USART_RFCS_RFFINT); + }else{ + USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(int_flag)); + } +} diff --git a/gd32a50x/standard_peripheral/source/gd32a50x_wwdgt.c b/gd32a50x/standard_peripheral/source/gd32a50x_wwdgt.c new file mode 100644 index 0000000..10cf040 --- /dev/null +++ b/gd32a50x/standard_peripheral/source/gd32a50x_wwdgt.c @@ -0,0 +1,125 @@ +/*! + \file gd32fxxx_wwdgt.c + \brief WWDGT driver + + \version 2022-01-30, V1.0.0, firmware for GD32A50x +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32a50x_wwdgt.h" + +/*! + \brief reset the window watchdog timer configuration + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_deinit(void) +{ + rcu_periph_reset_enable(RCU_WWDGTRST); + rcu_periph_reset_disable(RCU_WWDGTRST); +} + +/*! + \brief start the WWDGT counter + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_enable(void) +{ + WWDGT_CTL |= WWDGT_CTL_WDGTEN; +} + +/*! + \brief configure the WWDGT counter value + \param[in] counter_value: 0x40 - 0x7F + \param[out] none + \retval none +*/ +void wwdgt_counter_update(uint16_t counter_value) +{ + WWDGT_CTL = (uint32_t)(CTL_CNT(counter_value)); +} + +/*! + \brief configure counter value, window value, and prescaler divider value + \param[in] counter: 0x40 - 0x7F + \param[in] window: 0x40 - 0x7F + \param[in] prescaler: WWDGT prescaler value + only one parameter can be selected which is shown as below: + \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 + \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 + \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 + \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 + \param[out] none + \retval none +*/ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) +{ + WWDGT_CTL = (uint32_t)(CTL_CNT(counter)); + WWDGT_CFG = (uint32_t)(CFG_WIN(window) | prescaler); +} + +/*! + \brief check early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus wwdgt_flag_get(void) +{ + if (0U != (WWDGT_STAT & WWDGT_STAT_EWIF)){ + return SET; + } + + return RESET; +} + +/*! + \brief clear early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_flag_clear(void) +{ + WWDGT_STAT = (uint32_t)RESET; +} + +/*! + \brief enable early wakeup interrupt of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_interrupt_enable(void) +{ + WWDGT_CFG |= WWDGT_CFG_EWIE; +} diff --git a/gd32a50x/support/GigaDevice.GD32A50x_DFP.1.0.0.pack b/gd32a50x/support/GigaDevice.GD32A50x_DFP.1.0.0.pack new file mode 100644 index 0000000..58f81f6 Binary files /dev/null and b/gd32a50x/support/GigaDevice.GD32A50x_DFP.1.0.0.pack differ diff --git a/include/dt-bindings/pinctrl/gd32a503c(b-c)xx-pinctrl.h b/include/dt-bindings/pinctrl/gd32a503c(b-c)xx-pinctrl.h new file mode 100644 index 0000000..5411015 --- /dev/null +++ b/include/dt-bindings/pinctrl/gd32a503c(b-c)xx-pinctrl.h @@ -0,0 +1,823 @@ +/* + * Autogenerated file + * + * SPDX-License-Identifier: Apache 2.0 + */ + +#include "gd32-af.h" + +/* ADC0_IN0 */ +#define ADC0_IN0_PC11 \ + GD32_PINMUX_AF('C', 11, ANALOG) + +/* ADC0_IN1 */ +#define ADC0_IN1_PC10 \ + GD32_PINMUX_AF('C', 10, ANALOG) + +/* ADC0_IN10 */ +#define ADC0_IN10_PA4 \ + GD32_PINMUX_AF('A', 4, ANALOG) + +/* ADC0_IN11 */ +#define ADC0_IN11_PA3 \ + GD32_PINMUX_AF('A', 3, ANALOG) + +/* ADC0_IN12 */ +#define ADC0_IN12_PE12 \ + GD32_PINMUX_AF('E', 12, ANALOG) + +/* ADC0_IN13 */ +#define ADC0_IN13_PE11 \ + GD32_PINMUX_AF('E', 11, ANALOG) + +/* ADC0_IN14 */ +#define ADC0_IN14_PE10 \ + GD32_PINMUX_AF('E', 10, ANALOG) + +/* ADC0_IN3 */ +#define ADC0_IN3_PD9 \ + GD32_PINMUX_AF('D', 9, ANALOG) + +/* ADC0_IN4 */ +#define ADC0_IN4_PB14 \ + GD32_PINMUX_AF('B', 14, ANALOG) + +/* ADC0_IN5 */ +#define ADC0_IN5_PB13 \ + GD32_PINMUX_AF('B', 13, ANALOG) + +/* ADC0_IN6 */ +#define ADC0_IN6_PE14 \ + GD32_PINMUX_AF('E', 14, ANALOG) + +/* ADC0_IN7 */ +#define ADC0_IN7_PE13 \ + GD32_PINMUX_AF('E', 13, ANALOG) + +/* ADC0_IN8 */ +#define ADC0_IN8_PC7 \ + GD32_PINMUX_AF('C', 7, ANALOG) + +/* ADC0_IN9 */ +#define ADC0_IN9_PB1 \ + GD32_PINMUX_AF('B', 1, ANALOG) + +/* ADC1_IN0 */ +#define ADC1_IN0_PA11 \ + GD32_PINMUX_AF('A', 11, ANALOG) + +/* ADC1_IN1 */ +#define ADC1_IN1_PA10 \ + GD32_PINMUX_AF('A', 10, ANALOG) + +/* ADC1_IN14 */ +#define ADC1_IN14_PB14 \ + GD32_PINMUX_AF('B', 14, ANALOG) + +/* ADC1_IN15 */ +#define ADC1_IN15_PB13 \ + GD32_PINMUX_AF('B', 13, ANALOG) + +/* ADC1_IN2 */ +#define ADC1_IN2_PA9 \ + GD32_PINMUX_AF('A', 9, ANALOG) + +/* ADC1_IN3 */ +#define ADC1_IN3_PA8 \ + GD32_PINMUX_AF('A', 8, ANALOG) + +/* ADC1_IN4 */ +#define ADC1_IN4_PD0 \ + GD32_PINMUX_AF('D', 0, ANALOG) + +/* ADC1_IN5 */ +#define ADC1_IN5_PC12 \ + GD32_PINMUX_AF('C', 12, ANALOG) + +/* ADC1_IN8 */ +#define ADC1_IN8_PC7 \ + GD32_PINMUX_AF('C', 7, ANALOG) + +/* ANALOG */ +#define ANALOG_PA0 \ + GD32_PINMUX_AF('A', 0, ANALOG) +#define ANALOG_PA1 \ + GD32_PINMUX_AF('A', 1, ANALOG) +#define ANALOG_PA2 \ + GD32_PINMUX_AF('A', 2, ANALOG) +#define ANALOG_PA3 \ + GD32_PINMUX_AF('A', 3, ANALOG) +#define ANALOG_PA4 \ + GD32_PINMUX_AF('A', 4, ANALOG) +#define ANALOG_PA5 \ + GD32_PINMUX_AF('A', 5, ANALOG) +#define ANALOG_PA6 \ + GD32_PINMUX_AF('A', 6, ANALOG) +#define ANALOG_PA7 \ + GD32_PINMUX_AF('A', 7, ANALOG) +#define ANALOG_PA8 \ + GD32_PINMUX_AF('A', 8, ANALOG) +#define ANALOG_PA9 \ + GD32_PINMUX_AF('A', 9, ANALOG) +#define ANALOG_PA10 \ + GD32_PINMUX_AF('A', 10, ANALOG) +#define ANALOG_PA11 \ + GD32_PINMUX_AF('A', 11, ANALOG) +#define ANALOG_PB1 \ + GD32_PINMUX_AF('B', 1, ANALOG) +#define ANALOG_PB3 \ + GD32_PINMUX_AF('B', 3, ANALOG) +#define ANALOG_PB4 \ + GD32_PINMUX_AF('B', 4, ANALOG) +#define ANALOG_PB7 \ + GD32_PINMUX_AF('B', 7, ANALOG) +#define ANALOG_PB8 \ + GD32_PINMUX_AF('B', 8, ANALOG) +#define ANALOG_PB9 \ + GD32_PINMUX_AF('B', 9, ANALOG) +#define ANALOG_PB13 \ + GD32_PINMUX_AF('B', 13, ANALOG) +#define ANALOG_PB14 \ + GD32_PINMUX_AF('B', 14, ANALOG) +#define ANALOG_PB15 \ + GD32_PINMUX_AF('B', 15, ANALOG) +#define ANALOG_PC0 \ + GD32_PINMUX_AF('C', 0, ANALOG) +#define ANALOG_PC1 \ + GD32_PINMUX_AF('C', 1, ANALOG) +#define ANALOG_PC7 \ + GD32_PINMUX_AF('C', 7, ANALOG) +#define ANALOG_PC10 \ + GD32_PINMUX_AF('C', 10, ANALOG) +#define ANALOG_PC11 \ + GD32_PINMUX_AF('C', 11, ANALOG) +#define ANALOG_PC12 \ + GD32_PINMUX_AF('C', 12, ANALOG) +#define ANALOG_PC15 \ + GD32_PINMUX_AF('C', 15, ANALOG) +#define ANALOG_PD0 \ + GD32_PINMUX_AF('D', 0, ANALOG) +#define ANALOG_PD6 \ + GD32_PINMUX_AF('D', 6, ANALOG) +#define ANALOG_PD7 \ + GD32_PINMUX_AF('D', 7, ANALOG) +#define ANALOG_PD8 \ + GD32_PINMUX_AF('D', 8, ANALOG) +#define ANALOG_PD9 \ + GD32_PINMUX_AF('D', 9, ANALOG) +#define ANALOG_PE4 \ + GD32_PINMUX_AF('E', 4, ANALOG) +#define ANALOG_PE5 \ + GD32_PINMUX_AF('E', 5, ANALOG) +#define ANALOG_PE10 \ + GD32_PINMUX_AF('E', 10, ANALOG) +#define ANALOG_PE11 \ + GD32_PINMUX_AF('E', 11, ANALOG) +#define ANALOG_PE12 \ + GD32_PINMUX_AF('E', 12, ANALOG) +#define ANALOG_PE13 \ + GD32_PINMUX_AF('E', 13, ANALOG) +#define ANALOG_PE14 \ + GD32_PINMUX_AF('E', 14, ANALOG) +#define ANALOG_PF0 \ + GD32_PINMUX_AF('F', 0, ANALOG) +#define ANALOG_PF5 \ + GD32_PINMUX_AF('F', 5, ANALOG) +#define ANALOG_PF6 \ + GD32_PINMUX_AF('F', 6, ANALOG) +#define ANALOG_PF7 \ + GD32_PINMUX_AF('F', 7, ANALOG) + +/* CAN0_RX */ +#define CAN0_RX_PA4 \ + GD32_PINMUX_AF('A', 4, AF6) +#define CAN0_RX_PB14 \ + GD32_PINMUX_AF('B', 14, AF6) +#define CAN0_RX_PF0 \ + GD32_PINMUX_AF('F', 0, AF6) + +/* CAN0_TX */ +#define CAN0_TX_PA3 \ + GD32_PINMUX_AF('A', 3, AF6) +#define CAN0_TX_PB13 \ + GD32_PINMUX_AF('B', 13, AF6) +#define CAN0_TX_PC15 \ + GD32_PINMUX_AF('C', 15, AF6) + +/* CAN1_RX */ +#define CAN1_RX_PD0 \ + GD32_PINMUX_AF('D', 0, AF6) +#define CAN1_RX_PD7 \ + GD32_PINMUX_AF('D', 7, AF6) + +/* CAN1_TX */ +#define CAN1_TX_PC12 \ + GD32_PINMUX_AF('C', 12, AF6) +#define CAN1_TX_PD6 \ + GD32_PINMUX_AF('D', 6, AF6) + +/* CK_OUT0 */ +#define CK_OUT0_PA1 \ + GD32_PINMUX_AF('A', 1, AF0) + +/* CMP_OUT */ +#define CMP_OUT_PB9 \ + GD32_PINMUX_AF('B', 9, AF7) + +/* DAC_OUT */ +#define DAC_OUT_PA7 \ + GD32_PINMUX_AF('A', 7, ANALOG) + +/* EVENTOUT */ +#define EVENTOUT_PA0 \ + GD32_PINMUX_AF('A', 0, AF9) +#define EVENTOUT_PA1 \ + GD32_PINMUX_AF('A', 1, AF9) +#define EVENTOUT_PA2 \ + GD32_PINMUX_AF('A', 2, AF9) +#define EVENTOUT_PA3 \ + GD32_PINMUX_AF('A', 3, AF9) +#define EVENTOUT_PA4 \ + GD32_PINMUX_AF('A', 4, AF9) +#define EVENTOUT_PA5 \ + GD32_PINMUX_AF('A', 5, AF9) +#define EVENTOUT_PA7 \ + GD32_PINMUX_AF('A', 7, AF9) +#define EVENTOUT_PA8 \ + GD32_PINMUX_AF('A', 8, AF9) +#define EVENTOUT_PA9 \ + GD32_PINMUX_AF('A', 9, AF9) +#define EVENTOUT_PA10 \ + GD32_PINMUX_AF('A', 10, AF9) +#define EVENTOUT_PA11 \ + GD32_PINMUX_AF('A', 11, AF9) +#define EVENTOUT_PB1 \ + GD32_PINMUX_AF('B', 1, AF9) +#define EVENTOUT_PB3 \ + GD32_PINMUX_AF('B', 3, AF9) +#define EVENTOUT_PB4 \ + GD32_PINMUX_AF('B', 4, AF9) +#define EVENTOUT_PB7 \ + GD32_PINMUX_AF('B', 7, AF9) +#define EVENTOUT_PB8 \ + GD32_PINMUX_AF('B', 8, AF9) +#define EVENTOUT_PB9 \ + GD32_PINMUX_AF('B', 9, AF9) +#define EVENTOUT_PB13 \ + GD32_PINMUX_AF('B', 13, AF9) +#define EVENTOUT_PB14 \ + GD32_PINMUX_AF('B', 14, AF9) +#define EVENTOUT_PB15 \ + GD32_PINMUX_AF('B', 15, AF9) +#define EVENTOUT_PC0 \ + GD32_PINMUX_AF('C', 0, AF9) +#define EVENTOUT_PC1 \ + GD32_PINMUX_AF('C', 1, AF9) +#define EVENTOUT_PC7 \ + GD32_PINMUX_AF('C', 7, AF9) +#define EVENTOUT_PC10 \ + GD32_PINMUX_AF('C', 10, AF9) +#define EVENTOUT_PC11 \ + GD32_PINMUX_AF('C', 11, AF9) +#define EVENTOUT_PC12 \ + GD32_PINMUX_AF('C', 12, AF9) +#define EVENTOUT_PC15 \ + GD32_PINMUX_AF('C', 15, AF9) +#define EVENTOUT_PD0 \ + GD32_PINMUX_AF('D', 0, AF9) +#define EVENTOUT_PD6 \ + GD32_PINMUX_AF('D', 6, AF9) +#define EVENTOUT_PD7 \ + GD32_PINMUX_AF('D', 7, AF9) +#define EVENTOUT_PD8 \ + GD32_PINMUX_AF('D', 8, AF9) +#define EVENTOUT_PD9 \ + GD32_PINMUX_AF('D', 9, AF9) +#define EVENTOUT_PE4 \ + GD32_PINMUX_AF('E', 4, AF9) +#define EVENTOUT_PE5 \ + GD32_PINMUX_AF('E', 5, AF9) +#define EVENTOUT_PE10 \ + GD32_PINMUX_AF('E', 10, AF9) +#define EVENTOUT_PE11 \ + GD32_PINMUX_AF('E', 11, AF9) +#define EVENTOUT_PE12 \ + GD32_PINMUX_AF('E', 12, AF9) +#define EVENTOUT_PE13 \ + GD32_PINMUX_AF('E', 13, AF9) +#define EVENTOUT_PE14 \ + GD32_PINMUX_AF('E', 14, AF9) +#define EVENTOUT_PF0 \ + GD32_PINMUX_AF('F', 0, AF9) +#define EVENTOUT_PF5 \ + GD32_PINMUX_AF('F', 5, AF9) +#define EVENTOUT_PF6 \ + GD32_PINMUX_AF('F', 6, AF9) +#define EVENTOUT_PF7 \ + GD32_PINMUX_AF('F', 7, AF9) + +/* I2C0_SCL */ +#define I2C0_SCL_PA10 \ + GD32_PINMUX_AF('A', 10, AF3) +#define I2C0_SCL_PC11 \ + GD32_PINMUX_AF('C', 11, AF3) +#define I2C0_SCL_PF6 \ + GD32_PINMUX_AF('F', 6, AF3) + +/* I2C0_SDA */ +#define I2C0_SDA_PA11 \ + GD32_PINMUX_AF('A', 11, AF3) +#define I2C0_SDA_PC10 \ + GD32_PINMUX_AF('C', 10, AF3) +#define I2C0_SDA_PF7 \ + GD32_PINMUX_AF('F', 7, AF3) + +/* I2C1_SCL */ +#define I2C1_SCL_PB7 \ + GD32_PINMUX_AF('B', 7, AF5) +#define I2C1_SCL_PD6 \ + GD32_PINMUX_AF('D', 6, AF5) +#define I2C1_SCL_PE10 \ + GD32_PINMUX_AF('E', 10, AF5) + +/* I2C1_SDA */ +#define I2C1_SDA_PB8 \ + GD32_PINMUX_AF('B', 8, AF5) +#define I2C1_SDA_PD7 \ + GD32_PINMUX_AF('D', 7, AF5) +#define I2C1_SDA_PE11 \ + GD32_PINMUX_AF('E', 11, AF5) + +/* I2C1_SMBA */ +#define I2C1_SMBA_PB9 \ + GD32_PINMUX_AF('B', 9, AF5) +#define I2C1_SMBA_PE12 \ + GD32_PINMUX_AF('E', 12, AF5) + +/* I2S1_CK */ +#define I2S1_CK_PE5 \ + GD32_PINMUX_AF('E', 5, AF4) + +/* I2S1_MCK */ +#define I2S1_MCK_PC7 \ + GD32_PINMUX_AF('C', 7, AF4) + +/* I2S1_SD */ +#define I2S1_SD_PA9 \ + GD32_PINMUX_AF('A', 9, AF4) + +/* I2S1_WS */ +#define I2S1_WS_PA8 \ + GD32_PINMUX_AF('A', 8, AF4) + +/* JTCK */ +#define JTCK_PB8 \ + GD32_PINMUX_AF('B', 8, AF0) + +/* JTDI */ +#define JTDI_PB7 \ + GD32_PINMUX_AF('B', 7, AF0) + +/* JTDO */ +#define JTDO_PB4 \ + GD32_PINMUX_AF('B', 4, AF0) + +/* JTMS */ +#define JTMS_PB9 \ + GD32_PINMUX_AF('B', 9, AF0) + +/* MFCOM_D0 */ +#define MFCOM_D0_PB4 \ + GD32_PINMUX_AF('B', 4, AF6) +#define MFCOM_D0_PE5 \ + GD32_PINMUX_AF('E', 5, AF6) + +/* MFCOM_D1 */ +#define MFCOM_D1_PB3 \ + GD32_PINMUX_AF('B', 3, AF6) +#define MFCOM_D1_PE4 \ + GD32_PINMUX_AF('E', 4, AF6) + +/* MFCOM_D2 */ +#define MFCOM_D2_PC11 \ + GD32_PINMUX_AF('C', 11, AF6) + +/* MFCOM_D3 */ +#define MFCOM_D3_PC10 \ + GD32_PINMUX_AF('C', 10, AF6) + +/* MFCOM_D4 */ +#define MFCOM_D4_PA9 \ + GD32_PINMUX_AF('A', 9, AF6) +#define MFCOM_D4_PA11 \ + GD32_PINMUX_AF('A', 11, AF6) + +/* MFCOM_D5 */ +#define MFCOM_D5_PA8 \ + GD32_PINMUX_AF('A', 8, AF6) +#define MFCOM_D5_PA10 \ + GD32_PINMUX_AF('A', 10, AF6) + +/* MFCOM_D6 */ +#define MFCOM_D6_PA9 \ + GD32_PINMUX_AF('A', 9, AF5) +#define MFCOM_D6_PF0 \ + GD32_PINMUX_AF('F', 0, AF7) + +/* MFCOM_D7 */ +#define MFCOM_D7_PA8 \ + GD32_PINMUX_AF('A', 8, AF5) +#define MFCOM_D7_PC15 \ + GD32_PINMUX_AF('C', 15, AF7) + +/* NJTRST */ +#define NJTRST_PB3 \ + GD32_PINMUX_AF('B', 3, AF0) + +/* SPI0_IO2 */ +#define SPI0_IO2_PB3 \ + GD32_PINMUX_AF('B', 3, AF4) + +/* SPI0_IO3 */ +#define SPI0_IO3_PB4 \ + GD32_PINMUX_AF('B', 4, AF4) + +/* SPI0_MISO */ +#define SPI0_MISO_PE13 \ + GD32_PINMUX_AF('E', 13, AF4) +#define SPI0_MISO_PF5 \ + GD32_PINMUX_AF('F', 5, AF4) + +/* SPI0_MOSI */ +#define SPI0_MOSI_PA2 \ + GD32_PINMUX_AF('A', 2, AF4) +#define SPI0_MOSI_PB13 \ + GD32_PINMUX_AF('B', 13, AF4) + +/* SPI0_NSS */ +#define SPI0_NSS_PA1 \ + GD32_PINMUX_AF('A', 1, AF4) +#define SPI0_NSS_PB14 \ + GD32_PINMUX_AF('B', 14, AF3) + +/* SPI0_SCK */ +#define SPI0_SCK_PC0 \ + GD32_PINMUX_AF('C', 0, AF4) +#define SPI0_SCK_PE14 \ + GD32_PINMUX_AF('E', 14, AF4) + +/* SPI1_MISO */ +#define SPI1_MISO_PE4 \ + GD32_PINMUX_AF('E', 4, AF4) + +/* SPI1_MOSI */ +#define SPI1_MOSI_PA9 \ + GD32_PINMUX_AF('A', 9, AF4) + +/* SPI1_NSS */ +#define SPI1_NSS_PA8 \ + GD32_PINMUX_AF('A', 8, AF4) + +/* SPI1_SCK */ +#define SPI1_SCK_PE5 \ + GD32_PINMUX_AF('E', 5, AF4) + +/* SWCLK */ +#define SWCLK_PB8 \ + GD32_PINMUX_AF('B', 8, AF0) + +/* SWDIO */ +#define SWDIO_PB9 \ + GD32_PINMUX_AF('B', 9, AF0) + +/* TIMER0_BRKIN0 */ +#define TIMER0_BRKIN0_PA8 \ + GD32_PINMUX_AF('A', 8, AF1) + +/* TIMER0_BRKIN2 */ +#define TIMER0_BRKIN2_PD9 \ + GD32_PINMUX_AF('D', 9, AF2) + +/* TIMER0_CH0 */ +#define TIMER0_CH0_PC0 \ + GD32_PINMUX_AF('C', 0, AF1) + +/* TIMER0_CH1 */ +#define TIMER0_CH1_PA4 \ + GD32_PINMUX_AF('A', 4, AF1) +#define TIMER0_CH1_PE5 \ + GD32_PINMUX_AF('E', 5, AF1) + +/* TIMER0_CH2 */ +#define TIMER0_CH2_PA2 \ + GD32_PINMUX_AF('A', 2, AF1) + +/* TIMER0_CH3 */ +#define TIMER0_CH3_PA0 \ + GD32_PINMUX_AF('A', 0, AF1) + +/* TIMER0_MCH0 */ +#define TIMER0_MCH0_PB1 \ + GD32_PINMUX_AF('B', 1, AF1) +#define TIMER0_MCH0_PC7 \ + GD32_PINMUX_AF('C', 7, AF1) +#define TIMER0_MCH0_PF5 \ + GD32_PINMUX_AF('F', 5, AF1) + +/* TIMER0_MCH1 */ +#define TIMER0_MCH1_PA3 \ + GD32_PINMUX_AF('A', 3, AF1) +#define TIMER0_MCH1_PE4 \ + GD32_PINMUX_AF('E', 4, AF1) + +/* TIMER0_MCH2 */ +#define TIMER0_MCH2_PA1 \ + GD32_PINMUX_AF('A', 1, AF1) + +/* TIMER0_MCH3 */ +#define TIMER0_MCH3_PC1 \ + GD32_PINMUX_AF('C', 1, AF1) + +/* TIMER19_BRKIN1 */ +#define TIMER19_BRKIN1_PA7 \ + GD32_PINMUX_AF('A', 7, AF3) + +/* TIMER19_BRKIN2 */ +#define TIMER19_BRKIN2_PA6 \ + GD32_PINMUX_AF('A', 6, AF2) + +/* TIMER19_BRKIN3 */ +#define TIMER19_BRKIN3_PA5 \ + GD32_PINMUX_AF('A', 5, AF2) + +/* TIMER19_CH0 */ +#define TIMER19_CH0_PB7 \ + GD32_PINMUX_AF('B', 7, AF1) +#define TIMER19_CH0_PC11 \ + GD32_PINMUX_AF('C', 11, AF2) +#define TIMER19_CH0_PD6 \ + GD32_PINMUX_AF('D', 6, AF2) +#define TIMER19_CH0_PE5 \ + GD32_PINMUX_AF('E', 5, AF2) + +/* TIMER19_CH1 */ +#define TIMER19_CH1_PB7 \ + GD32_PINMUX_AF('B', 7, AF2) +#define TIMER19_CH1_PC15 \ + GD32_PINMUX_AF('C', 15, AF2) +#define TIMER19_CH1_PD7 \ + GD32_PINMUX_AF('D', 7, AF2) +#define TIMER19_CH1_PF0 \ + GD32_PINMUX_AF('F', 0, AF1) + +/* TIMER19_MCH0 */ +#define TIMER19_MCH0_PC11 \ + GD32_PINMUX_AF('C', 11, AF1) +#define TIMER19_MCH0_PE4 \ + GD32_PINMUX_AF('E', 4, AF2) + +/* TIMER19_MCH1 */ +#define TIMER19_MCH1_PA7 \ + GD32_PINMUX_AF('A', 7, AF1) +#define TIMER19_MCH1_PC15 \ + GD32_PINMUX_AF('C', 15, AF1) + +/* TIMER1_CH1 */ +#define TIMER1_CH1_PA7 \ + GD32_PINMUX_AF('A', 7, AF2) + +/* TIMER1_CH2 */ +#define TIMER1_CH2_PB14 \ + GD32_PINMUX_AF('B', 14, AF1) + +/* TIMER1_CH3 */ +#define TIMER1_CH3_PA3 \ + GD32_PINMUX_AF('A', 3, AF2) + +/* TIMER20_BRKIN1 */ +#define TIMER20_BRKIN1_PC7 \ + GD32_PINMUX_AF('C', 7, AF2) + +/* TIMER20_CH0 */ +#define TIMER20_CH0_PA11 \ + GD32_PINMUX_AF('A', 11, AF1) + +/* TIMER20_CH1 */ +#define TIMER20_CH1_PD0 \ + GD32_PINMUX_AF('D', 0, AF1) + +/* TIMER20_CH2 */ +#define TIMER20_CH2_PA9 \ + GD32_PINMUX_AF('A', 9, AF1) + +/* TIMER20_MCH0 */ +#define TIMER20_MCH0_PA10 \ + GD32_PINMUX_AF('A', 10, AF1) + +/* TIMER20_MCH1 */ +#define TIMER20_MCH1_PC12 \ + GD32_PINMUX_AF('C', 12, AF1) + +/* TIMER20_MCH2 */ +#define TIMER20_MCH2_PA8 \ + GD32_PINMUX_AF('A', 8, AF2) + +/* TIMER7_BRKIN0 */ +#define TIMER7_BRKIN0_PD8 \ + GD32_PINMUX_AF('D', 8, AF2) + +/* TIMER7_BRKIN1 */ +#define TIMER7_BRKIN1_PB15 \ + GD32_PINMUX_AF('B', 15, AF2) + +/* TIMER7_BRKIN2 */ +#define TIMER7_BRKIN2_PE10 \ + GD32_PINMUX_AF('E', 10, AF2) + +/* TIMER7_CH0 */ +#define TIMER7_CH0_PB8 \ + GD32_PINMUX_AF('B', 8, AF1) +#define TIMER7_CH0_PC10 \ + GD32_PINMUX_AF('C', 10, AF2) +#define TIMER7_CH0_PC12 \ + GD32_PINMUX_AF('C', 12, AF2) +#define TIMER7_CH0_PE13 \ + GD32_PINMUX_AF('E', 13, AF2) +#define TIMER7_CH0_PE14 \ + GD32_PINMUX_AF('E', 14, AF1) + +/* TIMER7_CH1 */ +#define TIMER7_CH1_PB8 \ + GD32_PINMUX_AF('B', 8, AF2) +#define TIMER7_CH1_PD0 \ + GD32_PINMUX_AF('D', 0, AF2) +#define TIMER7_CH1_PE12 \ + GD32_PINMUX_AF('E', 12, AF1) +#define TIMER7_CH1_PE14 \ + GD32_PINMUX_AF('E', 14, AF2) + +/* TIMER7_CH2 */ +#define TIMER7_CH2_PB4 \ + GD32_PINMUX_AF('B', 4, AF1) + +/* TIMER7_CH3 */ +#define TIMER7_CH3_PD7 \ + GD32_PINMUX_AF('D', 7, AF1) + +/* TIMER7_MCH0 */ +#define TIMER7_MCH0_PC10 \ + GD32_PINMUX_AF('C', 10, AF1) +#define TIMER7_MCH0_PE13 \ + GD32_PINMUX_AF('E', 13, AF1) + +/* TIMER7_MCH1 */ +#define TIMER7_MCH1_PE11 \ + GD32_PINMUX_AF('E', 11, AF1) + +/* TIMER7_MCH2 */ +#define TIMER7_MCH2_PB3 \ + GD32_PINMUX_AF('B', 3, AF1) + +/* TIMER7_MCH3 */ +#define TIMER7_MCH3_PB1 \ + GD32_PINMUX_AF('B', 1, AF2) +#define TIMER7_MCH3_PD6 \ + GD32_PINMUX_AF('D', 6, AF1) + +/* TIMER_ETI0 */ +#define TIMER_ETI0_PB13 \ + GD32_PINMUX_AF('B', 13, AF0) + +/* TIMER_ETI2 */ +#define TIMER_ETI2_PC15 \ + GD32_PINMUX_AF('C', 15, AF0) + +/* TRIGSEL_IN0 */ +#define TRIGSEL_IN0_PA1 \ + GD32_PINMUX_AF('A', 1, AF7) + +/* TRIGSEL_IN1 */ +#define TRIGSEL_IN1_PA2 \ + GD32_PINMUX_AF('A', 2, AF7) + +/* TRIGSEL_IN13 */ +#define TRIGSEL_IN13_PA11 \ + GD32_PINMUX_AF('A', 11, AF7) + +/* TRIGSEL_IN2 */ +#define TRIGSEL_IN2_PE13 \ + GD32_PINMUX_AF('E', 13, AF7) + +/* TRIGSEL_IN3 */ +#define TRIGSEL_IN3_PE14 \ + GD32_PINMUX_AF('E', 14, AF7) + +/* TRIGSEL_IN4 */ +#define TRIGSEL_IN4_PA8 \ + GD32_PINMUX_AF('A', 8, AF7) + +/* TRIGSEL_IN5 */ +#define TRIGSEL_IN5_PA9 \ + GD32_PINMUX_AF('A', 9, AF7) + +/* TRIGSEL_IN7 */ +#define TRIGSEL_IN7_PA7 \ + GD32_PINMUX_AF('A', 7, AF7) + +/* TRIGSEL_IN8 */ +#define TRIGSEL_IN8_PE11 \ + GD32_PINMUX_AF('E', 11, AF7) + +/* TRIGSEL_IN9 */ +#define TRIGSEL_IN9_PE12 \ + GD32_PINMUX_AF('E', 12, AF7) + +/* TRIGSEL_OUT0 */ +#define TRIGSEL_OUT0_PC10 \ + GD32_PINMUX_AF('C', 10, AF7) + +/* TRIGSEL_OUT1 */ +#define TRIGSEL_OUT1_PE5 \ + GD32_PINMUX_AF('E', 5, AF7) + +/* TRIGSEL_OUT2 */ +#define TRIGSEL_OUT2_PE4 \ + GD32_PINMUX_AF('E', 4, AF7) + +/* TRIGSEL_OUT3 */ +#define TRIGSEL_OUT3_PC11 \ + GD32_PINMUX_AF('C', 11, AF7) + +/* USART0_CTS */ +#define USART0_CTS_PC11 \ + GD32_PINMUX_AF('C', 11, AF5) +#define USART0_CTS_PD8 \ + GD32_PINMUX_AF('D', 8, AF5) + +/* USART0_DE */ +#define USART0_DE_PB15 \ + GD32_PINMUX_AF('B', 15, AF5) +#define USART0_DE_PC10 \ + GD32_PINMUX_AF('C', 10, AF5) + +/* USART0_RTS */ +#define USART0_RTS_PB15 \ + GD32_PINMUX_AF('B', 15, AF5) +#define USART0_RTS_PC10 \ + GD32_PINMUX_AF('C', 10, AF5) + +/* USART0_RX */ +#define USART0_RX_PA4 \ + GD32_PINMUX_AF('A', 4, AF5) +#define USART0_RX_PA11 \ + GD32_PINMUX_AF('A', 11, AF5) +#define USART0_RX_PB14 \ + GD32_PINMUX_AF('B', 14, AF5) + +/* USART0_TX */ +#define USART0_TX_PA3 \ + GD32_PINMUX_AF('A', 3, AF5) +#define USART0_TX_PA10 \ + GD32_PINMUX_AF('A', 10, AF5) +#define USART0_TX_PB13 \ + GD32_PINMUX_AF('B', 13, AF5) + +/* USART1_CTS */ +#define USART1_CTS_PF5 \ + GD32_PINMUX_AF('F', 5, AF5) + +/* USART1_DE */ +#define USART1_DE_PD9 \ + GD32_PINMUX_AF('D', 9, AF5) + +/* USART1_RTS */ +#define USART1_RTS_PD9 \ + GD32_PINMUX_AF('D', 9, AF5) + +/* USART1_RX */ +#define USART1_RX_PD0 \ + GD32_PINMUX_AF('D', 0, AF5) +#define USART1_RX_PD8 \ + GD32_PINMUX_AF('D', 8, AF4) + +/* USART1_TX */ +#define USART1_TX_PB15 \ + GD32_PINMUX_AF('B', 15, AF4) +#define USART1_TX_PC12 \ + GD32_PINMUX_AF('C', 12, AF5) + +/* USART2_CK */ +#define USART2_CK_PA7 \ + GD32_PINMUX_AF('A', 7, AF5) + +/* USART2_CTS */ +#define USART2_CTS_PC1 \ + GD32_PINMUX_AF('C', 1, AF5) + +/* USART2_RX */ +#define USART2_RX_PA6 \ + GD32_PINMUX_AF('A', 6, AF5) + +/* USART2_TX */ +#define USART2_TX_PA5 \ + GD32_PINMUX_AF('A', 5, AF5) diff --git a/include/dt-bindings/pinctrl/gd32a503k(b-c)xx-pinctrl.h b/include/dt-bindings/pinctrl/gd32a503k(b-c)xx-pinctrl.h new file mode 100644 index 0000000..d14bbf2 --- /dev/null +++ b/include/dt-bindings/pinctrl/gd32a503k(b-c)xx-pinctrl.h @@ -0,0 +1,563 @@ +/* + * Autogenerated file + * + * SPDX-License-Identifier: Apache 2.0 + */ + +#include "gd32-af.h" + +/* ADC0_IN0 */ +#define ADC0_IN0_PC11 \ + GD32_PINMUX_AF('C', 11, ANALOG) + +/* ADC0_IN1 */ +#define ADC0_IN1_PC10 \ + GD32_PINMUX_AF('C', 10, ANALOG) + +/* ADC0_IN10 */ +#define ADC0_IN10_PA4 \ + GD32_PINMUX_AF('A', 4, ANALOG) + +/* ADC0_IN11 */ +#define ADC0_IN11_PA3 \ + GD32_PINMUX_AF('A', 3, ANALOG) + +/* ADC0_IN3 */ +#define ADC0_IN3_PD9 \ + GD32_PINMUX_AF('D', 9, ANALOG) + +/* ADC0_IN4 */ +#define ADC0_IN4_PB14 \ + GD32_PINMUX_AF('B', 14, ANALOG) + +/* ADC0_IN5 */ +#define ADC0_IN5_PB13 \ + GD32_PINMUX_AF('B', 13, ANALOG) + +/* ADC0_IN6 */ +#define ADC0_IN6_PE14 \ + GD32_PINMUX_AF('E', 14, ANALOG) + +/* ADC0_IN7 */ +#define ADC0_IN7_PE13 \ + GD32_PINMUX_AF('E', 13, ANALOG) + +/* ADC1_IN0 */ +#define ADC1_IN0_PA11 \ + GD32_PINMUX_AF('A', 11, ANALOG) + +/* ADC1_IN1 */ +#define ADC1_IN1_PA10 \ + GD32_PINMUX_AF('A', 10, ANALOG) + +/* ADC1_IN14 */ +#define ADC1_IN14_PB14 \ + GD32_PINMUX_AF('B', 14, ANALOG) + +/* ADC1_IN15 */ +#define ADC1_IN15_PB13 \ + GD32_PINMUX_AF('B', 13, ANALOG) + +/* ADC1_IN3 */ +#define ADC1_IN3_PA8 \ + GD32_PINMUX_AF('A', 8, ANALOG) + +/* ANALOG */ +#define ANALOG_PA0 \ + GD32_PINMUX_AF('A', 0, ANALOG) +#define ANALOG_PA1 \ + GD32_PINMUX_AF('A', 1, ANALOG) +#define ANALOG_PA2 \ + GD32_PINMUX_AF('A', 2, ANALOG) +#define ANALOG_PA3 \ + GD32_PINMUX_AF('A', 3, ANALOG) +#define ANALOG_PA4 \ + GD32_PINMUX_AF('A', 4, ANALOG) +#define ANALOG_PA5 \ + GD32_PINMUX_AF('A', 5, ANALOG) +#define ANALOG_PA6 \ + GD32_PINMUX_AF('A', 6, ANALOG) +#define ANALOG_PA7 \ + GD32_PINMUX_AF('A', 7, ANALOG) +#define ANALOG_PA8 \ + GD32_PINMUX_AF('A', 8, ANALOG) +#define ANALOG_PA10 \ + GD32_PINMUX_AF('A', 10, ANALOG) +#define ANALOG_PA11 \ + GD32_PINMUX_AF('A', 11, ANALOG) +#define ANALOG_PB3 \ + GD32_PINMUX_AF('B', 3, ANALOG) +#define ANALOG_PB4 \ + GD32_PINMUX_AF('B', 4, ANALOG) +#define ANALOG_PB7 \ + GD32_PINMUX_AF('B', 7, ANALOG) +#define ANALOG_PB8 \ + GD32_PINMUX_AF('B', 8, ANALOG) +#define ANALOG_PB9 \ + GD32_PINMUX_AF('B', 9, ANALOG) +#define ANALOG_PB13 \ + GD32_PINMUX_AF('B', 13, ANALOG) +#define ANALOG_PB14 \ + GD32_PINMUX_AF('B', 14, ANALOG) +#define ANALOG_PC0 \ + GD32_PINMUX_AF('C', 0, ANALOG) +#define ANALOG_PC10 \ + GD32_PINMUX_AF('C', 10, ANALOG) +#define ANALOG_PC11 \ + GD32_PINMUX_AF('C', 11, ANALOG) +#define ANALOG_PC15 \ + GD32_PINMUX_AF('C', 15, ANALOG) +#define ANALOG_PD9 \ + GD32_PINMUX_AF('D', 9, ANALOG) +#define ANALOG_PE13 \ + GD32_PINMUX_AF('E', 13, ANALOG) +#define ANALOG_PE14 \ + GD32_PINMUX_AF('E', 14, ANALOG) +#define ANALOG_PF0 \ + GD32_PINMUX_AF('F', 0, ANALOG) +#define ANALOG_PF5 \ + GD32_PINMUX_AF('F', 5, ANALOG) +#define ANALOG_PF6 \ + GD32_PINMUX_AF('F', 6, ANALOG) +#define ANALOG_PF7 \ + GD32_PINMUX_AF('F', 7, ANALOG) + +/* CAN0_RX */ +#define CAN0_RX_PA4 \ + GD32_PINMUX_AF('A', 4, AF6) +#define CAN0_RX_PB14 \ + GD32_PINMUX_AF('B', 14, AF6) +#define CAN0_RX_PF0 \ + GD32_PINMUX_AF('F', 0, AF6) + +/* CAN0_TX */ +#define CAN0_TX_PA3 \ + GD32_PINMUX_AF('A', 3, AF6) +#define CAN0_TX_PB13 \ + GD32_PINMUX_AF('B', 13, AF6) +#define CAN0_TX_PC15 \ + GD32_PINMUX_AF('C', 15, AF6) + +/* CK_OUT0 */ +#define CK_OUT0_PA1 \ + GD32_PINMUX_AF('A', 1, AF0) + +/* CMP_OUT */ +#define CMP_OUT_PB9 \ + GD32_PINMUX_AF('B', 9, AF7) + +/* DAC_OUT */ +#define DAC_OUT_PA7 \ + GD32_PINMUX_AF('A', 7, ANALOG) + +/* EVENTOUT */ +#define EVENTOUT_PA0 \ + GD32_PINMUX_AF('A', 0, AF9) +#define EVENTOUT_PA1 \ + GD32_PINMUX_AF('A', 1, AF9) +#define EVENTOUT_PA2 \ + GD32_PINMUX_AF('A', 2, AF9) +#define EVENTOUT_PA3 \ + GD32_PINMUX_AF('A', 3, AF9) +#define EVENTOUT_PA4 \ + GD32_PINMUX_AF('A', 4, AF9) +#define EVENTOUT_PA5 \ + GD32_PINMUX_AF('A', 5, AF9) +#define EVENTOUT_PA7 \ + GD32_PINMUX_AF('A', 7, AF9) +#define EVENTOUT_PA8 \ + GD32_PINMUX_AF('A', 8, AF9) +#define EVENTOUT_PA10 \ + GD32_PINMUX_AF('A', 10, AF9) +#define EVENTOUT_PA11 \ + GD32_PINMUX_AF('A', 11, AF9) +#define EVENTOUT_PB3 \ + GD32_PINMUX_AF('B', 3, AF9) +#define EVENTOUT_PB4 \ + GD32_PINMUX_AF('B', 4, AF9) +#define EVENTOUT_PB7 \ + GD32_PINMUX_AF('B', 7, AF9) +#define EVENTOUT_PB8 \ + GD32_PINMUX_AF('B', 8, AF9) +#define EVENTOUT_PB9 \ + GD32_PINMUX_AF('B', 9, AF9) +#define EVENTOUT_PB13 \ + GD32_PINMUX_AF('B', 13, AF9) +#define EVENTOUT_PB14 \ + GD32_PINMUX_AF('B', 14, AF9) +#define EVENTOUT_PC0 \ + GD32_PINMUX_AF('C', 0, AF9) +#define EVENTOUT_PC10 \ + GD32_PINMUX_AF('C', 10, AF9) +#define EVENTOUT_PC11 \ + GD32_PINMUX_AF('C', 11, AF9) +#define EVENTOUT_PC15 \ + GD32_PINMUX_AF('C', 15, AF9) +#define EVENTOUT_PD9 \ + GD32_PINMUX_AF('D', 9, AF9) +#define EVENTOUT_PE13 \ + GD32_PINMUX_AF('E', 13, AF9) +#define EVENTOUT_PE14 \ + GD32_PINMUX_AF('E', 14, AF9) +#define EVENTOUT_PF0 \ + GD32_PINMUX_AF('F', 0, AF9) +#define EVENTOUT_PF5 \ + GD32_PINMUX_AF('F', 5, AF9) +#define EVENTOUT_PF6 \ + GD32_PINMUX_AF('F', 6, AF9) +#define EVENTOUT_PF7 \ + GD32_PINMUX_AF('F', 7, AF9) + +/* I2C0_SCL */ +#define I2C0_SCL_PA10 \ + GD32_PINMUX_AF('A', 10, AF3) +#define I2C0_SCL_PC11 \ + GD32_PINMUX_AF('C', 11, AF3) +#define I2C0_SCL_PF6 \ + GD32_PINMUX_AF('F', 6, AF3) + +/* I2C0_SDA */ +#define I2C0_SDA_PA11 \ + GD32_PINMUX_AF('A', 11, AF3) +#define I2C0_SDA_PC10 \ + GD32_PINMUX_AF('C', 10, AF3) +#define I2C0_SDA_PF7 \ + GD32_PINMUX_AF('F', 7, AF3) + +/* I2C1_SCL */ +#define I2C1_SCL_PB7 \ + GD32_PINMUX_AF('B', 7, AF5) + +/* I2C1_SDA */ +#define I2C1_SDA_PB8 \ + GD32_PINMUX_AF('B', 8, AF5) + +/* I2C1_SMBA */ +#define I2C1_SMBA_PB9 \ + GD32_PINMUX_AF('B', 9, AF5) + +/* I2S1_WS */ +#define I2S1_WS_PA8 \ + GD32_PINMUX_AF('A', 8, AF4) + +/* JTCK */ +#define JTCK_PB8 \ + GD32_PINMUX_AF('B', 8, AF0) + +/* JTDI */ +#define JTDI_PB7 \ + GD32_PINMUX_AF('B', 7, AF0) + +/* JTDO */ +#define JTDO_PB4 \ + GD32_PINMUX_AF('B', 4, AF0) + +/* JTMS */ +#define JTMS_PB9 \ + GD32_PINMUX_AF('B', 9, AF0) + +/* MFCOM_D0 */ +#define MFCOM_D0_PB4 \ + GD32_PINMUX_AF('B', 4, AF6) + +/* MFCOM_D1 */ +#define MFCOM_D1_PB3 \ + GD32_PINMUX_AF('B', 3, AF6) + +/* MFCOM_D2 */ +#define MFCOM_D2_PC11 \ + GD32_PINMUX_AF('C', 11, AF6) + +/* MFCOM_D3 */ +#define MFCOM_D3_PC10 \ + GD32_PINMUX_AF('C', 10, AF6) + +/* MFCOM_D4 */ +#define MFCOM_D4_PA11 \ + GD32_PINMUX_AF('A', 11, AF6) + +/* MFCOM_D5 */ +#define MFCOM_D5_PA8 \ + GD32_PINMUX_AF('A', 8, AF6) +#define MFCOM_D5_PA10 \ + GD32_PINMUX_AF('A', 10, AF6) + +/* MFCOM_D6 */ +#define MFCOM_D6_PF0 \ + GD32_PINMUX_AF('F', 0, AF7) + +/* MFCOM_D7 */ +#define MFCOM_D7_PA8 \ + GD32_PINMUX_AF('A', 8, AF5) +#define MFCOM_D7_PC15 \ + GD32_PINMUX_AF('C', 15, AF7) + +/* NJTRST */ +#define NJTRST_PB3 \ + GD32_PINMUX_AF('B', 3, AF0) + +/* SPI0_IO2 */ +#define SPI0_IO2_PB3 \ + GD32_PINMUX_AF('B', 3, AF4) + +/* SPI0_IO3 */ +#define SPI0_IO3_PB4 \ + GD32_PINMUX_AF('B', 4, AF4) + +/* SPI0_MISO */ +#define SPI0_MISO_PE13 \ + GD32_PINMUX_AF('E', 13, AF4) +#define SPI0_MISO_PF5 \ + GD32_PINMUX_AF('F', 5, AF4) + +/* SPI0_MOSI */ +#define SPI0_MOSI_PA2 \ + GD32_PINMUX_AF('A', 2, AF4) +#define SPI0_MOSI_PB13 \ + GD32_PINMUX_AF('B', 13, AF4) + +/* SPI0_NSS */ +#define SPI0_NSS_PA1 \ + GD32_PINMUX_AF('A', 1, AF4) +#define SPI0_NSS_PB14 \ + GD32_PINMUX_AF('B', 14, AF3) + +/* SPI0_SCK */ +#define SPI0_SCK_PC0 \ + GD32_PINMUX_AF('C', 0, AF4) +#define SPI0_SCK_PE14 \ + GD32_PINMUX_AF('E', 14, AF4) + +/* SPI1_NSS */ +#define SPI1_NSS_PA8 \ + GD32_PINMUX_AF('A', 8, AF4) + +/* SWCLK */ +#define SWCLK_PB8 \ + GD32_PINMUX_AF('B', 8, AF0) + +/* SWDIO */ +#define SWDIO_PB9 \ + GD32_PINMUX_AF('B', 9, AF0) + +/* TIMER0_BRKIN0 */ +#define TIMER0_BRKIN0_PA8 \ + GD32_PINMUX_AF('A', 8, AF1) + +/* TIMER0_BRKIN2 */ +#define TIMER0_BRKIN2_PD9 \ + GD32_PINMUX_AF('D', 9, AF2) + +/* TIMER0_CH0 */ +#define TIMER0_CH0_PC0 \ + GD32_PINMUX_AF('C', 0, AF1) + +/* TIMER0_CH1 */ +#define TIMER0_CH1_PA4 \ + GD32_PINMUX_AF('A', 4, AF1) + +/* TIMER0_CH2 */ +#define TIMER0_CH2_PA2 \ + GD32_PINMUX_AF('A', 2, AF1) + +/* TIMER0_CH3 */ +#define TIMER0_CH3_PA0 \ + GD32_PINMUX_AF('A', 0, AF1) + +/* TIMER0_MCH0 */ +#define TIMER0_MCH0_PF5 \ + GD32_PINMUX_AF('F', 5, AF1) + +/* TIMER0_MCH1 */ +#define TIMER0_MCH1_PA3 \ + GD32_PINMUX_AF('A', 3, AF1) + +/* TIMER0_MCH2 */ +#define TIMER0_MCH2_PA1 \ + GD32_PINMUX_AF('A', 1, AF1) + +/* TIMER19_BRKIN1 */ +#define TIMER19_BRKIN1_PA7 \ + GD32_PINMUX_AF('A', 7, AF3) + +/* TIMER19_BRKIN2 */ +#define TIMER19_BRKIN2_PA6 \ + GD32_PINMUX_AF('A', 6, AF2) + +/* TIMER19_BRKIN3 */ +#define TIMER19_BRKIN3_PA5 \ + GD32_PINMUX_AF('A', 5, AF2) + +/* TIMER19_CH0 */ +#define TIMER19_CH0_PB7 \ + GD32_PINMUX_AF('B', 7, AF1) +#define TIMER19_CH0_PC11 \ + GD32_PINMUX_AF('C', 11, AF2) + +/* TIMER19_CH1 */ +#define TIMER19_CH1_PB7 \ + GD32_PINMUX_AF('B', 7, AF2) +#define TIMER19_CH1_PC15 \ + GD32_PINMUX_AF('C', 15, AF2) +#define TIMER19_CH1_PF0 \ + GD32_PINMUX_AF('F', 0, AF1) + +/* TIMER19_MCH0 */ +#define TIMER19_MCH0_PC11 \ + GD32_PINMUX_AF('C', 11, AF1) + +/* TIMER19_MCH1 */ +#define TIMER19_MCH1_PA7 \ + GD32_PINMUX_AF('A', 7, AF1) +#define TIMER19_MCH1_PC15 \ + GD32_PINMUX_AF('C', 15, AF1) + +/* TIMER1_CH1 */ +#define TIMER1_CH1_PA7 \ + GD32_PINMUX_AF('A', 7, AF2) + +/* TIMER1_CH2 */ +#define TIMER1_CH2_PB14 \ + GD32_PINMUX_AF('B', 14, AF1) + +/* TIMER1_CH3 */ +#define TIMER1_CH3_PA3 \ + GD32_PINMUX_AF('A', 3, AF2) + +/* TIMER20_CH0 */ +#define TIMER20_CH0_PA11 \ + GD32_PINMUX_AF('A', 11, AF1) + +/* TIMER20_MCH0 */ +#define TIMER20_MCH0_PA10 \ + GD32_PINMUX_AF('A', 10, AF1) + +/* TIMER20_MCH2 */ +#define TIMER20_MCH2_PA8 \ + GD32_PINMUX_AF('A', 8, AF2) + +/* TIMER7_CH0 */ +#define TIMER7_CH0_PB8 \ + GD32_PINMUX_AF('B', 8, AF1) +#define TIMER7_CH0_PC10 \ + GD32_PINMUX_AF('C', 10, AF2) +#define TIMER7_CH0_PE13 \ + GD32_PINMUX_AF('E', 13, AF2) +#define TIMER7_CH0_PE14 \ + GD32_PINMUX_AF('E', 14, AF1) + +/* TIMER7_CH1 */ +#define TIMER7_CH1_PB8 \ + GD32_PINMUX_AF('B', 8, AF2) +#define TIMER7_CH1_PE14 \ + GD32_PINMUX_AF('E', 14, AF2) + +/* TIMER7_CH2 */ +#define TIMER7_CH2_PB4 \ + GD32_PINMUX_AF('B', 4, AF1) + +/* TIMER7_MCH0 */ +#define TIMER7_MCH0_PC10 \ + GD32_PINMUX_AF('C', 10, AF1) +#define TIMER7_MCH0_PE13 \ + GD32_PINMUX_AF('E', 13, AF1) + +/* TIMER7_MCH2 */ +#define TIMER7_MCH2_PB3 \ + GD32_PINMUX_AF('B', 3, AF1) + +/* TIMER_ETI0 */ +#define TIMER_ETI0_PB13 \ + GD32_PINMUX_AF('B', 13, AF0) + +/* TIMER_ETI2 */ +#define TIMER_ETI2_PC15 \ + GD32_PINMUX_AF('C', 15, AF0) + +/* TRIGSEL_IN0 */ +#define TRIGSEL_IN0_PA1 \ + GD32_PINMUX_AF('A', 1, AF7) + +/* TRIGSEL_IN1 */ +#define TRIGSEL_IN1_PA2 \ + GD32_PINMUX_AF('A', 2, AF7) + +/* TRIGSEL_IN13 */ +#define TRIGSEL_IN13_PA11 \ + GD32_PINMUX_AF('A', 11, AF7) + +/* TRIGSEL_IN2 */ +#define TRIGSEL_IN2_PE13 \ + GD32_PINMUX_AF('E', 13, AF7) + +/* TRIGSEL_IN3 */ +#define TRIGSEL_IN3_PE14 \ + GD32_PINMUX_AF('E', 14, AF7) + +/* TRIGSEL_IN4 */ +#define TRIGSEL_IN4_PA8 \ + GD32_PINMUX_AF('A', 8, AF7) + +/* TRIGSEL_IN7 */ +#define TRIGSEL_IN7_PA7 \ + GD32_PINMUX_AF('A', 7, AF7) + +/* TRIGSEL_OUT0 */ +#define TRIGSEL_OUT0_PC10 \ + GD32_PINMUX_AF('C', 10, AF7) + +/* TRIGSEL_OUT3 */ +#define TRIGSEL_OUT3_PC11 \ + GD32_PINMUX_AF('C', 11, AF7) + +/* USART0_CTS */ +#define USART0_CTS_PC11 \ + GD32_PINMUX_AF('C', 11, AF5) + +/* USART0_DE */ +#define USART0_DE_PC10 \ + GD32_PINMUX_AF('C', 10, AF5) + +/* USART0_RTS */ +#define USART0_RTS_PC10 \ + GD32_PINMUX_AF('C', 10, AF5) + +/* USART0_RX */ +#define USART0_RX_PA4 \ + GD32_PINMUX_AF('A', 4, AF5) +#define USART0_RX_PA11 \ + GD32_PINMUX_AF('A', 11, AF5) +#define USART0_RX_PB14 \ + GD32_PINMUX_AF('B', 14, AF5) + +/* USART0_TX */ +#define USART0_TX_PA3 \ + GD32_PINMUX_AF('A', 3, AF5) +#define USART0_TX_PA10 \ + GD32_PINMUX_AF('A', 10, AF5) +#define USART0_TX_PB13 \ + GD32_PINMUX_AF('B', 13, AF5) + +/* USART1_CTS */ +#define USART1_CTS_PF5 \ + GD32_PINMUX_AF('F', 5, AF5) + +/* USART1_DE */ +#define USART1_DE_PD9 \ + GD32_PINMUX_AF('D', 9, AF5) + +/* USART1_RTS */ +#define USART1_RTS_PD9 \ + GD32_PINMUX_AF('D', 9, AF5) + +/* USART2_CK */ +#define USART2_CK_PA7 \ + GD32_PINMUX_AF('A', 7, AF5) + +/* USART2_RX */ +#define USART2_RX_PA6 \ + GD32_PINMUX_AF('A', 6, AF5) + +/* USART2_TX */ +#define USART2_TX_PA5 \ + GD32_PINMUX_AF('A', 5, AF5) diff --git a/include/dt-bindings/pinctrl/gd32a503r(b-c-d)xx-pinctrl.h b/include/dt-bindings/pinctrl/gd32a503r(b-c-d)xx-pinctrl.h new file mode 100644 index 0000000..7e4bf66 --- /dev/null +++ b/include/dt-bindings/pinctrl/gd32a503r(b-c-d)xx-pinctrl.h @@ -0,0 +1,1039 @@ +/* + * Autogenerated file + * + * SPDX-License-Identifier: Apache 2.0 + */ + +#include "gd32-af.h" + +/* ADC0_IN0 */ +#define ADC0_IN0_PC11 \ + GD32_PINMUX_AF('C', 11, ANALOG) + +/* ADC0_IN1 */ +#define ADC0_IN1_PC10 \ + GD32_PINMUX_AF('C', 10, ANALOG) + +/* ADC0_IN10 */ +#define ADC0_IN10_PA4 \ + GD32_PINMUX_AF('A', 4, ANALOG) + +/* ADC0_IN11 */ +#define ADC0_IN11_PA3 \ + GD32_PINMUX_AF('A', 3, ANALOG) + +/* ADC0_IN12 */ +#define ADC0_IN12_PE12 \ + GD32_PINMUX_AF('E', 12, ANALOG) + +/* ADC0_IN13 */ +#define ADC0_IN13_PE11 \ + GD32_PINMUX_AF('E', 11, ANALOG) + +/* ADC0_IN14 */ +#define ADC0_IN14_PE10 \ + GD32_PINMUX_AF('E', 10, ANALOG) + +/* ADC0_IN15 */ +#define ADC0_IN15_PE9 \ + GD32_PINMUX_AF('E', 9, ANALOG) + +/* ADC0_IN2 */ +#define ADC0_IN2_PD10 \ + GD32_PINMUX_AF('D', 10, ANALOG) + +/* ADC0_IN3 */ +#define ADC0_IN3_PD9 \ + GD32_PINMUX_AF('D', 9, ANALOG) + +/* ADC0_IN4 */ +#define ADC0_IN4_PB14 \ + GD32_PINMUX_AF('B', 14, ANALOG) + +/* ADC0_IN5 */ +#define ADC0_IN5_PB13 \ + GD32_PINMUX_AF('B', 13, ANALOG) + +/* ADC0_IN6 */ +#define ADC0_IN6_PE14 \ + GD32_PINMUX_AF('E', 14, ANALOG) + +/* ADC0_IN7 */ +#define ADC0_IN7_PE13 \ + GD32_PINMUX_AF('E', 13, ANALOG) + +/* ADC0_IN8 */ +#define ADC0_IN8_PB2 \ + GD32_PINMUX_AF('B', 2, ANALOG) +#define ADC0_IN8_PC7 \ + GD32_PINMUX_AF('C', 7, ANALOG) + +/* ADC0_IN9 */ +#define ADC0_IN9_PB1 \ + GD32_PINMUX_AF('B', 1, ANALOG) + +/* ADC1_IN0 */ +#define ADC1_IN0_PA11 \ + GD32_PINMUX_AF('A', 11, ANALOG) + +/* ADC1_IN1 */ +#define ADC1_IN1_PA10 \ + GD32_PINMUX_AF('A', 10, ANALOG) + +/* ADC1_IN10 */ +#define ADC1_IN10_PD4 \ + GD32_PINMUX_AF('D', 4, ANALOG) + +/* ADC1_IN11 */ +#define ADC1_IN11_PD3 \ + GD32_PINMUX_AF('D', 3, ANALOG) + +/* ADC1_IN14 */ +#define ADC1_IN14_PB14 \ + GD32_PINMUX_AF('B', 14, ANALOG) + +/* ADC1_IN15 */ +#define ADC1_IN15_PB13 \ + GD32_PINMUX_AF('B', 13, ANALOG) + +/* ADC1_IN2 */ +#define ADC1_IN2_PA9 \ + GD32_PINMUX_AF('A', 9, ANALOG) + +/* ADC1_IN3 */ +#define ADC1_IN3_PA8 \ + GD32_PINMUX_AF('A', 8, ANALOG) + +/* ADC1_IN4 */ +#define ADC1_IN4_PD0 \ + GD32_PINMUX_AF('D', 0, ANALOG) + +/* ADC1_IN5 */ +#define ADC1_IN5_PC12 \ + GD32_PINMUX_AF('C', 12, ANALOG) + +/* ADC1_IN6 */ +#define ADC1_IN6_PC9 \ + GD32_PINMUX_AF('C', 9, ANALOG) + +/* ADC1_IN7 */ +#define ADC1_IN7_PC8 \ + GD32_PINMUX_AF('C', 8, ANALOG) + +/* ADC1_IN8 */ +#define ADC1_IN8_PC7 \ + GD32_PINMUX_AF('C', 7, ANALOG) + +/* ANALOG */ +#define ANALOG_PA0 \ + GD32_PINMUX_AF('A', 0, ANALOG) +#define ANALOG_PA1 \ + GD32_PINMUX_AF('A', 1, ANALOG) +#define ANALOG_PA2 \ + GD32_PINMUX_AF('A', 2, ANALOG) +#define ANALOG_PA3 \ + GD32_PINMUX_AF('A', 3, ANALOG) +#define ANALOG_PA4 \ + GD32_PINMUX_AF('A', 4, ANALOG) +#define ANALOG_PA5 \ + GD32_PINMUX_AF('A', 5, ANALOG) +#define ANALOG_PA6 \ + GD32_PINMUX_AF('A', 6, ANALOG) +#define ANALOG_PA7 \ + GD32_PINMUX_AF('A', 7, ANALOG) +#define ANALOG_PA8 \ + GD32_PINMUX_AF('A', 8, ANALOG) +#define ANALOG_PA9 \ + GD32_PINMUX_AF('A', 9, ANALOG) +#define ANALOG_PA10 \ + GD32_PINMUX_AF('A', 10, ANALOG) +#define ANALOG_PA11 \ + GD32_PINMUX_AF('A', 11, ANALOG) +#define ANALOG_PB1 \ + GD32_PINMUX_AF('B', 1, ANALOG) +#define ANALOG_PB2 \ + GD32_PINMUX_AF('B', 2, ANALOG) +#define ANALOG_PB3 \ + GD32_PINMUX_AF('B', 3, ANALOG) +#define ANALOG_PB4 \ + GD32_PINMUX_AF('B', 4, ANALOG) +#define ANALOG_PB5 \ + GD32_PINMUX_AF('B', 5, ANALOG) +#define ANALOG_PB6 \ + GD32_PINMUX_AF('B', 6, ANALOG) +#define ANALOG_PB7 \ + GD32_PINMUX_AF('B', 7, ANALOG) +#define ANALOG_PB8 \ + GD32_PINMUX_AF('B', 8, ANALOG) +#define ANALOG_PB9 \ + GD32_PINMUX_AF('B', 9, ANALOG) +#define ANALOG_PB13 \ + GD32_PINMUX_AF('B', 13, ANALOG) +#define ANALOG_PB14 \ + GD32_PINMUX_AF('B', 14, ANALOG) +#define ANALOG_PB15 \ + GD32_PINMUX_AF('B', 15, ANALOG) +#define ANALOG_PC0 \ + GD32_PINMUX_AF('C', 0, ANALOG) +#define ANALOG_PC1 \ + GD32_PINMUX_AF('C', 1, ANALOG) +#define ANALOG_PC7 \ + GD32_PINMUX_AF('C', 7, ANALOG) +#define ANALOG_PC8 \ + GD32_PINMUX_AF('C', 8, ANALOG) +#define ANALOG_PC9 \ + GD32_PINMUX_AF('C', 9, ANALOG) +#define ANALOG_PC10 \ + GD32_PINMUX_AF('C', 10, ANALOG) +#define ANALOG_PC11 \ + GD32_PINMUX_AF('C', 11, ANALOG) +#define ANALOG_PC12 \ + GD32_PINMUX_AF('C', 12, ANALOG) +#define ANALOG_PC13 \ + GD32_PINMUX_AF('C', 13, ANALOG) +#define ANALOG_PC15 \ + GD32_PINMUX_AF('C', 15, ANALOG) +#define ANALOG_PD0 \ + GD32_PINMUX_AF('D', 0, ANALOG) +#define ANALOG_PD3 \ + GD32_PINMUX_AF('D', 3, ANALOG) +#define ANALOG_PD4 \ + GD32_PINMUX_AF('D', 4, ANALOG) +#define ANALOG_PD6 \ + GD32_PINMUX_AF('D', 6, ANALOG) +#define ANALOG_PD7 \ + GD32_PINMUX_AF('D', 7, ANALOG) +#define ANALOG_PD8 \ + GD32_PINMUX_AF('D', 8, ANALOG) +#define ANALOG_PD9 \ + GD32_PINMUX_AF('D', 9, ANALOG) +#define ANALOG_PD10 \ + GD32_PINMUX_AF('D', 10, ANALOG) +#define ANALOG_PD11 \ + GD32_PINMUX_AF('D', 11, ANALOG) +#define ANALOG_PE4 \ + GD32_PINMUX_AF('E', 4, ANALOG) +#define ANALOG_PE5 \ + GD32_PINMUX_AF('E', 5, ANALOG) +#define ANALOG_PE6 \ + GD32_PINMUX_AF('E', 6, ANALOG) +#define ANALOG_PE9 \ + GD32_PINMUX_AF('E', 9, ANALOG) +#define ANALOG_PE10 \ + GD32_PINMUX_AF('E', 10, ANALOG) +#define ANALOG_PE11 \ + GD32_PINMUX_AF('E', 11, ANALOG) +#define ANALOG_PE12 \ + GD32_PINMUX_AF('E', 12, ANALOG) +#define ANALOG_PE13 \ + GD32_PINMUX_AF('E', 13, ANALOG) +#define ANALOG_PE14 \ + GD32_PINMUX_AF('E', 14, ANALOG) +#define ANALOG_PF0 \ + GD32_PINMUX_AF('F', 0, ANALOG) +#define ANALOG_PF2 \ + GD32_PINMUX_AF('F', 2, ANALOG) +#define ANALOG_PF5 \ + GD32_PINMUX_AF('F', 5, ANALOG) +#define ANALOG_PF6 \ + GD32_PINMUX_AF('F', 6, ANALOG) +#define ANALOG_PF7 \ + GD32_PINMUX_AF('F', 7, ANALOG) + +/* CAN0_RX */ +#define CAN0_RX_PA4 \ + GD32_PINMUX_AF('A', 4, AF6) +#define CAN0_RX_PB14 \ + GD32_PINMUX_AF('B', 14, AF6) +#define CAN0_RX_PF0 \ + GD32_PINMUX_AF('F', 0, AF6) + +/* CAN0_TX */ +#define CAN0_TX_PA3 \ + GD32_PINMUX_AF('A', 3, AF6) +#define CAN0_TX_PB13 \ + GD32_PINMUX_AF('B', 13, AF6) +#define CAN0_TX_PC15 \ + GD32_PINMUX_AF('C', 15, AF6) + +/* CAN1_RX */ +#define CAN1_RX_PD0 \ + GD32_PINMUX_AF('D', 0, AF6) +#define CAN1_RX_PD7 \ + GD32_PINMUX_AF('D', 7, AF6) + +/* CAN1_TX */ +#define CAN1_TX_PC12 \ + GD32_PINMUX_AF('C', 12, AF6) +#define CAN1_TX_PD6 \ + GD32_PINMUX_AF('D', 6, AF6) + +/* CK_OUT */ +#define CK_OUT_PC13 \ + GD32_PINMUX_AF('C', 13, AF0) + +/* CK_OUT0 */ +#define CK_OUT0_PA1 \ + GD32_PINMUX_AF('A', 1, AF0) + +/* CMP_OUT */ +#define CMP_OUT_PB9 \ + GD32_PINMUX_AF('B', 9, AF7) +#define CMP_OUT_PF2 \ + GD32_PINMUX_AF('F', 2, AF7) + +/* DAC_OUT */ +#define DAC_OUT_PA7 \ + GD32_PINMUX_AF('A', 7, ANALOG) + +/* EVENTOUT */ +#define EVENTOUT_PA0 \ + GD32_PINMUX_AF('A', 0, AF9) +#define EVENTOUT_PA1 \ + GD32_PINMUX_AF('A', 1, AF9) +#define EVENTOUT_PA2 \ + GD32_PINMUX_AF('A', 2, AF9) +#define EVENTOUT_PA3 \ + GD32_PINMUX_AF('A', 3, AF9) +#define EVENTOUT_PA4 \ + GD32_PINMUX_AF('A', 4, AF9) +#define EVENTOUT_PA5 \ + GD32_PINMUX_AF('A', 5, AF9) +#define EVENTOUT_PA7 \ + GD32_PINMUX_AF('A', 7, AF9) +#define EVENTOUT_PA8 \ + GD32_PINMUX_AF('A', 8, AF9) +#define EVENTOUT_PA9 \ + GD32_PINMUX_AF('A', 9, AF9) +#define EVENTOUT_PA10 \ + GD32_PINMUX_AF('A', 10, AF9) +#define EVENTOUT_PA11 \ + GD32_PINMUX_AF('A', 11, AF9) +#define EVENTOUT_PB1 \ + GD32_PINMUX_AF('B', 1, AF9) +#define EVENTOUT_PB2 \ + GD32_PINMUX_AF('B', 2, AF9) +#define EVENTOUT_PB3 \ + GD32_PINMUX_AF('B', 3, AF9) +#define EVENTOUT_PB4 \ + GD32_PINMUX_AF('B', 4, AF9) +#define EVENTOUT_PB5 \ + GD32_PINMUX_AF('B', 5, AF9) +#define EVENTOUT_PB6 \ + GD32_PINMUX_AF('B', 6, AF9) +#define EVENTOUT_PB7 \ + GD32_PINMUX_AF('B', 7, AF9) +#define EVENTOUT_PB8 \ + GD32_PINMUX_AF('B', 8, AF9) +#define EVENTOUT_PB9 \ + GD32_PINMUX_AF('B', 9, AF9) +#define EVENTOUT_PB13 \ + GD32_PINMUX_AF('B', 13, AF9) +#define EVENTOUT_PB14 \ + GD32_PINMUX_AF('B', 14, AF9) +#define EVENTOUT_PB15 \ + GD32_PINMUX_AF('B', 15, AF9) +#define EVENTOUT_PC0 \ + GD32_PINMUX_AF('C', 0, AF9) +#define EVENTOUT_PC1 \ + GD32_PINMUX_AF('C', 1, AF9) +#define EVENTOUT_PC7 \ + GD32_PINMUX_AF('C', 7, AF9) +#define EVENTOUT_PC8 \ + GD32_PINMUX_AF('C', 8, AF9) +#define EVENTOUT_PC9 \ + GD32_PINMUX_AF('C', 9, AF9) +#define EVENTOUT_PC10 \ + GD32_PINMUX_AF('C', 10, AF9) +#define EVENTOUT_PC11 \ + GD32_PINMUX_AF('C', 11, AF9) +#define EVENTOUT_PC12 \ + GD32_PINMUX_AF('C', 12, AF9) +#define EVENTOUT_PC13 \ + GD32_PINMUX_AF('C', 13, AF9) +#define EVENTOUT_PC15 \ + GD32_PINMUX_AF('C', 15, AF9) +#define EVENTOUT_PD0 \ + GD32_PINMUX_AF('D', 0, AF9) +#define EVENTOUT_PD3 \ + GD32_PINMUX_AF('D', 3, AF9) +#define EVENTOUT_PD4 \ + GD32_PINMUX_AF('D', 4, AF9) +#define EVENTOUT_PD6 \ + GD32_PINMUX_AF('D', 6, AF9) +#define EVENTOUT_PD7 \ + GD32_PINMUX_AF('D', 7, AF9) +#define EVENTOUT_PD8 \ + GD32_PINMUX_AF('D', 8, AF9) +#define EVENTOUT_PD9 \ + GD32_PINMUX_AF('D', 9, AF9) +#define EVENTOUT_PD10 \ + GD32_PINMUX_AF('D', 10, AF9) +#define EVENTOUT_PD11 \ + GD32_PINMUX_AF('D', 11, AF9) +#define EVENTOUT_PE4 \ + GD32_PINMUX_AF('E', 4, AF9) +#define EVENTOUT_PE5 \ + GD32_PINMUX_AF('E', 5, AF9) +#define EVENTOUT_PE6 \ + GD32_PINMUX_AF('E', 6, AF9) +#define EVENTOUT_PE9 \ + GD32_PINMUX_AF('E', 9, AF9) +#define EVENTOUT_PE10 \ + GD32_PINMUX_AF('E', 10, AF9) +#define EVENTOUT_PE11 \ + GD32_PINMUX_AF('E', 11, AF9) +#define EVENTOUT_PE12 \ + GD32_PINMUX_AF('E', 12, AF9) +#define EVENTOUT_PE13 \ + GD32_PINMUX_AF('E', 13, AF9) +#define EVENTOUT_PE14 \ + GD32_PINMUX_AF('E', 14, AF9) +#define EVENTOUT_PF0 \ + GD32_PINMUX_AF('F', 0, AF9) +#define EVENTOUT_PF2 \ + GD32_PINMUX_AF('F', 2, AF9) +#define EVENTOUT_PF5 \ + GD32_PINMUX_AF('F', 5, AF9) +#define EVENTOUT_PF6 \ + GD32_PINMUX_AF('F', 6, AF9) +#define EVENTOUT_PF7 \ + GD32_PINMUX_AF('F', 7, AF9) + +/* I2C0_SCL */ +#define I2C0_SCL_PA10 \ + GD32_PINMUX_AF('A', 10, AF3) +#define I2C0_SCL_PC11 \ + GD32_PINMUX_AF('C', 11, AF3) +#define I2C0_SCL_PF6 \ + GD32_PINMUX_AF('F', 6, AF3) + +/* I2C0_SDA */ +#define I2C0_SDA_PA11 \ + GD32_PINMUX_AF('A', 11, AF3) +#define I2C0_SDA_PC10 \ + GD32_PINMUX_AF('C', 10, AF3) +#define I2C0_SDA_PF7 \ + GD32_PINMUX_AF('F', 7, AF3) + +/* I2C0_SMBA */ +#define I2C0_SMBA_PB5 \ + GD32_PINMUX_AF('B', 5, AF3) + +/* I2C1_SCL */ +#define I2C1_SCL_PB7 \ + GD32_PINMUX_AF('B', 7, AF5) +#define I2C1_SCL_PD6 \ + GD32_PINMUX_AF('D', 6, AF5) +#define I2C1_SCL_PE10 \ + GD32_PINMUX_AF('E', 10, AF5) + +/* I2C1_SDA */ +#define I2C1_SDA_PB8 \ + GD32_PINMUX_AF('B', 8, AF5) +#define I2C1_SDA_PD7 \ + GD32_PINMUX_AF('D', 7, AF5) +#define I2C1_SDA_PE11 \ + GD32_PINMUX_AF('E', 11, AF5) + +/* I2C1_SMBA */ +#define I2C1_SMBA_PB9 \ + GD32_PINMUX_AF('B', 9, AF5) +#define I2C1_SMBA_PD11 \ + GD32_PINMUX_AF('D', 11, AF5) +#define I2C1_SMBA_PE12 \ + GD32_PINMUX_AF('E', 12, AF5) + +/* I2S1_CK */ +#define I2S1_CK_PE5 \ + GD32_PINMUX_AF('E', 5, AF4) + +/* I2S1_MCK */ +#define I2S1_MCK_PC7 \ + GD32_PINMUX_AF('C', 7, AF4) +#define I2S1_MCK_PE6 \ + GD32_PINMUX_AF('E', 6, AF4) + +/* I2S1_SD */ +#define I2S1_SD_PA9 \ + GD32_PINMUX_AF('A', 9, AF4) +#define I2S1_SD_PB6 \ + GD32_PINMUX_AF('B', 6, AF5) + +/* I2S1_WS */ +#define I2S1_WS_PA8 \ + GD32_PINMUX_AF('A', 8, AF4) +#define I2S1_WS_PB5 \ + GD32_PINMUX_AF('B', 5, AF6) +#define I2S1_WS_PD10 \ + GD32_PINMUX_AF('D', 10, AF4) + +/* JTCK */ +#define JTCK_PB8 \ + GD32_PINMUX_AF('B', 8, AF0) + +/* JTDI */ +#define JTDI_PB7 \ + GD32_PINMUX_AF('B', 7, AF0) + +/* JTDO */ +#define JTDO_PB4 \ + GD32_PINMUX_AF('B', 4, AF0) + +/* JTMS */ +#define JTMS_PB9 \ + GD32_PINMUX_AF('B', 9, AF0) + +/* MFCOM_D0 */ +#define MFCOM_D0_PB4 \ + GD32_PINMUX_AF('B', 4, AF6) +#define MFCOM_D0_PE5 \ + GD32_PINMUX_AF('E', 5, AF6) + +/* MFCOM_D1 */ +#define MFCOM_D1_PB3 \ + GD32_PINMUX_AF('B', 3, AF6) +#define MFCOM_D1_PE4 \ + GD32_PINMUX_AF('E', 4, AF6) + +/* MFCOM_D2 */ +#define MFCOM_D2_PC11 \ + GD32_PINMUX_AF('C', 11, AF6) + +/* MFCOM_D3 */ +#define MFCOM_D3_PC10 \ + GD32_PINMUX_AF('C', 10, AF6) + +/* MFCOM_D4 */ +#define MFCOM_D4_PA9 \ + GD32_PINMUX_AF('A', 9, AF6) +#define MFCOM_D4_PA11 \ + GD32_PINMUX_AF('A', 11, AF6) +#define MFCOM_D4_PC13 \ + GD32_PINMUX_AF('C', 13, AF6) + +/* MFCOM_D5 */ +#define MFCOM_D5_PA8 \ + GD32_PINMUX_AF('A', 8, AF6) +#define MFCOM_D5_PA10 \ + GD32_PINMUX_AF('A', 10, AF6) +#define MFCOM_D5_PE6 \ + GD32_PINMUX_AF('E', 6, AF6) + +/* MFCOM_D6 */ +#define MFCOM_D6_PA9 \ + GD32_PINMUX_AF('A', 9, AF5) +#define MFCOM_D6_PF0 \ + GD32_PINMUX_AF('F', 0, AF7) + +/* MFCOM_D7 */ +#define MFCOM_D7_PA8 \ + GD32_PINMUX_AF('A', 8, AF5) +#define MFCOM_D7_PC15 \ + GD32_PINMUX_AF('C', 15, AF7) + +/* NJTRST */ +#define NJTRST_PB3 \ + GD32_PINMUX_AF('B', 3, AF0) + +/* SPI0_IO2 */ +#define SPI0_IO2_PB3 \ + GD32_PINMUX_AF('B', 3, AF4) + +/* SPI0_IO3 */ +#define SPI0_IO3_PB4 \ + GD32_PINMUX_AF('B', 4, AF4) + +/* SPI0_MISO */ +#define SPI0_MISO_PB5 \ + GD32_PINMUX_AF('B', 5, AF4) +#define SPI0_MISO_PE13 \ + GD32_PINMUX_AF('E', 13, AF4) +#define SPI0_MISO_PF5 \ + GD32_PINMUX_AF('F', 5, AF4) + +/* SPI0_MOSI */ +#define SPI0_MOSI_PA2 \ + GD32_PINMUX_AF('A', 2, AF4) +#define SPI0_MOSI_PB13 \ + GD32_PINMUX_AF('B', 13, AF4) +#define SPI0_MOSI_PD4 \ + GD32_PINMUX_AF('D', 4, AF4) + +/* SPI0_NSS */ +#define SPI0_NSS_PA1 \ + GD32_PINMUX_AF('A', 1, AF4) +#define SPI0_NSS_PB14 \ + GD32_PINMUX_AF('B', 14, AF3) +#define SPI0_NSS_PD3 \ + GD32_PINMUX_AF('D', 3, AF4) + +/* SPI0_SCK */ +#define SPI0_SCK_PB6 \ + GD32_PINMUX_AF('B', 6, AF4) +#define SPI0_SCK_PC0 \ + GD32_PINMUX_AF('C', 0, AF4) +#define SPI0_SCK_PE14 \ + GD32_PINMUX_AF('E', 14, AF4) + +/* SPI1_MISO */ +#define SPI1_MISO_PE4 \ + GD32_PINMUX_AF('E', 4, AF4) + +/* SPI1_MOSI */ +#define SPI1_MOSI_PA9 \ + GD32_PINMUX_AF('A', 9, AF4) +#define SPI1_MOSI_PB6 \ + GD32_PINMUX_AF('B', 6, AF5) + +/* SPI1_NSS */ +#define SPI1_NSS_PA8 \ + GD32_PINMUX_AF('A', 8, AF4) +#define SPI1_NSS_PB5 \ + GD32_PINMUX_AF('B', 5, AF5) +#define SPI1_NSS_PD10 \ + GD32_PINMUX_AF('D', 10, AF4) + +/* SPI1_SCK */ +#define SPI1_SCK_PE5 \ + GD32_PINMUX_AF('E', 5, AF4) + +/* SWCLK */ +#define SWCLK_PB8 \ + GD32_PINMUX_AF('B', 8, AF0) + +/* SWDIO */ +#define SWDIO_PB9 \ + GD32_PINMUX_AF('B', 9, AF0) + +/* TIMER0_BRKIN0 */ +#define TIMER0_BRKIN0_PA8 \ + GD32_PINMUX_AF('A', 8, AF1) +#define TIMER0_BRKIN0_PF2 \ + GD32_PINMUX_AF('F', 2, AF1) + +/* TIMER0_BRKIN1 */ +#define TIMER0_BRKIN1_PD10 \ + GD32_PINMUX_AF('D', 10, AF2) + +/* TIMER0_BRKIN2 */ +#define TIMER0_BRKIN2_PD9 \ + GD32_PINMUX_AF('D', 9, AF2) + +/* TIMER0_BRKIN3 */ +#define TIMER0_BRKIN3_PC9 \ + GD32_PINMUX_AF('C', 9, AF1) + +/* TIMER0_CH0 */ +#define TIMER0_CH0_PB2 \ + GD32_PINMUX_AF('B', 2, AF1) +#define TIMER0_CH0_PC0 \ + GD32_PINMUX_AF('C', 0, AF1) +#define TIMER0_CH0_PC8 \ + GD32_PINMUX_AF('C', 8, AF1) + +/* TIMER0_CH1 */ +#define TIMER0_CH1_PA4 \ + GD32_PINMUX_AF('A', 4, AF1) +#define TIMER0_CH1_PE5 \ + GD32_PINMUX_AF('E', 5, AF1) + +/* TIMER0_CH2 */ +#define TIMER0_CH2_PA2 \ + GD32_PINMUX_AF('A', 2, AF1) + +/* TIMER0_CH3 */ +#define TIMER0_CH3_PA0 \ + GD32_PINMUX_AF('A', 0, AF1) + +/* TIMER0_MCH0 */ +#define TIMER0_MCH0_PB1 \ + GD32_PINMUX_AF('B', 1, AF1) +#define TIMER0_MCH0_PC7 \ + GD32_PINMUX_AF('C', 7, AF1) +#define TIMER0_MCH0_PF5 \ + GD32_PINMUX_AF('F', 5, AF1) + +/* TIMER0_MCH1 */ +#define TIMER0_MCH1_PA3 \ + GD32_PINMUX_AF('A', 3, AF1) +#define TIMER0_MCH1_PE4 \ + GD32_PINMUX_AF('E', 4, AF1) + +/* TIMER0_MCH2 */ +#define TIMER0_MCH2_PA1 \ + GD32_PINMUX_AF('A', 1, AF1) + +/* TIMER0_MCH3 */ +#define TIMER0_MCH3_PC1 \ + GD32_PINMUX_AF('C', 1, AF1) +#define TIMER0_MCH3_PD11 \ + GD32_PINMUX_AF('D', 11, AF1) + +/* TIMER19_BRKIN1 */ +#define TIMER19_BRKIN1_PA7 \ + GD32_PINMUX_AF('A', 7, AF3) + +/* TIMER19_BRKIN2 */ +#define TIMER19_BRKIN2_PA6 \ + GD32_PINMUX_AF('A', 6, AF2) + +/* TIMER19_BRKIN3 */ +#define TIMER19_BRKIN3_PA5 \ + GD32_PINMUX_AF('A', 5, AF2) + +/* TIMER19_CH0 */ +#define TIMER19_CH0_PB7 \ + GD32_PINMUX_AF('B', 7, AF1) +#define TIMER19_CH0_PC11 \ + GD32_PINMUX_AF('C', 11, AF2) +#define TIMER19_CH0_PD6 \ + GD32_PINMUX_AF('D', 6, AF2) +#define TIMER19_CH0_PE5 \ + GD32_PINMUX_AF('E', 5, AF2) + +/* TIMER19_CH1 */ +#define TIMER19_CH1_PB7 \ + GD32_PINMUX_AF('B', 7, AF2) +#define TIMER19_CH1_PC15 \ + GD32_PINMUX_AF('C', 15, AF2) +#define TIMER19_CH1_PD7 \ + GD32_PINMUX_AF('D', 7, AF2) +#define TIMER19_CH1_PF0 \ + GD32_PINMUX_AF('F', 0, AF1) + +/* TIMER19_CH2 */ +#define TIMER19_CH2_PC13 \ + GD32_PINMUX_AF('C', 13, AF1) + +/* TIMER19_MCH0 */ +#define TIMER19_MCH0_PC11 \ + GD32_PINMUX_AF('C', 11, AF1) +#define TIMER19_MCH0_PE4 \ + GD32_PINMUX_AF('E', 4, AF2) + +/* TIMER19_MCH1 */ +#define TIMER19_MCH1_PA7 \ + GD32_PINMUX_AF('A', 7, AF1) +#define TIMER19_MCH1_PC15 \ + GD32_PINMUX_AF('C', 15, AF1) + +/* TIMER19_MCH2 */ +#define TIMER19_MCH2_PE6 \ + GD32_PINMUX_AF('E', 6, AF2) + +/* TIMER1_CH0 */ +#define TIMER1_CH0_PE6 \ + GD32_PINMUX_AF('E', 6, AF1) + +/* TIMER1_CH1 */ +#define TIMER1_CH1_PA7 \ + GD32_PINMUX_AF('A', 7, AF2) + +/* TIMER1_CH2 */ +#define TIMER1_CH2_PB14 \ + GD32_PINMUX_AF('B', 14, AF1) +#define TIMER1_CH2_PD4 \ + GD32_PINMUX_AF('D', 4, AF2) + +/* TIMER1_CH3 */ +#define TIMER1_CH3_PA3 \ + GD32_PINMUX_AF('A', 3, AF2) + +/* TIMER1_ETI */ +#define TIMER1_ETI_PE6 \ + GD32_PINMUX_AF('E', 6, AF1) + +/* TIMER20_BRKIN0 */ +#define TIMER20_BRKIN0_PD11 \ + GD32_PINMUX_AF('D', 11, AF2) + +/* TIMER20_BRKIN1 */ +#define TIMER20_BRKIN1_PC7 \ + GD32_PINMUX_AF('C', 7, AF2) + +/* TIMER20_BRKIN2 */ +#define TIMER20_BRKIN2_PC8 \ + GD32_PINMUX_AF('C', 8, AF2) + +/* TIMER20_BRKIN3 */ +#define TIMER20_BRKIN3_PC9 \ + GD32_PINMUX_AF('C', 9, AF2) + +/* TIMER20_CH0 */ +#define TIMER20_CH0_PA11 \ + GD32_PINMUX_AF('A', 11, AF1) + +/* TIMER20_CH1 */ +#define TIMER20_CH1_PD0 \ + GD32_PINMUX_AF('D', 0, AF1) + +/* TIMER20_CH2 */ +#define TIMER20_CH2_PA9 \ + GD32_PINMUX_AF('A', 9, AF1) + +/* TIMER20_CH3 */ +#define TIMER20_CH3_PD4 \ + GD32_PINMUX_AF('D', 4, AF1) + +/* TIMER20_MCH0 */ +#define TIMER20_MCH0_PA10 \ + GD32_PINMUX_AF('A', 10, AF1) + +/* TIMER20_MCH1 */ +#define TIMER20_MCH1_PC12 \ + GD32_PINMUX_AF('C', 12, AF1) + +/* TIMER20_MCH2 */ +#define TIMER20_MCH2_PA8 \ + GD32_PINMUX_AF('A', 8, AF2) + +/* TIMER20_MCH3 */ +#define TIMER20_MCH3_PD3 \ + GD32_PINMUX_AF('D', 3, AF1) + +/* TIMER7_BRKIN0 */ +#define TIMER7_BRKIN0_PD8 \ + GD32_PINMUX_AF('D', 8, AF2) + +/* TIMER7_BRKIN1 */ +#define TIMER7_BRKIN1_PB5 \ + GD32_PINMUX_AF('B', 5, AF2) +#define TIMER7_BRKIN1_PB15 \ + GD32_PINMUX_AF('B', 15, AF2) + +/* TIMER7_BRKIN2 */ +#define TIMER7_BRKIN2_PB6 \ + GD32_PINMUX_AF('B', 6, AF2) +#define TIMER7_BRKIN2_PE10 \ + GD32_PINMUX_AF('E', 10, AF2) + +/* TIMER7_BRKIN3 */ +#define TIMER7_BRKIN3_PE9 \ + GD32_PINMUX_AF('E', 9, AF2) + +/* TIMER7_CH0 */ +#define TIMER7_CH0_PB8 \ + GD32_PINMUX_AF('B', 8, AF1) +#define TIMER7_CH0_PC10 \ + GD32_PINMUX_AF('C', 10, AF2) +#define TIMER7_CH0_PC12 \ + GD32_PINMUX_AF('C', 12, AF2) +#define TIMER7_CH0_PE13 \ + GD32_PINMUX_AF('E', 13, AF2) +#define TIMER7_CH0_PE14 \ + GD32_PINMUX_AF('E', 14, AF1) + +/* TIMER7_CH1 */ +#define TIMER7_CH1_PB8 \ + GD32_PINMUX_AF('B', 8, AF2) +#define TIMER7_CH1_PD0 \ + GD32_PINMUX_AF('D', 0, AF2) +#define TIMER7_CH1_PE12 \ + GD32_PINMUX_AF('E', 12, AF1) +#define TIMER7_CH1_PE14 \ + GD32_PINMUX_AF('E', 14, AF2) + +/* TIMER7_CH2 */ +#define TIMER7_CH2_PB4 \ + GD32_PINMUX_AF('B', 4, AF1) + +/* TIMER7_CH3 */ +#define TIMER7_CH3_PB2 \ + GD32_PINMUX_AF('B', 2, AF2) +#define TIMER7_CH3_PD7 \ + GD32_PINMUX_AF('D', 7, AF1) + +/* TIMER7_MCH0 */ +#define TIMER7_MCH0_PC10 \ + GD32_PINMUX_AF('C', 10, AF1) +#define TIMER7_MCH0_PE13 \ + GD32_PINMUX_AF('E', 13, AF1) + +/* TIMER7_MCH1 */ +#define TIMER7_MCH1_PE11 \ + GD32_PINMUX_AF('E', 11, AF1) + +/* TIMER7_MCH2 */ +#define TIMER7_MCH2_PB3 \ + GD32_PINMUX_AF('B', 3, AF1) + +/* TIMER7_MCH3 */ +#define TIMER7_MCH3_PB1 \ + GD32_PINMUX_AF('B', 1, AF2) +#define TIMER7_MCH3_PD6 \ + GD32_PINMUX_AF('D', 6, AF1) + +/* TIMER_ETI0 */ +#define TIMER_ETI0_PB13 \ + GD32_PINMUX_AF('B', 13, AF0) + +/* TIMER_ETI1 */ +#define TIMER_ETI1_PB6 \ + GD32_PINMUX_AF('B', 6, AF3) + +/* TIMER_ETI2 */ +#define TIMER_ETI2_PC15 \ + GD32_PINMUX_AF('C', 15, AF0) + +/* TIMRE19_BRKIN0 */ +#define TIMRE19_BRKIN0_PF2 \ + GD32_PINMUX_AF('F', 2, AF2) + +/* TRIGSEL_IN0 */ +#define TRIGSEL_IN0_PA1 \ + GD32_PINMUX_AF('A', 1, AF7) + +/* TRIGSEL_IN1 */ +#define TRIGSEL_IN1_PA2 \ + GD32_PINMUX_AF('A', 2, AF7) + +/* TRIGSEL_IN13 */ +#define TRIGSEL_IN13_PA11 \ + GD32_PINMUX_AF('A', 11, AF7) + +/* TRIGSEL_IN2 */ +#define TRIGSEL_IN2_PE13 \ + GD32_PINMUX_AF('E', 13, AF7) + +/* TRIGSEL_IN3 */ +#define TRIGSEL_IN3_PE14 \ + GD32_PINMUX_AF('E', 14, AF7) + +/* TRIGSEL_IN4 */ +#define TRIGSEL_IN4_PA8 \ + GD32_PINMUX_AF('A', 8, AF7) + +/* TRIGSEL_IN5 */ +#define TRIGSEL_IN5_PA9 \ + GD32_PINMUX_AF('A', 9, AF7) + +/* TRIGSEL_IN6 */ +#define TRIGSEL_IN6_PF2 \ + GD32_PINMUX_AF('F', 2, AF6) + +/* TRIGSEL_IN7 */ +#define TRIGSEL_IN7_PA7 \ + GD32_PINMUX_AF('A', 7, AF7) + +/* TRIGSEL_IN8 */ +#define TRIGSEL_IN8_PE11 \ + GD32_PINMUX_AF('E', 11, AF7) + +/* TRIGSEL_IN9 */ +#define TRIGSEL_IN9_PE12 \ + GD32_PINMUX_AF('E', 12, AF7) + +/* TRIGSEL_OUT0 */ +#define TRIGSEL_OUT0_PC10 \ + GD32_PINMUX_AF('C', 10, AF7) + +/* TRIGSEL_OUT1 */ +#define TRIGSEL_OUT1_PE5 \ + GD32_PINMUX_AF('E', 5, AF7) + +/* TRIGSEL_OUT2 */ +#define TRIGSEL_OUT2_PE4 \ + GD32_PINMUX_AF('E', 4, AF7) + +/* TRIGSEL_OUT3 */ +#define TRIGSEL_OUT3_PC11 \ + GD32_PINMUX_AF('C', 11, AF7) + +/* TRIGSEL_OUT4 */ +#define TRIGSEL_OUT4_PC13 \ + GD32_PINMUX_AF('C', 13, AF7) + +/* TRIGSEL_OUT5 */ +#define TRIGSEL_OUT5_PE6 \ + GD32_PINMUX_AF('E', 6, AF7) + +/* USART0_CTS */ +#define USART0_CTS_PC11 \ + GD32_PINMUX_AF('C', 11, AF5) +#define USART0_CTS_PD8 \ + GD32_PINMUX_AF('D', 8, AF5) + +/* USART0_DE */ +#define USART0_DE_PB15 \ + GD32_PINMUX_AF('B', 15, AF5) +#define USART0_DE_PC10 \ + GD32_PINMUX_AF('C', 10, AF5) + +/* USART0_RTS */ +#define USART0_RTS_PB15 \ + GD32_PINMUX_AF('B', 15, AF5) +#define USART0_RTS_PC10 \ + GD32_PINMUX_AF('C', 10, AF5) + +/* USART0_RX */ +#define USART0_RX_PA4 \ + GD32_PINMUX_AF('A', 4, AF5) +#define USART0_RX_PA11 \ + GD32_PINMUX_AF('A', 11, AF5) +#define USART0_RX_PB14 \ + GD32_PINMUX_AF('B', 14, AF5) + +/* USART0_TX */ +#define USART0_TX_PA3 \ + GD32_PINMUX_AF('A', 3, AF5) +#define USART0_TX_PA10 \ + GD32_PINMUX_AF('A', 10, AF5) +#define USART0_TX_PB13 \ + GD32_PINMUX_AF('B', 13, AF5) + +/* USART1_CTS */ +#define USART1_CTS_PD4 \ + GD32_PINMUX_AF('D', 4, AF5) +#define USART1_CTS_PD10 \ + GD32_PINMUX_AF('D', 10, AF5) +#define USART1_CTS_PF5 \ + GD32_PINMUX_AF('F', 5, AF5) + +/* USART1_DE */ +#define USART1_DE_PD3 \ + GD32_PINMUX_AF('D', 3, AF5) +#define USART1_DE_PD9 \ + GD32_PINMUX_AF('D', 9, AF5) + +/* USART1_RTS */ +#define USART1_RTS_PD3 \ + GD32_PINMUX_AF('D', 3, AF5) +#define USART1_RTS_PD9 \ + GD32_PINMUX_AF('D', 9, AF5) + +/* USART1_RX */ +#define USART1_RX_PD0 \ + GD32_PINMUX_AF('D', 0, AF5) +#define USART1_RX_PD8 \ + GD32_PINMUX_AF('D', 8, AF4) + +/* USART1_TX */ +#define USART1_TX_PB15 \ + GD32_PINMUX_AF('B', 15, AF4) +#define USART1_TX_PC12 \ + GD32_PINMUX_AF('C', 12, AF5) + +/* USART2_CK */ +#define USART2_CK_PA7 \ + GD32_PINMUX_AF('A', 7, AF5) + +/* USART2_CTS */ +#define USART2_CTS_PC1 \ + GD32_PINMUX_AF('C', 1, AF5) + +/* USART2_DE */ +#define USART2_DE_PF2 \ + GD32_PINMUX_AF('F', 2, AF5) + +/* USART2_RTS */ +#define USART2_RTS_PF2 \ + GD32_PINMUX_AF('F', 2, AF5) + +/* USART2_RX */ +#define USART2_RX_PA6 \ + GD32_PINMUX_AF('A', 6, AF5) + +/* USART2_TX */ +#define USART2_TX_PA5 \ + GD32_PINMUX_AF('A', 5, AF5) diff --git a/include/dt-bindings/pinctrl/gd32a503v(b-c-d)xx-pinctrl.h b/include/dt-bindings/pinctrl/gd32a503v(b-c-d)xx-pinctrl.h new file mode 100644 index 0000000..5c3e849 --- /dev/null +++ b/include/dt-bindings/pinctrl/gd32a503v(b-c-d)xx-pinctrl.h @@ -0,0 +1,1375 @@ +/* + * Autogenerated file + * + * SPDX-License-Identifier: Apache 2.0 + */ + +#include "gd32-af.h" + +/* ADC0_IN0 */ +#define ADC0_IN0_PC11 \ + GD32_PINMUX_AF('C', 11, ANALOG) + +/* ADC0_IN1 */ +#define ADC0_IN1_PC10 \ + GD32_PINMUX_AF('C', 10, ANALOG) + +/* ADC0_IN10 */ +#define ADC0_IN10_PA4 \ + GD32_PINMUX_AF('A', 4, ANALOG) + +/* ADC0_IN11 */ +#define ADC0_IN11_PA3 \ + GD32_PINMUX_AF('A', 3, ANALOG) + +/* ADC0_IN12 */ +#define ADC0_IN12_PE12 \ + GD32_PINMUX_AF('E', 12, ANALOG) + +/* ADC0_IN13 */ +#define ADC0_IN13_PE11 \ + GD32_PINMUX_AF('E', 11, ANALOG) + +/* ADC0_IN14 */ +#define ADC0_IN14_PE10 \ + GD32_PINMUX_AF('E', 10, ANALOG) + +/* ADC0_IN15 */ +#define ADC0_IN15_PE9 \ + GD32_PINMUX_AF('E', 9, ANALOG) + +/* ADC0_IN2 */ +#define ADC0_IN2_PD10 \ + GD32_PINMUX_AF('D', 10, ANALOG) + +/* ADC0_IN3 */ +#define ADC0_IN3_PD9 \ + GD32_PINMUX_AF('D', 9, ANALOG) + +/* ADC0_IN4 */ +#define ADC0_IN4_PB14 \ + GD32_PINMUX_AF('B', 14, ANALOG) + +/* ADC0_IN5 */ +#define ADC0_IN5_PB13 \ + GD32_PINMUX_AF('B', 13, ANALOG) + +/* ADC0_IN6 */ +#define ADC0_IN6_PE14 \ + GD32_PINMUX_AF('E', 14, ANALOG) + +/* ADC0_IN7 */ +#define ADC0_IN7_PE13 \ + GD32_PINMUX_AF('E', 13, ANALOG) + +/* ADC0_IN8 */ +#define ADC0_IN8_PB2 \ + GD32_PINMUX_AF('B', 2, ANALOG) +#define ADC0_IN8_PC7 \ + GD32_PINMUX_AF('C', 7, ANALOG) + +/* ADC0_IN9 */ +#define ADC0_IN9_PB1 \ + GD32_PINMUX_AF('B', 1, ANALOG) +#define ADC0_IN9_PC6 \ + GD32_PINMUX_AF('C', 6, ANALOG) + +/* ADC1_IN0 */ +#define ADC1_IN0_PA11 \ + GD32_PINMUX_AF('A', 11, ANALOG) + +/* ADC1_IN1 */ +#define ADC1_IN1_PA10 \ + GD32_PINMUX_AF('A', 10, ANALOG) + +/* ADC1_IN10 */ +#define ADC1_IN10_PD4 \ + GD32_PINMUX_AF('D', 4, ANALOG) + +/* ADC1_IN11 */ +#define ADC1_IN11_PD3 \ + GD32_PINMUX_AF('D', 3, ANALOG) + +/* ADC1_IN12 */ +#define ADC1_IN12_PD2 \ + GD32_PINMUX_AF('D', 2, ANALOG) + +/* ADC1_IN13 */ +#define ADC1_IN13_PD1 \ + GD32_PINMUX_AF('D', 1, ANALOG) + +/* ADC1_IN14 */ +#define ADC1_IN14_PB14 \ + GD32_PINMUX_AF('B', 14, ANALOG) +#define ADC1_IN14_PD15 \ + GD32_PINMUX_AF('D', 15, ANALOG) + +/* ADC1_IN15 */ +#define ADC1_IN15_PB13 \ + GD32_PINMUX_AF('B', 13, ANALOG) +#define ADC1_IN15_PD14 \ + GD32_PINMUX_AF('D', 14, ANALOG) + +/* ADC1_IN2 */ +#define ADC1_IN2_PA9 \ + GD32_PINMUX_AF('A', 9, ANALOG) + +/* ADC1_IN3 */ +#define ADC1_IN3_PA8 \ + GD32_PINMUX_AF('A', 8, ANALOG) + +/* ADC1_IN4 */ +#define ADC1_IN4_PD0 \ + GD32_PINMUX_AF('D', 0, ANALOG) + +/* ADC1_IN5 */ +#define ADC1_IN5_PC12 \ + GD32_PINMUX_AF('C', 12, ANALOG) + +/* ADC1_IN6 */ +#define ADC1_IN6_PC9 \ + GD32_PINMUX_AF('C', 9, ANALOG) + +/* ADC1_IN7 */ +#define ADC1_IN7_PC8 \ + GD32_PINMUX_AF('C', 8, ANALOG) + +/* ADC1_IN8 */ +#define ADC1_IN8_PC7 \ + GD32_PINMUX_AF('C', 7, ANALOG) + +/* ADC1_IN9 */ +#define ADC1_IN9_PC6 \ + GD32_PINMUX_AF('C', 6, ANALOG) + +/* ANALOG */ +#define ANALOG_PA0 \ + GD32_PINMUX_AF('A', 0, ANALOG) +#define ANALOG_PA1 \ + GD32_PINMUX_AF('A', 1, ANALOG) +#define ANALOG_PA2 \ + GD32_PINMUX_AF('A', 2, ANALOG) +#define ANALOG_PA3 \ + GD32_PINMUX_AF('A', 3, ANALOG) +#define ANALOG_PA4 \ + GD32_PINMUX_AF('A', 4, ANALOG) +#define ANALOG_PA5 \ + GD32_PINMUX_AF('A', 5, ANALOG) +#define ANALOG_PA6 \ + GD32_PINMUX_AF('A', 6, ANALOG) +#define ANALOG_PA7 \ + GD32_PINMUX_AF('A', 7, ANALOG) +#define ANALOG_PA8 \ + GD32_PINMUX_AF('A', 8, ANALOG) +#define ANALOG_PA9 \ + GD32_PINMUX_AF('A', 9, ANALOG) +#define ANALOG_PA10 \ + GD32_PINMUX_AF('A', 10, ANALOG) +#define ANALOG_PA11 \ + GD32_PINMUX_AF('A', 11, ANALOG) +#define ANALOG_PA12 \ + GD32_PINMUX_AF('A', 12, ANALOG) +#define ANALOG_PA13 \ + GD32_PINMUX_AF('A', 13, ANALOG) +#define ANALOG_PA14 \ + GD32_PINMUX_AF('A', 14, ANALOG) +#define ANALOG_PA15 \ + GD32_PINMUX_AF('A', 15, ANALOG) +#define ANALOG_PB0 \ + GD32_PINMUX_AF('B', 0, ANALOG) +#define ANALOG_PB1 \ + GD32_PINMUX_AF('B', 1, ANALOG) +#define ANALOG_PB2 \ + GD32_PINMUX_AF('B', 2, ANALOG) +#define ANALOG_PB3 \ + GD32_PINMUX_AF('B', 3, ANALOG) +#define ANALOG_PB4 \ + GD32_PINMUX_AF('B', 4, ANALOG) +#define ANALOG_PB5 \ + GD32_PINMUX_AF('B', 5, ANALOG) +#define ANALOG_PB6 \ + GD32_PINMUX_AF('B', 6, ANALOG) +#define ANALOG_PB7 \ + GD32_PINMUX_AF('B', 7, ANALOG) +#define ANALOG_PB8 \ + GD32_PINMUX_AF('B', 8, ANALOG) +#define ANALOG_PB9 \ + GD32_PINMUX_AF('B', 9, ANALOG) +#define ANALOG_PB10 \ + GD32_PINMUX_AF('B', 10, ANALOG) +#define ANALOG_PB11 \ + GD32_PINMUX_AF('B', 11, ANALOG) +#define ANALOG_PB12 \ + GD32_PINMUX_AF('B', 12, ANALOG) +#define ANALOG_PB13 \ + GD32_PINMUX_AF('B', 13, ANALOG) +#define ANALOG_PB14 \ + GD32_PINMUX_AF('B', 14, ANALOG) +#define ANALOG_PB15 \ + GD32_PINMUX_AF('B', 15, ANALOG) +#define ANALOG_PC0 \ + GD32_PINMUX_AF('C', 0, ANALOG) +#define ANALOG_PC1 \ + GD32_PINMUX_AF('C', 1, ANALOG) +#define ANALOG_PC2 \ + GD32_PINMUX_AF('C', 2, ANALOG) +#define ANALOG_PC3 \ + GD32_PINMUX_AF('C', 3, ANALOG) +#define ANALOG_PC4 \ + GD32_PINMUX_AF('C', 4, ANALOG) +#define ANALOG_PC5 \ + GD32_PINMUX_AF('C', 5, ANALOG) +#define ANALOG_PC6 \ + GD32_PINMUX_AF('C', 6, ANALOG) +#define ANALOG_PC7 \ + GD32_PINMUX_AF('C', 7, ANALOG) +#define ANALOG_PC8 \ + GD32_PINMUX_AF('C', 8, ANALOG) +#define ANALOG_PC9 \ + GD32_PINMUX_AF('C', 9, ANALOG) +#define ANALOG_PC10 \ + GD32_PINMUX_AF('C', 10, ANALOG) +#define ANALOG_PC11 \ + GD32_PINMUX_AF('C', 11, ANALOG) +#define ANALOG_PC12 \ + GD32_PINMUX_AF('C', 12, ANALOG) +#define ANALOG_PC13 \ + GD32_PINMUX_AF('C', 13, ANALOG) +#define ANALOG_PC14 \ + GD32_PINMUX_AF('C', 14, ANALOG) +#define ANALOG_PC15 \ + GD32_PINMUX_AF('C', 15, ANALOG) +#define ANALOG_PD0 \ + GD32_PINMUX_AF('D', 0, ANALOG) +#define ANALOG_PD1 \ + GD32_PINMUX_AF('D', 1, ANALOG) +#define ANALOG_PD2 \ + GD32_PINMUX_AF('D', 2, ANALOG) +#define ANALOG_PD3 \ + GD32_PINMUX_AF('D', 3, ANALOG) +#define ANALOG_PD4 \ + GD32_PINMUX_AF('D', 4, ANALOG) +#define ANALOG_PD5 \ + GD32_PINMUX_AF('D', 5, ANALOG) +#define ANALOG_PD6 \ + GD32_PINMUX_AF('D', 6, ANALOG) +#define ANALOG_PD7 \ + GD32_PINMUX_AF('D', 7, ANALOG) +#define ANALOG_PD8 \ + GD32_PINMUX_AF('D', 8, ANALOG) +#define ANALOG_PD9 \ + GD32_PINMUX_AF('D', 9, ANALOG) +#define ANALOG_PD10 \ + GD32_PINMUX_AF('D', 10, ANALOG) +#define ANALOG_PD11 \ + GD32_PINMUX_AF('D', 11, ANALOG) +#define ANALOG_PD12 \ + GD32_PINMUX_AF('D', 12, ANALOG) +#define ANALOG_PD13 \ + GD32_PINMUX_AF('D', 13, ANALOG) +#define ANALOG_PD14 \ + GD32_PINMUX_AF('D', 14, ANALOG) +#define ANALOG_PD15 \ + GD32_PINMUX_AF('D', 15, ANALOG) +#define ANALOG_PE0 \ + GD32_PINMUX_AF('E', 0, ANALOG) +#define ANALOG_PE1 \ + GD32_PINMUX_AF('E', 1, ANALOG) +#define ANALOG_PE2 \ + GD32_PINMUX_AF('E', 2, ANALOG) +#define ANALOG_PE3 \ + GD32_PINMUX_AF('E', 3, ANALOG) +#define ANALOG_PE4 \ + GD32_PINMUX_AF('E', 4, ANALOG) +#define ANALOG_PE5 \ + GD32_PINMUX_AF('E', 5, ANALOG) +#define ANALOG_PE6 \ + GD32_PINMUX_AF('E', 6, ANALOG) +#define ANALOG_PE7 \ + GD32_PINMUX_AF('E', 7, ANALOG) +#define ANALOG_PE8 \ + GD32_PINMUX_AF('E', 8, ANALOG) +#define ANALOG_PE9 \ + GD32_PINMUX_AF('E', 9, ANALOG) +#define ANALOG_PE10 \ + GD32_PINMUX_AF('E', 10, ANALOG) +#define ANALOG_PE11 \ + GD32_PINMUX_AF('E', 11, ANALOG) +#define ANALOG_PE12 \ + GD32_PINMUX_AF('E', 12, ANALOG) +#define ANALOG_PE13 \ + GD32_PINMUX_AF('E', 13, ANALOG) +#define ANALOG_PE14 \ + GD32_PINMUX_AF('E', 14, ANALOG) +#define ANALOG_PE15 \ + GD32_PINMUX_AF('E', 15, ANALOG) +#define ANALOG_PF0 \ + GD32_PINMUX_AF('F', 0, ANALOG) +#define ANALOG_PF1 \ + GD32_PINMUX_AF('F', 1, ANALOG) +#define ANALOG_PF2 \ + GD32_PINMUX_AF('F', 2, ANALOG) +#define ANALOG_PF3 \ + GD32_PINMUX_AF('F', 3, ANALOG) +#define ANALOG_PF4 \ + GD32_PINMUX_AF('F', 4, ANALOG) +#define ANALOG_PF5 \ + GD32_PINMUX_AF('F', 5, ANALOG) +#define ANALOG_PF6 \ + GD32_PINMUX_AF('F', 6, ANALOG) +#define ANALOG_PF7 \ + GD32_PINMUX_AF('F', 7, ANALOG) + +/* CAN0_RX */ +#define CAN0_RX_PA4 \ + GD32_PINMUX_AF('A', 4, AF6) +#define CAN0_RX_PB14 \ + GD32_PINMUX_AF('B', 14, AF6) +#define CAN0_RX_PF0 \ + GD32_PINMUX_AF('F', 0, AF6) + +/* CAN0_TX */ +#define CAN0_TX_PA3 \ + GD32_PINMUX_AF('A', 3, AF6) +#define CAN0_TX_PB13 \ + GD32_PINMUX_AF('B', 13, AF6) +#define CAN0_TX_PC15 \ + GD32_PINMUX_AF('C', 15, AF6) + +/* CAN1_RX */ +#define CAN1_RX_PD0 \ + GD32_PINMUX_AF('D', 0, AF6) +#define CAN1_RX_PD7 \ + GD32_PINMUX_AF('D', 7, AF6) + +/* CAN1_TX */ +#define CAN1_TX_PC12 \ + GD32_PINMUX_AF('C', 12, AF6) +#define CAN1_TX_PD6 \ + GD32_PINMUX_AF('D', 6, AF6) + +/* CK_OUT */ +#define CK_OUT_PC2 \ + GD32_PINMUX_AF('C', 2, AF0) +#define CK_OUT_PC13 \ + GD32_PINMUX_AF('C', 13, AF0) + +/* CK_OUT0 */ +#define CK_OUT0_PA1 \ + GD32_PINMUX_AF('A', 1, AF0) + +/* CMP_OUT */ +#define CMP_OUT_PB9 \ + GD32_PINMUX_AF('B', 9, AF7) +#define CMP_OUT_PF2 \ + GD32_PINMUX_AF('F', 2, AF7) + +/* DAC_OUT */ +#define DAC_OUT_PA7 \ + GD32_PINMUX_AF('A', 7, ANALOG) + +/* EVENTOUT */ +#define EVENTOUT_PA0 \ + GD32_PINMUX_AF('A', 0, AF9) +#define EVENTOUT_PA1 \ + GD32_PINMUX_AF('A', 1, AF9) +#define EVENTOUT_PA2 \ + GD32_PINMUX_AF('A', 2, AF9) +#define EVENTOUT_PA3 \ + GD32_PINMUX_AF('A', 3, AF9) +#define EVENTOUT_PA4 \ + GD32_PINMUX_AF('A', 4, AF9) +#define EVENTOUT_PA5 \ + GD32_PINMUX_AF('A', 5, AF9) +#define EVENTOUT_PA7 \ + GD32_PINMUX_AF('A', 7, AF9) +#define EVENTOUT_PA8 \ + GD32_PINMUX_AF('A', 8, AF9) +#define EVENTOUT_PA9 \ + GD32_PINMUX_AF('A', 9, AF9) +#define EVENTOUT_PA10 \ + GD32_PINMUX_AF('A', 10, AF9) +#define EVENTOUT_PA11 \ + GD32_PINMUX_AF('A', 11, AF9) +#define EVENTOUT_PA12 \ + GD32_PINMUX_AF('A', 12, AF9) +#define EVENTOUT_PA13 \ + GD32_PINMUX_AF('A', 13, AF9) +#define EVENTOUT_PA14 \ + GD32_PINMUX_AF('A', 14, AF9) +#define EVENTOUT_PA15 \ + GD32_PINMUX_AF('A', 15, AF9) +#define EVENTOUT_PB0 \ + GD32_PINMUX_AF('B', 0, AF9) +#define EVENTOUT_PB1 \ + GD32_PINMUX_AF('B', 1, AF9) +#define EVENTOUT_PB2 \ + GD32_PINMUX_AF('B', 2, AF9) +#define EVENTOUT_PB3 \ + GD32_PINMUX_AF('B', 3, AF9) +#define EVENTOUT_PB4 \ + GD32_PINMUX_AF('B', 4, AF9) +#define EVENTOUT_PB5 \ + GD32_PINMUX_AF('B', 5, AF9) +#define EVENTOUT_PB6 \ + GD32_PINMUX_AF('B', 6, AF9) +#define EVENTOUT_PB7 \ + GD32_PINMUX_AF('B', 7, AF9) +#define EVENTOUT_PB8 \ + GD32_PINMUX_AF('B', 8, AF9) +#define EVENTOUT_PB9 \ + GD32_PINMUX_AF('B', 9, AF9) +#define EVENTOUT_PB10 \ + GD32_PINMUX_AF('B', 10, AF9) +#define EVENTOUT_PB11 \ + GD32_PINMUX_AF('B', 11, AF9) +#define EVENTOUT_PB12 \ + GD32_PINMUX_AF('B', 12, AF9) +#define EVENTOUT_PB13 \ + GD32_PINMUX_AF('B', 13, AF9) +#define EVENTOUT_PB14 \ + GD32_PINMUX_AF('B', 14, AF9) +#define EVENTOUT_PB15 \ + GD32_PINMUX_AF('B', 15, AF9) +#define EVENTOUT_PC0 \ + GD32_PINMUX_AF('C', 0, AF9) +#define EVENTOUT_PC1 \ + GD32_PINMUX_AF('C', 1, AF9) +#define EVENTOUT_PC2 \ + GD32_PINMUX_AF('C', 2, AF9) +#define EVENTOUT_PC3 \ + GD32_PINMUX_AF('C', 3, AF9) +#define EVENTOUT_PC4 \ + GD32_PINMUX_AF('C', 4, AF9) +#define EVENTOUT_PC5 \ + GD32_PINMUX_AF('C', 5, AF9) +#define EVENTOUT_PC6 \ + GD32_PINMUX_AF('C', 6, AF9) +#define EVENTOUT_PC7 \ + GD32_PINMUX_AF('C', 7, AF9) +#define EVENTOUT_PC8 \ + GD32_PINMUX_AF('C', 8, AF9) +#define EVENTOUT_PC9 \ + GD32_PINMUX_AF('C', 9, AF9) +#define EVENTOUT_PC10 \ + GD32_PINMUX_AF('C', 10, AF9) +#define EVENTOUT_PC11 \ + GD32_PINMUX_AF('C', 11, AF9) +#define EVENTOUT_PC12 \ + GD32_PINMUX_AF('C', 12, AF9) +#define EVENTOUT_PC13 \ + GD32_PINMUX_AF('C', 13, AF9) +#define EVENTOUT_PC14 \ + GD32_PINMUX_AF('C', 14, AF9) +#define EVENTOUT_PC15 \ + GD32_PINMUX_AF('C', 15, AF9) +#define EVENTOUT_PD0 \ + GD32_PINMUX_AF('D', 0, AF9) +#define EVENTOUT_PD1 \ + GD32_PINMUX_AF('D', 1, AF9) +#define EVENTOUT_PD2 \ + GD32_PINMUX_AF('D', 2, AF9) +#define EVENTOUT_PD3 \ + GD32_PINMUX_AF('D', 3, AF9) +#define EVENTOUT_PD4 \ + GD32_PINMUX_AF('D', 4, AF9) +#define EVENTOUT_PD5 \ + GD32_PINMUX_AF('D', 5, AF9) +#define EVENTOUT_PD6 \ + GD32_PINMUX_AF('D', 6, AF9) +#define EVENTOUT_PD7 \ + GD32_PINMUX_AF('D', 7, AF9) +#define EVENTOUT_PD8 \ + GD32_PINMUX_AF('D', 8, AF9) +#define EVENTOUT_PD9 \ + GD32_PINMUX_AF('D', 9, AF9) +#define EVENTOUT_PD10 \ + GD32_PINMUX_AF('D', 10, AF9) +#define EVENTOUT_PD11 \ + GD32_PINMUX_AF('D', 11, AF9) +#define EVENTOUT_PD12 \ + GD32_PINMUX_AF('D', 12, AF9) +#define EVENTOUT_PD13 \ + GD32_PINMUX_AF('D', 13, AF9) +#define EVENTOUT_PD14 \ + GD32_PINMUX_AF('D', 14, AF9) +#define EVENTOUT_PD15 \ + GD32_PINMUX_AF('D', 15, AF9) +#define EVENTOUT_PE0 \ + GD32_PINMUX_AF('E', 0, AF9) +#define EVENTOUT_PE1 \ + GD32_PINMUX_AF('E', 1, AF9) +#define EVENTOUT_PE2 \ + GD32_PINMUX_AF('E', 2, AF9) +#define EVENTOUT_PE3 \ + GD32_PINMUX_AF('E', 3, AF9) +#define EVENTOUT_PE4 \ + GD32_PINMUX_AF('E', 4, AF9) +#define EVENTOUT_PE5 \ + GD32_PINMUX_AF('E', 5, AF9) +#define EVENTOUT_PE6 \ + GD32_PINMUX_AF('E', 6, AF9) +#define EVENTOUT_PE7 \ + GD32_PINMUX_AF('E', 7, AF9) +#define EVENTOUT_PE8 \ + GD32_PINMUX_AF('E', 8, AF9) +#define EVENTOUT_PE9 \ + GD32_PINMUX_AF('E', 9, AF9) +#define EVENTOUT_PE10 \ + GD32_PINMUX_AF('E', 10, AF9) +#define EVENTOUT_PE11 \ + GD32_PINMUX_AF('E', 11, AF9) +#define EVENTOUT_PE12 \ + GD32_PINMUX_AF('E', 12, AF9) +#define EVENTOUT_PE13 \ + GD32_PINMUX_AF('E', 13, AF9) +#define EVENTOUT_PE14 \ + GD32_PINMUX_AF('E', 14, AF9) +#define EVENTOUT_PE15 \ + GD32_PINMUX_AF('E', 15, AF9) +#define EVENTOUT_PF0 \ + GD32_PINMUX_AF('F', 0, AF9) +#define EVENTOUT_PF1 \ + GD32_PINMUX_AF('F', 1, AF9) +#define EVENTOUT_PF2 \ + GD32_PINMUX_AF('F', 2, AF9) +#define EVENTOUT_PF3 \ + GD32_PINMUX_AF('F', 3, AF9) +#define EVENTOUT_PF4 \ + GD32_PINMUX_AF('F', 4, AF9) +#define EVENTOUT_PF5 \ + GD32_PINMUX_AF('F', 5, AF9) +#define EVENTOUT_PF6 \ + GD32_PINMUX_AF('F', 6, AF9) +#define EVENTOUT_PF7 \ + GD32_PINMUX_AF('F', 7, AF9) + +/* I2C0_SCL */ +#define I2C0_SCL_PA10 \ + GD32_PINMUX_AF('A', 10, AF3) +#define I2C0_SCL_PA14 \ + GD32_PINMUX_AF('A', 14, AF3) +#define I2C0_SCL_PC11 \ + GD32_PINMUX_AF('C', 11, AF3) +#define I2C0_SCL_PF6 \ + GD32_PINMUX_AF('F', 6, AF3) + +/* I2C0_SDA */ +#define I2C0_SDA_PA11 \ + GD32_PINMUX_AF('A', 11, AF3) +#define I2C0_SDA_PA13 \ + GD32_PINMUX_AF('A', 13, AF3) +#define I2C0_SDA_PC10 \ + GD32_PINMUX_AF('C', 10, AF3) +#define I2C0_SDA_PF7 \ + GD32_PINMUX_AF('F', 7, AF3) + +/* I2C0_SMBA */ +#define I2C0_SMBA_PA12 \ + GD32_PINMUX_AF('A', 12, AF3) +#define I2C0_SMBA_PB5 \ + GD32_PINMUX_AF('B', 5, AF3) + +/* I2C1_SCL */ +#define I2C1_SCL_PB7 \ + GD32_PINMUX_AF('B', 7, AF5) +#define I2C1_SCL_PD6 \ + GD32_PINMUX_AF('D', 6, AF5) +#define I2C1_SCL_PE10 \ + GD32_PINMUX_AF('E', 10, AF5) + +/* I2C1_SDA */ +#define I2C1_SDA_PB8 \ + GD32_PINMUX_AF('B', 8, AF5) +#define I2C1_SDA_PD7 \ + GD32_PINMUX_AF('D', 7, AF5) +#define I2C1_SDA_PE11 \ + GD32_PINMUX_AF('E', 11, AF5) + +/* I2C1_SMBA */ +#define I2C1_SMBA_PB9 \ + GD32_PINMUX_AF('B', 9, AF5) +#define I2C1_SMBA_PD11 \ + GD32_PINMUX_AF('D', 11, AF5) +#define I2C1_SMBA_PE12 \ + GD32_PINMUX_AF('E', 12, AF5) + +/* I2S1_CK */ +#define I2S1_CK_PC6 \ + GD32_PINMUX_AF('C', 6, AF4) +#define I2S1_CK_PE5 \ + GD32_PINMUX_AF('E', 5, AF4) + +/* I2S1_MCK */ +#define I2S1_MCK_PC7 \ + GD32_PINMUX_AF('C', 7, AF4) +#define I2S1_MCK_PE6 \ + GD32_PINMUX_AF('E', 6, AF4) + +/* I2S1_SD */ +#define I2S1_SD_PA9 \ + GD32_PINMUX_AF('A', 9, AF4) +#define I2S1_SD_PB6 \ + GD32_PINMUX_AF('B', 6, AF5) +#define I2S1_SD_PD14 \ + GD32_PINMUX_AF('D', 14, AF4) + +/* I2S1_WS */ +#define I2S1_WS_PA8 \ + GD32_PINMUX_AF('A', 8, AF4) +#define I2S1_WS_PB5 \ + GD32_PINMUX_AF('B', 5, AF6) +#define I2S1_WS_PD1 \ + GD32_PINMUX_AF('D', 1, AF4) +#define I2S1_WS_PD10 \ + GD32_PINMUX_AF('D', 10, AF4) +#define I2S1_WS_PD13 \ + GD32_PINMUX_AF('D', 13, AF4) + +/* JTCK */ +#define JTCK_PB8 \ + GD32_PINMUX_AF('B', 8, AF0) + +/* JTDI */ +#define JTDI_PB7 \ + GD32_PINMUX_AF('B', 7, AF0) + +/* JTDO */ +#define JTDO_PB4 \ + GD32_PINMUX_AF('B', 4, AF0) + +/* JTMS */ +#define JTMS_PB9 \ + GD32_PINMUX_AF('B', 9, AF0) + +/* MFCOM_D0 */ +#define MFCOM_D0_PB4 \ + GD32_PINMUX_AF('B', 4, AF6) +#define MFCOM_D0_PE5 \ + GD32_PINMUX_AF('E', 5, AF6) +#define MFCOM_D0_PE7 \ + GD32_PINMUX_AF('E', 7, AF6) + +/* MFCOM_D1 */ +#define MFCOM_D1_PB3 \ + GD32_PINMUX_AF('B', 3, AF6) +#define MFCOM_D1_PE4 \ + GD32_PINMUX_AF('E', 4, AF6) +#define MFCOM_D1_PE8 \ + GD32_PINMUX_AF('E', 8, AF6) + +/* MFCOM_D2 */ +#define MFCOM_D2_PC11 \ + GD32_PINMUX_AF('C', 11, AF6) +#define MFCOM_D2_PE3 \ + GD32_PINMUX_AF('E', 3, AF12) + +/* MFCOM_D3 */ +#define MFCOM_D3_PC10 \ + GD32_PINMUX_AF('C', 10, AF6) +#define MFCOM_D3_PE2 \ + GD32_PINMUX_AF('E', 2, AF6) + +/* MFCOM_D4 */ +#define MFCOM_D4_PA9 \ + GD32_PINMUX_AF('A', 9, AF6) +#define MFCOM_D4_PA11 \ + GD32_PINMUX_AF('A', 11, AF6) +#define MFCOM_D4_PC13 \ + GD32_PINMUX_AF('C', 13, AF6) + +/* MFCOM_D5 */ +#define MFCOM_D5_PA8 \ + GD32_PINMUX_AF('A', 8, AF6) +#define MFCOM_D5_PA10 \ + GD32_PINMUX_AF('A', 10, AF6) +#define MFCOM_D5_PE6 \ + GD32_PINMUX_AF('E', 6, AF6) + +/* MFCOM_D6 */ +#define MFCOM_D6_PA9 \ + GD32_PINMUX_AF('A', 9, AF5) +#define MFCOM_D6_PE1 \ + GD32_PINMUX_AF('E', 1, AF6) +#define MFCOM_D6_PF0 \ + GD32_PINMUX_AF('F', 0, AF7) + +/* MFCOM_D7 */ +#define MFCOM_D7_PA8 \ + GD32_PINMUX_AF('A', 8, AF5) +#define MFCOM_D7_PC15 \ + GD32_PINMUX_AF('C', 15, AF7) +#define MFCOM_D7_PE0 \ + GD32_PINMUX_AF('E', 0, AF6) + +/* NJTRST */ +#define NJTRST_PB3 \ + GD32_PINMUX_AF('B', 3, AF0) + +/* SPI0_IO2 */ +#define SPI0_IO2_PB3 \ + GD32_PINMUX_AF('B', 3, AF4) +#define SPI0_IO2_PE15 \ + GD32_PINMUX_AF('E', 15, AF4) + +/* SPI0_IO3 */ +#define SPI0_IO3_PB4 \ + GD32_PINMUX_AF('B', 4, AF4) +#define SPI0_IO3_PB10 \ + GD32_PINMUX_AF('B', 10, AF4) + +/* SPI0_MISO */ +#define SPI0_MISO_PB5 \ + GD32_PINMUX_AF('B', 5, AF4) +#define SPI0_MISO_PE13 \ + GD32_PINMUX_AF('E', 13, AF4) +#define SPI0_MISO_PF5 \ + GD32_PINMUX_AF('F', 5, AF4) + +/* SPI0_MOSI */ +#define SPI0_MOSI_PA2 \ + GD32_PINMUX_AF('A', 2, AF4) +#define SPI0_MOSI_PB13 \ + GD32_PINMUX_AF('B', 13, AF4) +#define SPI0_MOSI_PD4 \ + GD32_PINMUX_AF('D', 4, AF4) + +/* SPI0_NSS */ +#define SPI0_NSS_PA1 \ + GD32_PINMUX_AF('A', 1, AF4) +#define SPI0_NSS_PB14 \ + GD32_PINMUX_AF('B', 14, AF3) +#define SPI0_NSS_PD2 \ + GD32_PINMUX_AF('D', 2, AF4) +#define SPI0_NSS_PD3 \ + GD32_PINMUX_AF('D', 3, AF4) + +/* SPI0_SCK */ +#define SPI0_SCK_PB6 \ + GD32_PINMUX_AF('B', 6, AF4) +#define SPI0_SCK_PC0 \ + GD32_PINMUX_AF('C', 0, AF4) +#define SPI0_SCK_PE14 \ + GD32_PINMUX_AF('E', 14, AF4) + +/* SPI1_MISO */ +#define SPI1_MISO_PD15 \ + GD32_PINMUX_AF('D', 15, AF4) +#define SPI1_MISO_PE4 \ + GD32_PINMUX_AF('E', 4, AF4) + +/* SPI1_MOSI */ +#define SPI1_MOSI_PA9 \ + GD32_PINMUX_AF('A', 9, AF4) +#define SPI1_MOSI_PB6 \ + GD32_PINMUX_AF('B', 6, AF5) +#define SPI1_MOSI_PD14 \ + GD32_PINMUX_AF('D', 14, AF4) + +/* SPI1_NSS */ +#define SPI1_NSS_PA8 \ + GD32_PINMUX_AF('A', 8, AF4) +#define SPI1_NSS_PB5 \ + GD32_PINMUX_AF('B', 5, AF5) +#define SPI1_NSS_PD1 \ + GD32_PINMUX_AF('D', 1, AF4) +#define SPI1_NSS_PD10 \ + GD32_PINMUX_AF('D', 10, AF4) +#define SPI1_NSS_PD13 \ + GD32_PINMUX_AF('D', 13, AF4) + +/* SPI1_SCK */ +#define SPI1_SCK_PC6 \ + GD32_PINMUX_AF('C', 6, AF4) +#define SPI1_SCK_PE5 \ + GD32_PINMUX_AF('E', 5, AF4) + +/* SWCLK */ +#define SWCLK_PB8 \ + GD32_PINMUX_AF('B', 8, AF0) + +/* SWDIO */ +#define SWDIO_PB9 \ + GD32_PINMUX_AF('B', 9, AF0) + +/* TIMER0_BRKIN0 */ +#define TIMER0_BRKIN0_PA8 \ + GD32_PINMUX_AF('A', 8, AF1) +#define TIMER0_BRKIN0_PD5 \ + GD32_PINMUX_AF('D', 5, AF7) +#define TIMER0_BRKIN0_PF2 \ + GD32_PINMUX_AF('F', 2, AF1) + +/* TIMER0_BRKIN1 */ +#define TIMER0_BRKIN1_PD10 \ + GD32_PINMUX_AF('D', 10, AF2) +#define TIMER0_BRKIN1_PF1 \ + GD32_PINMUX_AF('F', 1, AF1) + +/* TIMER0_BRKIN2 */ +#define TIMER0_BRKIN2_PD9 \ + GD32_PINMUX_AF('D', 9, AF2) +#define TIMER0_BRKIN2_PF4 \ + GD32_PINMUX_AF('F', 4, AF2) + +/* TIMER0_BRKIN3 */ +#define TIMER0_BRKIN3_PC9 \ + GD32_PINMUX_AF('C', 9, AF1) +#define TIMER0_BRKIN3_PF3 \ + GD32_PINMUX_AF('F', 3, AF2) + +/* TIMER0_CH0 */ +#define TIMER0_CH0_PB2 \ + GD32_PINMUX_AF('B', 2, AF1) +#define TIMER0_CH0_PC0 \ + GD32_PINMUX_AF('C', 0, AF1) +#define TIMER0_CH0_PC8 \ + GD32_PINMUX_AF('C', 8, AF1) + +/* TIMER0_CH1 */ +#define TIMER0_CH1_PA4 \ + GD32_PINMUX_AF('A', 4, AF1) +#define TIMER0_CH1_PC6 \ + GD32_PINMUX_AF('C', 6, AF1) +#define TIMER0_CH1_PE5 \ + GD32_PINMUX_AF('E', 5, AF1) + +/* TIMER0_CH2 */ +#define TIMER0_CH2_PA2 \ + GD32_PINMUX_AF('A', 2, AF1) +#define TIMER0_CH2_PD14 \ + GD32_PINMUX_AF('D', 14, AF1) + +/* TIMER0_CH3 */ +#define TIMER0_CH3_PA0 \ + GD32_PINMUX_AF('A', 0, AF1) +#define TIMER0_CH3_PD12 \ + GD32_PINMUX_AF('D', 12, AF1) + +/* TIMER0_MCH0 */ +#define TIMER0_MCH0_PB1 \ + GD32_PINMUX_AF('B', 1, AF1) +#define TIMER0_MCH0_PC7 \ + GD32_PINMUX_AF('C', 7, AF1) +#define TIMER0_MCH0_PF5 \ + GD32_PINMUX_AF('F', 5, AF1) + +/* TIMER0_MCH1 */ +#define TIMER0_MCH1_PA3 \ + GD32_PINMUX_AF('A', 3, AF1) +#define TIMER0_MCH1_PD15 \ + GD32_PINMUX_AF('D', 15, AF1) +#define TIMER0_MCH1_PE4 \ + GD32_PINMUX_AF('E', 4, AF1) + +/* TIMER0_MCH2 */ +#define TIMER0_MCH2_PA1 \ + GD32_PINMUX_AF('A', 1, AF1) +#define TIMER0_MCH2_PD13 \ + GD32_PINMUX_AF('D', 13, AF1) + +/* TIMER0_MCH3 */ +#define TIMER0_MCH3_PC1 \ + GD32_PINMUX_AF('C', 1, AF1) +#define TIMER0_MCH3_PD11 \ + GD32_PINMUX_AF('D', 11, AF1) + +/* TIMER19_BRKIN0 */ +#define TIMER19_BRKIN0_PC14 \ + GD32_PINMUX_AF('C', 14, AF2) + +/* TIMER19_BRKIN1 */ +#define TIMER19_BRKIN1_PA7 \ + GD32_PINMUX_AF('A', 7, AF3) +#define TIMER19_BRKIN1_PF1 \ + GD32_PINMUX_AF('F', 1, AF2) + +/* TIMER19_BRKIN2 */ +#define TIMER19_BRKIN2_PA6 \ + GD32_PINMUX_AF('A', 6, AF2) +#define TIMER19_BRKIN2_PE8 \ + GD32_PINMUX_AF('E', 8, AF2) + +/* TIMER19_BRKIN3 */ +#define TIMER19_BRKIN3_PA5 \ + GD32_PINMUX_AF('A', 5, AF2) +#define TIMER19_BRKIN3_PE7 \ + GD32_PINMUX_AF('E', 7, AF2) + +/* TIMER19_CH0 */ +#define TIMER19_CH0_PB0 \ + GD32_PINMUX_AF('B', 0, AF1) +#define TIMER19_CH0_PB7 \ + GD32_PINMUX_AF('B', 7, AF1) +#define TIMER19_CH0_PC5 \ + GD32_PINMUX_AF('C', 5, AF2) +#define TIMER19_CH0_PC11 \ + GD32_PINMUX_AF('C', 11, AF2) +#define TIMER19_CH0_PD6 \ + GD32_PINMUX_AF('D', 6, AF2) +#define TIMER19_CH0_PE5 \ + GD32_PINMUX_AF('E', 5, AF2) + +/* TIMER19_CH1 */ +#define TIMER19_CH1_PB0 \ + GD32_PINMUX_AF('B', 0, AF2) +#define TIMER19_CH1_PB7 \ + GD32_PINMUX_AF('B', 7, AF2) +#define TIMER19_CH1_PC4 \ + GD32_PINMUX_AF('C', 4, AF1) +#define TIMER19_CH1_PC15 \ + GD32_PINMUX_AF('C', 15, AF2) +#define TIMER19_CH1_PD7 \ + GD32_PINMUX_AF('D', 7, AF2) +#define TIMER19_CH1_PF0 \ + GD32_PINMUX_AF('F', 0, AF1) + +/* TIMER19_CH2 */ +#define TIMER19_CH2_PC3 \ + GD32_PINMUX_AF('C', 3, AF1) +#define TIMER19_CH2_PC13 \ + GD32_PINMUX_AF('C', 13, AF1) + +/* TIMER19_CH3 */ +#define TIMER19_CH3_PB10 \ + GD32_PINMUX_AF('B', 10, AF2) +#define TIMER19_CH3_PE3 \ + GD32_PINMUX_AF('E', 3, AF0) + +/* TIMER19_MCH0 */ +#define TIMER19_MCH0_PC5 \ + GD32_PINMUX_AF('C', 5, AF1) +#define TIMER19_MCH0_PC11 \ + GD32_PINMUX_AF('C', 11, AF1) +#define TIMER19_MCH0_PE4 \ + GD32_PINMUX_AF('E', 4, AF2) + +/* TIMER19_MCH1 */ +#define TIMER19_MCH1_PA7 \ + GD32_PINMUX_AF('A', 7, AF1) +#define TIMER19_MCH1_PC15 \ + GD32_PINMUX_AF('C', 15, AF1) + +/* TIMER19_MCH2 */ +#define TIMER19_MCH2_PC2 \ + GD32_PINMUX_AF('C', 2, AF1) +#define TIMER19_MCH2_PE6 \ + GD32_PINMUX_AF('E', 6, AF2) + +/* TIMER19_MCH3 */ +#define TIMER19_MCH3_PE2 \ + GD32_PINMUX_AF('E', 2, AF2) +#define TIMER19_MCH3_PE15 \ + GD32_PINMUX_AF('E', 15, AF2) + +/* TIMER1_CH0 */ +#define TIMER1_CH0_PE6 \ + GD32_PINMUX_AF('E', 6, AF1) + +/* TIMER1_CH1 */ +#define TIMER1_CH1_PA7 \ + GD32_PINMUX_AF('A', 7, AF2) + +/* TIMER1_CH2 */ +#define TIMER1_CH2_PB14 \ + GD32_PINMUX_AF('B', 14, AF1) +#define TIMER1_CH2_PD4 \ + GD32_PINMUX_AF('D', 4, AF2) + +/* TIMER1_CH3 */ +#define TIMER1_CH3_PA3 \ + GD32_PINMUX_AF('A', 3, AF2) +#define TIMER1_CH3_PB11 \ + GD32_PINMUX_AF('B', 11, AF2) + +/* TIMER1_ETI */ +#define TIMER1_ETI_PE6 \ + GD32_PINMUX_AF('E', 6, AF1) + +/* TIMER20_BRKIN0 */ +#define TIMER20_BRKIN0_PD11 \ + GD32_PINMUX_AF('D', 11, AF2) +#define TIMER20_BRKIN0_PD12 \ + GD32_PINMUX_AF('D', 12, AF2) + +/* TIMER20_BRKIN1 */ +#define TIMER20_BRKIN1_PC7 \ + GD32_PINMUX_AF('C', 7, AF2) +#define TIMER20_BRKIN1_PD5 \ + GD32_PINMUX_AF('D', 5, AF12) + +/* TIMER20_BRKIN2 */ +#define TIMER20_BRKIN2_PC8 \ + GD32_PINMUX_AF('C', 8, AF2) +#define TIMER20_BRKIN2_PE0 \ + GD32_PINMUX_AF('E', 0, AF1) + +/* TIMER20_BRKIN3 */ +#define TIMER20_BRKIN3_PC9 \ + GD32_PINMUX_AF('C', 9, AF2) +#define TIMER20_BRKIN3_PE1 \ + GD32_PINMUX_AF('E', 1, AF1) + +/* TIMER20_CH0 */ +#define TIMER20_CH0_PA11 \ + GD32_PINMUX_AF('A', 11, AF1) +#define TIMER20_CH0_PA15 \ + GD32_PINMUX_AF('A', 15, AF1) + +/* TIMER20_CH1 */ +#define TIMER20_CH1_PA13 \ + GD32_PINMUX_AF('A', 13, AF1) +#define TIMER20_CH1_PD0 \ + GD32_PINMUX_AF('D', 0, AF1) + +/* TIMER20_CH2 */ +#define TIMER20_CH2_PA9 \ + GD32_PINMUX_AF('A', 9, AF1) +#define TIMER20_CH2_PB12 \ + GD32_PINMUX_AF('B', 12, AF1) + +/* TIMER20_CH3 */ +#define TIMER20_CH3_PB10 \ + GD32_PINMUX_AF('B', 10, AF1) +#define TIMER20_CH3_PD4 \ + GD32_PINMUX_AF('D', 4, AF1) + +/* TIMER20_MCH0 */ +#define TIMER20_MCH0_PA10 \ + GD32_PINMUX_AF('A', 10, AF1) +#define TIMER20_MCH0_PA14 \ + GD32_PINMUX_AF('A', 14, AF1) + +/* TIMER20_MCH1 */ +#define TIMER20_MCH1_PA12 \ + GD32_PINMUX_AF('A', 12, AF1) +#define TIMER20_MCH1_PC12 \ + GD32_PINMUX_AF('C', 12, AF1) + +/* TIMER20_MCH2 */ +#define TIMER20_MCH2_PA8 \ + GD32_PINMUX_AF('A', 8, AF2) +#define TIMER20_MCH2_PB11 \ + GD32_PINMUX_AF('B', 11, AF1) + +/* TIMER20_MCH3 */ +#define TIMER20_MCH3_PD3 \ + GD32_PINMUX_AF('D', 3, AF1) +#define TIMER20_MCH3_PE15 \ + GD32_PINMUX_AF('E', 15, AF1) + +/* TIMER7_BRKIN0 */ +#define TIMER7_BRKIN0_PD5 \ + GD32_PINMUX_AF('D', 5, AF12) +#define TIMER7_BRKIN0_PD8 \ + GD32_PINMUX_AF('D', 8, AF2) + +/* TIMER7_BRKIN1 */ +#define TIMER7_BRKIN1_PB5 \ + GD32_PINMUX_AF('B', 5, AF2) +#define TIMER7_BRKIN1_PB15 \ + GD32_PINMUX_AF('B', 15, AF2) + +/* TIMER7_BRKIN2 */ +#define TIMER7_BRKIN2_PB6 \ + GD32_PINMUX_AF('B', 6, AF2) +#define TIMER7_BRKIN2_PE10 \ + GD32_PINMUX_AF('E', 10, AF2) + +/* TIMER7_BRKIN3 */ +#define TIMER7_BRKIN3_PE0 \ + GD32_PINMUX_AF('E', 0, AF2) +#define TIMER7_BRKIN3_PE9 \ + GD32_PINMUX_AF('E', 9, AF2) + +/* TIMER7_CH0 */ +#define TIMER7_CH0_PB8 \ + GD32_PINMUX_AF('B', 8, AF1) +#define TIMER7_CH0_PC10 \ + GD32_PINMUX_AF('C', 10, AF2) +#define TIMER7_CH0_PC12 \ + GD32_PINMUX_AF('C', 12, AF2) +#define TIMER7_CH0_PE13 \ + GD32_PINMUX_AF('E', 13, AF2) +#define TIMER7_CH0_PE14 \ + GD32_PINMUX_AF('E', 14, AF1) + +/* TIMER7_CH1 */ +#define TIMER7_CH1_PB8 \ + GD32_PINMUX_AF('B', 8, AF2) +#define TIMER7_CH1_PD0 \ + GD32_PINMUX_AF('D', 0, AF2) +#define TIMER7_CH1_PD2 \ + GD32_PINMUX_AF('D', 2, AF1) +#define TIMER7_CH1_PE12 \ + GD32_PINMUX_AF('E', 12, AF1) +#define TIMER7_CH1_PE14 \ + GD32_PINMUX_AF('E', 14, AF2) + +/* TIMER7_CH2 */ +#define TIMER7_CH2_PB4 \ + GD32_PINMUX_AF('B', 4, AF1) +#define TIMER7_CH2_PE8 \ + GD32_PINMUX_AF('E', 8, AF1) + +/* TIMER7_CH3 */ +#define TIMER7_CH3_PB2 \ + GD32_PINMUX_AF('B', 2, AF2) +#define TIMER7_CH3_PD7 \ + GD32_PINMUX_AF('D', 7, AF1) + +/* TIMER7_MCH0 */ +#define TIMER7_MCH0_PC10 \ + GD32_PINMUX_AF('C', 10, AF1) +#define TIMER7_MCH0_PE13 \ + GD32_PINMUX_AF('E', 13, AF1) + +/* TIMER7_MCH1 */ +#define TIMER7_MCH1_PD1 \ + GD32_PINMUX_AF('D', 1, AF1) +#define TIMER7_MCH1_PE11 \ + GD32_PINMUX_AF('E', 11, AF1) + +/* TIMER7_MCH2 */ +#define TIMER7_MCH2_PB3 \ + GD32_PINMUX_AF('B', 3, AF1) +#define TIMER7_MCH2_PE7 \ + GD32_PINMUX_AF('E', 7, AF1) + +/* TIMER7_MCH3 */ +#define TIMER7_MCH3_PB1 \ + GD32_PINMUX_AF('B', 1, AF2) +#define TIMER7_MCH3_PD6 \ + GD32_PINMUX_AF('D', 6, AF1) + +/* TIMER_ETI0 */ +#define TIMER_ETI0_PB13 \ + GD32_PINMUX_AF('B', 13, AF0) + +/* TIMER_ETI1 */ +#define TIMER_ETI1_PB6 \ + GD32_PINMUX_AF('B', 6, AF3) + +/* TIMER_ETI2 */ +#define TIMER_ETI2_PC15 \ + GD32_PINMUX_AF('C', 15, AF0) + +/* TIMRE19_BRKIN0 */ +#define TIMRE19_BRKIN0_PF2 \ + GD32_PINMUX_AF('F', 2, AF2) + +/* TRIGSEL_IN0 */ +#define TRIGSEL_IN0_PA1 \ + GD32_PINMUX_AF('A', 1, AF7) + +/* TRIGSEL_IN1 */ +#define TRIGSEL_IN1_PA2 \ + GD32_PINMUX_AF('A', 2, AF7) + +/* TRIGSEL_IN10 */ +#define TRIGSEL_IN10_PB11 \ + GD32_PINMUX_AF('B', 11, AF7) + +/* TRIGSEL_IN11 */ +#define TRIGSEL_IN11_PB12 \ + GD32_PINMUX_AF('B', 12, AF7) + +/* TRIGSEL_IN12 */ +#define TRIGSEL_IN12_PA15 \ + GD32_PINMUX_AF('A', 15, AF7) + +/* TRIGSEL_IN13 */ +#define TRIGSEL_IN13_PA11 \ + GD32_PINMUX_AF('A', 11, AF7) + +/* TRIGSEL_IN2 */ +#define TRIGSEL_IN2_PE13 \ + GD32_PINMUX_AF('E', 13, AF7) + +/* TRIGSEL_IN3 */ +#define TRIGSEL_IN3_PE14 \ + GD32_PINMUX_AF('E', 14, AF7) + +/* TRIGSEL_IN4 */ +#define TRIGSEL_IN4_PA8 \ + GD32_PINMUX_AF('A', 8, AF7) + +/* TRIGSEL_IN5 */ +#define TRIGSEL_IN5_PA9 \ + GD32_PINMUX_AF('A', 9, AF7) + +/* TRIGSEL_IN6 */ +#define TRIGSEL_IN6_PF2 \ + GD32_PINMUX_AF('F', 2, AF6) + +/* TRIGSEL_IN7 */ +#define TRIGSEL_IN7_PA7 \ + GD32_PINMUX_AF('A', 7, AF7) + +/* TRIGSEL_IN8 */ +#define TRIGSEL_IN8_PE11 \ + GD32_PINMUX_AF('E', 11, AF7) + +/* TRIGSEL_IN9 */ +#define TRIGSEL_IN9_PE12 \ + GD32_PINMUX_AF('E', 12, AF7) + +/* TRIGSEL_OUT0 */ +#define TRIGSEL_OUT0_PC10 \ + GD32_PINMUX_AF('C', 10, AF7) + +/* TRIGSEL_OUT1 */ +#define TRIGSEL_OUT1_PE5 \ + GD32_PINMUX_AF('E', 5, AF7) + +/* TRIGSEL_OUT2 */ +#define TRIGSEL_OUT2_PE4 \ + GD32_PINMUX_AF('E', 4, AF7) + +/* TRIGSEL_OUT3 */ +#define TRIGSEL_OUT3_PC11 \ + GD32_PINMUX_AF('C', 11, AF7) + +/* TRIGSEL_OUT4 */ +#define TRIGSEL_OUT4_PC13 \ + GD32_PINMUX_AF('C', 13, AF7) + +/* TRIGSEL_OUT5 */ +#define TRIGSEL_OUT5_PE6 \ + GD32_PINMUX_AF('E', 6, AF7) + +/* TRIGSEL_OUT6 */ +#define TRIGSEL_OUT6_PE3 \ + GD32_PINMUX_AF('E', 3, AF12) + +/* TRIGSEL_OUT7 */ +#define TRIGSEL_OUT7_PE2 \ + GD32_PINMUX_AF('E', 2, AF7) + +/* USART0_CK */ +#define USART0_CK_PA12 \ + GD32_PINMUX_AF('A', 12, AF5) + +/* USART0_CTS */ +#define USART0_CTS_PC11 \ + GD32_PINMUX_AF('C', 11, AF5) +#define USART0_CTS_PD8 \ + GD32_PINMUX_AF('D', 8, AF5) + +/* USART0_DE */ +#define USART0_DE_PB15 \ + GD32_PINMUX_AF('B', 15, AF5) +#define USART0_DE_PC10 \ + GD32_PINMUX_AF('C', 10, AF5) + +/* USART0_RTS */ +#define USART0_RTS_PB15 \ + GD32_PINMUX_AF('B', 15, AF5) +#define USART0_RTS_PC10 \ + GD32_PINMUX_AF('C', 10, AF5) + +/* USART0_RX */ +#define USART0_RX_PA4 \ + GD32_PINMUX_AF('A', 4, AF5) +#define USART0_RX_PA11 \ + GD32_PINMUX_AF('A', 11, AF5) +#define USART0_RX_PB14 \ + GD32_PINMUX_AF('B', 14, AF5) + +/* USART0_TX */ +#define USART0_TX_PA3 \ + GD32_PINMUX_AF('A', 3, AF5) +#define USART0_TX_PA10 \ + GD32_PINMUX_AF('A', 10, AF5) +#define USART0_TX_PB13 \ + GD32_PINMUX_AF('B', 13, AF5) + +/* USART1_CK */ +#define USART1_CK_PD5 \ + GD32_PINMUX_AF('D', 5, AF12) + +/* USART1_CTS */ +#define USART1_CTS_PD4 \ + GD32_PINMUX_AF('D', 4, AF5) +#define USART1_CTS_PD10 \ + GD32_PINMUX_AF('D', 10, AF5) +#define USART1_CTS_PE3 \ + GD32_PINMUX_AF('E', 3, AF12) +#define USART1_CTS_PF5 \ + GD32_PINMUX_AF('F', 5, AF5) + +/* USART1_DE */ +#define USART1_DE_PD3 \ + GD32_PINMUX_AF('D', 3, AF5) +#define USART1_DE_PD9 \ + GD32_PINMUX_AF('D', 9, AF5) +#define USART1_DE_PE2 \ + GD32_PINMUX_AF('E', 2, AF5) + +/* USART1_RTS */ +#define USART1_RTS_PD3 \ + GD32_PINMUX_AF('D', 3, AF5) +#define USART1_RTS_PD9 \ + GD32_PINMUX_AF('D', 9, AF5) +#define USART1_RTS_PE2 \ + GD32_PINMUX_AF('E', 2, AF5) + +/* USART1_RX */ +#define USART1_RX_PC3 \ + GD32_PINMUX_AF('C', 3, AF5) +#define USART1_RX_PD0 \ + GD32_PINMUX_AF('D', 0, AF5) +#define USART1_RX_PD8 \ + GD32_PINMUX_AF('D', 8, AF4) + +/* USART1_TX */ +#define USART1_TX_PB15 \ + GD32_PINMUX_AF('B', 15, AF4) +#define USART1_TX_PC2 \ + GD32_PINMUX_AF('C', 2, AF5) +#define USART1_TX_PC12 \ + GD32_PINMUX_AF('C', 12, AF5) + +/* USART2_CK */ +#define USART2_CK_PA7 \ + GD32_PINMUX_AF('A', 7, AF5) + +/* USART2_CTS */ +#define USART2_CTS_PB10 \ + GD32_PINMUX_AF('B', 10, AF5) +#define USART2_CTS_PC1 \ + GD32_PINMUX_AF('C', 1, AF5) +#define USART2_CTS_PC5 \ + GD32_PINMUX_AF('C', 5, AF5) + +/* USART2_DE */ +#define USART2_DE_PC4 \ + GD32_PINMUX_AF('C', 4, AF5) +#define USART2_DE_PE15 \ + GD32_PINMUX_AF('E', 15, AF5) +#define USART2_DE_PF2 \ + GD32_PINMUX_AF('F', 2, AF5) + +/* USART2_RTS */ +#define USART2_RTS_PC4 \ + GD32_PINMUX_AF('C', 4, AF5) +#define USART2_RTS_PE15 \ + GD32_PINMUX_AF('E', 15, AF5) +#define USART2_RTS_PF2 \ + GD32_PINMUX_AF('F', 2, AF5) + +/* USART2_RX */ +#define USART2_RX_PA6 \ + GD32_PINMUX_AF('A', 6, AF5) +#define USART2_RX_PE1 \ + GD32_PINMUX_AF('E', 1, AF5) +#define USART2_RX_PF4 \ + GD32_PINMUX_AF('F', 4, AF5) + +/* USART2_TX */ +#define USART2_TX_PA5 \ + GD32_PINMUX_AF('A', 5, AF5) +#define USART2_TX_PE0 \ + GD32_PINMUX_AF('E', 0, AF5) +#define USART2_TX_PF3 \ + GD32_PINMUX_AF('F', 3, AF5) diff --git a/pinconfigs/gd32a503xx.yml b/pinconfigs/gd32a503xx.yml new file mode 100644 index 0000000..aa0f936 --- /dev/null +++ b/pinconfigs/gd32a503xx.yml @@ -0,0 +1,722 @@ +# GD32A503XX pin definitions +# +# Sources: +# - GD32A503XX Datasheet (Revision 1.3) +# +# Pin codes: +# +# - 32 pins: K +# - 48 pins: C +# - 64 pins: R +# - 100 pins: V +# +# Memory codes: +# +# - 128Kb Flash, 24Kb SRAM: B +# - 256Kb Flash, 32Kb SRAM: C +# - 384Kb Flash, 48Kb SRAM: D +# +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache 2.0 + +model: af + +series: gd32a503 + +variants: + - pincode: K + memories: [B, C] + - pincode: C + memories: [B, C] + - pincode: R + memories: [B, C, D] + - pincode: V + memories: [B, C, D] + +pins: + PA0: + pincodes: [K, C, R, V] + afs: + TIMER0_CH3: 1 + EVENTOUT: 9 + PA1: + pincodes: [K, C, R, V] + afs: + CK_OUT0: 0 + TIMER0_MCH2: 1 + SPI0_NSS: 4 + TRIGSEL_IN0: 7 + EVENTOUT: 9 + PA2: + pincodes: [K, C, R, V] + afs: + TIMER0_CH2: 1 + SPI0_MOSI: 4 + TRIGSEL_IN1: 7 + EVENTOUT: 9 + PA3: + pincodes: [K, C, R, V] + afs: + ADC0_IN11: ANALOG + TIMER0_MCH1: 1 + TIMER1_CH3: 2 + USART0_TX: 5 + CAN0_TX: 6 + EVENTOUT: 9 + PA4: + pincodes: [K, C, R, V] + afs: + ADC0_IN10: ANALOG + TIMER0_CH1: 1 + USART0_RX: 5 + CAN0_RX: 6 + EVENTOUT: 9 + PA5: + pincodes: [K, C, R, V] + afs: + TIMER19_BRKIN3: 2 + USART2_TX: 5 + EVENTOUT: 9 + PA6: + pincodes: [K, C, R, V] + afs: + TIMER19_BRKIN2: 2 + USART2_RX: 5 + PA7: + pincodes: [K, C, R, V] + afs: + DAC_OUT: ANALOG + TIMER19_MCH1: 1 + TIMER1_CH1: 2 + TIMER19_BRKIN1: 3 + USART2_CK: 5 + TRIGSEL_IN7: 7 + EVENTOUT: 9 + PA8: + pincodes: [K, C, R, V] + afs: + ADC1_IN3: ANALOG + TIMER0_BRKIN0: 1 + TIMER20_MCH2: 2 + SPI1_NSS: 4 + I2S1_WS: 4 + MFCOM_D7: 5 + MFCOM_D5: 6 + TRIGSEL_IN4: 7 + EVENTOUT: 9 + PA9: + pincodes: [C, R, V] + afs: + ADC1_IN2: ANALOG + TIMER20_CH2: 1 + SPI1_MOSI: 4 + I2S1_SD: 4 + MFCOM_D6: 5 + MFCOM_D4: 6 + TRIGSEL_IN5: 7 + EVENTOUT: 9 + PA10: + pincodes: [K, C, R, V] + afs: + ADC1_IN1: ANALOG + TIMER20_MCH0: 1 + I2C0_SCL: 3 + USART0_TX: 5 + MFCOM_D5: 6 + EVENTOUT: 9 + PA11: + pincodes: [K, C, R, V] + afs: + ADC1_IN0: ANALOG + TIMER20_CH0: 1 + I2C0_SDA: 3 + USART0_RX: 5 + MFCOM_D4: 6 + TRIGSEL_IN13: 7 + EVENTOUT: 9 + PA12: + pincodes: [V] + afs: + TIMER20_MCH1: 1 + I2C0_SMBA: 3 + USART0_CK: 5 + EVENTOUT: 9 + PA13: + pincodes: [V] + afs: + TIMER20_CH1: 1 + I2C0_SDA: 3 + EVENTOUT: 9 + PA14: + pincodes: [V] + afs: + TIMER20_MCH0: 1 + I2C0_SCL: 3 + EVENTOUT: 9 + PA15: + pincodes: [V] + afs: + TIMER20_CH0: 1 + TRIGSEL_IN12: 7 + EVENTOUT: 9 + PB0: + pincodes: [V] + afs: + TIMER19_CH0: 1 + TIMER19_CH1: 2 + EVENTOUT: 9 + PB1: + pincodes: [C, R, V] + afs: + ADC0_IN9: ANALOG + TIMER0_MCH0: 1 + TIMER7_MCH3: 2 + EVENTOUT: 9 + PB2: + pincodes: [R, V] + afs: + ADC0_IN8: ANALOG + TIMER0_CH0: 1 + TIMER7_CH3: 2 + EVENTOUT: 9 + PB3: + pincodes: [K, C, R, V] + afs: + NJTRST: 0 + TIMER7_MCH2: 1 + SPI0_IO2: 4 + MFCOM_D1: 6 + EVENTOUT: 9 + PB4: + pincodes: [K, C, R, V] + afs: + JTDO: 0 + TIMER7_CH2: 1 + SPI0_IO3: 4 + MFCOM_D0: 6 + EVENTOUT: 9 + PB5: + pincodes: [R, V] + afs: + TIMER7_BRKIN1: 2 + I2C0_SMBA: 3 + SPI0_MISO: 4 + SPI1_NSS: 5 + I2S1_WS: 6 + EVENTOUT: 9 + PB6: + pincodes: [R, V] + afs: + TIMER7_BRKIN2: 2 + TIMER_ETI1: 3 + SPI0_SCK: 4 + SPI1_MOSI: 5 + I2S1_SD: 5 + EVENTOUT: 9 + PB7: + pincodes: [K, C, R, V] + afs: + JTDI: 0 + TIMER19_CH0: 1 + TIMER19_CH1: 2 + I2C1_SCL: 5 + EVENTOUT: 9 + PB8: + pincodes: [K, C, R, V] + afs: + JTCK: 0 + SWCLK: 0 + TIMER7_CH0: 1 + TIMER7_CH1: 2 + I2C1_SDA: 5 + EVENTOUT: 9 + PB9: + pincodes: [K, C, R, V] + afs: + JTMS: 0 + SWDIO: 0 + I2C1_SMBA: 5 + CMP_OUT: 7 + EVENTOUT: 9 + PB10: + pincodes: [V] + afs: + TIMER20_CH3: 1 + TIMER19_CH3: 2 + SPI0_IO3: 4 + USART2_CTS: 5 + EVENTOUT: 9 + PB11: + pincodes: [V] + afs: + TIMER20_MCH2: 1 + TIMER1_CH3: 2 + TRIGSEL_IN10: 7 + EVENTOUT: 9 + PB12: + pincodes: [V] + afs: + TIMER20_CH2: 1 + TRIGSEL_IN11: 7 + EVENTOUT: 9 + PB13: + pincodes: [K, C, R, V] + afs: + ADC0_IN5: ANALOG + ADC1_IN15: ANALOG + TIMER_ETI0: 0 + SPI0_MOSI: 4 + USART0_TX: 5 + CAN0_TX: 6 + EVENTOUT: 9 + PB14: + pincodes: [K, C, R, V] + afs: + ADC0_IN4: ANALOG + ADC1_IN14: ANALOG + TIMER1_CH2: 1 + SPI0_NSS: 3 + USART0_RX: 5 + CAN0_RX: 6 + EVENTOUT: 9 + PB15: + pincodes: [C, R, V] + afs: + TIMER7_BRKIN1: 2 + USART1_TX: 4 + USART0_RTS: 5 + USART0_DE: 5 + EVENTOUT: 9 + PC0: + pincodes: [K, C, R, V] + afs: + TIMER0_CH0: 1 + SPI0_SCK: 4 + EVENTOUT: 9 + PC1: + pincodes: [C, R, V] + afs: + TIMER0_MCH3: 1 + USART2_CTS: 5 + EVENTOUT: 9 + PC2: + pincodes: [V] + afs: + CK_OUT: 0 + TIMER19_MCH2: 1 + USART1_TX: 5 + EVENTOUT: 9 + PC3: + pincodes: [V] + afs: + TIMER19_CH2: 1 + USART1_RX: 5 + EVENTOUT: 9 + PC4: + pincodes: [V] + afs: + TIMER19_CH1: 1 + USART2_RTS: 5 + USART2_DE: 5 + EVENTOUT: 9 + PC5: + pincodes: [V] + afs: + TIMER19_MCH0: 1 + TIMER19_CH0: 2 + USART2_CTS: 5 + EVENTOUT: 9 + PC6: + pincodes: [V] + afs: + ADC1_IN9: ANALOG + ADC0_IN9: ANALOG + TIMER0_CH1: 1 + SPI1_SCK: 4 + I2S1_CK: 4 + EVENTOUT: 9 + PC7: + pincodes: [C, R, V] + afs: + ADC1_IN8: ANALOG + ADC0_IN8: ANALOG + TIMER0_MCH0: 1 + TIMER20_BRKIN1: 2 + I2S1_MCK: 4 + EVENTOUT: 9 + PC8: + pincodes: [R, V] + afs: + ADC1_IN7: ANALOG + TIMER0_CH0: 1 + TIMER20_BRKIN2: 2 + EVENTOUT: 9 + PC9: + pincodes: [R, V] + afs: + ADC1_IN6: ANALOG + TIMER0_BRKIN3: 1 + TIMER20_BRKIN3: 2 + EVENTOUT: 9 + PC10: + pincodes: [K, C, R, V] + afs: + ADC0_IN1: ANALOG + TIMER7_MCH0: 1 + TIMER7_CH0: 2 + I2C0_SDA: 3 + USART0_RTS: 5 + USART0_DE: 5 + MFCOM_D3: 6 + TRIGSEL_OUT0: 7 + EVENTOUT: 9 + PC11: + pincodes: [K, C, R, V] + afs: + ADC0_IN0: ANALOG + TIMER19_MCH0: 1 + TIMER19_CH0: 2 + I2C0_SCL: 3 + USART0_CTS: 5 + MFCOM_D2: 6 + TRIGSEL_OUT3: 7 + EVENTOUT: 9 + PC12: + pincodes: [C, R, V] + afs: + ADC1_IN5: ANALOG + TIMER20_MCH1: 1 + TIMER7_CH0: 2 + USART1_TX: 5 + CAN1_TX: 6 + EVENTOUT: 9 + PC13: + pincodes: [R, V] + afs: + CK_OUT: 0 + TIMER19_CH2: 1 + MFCOM_D4: 6 + TRIGSEL_OUT4: 7 + EVENTOUT: 9 + PC14: + pincodes: [V] + afs: + TIMER19_BRKIN0: 2 + EVENTOUT: 9 + PC15: + pincodes: [K, C, R, V] + afs: + TIMER_ETI2: 0 + TIMER19_MCH1: 1 + TIMER19_CH1: 2 + CAN0_TX: 6 + MFCOM_D7: 7 + EVENTOUT: 9 + PD0: + pincodes: [C, R, V] + afs: + ADC1_IN4: ANALOG + TIMER20_CH1: 1 + TIMER7_CH1: 2 + USART1_RX: 5 + CAN1_RX: 6 + EVENTOUT: 9 + PD1: + pincodes: [V] + afs: + ADC1_IN13: ANALOG + TIMER7_MCH1: 1 + SPI1_NSS: 4 + I2S1_WS: 4 + EVENTOUT: 9 + PD2: + pincodes: [V] + afs: + ADC1_IN12: ANALOG + TIMER7_CH1: 1 + SPI0_NSS: 4 + EVENTOUT: 9 + PD3: + pincodes: [R, V] + afs: + ADC1_IN11: ANALOG + TIMER20_MCH3: 1 + SPI0_NSS: 4 + USART1_RTS: 5 + USART1_DE: 5 + EVENTOUT: 9 + PD4: + pincodes: [R, V] + afs: + ADC1_IN10: ANALOG + TIMER20_CH3: 1 + TIMER1_CH2: 2 + SPI0_MOSI: 4 + USART1_CTS: 5 + EVENTOUT: 9 + PD5: + pincodes: [V] + afs: + TIMER0_BRKIN0: 7 + TIMER20_BRKIN1: 12 + TIMER7_BRKIN0: 12 + USART1_CK: 12 + EVENTOUT: 9 + PD6: + pincodes: [C, R, V] + afs: + TIMER7_MCH3: 1 + TIMER19_CH0: 2 + I2C1_SCL: 5 + CAN1_TX: 6 + EVENTOUT: 9 + PD7: + pincodes: [C, R, V] + afs: + TIMER7_CH3: 1 + TIMER19_CH1: 2 + I2C1_SDA: 5 + CAN1_RX: 6 + EVENTOUT: 9 + PD8: + pincodes: [C, R, V] + afs: + TIMER7_BRKIN0: 2 + USART1_RX: 4 + USART0_CTS: 5 + EVENTOUT: 9 + PD9: + pincodes: [K, C, R, V] + afs: + ADC0_IN3: ANALOG + TIMER0_BRKIN2: 2 + USART1_RTS: 5 + USART1_DE: 5 + EVENTOUT: 9 + PD10: + pincodes: [R, V] + afs: + ADC0_IN2: ANALOG + TIMER0_BRKIN1: 2 + SPI1_NSS: 4 + I2S1_WS: 4 + USART1_CTS: 5 + EVENTOUT: 9 + PD11: + pincodes: [R, V] + afs: + TIMER0_MCH3: 1 + TIMER20_BRKIN0: 2 + I2C1_SMBA: 5 + EVENTOUT: 9 + PD12: + pincodes: [V] + afs: + TIMER0_CH3: 1 + TIMER20_BRKIN0: 2 + EVENTOUT: 9 + PD13: + pincodes: [V] + afs: + TIMER0_MCH2: 1 + SPI1_NSS: 4 + I2S1_WS: 4 + EVENTOUT: 9 + PD14: + pincodes: [V] + afs: + ADC1_IN15: ANALOG + TIMER0_CH2: 1 + SPI1_MOSI: 4 + I2S1_SD: 4 + EVENTOUT: 9 + PD15: + pincodes: [V] + afs: + ADC1_IN14: ANALOG + TIMER0_MCH1: 1 + SPI1_MISO: 4 + EVENTOUT: 9 + PE0: + pincodes: [V] + afs: + TIMER20_BRKIN2: 1 + TIMER7_BRKIN3: 2 + USART2_TX: 5 + MFCOM_D7: 6 + EVENTOUT: 9 + PE1: + pincodes: [V] + afs: + TIMER20_BRKIN3: 1 + USART2_RX: 5 + MFCOM_D6: 6 + EVENTOUT: 9 + PE2: + pincodes: [V] + afs: + TIMER19_MCH3: 2 + USART1_RTS: 5 + USART1_DE: 5 + MFCOM_D3: 6 + TRIGSEL_OUT7: 7 + EVENTOUT: 9 + PE3: + pincodes: [V] + afs: + TIMER19_CH3: 0 + USART1_CTS: 12 + MFCOM_D2: 12 + TRIGSEL_OUT6: 12 + EVENTOUT: 9 + PE4: + pincodes: [C, R, V] + afs: + TIMER0_MCH1: 1 + TIMER19_MCH0: 2 + SPI1_MISO: 4 + MFCOM_D1: 6 + TRIGSEL_OUT2: 7 + EVENTOUT: 9 + PE5: + pincodes: [C, R, V] + afs: + TIMER0_CH1: 1 + TIMER19_CH0: 2 + SPI1_SCK: 4 + I2S1_CK: 4 + MFCOM_D0: 6 + TRIGSEL_OUT1: 7 + EVENTOUT: 9 + PE6: + pincodes: [R, V] + afs: + TIMER1_CH0: 1 + TIMER1_ETI: 1 + TIMER19_MCH2: 2 + I2S1_MCK: 4 + MFCOM_D5: 6 + TRIGSEL_OUT5: 7 + EVENTOUT: 9 + PE7: + pincodes: [V] + afs: + TIMER7_MCH2: 1 + TIMER19_BRKIN3: 2 + MFCOM_D0: 6 + EVENTOUT: 9 + PE8: + pincodes: [V] + afs: + TIMER7_CH2: 1 + TIMER19_BRKIN2: 2 + MFCOM_D1: 6 + EVENTOUT: 9 + PE9: + pincodes: [R, V] + afs: + ADC0_IN15: ANALOG + TIMER7_BRKIN3: 2 + EVENTOUT: 9 + PE10: + pincodes: [C, R, V] + afs: + ADC0_IN14: ANALOG + TIMER7_BRKIN2: 2 + I2C1_SCL: 5 + EVENTOUT: 9 + PE11: + pincodes: [C, R, V] + afs: + ADC0_IN13: ANALOG + TIMER7_MCH1: 1 + I2C1_SDA: 5 + TRIGSEL_IN8: 7 + EVENTOUT: 9 + PE12: + pincodes: [C, R, V] + afs: + ADC0_IN12: ANALOG + TIMER7_CH1: 1 + I2C1_SMBA: 5 + TRIGSEL_IN9: 7 + EVENTOUT: 9 + PE13: + pincodes: [K, C, R, V] + afs: + ADC0_IN7: ANALOG + TIMER7_MCH0: 1 + TIMER7_CH0: 2 + SPI0_MISO: 4 + TRIGSEL_IN2: 7 + EVENTOUT: 9 + PE14: + pincodes: [K, C, R, V] + afs: + ADC0_IN6: ANALOG + TIMER7_CH0: 1 + TIMER7_CH1: 2 + SPI0_SCK: 4 + TRIGSEL_IN3: 7 + EVENTOUT: 9 + PE15: + pincodes: [V] + afs: + TIMER20_MCH3: 1 + TIMER19_MCH3: 2 + SPI0_IO2: 4 + USART2_RTS: 5 + USART2_DE: 5 + EVENTOUT: 9 + PF0: + pincodes: [K, C, R, V] + afs: + TIMER19_CH1: 1 + CAN0_RX: 6 + MFCOM_D6: 7 + EVENTOUT: 9 + PF1: + pincodes: [V] + afs: + TIMER0_BRKIN1: 1 + TIMER19_BRKIN1: 2 + EVENTOUT: 9 + PF2: + pincodes: [R, V] + afs: + TIMER0_BRKIN0: 1 + TIMRE19_BRKIN0: 2 + USART2_RTS: 5 + USART2_DE: 5 + TRIGSEL_IN6: 6 + CMP_OUT: 7 + EVENTOUT: 9 + PF3: + pincodes: [V] + afs: + TIMER0_BRKIN3: 2 + USART2_TX: 5 + EVENTOUT: 9 + PF4: + pincodes: [V] + afs: + TIMER0_BRKIN2: 2 + USART2_RX: 5 + EVENTOUT: 9 + PF5: + pincodes: [K, C, R, V] + afs: + TIMER0_MCH0: 1 + SPI0_MISO: 4 + USART1_CTS: 5 + EVENTOUT: 9 + PF6: + pincodes: [K, C, R, V] + afs: + I2C0_SCL: 3 + EVENTOUT: 9 + PF7: + pincodes: [K, C, R, V] + afs: + I2C0_SDA: 3 + EVENTOUT: 9