diff --git a/common_include/gd32_usb.h b/common_include/gd32_usb.h new file mode 100644 index 00000000..578e98a6 --- /dev/null +++ b/common_include/gd32_usb.h @@ -0,0 +1,15 @@ +/* + * NOTE: Autogenerated file using gd32headers.py + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if defined(CONFIG_SOC_SERIES_GD32F4XX) +#include +#include +#include +#include +#include +#include +#include +#endif diff --git a/gd32e10x/cmsis/gd/gd32e10x/include/gd32e10x.h b/gd32e10x/cmsis/gd/gd32e10x/include/gd32e10x.h index 8986a722..d354c9e4 100644 --- a/gd32e10x/cmsis/gd/gd32e10x/include/gd32e10x.h +++ b/gd32e10x/cmsis/gd/gd32e10x/include/gd32e10x.h @@ -195,9 +195,9 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; #define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) -#ifndef BIT +#ifndef BIT #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) -#endif /* BIT */ +#endif /* BIT */ #define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) diff --git a/gd32f4xx/cmsis/gd/gd32f4xx/source/system_gd32f4xx.c b/gd32f4xx/cmsis/gd/gd32f4xx/source/system_gd32f4xx.c index f78725e1..25020f27 100644 --- a/gd32f4xx/cmsis/gd/gd32f4xx/source/system_gd32f4xx.c +++ b/gd32f4xx/cmsis/gd/gd32f4xx/source/system_gd32f4xx.c @@ -56,14 +56,21 @@ //#define __SYSTEM_CLOCK_240M_PLL_8M_HXTAL (uint32_t)(240000000) //#define __SYSTEM_CLOCK_240M_PLL_25M_HXTAL (uint32_t)(240000000) +#define RCU_MODIFY(__delay) do{ \ + volatile uint32_t i; \ + if(0 != __delay){ \ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \ + for(i=0; i<__delay; i++){ \ + } \ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \ + for(i=0; i<__delay; i++){ \ + } \ + } \ + }while(0) + #define SEL_IRC16M 0x00U #define SEL_HXTAL 0x01U #define SEL_PLLP 0x02U -#define RCU_MODIFY {volatile uint32_t i; \ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \ - for(i=0;i<50000;i++); \ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \ - for(i=0;i<50000;i++);} /* set the system clock frequency and declare the system clock configuration function */ #ifdef __SYSTEM_CLOCK_IRC16M @@ -129,8 +136,9 @@ void SystemInit (void) /* Reset the RCU clock configuration to the default reset state */ /* Set IRC16MEN bit */ RCU_CTL |= RCU_CTL_IRC16MEN; - - RCU_MODIFY + while(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + } + RCU_MODIFY(0x50); RCU_CFG0 &= ~RCU_CFG0_SCS; diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_adc.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_adc.h index 925f6f46..096b0c95 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_adc.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_adc.h @@ -46,153 +46,153 @@ OF SUCH DAMAGE. #define ADC2 (ADC_BASE + 0x200U) /* registers definitions */ -#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ -#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ -#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ -#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ -#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ -#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ -#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ -#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ -#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ -#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ -#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ -#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ -#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ -#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ -#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ -#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ -#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ -#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ -#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ -#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ -#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */ -#define ADC_SSTAT REG32((ADC_BASE) + 0x300U) /*!< ADC summary status register */ -#define ADC_SYNCCTL REG32((ADC_BASE) + 0x304U) /*!< ADC synchronization control register */ -#define ADC_SYNCDATA REG32((ADC_BASE) + 0x308U) /*!< ADC synchronization regular data register */ +#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ +#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ +#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ +#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ +#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ +#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ +#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ +#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ +#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ +#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ +#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ +#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC routine sequence register 0 */ +#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC routine sequence register 1 */ +#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC routine sequence register 2 */ +#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ +#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ +#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ +#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ +#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ +#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC routine data register */ +#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */ +#define ADC_SSTAT REG32((ADC_BASE) + 0x300U) /*!< ADC summary status register */ +#define ADC_SYNCCTL REG32((ADC_BASE) + 0x304U) /*!< ADC synchronization control register */ +#define ADC_SYNCDATA REG32((ADC_BASE) + 0x308U) /*!< ADC synchronization routine data register */ /* bits definitions */ /* ADC_STAT */ -#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ -#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ -#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ -#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ -#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ -#define ADC_STAT_ROVF BIT(5) /*!< regular data register overflow */ +#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ +#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ +#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ +#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ +#define ADC_STAT_STRC BIT(4) /*!< routine channel start flag */ +#define ADC_STAT_ROVF BIT(5) /*!< routine data register overflow */ /* ADC_CTL0 */ -#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ -#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ -#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ -#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ -#define ADC_CTL0_SM BIT(8) /*!< scan mode */ -#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ -#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ -#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ -#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ -#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ -#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ -#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ -#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ -#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */ +#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ +#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ +#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ +#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ +#define ADC_CTL0_SM BIT(8) /*!< scan mode */ +#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ +#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted sequence conversion */ +#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on routine channels */ +#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ +#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on routine channels */ +#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ +#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */ /* ADC_CTL1 */ -#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ -#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ -#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ -#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ -#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ -#define ADC_CTL1_DDM BIT(9) /*!< DMA disable mode */ -#define ADC_CTL1_EOCM BIT(10) /*!< end of conversion mode */ -#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ -#define ADC_CTL1_ETSIC BITS(16,19) /*!< external event select for inserted group */ -#define ADC_CTL1_ETMIC BITS(20,21) /*!< external trigger conversion mode for inserted channels */ -#define ADC_CTL1_SWICST BIT(22) /*!< start conversion of inserted channels */ -#define ADC_CTL1_ETSRC BITS(24,27) /*!< external event select for regular group */ -#define ADC_CTL1_ETMRC BITS(28,29) /*!< external trigger conversion mode for regular channels */ -#define ADC_CTL1_SWRCST BIT(30) /*!< start conversion of regular channels */ +#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ +#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ +#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ +#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ +#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ +#define ADC_CTL1_DDM BIT(9) /*!< DMA disable mode */ +#define ADC_CTL1_EOCM BIT(10) /*!< end of conversion mode */ +#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +#define ADC_CTL1_ETSIC BITS(16,19) /*!< external event select for inserted sequence */ +#define ADC_CTL1_ETMIC BITS(20,21) /*!< external trigger conversion mode for inserted channels */ +#define ADC_CTL1_SWICST BIT(22) /*!< start conversion of inserted channels */ +#define ADC_CTL1_ETSRC BITS(24,27) /*!< external event select for routine sequence */ +#define ADC_CTL1_ETMRC BITS(28,29) /*!< external trigger conversion mode for routine channels */ +#define ADC_CTL1_SWRCST BIT(30) /*!< start conversion of routine channels */ /* ADC_SAMPTx x=0..1 */ -#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */ +#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */ /* ADC_IOFFx x=0..3 */ -#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ +#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ /* ADC_WDHT */ -#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ +#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ /* ADC_WDLT */ -#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ +#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ /* ADC_RSQx */ -#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in regular sequence */ -#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ +#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in routine sequence */ +#define ADC_RSQ0_RL BITS(20,23) /*!< routine channel sequence length */ /* ADC_ISQ */ -#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in regular sequence */ -#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ +#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in inserted sequence */ +#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ /* ADC_IDATAx x=0..3*/ -#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */ +#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */ /* ADC_RDATA */ -#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ +#define ADC_RDATA_RDATA BITS(0,15) /*!< routine data */ /* ADC_OVSAMPCTL */ -#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ -#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ -#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ -#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ +#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ +#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ +#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ +#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ /* ADC_SSTAT */ -#define ADC_SSTAT_WDE0 BIT(0) /*!< the mirror image of the WDE bit of ADC0 */ -#define ADC_SSTAT_EOC0 BIT(1) /*!< the mirror image of the EOC bit of ADC0 */ -#define ADC_SSTAT_EOIC0 BIT(2) /*!< the mirror image of the EOIC bit of ADC0 */ -#define ADC_SSTAT_STIC0 BIT(3) /*!< the mirror image of the STIC bit of ADC0 */ -#define ADC_SSTAT_STRC0 BIT(4) /*!< the mirror image of the STRC bit of ADC0 */ -#define ADC_SSTAT_ROVF0 BIT(5) /*!< the mirror image of the ROVF bit of ADC0 */ -#define ADC_SSTAT_WDE1 BIT(8) /*!< the mirror image of the WDE bit of ADC1 */ -#define ADC_SSTAT_EOC1 BIT(9) /*!< the mirror image of the EOC bit of ADC1 */ -#define ADC_SSTAT_EOIC1 BIT(10) /*!< the mirror image of the EOIC bit of ADC1 */ -#define ADC_SSTAT_STIC1 BIT(11) /*!< the mirror image of the STIC bit of ADC1 */ -#define ADC_SSTAT_STRC1 BIT(12) /*!< the mirror image of the STRC bit of ADC1 */ -#define ADC_SSTAT_ROVF1 BIT(13) /*!< the mirror image of the ROVF bit of ADC1 */ -#define ADC_SSTAT_WDE2 BIT(16) /*!< the mirror image of the WDE bit of ADC2 */ -#define ADC_SSTAT_EOC2 BIT(17) /*!< the mirror image of the EOC bit of ADC2 */ -#define ADC_SSTAT_EOIC2 BIT(18) /*!< the mirror image of the EOIC bit of ADC2 */ -#define ADC_SSTAT_STIC2 BIT(19) /*!< the mirror image of the STIC bit of ADC2 */ -#define ADC_SSTAT_STRC2 BIT(20) /*!< the mirror image of the STRC bit of ADC2 */ -#define ADC_SSTAT_ROVF2 BIT(21) /*!< the mirror image of the ROVF bit of ADC2 */ +#define ADC_SSTAT_WDE0 BIT(0) /*!< the mirror image of the WDE bit of ADC0 */ +#define ADC_SSTAT_EOC0 BIT(1) /*!< the mirror image of the EOC bit of ADC0 */ +#define ADC_SSTAT_EOIC0 BIT(2) /*!< the mirror image of the EOIC bit of ADC0 */ +#define ADC_SSTAT_STIC0 BIT(3) /*!< the mirror image of the STIC bit of ADC0 */ +#define ADC_SSTAT_STRC0 BIT(4) /*!< the mirror image of the STRC bit of ADC0 */ +#define ADC_SSTAT_ROVF0 BIT(5) /*!< the mirror image of the ROVF bit of ADC0 */ +#define ADC_SSTAT_WDE1 BIT(8) /*!< the mirror image of the WDE bit of ADC1 */ +#define ADC_SSTAT_EOC1 BIT(9) /*!< the mirror image of the EOC bit of ADC1 */ +#define ADC_SSTAT_EOIC1 BIT(10) /*!< the mirror image of the EOIC bit of ADC1 */ +#define ADC_SSTAT_STIC1 BIT(11) /*!< the mirror image of the STIC bit of ADC1 */ +#define ADC_SSTAT_STRC1 BIT(12) /*!< the mirror image of the STRC bit of ADC1 */ +#define ADC_SSTAT_ROVF1 BIT(13) /*!< the mirror image of the ROVF bit of ADC1 */ +#define ADC_SSTAT_WDE2 BIT(16) /*!< the mirror image of the WDE bit of ADC2 */ +#define ADC_SSTAT_EOC2 BIT(17) /*!< the mirror image of the EOC bit of ADC2 */ +#define ADC_SSTAT_EOIC2 BIT(18) /*!< the mirror image of the EOIC bit of ADC2 */ +#define ADC_SSTAT_STIC2 BIT(19) /*!< the mirror image of the STIC bit of ADC2 */ +#define ADC_SSTAT_STRC2 BIT(20) /*!< the mirror image of the STRC bit of ADC2 */ +#define ADC_SSTAT_ROVF2 BIT(21) /*!< the mirror image of the ROVF bit of ADC2 */ /* ADC_SYNCCTL */ -#define ADC_SYNCCTL_SYNCM BITS(0,4) /*!< ADC synchronization mode */ -#define ADC_SYNCCTL_SYNCDLY BITS(8,11) /*!< ADC synchronization delay */ -#define ADC_SYNCCTL_SYNCDDM BIT(13) /*!< ADC synchronization DMA disable mode */ -#define ADC_SYNCCTL_SYNCDMA BITS(14,15) /*!< ADC synchronization DMA mode selection */ -#define ADC_SYNCCTL_ADCCK BITS(16,18) /*!< ADC clock */ -#define ADC_SYNCCTL_VBATEN BIT(22) /*!< channel 18 (1/4 voltate of external battery) enable of ADC0 */ -#define ADC_SYNCCTL_TSVREN BIT(23) /*!< channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0 */ +#define ADC_SYNCCTL_SYNCM BITS(0,4) /*!< ADC synchronization mode */ +#define ADC_SYNCCTL_SYNCDLY BITS(8,11) /*!< ADC synchronization delay */ +#define ADC_SYNCCTL_SYNCDDM BIT(13) /*!< ADC synchronization DMA disable mode */ +#define ADC_SYNCCTL_SYNCDMA BITS(14,15) /*!< ADC synchronization DMA mode selection */ +#define ADC_SYNCCTL_ADCCK BITS(16,18) /*!< ADC clock */ +#define ADC_SYNCCTL_VBATEN BIT(22) /*!< channel 18 (1/4 voltate of external battery) enable of ADC0 */ +#define ADC_SYNCCTL_TSVREN BIT(23) /*!< channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0 */ /* ADC_SYNCDATA */ -#define ADC_SYNCDATA_SYNCDATA0 BITS(0,15) /*!< regular data1 in ADC synchronization mode */ -#define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< regular data2 in ADC synchronization mode */ +#define ADC_SYNCDATA_SYNCDATA0 BITS(0,15) /*!< routine data1 in ADC synchronization mode */ +#define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< routine data2 in ADC synchronization mode */ /* constants definitions */ /* ADC status flag */ -#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ -#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ -#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ -#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ -#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ -#define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */ +#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< routine channel start flag */ +#define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */ /* adc_ctl0 register value */ #define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ /* ADC special function definitions */ -#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ -#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ -#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted sequence convert automatically */ +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ /* temperature sensor channel, internal reference voltage channel, VBAT channel */ #define ADC_VBAT_CHANNEL_SWITCH ADC_SYNCCTL_VBATEN /*!< VBAT channel */ @@ -201,210 +201,210 @@ OF SUCH DAMAGE. /* ADC synchronization mode */ #define SYNCCTL_SYNCM(regval) (BITS(0,4) & ((uint32_t)(regval))) /*!< write value to ADC_CTL0_SYNCM bit field */ #define ADC_SYNC_MODE_INDEPENDENT SYNCCTL_SYNCM(0) /*!< ADC synchronization mode disabled.All the ADCs work independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel & inserted parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel & trigger rotation mode. ADC2 works independently */ +#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< ADC0 and ADC1 work in combined routine parallel & inserted parallel mode. ADC2 works independently */ +#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< ADC0 and ADC1 work in combined routine parallel & trigger rotation mode. ADC2 works independently */ #define ADC_DAUL_INSERTED_PARALLEL SYNCCTL_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_PARALLEL SYNCCTL_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */ +#define ADC_DAUL_ROUTINE_PARALLEL SYNCCTL_SYNCM(6) /*!< ADC0 and ADC1 work in routine parallel mode. ADC2 works independently */ +#define ADC_DAUL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */ #define ADC_DAUL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */ -#define ADC_ALL_REGULAL_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(17) /*!< all ADCs work in combined regular parallel & inserted parallel mode */ -#define ADC_ALL_REGULAL_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(18) /*!< all ADCs work in combined regular parallel & trigger rotation mode */ +#define ADC_ALL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(17) /*!< all ADCs work in combined routine parallel & inserted parallel mode */ +#define ADC_ALL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(18) /*!< all ADCs work in combined routine parallel & trigger rotation mode */ #define ADC_ALL_INSERTED_PARALLEL SYNCCTL_SYNCM(21) /*!< all ADCs work in inserted parallel mode */ -#define ADC_ALL_REGULAL_PARALLEL SYNCCTL_SYNCM(22) /*!< all ADCs work in regular parallel mode */ -#define ADC_ALL_REGULAL_FOLLOW_UP SYNCCTL_SYNCM(23) /*!< all ADCs work in follow-up mode */ +#define ADC_ALL_ROUTINE_PARALLEL SYNCCTL_SYNCM(22) /*!< all ADCs work in routine parallel mode */ +#define ADC_ALL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(23) /*!< all ADCs work in follow-up mode */ #define ADC_ALL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(25) /*!< all ADCs work in trigger rotation mode */ /* ADC data alignment */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ -#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ -/* external trigger mode for regular and inserted channel */ -#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */ -#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */ -#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */ -#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */ +/* external trigger mode for routine and inserted channel */ +#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */ +#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */ +#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */ +#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */ -/* ADC external trigger select for regular channel */ +/* ADC external trigger select for routine channel */ #define CTL1_ETSRC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ -#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ -#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ -#define ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */ -#define ADC_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(4) /*!< timer 1 CC2 event select */ -#define ADC_EXTTRIG_REGULAR_T1_CH3 CTL1_ETSRC(5) /*!< timer 1 CC3 event select */ -#define ADC_EXTTRIG_REGULAR_T1_TRGO CTL1_ETSRC(6) /*!< timer 1 TRGO event select */ -#define ADC_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(7) /*!< timer 2 CC0 event select */ -#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(8) /*!< timer 2 TRGO event select */ -#define ADC_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(9) /*!< timer 3 CC3 event select */ -#define ADC_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(10) /*!< timer 4 CC0 event select */ -#define ADC_EXTTRIG_REGULAR_T4_CH1 CTL1_ETSRC(11) /*!< timer 4 CC1 event select */ -#define ADC_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(12) /*!< timer 4 CC2 event select */ -#define ADC_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(13) /*!< timer 7 CC0 event select */ -#define ADC_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(14) /*!< timer 7 TRGO event select */ -#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(15) /*!< extiline 11 select */ +#define ADC_EXTTRIG_ROUTINE_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ +#define ADC_EXTTRIG_ROUTINE_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_CH2 CTL1_ETSRC(4) /*!< timer 1 CC2 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_CH3 CTL1_ETSRC(5) /*!< timer 1 CC3 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_TRGO CTL1_ETSRC(6) /*!< timer 1 TRGO event select */ +#define ADC_EXTTRIG_ROUTINE_T2_CH0 CTL1_ETSRC(7) /*!< timer 2 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T2_TRGO CTL1_ETSRC(8) /*!< timer 2 TRGO event select */ +#define ADC_EXTTRIG_ROUTINE_T3_CH3 CTL1_ETSRC(9) /*!< timer 3 CC3 event select */ +#define ADC_EXTTRIG_ROUTINE_T4_CH0 CTL1_ETSRC(10) /*!< timer 4 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T4_CH1 CTL1_ETSRC(11) /*!< timer 4 CC1 event select */ +#define ADC_EXTTRIG_ROUTINE_T4_CH2 CTL1_ETSRC(12) /*!< timer 4 CC2 event select */ +#define ADC_EXTTRIG_ROUTINE_T7_CH0 CTL1_ETSRC(13) /*!< timer 7 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T7_TRGO CTL1_ETSRC(14) /*!< timer 7 TRGO event select */ +#define ADC_EXTTRIG_ROUTINE_EXTI_11 CTL1_ETSRC(15) /*!< extiline 11 select */ /* ADC external trigger select for inserted channel */ #define CTL1_ETSIC(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) -#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(0) /*!< timer0 capture compare 3 */ -#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(1) /*!< timer0 TRGO event */ -#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(2) /*!< timer1 capture compare 0 */ -#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(3) /*!< timer1 TRGO event */ -#define ADC_EXTTRIG_INSERTED_T2_CH1 CTL1_ETSIC(4) /*!< timer2 capture compare 1 */ -#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(5) /*!< timer2 capture compare 3 */ -#define ADC_EXTTRIG_INSERTED_T3_CH0 CTL1_ETSIC(6) /*!< timer3 capture compare 0 */ -#define ADC_EXTTRIG_INSERTED_T3_CH1 CTL1_ETSIC(7) /*!< timer3 capture compare 1 */ -#define ADC_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(8) /*!< timer3 capture compare 2 */ -#define ADC_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(9) /*!< timer3 capture compare TRGO */ -#define ADC_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(10) /*!< timer4 capture compare 3 */ -#define ADC_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(11) /*!< timer4 capture compare TRGO */ -#define ADC_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(12) /*!< timer7 capture compare 1 */ -#define ADC_EXTTRIG_INSERTED_T7_CH2 CTL1_ETSIC(13) /*!< timer7 capture compare 2 */ -#define ADC_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(14) /*!< timer7 capture compare 3 */ -#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(15) /*!< external interrupt line 15 */ +#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(0) /*!< timer0 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(1) /*!< timer0 TRGO event */ +#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(2) /*!< timer1 capture compare 0 */ +#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(3) /*!< timer1 TRGO event */ +#define ADC_EXTTRIG_INSERTED_T2_CH1 CTL1_ETSIC(4) /*!< timer2 capture compare 1 */ +#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(5) /*!< timer2 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_T3_CH0 CTL1_ETSIC(6) /*!< timer3 capture compare 0 */ +#define ADC_EXTTRIG_INSERTED_T3_CH1 CTL1_ETSIC(7) /*!< timer3 capture compare 1 */ +#define ADC_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(8) /*!< timer3 capture compare 2 */ +#define ADC_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(9) /*!< timer3 capture compare TRGO */ +#define ADC_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(10) /*!< timer4 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(11) /*!< timer4 capture compare TRGO */ +#define ADC_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(12) /*!< timer7 capture compare 1 */ +#define ADC_EXTTRIG_INSERTED_T7_CH2 CTL1_ETSIC(13) /*!< timer7 capture compare 2 */ +#define ADC_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(14) /*!< timer7 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(15) /*!< external interrupt line 15 */ /* ADC channel sample time */ -#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ -#define ADC_SAMPLETIME_3 SAMPTX_SPT(0) /*!< 3 sampling cycles */ -#define ADC_SAMPLETIME_15 SAMPTX_SPT(1) /*!< 15 sampling cycles */ -#define ADC_SAMPLETIME_28 SAMPTX_SPT(2) /*!< 28 sampling cycles */ -#define ADC_SAMPLETIME_56 SAMPTX_SPT(3) /*!< 56 sampling cycles */ -#define ADC_SAMPLETIME_84 SAMPTX_SPT(4) /*!< 84 sampling cycles */ -#define ADC_SAMPLETIME_112 SAMPTX_SPT(5) /*!< 112 sampling cycles */ -#define ADC_SAMPLETIME_144 SAMPTX_SPT(6) /*!< 144 sampling cycles */ -#define ADC_SAMPLETIME_480 SAMPTX_SPT(7) /*!< 480 sampling cycles */ +#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ +#define ADC_SAMPLETIME_3 SAMPTX_SPT(0) /*!< 3 sampling cycles */ +#define ADC_SAMPLETIME_15 SAMPTX_SPT(1) /*!< 15 sampling cycles */ +#define ADC_SAMPLETIME_28 SAMPTX_SPT(2) /*!< 28 sampling cycles */ +#define ADC_SAMPLETIME_56 SAMPTX_SPT(3) /*!< 56 sampling cycles */ +#define ADC_SAMPLETIME_84 SAMPTX_SPT(4) /*!< 84 sampling cycles */ +#define ADC_SAMPLETIME_112 SAMPTX_SPT(5) /*!< 112 sampling cycles */ +#define ADC_SAMPLETIME_144 SAMPTX_SPT(6) /*!< 144 sampling cycles */ +#define ADC_SAMPLETIME_480 SAMPTX_SPT(7) /*!< 480 sampling cycles */ /* adc_ioffx register value */ -#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ +#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ /* adc_wdht register value */ -#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ +#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ /* adc_wdlt register value */ -#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ +#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ /* adc_rsqx register value */ -#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ +#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ /* adc_isq register value */ -#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ +#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ /* adc_ovsampctl register value */ /* ADC resolution */ -#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< write value to ADC_CTL0_DRES bit field */ -#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ -#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ -#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ -#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ +#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< write value to ADC_CTL0_DRES bit field */ +#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ +#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ +#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ +#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ /* oversampling shift */ -#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ -#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ +#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ +#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ /* oversampling ratio */ -#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ -#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ -#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ -#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ -#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ -#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ -#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ -#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ -#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ - -/* triggered Oversampling */ -#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ -#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ - -/* ADC channel group definitions */ -#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ -#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ -#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ -#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ +#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ +#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ +#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ +#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ +#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ +#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ +#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ +#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ +#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ + +/* triggered oversampling */ +#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ +#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ + +/* ADC channel sequence definitions */ +#define ADC_ROUTINE_CHANNEL ((uint8_t)0x01U) /*!< adc routine sequence */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted sequence */ +#define ADC_ROUTINE_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both routine and inserted sequence */ +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of routine & inserted sequence */ /* ADC inserted channel definitions */ -#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ -#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ -#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ -#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ /* ADC channel definitions */ -#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ -#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ -#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ -#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ -#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ -#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ -#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ -#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ -#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ -#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ -#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ -#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ -#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ -#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ -#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ -#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ -#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ -#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ -#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ +#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ +#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ +#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ +#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ +#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ +#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ /* ADC interrupt flag */ -#define ADC_INT_WDE ADC_CTL0_WDEIE /*!< analog watchdog event interrupt */ -#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< end of group conversion interrupt */ -#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< end of inserted group conversion interrupt */ -#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< regular data register overflow */ +#define ADC_INT_WDE ADC_CTL0_WDEIE /*!< analog watchdog event interrupt */ +#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< end of sequence conversion interrupt */ +#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< end of inserted sequence conversion interrupt */ +#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< routine data register overflow */ /* ADC interrupt flag */ -#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ -#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ -#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ -#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */ +#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of sequence conversion interrupt */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted sequence conversion interrupt */ +#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */ /* configure the ADC clock for all the ADCs */ #define SYNCCTL_ADCCK(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) -#define ADC_ADCCK_PCLK2_DIV2 SYNCCTL_ADCCK(0) /*!< PCLK2 div2 */ -#define ADC_ADCCK_PCLK2_DIV4 SYNCCTL_ADCCK(1) /*!< PCLK2 div4 */ -#define ADC_ADCCK_PCLK2_DIV6 SYNCCTL_ADCCK(2) /*!< PCLK2 div6 */ -#define ADC_ADCCK_PCLK2_DIV8 SYNCCTL_ADCCK(3) /*!< PCLK2 div8 */ -#define ADC_ADCCK_HCLK_DIV5 SYNCCTL_ADCCK(4) /*!< HCLK div5 */ -#define ADC_ADCCK_HCLK_DIV6 SYNCCTL_ADCCK(5) /*!< HCLK div6 */ -#define ADC_ADCCK_HCLK_DIV10 SYNCCTL_ADCCK(6) /*!< HCLK div10 */ -#define ADC_ADCCK_HCLK_DIV20 SYNCCTL_ADCCK(7) /*!< HCLK div20 */ +#define ADC_ADCCK_PCLK2_DIV2 SYNCCTL_ADCCK(0) /*!< PCLK2 div2 */ +#define ADC_ADCCK_PCLK2_DIV4 SYNCCTL_ADCCK(1) /*!< PCLK2 div4 */ +#define ADC_ADCCK_PCLK2_DIV6 SYNCCTL_ADCCK(2) /*!< PCLK2 div6 */ +#define ADC_ADCCK_PCLK2_DIV8 SYNCCTL_ADCCK(3) /*!< PCLK2 div8 */ +#define ADC_ADCCK_HCLK_DIV5 SYNCCTL_ADCCK(4) /*!< HCLK div5 */ +#define ADC_ADCCK_HCLK_DIV6 SYNCCTL_ADCCK(5) /*!< HCLK div6 */ +#define ADC_ADCCK_HCLK_DIV10 SYNCCTL_ADCCK(6) /*!< HCLK div10 */ +#define ADC_ADCCK_HCLK_DIV20 SYNCCTL_ADCCK(7) /*!< HCLK div20 */ /* ADC synchronization delay */ -#define ADC_SYNC_DELAY_5CYCLE ((uint32_t)0x00000000U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 5 ADC clock cycles. */ -#define ADC_SYNC_DELAY_6CYCLE ((uint32_t)0x00000100U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 6 ADC clock cycles. */ -#define ADC_SYNC_DELAY_7CYCLE ((uint32_t)0x00000200U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 7 ADC clock cycles. */ -#define ADC_SYNC_DELAY_8CYCLE ((uint32_t)0x00000300U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 8 ADC clock cycles. */ -#define ADC_SYNC_DELAY_9CYCLE ((uint32_t)0x00000400U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 9 ADC clock cycles. */ -#define ADC_SYNC_DELAY_10CYCLE ((uint32_t)0x00000500U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 10 ADC clock cycles. */ -#define ADC_SYNC_DELAY_11CYCLE ((uint32_t)0x00000600U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 11 ADC clock cycles. */ -#define ADC_SYNC_DELAY_12CYCLE ((uint32_t)0x00000700U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 12 ADC clock cycles. */ -#define ADC_SYNC_DELAY_13CYCLE ((uint32_t)0x00000800U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 13 ADC clock cycles. */ -#define ADC_SYNC_DELAY_14CYCLE ((uint32_t)0x00000900U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 14 ADC clock cycles. */ -#define ADC_SYNC_DELAY_15CYCLE ((uint32_t)0x00000A00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 15 ADC clock cycles. */ -#define ADC_SYNC_DELAY_16CYCLE ((uint32_t)0x00000B00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 16 ADC clock cycles. */ -#define ADC_SYNC_DELAY_17CYCLE ((uint32_t)0x00000C00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 17 ADC clock cycles. */ -#define ADC_SYNC_DELAY_18CYCLE ((uint32_t)0x00000D00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 18 ADC clock cycles. */ -#define ADC_SYNC_DELAY_19CYCLE ((uint32_t)0x00000E00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 19 ADC clock cycles. */ -#define ADC_SYNC_DELAY_20CYCLE ((uint32_t)0x00000F00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 20 ADC clock cycles. */ +#define ADC_SYNC_DELAY_5CYCLE ((uint32_t)0x00000000U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 5 ADC clock cycles. */ +#define ADC_SYNC_DELAY_6CYCLE ((uint32_t)0x00000100U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 6 ADC clock cycles. */ +#define ADC_SYNC_DELAY_7CYCLE ((uint32_t)0x00000200U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 7 ADC clock cycles. */ +#define ADC_SYNC_DELAY_8CYCLE ((uint32_t)0x00000300U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 8 ADC clock cycles. */ +#define ADC_SYNC_DELAY_9CYCLE ((uint32_t)0x00000400U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 9 ADC clock cycles. */ +#define ADC_SYNC_DELAY_10CYCLE ((uint32_t)0x00000500U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 10 ADC clock cycles. */ +#define ADC_SYNC_DELAY_11CYCLE ((uint32_t)0x00000600U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 11 ADC clock cycles. */ +#define ADC_SYNC_DELAY_12CYCLE ((uint32_t)0x00000700U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 12 ADC clock cycles. */ +#define ADC_SYNC_DELAY_13CYCLE ((uint32_t)0x00000800U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 13 ADC clock cycles. */ +#define ADC_SYNC_DELAY_14CYCLE ((uint32_t)0x00000900U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 14 ADC clock cycles. */ +#define ADC_SYNC_DELAY_15CYCLE ((uint32_t)0x00000A00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 15 ADC clock cycles. */ +#define ADC_SYNC_DELAY_16CYCLE ((uint32_t)0x00000B00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 16 ADC clock cycles. */ +#define ADC_SYNC_DELAY_17CYCLE ((uint32_t)0x00000C00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 17 ADC clock cycles. */ +#define ADC_SYNC_DELAY_18CYCLE ((uint32_t)0x00000D00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 18 ADC clock cycles. */ +#define ADC_SYNC_DELAY_19CYCLE ((uint32_t)0x00000E00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 19 ADC clock cycles. */ +#define ADC_SYNC_DELAY_20CYCLE ((uint32_t)0x00000F00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 20 ADC clock cycles. */ /* ADC synchronization DMA mode selection */ -#define ADC_SYNC_DMA_DISABLE ((uint32_t)0x00000000U) /*!< ADC synchronization DMA disabled */ -#define ADC_SYNC_DMA_MODE0 ((uint32_t)0x00004000U) /*!< ADC synchronization DMA mode 0 */ -#define ADC_SYNC_DMA_MODE1 ((uint32_t)0x00008000U) /*!< ADC synchronization DMA mode 1 */ +#define ADC_SYNC_DMA_DISABLE ((uint32_t)0x00000000U) /*!< ADC synchronization DMA disabled */ +#define ADC_SYNC_DMA_MODE0 ((uint32_t)0x00004000U) /*!< ADC synchronization DMA mode 0 */ +#define ADC_SYNC_DMA_MODE1 ((uint32_t)0x00008000U) /*!< ADC synchronization DMA mode 1 */ /* end of conversion mode */ -#define ADC_EOC_SET_SEQUENCE ((uint8_t)0x00U) /*!< only at the end of a sequence of regular conversions, the EOC bit is set */ -#define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each regular conversion, the EOC bit is set */ +#define ADC_EOC_SET_SEQUENCE ((uint8_t)0x00U) /*!< only at the end of a sequence of routine conversions, the EOC bit is set */ +#define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each routine conversion, the EOC bit is set */ /* function declarations */ /* initialization config */ @@ -438,35 +438,35 @@ void adc_oversample_mode_disable(uint32_t adc_periph); void adc_dma_mode_enable(uint32_t adc_periph); /* disable DMA request */ void adc_dma_mode_disable(uint32_t adc_periph); -/* when DMA=1, the DMA engine issues a request at end of each regular conversion */ +/* when DMA=1, the DMA engine issues a request at end of each routine conversion */ void adc_dma_request_after_last_enable(uint32_t adc_periph); /* the DMA engine is disabled after the end of transfer signal from DMA controller is detected */ void adc_dma_request_after_last_disable(uint32_t adc_periph); -/* regular group and inserted group config */ +/* routine sequence and inserted sequence config */ /* configure ADC discontinuous mode */ -void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length); -/* configure the length of regular channel group or inserted channel group */ -void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length); -/* configure ADC regular channel */ -void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); +void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_sequence , uint8_t length); +/* configure the length of routine sequence or inserted sequence */ +void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t length); +/* configure ADC routine channel */ +void adc_routine_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); /* configure ADC inserted channel */ void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); /* configure ADC inserted channel offset */ void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); /* configure ADC external trigger source */ -void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source); +void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t external_trigger_source); /* enable ADC external trigger */ -void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t trigger_mode); +void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t trigger_mode); /* enable ADC software trigger */ -void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group); +void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_sequence); /* configure end of conversion mode */ void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection); /* get channel data */ -/* read ADC regular group data register */ -uint16_t adc_regular_data_read(uint32_t adc_periph); -/* read ADC inserted group data register */ +/* read ADC routine data register */ +uint16_t adc_routine_data_read(uint32_t adc_periph); +/* read ADC inserted data register */ uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); /* watchdog config */ @@ -474,10 +474,10 @@ uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); void adc_watchdog_single_channel_disable(uint32_t adc_periph ); /* enable ADC analog watchdog single channel */ void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel); -/* configure ADC analog watchdog group channel */ -void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel_group); +/* configure ADC analog watchdog sequence */ +void adc_watchdog_sequence_channel_enable(uint32_t adc_periph , uint8_t adc_sequence); /* disable ADC analog watchdog */ -void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group); +void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_sequence); /* configure ADC analog watchdog threshold */ void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold); @@ -487,7 +487,7 @@ FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag); /* clear the ADC flag bits */ void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag); /* get the bit state of ADCx software start conversion */ -FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph); +FlagStatus adc_routine_software_startconv_flag_get(uint32_t adc_periph); /* get the bit state of ADCx software inserted channel start conversion */ FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); /* get the ADC interrupt bits */ @@ -510,7 +510,7 @@ void adc_sync_dma_config(uint32_t dma_mode ); void adc_sync_dma_request_after_last_enable(void); /* configure ADC sync DMA engine issues requests according to the SYNCDMA bits */ void adc_sync_dma_request_after_last_disable(void); -/* read ADC sync regular data register */ -uint32_t adc_sync_regular_data_read(void); +/* read ADC sync routine data register */ +uint32_t adc_sync_routine_data_read(void); #endif /* GD32F4XX_ADC_H */ diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_can.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_can.h index e2e01a06..e42558d0 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_can.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_can.h @@ -406,8 +406,8 @@ typedef struct { ControlStatus time_triggered; /*!< time triggered communication mode */ ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ ControlStatus auto_wake_up; /*!< automatic wake-up mode */ - ControlStatus auto_retrans; /*!< automatic retransmission mode disable */ - ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode disable */ + ControlStatus auto_retrans; /*!< automatic retransmission mode */ + ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ ControlStatus trans_fifo_order; /*!< transmit FIFO order */ uint16_t prescaler; /*!< baudrate prescaler */ } can_parameter_struct; diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_ctc.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_ctc.h index 3fc39654..c07a5db8 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_ctc.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_ctc.h @@ -65,7 +65,6 @@ OF SUCH DAMAGE. #define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ #define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ #define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ -#define CTC_CTL1_USBSOFSEL BIT(30) /*!< USBFS or USBHS SOF signal selection */ #define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ /* CTC_STAT */ @@ -94,15 +93,10 @@ OF SUCH DAMAGE. #define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/ #define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ -/* USBFS or USBHS SOF signal selection definitions */ -#define CTC_USBSOFSEL_USBHS CTC_CTL1_USBSOFSEL /*!< USBHS SOF signal is selected*/ -#define CTC_USBSOFSEL_USBFS ((uint32_t)0x00000000U) /*!< USBFS SOF signal is selected*/ - /* reference signal source selection definitions */ #define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) #define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ #define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */ -#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBSOF is selected */ /* reference signal source prescaler definitions */ #define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) @@ -156,8 +150,6 @@ void ctc_hardware_trim_mode_config(uint32_t hardmode); /* configure reference signal source polarity */ void ctc_refsource_polarity_config(uint32_t polarity); -/* select USBFS or USBHS SOF signal */ -void ctc_usbsof_signal_select(uint32_t usbsof); /* select reference signal source */ void ctc_refsource_signal_select(uint32_t refs); /* configure reference signal source prescaler */ diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_enet.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_enet.h index d3ce5178..517c7c0d 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_enet.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_enet.h @@ -124,7 +124,7 @@ OF SUCH DAMAGE. #define ENET_MAC_HLH REG32((ENET) + 0x0008U) /*!< ethernet MAC hash list high register */ #define ENET_MAC_HLL REG32((ENET) + 0x000CU) /*!< ethernet MAC hash list low register */ #define ENET_MAC_PHY_CTL REG32((ENET) + 0x0010U) /*!< ethernet MAC PHY control register */ -#define ENET_MAC_PHY_DATA REG32((ENET) + 0x0014U) /*!< ethernet MAC MII data register */ +#define ENET_MAC_PHY_DATA REG32((ENET) + 0x0014U) /*!< ethernet MAC PHY data register */ #define ENET_MAC_FCTL REG32((ENET) + 0x0018U) /*!< ethernet MAC flow control register */ #define ENET_MAC_VLT REG32((ENET) + 0x001CU) /*!< ethernet MAC VLAN tag register */ #define ENET_MAC_RWFF REG32((ENET) + 0x0028U) /*!< ethernet MAC remote wakeup frame filter register */ @@ -1113,7 +1113,7 @@ typedef struct #define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-150 MHz; MDC clock= HCLK/62 */ #define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ #define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ -#define ENET_MDC_HCLK_DIV102 MAC_PHY_CTL_CLR(4) /*!< HCLK:150-200 MHz; MDC clock= HCLK/102 */ +#define ENET_MDC_HCLK_DIV102 MAC_PHY_CTL_CLR(4) /*!< HCLK:150-240 MHz; MDC clock= HCLK/102 */ #define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_exmc.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_exmc.h index ce0cca3e..e46ec388 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_exmc.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_exmc.h @@ -6,6 +6,7 @@ \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx \version 2022-03-09, V3.0.0, firmware for GD32F4xx + \version 2022-06-08, V3.0.1, firmware for GD32F4xx */ /* @@ -208,7 +209,7 @@ OF SUCH DAMAGE. /* EXMC_SDARI */ #define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */ #define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */ -#define EXMC_SDARI_REIE BIT(14) /*!< interrupt refresh error enable */ +#define EXMC_SDARI_REIE BIT(14) /*!< refresh error interrupt enable */ /* EXMC_SDSTAT */ #define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */ @@ -330,7 +331,7 @@ typedef struct { uint32_t sdram_device; /*!< device of SDRAM */ uint32_t pipeline_read_delay; /*!< the delay for reading data after CAS latency in HCLK clock cycles */ - uint32_t brust_read_switch; /*!< enable or disable the burst read */ + uint32_t burst_read_switch; /*!< enable or disable the burst read */ uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM banks */ uint32_t write_protection; /*!< enable or disable SDRAM bank write protection function */ uint32_t cas_latency; /*!< configure the SDRAM CAS latency */ @@ -718,7 +719,7 @@ void exmc_norsram_disable(uint32_t exmc_norsram_region); /* NAND */ /* deinitialize EXMC NAND bank */ void exmc_nand_deinit(uint32_t exmc_nand_bank); -/* initialize exmc_norsram_parameter_struct with the default values */ +/* initialize exmc_nand_parameter_struct with the default values */ void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct); /* initialize EXMC NAND bank */ void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); @@ -744,6 +745,8 @@ void exmc_sdram_deinit(uint32_t exmc_sdram_device); void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); /* initialize EXMC SDRAM device */ void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); +/* initialize exmc_sdram_command_parameter_struct with the default values */ +void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct); /* SQPIPSRAM */ /* deinitialize EXMC SQPIPSRAM */ void exmc_sqpipsram_deinit(void); @@ -774,7 +777,7 @@ void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_c void exmc_sdram_refresh_count_set(uint32_t exmc_count); /* set the number of successive auto-refresh command */ void exmc_sdram_autorefresh_number_set(uint32_t exmc_number); -/* config the write protection function */ +/* configure the write protection function */ void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue); /* get the status of SDRAM device0 or device1 */ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device); diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_exti.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_exti.h index e35c485d..294b5872 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_exti.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_exti.h @@ -177,34 +177,33 @@ OF SUCH DAMAGE. #define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */ /* EXTI_PD */ -#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ -#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ -#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ -#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ -#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ -#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ -#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ -#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ -#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ -#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ -#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ -#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ -#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ -#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ -#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ -#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ -#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ -#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ -#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ -#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ -#define EXTI_PD_PD20 BIT(20) /*!< interrupt/event pending status from line 20 */ -#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */ -#define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */ +#define EXTI_PD_PD0 BIT(0) /*!< interrupt pending status from line 0 */ +#define EXTI_PD_PD1 BIT(1) /*!< interrupt pending status from line 1 */ +#define EXTI_PD_PD2 BIT(2) /*!< interrupt pending status from line 2 */ +#define EXTI_PD_PD3 BIT(3) /*!< interrupt pending status from line 3 */ +#define EXTI_PD_PD4 BIT(4) /*!< interrupt pending status from line 4 */ +#define EXTI_PD_PD5 BIT(5) /*!< interrupt pending status from line 5 */ +#define EXTI_PD_PD6 BIT(6) /*!< interrupt pending status from line 6 */ +#define EXTI_PD_PD7 BIT(7) /*!< interrupt pending status from line 7 */ +#define EXTI_PD_PD8 BIT(8) /*!< interrupt pending status from line 8 */ +#define EXTI_PD_PD9 BIT(9) /*!< interrupt pending status from line 9 */ +#define EXTI_PD_PD10 BIT(10) /*!< interrupt pending status from line 10 */ +#define EXTI_PD_PD11 BIT(11) /*!< interrupt pending status from line 11 */ +#define EXTI_PD_PD12 BIT(12) /*!< interrupt pending status from line 12 */ +#define EXTI_PD_PD13 BIT(13) /*!< interrupt pending status from line 13 */ +#define EXTI_PD_PD14 BIT(14) /*!< interrupt pending status from line 14 */ +#define EXTI_PD_PD15 BIT(15) /*!< interrupt pending status from line 15 */ +#define EXTI_PD_PD16 BIT(16) /*!< interrupt pending status from line 16 */ +#define EXTI_PD_PD17 BIT(17) /*!< interrupt pending status from line 17 */ +#define EXTI_PD_PD18 BIT(18) /*!< interrupt pending status from line 18 */ +#define EXTI_PD_PD19 BIT(19) /*!< interrupt pending status from line 19 */ +#define EXTI_PD_PD20 BIT(20) /*!< interrupt pending status from line 20 */ +#define EXTI_PD_PD21 BIT(21) /*!< interrupt pending status from line 21 */ +#define EXTI_PD_PD22 BIT(22) /*!< interrupt pending status from line 22 */ /* constants definitions */ /* EXTI line number */ -typedef enum -{ +typedef enum { EXTI_0 = BIT(0), /*!< EXTI line 0 */ EXTI_1 = BIT(1), /*!< EXTI line 1 */ EXTI_2 = BIT(2), /*!< EXTI line 2 */ @@ -227,29 +226,27 @@ typedef enum EXTI_19 = BIT(19), /*!< EXTI line 19 */ EXTI_20 = BIT(20), /*!< EXTI line 20 */ EXTI_21 = BIT(21), /*!< EXTI line 21 */ - EXTI_22 = BIT(22), /*!< EXTI line 22 */ -}exti_line_enum; + EXTI_22 = BIT(22) /*!< EXTI line 22 */ +} exti_line_enum; /* external interrupt and event */ -typedef enum -{ +typedef enum { EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ EXTI_EVENT /*!< EXTI event mode */ -}exti_mode_enum; +} exti_mode_enum; /* interrupt trigger mode */ -typedef enum -{ +typedef enum { EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */ EXTI_TRIG_NONE /*!< none EXTI edge trigger */ -}exti_trig_type_enum; +} exti_trig_type_enum; /* function declarations */ /* deinitialize the EXTI */ void exti_deinit(void); -/* enable the configuration of EXTI initialize */ +/* initialize the EXTI line x */ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); /* enable the interrupts from EXTI line x */ void exti_interrupt_enable(exti_line_enum linex); @@ -259,19 +256,19 @@ void exti_interrupt_disable(exti_line_enum linex); void exti_event_enable(exti_line_enum linex); /* disable the events from EXTI line x */ void exti_event_disable(exti_line_enum linex); -/* EXTI software interrupt event enable */ +/* enable the software interrupt event from EXTI line x */ void exti_software_interrupt_enable(exti_line_enum linex); -/* EXTI software interrupt event disable */ +/* disable the software interrupt event from EXTI line x */ void exti_software_interrupt_disable(exti_line_enum linex); /* interrupt & flag functions */ -/* get EXTI lines pending flag */ +/* get EXTI line x interrupt pending flag */ FlagStatus exti_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ +/* clear EXTI line x interrupt pending flag */ void exti_flag_clear(exti_line_enum linex); -/* get EXTI lines flag when the interrupt flag is set */ +/* get EXTI line x interrupt pending flag */ FlagStatus exti_interrupt_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ +/* clear EXTI line x interrupt pending flag */ void exti_interrupt_flag_clear(exti_line_enum linex); #endif /* GD32F4XX_EXTI_H */ diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_fmc.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_fmc.h index 8924f818..db4d0f44 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_fmc.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_fmc.h @@ -12,27 +12,27 @@ /* Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -126,17 +126,16 @@ OF SUCH DAMAGE. /* constants definitions */ /* fmc state */ -typedef enum -{ - FMC_READY, /*!< the operation has been completed */ +typedef enum { + FMC_READY = 0, /*!< the operation has been completed */ FMC_BUSY, /*!< the operation is in progress */ FMC_RDDERR, /*!< read D-bus protection error */ FMC_PGSERR, /*!< program sequence error */ FMC_PGMERR, /*!< program size not match error */ FMC_WPERR, /*!< erase/program protection error */ FMC_OPERR, /*!< operation error */ - FMC_TOERR, /*!< timeout error */ -}fmc_state_enum; + FMC_TOERR /*!< timeout error */ +} fmc_state_enum; /* unlock key */ #define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ @@ -181,7 +180,7 @@ typedef enum #define OB_BB_DISABLE OBCTL0_BB(0) /*!< boot from bank0 */ #define OB_BB_ENABLE OBCTL0_BB(1) /*!< boot from bank1 or bank0 if bank1 is void */ -/* option byte software/hardware free watch dog timer */ +/* option byte software/hardware free watch dog timer */ #define OBCTL0_NWDG_HW(regval) (BIT(5) & ((uint32_t)(regval))<< 5) #define OB_FWDGT_SW OBCTL0_NWDG_HW(1) /*!< software free watchdog */ #define OB_FWDGT_HW OBCTL0_NWDG_HW(0) /*!< hardware free watchdog */ @@ -255,12 +254,12 @@ typedef enum #define OB_DRP_23_27 ((uint32_t)0x08000000U) /*!< D-bus read protection protection of sector 23~27 */ #define OB_DRP_ALL ((uint32_t)0x0FFF0FFFU) /*!< D-bus read protection protection of all sectors */ -/* double banks or single bank selection when flash size is 1M bytes */ +/* double banks or single bank selection when flash size is 1M bytes */ #define OBCTL0_DBS(regval) (BIT(30) & ((uint32_t)(regval) << 30U)) #define OB_DBS_DISABLE OBCTL0_DBS(0) /*!< single bank when flash size is 1M bytes */ #define OB_DBS_ENABLE OBCTL0_DBS(1) /*!< double bank when flash size is 1M bytes */ -/* option bytes D-bus read protection mode */ +/* option bytes D-bus read protection mode */ #define OBCTL0_DRP(regval) (BIT(31) & ((uint32_t)(regval) << 31U)) #define OB_DRP_DISABLE OBCTL0_DRP(0) /*!< the WPx bits used as erase/program protection of each sector */ #define OB_DRP_ENABLE OBCTL0_DRP(1) /*!< the WPx bits used as erase/program protection and D-bus read protection of each sector */ @@ -297,7 +296,7 @@ typedef enum #define CTL_SECTOR_NUMBER_23 CTL_SN(27) /*!< sector 23 */ -/* FMC program size */ +/* FMC program size */ #define CTL_PSZ(regval) (BITS(8,9) & ((uint32_t)(regval))<< 8U) #define CTL_PSZ_BYTE CTL_PSZ(0) /*!< FMC program by byte access */ #define CTL_PSZ_HALF_WORD CTL_PSZ(1) /*!< FMC program by half-word access */ @@ -372,15 +371,15 @@ ErrStatus ob_write_protection_disable(uint32_t ob_wp); void ob_drp_enable(uint32_t ob_drp); /* disable erase/program protection and D-bus read protection */ void ob_drp_disable(void); -/* set the option byte security protection level */ +/* configure security protection level */ void ob_security_protection_config(uint8_t ob_spc); -/* write the FMC option byte user */ +/* program the FMC user option byte */ void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby); -/* option byte BOR threshold value */ +/* program the option byte BOR threshold value */ void ob_user_bor_threshold(uint32_t ob_bor_th); /* configure the boot mode */ void ob_boot_mode_config(uint32_t boot_mode); -/* get the FMC option byte user */ +/* get the FMC user option byte */ uint8_t ob_user_get(void); /* get the FMC option byte write protection */ uint16_t ob_write_protection0_get(void); @@ -392,7 +391,7 @@ uint16_t ob_drp0_get(void); uint16_t ob_drp1_get(void); /* get option byte security protection code value */ FlagStatus ob_spc_get(void); -/* get the FMC threshold value */ +/* get the FMC option byte BOR threshold value */ uint8_t ob_user_bor_threshold_get(void); /* FMC interrupts and flags management functions */ @@ -408,9 +407,9 @@ void fmc_interrupt_disable(uint32_t fmc_int); FlagStatus fmc_interrupt_flag_get(uint32_t fmc_int_flag); /* clear the FMC interrupt flag */ void fmc_interrupt_flag_clear(uint32_t fmc_int_flag); -/* return the FMC state */ +/* get the FMC state */ fmc_state_enum fmc_state_get(void); -/* check FMC ready or not */ +/* check whether FMC is ready or not */ fmc_state_enum fmc_ready_wait(uint32_t timeout); #endif /* GD32F4XX_FMC_H */ diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_fwdgt.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_fwdgt.h index 0959b635..a3e6c6d7 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_fwdgt.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_fwdgt.h @@ -41,7 +41,7 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* FWDGT definitions */ -#define FWDGT FWDGT_BASE +#define FWDGT FWDGT_BASE /*!< FWDGT base address */ /* registers definitions */ #define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */ @@ -88,6 +88,9 @@ OF SUCH DAMAGE. #define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ #define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ +/* write value to FWDGT_RLD_RLD bit field */ +#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + /* function declarations */ /* enable write access to FWDGT_PSC and FWDGT_RLD */ void fwdgt_write_enable(void); @@ -96,6 +99,10 @@ void fwdgt_write_disable(void); /* start the free watchdog timer counter */ void fwdgt_enable(void); +/* configure the free watchdog timer counter prescaler value */ +ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value); +/* configure the free watchdog timer counter reload value */ +ErrStatus fwdgt_reload_value_config(uint16_t reload_value); /* reload the counter of FWDGT */ void fwdgt_counter_reload(void); /* configure counter reload value, and prescaler divider value */ diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_i2c.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_i2c.h index 45fac8d9..7d95aacb 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_i2c.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_i2c.h @@ -144,10 +144,10 @@ OF SUCH DAMAGE. #define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */ #define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */ #define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */ -#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag, cleared by software write 0 */ -#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag, cleared by software write 0 */ -#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag, cleared by software write 0 */ -#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag, cleared by software write 0 */ +#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */ +#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */ +#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */ +#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */ /* constants definitions */ /* define the I2C bit position and its register index offset */ diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_misc.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_misc.h index f643d00c..b265608b 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_misc.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_misc.h @@ -41,8 +41,8 @@ OF SUCH DAMAGE. /* constants definitions */ /* set the RAM and FLASH base address */ -#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ -#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ +#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ +#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ /* set the NVIC vector table offset mask */ #define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) @@ -51,24 +51,24 @@ OF SUCH DAMAGE. #define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) /* priority group - define the pre-emption priority and the subpriority */ -#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ -#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ -#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ -#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ -#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ +#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ +#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ +#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ +#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ +#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ /* choose the method to enter or exit the lowpower mode */ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ #define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT #define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP #define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /* choose the systick clock source */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ /* function declarations */ /* set the priority group */ diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_pmu.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_pmu.h index 1c83d5ee..64f6dfd5 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_pmu.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_pmu.h @@ -183,7 +183,7 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd); /* PMU work in deepsleep mode */ void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd); /* PMU work in standby mode */ -void pmu_to_standbymode(uint8_t standbymodecmd); +void pmu_to_standbymode(void); /* enable PMU wakeup pin */ void pmu_wakeup_pin_enable(void); /* disable PMU wakeup pin */ diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_rcu.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_rcu.h index 59838496..c2471ddc 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_rcu.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_rcu.h @@ -398,13 +398,11 @@ OF SUCH DAMAGE. /* RCU_PLLI2S */ #define RCU_PLLI2S_PLLI2SN BITS(6,14) /*!< the PLLI2S VCO clock multi factor */ -#define RCU_PLLI2S_PLLI2SQ BITS(24,27) /*!< the PLLI2S Q output frequency division factor from PLLI2S VCO clock */ #define RCU_PLLI2S_PLLI2SR BITS(28,30) /*!< the PLLI2S R output frequency division factor from PLLI2S VCO clock */ /* RCU_PLLSAI */ #define RCU_PLLSAI_PLLSAIN BITS(6,14) /*!< the PLLSAI VCO clock multi factor */ #define RCU_PLLSAI_PLLSAIP BITS(16,17) /*!< the PLLSAI P output frequency division factor from PLLSAI VCO clock */ -#define RCU_PLLSAI_PLLSAIQ BITS(24,27) /*!< the PLLSAI Q output frequency division factor from PLLSAI VCO clock */ #define RCU_PLLSAI_PLLSAIR BITS(28,30) /*!< the PLLSAI R output frequency division factor from PLLSAI VCO clock */ /* RCU_CFG1 */ @@ -1076,6 +1074,7 @@ typedef enum /* function declarations */ +/* peripherals clock configure functions */ /* deinitialize the RCU */ void rcu_deinit(void); /* enable the peripherals clock */ @@ -1095,6 +1094,7 @@ void rcu_bkp_reset_enable(void); /* disable the BKP reset */ void rcu_bkp_reset_disable(void); +/* system and peripherals clock source, system reset configure functions */ /* configure the system clock source */ void rcu_system_clock_source_config(uint32_t ck_sys); /* get the system clock source */ @@ -1130,20 +1130,7 @@ void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler); /* configure the TLI clock division selection */ void rcu_tli_clock_div_config(uint32_t pllsai_r_div); - -/* get the clock stabilization and periphral reset flags */ -FlagStatus rcu_flag_get(rcu_flag_enum flag); -/* clear the reset flag */ -void rcu_all_reset_flag_clear(void); -/* get the clock stabilization interrupt and ckm flags */ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); -/* clear the interrupt flags */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag); -/* enable the stabilization interrupt */ -void rcu_interrupt_enable(rcu_int_enum interrupt); -/* disable the stabilization interrupt */ -void rcu_interrupt_disable(rcu_int_enum interrupt); - +/* LXTAL, IRC8M, PLL and other oscillator configure functions */ /* configure the LXTAL drive capability */ void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); /* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ @@ -1156,11 +1143,6 @@ void rcu_osci_off(rcu_osci_type_enum osci); void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); /* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); -/* enable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_enable(void); -/* disable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_disable(void); - /* set the IRC16M adjust value */ void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval); /* configure the spread spectrum modulation for the main PLL clock */ @@ -1168,13 +1150,34 @@ void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, /* enable the spread spectrum modulation for the main PLL clock */ void rcu_spread_spectrum_enable(void); /* disable the spread spectrum modulation for the main PLL clock */ -void rcu_spread_spectrum_disable(void); +void rcu_spread_spectrum_disable(void); + +/* clock monitor configure functions */ +/* enable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_enable(void); +/* disable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_disable(void); + +/* voltage configure and clock frequency get functions */ /* unlock the voltage key */ void rcu_voltage_key_unlock(void); /* set the deep sleep mode voltage */ void rcu_deepsleep_voltage_set(uint32_t dsvol); - /* get the system clock, bus and peripheral clock frequency */ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); +/* flag & interrupt functions */ +/* get the clock stabilization and periphral reset flags */ +FlagStatus rcu_flag_get(rcu_flag_enum flag); +/* clear the reset flag */ +void rcu_all_reset_flag_clear(void); +/* get the clock stabilization interrupt and ckm flags */ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); +/* clear the interrupt flags */ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag); +/* enable the stabilization interrupt */ +void rcu_interrupt_enable(rcu_int_enum interrupt); +/* disable the stabilization interrupt */ +void rcu_interrupt_disable(rcu_int_enum interrupt); + #endif /* GD32F4XX_RCU_H */ diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_spi.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_spi.h index a0478a66..d5696787 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_spi.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_spi.h @@ -54,27 +54,27 @@ OF SUCH DAMAGE. #define I2S2_ADD (I2S_ADD_BASE + 0x00000C00U) /* SPI registers definitions */ -#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ -#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ -#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ -#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ -#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ -#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ -#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ -#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ -#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ -#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad mode control register */ +#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */ +#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/ +#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */ +#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */ +#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */ +#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */ +#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */ +#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */ +#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */ +#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register */ /* I2S_ADD registers definitions */ -#define I2S_ADD_CTL0(i2sx_add) REG32((i2sx_add) + 0x00U) /*!< I2S_ADD control register 0 */ -#define I2S_ADD_CTL1(i2sx_add) REG32((i2sx_add) + 0x04U) /*!< I2S_ADD control register 1*/ -#define I2S_ADD_STAT(i2sx_add) REG32((i2sx_add) + 0x08U) /*!< I2S_ADD status register */ -#define I2S_ADD_DATA(i2sx_add) REG32((i2sx_add) + 0x0CU) /*!< I2S_ADD data register */ -#define I2S_ADD_CRCPOLY(i2sx_add) REG32((i2sx_add) + 0x10U) /*!< I2S_ADD CRC polynomial register */ -#define I2S_ADD_RCRC(i2sx_add) REG32((i2sx_add) + 0x14U) /*!< I2S_ADD receive CRC register */ -#define I2S_ADD_TCRC(i2sx_add) REG32((i2sx_add) + 0x18U) /*!< I2S_ADD transmit CRC register */ -#define I2S_ADD_I2SCTL(i2sx_add) REG32((i2sx_add) + 0x1CU) /*!< I2S_ADD I2S control register */ -#define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x20U) /*!< I2S_ADD I2S clock prescaler register */ +#define I2S_ADD_CTL0(i2sx_add) REG32((i2sx_add) + 0x00000000U) /*!< I2S_ADD control register 0 */ +#define I2S_ADD_CTL1(i2sx_add) REG32((i2sx_add) + 0x00000004U) /*!< I2S_ADD control register 1*/ +#define I2S_ADD_STAT(i2sx_add) REG32((i2sx_add) + 0x00000008U) /*!< I2S_ADD status register */ +#define I2S_ADD_DATA(i2sx_add) REG32((i2sx_add) + 0x0000000CU) /*!< I2S_ADD data register */ +#define I2S_ADD_CRCPOLY(i2sx_add) REG32((i2sx_add) + 0x00000010U) /*!< I2S_ADD CRC polynomial register */ +#define I2S_ADD_RCRC(i2sx_add) REG32((i2sx_add) + 0x00000014U) /*!< I2S_ADD receive CRC register */ +#define I2S_ADD_TCRC(i2sx_add) REG32((i2sx_add) + 0x00000018U) /*!< I2S_ADD transmit CRC register */ +#define I2S_ADD_I2SCTL(i2sx_add) REG32((i2sx_add) + 0x0000001CU) /*!< I2S_ADD I2S control register */ +#define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x00000020U) /*!< I2S_ADD I2S clock prescaler register */ /* bits definitions */ /* SPI_CTL0 */ @@ -326,6 +326,10 @@ void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); uint16_t spi_i2s_data_receive(uint32_t spi_periph); /* configure SPI bidirectional transfer direction */ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); +/* configure i2s full duplex mode */ +void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl, uint32_t i2s_frameformat); +/* clear TI Mode Format Error flag status */ +void spi_i2s_format_error_clear(uint32_t spi_periph, uint32_t flag); /* SPI CRC functions */ /* set SPI CRC polynomial */ @@ -340,6 +344,8 @@ void spi_crc_off(uint32_t spi_periph); void spi_crc_next(uint32_t spi_periph); /* get SPI CRC send value or receive value */ uint16_t spi_crc_get(uint32_t spi_periph, uint8_t spi_crc); +/* clear SPI CRC error flag status */ +void spi_crc_error_clear(uint32_t spi_periph); /* SPI TI mode functions */ /* enable SPI TI mode */ @@ -347,33 +353,28 @@ void spi_ti_mode_enable(uint32_t spi_periph); /* disable SPI TI mode */ void spi_ti_mode_disable(uint32_t spi_periph); -/* configure i2s full duplex mode */ -void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl, uint32_t i2s_frameformat); - /* quad wire SPI functions */ /* enable quad wire SPI */ -void qspi_enable(uint32_t spi_periph); +void spi_quad_enable(uint32_t spi_periph); /* disable quad wire SPI */ -void qspi_disable(uint32_t spi_periph); +void spi_quad_disable(uint32_t spi_periph); /* enable quad wire SPI write */ -void qspi_write_enable(uint32_t spi_periph); +void spi_quad_write_enable(uint32_t spi_periph); /* enable quad wire SPI read */ -void qspi_read_enable(uint32_t spi_periph); +void spi_quad_read_enable(uint32_t spi_periph); /* enable SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_enable(uint32_t spi_periph); +void spi_quad_io23_output_enable(uint32_t spi_periph); /* disable SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_disable(uint32_t spi_periph); +void spi_quad_io23_output_disable(uint32_t spi_periph); -/* flag & interrupt functions */ +/* flag and interrupt functions */ +/* get SPI and I2S flag status */ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); /* enable SPI and I2S interrupt */ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int); +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); /* disable SPI and I2S interrupt */ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int); +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); /* get SPI and I2S interrupt status*/ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int); -/* get SPI and I2S flag status */ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t spi_i2s_flag); -/* clear SPI CRC error flag status */ -void spi_crc_error_clear(uint32_t spi_periph); +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); #endif /* GD32F4XX_SPI_H */ diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_timer.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_timer.h index c4c72372..eb7be5c6 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_timer.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_timer.h @@ -561,9 +561,9 @@ typedef struct /* slave mode control */ #define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ -#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ -#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ -#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ +#define TIMER_QUAD_DECODER_MODE0 SMCFG_SMC(1) /*!< quadrature decoder mode 0 */ +#define TIMER_QUAD_DECODER_MODE1 SMCFG_SMC(2) /*!< quadrature decoder mode 1 */ +#define TIMER_QUAD_DECODER_MODE2 SMCFG_SMC(3) /*!< quadrature decoder mode 2 */ #define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ #define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ #define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_trng.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_trng.h index 05025000..dc6cd3af 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_trng.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_trng.h @@ -44,14 +44,14 @@ OF SUCH DAMAGE. #define TRNG TRNG_BASE /* registers definitions */ -#define TRNG_CTL REG32(TRNG + 0x00U) /*!< control register */ -#define TRNG_STAT REG32(TRNG + 0x04U) /*!< status register */ -#define TRNG_DATA REG32(TRNG + 0x08U) /*!< data register */ +#define TRNG_CTL REG32(TRNG + 0x00000000U) /*!< control register */ +#define TRNG_STAT REG32(TRNG + 0x00000004U) /*!< status register */ +#define TRNG_DATA REG32(TRNG + 0x00000008U) /*!< data register */ /* bits definitions */ /* TRNG_CTL */ #define TRNG_CTL_TRNGEN BIT(2) /*!< TRNG enable bit */ -#define TRNG_CTL_IE BIT(3) /*!< interrupt enable bit */ +#define TRNG_CTL_TRNGIE BIT(3) /*!< interrupt enable bit */ /* TRNG_STAT */ #define TRNG_STAT_DRDY BIT(0) /*!< random data ready status bit */ @@ -61,45 +61,43 @@ OF SUCH DAMAGE. #define TRNG_STAT_SEIF BIT(6) /*!< seed error interrupt flag */ /* TRNG_DATA */ -#define TRNG_DATA_TRNDATA BITS(0,31) /*!< 32-Bit Random data */ +#define TRNG_DATA_TRNGDATA BITS(0,31) /*!< 32-Bit Random data */ /* constants definitions */ -/* trng status flag */ -typedef enum -{ +/* TRNG status flag */ +typedef enum { TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random Data ready status */ TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */ TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */ -}trng_flag_enum; +} trng_flag_enum; -/* trng inerrupt flag */ -typedef enum -{ +/* TRNG inerrupt flag */ +typedef enum { TRNG_INT_FLAG_CEIF = TRNG_STAT_CEIF, /*!< clock error interrupt flag */ TRNG_INT_FLAG_SEIF = TRNG_STAT_SEIF /*!< seed error interrupt flag */ -}trng_int_flag_enum; +} trng_int_flag_enum; /* function declarations */ /* initialization functions */ -/* deinitialize the TRNG */ +/* reset TRNG */ void trng_deinit(void); -/* enable the TRNG interface */ +/* enable TRNG */ void trng_enable(void); -/* disable the TRNG interface */ +/* disable TRNG */ void trng_disable(void); /* get the true random data */ uint32_t trng_get_true_random_data(void); -/* flag & interrupt functions */ -/* trng interrupt enable */ +/* interrupt & flag functions */ +/* enable TRNG interrupt */ void trng_interrupt_enable(void); -/* trng interrupt disable */ +/* disable TRNG interrupt */ void trng_interrupt_disable(void); -/* get the trng status flags */ +/* get TRNG flag status */ FlagStatus trng_flag_get(trng_flag_enum flag); -/* get the trng interrupt flags */ +/* get TRNG interrupt flag status */ FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag); -/* clear the trng interrupt flags */ +/* clear TRNG interrupt flag status */ void trng_interrupt_flag_clear(trng_int_flag_enum int_flag); #endif /* GD32F4XX_TRNG_H */ diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_usart.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_usart.h index 303ec662..6f55eeee 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_usart.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_usart.h @@ -65,94 +65,94 @@ OF SUCH DAMAGE. /* bits definitions */ /* USARTx_STAT0 */ -#define USART_STAT0_PERR BIT(0) /*!< parity error flag */ -#define USART_STAT0_FERR BIT(1) /*!< frame error flag */ -#define USART_STAT0_NERR BIT(2) /*!< noise error flag */ -#define USART_STAT0_ORERR BIT(3) /*!< overrun error */ -#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ -#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ -#define USART_STAT0_TC BIT(6) /*!< transmission complete */ -#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ -#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ -#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ +#define USART_STAT0_PERR BIT(0) /*!< parity error flag */ +#define USART_STAT0_FERR BIT(1) /*!< frame error flag */ +#define USART_STAT0_NERR BIT(2) /*!< noise error flag */ +#define USART_STAT0_ORERR BIT(3) /*!< overrun error */ +#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ +#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ +#define USART_STAT0_TC BIT(6) /*!< transmission complete */ +#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ +#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ +#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ /* USARTx_DATA */ -#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ +#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ /* USARTx_BAUD */ -#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ -#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ +#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ +#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ /* USARTx_CTL0 */ -#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ -#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ -#define USART_CTL0_REN BIT(2) /*!< receiver enable */ -#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ -#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ -#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ -#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ -#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ -#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ -#define USART_CTL0_PM BIT(9) /*!< parity mode */ -#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ -#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ -#define USART_CTL0_WL BIT(12) /*!< word length */ -#define USART_CTL0_UEN BIT(13) /*!< USART enable */ -#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ +#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ +#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ +#define USART_CTL0_REN BIT(2) /*!< enable receiver */ +#define USART_CTL0_TEN BIT(3) /*!< enable transmitter */ +#define USART_CTL0_IDLEIE BIT(4) /*!< enable idle line detected interrupt */ +#define USART_CTL0_RBNEIE BIT(5) /*!< enable read data buffer not empty interrupt and overrun error interrupt */ +#define USART_CTL0_TCIE BIT(6) /*!< enable transmission complete interrupt */ +#define USART_CTL0_TBEIE BIT(7) /*!< enable transmitter buffer empty interrupt */ +#define USART_CTL0_PERRIE BIT(8) /*!< enable parity error interrupt */ +#define USART_CTL0_PM BIT(9) /*!< parity mode */ +#define USART_CTL0_PCEN BIT(10) /*!< enable parity check function */ +#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ +#define USART_CTL0_WL BIT(12) /*!< word length */ +#define USART_CTL0_UEN BIT(13) /*!< enable USART */ +#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ /* USARTx_CTL1 */ -#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ -#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ -#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ -#define USART_CTL1_CLEN BIT(8) /*!< CK length */ -#define USART_CTL1_CPH BIT(9) /*!< CK phase */ -#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ -#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ -#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ -#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ +#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ +#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ +#define USART_CTL1_LBDIE BIT(6) /*!< enable LIN break detected interrupt */ +#define USART_CTL1_CLEN BIT(8) /*!< CK length */ +#define USART_CTL1_CPH BIT(9) /*!< CK phase */ +#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ +#define USART_CTL1_CKEN BIT(11) /*!< enable CK pin */ +#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ +#define USART_CTL1_LMEN BIT(14) /*!< enable LIN mode */ /* USARTx_CTL2 */ -#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ -#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ -#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ -#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ -#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ -#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ -#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ -#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ -#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ -#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ -#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ -#define USART_CTL2_OSB BIT(11) /*!< one sample bit method */ +#define USART_CTL2_ERRIE BIT(0) /*!< enable error interrupt */ +#define USART_CTL2_IREN BIT(1) /*!< enable IrDA mode */ +#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ +#define USART_CTL2_HDEN BIT(3) /*!< enable half-duplex */ +#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ +#define USART_CTL2_SCEN BIT(5) /*!< enable smartcard mode */ +#define USART_CTL2_DENR BIT(6) /*!< enable DMA request for reception */ +#define USART_CTL2_DENT BIT(7) /*!< enable DMA request for transmission */ +#define USART_CTL2_RTSEN BIT(8) /*!< enable RTS */ +#define USART_CTL2_CTSEN BIT(9) /*!< enable CTS */ +#define USART_CTL2_CTSIE BIT(10) /*!< enable CTS interrupt */ +#define USART_CTL2_OSB BIT(11) /*!< one sample bit method */ /* USARTx_GP */ -#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ -#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ +#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ /* USARTx_CTL3 */ -#define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ -#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ -#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ -#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ -#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ -#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ -#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ -#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ +#define USART_CTL3_RTEN BIT(0) /*!< enable receiver timeout */ +#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ +#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ +#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ +#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ +#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ +#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ +#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ /* USARTx_RT */ -#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ -#define USART_RT_BL BITS(24,31) /*!< block length */ +#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ +#define USART_RT_BL BITS(24,31) /*!< block length */ /* USARTx_STAT1 */ -#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ -#define USART_STAT1_EBF BIT(12) /*!< end of block flag */ -#define USART_STAT1_BSY BIT(16) /*!< busy flag */ +#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ +#define USART_STAT1_EBF BIT(12) /*!< end of block flag */ +#define USART_STAT1_BSY BIT(16) /*!< busy flag */ /* USARTx_CHC */ -#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ -#define USART_CHC_PCM BIT(1) /*!< parity check coherence mode */ -#define USART_CHC_BCM BIT(2) /*!< break frame coherence mode */ -#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ +#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ +#define USART_CHC_PCM BIT(1) /*!< parity check coherence mode */ +#define USART_CHC_BCM BIT(2) /*!< break frame coherence mode */ +#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ /* constants definitions */ /* define the USART bit position and its register index offset */ @@ -165,13 +165,13 @@ OF SUCH DAMAGE. #define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) /* register offset */ -#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ -#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ -#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ -#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ -#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ -#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ -#define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */ +#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ +#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ +#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ +#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ +#define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */ /* USART flags */ typedef enum { @@ -233,7 +233,7 @@ typedef enum { USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */ } usart_interrupt_enum; -/* USART invert configure */ +/* configure USART invert */ typedef enum { /* data bit level inversion */ USART_DINV_ENABLE, /*!< data bit level inversion */ @@ -246,12 +246,12 @@ typedef enum { USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ } usart_invert_enum; -/* USART receiver configure */ +/* configure USART receiver */ #define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) #define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ #define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ -/* USART transmitter configure */ +/* configure USART transmitter */ #define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) #define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ #define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ @@ -304,32 +304,32 @@ typedef enum { #define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ #define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ -/* USART DMA request for receive configure */ +/* configure USART DMA request for receive */ #define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) -#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ -#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ +#define USART_RECEIVE_DMA_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ +#define USART_RECEIVE_DMA_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ -/* USART DMA request for transmission configure */ +/* configure USART DMA request for transmission */ #define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) -#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ -#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ +#define USART_TRANSMIT_DMA_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ +#define USART_TRANSMIT_DMA_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ -/* USART RTS configure */ +/* configure USART RTS */ #define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ -#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ +#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< enable RTS */ +#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< disable RTS */ -/* USART CTS configure */ +/* configure USART CTS */ #define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ -#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ +#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< enable CTS */ +#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< disable CTS */ -/* USART one sample bit method configure */ +/* configure USART one sample bit method */ #define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11)) #define USART_OSB_1bit CTL2_OSB(1) /*!< 1 bit */ #define USART_OSB_3bit CTL2_OSB(0) /*!< 3 bits */ -/* USART IrDA low-power enable */ +/* enable USART IrDA low-power */ #define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) #define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ #define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ @@ -391,7 +391,7 @@ void usart_receiver_timeout_disable(uint32_t usart_periph); /* configure receiver timeout threshold */ void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); /* USART transmit data function */ -void usart_data_transmit(uint32_t usart_periph, uint32_t data); +void usart_data_transmit(uint32_t usart_periph, uint16_t data); /* USART receive data function */ uint16_t usart_data_receive(uint32_t usart_periph); @@ -431,7 +431,7 @@ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32 /* smartcard communication */ /* configure guard time value in smartcard mode */ -void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); +void usart_guard_time_config(uint32_t usart_periph, uint8_t guat); /* enable smartcard mode */ void usart_smartcard_mode_enable(uint32_t usart_periph); /* disable smartcard mode */ @@ -441,9 +441,9 @@ void usart_smartcard_mode_nack_enable(uint32_t usart_periph); /* disable NACK in smartcard mode */ void usart_smartcard_mode_nack_disable(uint32_t usart_periph); /* configure smartcard auto-retry number */ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint8_t scrtnum); /* configure block length */ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl); +void usart_block_length_config(uint32_t usart_periph, uint8_t bl); /* IrDA communication */ /* enable IrDA mode */ diff --git a/gd32f4xx/standard_peripheral/include/gd32f4xx_wwdgt.h b/gd32f4xx/standard_peripheral/include/gd32f4xx_wwdgt.h index 3a55b93f..69cdbff3 100644 --- a/gd32f4xx/standard_peripheral/include/gd32f4xx_wwdgt.h +++ b/gd32f4xx/standard_peripheral/include/gd32f4xx_wwdgt.h @@ -41,7 +41,7 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* WWDGT definitions */ -#define WWDGT WWDGT_BASE +#define WWDGT WWDGT_BASE /*!< WWDGT base address */ /* registers definitions */ #define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */ @@ -68,6 +68,11 @@ OF SUCH DAMAGE. #define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ #define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ +/* write value to WWDGT_CTL_CNT bit field */ +#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) +/* write value to WWDGT_CFG_WIN bit field */ +#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + /* function declarations */ /* reset the window watchdog timer configuration */ void wwdgt_deinit(void); diff --git a/gd32f4xx/standard_peripheral/source/gd32f4xx_adc.c b/gd32f4xx/standard_peripheral/source/gd32f4xx_adc.c index e7384860..3ea466fc 100644 --- a/gd32f4xx/standard_peripheral/source/gd32f4xx_adc.c +++ b/gd32f4xx/standard_peripheral/source/gd32f4xx_adc.c @@ -37,29 +37,29 @@ OF SUCH DAMAGE. #include "gd32f4xx_adc.h" -#define REGULAR_TRIGGER_MODE ((uint32_t)28U) +#define ROUTINE_TRIGGER_MODE ((uint32_t)28U) #define INSERTED_TRIGGER_MODE ((uint32_t)20U) /* discontinuous mode macro*/ -#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) +#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) -/* ADC regular channel macro */ -#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U) -#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U) -#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) -#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U) +/* ADC routine channel macro */ +#define ADC_ROUTINE_CHANNEL_RANK_SIX ((uint8_t)6U) +#define ADC_ROUTINE_CHANNEL_RANK_TWELVE ((uint8_t)12U) +#define ADC_ROUTINE_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) +#define ADC_ROUTINE_CHANNEL_RANK_LENGTH ((uint8_t)5U) /* ADC sampling time macro */ -#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) -#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) -#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) +#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) +#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) +#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) /* ADC inserted channel macro */ -#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) -#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) +#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) +#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) /* ADC inserted channel offset macro */ -#define ADC_OFFSET_LENGTH ((uint8_t)3U) -#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) +#define ADC_OFFSET_LENGTH ((uint8_t)3U) +#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) /*! \brief reset ADC @@ -100,7 +100,7 @@ void adc_clock_config(uint32_t prescaler) \param[in] function: the function to config only one parameter can be selected which is shown as below: \arg ADC_SCAN_MODE: scan mode select - \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically + \arg ADC_INSERTED_CHANNEL_AUTO: inserted sequence convert automatically \arg ADC_CONTINUOUS_MODE: continuous mode select \param[in] newvalue: ENABLE or DISABLE \param[out] none @@ -114,7 +114,7 @@ void adc_special_function_config(uint32_t adc_periph, uint32_t function, Control ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; } if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { - /* enable inserted channel group convert automatically */ + /* enable inserted sequence convert automatically */ ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; } if(0U != (function & ADC_CONTINUOUS_MODE)) { @@ -127,7 +127,7 @@ void adc_special_function_config(uint32_t adc_periph, uint32_t function, Control ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; } if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { - /* disable inserted channel group convert automatically */ + /* disable inserted sequence convert automatically */ ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; } if(0U != (function & ADC_CONTINUOUS_MODE)) { @@ -345,7 +345,7 @@ void adc_dma_mode_disable(uint32_t adc_periph) } /*! - \brief when DMA=1, the DMA engine issues a request at end of each regular conversion + \brief when DMA=1, the DMA engine issues a request at end of each routine conversion \param[in] adc_periph: ADCx,x=0,1,2 \param[out] none \retval none @@ -369,58 +369,58 @@ void adc_dma_request_after_last_disable(uint32_t adc_periph) /*! \brief configure ADC discontinuous mode \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group + \param[in] adc_sequence: select the sequence only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of routine & inserted channel \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 - for regular channel ,the number has no effect for inserted channel + for routine sequence ,the number has no effect for inserted sequence \param[out] none \retval none */ -void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length) +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_sequence, uint8_t length) { - /* disable discontinuous mode of regular & inserted channel */ + /* disable discontinuous mode of routine & inserted channel */ ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); - switch(adc_channel_group) { - case ADC_REGULAR_CHANNEL: + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: /* config the number of conversions in discontinuous mode */ ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); if((length <= 8U) && (length >= 1U)) { ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); } - /* enable regular channel group discontinuous mode */ + /* enable routine sequence discontinuous mode */ ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; break; case ADC_INSERTED_CHANNEL: - /* enable inserted channel group discontinuous mode */ + /* enable inserted sequence discontinuous mode */ ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; break; case ADC_CHANNEL_DISCON_DISABLE: - /* disable discontinuous mode of regular & inserted channel */ + /* disable discontinuous mode of routine & inserted channel */ default: break; } } /*! - \brief configure the length of regular channel group or inserted channel group + \brief configure the length of routine sequence or inserted sequence \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group + \param[in] adc_sequence: select the sequence only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence \param[in] length: the length of the channel - regular channel 1-16 + routine channel 1-16 inserted channel 1-4 \param[out] none \retval none */ -void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t length) { - switch(adc_channel_group) { - case ADC_REGULAR_CHANNEL: + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: if((length >= 1U) && (length <= 16U)) { ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); @@ -438,12 +438,12 @@ void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, u } /*! - \brief configure ADC regular channel + \brief configure ADC routine channel \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] rank: the regular group sequencer rank,this parameter must be between 0 to 15 + \param[in] rank: the routine sequence rank,this parameter must be between 0 to 15 \param[in] adc_channel: the selected ADC channel only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..18): ADC Channelx + \arg ADC_CHANNEL_x(x=0..18): ADC channelx \param[in] sample_time: the sample time value only one parameter can be selected which is shown as below: \arg ADC_SAMPLETIME_3: 3 cycles @@ -457,45 +457,45 @@ void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, u \param[out] none \retval none */ -void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) +void adc_routine_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) { uint32_t rsq, sampt; - /* ADC regular sequence config */ - if(rank < ADC_REGULAR_CHANNEL_RANK_SIX) { - /* the regular group sequence rank is smaller than six */ + /* ADC routine sequence config */ + if(rank < ADC_ROUTINE_CHANNEL_RANK_SIX) { + /* the routine sequence rank is smaller than six */ rsq = ADC_RSQ2(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * rank))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * rank)); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * rank))); + /* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */ + rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * rank)); ADC_RSQ2(adc_periph) = rsq; - } else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE) { - /* the regular group sequence rank is smaller than twelve */ + } else if(rank < ADC_ROUTINE_CHANNEL_RANK_TWELVE) { + /* the routine sequence rank is smaller than twelve */ rsq = ADC_RSQ1(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_SIX)))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_SIX))); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_SIX)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */ + rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_SIX))); ADC_RSQ1(adc_periph) = rsq; - } else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN) { - /* the regular group sequence rank is smaller than sixteen */ + } else if(rank < ADC_ROUTINE_CHANNEL_RANK_SIXTEEN) { + /* the routine sequence rank is smaller than sixteen */ rsq = ADC_RSQ0(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_TWELVE)))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_TWELVE))); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_TWELVE)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */ + rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_TWELVE))); ADC_RSQ0(adc_periph) = rsq; } else { } /* ADC sampling time config */ if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) { - /* the regular group sequence rank is smaller than ten */ + /* the routine sequence rank is smaller than ten */ sampt = ADC_SAMPT1(adc_periph); sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel))); /* channel sample time set*/ sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel)); ADC_SAMPT1(adc_periph) = sampt; } else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN) { - /* the regular group sequence rank is smaller than eighteen */ + /* the routine sequence rank is smaller than eighteen */ sampt = ADC_SAMPT0(adc_periph); sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); /* channel sample time set*/ @@ -508,7 +508,7 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c /*! \brief configure ADC inserted channel \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 + \param[in] rank: the inserted sequence rank,this parameter must be between 0 to 3 \param[in] adc_channel: the selected ADC channel only one parameter can be selected which is shown as below: \arg ADC_CHANNEL_x(x=0..18): ADC Channelx @@ -530,9 +530,9 @@ void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_ uint8_t inserted_length; uint32_t isq, sampt; - /* get inserted channel group length */ + /* get inserted sequence length */ inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); - /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */ + /* the channel number is written to these bits to select a channel as the nth conversion in the inserted sequence */ if(rank < 4U) { isq = ADC_ISQ(adc_periph); isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH))); @@ -542,14 +542,14 @@ void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_ /* ADC sampling time config */ if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) { - /* the inserted group sequence rank is smaller than ten */ + /* the inserted sequence rank is smaller than ten */ sampt = ADC_SAMPT1(adc_periph); sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel))); /* channel sample time set*/ sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel); ADC_SAMPT1(adc_periph) = sampt; } else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN) { - /* the inserted group sequence rank is smaller than eighteen */ + /* the inserted sequence rank is smaller than eighteen */ sampt = ADC_SAMPT0(adc_periph); sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); /* channel sample time set*/ @@ -591,30 +591,30 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_ch /*! \brief configure ADC external trigger source \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group + \param[in] adc_sequence: select the sequence only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] external_trigger_source: regular or inserted group trigger source - for regular channel: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \param[in] external_trigger_source: routine or inserted sequence trigger source + for routine sequence: only one parameter can be selected which is shown as below: - \arg ADC_EXTTRIG_REGULAR_T0_CH0: external trigger timer 0 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T0_CH1: external trigger timer 0 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T0_CH2: external trigger timer 0 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH1: external trigger timer 1 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH2: external trigger timer 1 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH3: external trigger timer 1 CC3 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_TRGO: external trigger timer 1 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T2_CH0 : external trigger timer 2 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T2_TRGO : external trigger timer 2 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T3_CH3: external trigger timer 3 CC3 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH0: external trigger timer 4 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH1: external trigger timer 4 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH2: external trigger timer 4 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T7_CH0: external trigger timer 7 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T7_TRGO: external trigger timer 7 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_EXTI_11: external trigger extiline 11 select for regular channel - for inserted channel: + \arg ADC_EXTTRIG_ROUTINE_T0_CH0: external trigger timer 0 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T0_CH1: external trigger timer 0 CC1 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T0_CH2: external trigger timer 0 CC2 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_CH1: external trigger timer 1 CC1 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_CH2: external trigger timer 1 CC2 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_CH3: external trigger timer 1 CC3 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_TRGO: external trigger timer 1 TRGO event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T2_CH0 : external trigger timer 2 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T2_TRGO : external trigger timer 2 TRGO event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T3_CH3: external trigger timer 3 CC3 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T4_CH0: external trigger timer 4 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T4_CH1: external trigger timer 4 CC1 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T4_CH2: external trigger timer 4 CC2 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T7_CH0: external trigger timer 7 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T7_TRGO: external trigger timer 7 TRGO event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_EXTI_11: external trigger extiline 11 select for routine sequence + for inserted sequence: only one parameter can be selected which is shown as below: \arg ADC_EXTTRIG_INSERTED_T0_CH3: timer0 capture compare 3 \arg ADC_EXTTRIG_INSERTED_T0_TRGO: timer0 TRGO event @@ -635,16 +635,16 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_ch \param[out] none \retval none */ -void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t external_trigger_source) { - switch(adc_channel_group) { - case ADC_REGULAR_CHANNEL: - /* configure ADC regular group external trigger source */ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* configure ADC routine sequence external trigger source */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; break; case ADC_INSERTED_CHANNEL: - /* configure ADC inserted group external trigger source */ + /* configure ADC inserted sequence external trigger source */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; break; @@ -656,10 +656,10 @@ void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel /*! \brief enable ADC external trigger \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group + \param[in] adc_sequence: select the sequence only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence \param[in] trigger_mode: external trigger mode only one parameter can be selected which is shown as below: \arg EXTERNAL_TRIGGER_DISABLE: external trigger disable @@ -669,16 +669,16 @@ void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel \param[out] none \retval none */ -void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t trigger_mode) +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t trigger_mode) { - switch(adc_channel_group) { - case ADC_REGULAR_CHANNEL: - /* configure ADC regular channel group external trigger mode */ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* configure ADC routine sequence external trigger mode */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMRC); - ADC_CTL1(adc_periph) |= (uint32_t)(trigger_mode << REGULAR_TRIGGER_MODE); + ADC_CTL1(adc_periph) |= (uint32_t)(trigger_mode << ROUTINE_TRIGGER_MODE); break; case ADC_INSERTED_CHANNEL: - /* configure ADC inserted channel group external trigger mode */ + /* configure ADC inserted sequence external trigger mode */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMIC); ADC_CTL1(adc_periph) |= (uint32_t)(trigger_mode << INSERTED_TRIGGER_MODE); break; @@ -690,22 +690,22 @@ void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, /*! \brief enable ADC software trigger \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group + \param[in] adc_sequence: select the sequence only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence \param[out] none \retval none */ -void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group) +void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_sequence) { - switch(adc_channel_group) { - case ADC_REGULAR_CHANNEL: - /* enable ADC regular channel group software trigger */ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* enable ADC routine sequence software trigger */ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWRCST; break; case ADC_INSERTED_CHANNEL: - /* enable ADC inserted channel group software trigger */ + /* enable ADC inserted sequence software trigger */ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWICST; break; default: @@ -718,8 +718,8 @@ void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group) \param[in] adc_periph: ADCx,x=0,1,2 \param[in] end_selection: end of conversion mode only one parameter can be selected which is shown as below: - \arg ADC_EOC_SET_SEQUENCE: only at the end of a sequence of regular conversions, the EOC bit is set.Overflow detection is disabled unless DMA=1. - \arg ADC_EOC_SET_CONVERSION: at the end of each regular conversion, the EOC bit is set.Overflow is detected automatically. + \arg ADC_EOC_SET_SEQUENCE: only at the end of a sequence of routine conversions, the EOC bit is set.Overflow detection is disabled unless DMA=1. + \arg ADC_EOC_SET_CONVERSION: at the end of each routine conversion, the EOC bit is set.Overflow is detected automatically. \param[out] none \retval none */ @@ -727,11 +727,11 @@ void adc_end_of_conversion_config(uint32_t adc_periph, uint8_t end_selection) { switch(end_selection) { case ADC_EOC_SET_SEQUENCE: - /* only at the end of a sequence of regular conversions, the EOC bit is set */ + /* only at the end of a sequence of routine conversions, the EOC bit is set */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM); break; case ADC_EOC_SET_CONVERSION: - /* at the end of each regular conversion, the EOC bit is set.Overflow is detected automatically */ + /* at the end of each routine conversion, the EOC bit is set.Overflow is detected automatically */ ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_EOCM); break; default: @@ -740,26 +740,26 @@ void adc_end_of_conversion_config(uint32_t adc_periph, uint8_t end_selection) } /*! - \brief read ADC regular group data register + \brief read ADC routine data register \param[in] adc_periph: ADCx,x=0,1,2 \param[in] none \param[out] none \retval the conversion value */ -uint16_t adc_regular_data_read(uint32_t adc_periph) +uint16_t adc_routine_data_read(uint32_t adc_periph) { return (uint16_t)(ADC_RDATA(adc_periph)); } /*! - \brief read ADC inserted group data register + \brief read ADC inserted data register \param[in] adc_periph: ADCx,x=0,1,2 \param[in] inserted_channel : insert channel select only one parameter can be selected which is shown as below: - \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 + \arg ADC_INSERTED_CHANNEL_0: inserted channel0 \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 + \arg ADC_INSERTED_CHANNEL_2: inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted channel3 \param[out] none \retval the conversion value */ @@ -821,31 +821,31 @@ void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel } /*! - \brief configure ADC analog watchdog group channel + \brief configure ADC analog watchdog sequence channel \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: the channel group use analog watchdog + \param[in] adc_sequence: the sequence use analog watchdog only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_ROUTINE_INSERTED_CHANNEL: both routine and inserted sequence \param[out] none \retval none */ -void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group) +void adc_watchdog_sequence_channel_enable(uint32_t adc_periph, uint8_t adc_sequence) { ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC)); - /* select the group */ - switch(adc_channel_group) { - case ADC_REGULAR_CHANNEL: - /* regular channel analog watchdog enable */ + /* select the sequence */ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* routine channel analog watchdog enable */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; break; case ADC_INSERTED_CHANNEL: /* inserted channel analog watchdog enable */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; break; - case ADC_REGULAR_INSERTED_CHANNEL: - /* regular and inserted channel analog watchdog enable */ + case ADC_ROUTINE_INSERTED_CHANNEL: + /* routine and inserted channel analog watchdog enable */ ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); break; default: @@ -856,28 +856,28 @@ void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_ /*! \brief disable ADC analog watchdog \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: the channel group use analog watchdog + \param[in] adc_sequence: the sequence use analog watchdog only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_ROUTINE_INSERTED_CHANNEL: both routine and inserted sequence \param[out] none \retval none */ -void adc_watchdog_disable(uint32_t adc_periph, uint8_t adc_channel_group) +void adc_watchdog_disable(uint32_t adc_periph, uint8_t adc_sequence) { - /* select the group */ - switch(adc_channel_group) { - case ADC_REGULAR_CHANNEL: - /* disable ADC analog watchdog regular channel group */ + /* select the sequence */ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* disable ADC analog watchdog routine sequence */ ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_RWDEN); break; case ADC_INSERTED_CHANNEL: - /* disable ADC analog watchdog inserted channel group */ + /* disable ADC analog watchdog inserted sequence */ ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_IWDEN); break; - case ADC_REGULAR_INSERTED_CHANNEL: - /* disable ADC analog watchdog regular and inserted channel group */ + case ADC_ROUTINE_INSERTED_CHANNEL: + /* disable ADC analog watchdog routine and inserted sequence */ ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN)); break; default: @@ -907,11 +907,11 @@ void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, \param[in] adc_flag: the adc flag bits only one parameter can be selected which is shown as below: \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \arg ADC_FLAG_ROVF: regular data register overflow flag + \arg ADC_FLAG_EOC: end of sequence conversion flag + \arg ADC_FLAG_EOIC: end of inserted sequence conversion flag + \arg ADC_FLAG_STIC: start flag of inserted sequence + \arg ADC_FLAG_STRC: start flag of routine sequence + \arg ADC_FLAG_ROVF: routine data register overflow flag \param[out] none \retval FlagStatus: SET or RESET */ @@ -931,11 +931,11 @@ FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag) \param[in] adc_flag: the adc flag bits only one parameter can be selected which is shown as below: \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \arg ADC_FLAG_ROVF: regular data register overflow flag + \arg ADC_FLAG_EOC: end of sequence conversion flag + \arg ADC_FLAG_EOIC: end of inserted sequence conversion flag + \arg ADC_FLAG_STIC: start flag of inserted sequence + \arg ADC_FLAG_STRC: start flag of routine sequence + \arg ADC_FLAG_ROVF: routine data register overflow flag \param[out] none \retval none */ @@ -951,7 +951,7 @@ void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag) \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) +FlagStatus adc_routine_software_startconv_flag_get(uint32_t adc_periph) { FlagStatus reval = RESET; if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STRC)) { @@ -982,9 +982,9 @@ FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) \param[in] adc_interrupt: the adc interrupt bits only one parameter can be selected which is shown as below: \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \arg ADC_INT_FLAG_ROVF: regular data register overflow interrupt + \arg ADC_INT_FLAG_EOC: end of sequence conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted sequence conversion interrupt + \arg ADC_INT_FLAG_ROVF: routine data register overflow interrupt \param[out] none \retval FlagStatus: SET or RESET */ @@ -1002,21 +1002,21 @@ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) } break; case ADC_INT_FLAG_EOC: - /* get the ADC end of group conversion interrupt bits */ + /* get the ADC end of sequence conversion interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_EOC; if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state) { interrupt_flag = SET; } break; case ADC_INT_FLAG_EOIC: - /* get the ADC end of inserted group conversion interrupt bits */ + /* get the ADC end of inserted sequence conversion interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state) { interrupt_flag = SET; } break; case ADC_INT_FLAG_ROVF: - /* get the ADC regular data register overflow interrupt bits */ + /* get the ADC routine data register overflow interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_ROVF; if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state) { interrupt_flag = SET; @@ -1034,9 +1034,9 @@ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) \param[in] adc_interrupt: the adc status flag only one parameter can be selected which is shown as below: \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \arg ADC_INT_FLAG_ROVF: regular data register overflow interrupt + \arg ADC_INT_FLAG_EOC: end of sequence conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted sequence conversion interrupt + \arg ADC_INT_FLAG_ROVF: routine data register overflow interrupt \param[out] none \retval none */ @@ -1051,9 +1051,9 @@ void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) \param[in] adc_interrupt: the adc interrupt flag only one parameter can be selected which is shown as below: \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \arg ADC_INT_ROVF: regular data register overflow interrupt flag + \arg ADC_INT_EOC: end of sequence conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted sequence conversion interrupt flag + \arg ADC_INT_ROVF: routine data register overflow interrupt flag \param[out] none \retval none */ @@ -1065,11 +1065,11 @@ void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; break; case ADC_INT_EOC: - /* enable end of group conversion interrupt */ + /* enable end of sequence conversion interrupt */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; break; case ADC_INT_EOIC: - /* enable end of inserted group conversion interrupt */ + /* enable end of inserted sequence conversion interrupt */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; break; case ADC_INT_ROVF: @@ -1086,9 +1086,9 @@ void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) \param[in] adc_flag: the adc interrupt flag only one parameter can be selected which is shown as below: \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \arg ADC_INT_ROVF: regular data register overflow interrupt flag + \arg ADC_INT_EOC: end of sequence conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted sequence conversion interrupt flag + \arg ADC_INT_ROVF: routine data register overflow interrupt flag \param[out] none \retval none */ @@ -1118,17 +1118,17 @@ void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) \param[in] sync_mode: ADC sync mode only one parameter can be selected which is shown as below: \arg ADC_SYNC_MODE_INDEPENDENT: all the ADCs work independently - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel & inserted parallel mode - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel & trigger rotation mode + \arg ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined routine parallel & inserted parallel mode + \arg ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined routine parallel & trigger rotation mode \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode - \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode - \arg ADC_DAUL_REGULAL_FOLLOW_UP: ADC0 and ADC1 work in follow-up mode + \arg ADC_DAUL_ROUTINE_PARALLEL: ADC0 and ADC1 work in routine parallel mode + \arg ADC_DAUL_ROUTINE_FOLLOW_UP: ADC0 and ADC1 work in follow-up mode \arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode - \arg ADC_ALL_REGULAL_PARALLEL_INSERTED_PARALLEL: all ADCs work in combined regular parallel & inserted parallel mode - \arg ADC_ALL_REGULAL_PARALLEL_INSERTED_ROTATION: all ADCs work in combined regular parallel & trigger rotation mode + \arg ADC_ALL_ROUTINE_PARALLEL_INSERTED_PARALLEL: all ADCs work in combined routine parallel & inserted parallel mode + \arg ADC_ALL_ROUTINE_PARALLEL_INSERTED_ROTATION: all ADCs work in combined routine parallel & trigger rotation mode \arg ADC_ALL_INSERTED_PARALLEL: all ADCs work in inserted parallel mode - \arg ADC_ALL_REGULAL_PARALLEL: all ADCs work in regular parallel mode - \arg ADC_ALL_REGULAL_FOLLOW_UP: all ADCs work in follow-up mode + \arg ADC_ALL_ROUTINE_PARALLEL: all ADCs work in routine parallel mode + \arg ADC_ALL_ROUTINE_FOLLOW_UP: all ADCs work in follow-up mode \arg ADC_ALL_INSERTED_TRRIGGER_ROTATION: all ADCs work in trigger rotation mode \param[out] none \retval none @@ -1192,12 +1192,12 @@ void adc_sync_dma_request_after_last_disable(void) } /*! - \brief read ADC sync regular data register + \brief read ADC sync routine data register \param[in] none \param[out] none - \retval sync regular data + \retval sync routine data */ -uint32_t adc_sync_regular_data_read(void) +uint32_t adc_sync_routine_data_read(void) { return (uint32_t)ADC_SYNCDATA; } diff --git a/gd32f4xx/standard_peripheral/source/gd32f4xx_can.c b/gd32f4xx/standard_peripheral/source/gd32f4xx_can.c index 86358fc0..a15df30b 100644 --- a/gd32f4xx/standard_peripheral/source/gd32f4xx_can.c +++ b/gd32f4xx/standard_peripheral/source/gd32f4xx_can.c @@ -39,6 +39,7 @@ OF SUCH DAMAGE. */ #include "gd32f4xx_can.h" +#include #define CAN_ERROR_HANDLE(s) do{}while(1) @@ -51,10 +52,10 @@ OF SUCH DAMAGE. */ void can_deinit(uint32_t can_periph) { - if(CAN0 == can_periph) { + if(CAN0 == can_periph){ rcu_periph_reset_enable(RCU_CAN0RST); rcu_periph_reset_disable(RCU_CAN0RST); - } else { + }else{ rcu_periph_reset_enable(RCU_CAN1RST); rcu_periph_reset_disable(RCU_CAN1RST); } @@ -75,15 +76,19 @@ void can_struct_para_init(can_struct_type_enum type, void *p_struct) { uint8_t i; + if(NULL == p_struct) { + CAN_ERROR_HANDLE("struct parameter can not be NULL \r\n"); + } + /* get type of the struct */ switch(type) { /* used for can_init() */ case CAN_INIT_STRUCT: ((can_parameter_struct *)p_struct)->auto_bus_off_recovery = DISABLE; - ((can_parameter_struct *)p_struct)->auto_retrans = ENABLE; + ((can_parameter_struct *)p_struct)->auto_retrans = DISABLE; ((can_parameter_struct *)p_struct)->auto_wake_up = DISABLE; ((can_parameter_struct *)p_struct)->prescaler = 0x03FFU; - ((can_parameter_struct *)p_struct)->rec_fifo_overwrite = ENABLE; + ((can_parameter_struct *)p_struct)->rec_fifo_overwrite = DISABLE; ((can_parameter_struct *)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; ((can_parameter_struct *)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; ((can_parameter_struct *)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; @@ -199,17 +204,17 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init } else { CAN_CTL(can_periph) &= ~CAN_CTL_AWU; } - /* automatic retransmission mode disable */ - if(DISABLE == can_parameter_init->auto_retrans) { - CAN_CTL(can_periph) |= CAN_CTL_ARD; - } else { + /* automatic retransmission mode */ + if(ENABLE == can_parameter_init->auto_retrans) { CAN_CTL(can_periph) &= ~CAN_CTL_ARD; - } - /* receive FIFO overwrite mode disable */ - if(DISABLE == can_parameter_init->rec_fifo_overwrite) { - CAN_CTL(can_periph) |= CAN_CTL_RFOD; } else { + CAN_CTL(can_periph) |= CAN_CTL_ARD; + } + /* receive FIFO overwrite mode */ + if(ENABLE == can_parameter_init->rec_fifo_overwrite) { CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; + } else { + CAN_CTL(can_periph) |= CAN_CTL_RFOD; } /* transmit FIFO order */ if(ENABLE == can_parameter_init->trans_fifo_order) { @@ -345,7 +350,7 @@ void can_debug_freeze_enable(uint32_t can_periph) if(CAN0 == can_periph) { dbg_periph_enable(DBG_CAN0_HOLD); - } else { + }else{ dbg_periph_enable(DBG_CAN1_HOLD); } } @@ -362,9 +367,9 @@ void can_debug_freeze_disable(uint32_t can_periph) /* set DFZ bit */ CAN_CTL(can_periph) &= ~CAN_CTL_DFZ; - if(CAN0 == can_periph) { + if(CAN0 == can_periph){ dbg_periph_disable(DBG_CAN0_HOLD); - } else { + }else{ dbg_periph_disable(DBG_CAN1_HOLD); } } diff --git a/gd32f4xx/standard_peripheral/source/gd32f4xx_ctc.c b/gd32f4xx/standard_peripheral/source/gd32f4xx_ctc.c index e7bcda6c..4ae5ccde 100644 --- a/gd32f4xx/standard_peripheral/source/gd32f4xx_ctc.c +++ b/gd32f4xx/standard_peripheral/source/gd32f4xx_ctc.c @@ -136,27 +136,12 @@ void ctc_refsource_polarity_config(uint32_t polarity) CTC_CTL1 |= (uint32_t)polarity; } -/*! - \brief select USBFS or USBHS SOF signal - \param[in] usbsof: - \arg CTC_USBSOFSEL_USBHS: USBHS SOF signal is selected - \arg CTC_USBSOFSEL_USBFS: USBFS SOF signal is selected - \param[out] none - \retval none -*/ -void ctc_usbsof_signal_select(uint32_t usbsof) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_USBSOFSEL); - CTC_CTL1 |= (uint32_t)usbsof; -} - /*! \brief select reference signal source \param[in] refs: only one parameter can be selected which is shown as below: \arg CTC_REFSOURCE_GPIO: GPIO is selected \arg CTC_REFSOURCE_LXTAL: LXTAL is selected - \arg CTC_REFSOURCE_USBSOF: USBSOF is selected \param[out] none \retval none */ diff --git a/gd32f4xx/standard_peripheral/source/gd32f4xx_exmc.c b/gd32f4xx/standard_peripheral/source/gd32f4xx_exmc.c index 990f728b..71d26c3a 100644 --- a/gd32f4xx/standard_peripheral/source/gd32f4xx_exmc.c +++ b/gd32f4xx/standard_peripheral/source/gd32f4xx_exmc.c @@ -6,6 +6,7 @@ \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx \version 2022-03-09, V3.0.0, firmware for GD32F4xx + \version 2022-06-08, V3.0.1, firmware for GD32F4xx */ /* @@ -122,7 +123,7 @@ OF SUCH DAMAGE. #define INTEN_INTS_OFFSET ((uint32_t)3U) /*! - \brief deinitialize EXMC NOR/SRAM region + \brief deinitialize EXMC NOR/SRAM region \param[in] exmc_norsram_region: select the region of bank0 only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) @@ -138,7 +139,7 @@ void exmc_norsram_deinit(uint32_t exmc_norsram_region) } /*! - \brief initialize exmc_norsram_parameter_struct with the default values + \brief initialize exmc_norsram_parameter_struct with the default values \param[in] none \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer \retval none @@ -169,7 +170,7 @@ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct *exmc_norsram_i exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; - /* write timing configure, when extended mode is used */ + /* configure write timing, when extended mode is used */ exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; @@ -178,7 +179,7 @@ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct *exmc_norsram_i } /*! - \brief initialize EXMC NOR/SRAM region + \brief initialize EXMC NOR/SRAM region \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter norsram_region: EXMC_BANK0_NORSRAM_REGIONx, x=0..3 write_mode: EXMC_ASYN_WRITE, EXMC_SYN_WRITE @@ -225,6 +226,7 @@ void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWTEN | EXMC_SNCTL_SYNCWR | EXMC_SNCTL_NRMUX)); + /* configure control bits */ snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | exmc_norsram_init_struct->memory_type | exmc_norsram_init_struct->databus_width | @@ -238,6 +240,7 @@ void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | exmc_norsram_init_struct->write_mode; + /* configure timing */ sntcfg = (uint32_t)exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime | (exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | (exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | @@ -246,12 +249,12 @@ void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) exmc_norsram_init_struct->read_write_timing->syn_data_latency | exmc_norsram_init_struct->read_write_timing->asyn_access_mode; - /* nor flash access enable */ + /* enable nor flash access */ if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) { snctl |= (uint32_t)EXMC_SNCTL_NREN; } - /* extended mode configure */ + /* configure extended mode */ if(ENABLE == exmc_norsram_init_struct->extended_mode) { snwtcfg = (uint32_t)exmc_norsram_init_struct->write_timing->asyn_address_setuptime | (exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | @@ -269,7 +272,7 @@ void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) } /*! - \brief enable EXMC NOR/PSRAM bank region + \brief enable EXMC NOR/PSRAM bank region \param[in] exmc_norsram_region: specify the region of NOR/PSRAM bank only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) @@ -282,7 +285,7 @@ void exmc_norsram_enable(uint32_t exmc_norsram_region) } /*! - \brief disable EXMC NOR/PSRAM bank region + \brief disable EXMC NOR/PSRAM bank region \param[in] exmc_norsram_region: specify the region of NOR/PSRAM Bank only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) @@ -295,7 +298,7 @@ void exmc_norsram_disable(uint32_t exmc_norsram_region) } /*! - \brief deinitialize EXMC NAND bank + \brief deinitialize EXMC NAND bank \param[in] exmc_nand_bank: select the bank of NAND only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1..2) @@ -312,7 +315,7 @@ void exmc_nand_deinit(uint32_t exmc_nand_bank) } /*! - \brief initialize exmc_norsram_parameter_struct with the default values + \brief initialize exmc_norsram_parameter_struct with the default values \param[in] none \param[out] the initialized struct exmc_norsram_parameter_struct pointer \retval none @@ -338,7 +341,7 @@ void exmc_nand_struct_para_init(exmc_nand_parameter_struct *exmc_nand_init_struc } /*! - \brief initialize EXMC NAND bank + \brief initialize EXMC NAND bank \param[in] exmc_nand_parameter_struct: configure the EXMC NAND parameter nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 @@ -382,14 +385,14 @@ void exmc_nand_init(exmc_nand_parameter_struct *exmc_nand_init_struct) ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) | ((exmc_nand_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); - /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */ + /* initialize EXMC_BANK1_NAND or EXMC_BANK2_NAND */ EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg; EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg; } /*! - \brief enable NAND bank + \brief enable NAND bank \param[in] exmc_nand_bank: specify the NAND bank only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) @@ -402,7 +405,7 @@ void exmc_nand_enable(uint32_t exmc_nand_bank) } /*! - \brief disable NAND bank + \brief disable NAND bank \param[in] exmc_nand_bank: specify the NAND bank only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) @@ -415,7 +418,7 @@ void exmc_nand_disable(uint32_t exmc_nand_bank) } /*! - \brief deinitialize EXMC PC card bank + \brief deinitialize EXMC PC card bank \param[in] none \param[out] none \retval none @@ -431,7 +434,7 @@ void exmc_pccard_deinit(void) } /*! - \brief initialize exmc_pccard_parameter_struct with the default values + \brief initialize exmc_pccard_parameter_struct with the default values \param[in] none \param[out] the initialized struct exmc_pccard_parameter_struct pointer \retval none @@ -457,7 +460,7 @@ void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct *exmc_pccard_init } /*! - \brief initialize EXMC PC card bank + \brief initialize EXMC PC card bank \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 @@ -508,7 +511,7 @@ void exmc_pccard_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct) } /*! - \brief enable PC Card Bank + \brief enable PC Card Bank \param[in] none \param[out] none \retval none @@ -519,7 +522,7 @@ void exmc_pccard_enable(void) } /*! - \brief disable PC Card Bank + \brief disable PC Card Bank \param[in] none \param[out] none \retval none @@ -530,7 +533,7 @@ void exmc_pccard_disable(void) } /*! - \brief deinitialize EXMC SDRAM device + \brief deinitialize EXMC SDRAM device \param[in] exmc_sdram_device: select the SRAM device only one parameter can be selected which is shown as below: \arg EXMC_SDRAM_DEVICEx(x=0, 1) @@ -549,7 +552,7 @@ void exmc_sdram_deinit(uint32_t exmc_sdram_device) } /*! - \brief initialize exmc_sdram_parameter_struct with the default values + \brief initialize exmc_sdram_parameter_struct with the default values \param[in] none \param[out] the initialized struct exmc_pccard_parameter_struct pointer \retval none @@ -565,7 +568,7 @@ void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct *exmc_sdram_init_st exmc_sdram_init_struct->cas_latency = EXMC_CAS_LATENCY_1_SDCLK; exmc_sdram_init_struct->write_protection = ENABLE; exmc_sdram_init_struct->sdclock_config = EXMC_SDCLK_DISABLE; - exmc_sdram_init_struct->brust_read_switch = DISABLE; + exmc_sdram_init_struct->burst_read_switch = DISABLE; exmc_sdram_init_struct->pipeline_read_delay = EXMC_PIPELINE_DELAY_0_HCLK; exmc_sdram_init_struct->timing->load_mode_register_delay = 16U; @@ -578,11 +581,11 @@ void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct *exmc_sdram_init_st } /*! - \brief initialize EXMC SDRAM device + \brief initialize EXMC SDRAM device \param[in] exmc_sdram_parameter_struct: configure the EXMC SDRAM parameter sdram_device: EXMC_SDRAM_DEVICE0,EXMC_SDRAM_DEVICE1 pipeline_read_delay: EXMC_PIPELINE_DELAY_x_HCLK,x=0..2 - brust_read_switch: ENABLE or DISABLE + burst_read_switch: ENABLE or DISABLE sdclock_config: EXMC_SDCLK_DISABLE,EXMC_SDCLK_PERIODS_2_HCLK,EXMC_SDCLK_PERIODS_3_HCLK write_protection: ENABLE or DISABLE cas_latency: EXMC_CAS_LATENCY_x_SDCLK,x=1..3 @@ -605,20 +608,20 @@ void exmc_sdram_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct) { uint32_t sdctl0, sdctl1, sdtcfg0, sdtcfg1; - /* configuration EXMC_SDCTL0 or EXMC_SDCTL1 */ + /* configure EXMC_SDCTL0 or EXMC_SDCTL1 */ if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device) { - /* configuration EXMC_SDCTL0 */ - EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)exmc_sdram_init_struct->column_address_width | - exmc_sdram_init_struct->row_address_width | - exmc_sdram_init_struct->data_width | - exmc_sdram_init_struct->internal_bank_number | - exmc_sdram_init_struct->cas_latency | - (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET) | - exmc_sdram_init_struct->sdclock_config | - (exmc_sdram_init_struct->brust_read_switch << SDCTL_BRSTRD_OFFSET) | - exmc_sdram_init_struct->pipeline_read_delay; - - /* configuration EXMC_SDTCFG0 */ + /* configure EXMC_SDCTL0 */ + EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)(exmc_sdram_init_struct->column_address_width | + exmc_sdram_init_struct->row_address_width | + exmc_sdram_init_struct->data_width | + exmc_sdram_init_struct->internal_bank_number | + exmc_sdram_init_struct->cas_latency | + (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET) | + exmc_sdram_init_struct->sdclock_config | + (exmc_sdram_init_struct->burst_read_switch << SDCTL_BRSTRD_OFFSET) | + exmc_sdram_init_struct->pipeline_read_delay); + + /* configure EXMC_SDTCFG0 */ EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay) - 1U) | (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) | (((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) | @@ -627,36 +630,36 @@ void exmc_sdram_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct) (((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) | (((exmc_sdram_init_struct->timing->row_to_column_delay) - 1U) << SDTCFG_RCD_OFFSET); } else { - /* configuration EXMC_SDCTL0 and EXMC_SDCTL1 */ + /* configure EXMC_SDCTL0 and EXMC_SDCTL1 */ /* some bits in the EXMC_SDCTL1 register are reserved */ sdctl0 = EXMC_SDCTL(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDCTL_PIPED | EXMC_SDCTL_BRSTRD | EXMC_SDCTL_SDCLK)); - sdctl0 |= (uint32_t)exmc_sdram_init_struct->sdclock_config | - exmc_sdram_init_struct->brust_read_switch | - exmc_sdram_init_struct->pipeline_read_delay; - - sdctl1 = (uint32_t)exmc_sdram_init_struct->column_address_width | - exmc_sdram_init_struct->row_address_width | - exmc_sdram_init_struct->data_width | - exmc_sdram_init_struct->internal_bank_number | - exmc_sdram_init_struct->cas_latency | - exmc_sdram_init_struct->write_protection ; + sdctl0 |= (uint32_t)(exmc_sdram_init_struct->sdclock_config | + (exmc_sdram_init_struct->burst_read_switch << SDCTL_BRSTRD_OFFSET) | + exmc_sdram_init_struct->pipeline_read_delay); + + sdctl1 = (uint32_t)(exmc_sdram_init_struct->column_address_width | + exmc_sdram_init_struct->row_address_width | + exmc_sdram_init_struct->data_width | + exmc_sdram_init_struct->internal_bank_number | + exmc_sdram_init_struct->cas_latency | + (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET)); EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = sdctl0; EXMC_SDCTL(EXMC_SDRAM_DEVICE1) = sdctl1; - /* configuration EXMC_SDTCFG0 and EXMC_SDTCFG1 */ + /* configure EXMC_SDTCFG0 and EXMC_SDTCFG1 */ /* some bits in the EXMC_SDTCFG1 register are reserved */ sdtcfg0 = EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDTCFG_RPD | EXMC_SDTCFG_WRD | EXMC_SDTCFG_ARFD)); - sdtcfg0 |= (uint32_t)(((exmc_sdram_init_struct->timing->auto_refresh_delay) - 1U) << SDTCFG_ARFD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) | - (((exmc_sdram_init_struct->timing->write_recovery_delay) - 1U) << SDTCFG_WRD_OFFSET); + sdtcfg0 |= (uint32_t)((((exmc_sdram_init_struct->timing->auto_refresh_delay) - 1U) << SDTCFG_ARFD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) | + (((exmc_sdram_init_struct->timing->write_recovery_delay) - 1U) << SDTCFG_WRD_OFFSET)); - sdtcfg1 = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay) - 1U) | - (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_to_column_delay) - 1U) << SDTCFG_RCD_OFFSET); + sdtcfg1 = (uint32_t)(((exmc_sdram_init_struct->timing->load_mode_register_delay) - 1U) | + (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_to_column_delay) - 1U) << SDTCFG_RCD_OFFSET)); EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = sdtcfg0; EXMC_SDTCFG(EXMC_SDRAM_DEVICE1) = sdtcfg1; @@ -664,7 +667,22 @@ void exmc_sdram_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct) } /*! - \brief deinitialize exmc SQPIPSRAM + \brief initialize exmc_sdram_struct_command_para_init with the default values + \param[in] none + \param[out] the initialized struct exmc_sdram_struct_command_para_init pointer + \retval none +*/ +void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct) +{ + /* configure the structure with default value */ + exmc_sdram_command_init_struct->mode_register_content = 0U; + exmc_sdram_command_init_struct->auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK; + exmc_sdram_command_init_struct->bank_select = EXMC_SDRAM_DEVICE0_SELECT; + exmc_sdram_command_init_struct->command = EXMC_SDRAM_NORMAL_OPERATION; +} + +/*! + \brief deinitialize exmc SQPIPSRAM \param[in] none \param[out] none \retval none @@ -680,7 +698,7 @@ void exmc_sqpipsram_deinit(void) } /*! - \brief initialize exmc_sqpipsram_parameter_struct with the default values + \brief initialize exmc_sqpipsram_parameter_struct with the default values \param[in] the struct exmc_sqpipsram_parameter_struct pointer \param[out] none \retval none @@ -695,7 +713,7 @@ void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct *exmc_sqpip } /*! - \brief initialize EXMC SQPIPSRAM + \brief initialize EXMC SQPIPSRAM \param[in] exmc_sqpipsram_parameter_struct: configure the EXMC SQPIPSRAM parameter sample_polarity: EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE,EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE id_length: EXMC_SQPIPSRAM_ID_LENGTH_xB,x=8,16,32,64 @@ -714,7 +732,7 @@ void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct *exmc_sqpipsram_init_st } /*! - \brief configure consecutive clock + \brief configure consecutive clock \param[in] clock_mode: specify when the clock is generated only one parameter can be selected which is shown as below: \arg EXMC_CLOCK_SYN_MODE: the clock is generated only during synchronous access @@ -732,7 +750,7 @@ void exmc_norsram_consecutive_clock_config(uint32_t clock_mode) } /*! - \brief configure CRAM page size + \brief configure CRAM page size \param[in] exmc_norsram_region: select the region of bank0 only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) @@ -756,7 +774,7 @@ void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_s } /*! - \brief enable or disable the EXMC NAND ECC function + \brief enable or disable the EXMC NAND ECC function \param[in] exmc_nand_bank: specify the NAND bank only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) @@ -776,7 +794,7 @@ void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) } /*! - \brief get the EXMC ECC value + \brief get the EXMC ECC value \param[in] exmc_nand_bank: specify the NAND bank only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) @@ -789,7 +807,7 @@ uint32_t exmc_ecc_get(uint32_t exmc_nand_bank) } /*! - \brief enable or disable read sample + \brief enable or disable read sample \param[in] newvalue: ENABLE or DISABLE \param[out] none \retval none @@ -804,7 +822,7 @@ void exmc_sdram_readsample_enable(ControlStatus newvalue) } /*! - \brief configure the delayed sample clock of read data + \brief configure the delayed sample clock of read data \param[in] delay_cell: SDRAM the delayed sample clock of read data only one parameter can be selected which is shown as below: \arg EXMC_SDRAM_x_DELAY_CELL(x=0..15) @@ -826,7 +844,7 @@ void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk) } /*! - \brief configure the SDRAM memory command + \brief configure the SDRAM memory command \param[in] exmc_sdram_command_init_struct: initialize EXMC SDRAM command mode_register_content: auto_refresh_number: EXMC_SDRAM_AUTO_REFLESH_x_SDCLK, x=1..15 @@ -847,7 +865,7 @@ void exmc_sdram_command_config(exmc_sdram_command_parameter_struct *exmc_sdram_c } /*! - \brief set auto-refresh interval + \brief set auto-refresh interval \param[in] exmc_count: the number SDRAM clock cycles unit between two successive auto-refresh commands, 0x0000~0x1FFF \param[out] none \retval none @@ -860,7 +878,7 @@ void exmc_sdram_refresh_count_set(uint32_t exmc_count) } /*! - \brief set the number of successive auto-refresh command + \brief set the number of successive auto-refresh command \param[in] exmc_number: the number of successive Auto-refresh cycles will be send, 1~15 \param[out] none \retval none @@ -873,7 +891,7 @@ void exmc_sdram_autorefresh_number_set(uint32_t exmc_number) } /*! - \brief config the write protection function + \brief configure the write protection function \param[in] exmc_sdram_device: specify the SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_SDRAM_DEVICEx(x=0,1) @@ -892,7 +910,7 @@ void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatu } /*! - \brief get the status of SDRAM device0 or device1 + \brief get the status of SDRAM device0 or device1 \param[in] exmc_sdram_device: specify the SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_SDRAM_DEVICEx(x=0,1) @@ -913,7 +931,7 @@ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device) } /*! - \brief set the read command + \brief set the read command \param[in] read_command_mode: configure SPI PSRAM read command mode only one parameter can be selected which is shown as below: \arg EXMC_SQPIPSRAM_READ_MODE_DISABLE: not SPI mode @@ -936,7 +954,7 @@ void exmc_sqpipsram_read_command_set(uint32_t read_command_mode, uint32_t read_w } /*! - \brief set the write command + \brief set the write command \param[in] write_command_mode: configure SPI PSRAM write command mode only one parameter can be selected which is shown as below: \arg EXMC_SQPIPSRAM_WRITE_MODE_DISABLE: not SPI mode @@ -959,7 +977,7 @@ void exmc_sqpipsram_write_command_set(uint32_t write_command_mode, uint32_t writ } /*! - \brief send SPI read ID command + \brief send SPI read ID command \param[in] none \param[out] none \retval none @@ -970,7 +988,7 @@ void exmc_sqpipsram_read_id_command_send(void) } /*! - \brief send SPI special command which does not have address and data phase + \brief send SPI special command which does not have address and data phase \param[in] none \param[out] none \retval none @@ -981,7 +999,7 @@ void exmc_sqpipsram_write_cmd_send(void) } /*! - \brief get the EXMC SPI ID low data + \brief get the EXMC SPI ID low data \param[in] none \param[out] none \retval the ID low data @@ -992,7 +1010,7 @@ uint32_t exmc_sqpipsram_low_id_get(void) } /*! - \brief get the EXMC SPI ID high data + \brief get the EXMC SPI ID high data \param[in] none \param[out] none \retval the ID high data @@ -1003,7 +1021,7 @@ uint32_t exmc_sqpipsram_high_id_get(void) } /*! - \brief get the bit value of EXMC send write command bit or read ID command + \brief get the bit value of EXMC send write command bit or read ID command \param[in] send_command_flag: the send command flag only one parameter can be selected which is shown as below: \arg EXMC_SEND_COMMAND_FLAG_RDID: EXMC_SRCMD_RDID flag bit @@ -1032,7 +1050,7 @@ FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag) } /*! - \brief enable EXMC interrupt + \brief enable EXMC interrupt \param[in] exmc_bank: specify the NAND bank,PC card bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 @@ -1061,7 +1079,7 @@ void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt) } /*! - \brief disable EXMC interrupt + \brief disable EXMC interrupt \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 @@ -1090,7 +1108,7 @@ void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt) } /*! - \brief get EXMC flag status + \brief get EXMC flag status \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 @@ -1131,7 +1149,7 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank, uint32_t flag) } /*! - \brief clear EXMC flag status + \brief clear EXMC flag status \param[in] exmc_bank: specify the NAND bank , PCCARD bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 @@ -1162,7 +1180,7 @@ void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag) } /*! - \brief get EXMC interrupt flag + \brief get EXMC interrupt flag \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 @@ -1205,7 +1223,7 @@ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt) } /*! - \brief clear EXMC interrupt flag + \brief clear EXMC interrupt flag \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 diff --git a/gd32f4xx/standard_peripheral/source/gd32f4xx_exti.c b/gd32f4xx/standard_peripheral/source/gd32f4xx_exti.c index f3619c6f..413dff93 100644 --- a/gd32f4xx/standard_peripheral/source/gd32f4xx_exti.c +++ b/gd32f4xx/standard_peripheral/source/gd32f4xx_exti.c @@ -36,6 +36,8 @@ OF SUCH DAMAGE. #include "gd32f4xx_exti.h" +#define EXTI_REG_RESET_VALUE ((uint32_t)0x00000000U) + /*! \brief deinitialize the EXTI \param[in] none @@ -45,15 +47,15 @@ OF SUCH DAMAGE. void exti_deinit(void) { /* reset the value of all the EXTI registers */ - EXTI_INTEN = (uint32_t)0x00000000U; - EXTI_EVEN = (uint32_t)0x00000000U; - EXTI_RTEN = (uint32_t)0x00000000U; - EXTI_FTEN = (uint32_t)0x00000000U; - EXTI_SWIEV = (uint32_t)0x00000000U; + EXTI_INTEN = EXTI_REG_RESET_VALUE; + EXTI_EVEN = EXTI_REG_RESET_VALUE; + EXTI_RTEN = EXTI_REG_RESET_VALUE; + EXTI_FTEN = EXTI_REG_RESET_VALUE; + EXTI_SWIEV = EXTI_REG_RESET_VALUE; } /*! - \brief initialize the EXTI + \brief initialize the EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -165,7 +167,7 @@ void exti_event_disable(exti_line_enum linex) } /*! - \brief enable EXTI software interrupt event + \brief enable the software interrupt event from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -178,7 +180,7 @@ void exti_software_interrupt_enable(exti_line_enum linex) } /*! - \brief disable EXTI software interrupt event + \brief disable the software interrupt event from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -191,7 +193,7 @@ void exti_software_interrupt_disable(exti_line_enum linex) } /*! - \brief get EXTI lines flag + \brief get EXTI line x interrupt pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -208,7 +210,7 @@ FlagStatus exti_flag_get(exti_line_enum linex) } /*! - \brief clear EXTI lines pending flag + \brief clear EXTI line x interrupt pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -221,7 +223,7 @@ void exti_flag_clear(exti_line_enum linex) } /*! - \brief get EXTI lines flag when the interrupt flag is set + \brief get EXTI line x interrupt pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -230,12 +232,7 @@ void exti_flag_clear(exti_line_enum linex) */ FlagStatus exti_interrupt_flag_get(exti_line_enum linex) { - uint32_t flag_left, flag_right; - - flag_left = EXTI_PD & (uint32_t)linex; - flag_right = EXTI_INTEN & (uint32_t)linex; - - if((RESET != flag_left) && (RESET != flag_right)) { + if(RESET != (EXTI_PD & (uint32_t)linex)) { return SET; } else { return RESET; @@ -243,7 +240,7 @@ FlagStatus exti_interrupt_flag_get(exti_line_enum linex) } /*! - \brief clear EXTI lines pending flag + \brief clear EXTI line x interrupt pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x diff --git a/gd32f4xx/standard_peripheral/source/gd32f4xx_fmc.c b/gd32f4xx/standard_peripheral/source/gd32f4xx_fmc.c index 33a8f119..9dfa1904 100644 --- a/gd32f4xx/standard_peripheral/source/gd32f4xx_fmc.c +++ b/gd32f4xx/standard_peripheral/source/gd32f4xx_fmc.c @@ -39,7 +39,7 @@ OF SUCH DAMAGE. #include "gd32f4xx_fmc.h" /*! - \brief set the wait state counter value + \brief set the FMC wait state counter \param[in] wscnt: wait state counter value only one parameter can be selected which is shown as below: \arg WS_WSCNT_0: FMC 0 wait @@ -122,7 +122,7 @@ fmc_state_enum fmc_page_erase(uint32_t page_addr) fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); if(FMC_READY == fmc_state) { - /* unlock */ + /* unlock page erase operation */ FMC_PEKEY = UNLOCK_PE_KEY; /* start page erase */ @@ -145,7 +145,7 @@ fmc_state_enum fmc_page_erase(uint32_t page_addr) #endif /*! - \brief erase sector + \brief FMC erase sector \param[in] fmc_sector: select the sector to erase only one parameter can be selected which is shown as below: \arg CTL_SECTOR_NUMBER_0: sector 0 @@ -212,7 +212,7 @@ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector) } /*! - \brief erase whole chip + \brief FMC erase whole chip \param[in] none \param[out] none \retval state of FMC @@ -248,7 +248,7 @@ fmc_state_enum fmc_mass_erase(void) } /*! - \brief erase all FMC sectors in bank0 + \brief FMC erase whole bank0 \param[in] none \param[out] none \retval state of FMC @@ -284,7 +284,7 @@ fmc_state_enum fmc_bank0_erase(void) } /*! - \brief erase all FMC sectors in bank1 + \brief FMC erase whole bank1 \param[in] none \param[out] none \retval state of FMC @@ -620,11 +620,7 @@ void ob_drp_enable(uint32_t ob_drp) /*! \brief disable erase/program protection and D-bus read protection - \param[in] ob_drp: disable the WPx bits used as erase/program protection and D-bus read protection of each sector - one or more parameters can be selected which are shown as below: - \arg OB_DRP_x(x=0..22): sector x(x = 0,1,2...22) - \arg OB_DRP_23_27: sector23~27 - \arg OB_DRP_ALL: all sector + \param[in] none \param[out] none \retval none */ @@ -796,7 +792,7 @@ uint16_t ob_write_protection1_get(void) } /*! - \brief get the FMC D-bus read protection protection + \brief get the FMC erase/program protection and D-bus read protection option bytes value \param[in] none \param[out] none \retval the FMC erase/program protection and D-bus read protection option bytes value @@ -812,7 +808,7 @@ uint16_t ob_drp0_get(void) } /*! - \brief get the FMC D-bus read protection protection + \brief get the FMC erase/program protection and D-bus read protection option bytes value \param[in] none \param[out] none \retval the FMC erase/program protection and D-bus read protection option bytes value @@ -828,7 +824,7 @@ uint16_t ob_drp1_get(void) } /*! - \brief get the FMC option byte security protection + \brief get option byte security protection code value \param[in] none \param[out] none \retval FlagStatus: SET or RESET diff --git a/gd32f4xx/standard_peripheral/source/gd32f4xx_fwdgt.c b/gd32f4xx/standard_peripheral/source/gd32f4xx_fwdgt.c index fabc1c5e..4240327b 100644 --- a/gd32f4xx/standard_peripheral/source/gd32f4xx_fwdgt.c +++ b/gd32f4xx/standard_peripheral/source/gd32f4xx_fwdgt.c @@ -37,11 +37,6 @@ OF SUCH DAMAGE. #include "gd32f4xx_fwdgt.h" -/* write value to FWDGT_CTL_CMD bit field */ -#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -/* write value to FWDGT_RLD_RLD bit field */ -#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - /*! \brief enable write access to FWDGT_PSC and FWDGT_RLD \param[in] none @@ -75,6 +70,71 @@ void fwdgt_enable(void) FWDGT_CTL = FWDGT_KEY_ENABLE; } +/*! + \brief configure the free watchdog timer counter prescaler value + \param[in] prescaler_value: specify prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the PUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_value; + + return SUCCESS; +} + +/*! + \brief configure the free watchdog timer counter reload value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_reload_value_config(uint16_t reload_value) +{ + uint32_t timeout = FWDGT_RLD_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the RUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + FWDGT_RLD = RLD_RLD(reload_value); + + return SUCCESS; +} + /*! \brief reload the counter of FWDGT \param[in] none diff --git a/gd32f4xx/standard_peripheral/source/gd32f4xx_pmu.c b/gd32f4xx/standard_peripheral/source/gd32f4xx_pmu.c index 67c90dbd..50086e72 100644 --- a/gd32f4xx/standard_peripheral/source/gd32f4xx_pmu.c +++ b/gd32f4xx/standard_peripheral/source/gd32f4xx_pmu.c @@ -282,30 +282,28 @@ void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmode /*! \brief pmu work in standby mode - \param[in] standbymodecmd: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command + \param[in] none \param[out] none \retval none */ -void pmu_to_standbymode(uint8_t standbymodecmd) +void pmu_to_standbymode(void) { - /* set sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - /* set stbmod bit */ PMU_CTL |= PMU_CTL_STBMOD; /* reset wakeup flag */ PMU_CTL |= PMU_CTL_WURST; - /* select WFI or WFE command to enter standby mode */ - if(WFI_CMD == standbymodecmd) { - __WFI(); - } else { - __WFE(); - __WFE(); - } + /* set sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + REG32(0xE000E010U) &= 0x00010004U; + REG32(0xE000E180U) = 0XFFFFFFF7U; + REG32(0xE000E184U) = 0XFFFFFDFFU; + REG32(0xE000E188U) = 0xFFFFFFFFU; + + /* select WFI command to enter standby mode */ + __WFI(); } /*! diff --git a/gd32f4xx/standard_peripheral/source/gd32f4xx_rcu.c b/gd32f4xx/standard_peripheral/source/gd32f4xx_rcu.c index 9cd70781..42b8aaec 100644 --- a/gd32f4xx/standard_peripheral/source/gd32f4xx_rcu.c +++ b/gd32f4xx/standard_peripheral/source/gd32f4xx_rcu.c @@ -86,7 +86,7 @@ void rcu_deinit(void) \brief enable the peripherals clock \param[in] periph: RCU peripherals, refer to rcu_periph_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E,F,G,H,I): GPIO ports clock + \arg RCU_GPIOx (x = A, B, C, D, E, F, G, H, I): GPIO ports clock \arg RCU_CRC: CRC clock \arg RCU_BKPSRAM: BKPSRAM clock \arg RCU_TCMSRAM: TCMSRAM clock @@ -102,17 +102,17 @@ void rcu_deinit(void) \arg RCU_TRNG: TRNG clock \arg RCU_USBFS: USBFS clock \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock + \arg RCU_TIMERx (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2,3,4,5): SPI clock - \arg RCU_USARTx (x=0,1,2,5): USART clock - \arg RCU_UARTx (x=3,4,6,7): UART clock - \arg RCU_I2Cx (x=0,1,2): I2C clock - \arg RCU_CANx (x=0,1): CAN clock + \arg RCU_SPIx (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx (x = 0, 1, 2): I2C clock + \arg RCU_CANx (x = 0, 1): CAN clock \arg RCU_PMU: PMU clock \arg RCU_DAC: DAC clock \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1,2): ADC clock + \arg RCU_ADCx (x = 0, 1, 2): ADC clock \arg RCU_SDIO: SDIO clock \arg RCU_SYSCFG: SYSCFG clock \arg RCU_TLI: TLI clock @@ -130,7 +130,7 @@ void rcu_periph_clock_enable(rcu_periph_enum periph) \brief disable the peripherals clock \param[in] periph: RCU peripherals, refer to rcu_periph_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E,F,G,H,I): GPIO ports clock + \arg RCU_GPIOx (x = A, B, C, D, E, F, G, H, I): GPIO ports clock \arg RCU_CRC: CRC clock \arg RCU_BKPSRAM: BKPSRAM clock \arg RCU_TCMSRAM: TCMSRAM clock @@ -146,17 +146,17 @@ void rcu_periph_clock_enable(rcu_periph_enum periph) \arg RCU_TRNG: TRNG clock \arg RCU_USBFS: USBFS clock \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock + \arg RCU_TIMERx (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2,3,4,5): SPI clock - \arg RCU_USARTx (x=0,1,2,5): USART clock - \arg RCU_UARTx (x=3,4,6,7): UART clock - \arg RCU_I2Cx (x=0,1,2): I2C clock - \arg RCU_CANx (x=0,1): CAN clock + \arg RCU_SPIx (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx (x = 0, 1, 2): I2C clock + \arg RCU_CANx (x = 0, 1): CAN clock \arg RCU_PMU: PMU clock \arg RCU_DAC: DAC clock \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1,2): ADC clock + \arg RCU_ADCx (x = 0, 1, 2): ADC clock \arg RCU_SDIO: SDIO clock \arg RCU_SYSCFG: SYSCFG clock \arg RCU_TLI: TLI clock @@ -174,7 +174,7 @@ void rcu_periph_clock_disable(rcu_periph_enum periph) \brief enable the peripherals clock when sleep mode \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOx_SLP (x=A,B,C,D,E,F,G,H,I): GPIO ports clock + \arg RCU_GPIOx_SLP (x = A, B, C, D, E, F, G, H, I): GPIO ports clock \arg RCU_CRC_SLP: CRC clock \arg RCU_FMC_SLP: FMC clock \arg RCU_SRAM0_SLP: SRAM0 clock @@ -193,17 +193,17 @@ void rcu_periph_clock_disable(rcu_periph_enum periph) \arg RCU_TRNG_SLP: TRNG clock \arg RCU_USBFS_SLP: USBFS clock \arg RCU_EXMC_SLP: EXMC clock - \arg RCU_TIMERx_SLP (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock + \arg RCU_TIMERx_SLP (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock \arg RCU_WWDGT_SLP: WWDGT clock - \arg RCU_SPIx_SLP (x=0,1,2,3,4,5): SPI clock - \arg RCU_USARTx_SLP (x=0,1,2,5): USART clock - \arg RCU_UARTx_SLP (x=3,4,6,7): UART clock - \arg RCU_I2Cx_SLP (x=0,1,2): I2C clock - \arg RCU_CANx_SLP (x=0,1): CAN clock + \arg RCU_SPIx_SLP (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx_SLP (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx_SLP (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx_SLP (x = 0, 1, 2): I2C clock + \arg RCU_CANx_SLP (x = 0, 1): CAN clock \arg RCU_PMU_SLP: PMU clock \arg RCU_DAC_SLP: DAC clock \arg RCU_RTC_SLP: RTC clock - \arg RCU_ADCx_SLP (x=0,1,2): ADC clock + \arg RCU_ADCx_SLP (x = 0, 1, 2): ADC clock \arg RCU_SDIO_SLP: SDIO clock \arg RCU_SYSCFG_SLP: SYSCFG clock \arg RCU_TLI_SLP: TLI clock @@ -221,7 +221,7 @@ void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) \brief disable the peripherals clock when sleep mode \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOx_SLP (x=A,B,C,D,E,F,G,H,I): GPIO ports clock + \arg RCU_GPIOx_SLP (x = A, B, C, D, E, F, G, H, I): GPIO ports clock \arg RCU_CRC_SLP: CRC clock \arg RCU_FMC_SLP: FMC clock \arg RCU_SRAM0_SLP: SRAM0 clock @@ -240,17 +240,17 @@ void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) \arg RCU_TRNG_SLP: TRNG clock \arg RCU_USBFS_SLP: USBFS clock \arg RCU_EXMC_SLP: EXMC clock - \arg RCU_TIMERx_SLP (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock + \arg RCU_TIMERx_SLP (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock \arg RCU_WWDGT_SLP: WWDGT clock - \arg RCU_SPIx_SLP (x=0,1,2,3,4,5): SPI clock - \arg RCU_USARTx_SLP (x=0,1,2,5): USART clock - \arg RCU_UARTx_SLP (x=3,4,6,7): UART clock - \arg RCU_I2Cx_SLP (x=0,1,2): I2C clock - \arg RCU_CANx_SLP (x=0,1): CAN clock + \arg RCU_SPIx_SLP (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx_SLP (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx_SLP (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx_SLP (x = 0, 1, 2): I2C clock + \arg RCU_CANx_SLP (x = 0, 1): CAN clock \arg RCU_PMU_SLP: PMU clock \arg RCU_DAC_SLP: DAC clock \arg RCU_RTC_SLP: RTC clock - \arg RCU_ADCx_SLP (x=0,1,2): ADC clock + \arg RCU_ADCx_SLP (x = 0, 1, 2): ADC clock \arg RCU_SDIO_SLP: SDIO clock \arg RCU_SYSCFG_SLP: SYSCFG clock \arg RCU_TLI_SLP: TLI clock @@ -268,7 +268,7 @@ void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) \brief reset the peripherals \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G,H,I): reset GPIO ports + \arg RCU_GPIOxRST (x = A, B, C, D, E, F, G, H, I): reset GPIO ports \arg RCU_CRCRST: reset CRC \arg RCU_DMAxRST (x=0,1): reset DMA \arg RCU_IPARST: reset IPA @@ -278,16 +278,16 @@ void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) \arg RCU_TRNGRST: reset TRNG \arg RCU_USBFSRST: reset USBFS \arg RCU_EXMCRST: reset EXMC - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): reset TIMER + \arg RCU_TIMERxRST (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): reset TIMER \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2,3,4,5): reset SPI - \arg RCU_USARTxRST (x=0,1,2,5): reset USART - \arg RCU_UARTxRST (x=3,4,6,7): reset UART - \arg RCU_I2CxRST (x=0,1,2): reset I2C - \arg RCU_CANxRST (x=0,1): reset CAN + \arg RCU_SPIxRST (x = 0, 1, 2, 3, 4, 5): reset SPI + \arg RCU_USARTxRST (x = 0, 1, 2, 5): reset USART + \arg RCU_UARTxRST (x = 3, 4, 6, 7): reset UART + \arg RCU_I2CxRST (x = 0, 1, 2): reset I2C + \arg RCU_CANxRST (x = 0, 1): reset CAN \arg RCU_PMURST: reset PMU \arg RCU_DACRST: reset DAC - \arg RCU_ADCRST (x=0,1,2): reset ADC + \arg RCU_ADCRST (x = 0, 1, 2): reset ADC \arg RCU_SDIORST: reset SDIO \arg RCU_SYSCFGRST: reset SYSCFG \arg RCU_TLIRST: reset TLI @@ -305,7 +305,7 @@ void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) \brief disable reset the peripheral \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G,H,I): reset GPIO ports + \arg RCU_GPIOxRST (x = A, B, C, D, E, F, G, H, I): reset GPIO ports \arg RCU_CRCRST: reset CRC \arg RCU_DMAxRST (x=0,1): reset DMA \arg RCU_IPARST: reset IPA @@ -315,16 +315,16 @@ void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) \arg RCU_TRNGRST: reset TRNG \arg RCU_USBFSRST: reset USBFS \arg RCU_EXMCRST: reset EXMC - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): reset TIMER + \arg RCU_TIMERxRST (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): reset TIMER \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2,3,4,5): reset SPI - \arg RCU_USARTxRST (x=0,1,2,5): reset USART - \arg RCU_UARTxRST (x=3,4,6,7): reset UART - \arg RCU_I2CxRST (x=0,1,2): reset I2C - \arg RCU_CANxRST (x=0,1): reset CAN + \arg RCU_SPIxRST (x = 0, 1, 2, 3, 4, 5): reset SPI + \arg RCU_USARTxRST (x = 0, 1, 2, 5): reset USART + \arg RCU_UARTxRST (x = 3, 4, 6, 7): reset UART + \arg RCU_I2CxRST (x = 0, 1, 2): reset I2C + \arg RCU_CANxRST (x = 0, 1): reset CAN \arg RCU_PMURST: reset PMU \arg RCU_DACRST: reset DAC - \arg RCU_ADCRST (x=0,1,2): reset ADC + \arg RCU_ADCRST (x = 0, 1, 2): reset ADC \arg RCU_SDIORST: reset SDIO \arg RCU_SYSCFGRST: reset SYSCFG \arg RCU_TLIRST: reset TLI @@ -398,7 +398,7 @@ uint32_t rcu_system_clock_source_get(void) \brief configure the AHB clock prescaler selection \param[in] ck_ahb: AHB clock prescaler selection only one parameter can be selected which is shown as below: - \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 + \arg RCU_AHB_CKSYS_DIVx (x = 1, 2, 4, 8, 16, 64, 128, 256, 512): select CK_SYS / x as CK_AHB \param[out] none \retval none */ @@ -417,10 +417,10 @@ void rcu_ahb_clock_config(uint32_t ck_ahb) \param[in] ck_apb1: APB1 clock prescaler selection only one parameter can be selected which is shown as below: \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 - \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV2: select CK_AHB / 2 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV4: select CK_AHB / 4 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV8: select CK_AHB / 8 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV16: select CK_AHB / 16 as CK_APB1 \param[out] none \retval none */ @@ -439,10 +439,10 @@ void rcu_apb1_clock_config(uint32_t ck_apb1) \param[in] ck_apb2: APB2 clock prescaler selection only one parameter can be selected which is shown as below: \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 - \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV2: select CK_AHB / 2 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV4: select CK_AHB / 4 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV8: select CK_AHB / 8 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV16: select CK_AHB / 16 as CK_APB2 \param[out] none \retval none */ @@ -465,7 +465,7 @@ void rcu_apb2_clock_config(uint32_t ck_apb2) \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected \arg RCU_CKOUT0SRC_PLLP: PLLP selected \param[in] ckout0_div: CK_OUT0 divider - \arg RCU_CKOUT0_DIVx(x=1,2,3,4,5): CK_OUT0 is divided by x + \arg RCU_CKOUT0_DIVx(x = 1, 2, 3, 4, 5): CK_OUT0 is divided by x \param[out] none \retval none */ @@ -488,7 +488,7 @@ void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) \arg RCU_CKOUT1SRC_HXTAL: HXTAL selected \arg RCU_CKOUT1SRC_PLLP: PLLP selected \param[in] ckout1_div: CK_OUT1 divider - \arg RCU_CKOUT1_DIVx(x=1,2,3,4,5): CK_OUT1 is divided by x + \arg RCU_CKOUT1_DIVx(x = 1, 2, 3, 4, 5): CK_OUT1 is divided by x \param[out] none \retval none */ @@ -604,7 +604,7 @@ ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsa \arg RCU_RTCSRC_NONE: no clock selected \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock \arg RCU_RTCSRC_IRC32K: CK_IRC32K selected as RTC source clock - \arg RCU_RTCSRC_HXTAL_DIV_RTCDIV: CK_HXTAL/RTCDIV selected as RTC source clock + \arg RCU_RTCSRC_HXTAL_DIV_RTCDIV: CK_HXTAL / RTCDIV selected as RTC source clock \param[out] none \retval none */ @@ -623,7 +623,7 @@ void rcu_rtc_clock_config(uint32_t rtc_clock_source) \param[in] rtc_div: RTC clock frequency division only one parameter can be selected which is shown as below: \arg RCU_RTC_HXTAL_NONE: no clock for RTC - \arg RCU_RTC_HXTAL_DIVx: RTCDIV clock select CK_HXTAL/x, x = 2....31 + \arg RCU_RTC_HXTAL_DIVx: RTCDIV clock select CK_HXTAL / x, x = 2....31 \param[out] none \retval none */ @@ -738,137 +738,6 @@ void rcu_tli_clock_div_config(uint32_t pllsai_r_div) RCU_CFG1 = (reg | pllsai_r_div); } -/*! - \brief get the clock stabilization and periphral reset flags - \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_FLAG_IRC16MSTB: IRC16M stabilization flag - \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag - \arg RCU_FLAG_PLLSTB: PLL stabilization flag - \arg RCU_FLAG_PLLI2SSTB: PLLI2S stabilization flag - \arg RCU_FLAG_PLLSAISTB: PLLSAI stabilization flag - \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag - \arg RCU_FLAG_IRC32KSTB: IRC32K stabilization flag - \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag - \arg RCU_FLAG_BORRST: BOR reset flags - \arg RCU_FLAG_EPRST: external PIN reset flag - \arg RCU_FLAG_PORRST: Power reset flag - \arg RCU_FLAG_SWRST: software reset flag - \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag - \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag - \arg RCU_FLAG_LPRST: low-power reset flag - \param[out] none - \retval none -*/ -FlagStatus rcu_flag_get(rcu_flag_enum flag) -{ - /* get the rcu flag */ - if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear all the reset flag - \param[in] none - \param[out] none - \retval none -*/ -void rcu_all_reset_flag_clear(void) -{ - RCU_RSTSCK |= RCU_RSTSCK_RSTFC; -} - -/*! - \brief get the clock stabilization interrupt and ckm flags - \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC32KSTB: IRC32K stabilization interrupt flag - \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC16MSTB: IRC16M stabilization interrupt flag - \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLI2SSTB: PLLI2S stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSAISTB: PLLSAI stabilization interrupt flag - \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag - \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) -{ - /* get the rcu interrupt flag */ - if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear the interrupt flags - \param[in] int_flag: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC32KSTB_CLR: IRC32K stabilization interrupt flag clear - \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC16MSTB_CLR: IRC16M stabilization interrupt flag clear - \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLI2SSTB_CLR: PLLI2S stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSAISTB_CLR: PLLSAI stabilization interrupt flag clear - \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear - \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear - \param[out] none - \retval none -*/ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag) -{ - RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag)); -} - -/*! - \brief enable the stabilization interrupt - \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum - Only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt enable - \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt enable - \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable - \param[out] none - \retval none -*/ -void rcu_interrupt_enable(rcu_int_enum interrupt) -{ - RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt)); -} - - -/*! - \brief disable the stabilization interrupt - \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt disable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable - \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt disable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable - \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt disable - \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt disable - \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable - \param[out] none - \retval none -*/ -void rcu_interrupt_disable(rcu_int_enum interrupt) -{ - RCU_REG_VAL(interrupt) &= ~BIT(RCU_BIT_POS(interrupt)); -} - /*! \brief configure the LXTAL drive capability \param[in] lxtal_dricap: drive capability of LXTAL @@ -1132,29 +1001,6 @@ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) } } -/*! - \brief enable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ - -void rcu_hxtal_clock_monitor_enable(void) -{ - RCU_CTL |= RCU_CTL_CKMEN; -} - -/*! - \brief disable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ -void rcu_hxtal_clock_monitor_disable(void) -{ - RCU_CTL &= ~RCU_CTL_CKMEN; -} - /*! \brief set the IRC16M adjust value \param[in] irc16m_adjval: IRC16M adjust value, must be between 0 and 0x1F @@ -1172,34 +1018,6 @@ void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval) RCU_CTL = (reg | ((irc16m_adjval & RCU_IRC16M_ADJUST_MASK) << RCU_IRC16M_ADJUST_OFFSET)); } -/*! - \brief unlock the voltage key - \param[in] none - \param[out] none - \retval none -*/ -void rcu_voltage_key_unlock(void) -{ - RCU_VKEY = RCU_VKEY_UNLOCK; -} - -/*! - \brief deep-sleep mode voltage select - \param[in] dsvol: deep sleep mode voltage - only one parameter can be selected which is shown as below: - \arg RCU_DEEPSLEEP_V_0: the core voltage is default value - \arg RCU_DEEPSLEEP_V_1: the core voltage is (default value-0.1)V(customers are not recommended to use it) - \arg RCU_DEEPSLEEP_V_2: the core voltage is (default value-0.2)V(customers are not recommended to use it) - \arg RCU_DEEPSLEEP_V_3: the core voltage is (default value-0.3)V(customers are not recommended to use it) - \param[out] none - \retval none -*/ -void rcu_deepsleep_voltage_set(uint32_t dsvol) -{ - dsvol &= RCU_DSV_DSLPVS; - RCU_DSV = dsvol; -} - /*! \brief configure the spread spectrum modulation for the main PLL clock \param[in] spread_spectrum_type: PLL spread spectrum modulation type select @@ -1244,6 +1062,57 @@ void rcu_spread_spectrum_disable(void) RCU_PLLSSCTL &= ~RCU_PLLSSCTL_SSCGON; } +/*! + \brief enable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ + +void rcu_hxtal_clock_monitor_enable(void) +{ + RCU_CTL |= RCU_CTL_CKMEN; +} + +/*! + \brief disable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_disable(void) +{ + RCU_CTL &= ~RCU_CTL_CKMEN; +} + +/*! + \brief unlock the voltage key + \param[in] none + \param[out] none + \retval none +*/ +void rcu_voltage_key_unlock(void) +{ + RCU_VKEY = RCU_VKEY_UNLOCK; +} + +/*! + \brief deep-sleep mode voltage select + \param[in] dsvol: deep sleep mode voltage + only one parameter can be selected which is shown as below: + \arg RCU_DEEPSLEEP_V_0: the core voltage is default value + \arg RCU_DEEPSLEEP_V_1: the core voltage is (default value-0.1)V(customers are not recommended to use it) + \arg RCU_DEEPSLEEP_V_2: the core voltage is (default value-0.2)V(customers are not recommended to use it) + \arg RCU_DEEPSLEEP_V_3: the core voltage is (default value-0.3)V(customers are not recommended to use it) + \param[out] none + \retval none +*/ +void rcu_deepsleep_voltage_set(uint32_t dsvol) +{ + dsvol &= RCU_DSV_DSLPVS; + RCU_DSV = dsvol; +} + /*! \brief get the system clock, bus and peripheral clock frequency \param[in] clock: the clock frequency which to get @@ -1330,3 +1199,134 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) } return ck_freq; } + +/*! + \brief get the clock stabilization and periphral reset flags + \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_FLAG_IRC16MSTB: IRC16M stabilization flag + \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag + \arg RCU_FLAG_PLLSTB: PLL stabilization flag + \arg RCU_FLAG_PLLI2SSTB: PLLI2S stabilization flag + \arg RCU_FLAG_PLLSAISTB: PLLSAI stabilization flag + \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag + \arg RCU_FLAG_IRC32KSTB: IRC32K stabilization flag + \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag + \arg RCU_FLAG_BORRST: BOR reset flags + \arg RCU_FLAG_EPRST: external PIN reset flag + \arg RCU_FLAG_PORRST: Power reset flag + \arg RCU_FLAG_SWRST: software reset flag + \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag + \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag + \arg RCU_FLAG_LPRST: low-power reset flag + \param[out] none + \retval none +*/ +FlagStatus rcu_flag_get(rcu_flag_enum flag) +{ + /* get the rcu flag */ + if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear all the reset flag + \param[in] none + \param[out] none + \retval none +*/ +void rcu_all_reset_flag_clear(void) +{ + RCU_RSTSCK |= RCU_RSTSCK_RSTFC; +} + +/*! + \brief get the clock stabilization interrupt and ckm flags + \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC32KSTB: IRC32K stabilization interrupt flag + \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC16MSTB: IRC16M stabilization interrupt flag + \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLI2SSTB: PLLI2S stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSAISTB: PLLSAI stabilization interrupt flag + \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag + \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) +{ + /* get the rcu interrupt flag */ + if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the interrupt flags + \param[in] int_flag: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC32KSTB_CLR: IRC32K stabilization interrupt flag clear + \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC16MSTB_CLR: IRC16M stabilization interrupt flag clear + \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLI2SSTB_CLR: PLLI2S stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSAISTB_CLR: PLLSAI stabilization interrupt flag clear + \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear + \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear + \param[out] none + \retval none +*/ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag) +{ + RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag)); +} + +/*! + \brief enable the stabilization interrupt + \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum + Only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt enable + \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt enable + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable + \param[out] none + \retval none +*/ +void rcu_interrupt_enable(rcu_int_enum interrupt) +{ + RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt)); +} + + +/*! + \brief disable the stabilization interrupt + \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt disable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable + \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt disable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable + \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt disable + \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt disable + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable + \param[out] none + \retval none +*/ +void rcu_interrupt_disable(rcu_int_enum interrupt) +{ + RCU_REG_VAL(interrupt) &= ~BIT(RCU_BIT_POS(interrupt)); +} diff --git a/gd32f4xx/standard_peripheral/source/gd32f4xx_rtc.c b/gd32f4xx/standard_peripheral/source/gd32f4xx_rtc.c index 318f8708..8003e92c 100644 --- a/gd32f4xx/standard_peripheral/source/gd32f4xx_rtc.c +++ b/gd32f4xx/standard_peripheral/source/gd32f4xx_rtc.c @@ -295,7 +295,7 @@ void rtc_current_time_get(rtc_parameter_struct *rtc_initpara_struct) rtc_initpara_struct->second = (uint8_t)GET_TIME_SC(temp_tr); rtc_initpara_struct->factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr); rtc_initpara_struct->factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr); - rtc_initpara_struct->am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM); + rtc_initpara_struct->am_pm = (uint32_t)(temp_tr & RTC_TIME_PM); rtc_initpara_struct->display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS); } diff --git a/gd32f4xx/standard_peripheral/source/gd32f4xx_spi.c b/gd32f4xx/standard_peripheral/source/gd32f4xx_spi.c index 88fc8ed0..c2fe7c1c 100644 --- a/gd32f4xx/standard_peripheral/source/gd32f4xx_spi.c +++ b/gd32f4xx/standard_peripheral/source/gd32f4xx_spi.c @@ -486,6 +486,75 @@ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_di } } +/*! + \brief configure i2s full duplex mode + \param[in] i2s_add_periph: I2Sx_ADD(x=1,2) + \param[in] i2s_mode: + \arg I2S_MODE_SLAVETX : I2S slave transmit mode + \arg I2S_MODE_SLAVERX : I2S slave receive mode + \arg I2S_MODE_MASTERTX : I2S master transmit mode + \arg I2S_MODE_MASTERRX : I2S master receive mode + \param[in] i2s_standard: + \arg I2S_STD_PHILLIPS : I2S phillips standard + \arg I2S_STD_MSB : I2S MSB standard + \arg I2S_STD_LSB : I2S LSB standard + \arg I2S_STD_PCMSHORT : I2S PCM short standard + \arg I2S_STD_PCMLONG : I2S PCM long standard + \param[in] i2s_ckpl: + \arg I2S_CKPL_LOW : I2S clock polarity low level + \arg I2S_CKPL_HIGH : I2S clock polarity high level + \param[in] i2s_frameformat: + \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit + \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \param[out] none + \retval none +*/ +void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard, + uint32_t i2s_ckpl, uint32_t i2s_frameformat) +{ + uint32_t reg = 0U, tmp = 0U; + + reg = I2S_ADD_I2SCTL(i2s_add_periph); + reg &= I2S_FULL_DUPLEX_MASK; + + /* get the mode of the extra I2S module I2Sx_ADD */ + if((I2S_MODE_MASTERTX == i2s_mode) || (I2S_MODE_SLAVETX == i2s_mode)) { + tmp = I2S_MODE_SLAVERX; + } else { + tmp = I2S_MODE_SLAVETX; + } + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)tmp; + /* select I2S standard */ + reg |= (uint32_t)i2s_standard; + /* select I2S polarity */ + reg |= (uint32_t)i2s_ckpl; + /* configure data frame format */ + reg |= (uint32_t)i2s_frameformat; + + /* write to SPI_I2SCTL register */ + I2S_ADD_I2SCTL(i2s_add_periph) = (uint32_t)reg; +} + +/*! + \brief clear SPI/I2S format error flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] flag: SPI/I2S frame format error flag + \arg SPI_FLAG_FERR: only for SPI work in TI mode + \arg I2S_FLAG_FERR: for I2S + \param[out] none + \retval none +*/ +void spi_i2s_format_error_clear(uint32_t spi_periph, uint32_t flag) +{ + SPI_STAT(spi_periph) = (uint32_t)(~flag); +} + /*! \brief set SPI CRC polynomial \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) @@ -563,80 +632,36 @@ uint16_t spi_crc_get(uint32_t spi_periph, uint8_t spi_crc) } /*! - \brief enable SPI TI mode + \brief clear SPI CRC error flag status \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none */ -void spi_ti_mode_enable(uint32_t spi_periph) +void spi_crc_error_clear(uint32_t spi_periph) { - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; + SPI_STAT(spi_periph) = (uint32_t)(~SPI_FLAG_CRCERR); } /*! - \brief disable SPI TI mode + \brief enable SPI TI mode \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none */ -void spi_ti_mode_disable(uint32_t spi_periph) +void spi_ti_mode_enable(uint32_t spi_periph) { - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; } /*! - \brief configure i2s full duplex mode - \param[in] i2s_add_periph: I2Sx_ADD(x=1,2) - \param[in] i2s_mode: - \arg I2S_MODE_SLAVETX : I2S slave transmit mode - \arg I2S_MODE_SLAVERX : I2S slave receive mode - \arg I2S_MODE_MASTERTX : I2S master transmit mode - \arg I2S_MODE_MASTERRX : I2S master receive mode - \param[in] i2s_standard: - \arg I2S_STD_PHILLIPS : I2S phillips standard - \arg I2S_STD_MSB : I2S MSB standard - \arg I2S_STD_LSB : I2S LSB standard - \arg I2S_STD_PCMSHORT : I2S PCM short standard - \arg I2S_STD_PCMLONG : I2S PCM long standard - \param[in] i2s_ckpl: - \arg I2S_CKPL_LOW : I2S clock polarity low level - \arg I2S_CKPL_HIGH : I2S clock polarity high level - \param[in] i2s_frameformat: - \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit - \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \brief disable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none */ -void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard, - uint32_t i2s_ckpl, uint32_t i2s_frameformat) +void spi_ti_mode_disable(uint32_t spi_periph) { - uint32_t reg = 0U, tmp = 0U; - - reg = I2S_ADD_I2SCTL(i2s_add_periph); - reg &= I2S_FULL_DUPLEX_MASK; - - /* get the mode of the extra I2S module I2Sx_ADD */ - if((I2S_MODE_MASTERTX == i2s_mode) || (I2S_MODE_SLAVETX == i2s_mode)) { - tmp = I2S_MODE_SLAVERX; - } else { - tmp = I2S_MODE_SLAVETX; - } - - /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; - /* select I2S mode */ - reg |= (uint32_t)tmp; - /* select I2S standard */ - reg |= (uint32_t)i2s_standard; - /* select I2S polarity */ - reg |= (uint32_t)i2s_ckpl; - /* configure data frame format */ - reg |= (uint32_t)i2s_frameformat; - - /* write to SPI_I2SCTL register */ - I2S_ADD_I2SCTL(i2s_add_periph) = (uint32_t)reg; + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); } /*! @@ -645,7 +670,7 @@ void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uin \param[out] none \retval none */ -void qspi_enable(uint32_t spi_periph) +void spi_quad_enable(uint32_t spi_periph) { SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; } @@ -656,7 +681,7 @@ void qspi_enable(uint32_t spi_periph) \param[out] none \retval none */ -void qspi_disable(uint32_t spi_periph) +void spi_quad_disable(uint32_t spi_periph) { SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); } @@ -667,7 +692,7 @@ void qspi_disable(uint32_t spi_periph) \param[out] none \retval none */ -void qspi_write_enable(uint32_t spi_periph) +void spi_quad_write_enable(uint32_t spi_periph) { SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); } @@ -678,7 +703,7 @@ void qspi_write_enable(uint32_t spi_periph) \param[out] none \retval none */ -void qspi_read_enable(uint32_t spi_periph) +void spi_quad_read_enable(uint32_t spi_periph) { SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; } @@ -689,7 +714,7 @@ void qspi_read_enable(uint32_t spi_periph) \param[out] none \retval none */ -void qspi_io23_output_enable(uint32_t spi_periph) +void spi_quad_io23_output_enable(uint32_t spi_periph) { SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; } @@ -700,11 +725,42 @@ void qspi_io23_output_enable(uint32_t spi_periph) \param[out] none \retval none */ -void qspi_io23_output_disable(uint32_t spi_periph) +void spi_quad_io23_output_disable(uint32_t spi_periph) { SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); } +/*! + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_flag: SPI/I2S flag status + only one parameter can be selected which are shown as below: + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg SPI_FLAG_FERR: format error flag + \arg I2S_FLAG_TBE: transmit buffer empty flag + \arg I2S_FLAG_RBNE: receive buffer not empty flag + \arg I2S_FLAG_TRANS: transmit on-going flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \arg I2S_FLAG_FERR: format error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) +{ + if(SPI_STAT(spi_periph) & flag) { + return SET; + } else { + return RESET; + } +} + /*! \brief enable SPI and I2S interrupt \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) @@ -717,9 +773,9 @@ void qspi_io23_output_disable(uint32_t spi_periph) \param[out] none \retval none */ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int) +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) { - switch(spi_i2s_int) { + switch(interrupt) { /* SPI/I2S transmit buffer empty interrupt */ case SPI_I2S_INT_TBE: SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; @@ -749,9 +805,9 @@ void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int) \param[out] none \retval none */ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int) +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) { - switch(spi_i2s_int) { + switch(interrupt) { /* SPI/I2S transmit buffer empty interrupt */ case SPI_I2S_INT_TBE : SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); @@ -784,12 +840,12 @@ void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int) \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int) +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) { uint32_t reg1 = SPI_STAT(spi_periph); uint32_t reg2 = SPI_CTL1(spi_periph); - switch(spi_i2s_int) { + switch(interrupt) { /* SPI/I2S transmit buffer empty interrupt */ case SPI_I2S_INT_FLAG_TBE : reg1 = reg1 & SPI_STAT_TBE; @@ -835,46 +891,3 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int) return RESET; } } - -/*! - \brief get SPI and I2S flag status - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_i2s_flag: SPI/I2S flag status - only one parameter can be selected which are shown as below: - \arg SPI_FLAG_TBE: transmit buffer empty flag - \arg SPI_FLAG_RBNE: receive buffer not empty flag - \arg SPI_FLAG_TRANS: transmit on-going flag - \arg SPI_FLAG_RXORERR: receive overrun error flag - \arg SPI_FLAG_CONFERR: mode config error flag - \arg SPI_FLAG_CRCERR: CRC error flag - \arg SPI_FLAG_FERR: format error flag - \arg I2S_FLAG_TBE: transmit buffer empty flag - \arg I2S_FLAG_RBNE: receive buffer not empty flag - \arg I2S_FLAG_TRANS: transmit on-going flag - \arg I2S_FLAG_RXORERR: overrun error flag - \arg I2S_FLAG_TXURERR: underrun error flag - \arg I2S_FLAG_CH: channel side flag - \arg I2S_FLAG_FERR: format error flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t spi_i2s_flag) -{ - if(SPI_STAT(spi_periph) & spi_i2s_flag) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear SPI CRC error flag status - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_crc_error_clear(uint32_t spi_periph) -{ - SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); -} - diff --git a/gd32f4xx/standard_peripheral/source/gd32f4xx_timer.c b/gd32f4xx/standard_peripheral/source/gd32f4xx_timer.c index 68b40674..d0c016f1 100644 --- a/gd32f4xx/standard_peripheral/source/gd32f4xx_timer.c +++ b/gd32f4xx/standard_peripheral/source/gd32f4xx_timer.c @@ -1599,9 +1599,9 @@ void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t o \param[in] slavemode: only one parameter can be selected which is shown as below: \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..4,7,8,11)) - \arg TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0..4,7)) - \arg TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0..4,7)) - \arg TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0..4,7)) + \arg TIMER_QUAD_DECODER_MODE0: quadrature decoder mode 0(TIMERx(x=0..4,7)) + \arg TIMER_QUAD_DECODER_MODE1: quadrature decoder mode 1(TIMERx(x=0..4,7)) + \arg TIMER_QUAD_DECODER_MODE2: quadrature decoder mode 2(TIMERx(x=0..4,7)) \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..4,7,8,11)) \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..4,7,8,11)) \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..4,7,8,11)) @@ -1668,9 +1668,9 @@ void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, \param[in] timer_periph: TIMERx(x=0..4,7) \param[in] decomode: only one parameter can be selected which is shown as below: - \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level - \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level - \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input + \arg TIMER_QUAD_DECODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level + \arg TIMER_QUAD_DECODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level + \arg TIMER_QUAD_DECODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input \param[in] ic0polarity: only one parameter can be selected which is shown as below: \arg TIMER_IC_POLARITY_RISING: capture rising edge @@ -1932,10 +1932,10 @@ void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) - \arg TIMER_FLAG_CH0OF: channel 0 overcapture flag,TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1OF: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2OF: channel 2 overcapture flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3OF: channel 3 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) \param[out] none \retval FlagStatus: SET or RESET */ @@ -1961,10 +1961,10 @@ FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) - \arg TIMER_FLAG_CH0OF: channel 0 overcapture flag,TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1OF: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2OF: channel 2 overcapture flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3OF: channel 3 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) \param[out] none \retval none */ diff --git a/gd32f4xx/standard_peripheral/source/gd32f4xx_trng.c b/gd32f4xx/standard_peripheral/source/gd32f4xx_trng.c index 69c681b8..862432ca 100644 --- a/gd32f4xx/standard_peripheral/source/gd32f4xx_trng.c +++ b/gd32f4xx/standard_peripheral/source/gd32f4xx_trng.c @@ -38,7 +38,7 @@ OF SUCH DAMAGE. #include "gd32f4xx_trng.h" /*! - \brief deinitialize the TRNG + \brief reset TRNG \param[in] none \param[out] none \retval none @@ -50,7 +50,7 @@ void trng_deinit(void) } /*! - \brief enable the TRNG interface + \brief enable TRNG \param[in] none \param[out] none \retval none @@ -61,7 +61,7 @@ void trng_enable(void) } /*! - \brief disable the TRNG interface + \brief disable TRNG \param[in] none \param[out] none \retval none @@ -72,10 +72,10 @@ void trng_disable(void) } /*! - \brief get the true random data + \brief get the true random data \param[in] none \param[out] none - \retval the generated random data + \retval uint32_t: 0x0-0xFFFFFFFF */ uint32_t trng_get_true_random_data(void) { @@ -83,34 +83,34 @@ uint32_t trng_get_true_random_data(void) } /*! - \brief enable the TRNG interrupt + \brief enable TRNG interrupt \param[in] none \param[out] none \retval none */ void trng_interrupt_enable(void) { - TRNG_CTL |= TRNG_CTL_IE; + TRNG_CTL |= TRNG_CTL_TRNGIE; } /*! - \brief disable the TRNG interrupt + \brief disable TRNG interrupt \param[in] none \param[out] none \retval none */ void trng_interrupt_disable(void) { - TRNG_CTL &= ~TRNG_CTL_IE; + TRNG_CTL &= ~TRNG_CTL_TRNGIE; } /*! - \brief get the trng status flags - \param[in] flag: trng status flag, refer to trng_flag_enum + \brief get TRNG flag status + \param[in] flag: TRNG flag only one parameter can be selected which is shown as below: - \arg TRNG_FLAG_DRDY: Random Data ready status - \arg TRNG_FLAG_CECS: Clock error current status - \arg TRNG_FLAG_SECS: Seed error current status + \arg TRNG_FLAG_DRDY: random Data ready status + \arg TRNG_FLAG_CECS: clock error current status + \arg TRNG_FLAG_SECS: seed error current status \param[out] none \retval FlagStatus: SET or RESET */ @@ -124,11 +124,11 @@ FlagStatus trng_flag_get(trng_flag_enum flag) } /*! - \brief get the trng interrupt flags - \param[in] int_flag: trng interrupt flag, refer to trng_int_flag_enum + \brief get TRNG interrupt flag status + \param[in] int_flag: TRNG interrupt flag only one parameter can be selected which is shown as below: \arg TRNG_INT_FLAG_CEIF: clock error interrupt flag - \arg TRNG_INT_FLAG_SEIF: Seed error interrupt flag + \arg TRNG_INT_FLAG_SEIF: seed error interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ @@ -142,11 +142,11 @@ FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag) } /*! - \brief clear the trng interrupt flags - \param[in] int_flag: trng interrupt flag, refer to trng_int_flag_enum + \brief clear TRNG interrupt flag status + \param[in] int_flag: TRNG interrupt flag only one parameter can be selected which is shown as below: \arg TRNG_INT_FLAG_CEIF: clock error interrupt flag - \arg TRNG_INT_FLAG_SEIF: Seed error interrupt flag + \arg TRNG_INT_FLAG_SEIF: seed error interrupt flag \param[out] none \retval none */ diff --git a/gd32f4xx/standard_peripheral/source/gd32f4xx_usart.c b/gd32f4xx/standard_peripheral/source/gd32f4xx_usart.c index f9f8d0da..e54929d9 100644 --- a/gd32f4xx/standard_peripheral/source/gd32f4xx_usart.c +++ b/gd32f4xx/standard_peripheral/source/gd32f4xx_usart.c @@ -399,9 +399,9 @@ void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rti \param[out] none \retval none */ -void usart_data_transmit(uint32_t usart_periph, uint32_t data) +void usart_data_transmit(uint32_t usart_periph, uint16_t data) { - USART_DATA(usart_periph) = ((uint16_t)USART_DATA_DATA & data); + USART_DATA(usart_periph) = USART_DATA_DATA & (uint32_t)data; } /*! @@ -425,7 +425,7 @@ uint16_t usart_data_receive(uint32_t usart_periph) void usart_address_config(uint32_t usart_periph, uint8_t addr) { USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); - USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); + USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (uint32_t)addr); } /*! @@ -579,15 +579,8 @@ void usart_synchronous_clock_disable(uint32_t usart_periph) */ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) { - uint32_t ctl = 0U; - - /* read USART_CTL1 register */ - ctl = USART_CTL1(usart_periph); - ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); - /* set CK length, CK phase, CK polarity */ - ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); - - USART_CTL1(usart_periph) = ctl; + USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); + USART_CTL1(usart_periph) = (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); } /*! @@ -597,10 +590,10 @@ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32 \param[out] none \retval none */ -void usart_guard_time_config(uint32_t usart_periph, uint32_t guat) +void usart_guard_time_config(uint32_t usart_periph, uint8_t guat) { USART_GP(usart_periph) &= ~(USART_GP_GUAT); - USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << GP_GUAT_OFFSET)); + USART_GP(usart_periph) |= (USART_GP_GUAT & ((uint32_t)guat << GP_GUAT_OFFSET)); } /*! @@ -654,10 +647,10 @@ void usart_smartcard_mode_nack_disable(uint32_t usart_periph) \param[out] none \retval none */ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint8_t scrtnum) { USART_CTL3(usart_periph) &= ~(USART_CTL3_SCRTNUM); - USART_CTL3(usart_periph) |= (USART_CTL3_SCRTNUM & ((scrtnum) << CTL3_SCRTNUM_OFFSET)); + USART_CTL3(usart_periph) |= (USART_CTL3_SCRTNUM & ((uint32_t)scrtnum << CTL3_SCRTNUM_OFFSET)); } /*! @@ -667,10 +660,10 @@ void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) \param[out] none \retval none */ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl) +void usart_block_length_config(uint32_t usart_periph, uint8_t bl) { USART_RT(usart_periph) &= ~(USART_RT_BL); - USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << RT_BL_OFFSET)); + USART_RT(usart_periph) |= (USART_RT_BL & ((uint32_t)bl << RT_BL_OFFSET)); } /*! @@ -705,7 +698,7 @@ void usart_irda_mode_disable(uint32_t usart_periph) void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) { USART_GP(usart_periph) &= ~(USART_GP_PSC); - USART_GP(usart_periph) |= psc; + USART_GP(usart_periph) |= (uint32_t)psc; } /*! @@ -736,15 +729,9 @@ void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) */ void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) { - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_RTSEN; - ctl |= rtsconfig; - /* configure RTS */ - USART_CTL2(usart_periph) = ctl; + USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN); + USART_CTL2(usart_periph) |= (USART_CTL2_RTSEN & rtsconfig); } - /*! \brief configure hardware flow control CTS \param[in] usart_periph: USARTx(x=0,1,2,5) @@ -757,13 +744,8 @@ void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) */ void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) { - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_CTSEN; - ctl |= ctsconfig; - /* configure CTS */ - USART_CTL2(usart_periph) = ctl; + USART_CTL2(usart_periph) &= ~(USART_CTL2_CTSEN); + USART_CTL2(usart_periph) |= (USART_CTL2_CTSEN & ctsconfig); } /*! @@ -819,20 +801,15 @@ void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm) \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] dmacmd: enable or disable DMA for reception only one parameter can be selected which is shown as below: - \arg USART_DENR_ENABLE: DMA enable for reception - \arg USART_DENR_DISABLE: DMA disable for reception + \arg USART_RECEIVE_DMA_ENABLE: DMA enable for reception + \arg USART_RECEIVE_DMA_DISABLE: DMA disable for reception \param[out] none \retval none */ void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) { - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_DENR; - ctl |= dmacmd; - /* configure DMA reception */ - USART_CTL2(usart_periph) = ctl; + USART_CTL2(usart_periph) &= ~(USART_CTL2_DENR); + USART_CTL2(usart_periph) |= (USART_CTL2_DENR & dmacmd); } /*! @@ -840,20 +817,15 @@ void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] dmacmd: enable or disable DMA for transmission only one parameter can be selected which is shown as below: - \arg USART_DENT_ENABLE: DMA enable for transmission - \arg USART_DENT_DISABLE: DMA disable for transmission + \arg USART_TRANSMIT_DMA_ENABLE: DMA enable for transmission + \arg USART_TRANSMIT_DMA_DISABLE: DMA disable for transmission \param[out] none \retval none */ void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) { - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_DENT; - ctl |= dmacmd; - /* configure DMA transmission */ - USART_CTL2(usart_periph) = ctl; + USART_CTL2(usart_periph) &= ~(USART_CTL2_DENT); + USART_CTL2(usart_periph) |= (USART_CTL2_DENT & dmacmd); } /*! diff --git a/gd32f4xx/standard_peripheral/source/gd32f4xx_wwdgt.c b/gd32f4xx/standard_peripheral/source/gd32f4xx_wwdgt.c index 8031f84b..63628659 100644 --- a/gd32f4xx/standard_peripheral/source/gd32f4xx_wwdgt.c +++ b/gd32f4xx/standard_peripheral/source/gd32f4xx_wwdgt.c @@ -37,11 +37,6 @@ OF SUCH DAMAGE. #include "gd32f4xx_wwdgt.h" -/* write value to WWDGT_CTL_CNT bit field */ -#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -/* write value to WWDGT_CFG_WIN bit field */ -#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) - /*! \brief reset the window watchdog timer configuration \param[in] none @@ -73,12 +68,7 @@ void wwdgt_enable(void) */ void wwdgt_counter_update(uint16_t counter_value) { - uint32_t reg = 0U; - - reg = (WWDGT_CTL & (~WWDGT_CTL_CNT)); - reg |= CTL_CNT(counter_value); - - WWDGT_CTL = reg; + WWDGT_CTL = (uint32_t)(CTL_CNT(counter_value)); } /*! @@ -96,19 +86,9 @@ void wwdgt_counter_update(uint16_t counter_value) */ void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) { - uint32_t reg_cfg = 0U, reg_ctl = 0U; - - /* clear WIN and PSC bits, clear CNT bit */ - reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC))); - reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT)); - /* configure WIN and PSC bits, configure CNT bit */ - reg_cfg |= CFG_WIN(window); - reg_cfg |= prescaler; - reg_ctl |= CTL_CNT(counter); - - WWDGT_CTL = reg_ctl; - WWDGT_CFG = reg_cfg; + WWDGT_CTL = (uint32_t)(CTL_CNT(counter)); + WWDGT_CFG = (uint32_t)(CFG_WIN(window) | prescaler); } /*! @@ -134,7 +114,7 @@ FlagStatus wwdgt_flag_get(void) */ void wwdgt_flag_clear(void) { - WWDGT_STAT &= (~WWDGT_STAT_EWIF); + WWDGT_STAT = (uint32_t)(RESET); } /*! diff --git a/gd32f4xx/usb_drivers/include/drv_usb_core.h b/gd32f4xx/usb_drivers/include/drv_usb_core.h new file mode 100644 index 00000000..fa6bd8e1 --- /dev/null +++ b/gd32f4xx/usb_drivers/include/drv_usb_core.h @@ -0,0 +1,358 @@ +/*! + \file drv_usb_core.h + \brief USB core low level driver header file + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_CORE_H +#define __DRV_USB_CORE_H + +#include "drv_usb_regs.h" +#include "usb_ch9_std.h" + +#ifdef USE_DEVICE_MODE + #include "usbd_conf.h" +#endif /* USE_DEVICE_MODE */ + +#define USB_FS_EP0_MAX_LEN 64U /*!< maximum packet size of endpoint 0 */ +#define HC_MAX_PACKET_COUNT 140U /*!< maximum packet count */ + +#define EP_ID(x) ((uint8_t)((x) & 0x7FU)) /*!< endpoint number */ +#define EP_DIR(x) ((uint8_t)((x) >> 7)) /*!< endpoint direction */ + +enum _usb_mode { + DEVICE_MODE = 0U, /*!< device mode */ + HOST_MODE, /*!< host mode */ + OTG_MODE /*!< OTG mode */ +}; + +enum _usb_eptype { + USB_EPTYPE_CTRL = 0U, /*!< control endpoint type */ + USB_EPTYPE_ISOC = 1U, /*!< isochronous endpoint type */ + USB_EPTYPE_BULK = 2U, /*!< bulk endpoint type */ + USB_EPTYPE_INTR = 3U, /*!< interrupt endpoint type */ + USB_EPTYPE_MASK = 3U /*!< endpoint type mask */ +}; + +typedef enum +{ + USB_OTG_OK = 0U, /*!< USB OTG status OK*/ + USB_OTG_FAIL /*!< USB OTG status fail*/ +} usb_otg_status; + +typedef enum +{ + USB_OK = 0U, /*!< USB status OK*/ + USB_FAIL /*!< USB status fail*/ +} usb_status; + +typedef enum +{ + USB_USE_FIFO, /*!< USB use FIFO transfer mode */ + USB_USE_DMA /*!< USB use DMA transfer mode */ +} usb_transfer_mode; + +typedef struct +{ + uint8_t core_enum; /*!< USB core type */ + uint8_t core_speed; /*!< USB core speed */ + uint8_t num_pipe; /*!< USB host channel numbers */ + uint8_t num_ep; /*!< USB device endpoint numbers */ + uint8_t transfer_mode; /*!< USB transfer mode */ + uint8_t phy_itf; /*!< USB core PHY interface */ + uint8_t sof_enable; /*!< USB SOF output */ + uint8_t low_power; /*!< USB low power */ + uint8_t lpm_enable; /*!< USB link power mode(LPM) */ + uint8_t vbus_sensing_enable; /*!< USB VBUS sensing feature */ + uint8_t use_dedicated_ep1; /*!< USB dedicated endpoint1 interrupt */ + uint8_t use_external_vbus; /*!< enable or disable the use of the external VBUS */ + uint32_t base_reg; /*!< base register address */ +} usb_core_basic; + +#ifdef USE_DEVICE_MODE + +/* USB descriptor */ +typedef struct _usb_desc { + uint8_t *dev_desc; /*!< device descriptor */ + uint8_t *config_desc; /*!< configure descriptor */ + uint8_t *bos_desc; /*!< BOS descriptor */ + +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + uint8_t *other_speed_config_desc; /*!< other speed configuration descriptor */ + uint8_t *qualifier_desc; /*!< qualifier descriptor */ +#endif + + void* const *strings; /*!< string descriptor */ +} usb_desc; + +/* USB power management */ +typedef struct _usb_pm { + uint8_t power_mode; /*!< power mode */ + uint8_t power_low; /*!< power low */ + uint8_t dev_remote_wakeup; /*!< remote wakeup */ + uint8_t remote_wakeup_on; /*!< remote wakeup on */ +} usb_pm; + +/* USB control information */ +typedef struct _usb_control { + usb_req req; /*!< USB standard device request */ + + uint8_t ctl_state; /*!< USB control transfer state */ + uint8_t ctl_zlp; /*!< zero length package */ +} usb_control; + +typedef struct +{ + struct { + uint8_t num: 4; /*!< the endpoint number.it can be from 0 to 6 */ + uint8_t pad: 3; /*!< padding between number and direction */ + uint8_t dir: 1; /*!< the endpoint direction */ + } ep_addr; + + uint8_t ep_type; /*!< USB endpoint type */ + uint8_t ep_stall; /*!< USB endpoint stall status */ + + uint8_t frame_num; /*!< number of frame */ + uint16_t max_len; /*!< Maximum packet length */ + + /* transaction level variables */ + uint8_t *xfer_buf; /*!< transmit buffer */ + uint32_t xfer_len; /*!< transmit buffer length */ + uint32_t xfer_count; /*!< transmit buffer count */ + + uint32_t remain_len; /*!< remain packet length */ + + uint32_t dma_addr; /*!< DMA address */ +} usb_transc; + +typedef struct _usb_core_driver usb_dev; + +typedef struct _usb_class_core +{ + uint8_t command; /*!< device class request command */ + uint8_t alter_set; /*!< alternative set */ + + uint8_t (*init) (usb_dev *udev, uint8_t config_index); /*!< initialize handler */ + uint8_t (*deinit) (usb_dev *udev, uint8_t config_index); /*!< de-initialize handler */ + + uint8_t (*req_proc) (usb_dev *udev, usb_req *req); /*!< device request handler */ + + uint8_t (*set_intf) (usb_dev *udev, usb_req *req); /*!< device set interface callback */ + + uint8_t (*ctlx_in) (usb_dev *udev); /*!< device contrl in callback */ + uint8_t (*ctlx_out) (usb_dev *udev); + + uint8_t (*data_in) (usb_dev *udev, uint8_t ep_num); /*!< device data in handler */ + uint8_t (*data_out) (usb_dev *udev, uint8_t ep_num); /*!< device data out handler */ + + uint8_t (*SOF) (usb_dev *udev); /*!< Start of frame handler */ + + uint8_t (*incomplete_isoc_in) (usb_dev *udev); /*!< Incomplete synchronization IN transfer handler */ + uint8_t (*incomplete_isoc_out) (usb_dev *udev); /*!< Incomplete synchronization OUT transfer handler */ +} usb_class_core; + +typedef struct _usb_perp_dev +{ + uint8_t config; /*!< configuration */ + uint8_t dev_addr; /*!< device address */ + + __IO uint8_t cur_status; /*!< current status */ + __IO uint8_t backup_status; /*!< backup status */ + + usb_transc transc_in[USBFS_MAX_TX_FIFOS]; /*!< endpoint IN transaction */ + usb_transc transc_out[USBFS_MAX_TX_FIFOS]; /*!< endpoint OUT transaction */ + + usb_pm pm; /*!< power management */ + usb_control control; /*!< USB control information */ + usb_desc *desc; /*!< USB descriptors pointer */ + usb_class_core *class_core; /*!< class driver */ + void *class_data[USBD_ITF_MAX_NUM]; /*!< class data pointer */ + void *user_data; /*!< user data pointer */ + void *pdata; /*!< reserved data pointer */ +} usb_perp_dev; + +#endif /* USE_DEVICE_MODE */ + +#ifdef USE_HOST_MODE + +typedef enum _usb_pipe_status +{ + PIPE_IDLE = 0U, + PIPE_XF, + PIPE_HALTED, + PIPE_NAK, + PIPE_NYET, + PIPE_STALL, + PIPE_TRACERR, + PIPE_BBERR, + PIPE_REQOVR, + PIPE_DTGERR, +} usb_pipe_staus; + +typedef enum _usb_urb_state +{ + URB_IDLE = 0U, + URB_DONE, + URB_NOTREADY, + URB_ERROR, + URB_STALL, + URB_PING +} usb_urb_state; + +typedef struct _usb_pipe +{ + uint8_t in_used; + uint8_t dev_addr; + uint32_t dev_speed; + + struct { + uint8_t num; + uint8_t dir; + uint8_t type; + uint16_t mps; + } ep; + + __IO uint8_t supp_ping; + __IO uint8_t do_ping; + __IO uint32_t DPID; + + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t xfer_count; + + uint8_t data_toggle_in; + uint8_t data_toggle_out; + + __IO uint32_t err_count; + __IO usb_pipe_staus pp_status; + __IO usb_urb_state urb_state; +} usb_pipe; + +typedef struct _usb_host_drv +{ + __IO uint32_t connect_status; + __IO uint32_t port_enabled; + uint32_t backup_xfercount[USBFS_MAX_TX_FIFOS]; + + usb_pipe pipe[USBFS_MAX_TX_FIFOS]; + void *data; +} usb_host_drv; + +#endif /* USE_HOST_MODE */ + +typedef struct _usb_core_driver +{ + usb_core_basic bp; /*!< USB basic parameters */ + usb_core_regs regs; /*!< USB registers */ + +#ifdef USE_DEVICE_MODE + usb_perp_dev dev; /*!< USB peripheral device */ +#endif /* USE_DEVICE_MODE */ + +#ifdef USE_HOST_MODE + usb_host_drv host; +#endif /* USE_HOST_MODE */ +} usb_core_driver; + +/* static inline function definitions */ + +/*! + \brief get the global interrupts + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_coreintr_get(usb_core_regs *usb_regs) +{ + uint32_t reg_data = usb_regs->gr->GINTEN; + + reg_data &= usb_regs->gr->GINTF; + + return reg_data; +} + +/*! + \brief set USB RX FIFO size + \param[in] usb_regs: pointer to USB core registers + \param[in] size: assigned FIFO size + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_set_rxfifo(usb_core_regs *usb_regs, uint16_t size) +{ + usb_regs->gr->GRFLEN = size; +} + +/*! + \brief enable the global interrupts + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_globalint_enable(usb_core_regs *usb_regs) +{ + /* enable USB global interrupt */ + usb_regs->gr->GAHBCS |= GAHBCS_GINTEN; +} + +/*! + \brief disable the global interrupts + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_globalint_disable(usb_core_regs *usb_regs) +{ + /* disable USB global interrupt */ + usb_regs->gr->GAHBCS &= ~GAHBCS_GINTEN; +} + +/* function declarations */ +/* configure core capabilities */ +usb_status usb_basic_init (usb_core_basic *usb_basic, usb_core_regs *usb_regs, usb_core_enum usb_core); +/* initializes the USB controller registers and prepares the core device mode or host mode operation */ +usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs); +/* write a packet into the Tx FIFO associated with the endpoint */ +usb_status usb_txfifo_write (usb_core_regs *usb_regs, uint8_t *src_buf, uint8_t fifo_num, uint16_t byte_count); +/* read a packet from the Rx FIFO associated with the endpoint */ +void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count); +/* flush a Tx FIFO or all Tx FIFOs */ +usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num); +/* flush the entire Rx FIFO */ +usb_status usb_rxfifo_flush (usb_core_regs *usb_regs); +/* set endpoint or channel TX FIFO size */ +void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size); +/* set USB current mode */ +void usb_curmode_set(usb_core_regs *usb_regs, uint8_t mode); + +#endif /* __DRV_USB_CORE_H */ diff --git a/gd32f4xx/usb_drivers/include/drv_usb_dev.h b/gd32f4xx/usb_drivers/include/drv_usb_dev.h new file mode 100644 index 00000000..d891b433 --- /dev/null +++ b/gd32f4xx/usb_drivers/include/drv_usb_dev.h @@ -0,0 +1,199 @@ +/*! + \file drv_usb_dev.h + \brief USB device low level driver header file + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_DEV_H +#define __DRV_USB_DEV_H + +#include "usbd_conf.h" +#include "drv_usb_core.h" + +#define EP_IN(x) ((uint8_t)(0x80U | (x))) /*!< device IN endpoint */ +#define EP_OUT(x) ((uint8_t)(x)) /*!< device OUT endpoint */ + +enum usb_ctl_status { + USB_CTL_IDLE = 0U, /*!< USB control transfer idle state */ + USB_CTL_DATA_IN, /*!< USB control transfer data in state */ + USB_CTL_LAST_DATA_IN, /*!< USB control transfer last data in state */ + USB_CTL_DATA_OUT, /*!< USB control transfer data out state */ + USB_CTL_LAST_DATA_OUT, /*!< USB control transfer last data out state */ + USB_CTL_STATUS_IN, /*!< USB control transfer status in state*/ + USB_CTL_STATUS_OUT /*!< USB control transfer status out state */ +}; + +/* static inline function definitions */ + +/*! + \brief configure the USB device to be disconnected + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usb_dev_disconnect (usb_core_driver *udev) +{ + udev->regs.dr->DCTL |= DCTL_SD; +} + +/*! + \brief configure the USB device to be connected + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usb_dev_connect (usb_core_driver *udev) +{ + udev->regs.dr->DCTL &= ~DCTL_SD; +} + +/*! + \brief set the USB device address + \param[in] udev: pointer to USB device + \param[in] dev_addr: device address for setting + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usb_devaddr_set (usb_core_driver *udev, uint8_t dev_addr) +{ + udev->regs.dr->DCFG &= ~DCFG_DAR; + udev->regs.dr->DCFG |= (uint32_t)dev_addr << 4U; +} + +/*! + \brief read device all OUT endpoint interrupt register + \param[in] udev: pointer to USB device + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_oepintnum_read (usb_core_driver *udev) +{ + uint32_t value = udev->regs.dr->DAEPINT; + + value &= udev->regs.dr->DAEPINTEN; + + return (value & DAEPINT_OEPITB) >> 16U; +} + +/*! + \brief read device OUT endpoint interrupt flag register + \param[in] udev: pointer to USB device + \param[in] ep_num: endpoint number + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_oepintr_read (usb_core_driver *udev, uint8_t ep_num) +{ + uint32_t value = udev->regs.er_out[ep_num]->DOEPINTF; + + value &= udev->regs.dr->DOEPINTEN; + + return value; +} + +/*! + \brief read device all IN endpoint interrupt register + \param[in] udev: pointer to USB device + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_iepintnum_read (usb_core_driver *udev) +{ + uint32_t value = udev->regs.dr->DAEPINT; + + value &= udev->regs.dr->DAEPINTEN; + + return value & DAEPINT_IEPITB; +} + +/*! + \brief set remote wakeup signaling + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_rwkup_set (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + /* enable remote wakeup signaling */ + udev->regs.dr->DCTL |= DCTL_RWKUP; + } +} + +/*! + \brief reset remote wakeup signaling + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_rwkup_reset (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + /* disable remote wakeup signaling */ + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + } +} + +/* function declarations */ +/* initialize USB core registers for device mode */ +usb_status usb_devcore_init (usb_core_driver *udev); +/* enable the USB device mode interrupts */ +usb_status usb_devint_enable (usb_core_driver *udev); +/* active the USB endpoint 0 transaction */ +usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc); +/* active the USB transaction */ +usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc); +/* deactivate the USB transaction */ +usb_status usb_transc_deactivate (usb_core_driver *udev, usb_transc *transc); +/* configure USB transaction to start IN transfer */ +usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc); +/* configure USB transaction to start OUT transfer */ +usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc); +/* set the USB transaction STALL status */ +usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc); +/* clear the USB transaction STALL status */ +usb_status usb_transc_clrstall (usb_core_driver *udev, usb_transc *transc); +/* read device IN endpoint interrupt flag register */ +uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num); +/* configures OUT endpoint 0 to receive SETUP packets */ +void usb_ctlep_startout (usb_core_driver *udev); +/* active remote wakeup signaling */ +void usb_rwkup_active (usb_core_driver *udev); +/* active USB core clock */ +void usb_clock_active (usb_core_driver *udev); +/* USB device suspend */ +void usb_dev_suspend (usb_core_driver *udev); +/* stop the device and clean up FIFOs */ +void usb_dev_stop (usb_core_driver *udev); + +#endif /* __DRV_USB_DEV_H */ diff --git a/gd32f4xx/usb_drivers/include/drv_usb_host.h b/gd32f4xx/usb_drivers/include/drv_usb_host.h new file mode 100644 index 00000000..25579cd6 --- /dev/null +++ b/gd32f4xx/usb_drivers/include/drv_usb_host.h @@ -0,0 +1,125 @@ +/*! + \file drv_usb_host.h + \brief USB host mode low level driver header file + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_HOST_H +#define __DRV_USB_HOST_H + +#include "drv_usb_regs.h" +#include "usb_ch9_std.h" +#include "drv_usb_core.h" + +typedef enum _usb_pipe_mode +{ + PIPE_PERIOD = 0U, + PIPE_NON_PERIOD = 1U +} usb_pipe_mode; + +/*! + \brief get USB even frame + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +__STATIC_INLINE uint8_t usb_frame_even (usb_core_driver *udev) +{ + return (uint8_t)!(udev->regs.hr->HFINFR & 0x01U); +} + +/*! + \brief configure USB clock of PHY + \param[in] udev: pointer to USB device + \param[in] clock: PHY clock + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_phyclock_config (usb_core_driver *udev, uint8_t clock) +{ + udev->regs.hr->HCTL &= ~HCTL_CLKSEL; + udev->regs.hr->HCTL |= clock; +} + +/*! + \brief read USB port + \param[in] udev: pointer to USB device + \param[out] none + \retval port status +*/ +__STATIC_INLINE uint32_t usb_port_read (usb_core_driver *udev) +{ + return *udev->regs.HPCS & ~(HPCS_PE | HPCS_PCD | HPCS_PEDC); +} + +/*! + \brief get USB current speed + \param[in] udev: pointer to USB device + \param[out] none + \retval USB current speed +*/ +__STATIC_INLINE uint32_t usb_curspeed_get (usb_core_driver *udev) +{ + return *udev->regs.HPCS & HPCS_PS; +} + +/*! + \brief get USB current frame + \param[in] udev: pointer to USB device + \param[out] none + \retval USB current frame +*/ +__STATIC_INLINE uint32_t usb_curframe_get (usb_core_driver *udev) +{ + return (udev->regs.hr->HFINFR & 0xFFFFU); +} + +/* function declarations */ +/* initializes USB core for host mode */ +usb_status usb_host_init (usb_core_driver *udev); +/* control the VBUS to power */ +void usb_portvbus_switch (usb_core_driver *udev, uint8_t state); +/* reset host port */ +uint32_t usb_port_reset (usb_core_driver *udev); +/* initialize host pipe */ +usb_status usb_pipe_init (usb_core_driver *udev, uint8_t pipe_num); +/* prepare host pipe for transferring packets */ +usb_status usb_pipe_xfer (usb_core_driver *udev, uint8_t pipe_num); +/* halt host pipe */ +usb_status usb_pipe_halt (usb_core_driver *udev, uint8_t pipe_num); +/* configure host pipe to do ping operation */ +usb_status usb_pipe_ping (usb_core_driver *udev, uint8_t pipe_num); +/* stop the USB host and clean up FIFO */ +void usb_host_stop (usb_core_driver *udev); + +#endif /* __DRV_USB_HOST_H */ diff --git a/gd32f4xx/usb_drivers/include/drv_usb_hw.h b/gd32f4xx/usb_drivers/include/drv_usb_hw.h new file mode 100644 index 00000000..bd1c89c0 --- /dev/null +++ b/gd32f4xx/usb_drivers/include/drv_usb_hw.h @@ -0,0 +1,64 @@ +/*! + \file drv_usb_hw.h + \brief usb hardware configuration header file + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_HW_H +#define __DRV_USB_HW_H + +#include "usb_conf.h" + +/* function declarations */ +/* configure USB clock */ +void usb_rcu_config (void); +/* configure USB data line gpio */ +void usb_gpio_config (void); +/* configure USB interrupt */ +void usb_intr_config (void); +/* initializes delay unit using Timer2 */ +void usb_timer_init (void); +/* delay in micro seconds */ +void usb_udelay (const uint32_t usec); +/* delay in milliseconds */ +void usb_mdelay (const uint32_t msec); +/* configures system clock after wakeup from STOP mode */ +void system_clk_config_stop(void); +#ifdef USE_HOST_MODE +/* configure USB VBus */ +void usb_vbus_config (void); +/* drive USB VBus */ +void usb_vbus_drive (uint8_t State); +#endif /* USE_HOST_MODE */ + +#endif /* __DRV_USB_HW_H */ diff --git a/gd32f4xx/usb_drivers/include/drv_usb_regs.h b/gd32f4xx/usb_drivers/include/drv_usb_regs.h new file mode 100644 index 00000000..4c573471 --- /dev/null +++ b/gd32f4xx/usb_drivers/include/drv_usb_regs.h @@ -0,0 +1,664 @@ +/*! + \file drv_usb_regs.h + \brief USB cell registers definition and handle macros + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_REGS_H +#define __DRV_USB_REGS_H + +#include "usb_conf.h" + +#define USBHS_REG_BASE 0x40040000L /*!< base address of USBHS registers */ +#define USBFS_REG_BASE 0x50000000L /*!< base address of USBFS registers */ + +#define USBFS_MAX_TX_FIFOS 15U /*!< FIFO number */ + +#define USBFS_MAX_PACKET_SIZE 64U /*!< USBFS max packet size */ +#define USBFS_MAX_CHANNEL_COUNT 8U /*!< USBFS host channel count */ +#define USBFS_MAX_EP_COUNT 4U /*!< USBFS device endpoint count */ +#define USBFS_MAX_FIFO_WORDLEN 320U /*!< USBFS max fifo size in words */ + +#define USBHS_MAX_PACKET_SIZE 512U /*!< USBHS max packet size */ +#define USBHS_MAX_CHANNEL_COUNT 12U /*!< USBHS host channel count */ +#define USBHS_MAX_EP_COUNT 6U /*!< USBHS device endpoint count */ +#define USBHS_MAX_FIFO_WORDLEN 1280U /*!< USBHS max fifo size in words */ + +#define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */ +#define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */ + +typedef enum +{ + USB_CORE_ENUM_HS = 0, /*!< USB core type is HS */ + USB_CORE_ENUM_FS = 1 /*!< USB core type is FS */ +} usb_core_enum; + +enum USB_SPEED { + USB_SPEED_UNKNOWN = 0, /*!< USB speed unknown */ + USB_SPEED_LOW, /*!< USB speed low */ + USB_SPEED_FULL, /*!< USB speed full */ + USB_SPEED_HIGH, /*!< USB speed high */ +}; + +enum usb_reg_offset { + USB_REG_OFFSET_CORE = 0x0000U, /*!< global OTG control and status register */ + USB_REG_OFFSET_DEV = 0x0800U, /*!< device mode control and status registers */ + USB_REG_OFFSET_EP = 0x0020U, + USB_REG_OFFSET_EP_IN = 0x0900U, /*!< device IN endpoint 0 control register */ + USB_REG_OFFSET_EP_OUT = 0x0B00U, /*!< device OUT endpoint 0 control register */ + USB_REG_OFFSET_HOST = 0x0400U, /*!< host control register */ + USB_REG_OFFSET_CH = 0x0020U, + USB_REG_OFFSET_PORT = 0x0440U, /*!< host port control and status register */ + USB_REG_OFFSET_CH_INOUT = 0x0500U, /*!< Host channel-x control registers */ + USB_REG_OFFSET_PWRCLKCTL = 0x0E00U, /*!< power and clock register */ +}; + +typedef struct +{ + __IO uint32_t GOTGCS; /*!< USB global OTG control and status register 000h */ + __IO uint32_t GOTGINTF; /*!< USB global OTG interrupt flag register 004h */ + __IO uint32_t GAHBCS; /*!< USB global AHB control and status register 008h */ + __IO uint32_t GUSBCS; /*!< USB global USB control and status register 00Ch */ + __IO uint32_t GRSTCTL; /*!< USB global reset control register 010h */ + __IO uint32_t GINTF; /*!< USB global interrupt flag register 014h */ + __IO uint32_t GINTEN; /*!< USB global interrupt enable register 018h */ + __IO uint32_t GRSTATR; /*!< USB receive status debug read register 01Ch */ + __IO uint32_t GRSTATP; /*!< USB receive status and pop register 020h */ + __IO uint32_t GRFLEN; /*!< USB global receive FIFO length register 024h */ + __IO uint32_t DIEP0TFLEN_HNPTFLEN; /*!< USB device IN endpoint 0/host non-periodic transmit FIFO length register 028h */ + __IO uint32_t HNPTFQSTAT; /*!< USB host non-periodic FIFO/queue status register 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< USB global core configuration register 038h */ + __IO uint32_t CID; /*!< USB core ID register 03Ch */ + uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ + __IO uint32_t HPTFLEN; /*!< USB host periodic transmit FIFO length register 100h */ + __IO uint32_t DIEPTFLEN[15]; /*!< USB device IN endpoint transmit FIFO length register 104h */ +} usb_gr; + + +typedef struct +{ + __IO uint32_t HCTL; /*!< USB host control register 400h */ + __IO uint32_t HFT; /*!< USB host frame interval register 404h */ + __IO uint32_t HFINFR; /*!< USB host frame information remaining register 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTFQSTAT; /*!< USB host periodic transmit FIFO/queue status register 410h */ + __IO uint32_t HACHINT; /*!< USB host all channels interrupt register 414h */ + __IO uint32_t HACHINTEN; /*!< USB host all channels interrupt enable register 418h */ +} usb_hr; + +typedef struct +{ + __IO uint32_t HCHCTL; /*!< USB host channel control register 500h */ + __IO uint32_t HCHSTCTL; /*!< Reserved 504h */ + __IO uint32_t HCHINTF; /*!< USB host channel interrupt flag register 508h */ + __IO uint32_t HCHINTEN; /*!< USB host channel interrupt enable register 50Ch */ + __IO uint32_t HCHLEN; /*!< USB host channel transfer length register 510h */ + __IO uint32_t HCHDMAADDR; /*!< USB host channel-x DMA address register 514h*/ + uint32_t Reserved[2]; +} usb_pr; + +typedef struct +{ + __IO uint32_t DCFG; /*!< USB device configuration register 800h */ + __IO uint32_t DCTL; /*!< USB device control register 804h */ + __IO uint32_t DSTAT; /*!< USB device status register 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPINTEN; /*!< USB device IN endpoint common interrupt enable register 810h */ + __IO uint32_t DOEPINTEN; /*!< USB device OUT endpoint common interrupt enable register 814h */ + __IO uint32_t DAEPINT; /*!< USB device all endpoints interrupt register 818h */ + __IO uint32_t DAEPINTEN; /*!< USB device all endpoints interrupt enable register 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved24; /*!< Reserved 824h */ + __IO uint32_t DVBUSDT; /*!< USB device VBUS discharge time register 828h */ + __IO uint32_t DVBUSPT; /*!< USB device VBUS pulsing time register 82Ch */ + __IO uint32_t DTHRCTL; /*!< device threshold control 830h */ + __IO uint32_t DIEPFEINTEN; /*!< USB Device IN endpoint FIFO empty interrupt enable register 834h */ + __IO uint32_t DEP1INT; /*!< USB device endpoint 1 interrupt register 838h */ + __IO uint32_t DEP1INTEN; /*!< USB device endpoint 1 interrupt enable register 83Ch */ + uint32_t Reserved40; /*!< Reserved 840h */ + __IO uint32_t DIEP1INTEN; /*!< USB device IN endpoint-1 interrupt enable register 844h */ + uint32_t Reserved48[15]; /*!< Reserved 848-880h */ + __IO uint32_t DOEP1INTEN; /*!< USB device OUT endpoint-1 interrupt enable register 884h */ +} usb_dr; + +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< USB device IN endpoint control register 900h + (EpNum * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (EpNum * 20h) + 04h */ + __IO uint32_t DIEPINTF; /*!< USB device IN endpoint interrupt flag register 900h + (EpNum * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (EpNum * 20h) + 0Ch */ + __IO uint32_t DIEPLEN; /*!< USB device IN endpoint transfer length register 900h + (EpNum * 20h) + 10h */ + __IO uint32_t DIEPDMAADDR; /*!< Device IN endpoint-x DMA address register 900h + (EpNum * 20h) + 14h */ + __IO uint32_t DIEPTFSTAT; /*!< USB device IN endpoint transmit FIFO status register 900h + (EpNum * 20h) + 18h */ +} usb_erin; + +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< USB device IN endpoint control register B00h + (EpNum * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (EpNum * 20h) + 04h */ + __IO uint32_t DOEPINTF; /*!< USB device IN endpoint interrupt flag register B00h + (EpNum * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (EpNum * 20h) + 0Ch */ + __IO uint32_t DOEPLEN; /*!< USB device IN endpoint transfer length register B00h + (EpNum * 20h) + 10h */ + __IO uint32_t DOEPDMAADDR; /*!< Device OUT endpoint-x DMA address register B00h + (EpNum * 20h) + 0Ch */ +} usb_erout; + +typedef struct _usb_regs +{ + usb_gr *gr; /*!< USBFS global registers */ + usb_dr *dr; /*!< Device control and status registers */ + usb_hr *hr; /*!< Host control and status registers */ + usb_erin *er_in[6]; /*!< USB device IN endpoint register */ + usb_erout *er_out[6]; /*!< USB device OUT endpoint register */ + usb_pr *pr[15]; /*!< USB Host channel-x control register */ + + __IO uint32_t *HPCS; /*!< USB host port control and status register */ + __IO uint32_t *DFIFO[USBFS_MAX_TX_FIFOS]; + __IO uint32_t *PWRCLKCTL; /*!< USB power and clock control register */ +} usb_core_regs; + +/* global OTG control and status register bits definitions */ +#define GOTGCS_BSV BIT(19) /*!< B-Session Valid */ +#define GOTGCS_ASV BIT(18) /*!< A-session valid */ +#define GOTGCS_DI BIT(17) /*!< debounce interval */ +#define GOTGCS_CIDPS BIT(16) /*!< id pin status */ +#define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */ +#define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */ +#define GOTGCS_HNPREQ BIT(9) /*!< HNP request */ +#define GOTGCS_HNPS BIT(8) /*!< HNP successes */ +#define GOTGCS_SRPREQ BIT(1) /*!< SRP request */ +#define GOTGCS_SRPS BIT(0) /*!< SRP successes */ + +/* global OTG interrupt flag register bits definitions */ +#define GOTGINTF_DF BIT(19) /*!< debounce finish */ +#define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */ +#define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */ +#define GOTGINTF_HNPEND BIT(9) /*!< HNP end */ +#define GOTGINTF_SRPEND BIT(8) /*!< SRP end */ +#define GOTGINTF_SESEND BIT(2) /*!< session end */ + +/* global AHB control and status register bits definitions */ +#define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */ +#define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */ +#define GAHBCS_DMAEN BIT(5) /*!< DMA function Enable */ +#define GAHBCS_BURST BITS(1, 4) /*!< the AHB burst type used by DMA */ +#define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ + +/* global USB control and status register bits definitions */ +#define GUSBCS_FDM BIT(30) /*!< force device mode */ +#define GUSBCS_FHM BIT(29) /*!< force host mode */ +#define GUSBCS_ULPIEOI BIT(21) /*!< ULPI external over-current indicator */ +#define GUSBCS_ULPIEVD BIT(20) /*!< ULPI external VBUS driver */ +#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ +#define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ +#define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ +#define GUSBCS_EMBPHY BIT(6) /*!< embedded PHY selected */ +#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ + +/* global reset control register bits definitions */ +#define GRSTCTL_DMAIDL BIT(31) /*!< DMA idle state */ +#define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */ +#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */ +#define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */ +#define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */ +#define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ +#define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */ +#define GRSTCTL_CSRST BIT(0) /*!< core soft reset */ + +/* global interrupt flag register bits definitions */ +#define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */ +#define GINTF_SESIF BIT(30) /*!< session interrupt flag */ +#define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */ +#define GINTF_IDPSC BIT(28) /*!< id pin status change */ +#define GINTF_PTXFEIF BIT(26) /*!< periodic tx FIFO empty interrupt flag */ +#define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */ +#define GINTF_HPIF BIT(24) /*!< host port interrupt flag */ +#define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */ +#define GINTF_ISOONCIF BIT(21) /*!< isochronous OUT transfer not complete interrupt flag */ +#define GINTF_ISOINCIF BIT(20) /*!< isochronous IN transfer not complete interrupt flag */ +#define GINTF_OEPIF BIT(19) /*!< OUT endpoint interrupt flag */ +#define GINTF_IEPIF BIT(18) /*!< IN endpoint interrupt flag */ +#define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */ +#define GINTF_ISOOPDIF BIT(14) /*!< isochronous OUT packet dropped interrupt flag */ +#define GINTF_ENUMFIF BIT(13) /*!< enumeration finished */ +#define GINTF_RST BIT(12) /*!< USB reset */ +#define GINTF_SP BIT(11) /*!< USB suspend */ +#define GINTF_ESP BIT(10) /*!< early suspend */ +#define GINTF_GONAK BIT(7) /*!< global OUT NAK effective */ +#define GINTF_GNPINAK BIT(6) /*!< global IN non-periodic NAK effective */ +#define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx FIFO empty interrupt flag */ +#define GINTF_RXFNEIF BIT(4) /*!< rx FIFO non-empty interrupt flag */ +#define GINTF_SOF BIT(3) /*!< start of frame */ +#define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */ +#define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */ +#define GINTF_COPM BIT(0) /*!< current operation mode */ + +/* global interrupt enable register bits definitions */ +#define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */ +#define GINTEN_SESIE BIT(30) /*!< session interrupt enable */ +#define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */ +#define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */ +#define GINTEN_PTXFEIE BIT(26) /*!< periodic tx FIFO empty interrupt enable */ +#define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */ +#define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */ +#define GINTEN_IPXIE BIT(21) /*!< periodic transfer not complete interrupt enable */ +#define GINTEN_ISOONCIE BIT(21) /*!< isochronous OUT transfer not complete interrupt enable */ +#define GINTEN_ISOINCIE BIT(20) /*!< isochronous IN transfer not complete interrupt enable */ +#define GINTEN_OEPIE BIT(19) /*!< OUT endpoints interrupt enable */ +#define GINTEN_IEPIE BIT(18) /*!< IN endpoints interrupt enable */ +#define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */ +#define GINTEN_ISOOPDIE BIT(14) /*!< isochronous OUT packet dropped interrupt enable */ +#define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */ +#define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */ +#define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */ +#define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */ +#define GINTEN_GONAKIE BIT(7) /*!< global OUT NAK effective interrupt enable */ +#define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic IN NAK effective interrupt enable */ +#define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic Tx FIFO empty interrupt enable */ +#define GINTEN_RXFNEIE BIT(4) /*!< receive FIFO non-empty interrupt enable */ +#define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */ +#define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */ +#define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ + +/* global receive status read and pop register bits definitions */ +#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ +#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ +#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ +#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ +#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ + +/* global receive FIFO length register bits definitions */ +#define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */ + +/* host non-periodic transmit FIFO length register bits definitions */ +#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ +#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ + +/* USB IN endpoint 0 transmit FIFO length register bits definitions */ +#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ +#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ + +/* host non-periodic transmit FIFO/queue status register bits definitions */ +#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ +#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */ +#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */ +#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ +#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ +#define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + +/* global core configuration register bits definitions */ +#define GCCFG_VBUSIG BIT(21) /*!< vbus ignored */ +#define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */ +#define GCCFG_VBUSBCEN BIT(19) /*!< the VBUS B-device comparer enable */ +#define GCCFG_VBUSACEN BIT(18) /*!< the VBUS A-device comparer enable */ +#define GCCFG_PWRON BIT(16) /*!< power on */ + +/* core ID register bits definitions */ +#define CID_CID BITS(0, 31) /*!< core ID */ + +/* host periodic transmit FIFO length register bits definitions */ +#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */ +#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */ + +/* device IN endpoint transmit FIFO length register bits definitions */ +#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ +#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ + +/* host control register bits definitions */ +#define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */ +#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ + +/* host frame interval register bits definitions */ +#define HFT_FRI BITS(0, 15) /*!< frame interval */ + +/* host frame information remaining register bits definitions */ +#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ +#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ + +/* host periodic transmit FIFO/queue status register bits definitions */ +#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */ +#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */ +#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */ +#define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ +#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ +#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ +#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + +#define TFQSTAT_TXFS BITS(0, 15) +#define TFQSTAT_CNUM BITS(27, 30) + +/* host all channels interrupt register bits definitions */ +#define HACHINT_HACHINT BITS(0, 11) /*!< host all channel interrupts */ + +/* host all channels interrupt enable register bits definitions */ +#define HACHINTEN_CINTEN BITS(0, 11) /*!< channel interrupt enable */ + +/* host port control and status register bits definitions */ +#define HPCS_PS BITS(17, 18) /*!< port speed */ +#define HPCS_PP BIT(12) /*!< port power */ +#define HPCS_PLST BITS(10, 11) /*!< port line status */ +#define HPCS_PRST BIT(8) /*!< port reset */ +#define HPCS_PSP BIT(7) /*!< port suspend */ +#define HPCS_PREM BIT(6) /*!< port resume */ +#define HPCS_PEDC BIT(3) /*!< port enable/disable change */ +#define HPCS_PE BIT(2) /*!< port enable */ +#define HPCS_PCD BIT(1) /*!< port connect detected */ +#define HPCS_PCST BIT(0) /*!< port connect status */ + +/* host channel-x control register bits definitions */ +#define HCHCTL_CEN BIT(31) /*!< channel enable */ +#define HCHCTL_CDIS BIT(30) /*!< channel disable */ +#define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ +#define HCHCTL_DAR BITS(22, 28) /*!< device address */ +#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ +#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define HCHCTL_LSD BIT(17) /*!< low-speed device */ +#define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ +#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ +#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ + +/* host channel-x split transaction register bits definitions */ +#define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */ +#define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */ +#define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */ +#define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */ +#define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */ + +/* host channel-x interrupt flag register bits definitions */ +#define HCHINTF_DTER BIT(10) /*!< data toggle error */ +#define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */ +#define HCHINTF_BBER BIT(8) /*!< babble error */ +#define HCHINTF_USBER BIT(7) /*!< USB bus Error */ +#define HCHINTF_NYET BIT(6) /*!< NYET */ +#define HCHINTF_ACK BIT(5) /*!< ACK */ +#define HCHINTF_NAK BIT(4) /*!< NAK */ +#define HCHINTF_STALL BIT(3) /*!< STALL */ +#define HCHINTF_DMAER BIT(2) /*!< DMA error */ +#define HCHINTF_CH BIT(1) /*!< channel halted */ +#define HCHINTF_TF BIT(0) /*!< transfer finished */ + +/* host channel-x interrupt enable register bits definitions */ +#define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */ +#define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */ +#define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */ +#define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */ +#define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */ +#define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */ +#define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */ +#define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */ +#define HCHINTEN_DMAERIE BIT(2) /*!< DMA error interrupt enable */ +#define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */ +#define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ + +/* host channel-x transfer length register bits definitions */ +#define HCHLEN_PING BIT(31) /*!< PING token request */ +#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ +#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ +#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ + +/* host channel-x DMA address register bits definitions */ +#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ + +#define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */ + +#define PORT_SPEED_HIGH PORT_SPEED(0U) /*!< high speed */ +#define PORT_SPEED_FULL PORT_SPEED(1U) /*!< full speed */ +#define PORT_SPEED_LOW PORT_SPEED(2U) /*!< low speed */ + +#define PIPE_CTL_DAR(x) (((uint32_t)(x) << 22) & HCHCTL_DAR) /*!< device address */ +#define PIPE_CTL_EPTYPE(x) (((uint32_t)(x) << 18) & HCHCTL_EPTYPE) /*!< endpoint type */ +#define PIPE_CTL_EPNUM(x) (((uint32_t)(x) << 11) & HCHCTL_EPNUM) /*!< endpoint number */ +#define PIPE_CTL_EPDIR(x) (((uint32_t)(x) << 15) & HCHCTL_EPDIR) /*!< endpoint direction */ +#define PIPE_CTL_EPMPL(x) (((uint32_t)(x) << 0) & HCHCTL_MPL) /*!< maximum packet length */ +#define PIPE_CTL_LSD(x) (((uint32_t)(x) << 17) & HCHCTL_LSD) /*!< low-Speed device */ + +#define PIPE_XFER_PCNT(x) (((uint32_t)(x) << 19) & HCHLEN_PCNT) /*!< packet count */ +#define PIPE_XFER_DPID(x) (((uint32_t)(x) << 29) & HCHLEN_DPID) /*!< data PID */ + +#define PIPE_DPID_DATA0 PIPE_XFER_DPID(0) /*!< DATA0 */ +#define PIPE_DPID_DATA1 PIPE_XFER_DPID(2) /*!< DATA1 */ +#define PIPE_DPID_DATA2 PIPE_XFER_DPID(1) /*!< DATA2 */ +#define PIPE_DPID_SETUP PIPE_XFER_DPID(3) /*!< MDATA (non-control)/SETUP (control) */ + +extern const uint32_t PIPE_DPID[2]; + +/* device configuration registers bits definitions */ +#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ +#define DCFG_DAR BITS(4, 10) /*!< device address */ +#define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */ +#define DCFG_DS BITS(0, 1) /*!< device speed */ + +/* device control registers bits definitions */ +#define DCTL_POIF BIT(11) /*!< power-on initialization finished */ +#define DCTL_CGONAK BIT(10) /*!< clear global OUT NAK */ +#define DCTL_SGONAK BIT(9) /*!< set global OUT NAK */ +#define DCTL_CGINAK BIT(8) /*!< clear global IN NAK */ +#define DCTL_SGINAK BIT(7) /*!< set global IN NAK */ +#define DCTL_GONS BIT(3) /*!< global OUT NAK status */ +#define DCTL_GINS BIT(2) /*!< global IN NAK status */ +#define DCTL_SD BIT(1) /*!< soft disconnect */ +#define DCTL_RWKUP BIT(0) /*!< remote wakeup */ + +/* device status registers bits definitions */ +#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ +#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ +#define DSTAT_SPST BIT(0) /*!< suspend status */ + +/* device IN endpoint common interrupt enable registers bits definitions */ +#define DIEPINTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */ +#define DIEPINTEN_TXFEEN BIT(7) /*!< transmit FIFO empty interrupt enable bit */ +#define DIEPINTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */ +#define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */ +#define DIEPINTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */ +#define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ +#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + +/* device OUT endpoint common interrupt enable registers bits definitions */ +#define DOEPINTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */ +#define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */ +#define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint Rx FIFO overrun interrupt enable bit */ +#define DOEPINTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */ +#define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ +#define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + +/* device all endpoints interrupt registers bits definitions */ +#define DAEPINT_OEPITB BITS(16, 21) /*!< device all OUT endpoint interrupt bits */ +#define DAEPINT_IEPITB BITS(0, 5) /*!< device all IN endpoint interrupt bits */ + +/* device all endpoints interrupt enable registers bits definitions */ +#define DAEPINTEN_OEPIE BITS(16, 21) /*!< OUT endpoint interrupt enable */ +#define DAEPINTEN_IEPIE BITS(0, 3) /*!< IN endpoint interrupt enable */ + +/* device Vbus discharge time registers bits definitions */ +#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ + +/* device Vbus pulsing time registers bits definitions */ +#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ + +/* device IN endpoint FIFO empty interrupt enable register bits definitions */ +#define DIEPFEINTEN_IEPTXFEIE BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ + +/* device endpoint 0 control register bits definitions */ +#define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ +#define DEP0CTL_SNAK BIT(27) /*!< set NAK */ +#define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ +#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ +#define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ +#define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */ +#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEP0CTL_NAKS BIT(17) /*!< NAK status */ +#define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ +#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ + +/* device endpoint x control register bits definitions */ +#define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEPCTL_EPD BIT(30) /*!< endpoint disable */ +#define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */ +#define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ +#define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */ +#define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ +#define DEPCTL_SNAK BIT(27) /*!< set NAK */ +#define DEPCTL_CNAK BIT(26) /*!< clear NAK */ +#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ +#define DEPCTL_STALL BIT(21) /*!< STALL handshake */ +#define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */ +#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEPCTL_NAKS BIT(17) /*!< NAK status */ +#define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ +#define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ +#define DEPCTL_EPACT BIT(15) /*!< endpoint active */ +#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ + +/* device IN endpoint-x interrupt flag register bits definitions */ +#define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBHS */ +#define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */ +#define DIEPINTF_IEPNE BIT(6) /*!< IN endpoint NAK effective */ +#define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint Tx FIFO underrun */ +#define DIEPINTF_CITO BIT(3) /*!< control In Timeout interrupt */ +#define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ +#define DIEPINTF_TF BIT(0) /*!< transfer finished */ + +/* device OUT endpoint-x interrupt flag register bits definitions */ +#define DOEPINTF_NYET BIT(14) /*!< NYET handshake is sent */ +#define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back SETUP packets */ +#define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint Rx FIFO overrun */ +#define DOEPINTF_STPF BIT(3) /*!< SETUP phase finished */ +#define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ +#define DOEPINTF_TF BIT(0) /*!< transfer finished */ + +/* device IN endpoint 0 transfer length register bits definitions */ +#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ +#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ + +/* device OUT endpoint 0 transfer length register bits definitions */ +#define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ +#define DOEP0LEN_PCNT BIT(19) /*!< packet count */ +#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ + +/* device OUT endpoint-x transfer length register bits definitions */ +#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ +#define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ +#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ +#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ +#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ + +/* device IN endpoint-x DMA address register bits definitions */ +#define DIEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ + +/* device OUT endpoint-x DMA address register bits definitions */ +#define DOEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ + +/* device IN endpoint-x transmit FIFO status register bits definitions */ +#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint Tx FIFO space remaining */ + +/* USB power and clock registers bits definition */ +#define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ +#define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */ + +#define RSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */ +#define RSTAT_DATA_UPDT 2U /* OUT data packet received */ +#define RSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */ +#define RSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */ +#define RSTAT_SETUP_UPDT 6U /* SETUP data packet received */ + +#define DSTAT_EM_HS_PHY_30MHZ_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */ +#define DSTAT_EM_FS_PHY_30MHZ_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */ +#define DSTAT_EM_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */ +#define DSTAT_EM_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */ + +#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */ +#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */ +#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */ +#define DPID_MDATA 3U /* device endpoint data PID is MDATA */ + +#define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1)) /*!< AHB burst type used by DMA*/ + +#define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/ +#define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA*/ +#define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA*/ +#define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA*/ +#define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA*/ + +#define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11)) /*!< end of periodic frame time configuration */ + +#define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */ +#define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */ +#define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ +#define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ + +#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0)) /*!< device speed configuration */ + +#define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ +#define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ +#define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ + +#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0)) /*!< maximum packet length configuration */ + +#define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ +#define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ +#define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */ +#define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */ + +#define DOEP0_TLEN(regval) (DOEP0LEN_TLEN & ((regval) << 0)) /*!< transfer length */ +#define DOEP0_PCNT(regval) (DOEP0LEN_PCNT & ((regval) << 19)) /*!< packet count */ +#define DOEP0_STPCNT(regval) (DOEP0LEN_STPCNT & ((regval) << 29)) /*!< SETUP packet count */ + +#define USB_ULPI_PHY 1U /*!< ULPI interface external PHY */ +#define USB_EMBEDDED_PHY 2U /*!< embedded PHY */ + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define HCTL_30_60MHZ 0U /*!< USB clock 30-60MHZ */ +#define HCTL_48MHZ 1U /*!< USB clock 48MHZ */ +#define HCTL_6MHZ 2U /*!< USB clock 6MHZ */ + +#define EP0_OUT ((uint8_t)0x00) /*!< endpoint out 0 */ +#define EP0_IN ((uint8_t)0x80) /*!< endpoint in 0 */ +#define EP1_OUT ((uint8_t)0x01) /*!< endpoint out 1 */ +#define EP1_IN ((uint8_t)0x81) /*!< endpoint in 1 */ +#define EP2_OUT ((uint8_t)0x02) /*!< endpoint out 2 */ +#define EP2_IN ((uint8_t)0x82) /*!< endpoint in 2 */ +#define EP3_OUT ((uint8_t)0x03) /*!< endpoint out 3 */ +#define EP3_IN ((uint8_t)0x83) /*!< endpoint in 3 */ +#define EP4_OUT ((uint8_t)0x04) /*!< endpoint out 4 */ +#define EP4_IN ((uint8_t)0x84) /*!< endpoint in 4 */ +#define EP5_OUT ((uint8_t)0x05) /*!< endpoint out 5 */ +#define EP5_IN ((uint8_t)0x85) /*!< endpoint in 5 */ + +#endif /* __DRV_USB_REGS_H */ diff --git a/gd32f4xx/usb_drivers/include/drv_usbd_int.h b/gd32f4xx/usb_drivers/include/drv_usbd_int.h new file mode 100644 index 00000000..c1187859 --- /dev/null +++ b/gd32f4xx/usb_drivers/include/drv_usbd_int.h @@ -0,0 +1,54 @@ +/*! + \file drv_usbd_int.h + \brief USB device mode interrupt header file + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USBD_INT_H +#define __DRV_USBD_INT_H + +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +/* function declarations */ +/* USB device-mode interrupts global service routine handler */ +void usbd_isr (usb_core_driver *udev); + +#ifdef USB_HS_DEDICATED_EP1_ENABLED +/* USB dedicated IN endpoint 1 interrupt service routine handler */ +uint32_t usbd_int_dedicated_ep1in (usb_core_driver *udev); +/* USB dedicated OUT endpoint 1 interrupt service routine handler */ +uint32_t usbd_int_dedicated_ep1out (usb_core_driver *udev); +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + +#endif /* __DRV_USBD_INT_H */ diff --git a/gd32f4xx/usb_drivers/include/drv_usbh_int.h b/gd32f4xx/usb_drivers/include/drv_usbh_int.h new file mode 100644 index 00000000..a534d73d --- /dev/null +++ b/gd32f4xx/usb_drivers/include/drv_usbh_int.h @@ -0,0 +1,56 @@ +/*! + \file drv_usbh_int.h.h + \brief USB host mode interrupt management header file + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USBH_INT_H +#define __DRV_USBH_INT_H + +#include "drv_usb_host.h" +#include "usbh_core.h" + +typedef struct _usbh_ev_cb +{ + uint8_t (*connect) (usbh_host *uhost); + uint8_t (*disconnect) (usbh_host *uhost); + uint8_t (*SOF) (usbh_host *uhost); +} usbh_ev_cb; + +extern usbh_ev_cb *usbh_int_fop; + +/* function declarations */ +/* handle global host interrupt */ +uint32_t usbh_isr (usb_core_driver *udev); + +#endif /* __DRV_USBH_INT_H */ diff --git a/gd32f4xx/usb_drivers/source/drv_usb_core.c b/gd32f4xx/usb_drivers/source/drv_usb_core.c new file mode 100644 index 00000000..0382fbeb --- /dev/null +++ b/gd32f4xx/usb_drivers/source/drv_usb_core.c @@ -0,0 +1,374 @@ +/*! + \file drv_usb_core.c + \brief USB core driver which can operate in host and device mode + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_core.h" +#include "drv_usb_hw.h" + +/* local function prototypes ('static') */ +static void usb_core_reset (usb_core_regs *usb_regs); + +/*! + \brief configure USB core basic + \param[in] usb_basic: pointer to USB capabilities + \param[in] usb_regs: USB core registers + \param[in] usb_core: USB core + \param[out] none + \retval operation status +*/ +usb_status usb_basic_init (usb_core_basic *usb_basic, + usb_core_regs *usb_regs, + usb_core_enum usb_core) +{ + /* configure USB default transfer mode as FIFO mode */ + usb_basic->transfer_mode = (uint8_t)USB_USE_FIFO; + + /* USB default speed is full-speed */ + usb_basic->core_speed = (uint8_t)USB_SPEED_FULL; + + usb_basic->core_enum = (uint8_t)usb_core; + + switch (usb_core) { + case USB_CORE_ENUM_HS: + usb_basic->base_reg = (uint32_t)USBHS_REG_BASE; + + /* set the host channel numbers */ + usb_basic->num_pipe = USBHS_MAX_CHANNEL_COUNT; + + /* set the device endpoint numbers */ + usb_basic->num_ep = USBHS_MAX_EP_COUNT; + +#ifdef USB_ULPI_PHY_ENABLED + usb_basic->phy_itf = USB_ULPI_PHY; +#else + usb_basic->phy_itf = USB_EMBEDDED_PHY; +#endif /* USB_ULPI_PHY_ENABLED */ + +#ifdef USB_HS_INTERNAL_DMA_ENABLED + usb_basic->transfer_mode = USB_USE_DMA; +#endif /* USB_HS_INTERNAL_DMA_ENABLED */ + +#ifdef USB_HS_CORE + /* configure the SOF output and the low power support */ + usb_basic->sof_enable = USBHS_SOF_OUTPUT; + usb_basic->low_power = USBHS_LOW_POWER; +#endif /* USB_HS_CORE */ + break; + + case USB_CORE_ENUM_FS: + usb_basic->base_reg = (uint32_t)USBFS_REG_BASE; + + /* set the host channel numbers */ + usb_basic->num_pipe = USBFS_MAX_CHANNEL_COUNT; + + /* set the device endpoint numbers */ + usb_basic->num_ep = USBFS_MAX_EP_COUNT; + + /* USBFS core use embedded physical layer */ + usb_basic->phy_itf = USB_EMBEDDED_PHY; + +#ifdef USB_FS_CORE + /* configure the SOF output and the low power support */ + usb_basic->sof_enable = USBFS_SOF_OUTPUT; + usb_basic->low_power = USBFS_LOW_POWER; +#endif /* USB_FS_CORE */ + break; + + default: + return USB_FAIL; + } + + /* assign main registers address */ + *usb_regs = (usb_core_regs) { + .gr = (usb_gr*) (usb_basic->base_reg + USB_REG_OFFSET_CORE), + .hr = (usb_hr*) (usb_basic->base_reg + USB_REG_OFFSET_HOST), + .dr = (usb_dr*) (usb_basic->base_reg + USB_REG_OFFSET_DEV), + + .HPCS = (uint32_t*) (usb_basic->base_reg + USB_REG_OFFSET_PORT), + .PWRCLKCTL = (uint32_t*) (usb_basic->base_reg + USB_REG_OFFSET_PWRCLKCTL) + }; + + /* assign device endpoint registers address */ + for (uint8_t i = 0U; i < usb_basic->num_ep; i++) { + usb_regs->er_in[i] = (usb_erin *) \ + (usb_basic->base_reg + USB_REG_OFFSET_EP_IN + (i * USB_REG_OFFSET_EP)); + + usb_regs->er_out[i] = (usb_erout *)\ + (usb_basic->base_reg + USB_REG_OFFSET_EP_OUT + (i * USB_REG_OFFSET_EP)); + } + + /* assign host pipe registers address */ + for (uint8_t i = 0U; i < usb_basic->num_pipe; i++) { + usb_regs->pr[i] = (usb_pr *) \ + (usb_basic->base_reg + USB_REG_OFFSET_CH_INOUT + (i * USB_REG_OFFSET_CH)); + + usb_regs->DFIFO[i] = (uint32_t *) \ + (usb_basic->base_reg + USB_DATA_FIFO_OFFSET + (i * USB_DATA_FIFO_SIZE)); + } + + return USB_OK; +} + +/*! + \brief initializes the USB controller registers and + prepares the core device mode or host mode operation + \param[in] usb_basic: pointer to USB capabilities + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval operation status +*/ +usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs) +{ + if (USB_ULPI_PHY == usb_basic.phy_itf) { + usb_regs->gr->GCCFG &= ~GCCFG_PWRON; + + if (usb_basic.sof_enable) { + usb_regs->gr->GCCFG |= GCCFG_SOFOEN; + } + + /* initialize the ULPI interface */ + usb_regs->gr->GUSBCS &= ~(GUSBCS_EMBPHY | GUSBCS_ULPIEOI); + +#ifdef USBHS_EXTERNAL_VBUS_ENABLED + /* use external VBUS driver */ + usb_regs->gr->GUSBCS |= GUSBCS_ULPIEVD; +#else + /* use internal VBUS driver */ + usb_regs->gr->GUSBCS &= ~GUSBCS_ULPIEVD; +#endif /* USBHS_EXTERNAL_VBUS_ENABLED */ + + /* soft reset the core */ + usb_core_reset (usb_regs); + } else { + usb_regs->gr->GUSBCS |= GUSBCS_EMBPHY; + + /* soft reset the core */ + usb_core_reset (usb_regs); + + /* active the transceiver and enable VBUS sensing */ + usb_regs->gr->GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; + +#ifndef VBUS_SENSING_ENABLED + usb_regs->gr->GCCFG |= GCCFG_VBUSIG; +#endif /* VBUS_SENSING_ENABLED */ + + /* enable SOF output */ + if (usb_basic.sof_enable) { + usb_regs->gr->GCCFG |= GCCFG_SOFOEN; + } + + usb_mdelay(20U); + } + + if ((uint8_t)USB_USE_DMA == usb_basic.transfer_mode) { + usb_regs->gr->GAHBCS &= ~GAHBCS_BURST; + usb_regs->gr->GAHBCS |= DMA_INCR8 | GAHBCS_DMAEN; + } + +#ifdef USE_OTG_MODE + + /* enable USB OTG features */ + usb_regs->gr->GUSBCS |= GUSBCS_HNPCEN | GUSBCS_SRPCEN; + + /* enable the USB wakeup and suspend interrupts */ + usb_regs->gr->GINTF = 0xBFFFFFFFU; + + usb_regs->gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE | \ + GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; + +#endif /* USE_OTG_MODE */ + + return USB_OK; +} + +/*! + \brief write a packet into the Tx FIFO associated with the endpoint + \param[in] usb_regs: pointer to USB core registers + \param[in] src_buf: pointer to source buffer + \param[in] fifo_num: FIFO number which is in (0..3 or 0..5) + \param[in] byte_count: packet byte count + \param[out] none + \retval operation status +*/ +usb_status usb_txfifo_write (usb_core_regs *usb_regs, + uint8_t *src_buf, + uint8_t fifo_num, + uint16_t byte_count) +{ + uint32_t word_count = (byte_count + 3U) / 4U; + + __IO uint32_t *fifo = usb_regs->DFIFO[fifo_num]; + + while (word_count-- > 0U) { + *fifo = *((__packed uint32_t *)src_buf); + + src_buf += 4U; + } + + return USB_OK; +} + +/*! + \brief read a packet from the Rx FIFO associated with the endpoint + \param[in] usb_regs: pointer to USB core registers + \param[in] dest_buf: pointer to destination buffer + \param[in] byte_count: packet byte count + \param[out] none + \retval void type pointer +*/ +void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count) +{ + uint32_t word_count = (byte_count + 3U) / 4U; + + __IO uint32_t *fifo = usb_regs->DFIFO[0]; + + while (word_count-- > 0U) { + *(__packed uint32_t *)dest_buf = *fifo; + + dest_buf += 4U; + } + + return ((void *)dest_buf); +} + +/*! + \brief flush a Tx FIFO or all Tx FIFOs + \param[in] usb_regs: pointer to USB core registers + \param[in] fifo_num: FIFO number which is in (0..3 or 0..5) + \param[out] none + \retval operation status +*/ +usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num) +{ + usb_regs->gr->GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; + + /* wait for Tx FIFO flush bit is set */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_TXFF) { + /* no operation */ + } + + /* wait for 3 PHY clocks*/ + usb_udelay(3U); + + return USB_OK; +} + +/*! + \brief flush the entire Rx FIFO + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval operation status +*/ +usb_status usb_rxfifo_flush (usb_core_regs *usb_regs) +{ + usb_regs->gr->GRSTCTL = GRSTCTL_RXFF; + + /* wait for Rx FIFO flush bit is set */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_RXFF) { + /* no operation */ + } + + /* wait for 3 PHY clocks */ + usb_udelay(3U); + + return USB_OK; +} + +/*! + \brief set endpoint or channel TX FIFO size + \param[in] usb_regs: pointer to USB core registers + \param[in] fifo: TX FIFO number + \param[in] size: assigned TX FIFO size + \param[out] none + \retval none +*/ +void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size) +{ + uint32_t tx_offset; + + tx_offset = usb_regs->gr->GRFLEN; + + if(0U == fifo) { + usb_regs->gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)size << 16) | tx_offset; + } else { + tx_offset += (usb_regs->gr->DIEP0TFLEN_HNPTFLEN) >> 16; + + for (uint8_t i = 0U; i < (fifo - 1U); i++) { + tx_offset += (usb_regs->gr->DIEPTFLEN[i] >> 16); + } + + /* multiply Tx_Size by 2 to get higher performance */ + usb_regs->gr->DIEPTFLEN[fifo - 1U] = ((uint32_t)size << 16) | tx_offset; + } +} + +/*! + \brief set USB current mode + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +void usb_curmode_set(usb_core_regs *usb_regs, uint8_t mode) +{ + usb_regs->gr->GUSBCS &= ~(GUSBCS_FDM | GUSBCS_FHM); + + if (DEVICE_MODE == mode) { + usb_regs->gr->GUSBCS |= GUSBCS_FDM; + } else if (HOST_MODE == mode) { + usb_regs->gr->GUSBCS |= GUSBCS_FHM; + } else { + /* OTG mode and other mode can not be here! */ + } +} + +/*! + \brief configure USB core to soft reset + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +static void usb_core_reset (usb_core_regs *usb_regs) +{ + /* enable core soft reset */ + usb_regs->gr->GRSTCTL |= GRSTCTL_CSRST; + + /* wait for the core to be soft reset */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_CSRST) { + /* no operation */ + } + + /* wait for additional 3 PHY clocks */ + usb_udelay(3U); +} diff --git a/gd32f4xx/usb_drivers/source/drv_usb_dev.c b/gd32f4xx/usb_drivers/source/drv_usb_dev.c new file mode 100644 index 00000000..2998f80c --- /dev/null +++ b/gd32f4xx/usb_drivers/source/drv_usb_dev.c @@ -0,0 +1,666 @@ +/*! + \file drv_usb_dev.c + \brief USB device mode low level driver + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +/* endpoint 0 max packet length */ +static const uint8_t EP0_MAXLEN[4] = { + [DSTAT_EM_HS_PHY_30MHZ_60MHZ] = EP0MPL_64, + [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = EP0MPL_64, + [DSTAT_EM_FS_PHY_48MHZ] = EP0MPL_64, + [DSTAT_EM_LS_PHY_6MHZ] = EP0MPL_8 +}; + +#ifdef USB_FS_CORE + +/* USB endpoint Tx FIFO size */ +static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] = +{ + (uint16_t)TX0_FIFO_FS_SIZE, + (uint16_t)TX1_FIFO_FS_SIZE, + (uint16_t)TX2_FIFO_FS_SIZE, + (uint16_t)TX3_FIFO_FS_SIZE +}; + +#endif /* USBFS_CORE */ + +#ifdef USB_HS_CORE + +uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT] = +{ + (uint16_t)TX0_FIFO_HS_SIZE, + (uint16_t)TX1_FIFO_HS_SIZE, + (uint16_t)TX2_FIFO_HS_SIZE, + (uint16_t)TX3_FIFO_HS_SIZE, + (uint16_t)TX4_FIFO_HS_SIZE, + (uint16_t)TX5_FIFO_HS_SIZE +}; + +#endif /* USBHS_CORE */ + +/*! + \brief initialize USB core registers for device mode + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +usb_status usb_devcore_init (usb_core_driver *udev) +{ + uint8_t i; + + /* restart the PHY clock (maybe don't need to...) */ + *udev->regs.PWRCLKCTL = 0U; + + /* configure periodic frame interval to default value */ + udev->regs.dr->DCFG &= ~DCFG_EOPFT; + udev->regs.dr->DCFG |= FRAME_INTERVAL_80; + + udev->regs.dr->DCFG &= ~DCFG_DS; + +#ifdef USB_FS_CORE + if (udev->bp.core_enum == (uint8_t)USB_CORE_ENUM_FS) { + /* set full-speed PHY */ + udev->regs.dr->DCFG |= USB_SPEED_INP_FULL; + + /* set Rx FIFO size */ + usb_set_rxfifo(&udev->regs, RX_FIFO_FS_SIZE); + + /* set endpoint 0 to 3's Tx FIFO length and RAM address */ + for (i = 0U; i < USBFS_MAX_EP_COUNT; i++) { + usb_set_txfifo(&udev->regs, i, USBFS_TX_FIFO_SIZE[i]); + } + } +#endif /* USB_FS_CORE */ + +#ifdef USB_HS_CORE + if (udev->bp.core_enum == USB_CORE_ENUM_HS) { + if (udev->bp.phy_itf == USB_ULPI_PHY) { + udev->regs.dr->DCFG |= USB_SPEED_EXP_HIGH; + } else {/* set High speed PHY in Full speed mode */ + udev->regs.dr->DCFG |= USB_SPEED_EXP_FULL; + } + + /* Set Rx FIFO size */ + usb_set_rxfifo(&udev->regs, RX_FIFO_HS_SIZE); + + /* Set endpoint 0 to 6's TX FIFO length and RAM address */ + for (i = 0; i < USBHS_MAX_EP_COUNT; i++) { + usb_set_txfifo(&udev->regs, i, USBHS_TX_FIFO_SIZE[i]); + } + } +#endif /* USB_FS_CORE */ + + /* make sure all FIFOs are flushed */ + + /* flush all Tx FIFOs */ + (void)usb_txfifo_flush (&udev->regs, 0x10U); + + /* flush entire Rx FIFO */ + (void)usb_rxfifo_flush (&udev->regs); + + /* clear all pending device interrupts */ + udev->regs.dr->DIEPINTEN = 0U; + udev->regs.dr->DOEPINTEN = 0U; + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + udev->regs.dr->DAEPINTEN = 0U; + + /* configure all IN/OUT endpoints */ + for (i = 0U; i < udev->bp.num_ep; i++) { + if (udev->regs.er_in[i]->DIEPCTL & DEPCTL_EPEN) { + udev->regs.er_in[i]->DIEPCTL |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + udev->regs.er_in[i]->DIEPCTL = 0U; + } + + /* set IN endpoint transfer length to 0 */ + udev->regs.er_in[i]->DIEPLEN = 0U; + + /* clear all pending IN endpoint interrupts */ + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + + if (udev->regs.er_out[i]->DOEPCTL & DEPCTL_EPEN) { + udev->regs.er_out[i]->DOEPCTL |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + udev->regs.er_out[i]->DOEPCTL = 0U; + } + + /* set OUT endpoint transfer length to 0 */ + udev->regs.er_out[i]->DOEPLEN = 0U; + + /* clear all pending OUT endpoint interrupts */ + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + udev->regs.dr->DIEPINTEN |= DIEPINTEN_EPTXFUDEN; + + (void)usb_devint_enable (udev); + + return USB_OK; +} + +/*! + \brief enable the USB device mode interrupts + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +usb_status usb_devint_enable (usb_core_driver *udev) +{ + /* clear any pending USB OTG interrupts */ + udev->regs.gr->GOTGINTF = 0xFFFFFFFFU; + + /* clear any pending interrupts */ + udev->regs.gr->GINTF = 0xBFFFFFFFU; + + /* enable the USB wakeup and suspend interrupts */ + udev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; + + /* enable device_mode-related interrupts */ + if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) { + udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + } + + udev->regs.gr->GINTEN |= GINTEN_RSTIE | GINTEN_ENUMFIE | GINTEN_IEPIE |\ + GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_ISOONCIE | GINTEN_ISOINCIE; + +#ifdef VBUS_SENSING_ENABLED + udev->regs.gr->GINTEN |= GINTEN_SESIE | GINTEN_OTGIE; +#endif /* VBUS_SENSING_ENABLED */ + + return USB_OK; +} + +/*! + \brief active the USB endpoint0 transaction + \param[in] udev: pointer to USB device + \param[in] transc: the USB endpoint0 transaction + \param[out] none + \retval operation status +*/ +usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES; + + /* get the endpoint number */ + uint8_t ep_num = transc->ep_addr.num; + + if (ep_num) { + /* not endpoint 0 */ + return USB_FAIL; + } + + if (transc->ep_addr.dir) { + reg_addr = &udev->regs.er_in[0]->DIEPCTL; + } else { + reg_addr = &udev->regs.er_out[0]->DOEPCTL; + } + + /* endpoint 0 is activated after USB clock is enabled */ + *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM); + + /* set endpoint 0 maximum packet length */ + *reg_addr |= EP0_MAXLEN[enum_speed]; + + /* activate endpoint */ + *reg_addr |= ((uint32_t)transc->ep_type << 18U) | ((uint32_t)ep_num << 22U) | DEPCTL_SD0PID | DEPCTL_EPACT; + + return USB_OK; +} + +/*! + \brief active the USB transaction + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + uint32_t epinten = 0U; + uint8_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES; + + /* get the endpoint number */ + uint8_t ep_num = transc->ep_addr.num; + + /* enable endpoint interrupt number */ + if (transc->ep_addr.dir) { + reg_addr = &udev->regs.er_in[ep_num]->DIEPCTL; + + epinten = 1U << ep_num; + } else { + reg_addr = &udev->regs.er_out[ep_num]->DOEPCTL; + + epinten = 1U << (16U + ep_num); + } + + /* if the endpoint is not active, need change the endpoint control register */ + if (!(*reg_addr & DEPCTL_EPACT)) { + *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM); + + /* set endpoint maximum packet length */ + if (0U == ep_num) { + *reg_addr |= EP0_MAXLEN[enum_speed]; + } else { + *reg_addr |= transc->max_len; + } + + /* activate endpoint */ + *reg_addr |= ((uint32_t)transc->ep_type << 18U) | ((uint32_t)ep_num << 22U) | DEPCTL_SD0PID | DEPCTL_EPACT; + } + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + if ((ep_num == 1U) && (udev->bp.core_enum == USB_CORE_ENUM_HS)) { + udev->regs.dr->DEP1INTEN |= epinten; + } + else +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + { + /* enable the interrupts for this endpoint */ + udev->regs.dr->DAEPINTEN |= epinten; + } + + return USB_OK; +} + +/*! + \brief deactivate the USB transaction + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc) +{ + uint32_t epinten = 0U; + + uint8_t ep_num = transc->ep_addr.num; + + /* disable endpoint interrupt number */ + if (transc->ep_addr.dir) { + epinten = 1U << ep_num; + + udev->regs.er_in[ep_num]->DIEPCTL &= ~DEPCTL_EPACT; + } else { + epinten = 1U << (ep_num + 16U); + + udev->regs.er_out[ep_num]->DOEPCTL &= ~DEPCTL_EPACT; + } + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + if ((ep_num == 1U) && (udev->bp.core_enum == USB_CORE_ENUM_HS)) { + udev->regs.dr->DEP1INTEN &= ~epinten; + } + else +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + { + /* disable the interrupts for this endpoint */ + udev->regs.dr->DAEPINTEN &= ~epinten; + } + + return USB_OK; +} + +/*! + \brief configure USB transaction to start IN transfer + \param[in] udev: pointer to USB device + \param[in] transc: the USB IN transaction + \param[out] none + \retval operation status +*/ +usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc) +{ + usb_status status = USB_OK; + + uint8_t ep_num = transc->ep_addr.num; + + __IO uint32_t epctl = udev->regs.er_in[ep_num]->DIEPCTL; + __IO uint32_t eplen = udev->regs.er_in[ep_num]->DIEPLEN; + + eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT); + + /* zero length packet or endpoint 0 */ + if (0U == transc->xfer_len) { + /* set transfer packet count to 1 */ + eplen |= 1U << 19U; + } else { + /* set transfer packet count */ + if (0U == ep_num) { + transc->xfer_len = USB_MIN(transc->xfer_len, transc->max_len); + + eplen |= 1U << 19U; + } else { + eplen |= (((transc->xfer_len - 1U) + transc->max_len) / transc->max_len) << 19U; + } + + /* set endpoint transfer length */ + eplen |= transc->xfer_len; + + if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) { + eplen |= DIEPLEN_MCNT & (1U << 29U); + } + } + + udev->regs.er_in[ep_num]->DIEPLEN = eplen; + + if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) { + if (((udev->regs.dr->DSTAT & DSTAT_FNRSOF) >> 8U) & 0x01U) { + epctl |= DEPCTL_SEVNFRM; + } else { + epctl |= DEPCTL_SODDFRM; + } + } + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_in[ep_num]->DIEPDMAADDR = transc->dma_addr; + } + + /* enable the endpoint and clear the NAK */ + epctl |= DEPCTL_CNAK | DEPCTL_EPEN; + + udev->regs.er_in[ep_num]->DIEPCTL = epctl; + + if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) { + if (transc->ep_type != (uint8_t)USB_EPTYPE_ISOC) { + /* enable the Tx FIFO empty interrupt for this endpoint */ + if (transc->xfer_len > 0U) { + udev->regs.dr->DIEPFEINTEN |= 1U << ep_num; + } + } else { + (void)usb_txfifo_write (&udev->regs, transc->xfer_buf, ep_num, (uint16_t)transc->xfer_len); + } + } + + return status; +} + +/*! + \brief configure USB transaction to start OUT transfer + \param[in] udev: pointer to USB device + \param[in] transc: the USB OUT transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc) +{ + usb_status status = USB_OK; + + uint8_t ep_num = transc->ep_addr.num; + + uint32_t epctl = udev->regs.er_out[ep_num]->DOEPCTL; + uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN; + + eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT); + + /* zero length packet or endpoint 0 */ + if ((0U == transc->xfer_len) || (0U == ep_num)) { + /* set the transfer length to max packet size */ + eplen |= transc->max_len; + + /* set the transfer packet count to 1 */ + eplen |= 1U << 19U; + } else { + /* configure the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + uint32_t packet_count = (transc->xfer_len + transc->max_len - 1U) / transc->max_len; + + eplen |= packet_count << 19U; + eplen |= packet_count * transc->max_len; + +#ifdef INT_HIGH_BW + if (transc->ep_type == (uint8_t)USB_EPTYPE_INTR) { + eplen |= DIEPLEN_MCNT & (3U << 29U); + } +#endif /* INT_HIGH_BW */ + } + + udev->regs.er_out[ep_num]->DOEPLEN = eplen; + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_out[ep_num]->DOEPDMAADDR = transc->dma_addr; + } + + if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) { + if (transc->frame_num) { + epctl |= DEPCTL_SD1PID; + } else { + epctl |= DEPCTL_SD0PID; + } + } + + /* enable the endpoint and clear the NAK */ + epctl |= DEPCTL_EPEN | DEPCTL_CNAK; + + udev->regs.er_out[ep_num]->DOEPCTL = epctl; + + return status; +} + +/*! + \brief set the USB transaction STALL status + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t ep_num = transc->ep_addr.num; + + if (transc->ep_addr.dir) { + reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL); + + /* set the endpoint disable bit */ + if (*reg_addr & DEPCTL_EPEN) { + *reg_addr |= DEPCTL_EPD; + } + } else { + /* set the endpoint stall bit */ + reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL); + } + + /* set the endpoint stall bit */ + *reg_addr |= DEPCTL_STALL; + + return USB_OK; +} + +/*! + \brief clear the USB transaction STALL status + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval operation status +*/ +usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t ep_num = transc->ep_addr.num; + + if (transc->ep_addr.dir) { + reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL); + } else { + reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL); + } + + /* clear the endpoint stall bits */ + *reg_addr &= ~DEPCTL_STALL; + + /* reset data PID of the periodic endpoints */ + if ((transc->ep_type == (uint8_t)USB_EPTYPE_INTR) || (transc->ep_type == (uint8_t)USB_EPTYPE_BULK)) { + *reg_addr |= DEPCTL_SD0PID; + } + + return USB_OK; +} + +/*! + \brief read device IN endpoint interrupt flag register + \param[in] udev: pointer to USB device + \param[in] ep_num: endpoint number + \param[out] none + \retval interrupt value +*/ +uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num) +{ + uint32_t value = 0U, fifoemptymask, commonintmask; + + commonintmask = udev->regs.dr->DIEPINTEN; + fifoemptymask = udev->regs.dr->DIEPFEINTEN; + + /* check FIFO empty interrupt enable bit */ + commonintmask |= ((fifoemptymask >> ep_num) & 0x1U) << 7; + + value = udev->regs.er_in[ep_num]->DIEPINTF & commonintmask; + + return value; +} + +/*! + \brief configures OUT endpoint 0 to receive SETUP packets + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_ctlep_startout (usb_core_driver *udev) +{ + /* set OUT endpoint 0 receive length to 24 bytes, 1 packet and 3 setup packets */ + udev->regs.er_out[0]->DOEPLEN = DOEP0_TLEN(8U * 3U) | DOEP0_PCNT(1U) | DOEP0_STPCNT(3U); + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_out[0]->DOEPDMAADDR = (uint32_t)&udev->dev.control.req; + + /* endpoint enable */ + udev->regs.er_out[0]->DOEPCTL |= DEPCTL_EPACT | DEPCTL_EPEN; + } +} + +/*! + \brief active remote wakeup signaling + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_rwkup_active (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + if (udev->regs.dr->DSTAT & DSTAT_SPST) { + if (udev->bp.low_power) { + /* ungate USB core clock */ + *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK); + } + + /* active remote wakeup signaling */ + udev->regs.dr->DCTL |= DCTL_RWKUP; + + usb_mdelay(5U); + + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + } + } +} + +/*! + \brief active USB core clock + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_clock_active (usb_core_driver *udev) +{ + if (udev->bp.low_power) { + if (udev->regs.dr->DSTAT & DSTAT_SPST) { + /* ungate USB Core clock */ + *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK); + } + } +} + +/*! + \brief USB device suspend + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_dev_suspend (usb_core_driver *udev) +{ + __IO uint32_t devstat = udev->regs.dr->DSTAT; + + if ((udev->bp.low_power) && (devstat & DSTAT_SPST)) { + /* switch-off the USB clocks */ + *udev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK; + + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER,PMU_LOWDRIVER_DISABLE,WFI_CMD); + } +} + +/*! + \brief stop the device and clean up FIFOs + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_dev_stop (usb_core_driver *udev) +{ + uint32_t i; + + udev->dev.cur_status = 1U; + + /* clear all interrupt flag and enable bits */ + for (i = 0U; i < udev->bp.num_ep; i++) { + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + udev->regs.dr->DIEPINTEN = 0U; + udev->regs.dr->DOEPINTEN = 0U; + udev->regs.dr->DAEPINTEN = 0U; + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + + /* flush the FIFO */ + (void)usb_rxfifo_flush (&udev->regs); + (void)usb_txfifo_flush (&udev->regs, 0x10U); +} diff --git a/gd32f4xx/usb_drivers/source/drv_usb_host.c b/gd32f4xx/usb_drivers/source/drv_usb_host.c new file mode 100644 index 00000000..366504ab --- /dev/null +++ b/gd32f4xx/usb_drivers/source/drv_usb_host.c @@ -0,0 +1,477 @@ +/*! + \file drv_usb_host.c + \brief USB host mode low level driver + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "drv_usb_core.h" +#include "drv_usb_host.h" + +const uint32_t PIPE_DPID[2] = { + PIPE_DPID_DATA0, + PIPE_DPID_DATA1 +}; + +/*! + \brief initializes USB core for host mode + \param[in] udev: pointer to selected USB host + \param[out] none + \retval operation status +*/ +usb_status usb_host_init (usb_core_driver *udev) +{ + uint32_t i = 0U, inten = 0U; + + uint32_t nptxfifolen = 0U; + uint32_t ptxfifolen = 0U; + + /* restart the PHY Clock */ + *udev->regs.PWRCLKCTL = 0U; + + /* initialize host configuration register */ + if (USB_ULPI_PHY == udev->bp.phy_itf) { + usb_phyclock_config (udev, HCTL_30_60MHZ); + } else { + usb_phyclock_config (udev, HCTL_48MHZ); + } + + /* support FS/LS only */ + udev->regs.hr->HCTL &= ~HCTL_SPDFSLS; + + /* configure data FIFOs size */ +#ifdef USB_FS_CORE + if (USB_CORE_ENUM_FS == udev->bp.core_enum) { + /* set Rx FIFO size */ + udev->regs.gr->GRFLEN = USB_RX_FIFO_FS_SIZE; + + /* set non-periodic Tx FIFO size and address */ + nptxfifolen |= USB_RX_FIFO_FS_SIZE; + nptxfifolen |= USB_HTX_NPFIFO_FS_SIZE << 16U; + udev->regs.gr->DIEP0TFLEN_HNPTFLEN = nptxfifolen; + + /* set periodic Tx FIFO size and address */ + ptxfifolen |= USB_RX_FIFO_FS_SIZE + USB_HTX_NPFIFO_FS_SIZE; + ptxfifolen |= USB_HTX_PFIFO_FS_SIZE << 16U; + udev->regs.gr->HPTFLEN = ptxfifolen; + } +#endif /* USB_FS_CORE */ + +#ifdef USB_HS_CORE + if (USB_CORE_ENUM_HS == udev->bp.core_enum) { + /* set Rx FIFO size */ + udev->regs.gr->GRFLEN = USB_RX_FIFO_HS_SIZE; + + /* set non-periodic Tx FIFO size and address */ + nptxfifolen |= USB_RX_FIFO_HS_SIZE; + nptxfifolen |= USB_HTX_NPFIFO_HS_SIZE << 16U; + udev->regs.gr->DIEP0TFLEN_HNPTFLEN = nptxfifolen; + + /* set periodic Tx FIFO size and address */ + ptxfifolen |= USB_RX_FIFO_HS_SIZE + USB_HTX_NPFIFO_HS_SIZE; + ptxfifolen |= USB_HTX_PFIFO_HS_SIZE << 16U; + udev->regs.gr->HPTFLEN = ptxfifolen; + } +#endif /* USB_HS_CORE */ + +#ifdef USE_OTG_MODE + + /* clear host set HNP enable in the usb_otg control register */ + udev->regs.gr->GOTGCS &= ~GOTGCS_HHNPEN; + +#endif /* USE_OTG_MODE */ + + /* make sure the FIFOs are flushed */ + + /* flush all Tx FIFOs in device or host mode */ + usb_txfifo_flush (&udev->regs, 0x10U); + + /* flush the entire Rx FIFO */ + usb_rxfifo_flush (&udev->regs); + + /* disable all interrupts */ + udev->regs.gr->GINTEN = 0U; + + /* clear any pending USB OTG interrupts */ + udev->regs.gr->GOTGINTF = 0xFFFFFFFFU; + + /* enable the USB wakeup and suspend interrupts */ + udev->regs.gr->GINTF = 0xBFFFFFFFU; + + /* clear all pending host channel interrupts */ + for (i = 0U; i < udev->bp.num_pipe; i++) { + udev->regs.pr[i]->HCHINTF = 0xFFFFFFFFU; + udev->regs.pr[i]->HCHINTEN = 0U; + } + +#ifndef USE_OTG_MODE + usb_portvbus_switch (udev, 1U); +#endif /* USE_OTG_MODE */ + + udev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; + + /* enable host_mode-related interrupts */ + if (USB_USE_FIFO == udev->bp.transfer_mode) { + inten = GINTEN_RXFNEIE; + } + + inten |= GINTEN_SESIE | GINTEN_HPIE | GINTEN_HCIE | GINTEN_ISOINCIE; + + udev->regs.gr->GINTEN |= inten; + + inten = GINTEN_DISCIE | GINTEN_SOFIE; + + udev->regs.gr->GINTEN &= ~inten; + + return USB_OK; +} + +/*! + \brief control the VBUS to power + \param[in] udev: pointer to selected usb host + \param[in] state: VBUS state + \param[out] none + \retval none +*/ +void usb_portvbus_switch (usb_core_driver *udev, uint8_t state) +{ + uint32_t port = 0U; + + /* enable or disable the external charge pump */ + usb_vbus_drive (state); + + /* turn on the host port power. */ + port = usb_port_read (udev); + + if (!(port & HPCS_PP) && (1U == state)) { + port |= HPCS_PP; + } + + if ((port & HPCS_PP) && (0U == state)) { + port &= ~HPCS_PP; + } + + *udev->regs.HPCS = port; + + usb_mdelay (200U); +} + +/*! + \brief reset host port + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +uint32_t usb_port_reset (usb_core_driver *udev) +{ + __IO uint32_t port = usb_port_read (udev); + + *udev->regs.HPCS = port | HPCS_PRST; + + usb_mdelay(20U); /* see note */ + + *udev->regs.HPCS = port & ~HPCS_PRST; + + usb_mdelay(20U); + + return 1U; +} + +/*! + \brief initialize host pipe + \param[in] udev: pointer to USB device + \param[in] pipe_num: host pipe number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status usb_pipe_init (usb_core_driver *udev, uint8_t pipe_num) +{ + usb_status status = USB_OK; + + __IO uint32_t pp_ctl = 0U; + __IO uint32_t pp_inten = HCHINTEN_TFIE; + + usb_pipe *pp = &udev->host.pipe[pipe_num]; + + /* clear old interrupt conditions for this host channel */ + udev->regs.pr[pipe_num]->HCHINTF = 0xFFFFFFFFU; + + if (USB_USE_DMA == udev->bp.transfer_mode) { + pp_inten |= HCHINTEN_DMAERIE; + } + + if (pp->ep.dir) { + pp_inten |= HCHINTEN_BBERIE; + } + + /* enable channel interrupts required for this transfer */ + switch (pp->ep.type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE \ + | HCHINTEN_DTERIE | HCHINTEN_NAKIE; + + if (!pp->ep.dir) { + if (PORT_SPEED_HIGH == pp->dev_speed) { + pp_inten |= HCHINTEN_NYETIE; + pp_inten |= HCHINTEN_ACKIE; + } + } + break; + + case USB_EPTYPE_INTR: + pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \ + | HCHINTEN_NAKIE | HCHINTEN_REQOVRIE; + break; + + case USB_EPTYPE_ISOC: + pp_inten |= HCHINTEN_REQOVRIE | HCHINTEN_ACKIE; + + if (pp->ep.dir) { + pp_inten |= HCHINTEN_USBERIE; + } + break; + + default: + break; + } + + udev->regs.pr[pipe_num]->HCHINTEN = pp_inten; + + /* enable the top level host channel interrupt */ + udev->regs.hr->HACHINTEN |= 1U << pipe_num; + + /* make sure host channel interrupts are enabled */ + udev->regs.gr->GINTEN |= GINTEN_HCIE; + + /* program the host channel control register */ + pp_ctl |= PIPE_CTL_DAR(pp->dev_addr); + pp_ctl |= PIPE_CTL_EPNUM(pp->ep.num); + pp_ctl |= PIPE_CTL_EPDIR(pp->ep.dir); + pp_ctl |= PIPE_CTL_EPTYPE(pp->ep.type); + pp_ctl |= PIPE_CTL_LSD(pp->dev_speed == PORT_SPEED_LOW); + + pp_ctl |= pp->ep.mps; + pp_ctl |= ((uint32_t)(pp->ep.type == USB_EPTYPE_INTR) << 29U) & HCHCTL_ODDFRM; + + udev->regs.pr[pipe_num]->HCHCTL = pp_ctl; + + return status; +} + +/*! + \brief prepare host channel for transferring packets + \param[in] udev: pointer to USB device + \param[in] pipe_num: host pipe number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status usb_pipe_xfer (usb_core_driver *udev, uint8_t pipe_num) +{ + usb_status status = USB_OK; + + uint16_t dword_len = 0U; + uint16_t packet_count = 0U; + + __IO uint32_t pp_ctl = 0U; + + usb_pipe *pp = &udev->host.pipe[pipe_num]; + + uint16_t max_packet_len = pp->ep.mps; + + /* compute the expected number of packets associated to the transfer */ + if (pp->xfer_len > 0U) { + packet_count = (uint16_t)((pp->xfer_len + max_packet_len - 1U) / max_packet_len); + + if (packet_count > HC_MAX_PACKET_COUNT) { + packet_count = HC_MAX_PACKET_COUNT; + pp->xfer_len = (uint16_t)(packet_count * max_packet_len); + } + } else { + packet_count = 1U; + } + + if (pp->ep.dir) { + pp->xfer_len = (uint16_t)(packet_count * max_packet_len); + } + + /* initialize the host channel transfer information */ + udev->regs.pr[pipe_num]->HCHLEN = pp->xfer_len | pp->DPID | PIPE_XFER_PCNT(packet_count); + + if (USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.pr[pipe_num]->HCHDMAADDR = (unsigned int)pp->xfer_buf; + } + + pp_ctl = udev->regs.pr[pipe_num]->HCHCTL; + + if (usb_frame_even(udev)) { + pp_ctl |= HCHCTL_ODDFRM; + } else { + pp_ctl &= ~HCHCTL_ODDFRM; + } + + /* set host channel enabled */ + pp_ctl |= HCHCTL_CEN; + pp_ctl &= ~HCHCTL_CDIS; + + udev->regs.pr[pipe_num]->HCHCTL = pp_ctl; + + if (USB_USE_FIFO == udev->bp.transfer_mode) { + if ((0U == pp->ep.dir) && (pp->xfer_len > 0U)) { + switch (pp->ep.type) { + /* non-periodic transfer */ + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + dword_len = (uint16_t)((pp->xfer_len + 3U) / 4U); + + /* check if there is enough space in FIFO space */ + if (dword_len > (udev->regs.gr->HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { + /* need to process data in nptxfempty interrupt */ + udev->regs.gr->GINTEN |= GINTEN_NPTXFEIE; + } + break; + + /* periodic transfer */ + case USB_EPTYPE_INTR: + case USB_EPTYPE_ISOC: + dword_len = (uint16_t)((pp->xfer_len + 3U) / 4U); + + /* check if there is enough space in fifo space */ + if (dword_len > (udev->regs.hr->HPTFQSTAT & HPTFQSTAT_PTXFS)) { + /* need to process data in ptxfempty interrupt */ + udev->regs.gr->GINTEN |= GINTEN_PTXFEIE; + } + break; + + default: + break; + } + + /* write packet into the Tx fifo. */ + usb_txfifo_write (&udev->regs, pp->xfer_buf, pipe_num, (uint16_t)pp->xfer_len); + } + } + + return status; +} + +/*! + \brief halt pipe + \param[in] udev: pointer to USB device + \param[in] pipe_num: host pipe number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status usb_pipe_halt (usb_core_driver *udev, uint8_t pipe_num) +{ + __IO uint32_t pp_ctl = udev->regs.pr[pipe_num]->HCHCTL; + + uint8_t ep_type = (uint8_t)((pp_ctl & HCHCTL_EPTYPE) >> 18U); + + pp_ctl |= HCHCTL_CEN | HCHCTL_CDIS; + + switch (ep_type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + if (0U == (udev->regs.gr->HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { + pp_ctl &= ~HCHCTL_CEN; + } + break; + + case USB_EPTYPE_INTR: + case USB_EPTYPE_ISOC: + if (0U == (udev->regs.hr->HPTFQSTAT & HPTFQSTAT_PTXFS)) { + pp_ctl &= ~HCHCTL_CEN; + } + break; + + default: + break; + } + + udev->regs.pr[pipe_num]->HCHCTL = pp_ctl; + + return USB_OK; +} + +/*! + \brief configure host pipe to do ping operation + \param[in] udev: pointer to USB device + \param[in] pipe_num: host pipe number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status usb_pipe_ping (usb_core_driver *udev, uint8_t pipe_num) +{ + uint32_t pp_ctl = 0U; + + udev->regs.pr[pipe_num]->HCHLEN = HCHLEN_PING | (HCHLEN_PCNT & (1U << 19U)); + + pp_ctl = udev->regs.pr[pipe_num]->HCHCTL; + + pp_ctl |= HCHCTL_CEN; + pp_ctl &= ~HCHCTL_CDIS; + + udev->regs.pr[pipe_num]->HCHCTL = pp_ctl; + + return USB_OK; +} + +/*! + \brief stop the USB host and clean up FIFO + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_host_stop (usb_core_driver *udev) +{ + uint32_t i; + __IO uint32_t pp_ctl = 0U; + + udev->regs.hr->HACHINTEN = 0x0U; + udev->regs.hr->HACHINT = 0xFFFFFFFFU; + + /* flush out any leftover queued requests. */ + for (i = 0U; i < udev->bp.num_pipe; i++) { + pp_ctl = udev->regs.pr[i]->HCHCTL; + + pp_ctl &= ~(HCHCTL_CEN | HCHCTL_EPDIR); + pp_ctl |= HCHCTL_CDIS; + + udev->regs.pr[i]->HCHCTL = pp_ctl; + } + + /* flush the FIFO */ + usb_rxfifo_flush (&udev->regs); + usb_txfifo_flush (&udev->regs, 0x10U); +} diff --git a/gd32f4xx/usb_drivers/source/drv_usbd_int.c b/gd32f4xx/usb_drivers/source/drv_usbd_int.c new file mode 100644 index 00000000..309f712e --- /dev/null +++ b/gd32f4xx/usb_drivers/source/drv_usbd_int.c @@ -0,0 +1,590 @@ +/*! + \file drv_usbd_int.c + \brief USB device mode interrupt routines + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_conf.h" +#include "drv_usbd_int.h" +#include "usbd_transc.h" + +/* local function prototypes ('static') */ +static uint32_t usbd_int_epout (usb_core_driver *udev); +static uint32_t usbd_int_epin (usb_core_driver *udev); +static uint32_t usbd_int_rxfifo (usb_core_driver *udev); +static uint32_t usbd_int_reset (usb_core_driver *udev); +static uint32_t usbd_int_enumfinish (usb_core_driver *udev); +static uint32_t usbd_int_suspend (usb_core_driver *udev); +static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num); + +static const uint8_t USB_SPEED[4] = { + [DSTAT_EM_HS_PHY_30MHZ_60MHZ] = (uint8_t)USB_SPEED_HIGH, + [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = (uint8_t)USB_SPEED_FULL, + [DSTAT_EM_FS_PHY_48MHZ] = (uint8_t)USB_SPEED_FULL, + [DSTAT_EM_LS_PHY_6MHZ] = (uint8_t)USB_SPEED_LOW +}; + +/*! + \brief USB device-mode interrupts global service routine handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_isr (usb_core_driver *udev) +{ + if (HOST_MODE != (udev->regs.gr->GINTF & GINTF_COPM)) { + uint32_t intr = udev->regs.gr->GINTF; + intr &= udev->regs.gr->GINTEN; + + /* there are no interrupts, avoid spurious interrupt */ + if (!intr) { + return; + } + + /* OUT endpoints interrupts */ + if (intr & GINTF_OEPIF) { + (void)usbd_int_epout (udev); + } + + /* IN endpoints interrupts */ + if (intr & GINTF_IEPIF) { + (void)usbd_int_epin (udev); + } + + /* suspend interrupt */ + if (intr & GINTF_SP) { + (void)usbd_int_suspend (udev); + } + + /* wakeup interrupt */ + if (intr & GINTF_WKUPIF) { + /* inform upper layer by the resume event */ + udev->dev.cur_status = USBD_CONFIGURED; + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_WKUPIF; + } + + /* start of frame interrupt */ + if (intr & GINTF_SOF) { + if (udev->dev.class_core->SOF) { + (void)udev->dev.class_core->SOF(udev); + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_SOF; + } + + /* receive FIFO not empty interrupt */ + if (intr & GINTF_RXFNEIF) { + (void)usbd_int_rxfifo (udev); + } + + /* USB reset interrupt */ + if (intr & GINTF_RST) { + (void)usbd_int_reset (udev); + } + + /* enumeration has been done interrupt */ + if (intr & GINTF_ENUMFIF) { + (void)usbd_int_enumfinish (udev); + } + + /* incomplete synchronization IN transfer interrupt*/ + if (intr & GINTF_ISOINCIF) { + if (NULL != udev->dev.class_core->incomplete_isoc_in) { + (void)udev->dev.class_core->incomplete_isoc_in(udev); + } + + /* Clear interrupt */ + udev->regs.gr->GINTF = GINTF_ISOINCIF; + } + + /* incomplete synchronization OUT transfer interrupt*/ + if (intr & GINTF_ISOONCIF) { + if (NULL != udev->dev.class_core->incomplete_isoc_out) { + (void)udev->dev.class_core->incomplete_isoc_out(udev); + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_ISOONCIF; + } + +#ifdef VBUS_SENSING_ENABLED + + /* session request interrupt */ + if (intr & GINTF_SESIF) { + udev->regs.gr->GINTF = GINTF_SESIF; + } + + /* OTG mode interrupt */ + if (intr & GINTF_OTGIF) { + if(udev->regs.gr->GOTGINTF & GOTGINTF_SESEND) { + + } + + /* clear OTG interrupt */ + udev->regs.gr->GINTF = GINTF_OTGIF; + } +#endif /* VBUS_SENSING_ENABLED */ + } +} + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + +/*! + \brief USB dedicated OUT endpoint 1 interrupt service routine handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +uint32_t usbd_int_dedicated_ep1out (usb_core_driver *udev) +{ + uint32_t oepintr = 0U; + uint32_t oeplen = 0U; + + oepintr = udev->regs.er_out[1]->DOEPINTF; + oepintr &= udev->regs.dr->DOEP1INTEN; + + /* transfer complete */ + if(oepintr & DOEPINTF_TF){ + /* clear the bit in DOEPINTn for this interrupt */ + udev->regs.er_out[1]->DOEPINTF = DOEPINTF_TF; + + if(USB_USE_DMA == udev->bp.transfer_mode){ + oeplen = udev->regs.er_out[1]->DOEPLEN; + + /* to do : handle more than one single max packet size packet */ + udev->dev.transc_out[1].xfer_count = udev->dev.transc_out[1].max_len - \ + (oeplen & DEPLEN_TLEN); + } + + /* rx complete */ + usbd_out_transc (udev, 1U); + } + + return 1U; +} + +/*! + \brief USB dedicated IN endpoint 1 interrupt service routine handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +uint32_t usbd_int_dedicated_ep1in (usb_core_driver *udev) +{ + uint32_t inten, intr, emptyen; + + inten = udev->regs.dr->DIEP1INTEN; + emptyen = udev->regs.dr->DIEPFEINTEN; + + inten |= ((emptyen >> 1 ) & 0x1) << 7; + + intr = udev->regs.er_in[1]->DIEPINTF & inten; + + if(intr & DIEPINTF_TF){ + udev->regs.dr->DIEPFEINTEN &= ~(0x1 << 1); + + udev->regs.er_in[1]->DIEPINTF = DIEPINTF_TF; + + /* TX complete */ + usbd_in_transc (udev, 1); + } + + if(intr & DIEPINTF_TXFE){ + usbd_emptytxfifo_write(udev, 1); + + udev->regs.er_in[1]->DIEPINTF = DIEPINTF_TXFE; + } + + return 1; +} + +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + +/*! + \brief indicates that an OUT endpoint has a pending interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_epout (usb_core_driver *udev) +{ + uint32_t epintnum = 0U; + uint8_t ep_num = 0U; + + for (epintnum = usb_oepintnum_read (udev); epintnum; epintnum >>= 1, ep_num++) { + if (epintnum & 0x01U) { + __IO uint32_t oepintr = usb_oepintr_read (udev, ep_num); + + /* transfer complete interrupt */ + if (oepintr & DOEPINTF_TF) { + /* clear the bit in DOEPINTF for this interrupt */ + udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_TF; + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + __IO uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN; + + udev->dev.transc_out[ep_num].xfer_count = udev->dev.transc_out[ep_num].max_len - \ + (eplen & DEPLEN_TLEN); + } + + /* inform upper layer: data ready */ + (void)usbd_out_transc (udev, ep_num); + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + if ((0U == ep_num) && ((uint8_t)USB_CTL_STATUS_OUT == udev->dev.control.ctl_state)) { + usb_ctlep_startout (udev); + } + } + } + + /* setup phase finished interrupt (control endpoints) */ + if (oepintr & DOEPINTF_STPF) { + /* inform the upper layer that a setup packet is available */ + (void)usbd_setup_transc (udev); + + udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_STPF; + } + } + } + + return 1U; +} + +/*! + \brief indicates that an IN endpoint has a pending interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_epin (usb_core_driver *udev) +{ + uint32_t epintnum = 0U; + uint8_t ep_num = 0U; + + for (epintnum = usb_iepintnum_read (udev); epintnum; epintnum >>= 1, ep_num++) { + if (epintnum & 0x1U) { + __IO uint32_t iepintr = usb_iepintr_read (udev, ep_num); + + if (iepintr & DIEPINTF_TF) { + udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TF; + + /* data transmission is completed */ + (void)usbd_in_transc (udev, ep_num); + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + if ((0U == ep_num) && ((uint8_t)USB_CTL_STATUS_IN == udev->dev.control.ctl_state)) { + usb_ctlep_startout (udev); + } + } + } + + if (iepintr & DIEPINTF_TXFE) { + usbd_emptytxfifo_write (udev, (uint32_t)ep_num); + + udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TXFE; + } + } + } + + return 1U; +} + +/*! + \brief handle the RX status queue level interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_rxfifo (usb_core_driver *udev) +{ + usb_transc *transc = NULL; + + uint8_t data_PID = 0U; + uint32_t bcount = 0U; + + __IO uint32_t devrxstat = 0U; + + /* disable the Rx status queue non-empty interrupt */ + udev->regs.gr->GINTEN &= ~GINTEN_RXFNEIE; + + /* get the status from the top of the FIFO */ + devrxstat = udev->regs.gr->GRSTATP; + + uint8_t ep_num = (uint8_t)(devrxstat & GRSTATRP_EPNUM); + + transc = &udev->dev.transc_out[ep_num]; + + bcount = (devrxstat & GRSTATRP_BCOUNT) >> 4U; + data_PID = (uint8_t)((devrxstat & GRSTATRP_DPID) >> 15U); + +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + #ifndef USE_450Z_EVAL + /* ensure no-DMA mode can work */ + if (0U == (udev->regs.er_out[ep_num]->DOEPLEN & DEPLEN_PCNT)) { + uint32_t devepctl = udev->regs.er_out[ep_num]->DOEPCTL; + + devepctl |= DEPCTL_SNAK; + devepctl &= ~DEPCTL_EPEN; + devepctl &= ~DEPCTL_EPD; + + udev->regs.er_out[ep_num]->DOEPCTL = devepctl; + } + #endif /* USE_450Z_EVAL */ +#endif /* USE_USB_HS && USE_ULPI_PHY */ + + switch ((devrxstat & GRSTATRP_RPCKST) >> 17U) { + case RSTAT_GOUT_NAK: + break; + + case RSTAT_DATA_UPDT: + if (bcount > 0U) { + (void)usb_rxfifo_read (&udev->regs, transc->xfer_buf, (uint16_t)bcount); + + transc->xfer_buf += bcount; + transc->xfer_count += bcount; + } + break; + + case RSTAT_XFER_COMP: + /* trigger the OUT endpoint interrupt */ + break; + + case RSTAT_SETUP_COMP: + /* trigger the OUT endpoint interrupt */ + break; + + case RSTAT_SETUP_UPDT: + if ((0U == transc->ep_addr.num) && (8U == bcount) && (DPID_DATA0 == data_PID)) { + /* copy the setup packet received in FIFO into the setup buffer in RAM */ + (void)usb_rxfifo_read (&udev->regs, (uint8_t *)&udev->dev.control.req, (uint16_t)bcount); + + transc->xfer_count += bcount; + } + break; + + default: + break; + } + + /* enable the Rx status queue level interrupt */ + udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + + return 1U; +} + +/*! + \brief handle USB reset interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_int_reset (usb_core_driver *udev) +{ + uint32_t i; + + /* clear the remote wakeup signaling */ + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + + /* flush the Tx FIFO */ + (void)usb_txfifo_flush (&udev->regs, 0U); + + for (i = 0U; i < udev->bp.num_ep; i++) { + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + /* clear all pending device endpoint interrupts */ + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + + /* enable endpoint 0 interrupts */ + udev->regs.dr->DAEPINTEN = 1U | (1U << 16U); + + /* enable OUT endpoint interrupts */ + udev->regs.dr->DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN; + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + udev->regs.dr->DOEP1INTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN; +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + + /* enable IN endpoint interrupts */ + udev->regs.dr->DIEPINTEN = DIEPINTEN_TFEN; + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + udev->regs.dr->DIEP1INTEN = DIEPINTEN_TFEN; +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + + /* reset device address */ + udev->regs.dr->DCFG &= ~DCFG_DAR; + + /* configure endpoint 0 to receive SETUP packets */ + usb_ctlep_startout (udev); + + /* clear USB reset interrupt */ + udev->regs.gr->GINTF = GINTF_RST; + + udev->dev.transc_out[0] = (usb_transc) { + .ep_type = USB_EPTYPE_CTRL, + .max_len = USB_FS_EP0_MAX_LEN + }; + + (void)usb_transc_active (udev, &udev->dev.transc_out[0]); + + udev->dev.transc_in[0] = (usb_transc) { + .ep_addr = { + .dir = 1U + }, + + .ep_type = USB_EPTYPE_CTRL, + .max_len = USB_FS_EP0_MAX_LEN + }; + + (void)usb_transc_active (udev, &udev->dev.transc_in[0]); + + /* upon reset call user call back */ + udev->dev.cur_status = (uint8_t)USBD_DEFAULT; + + return 1U; +} + +/*! + \brief handle USB speed enumeration finish interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_int_enumfinish (usb_core_driver *udev) +{ + uint8_t enum_speed = (uint8_t)((udev->regs.dr->DSTAT & DSTAT_ES) >> 1U); + + udev->regs.dr->DCTL &= ~DCTL_CGINAK; + udev->regs.dr->DCTL |= DCTL_CGINAK; + + udev->regs.gr->GUSBCS &= ~GUSBCS_UTT; + + /* set USB turn-around time based on device speed and PHY interface */ + if (USB_SPEED[enum_speed] == (uint8_t)USB_SPEED_HIGH) { + udev->bp.core_speed = (uint8_t)USB_SPEED_HIGH; + + udev->regs.gr->GUSBCS |= 0x09U << 10U; + } else { + udev->bp.core_speed = (uint8_t)USB_SPEED_FULL; + + udev->regs.gr->GUSBCS |= 0x05U << 10U; + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_ENUMFIF; + + return 1U; +} + +/*! + \brief USB suspend interrupt handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_suspend (usb_core_driver *udev) +{ + __IO uint8_t low_power = udev->bp.low_power; + __IO uint8_t suspend = (uint8_t)(udev->regs.dr->DSTAT & DSTAT_SPST); + __IO uint8_t is_configured = (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) ? 1U : 0U; + + udev->dev.backup_status = udev->dev.cur_status; + udev->dev.cur_status = (uint8_t)USBD_SUSPENDED; + + if (low_power && suspend && is_configured) { + /* switch-off the OTG clocks */ + *udev->regs.PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK; + + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD); + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_SP; + + return 1U; +} + +/*! + \brief check FIFO for the next packet to be loaded + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier which is in (0..3) + \param[out] none + \retval status +*/ +static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num) +{ + uint32_t len; + uint32_t word_count; + + usb_transc *transc = &udev->dev.transc_in[ep_num]; + + len = transc->xfer_len - transc->xfer_count; + + /* get the data length to write */ + if (len > transc->max_len) { + len = transc->max_len; + } + + word_count = (len + 3U) / 4U; + + while (((udev->regs.er_in[ep_num]->DIEPTFSTAT & DIEPTFSTAT_IEPTFS) >= word_count) && \ + (transc->xfer_count < transc->xfer_len)) { + len = transc->xfer_len - transc->xfer_count; + + if (len > transc->max_len) { + len = transc->max_len; + } + + /* write FIFO in word(4bytes) */ + word_count = (len + 3U) / 4U; + + /* write the FIFO */ + (void)usb_txfifo_write (&udev->regs, transc->xfer_buf, (uint8_t)ep_num, (uint16_t)len); + + transc->xfer_buf += len; + transc->xfer_count += len; + + if (transc->xfer_count == transc->xfer_len) { + /* disable the device endpoint FIFO empty interrupt */ + udev->regs.dr->DIEPFEINTEN &= ~(0x01U << ep_num); + } + } + + return 1U; +} diff --git a/gd32f4xx/usb_drivers/source/drv_usbh_int.c b/gd32f4xx/usb_drivers/source/drv_usbh_int.c new file mode 100644 index 00000000..4d3ebb4b --- /dev/null +++ b/gd32f4xx/usb_drivers/source/drv_usbh_int.c @@ -0,0 +1,630 @@ +/*! + \file drv_usbh_int.c + \brief USB host mode interrupt handler file + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usbh_int.h" + +#if defined (__CC_ARM) /*!< ARM compiler */ + #pragma O0 +#elif defined (__GNUC__) /*!< GNU compiler */ + #pragma GCC optimize ("O0") +#elif defined (__TASKING__) /*!< TASKING compiler */ + #pragma optimize=0 +#endif /* __CC_ARM */ + +/* local function prototypes ('static') */ +static uint32_t usbh_int_port (usb_core_driver *udev); +static uint32_t usbh_int_pipe (usb_core_driver *udev); +static uint32_t usbh_int_pipe_in (usb_core_driver *udev, uint32_t pp_num); +static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num); +static uint32_t usbh_int_rxfifonoempty (usb_core_driver *udev); +static uint32_t usbh_int_txfifoempty (usb_core_driver *udev, usb_pipe_mode pp_mode); + +/*! + \brief handle global host interrupt + \param[in] udev: pointer to USB core instance + \param[out] none + \retval operation status +*/ +uint32_t usbh_isr (usb_core_driver *udev) +{ + uint32_t retval = 0U; + + __IO uint32_t intr = 0U; + + /* check if host mode */ + if (HOST_MODE == (udev->regs.gr->GINTF & GINTF_COPM)) { + intr = usb_coreintr_get(&udev->regs); + + if (!intr) { + return 0U; + } + + if (intr & GINTF_SOF) { + usbh_int_fop->SOF(udev->host.data); + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_SOF; + } + + if (intr & GINTF_RXFNEIF) { + retval |= usbh_int_rxfifonoempty (udev); + } + + if (intr & GINTF_NPTXFEIF) { + retval |= usbh_int_txfifoempty (udev, PIPE_NON_PERIOD); + } + + if (intr & GINTF_PTXFEIF) { + retval |= usbh_int_txfifoempty (udev, PIPE_PERIOD); + } + + if (intr & GINTF_HCIF) { + retval |= usbh_int_pipe (udev); + } + + if (intr & GINTF_HPIF) { + retval |= usbh_int_port (udev); + } + + if (intr & GINTF_DISCIF) { + usbh_int_fop->disconnect(udev->host.data); + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_DISCIF; + } + + if (intr & GINTF_ISOONCIF) { + udev->regs.pr[0]->HCHCTL |= HCHCTL_CEN | HCHCTL_CDIS; + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_ISOONCIF; + } + + if (intr & GINTF_SESIF) { + usb_portvbus_switch (udev, 1U); + + udev->regs.gr->GINTF = GINTF_SESIF; + } + + if (intr & GINTF_WKUPIF) { + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_WKUPIF; + } + } + + return retval; +} + +/*! + \brief handle USB pipe halt + \param[in] udev: pointer to USB core instance + \param[in] pp_num: pp_num: host channel number which is in (0..7) + \param[in] pp_int: pipe interrupt + \param[in] pp_status: pipe status + \param[out] none + \retval none +*/ +static inline void usb_pp_halt (usb_core_driver *udev, + uint8_t pp_num, + uint32_t pp_int, + usb_pipe_staus pp_status) +{ + udev->regs.pr[pp_num]->HCHINTEN |= HCHINTEN_CHIE; + + usb_pipe_halt(udev, pp_num); + + udev->regs.pr[pp_num]->HCHINTF = pp_int; + + udev->host.pipe[pp_num].pp_status = pp_status; +} + +/*! + \brief handle the host port interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +#if defined (__ICCARM__) /*!< IAR compiler */ + #pragma optimize = none +#endif /* __ICCARM */ +static uint32_t usbh_int_port (usb_core_driver *udev) +{ + uint32_t retval = 0U; + + /* note: when the USB PHY use USB HS PHY, the flag is needed */ + uint8_t port_reset = 0U; + + __IO uint32_t port_state = *udev->regs.HPCS; + + /* clear the interrupt bits in GINTSTS */ + port_state &= ~(HPCS_PE | HPCS_PCD | HPCS_PEDC); + + /* port connect detected */ + if (*udev->regs.HPCS & HPCS_PCD) { + port_state |= HPCS_PCD; + + usbh_int_fop->connect(udev->host.data); + + retval |= 1U; + } + + /* port enable changed */ + if (*udev->regs.HPCS & HPCS_PEDC) { + port_state |= HPCS_PEDC; + + if (*udev->regs.HPCS & HPCS_PE) { + uint32_t port_speed = usb_curspeed_get(udev); + uint32_t clock_type = udev->regs.hr->HCTL & HCTL_CLKSEL; + + udev->host.connect_status = 1U; + + if (PORT_SPEED_LOW == port_speed) { + udev->regs.hr->HFT = 6000U; + + if (HCTL_6MHZ != clock_type) { + if (USB_EMBEDDED_PHY == udev->bp.phy_itf) { + usb_phyclock_config (udev, HCTL_6MHZ); + } + + port_reset = 1U; + } + } else if (PORT_SPEED_FULL == port_speed) { + udev->regs.hr->HFT = 48000U; + + if (HCTL_48MHZ != clock_type) { + if (USB_EMBEDDED_PHY == udev->bp.phy_itf) { + usb_phyclock_config (udev, HCTL_48MHZ); + } + + port_reset = 1U; + } + } else { + /* for high speed device and others */ + port_reset = 1U; + } + + udev->host.port_enabled = 1; + + udev->regs.gr->GINTEN |= GINTEN_DISCIE | GINTEN_SOFIE; + } else { + udev->host.port_enabled = 0; + } + } + + if (port_reset) { + usb_port_reset(udev); + } + + /* clear port interrupts */ + *udev->regs.HPCS = port_state; + + return retval; +} + +/*! + \brief handle all host channels interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_int_pipe (usb_core_driver *udev) +{ + uint32_t pp_num = 0U; + uint32_t retval = 0U; + + for (pp_num = 0U; pp_num < udev->bp.num_pipe; pp_num++) { + if ((udev->regs.hr->HACHINT & HACHINT_HACHINT) & (1UL << pp_num)) { + if (udev->regs.pr[pp_num]->HCHCTL & HCHCTL_EPDIR) { + retval |= usbh_int_pipe_in (udev, pp_num); + } else { + retval |= usbh_int_pipe_out (udev, pp_num); + } + } + } + + return retval; +} + +/*! + \brief handle the IN channel interrupt + \param[in] udev: pointer to USB device instance + \param[in] pp_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +#if defined (__ICCARM__) /*!< IAR compiler */ + #pragma optimize = none +#endif /* __ICCARM */ +static uint32_t usbh_int_pipe_in (usb_core_driver *udev, uint32_t pp_num) +{ + usb_pr *pp_reg = udev->regs.pr[pp_num]; + + usb_pipe *pp = &udev->host.pipe[pp_num]; + + uint32_t intr_pp = pp_reg->HCHINTF; + intr_pp &= pp_reg->HCHINTEN; + + uint8_t ep_type = (uint8_t)((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U); + + if (intr_pp & HCHINTF_ACK) { + pp_reg->HCHINTF = HCHINTF_ACK; + } else if (intr_pp & HCHINTF_STALL) { + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_STALL, PIPE_STALL); + pp_reg->HCHINTF = HCHINTF_NAK; + + /* note: When there is a 'STALL', reset also NAK, + else, the udev->host.pp_status = HC_STALL + will be overwritten by 'NAK' in code below */ + intr_pp &= ~HCHINTF_NAK; + } else if (intr_pp & HCHINTF_DTER) { + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_DTER, PIPE_DTGERR); + pp_reg->HCHINTF = HCHINTF_NAK; + } else { + /* no operation */ + } + + if (intr_pp & HCHINTF_REQOVR) { + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_REQOVR, PIPE_REQOVR); + } else if (intr_pp & HCHINTF_TF) { + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + udev->host.backup_xfercount[pp_num] = pp->xfer_len - (pp_reg->HCHLEN & HCHLEN_TLEN); + } + + pp->pp_status = PIPE_XF; + pp->err_count = 0U; + + pp_reg->HCHINTF = HCHINTF_TF; + + switch (ep_type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_XF); + + pp->data_toggle_in ^= 1U; + break; + + case USB_EPTYPE_INTR: + case USB_EPTYPE_ISOC: + pp_reg->HCHCTL |= HCHCTL_ODDFRM; + pp->urb_state = URB_DONE; + break; + + default: + break; + } + } else if (intr_pp & HCHINTF_CH) { + pp_reg->HCHINTEN &= ~HCHINTEN_CHIE; + + switch (pp->pp_status) { + case PIPE_XF: + pp->urb_state = URB_DONE; + break; + + case PIPE_STALL: + pp->urb_state = URB_STALL; + break; + + case PIPE_TRACERR: + case PIPE_DTGERR: + pp->err_count = 0U; + pp->urb_state = URB_ERROR; + + pp->data_toggle_in ^= 1U; + break; + + case PIPE_IDLE: + case PIPE_HALTED: + case PIPE_NAK: + case PIPE_NYET: + case PIPE_BBERR: + case PIPE_REQOVR: + default: + if((uint8_t)USB_EPTYPE_INTR == ep_type) { + pp->data_toggle_in ^= 1U; + } + break; + } + + pp_reg->HCHINTF = HCHINTF_CH; + } else if (intr_pp & HCHINTF_USBER) { + pp->err_count++; + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_USBER, PIPE_TRACERR); + } else if (intr_pp & HCHINTF_NAK) { + switch (ep_type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + /* re-activate the channel */ + pp_reg->HCHCTL = (pp_reg->HCHCTL | HCHCTL_CEN) & ~HCHCTL_CDIS; + break; + + case USB_EPTYPE_INTR: + pp_reg->HCHINTEN |= HCHINTEN_CHIE; + + (void)usb_pipe_halt(udev, (uint8_t)pp_num); + break; + + default: + break; + } + + pp->pp_status = PIPE_NAK; + + pp_reg->HCHINTF = HCHINTF_NAK; + } else { + /* no operation */ + } + + return 1U; +} + +/*! + \brief handle the OUT channel interrupt + \param[in] udev: pointer to USB device instance + \param[in] pp_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +#if defined (__ICCARM__) /*!< IAR compiler */ + #pragma optimize = none +#endif /* __ICCARM */ +static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num) +{ + usbh_host *uhost = udev->host.data; + usb_pr *pp_reg = udev->regs.pr[pp_num]; + usb_pipe *pp = &udev->host.pipe[pp_num]; + uint32_t intr_pp = pp_reg->HCHINTF; + intr_pp &= pp_reg->HCHINTEN; + + if (intr_pp & HCHINTF_ACK) { + if (1U == udev->host.pipe[pp_num].do_ping) { + udev->host.pipe[pp_num].do_ping = 0; + pp->err_count = 0U; + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_ACK, pp->pp_status); + } + + pp_reg->HCHINTF = HCHINTF_ACK; + } else if (intr_pp & HCHINTF_STALL) { + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_STALL, PIPE_STALL); + } else if (intr_pp & HCHINTF_DTER) { + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_DTER, PIPE_DTGERR); + pp_reg->HCHINTF = HCHINTF_NAK; + } else if (intr_pp & HCHINTF_REQOVR) { + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_REQOVR, PIPE_REQOVR); + } else if (intr_pp & HCHINTF_TF) { + pp->err_count = 0U; + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_TF, PIPE_XF); + } else if (intr_pp & HCHINTF_NAK) { + if (0U == udev->host.pipe[pp_num].do_ping) { + if (1U == udev->host.pipe[pp_num].supp_ping) { + udev->host.pipe[pp_num].do_ping = 1; + } + } + + pp->err_count = 0U; + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_NAK); + } else if (intr_pp & HCHINTF_USBER) { + pp->err_count++; + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_USBER, PIPE_TRACERR); + } else if (intr_pp & HCHINTF_NYET) { + if (CTL_STATUS_OUT != uhost->control.ctl_state) { + if (0U == udev->host.pipe[pp_num].do_ping) { + if (1U == udev->host.pipe[pp_num].supp_ping) { + udev->host.pipe[pp_num].do_ping = 1; + } + } + + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NYET, PIPE_NYET); + } else { + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NYET, PIPE_XF); + } + + pp->err_count = 0U; + } else if (intr_pp & HCHINTF_CH) { + udev->regs.pr[pp_num]->HCHINTEN &= ~HCHINTEN_CHIE; + + switch (pp->pp_status) { + case PIPE_XF: + pp->urb_state = URB_DONE; + + if ((uint8_t)USB_EPTYPE_BULK == ((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U)) { + pp->data_toggle_out ^= 1U; + } + break; + + case PIPE_NAK: + case PIPE_NYET: + pp->urb_state = URB_NOTREADY; + break; + + case PIPE_STALL: + pp->urb_state = URB_STALL; + break; + + case PIPE_TRACERR: + if (3U == pp->err_count) { + pp->urb_state = URB_ERROR; + pp->err_count = 0U; + } + break; + + case PIPE_IDLE: + case PIPE_HALTED: + case PIPE_BBERR: + case PIPE_REQOVR: + case PIPE_DTGERR: + default: + break; + } + + pp_reg->HCHINTF = HCHINTF_CH; + } else { + /* no operation */ + } + + return 1U; +} + +/*! + \brief handle the RX FIFO non-empty interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +#if defined (__ICCARM__) /*!< IAR compiler */ + #pragma optimize = none +#endif /* __ICCARM */ +static uint32_t usbh_int_rxfifonoempty (usb_core_driver *udev) +{ + uint32_t count = 0U, xfer_count = 0U; + + __IO uint8_t pp_num = 0U; + __IO uint32_t rx_stat = 0U; + + /* disable the RX status queue level interrupt */ + udev->regs.gr->GINTEN &= ~GINTEN_RXFNEIE; + + rx_stat = udev->regs.gr->GRSTATP; + pp_num = (uint8_t)(rx_stat & GRSTATRP_CNUM); + + switch ((rx_stat & GRSTATRP_RPCKST) >> 17U) { + case GRXSTS_PKTSTS_IN: + count = (rx_stat & GRSTATRP_BCOUNT) >> 4U; + + /* read the data into the host buffer. */ + if ((count > 0U) && (NULL != udev->host.pipe[pp_num].xfer_buf)) { + (void)usb_rxfifo_read (&udev->regs, udev->host.pipe[pp_num].xfer_buf, (uint16_t)count); + + /* manage multiple transfer packet */ + udev->host.pipe[pp_num].xfer_buf += count; + udev->host.pipe[pp_num].xfer_count += count; + + xfer_count = udev->host.pipe[pp_num].xfer_count; + + udev->host.backup_xfercount[pp_num] = xfer_count; + + if (udev->regs.pr[pp_num]->HCHLEN & HCHLEN_PCNT) { + /* re-activate the channel when more packets are expected */ + uint32_t pp_ctl = udev->regs.pr[pp_num]->HCHCTL; + + pp_ctl |= HCHCTL_CEN; + pp_ctl &= ~HCHCTL_CDIS; + + udev->regs.pr[pp_num]->HCHCTL = pp_ctl; + } + } + break; + + case GRXSTS_PKTSTS_IN_XFER_COMP: + break; + + case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + count = (rx_stat & GRSTATRP_BCOUNT) >> 4U; + + while (count > 0U) { + rx_stat = udev->regs.gr->GRSTATP; + count--; + } + break; + + case GRXSTS_PKTSTS_CH_HALTED: + break; + + default: + break; + } + + /* enable the RX status queue level interrupt */ + udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + + return 1U; +} + +/*! + \brief handle the TX FIFO empty interrupt + \param[in] udev: pointer to USB device instance + \param[in] pp_mode: pipe mode + \param[out] none + \retval operation status +*/ +#if defined (__ICCARM__) /*!< IAR compiler */ + #pragma optimize = none +#endif /* __ICCARM */ +static uint32_t usbh_int_txfifoempty (usb_core_driver *udev, usb_pipe_mode pp_mode) +{ + uint8_t pp_num = 0U; + uint16_t word_count = 0U, len = 0U; + __IO uint32_t *txfiforeg = 0U, txfifostate = 0U; + + if (PIPE_NON_PERIOD == pp_mode) { + txfiforeg = &udev->regs.gr->HNPTFQSTAT; + } else if (PIPE_PERIOD == pp_mode) { + txfiforeg = &udev->regs.hr->HPTFQSTAT; + } else { + return 0U; + } + + txfifostate = *txfiforeg; + + pp_num = (uint8_t)((txfifostate & TFQSTAT_CNUM) >> 27U); + + word_count = (uint16_t)(udev->host.pipe[pp_num].xfer_len + 3U) / 4U; + + while (((txfifostate & TFQSTAT_TXFS) >= word_count) && (0U != udev->host.pipe[pp_num].xfer_len)) { + len = (uint16_t)(txfifostate & TFQSTAT_TXFS) * 4U; + + if (len > udev->host.pipe[pp_num].xfer_len) { + /* last packet */ + len = (uint16_t)udev->host.pipe[pp_num].xfer_len; + + if (PIPE_NON_PERIOD == pp_mode) { + udev->regs.gr->GINTEN &= ~GINTEN_NPTXFEIE; + } else { + udev->regs.gr->GINTEN &= ~GINTEN_PTXFEIE; + } + } + + word_count = (uint16_t)((udev->host.pipe[pp_num].xfer_len + 3U) / 4U); + usb_txfifo_write (&udev->regs, udev->host.pipe[pp_num].xfer_buf, pp_num, len); + + udev->host.pipe[pp_num].xfer_buf += len; + udev->host.pipe[pp_num].xfer_len -= len; + udev->host.pipe[pp_num].xfer_count += len; + + txfifostate = *txfiforeg; + } + + return 1U; +} diff --git a/scripts/gd32headers.py b/scripts/gd32headers.py index 33bcc5b2..b16a3c70 100644 --- a/scripts/gd32headers.py +++ b/scripts/gd32headers.py @@ -30,6 +30,8 @@ def main(hal_path, output): # obtain all available APIs for each series apis = dict() + usb_series = list() + usb_headers = list() for entry in sorted(hal_path.iterdir()): if not entry.is_dir() or not entry.name.startswith("gd32"): continue @@ -51,6 +53,16 @@ def main(hal_path, output): apis[api] = list() apis[api].append(entry.name) + usb_drivers = entry / "usb_drivers" / "include" + if not usb_drivers.exists(): + continue + + usb_series.append(entry.name) + + # All usb headers are same between gd32 series. + if not usb_headers: + usb_headers = [p.name for p in usb_drivers.iterdir()] + if output.exists(): shutil.rmtree(output) output.mkdir(parents=True) @@ -70,6 +82,24 @@ def main(hal_path, output): f.write(f"#include <{series}_{api}.h>\n") f.write("#endif\n") + usb_header_file = output / ("gd32_usb.h") + with open(usb_header_file, "w") as f: + f.write("/*\n") + f.write(" * NOTE: Autogenerated file using gd32headers.py\n") + f.write(" *\n") + f.write(" * SPDX-License-Identifier: Apache-2.0\n") + f.write(" */\n\n") + + for series in usb_series: + f.write(f"#if " if series == usb_series[0] else "\t") + f.write(f"defined(CONFIG_SOC_SERIES_{series.upper()})") + f.write(" || \\\n" if series != usb_series[-1] else "\n") + + for header in usb_headers: + f.write("#include <" + header + ">\n") + + f.write("#endif\n") + if __name__ == "__main__": parser = argparse.ArgumentParser()