nrfx: Update to version 3.12.0

Update nrfx to the recently released version. See
https://github.com/NordicSemiconductor/nrfx/blob/v3.12.0/CHANGELOG.md
for a list of changes that this version introduces.

Origin: nrfx
License: BSD 3-Clause
URL: https://github.com/NordicSemiconductor/nrfx/tree/v3.12.0
commit: db85149b1871aa09e8ff8ed240a177e8406ead58
Purpose: Provide peripheral drivers for Nordic SoCs
Maintained-by: External

Signed-off-by: Nikodem Kastelik <[email protected]>

Author: nika-nordic

nrfx/CHANGELOG.md

@@ -1,6 +1,38 @@
 # Changelog
 All notable changes to this project are documented in this file.
 
+## [3.12.0] - 2025-06-02
+### Added
+- Added a driver, HALY and HAL for MRAMC.
+- Added support for 24 MHz clock on the nRF54LM20A Eng A SoC in the CLOCK driver.
+- Added the workaround for nRF54L Series anomaly 55 in the SPIM driver.
+- Added functions for setting compare value in an optimized way in the GRTC driver.
+- Added a function for retrieving compare value in the GRTC driver.
+- Added a function for setting and getting an event handler in the TWIM driver.
+- Added support for chopping and high-speed analog pin configuration on the affected SoCs in the SAADC driver.
+- Added a function for getting a driver instance associated with a DPPIC instance located on the same APB as the specified peripheral in the DPPI driver.
+- Added functions for managing all RAM blocks at once in the ``nrfx_ram_ctrl`` helper.
+- Added a function for getting a pin drive setting in the GPIO HAL.
+- Added a function for checking whether the XIP is active in the QSPI HAL.
+- Added an enumerator for frequency divider ratio in the AUXPLL HAL.
+- Added new functions for enabling, disabling and checking status of voltage regulators in POWER HAL. Previous functions are deprecated.
+- Added functions for getting the SUBSCRIBE and PUBLISH registers in all HALs.
+
+### Changed
+- Updated MDK to version 8.71.1.
+- Optimized counter setting and reading procedures to make them more performant in the GRTC driver.
+- Restored USBPWRRDY event clearing before initialization in the USBREG driver.
+
+### Fixed
+- Fixed 8-bit samples handling for the nRF54 Series in the SAADC driver.
+- Fixed missing DONE event clearing after a calibration in the SAADC driver.
+- Fixed the processing order when events arrive simultaneously in the SPIS driver.
+- Fixed pin idle state handling for the nRF54 Series in the PWM driver.
+- Fixed the counter reading procedure for VPR cores in the GRTC HALY.
+- Fixed the custom ratio setting procedure in the PDM HALY.
+- Fixed missing array list functionality for the nRF54 Series in the SPIM HAL.
+- Fixed a workaround for the anomaly 161 on the nRF5340 SoC in non-secure variant in the RESET HAL.
+
 ## [3.11.0] - 2025-02-24
 ### Added
 - Added the workaround for nRF54L Series anomaly 39 in the CLOCK driver.

nrfx/README

@@ -2,10 +2,10 @@ nrfx
 ####
 
 Origin:
-   https://github.com/NordicSemiconductor/nrfx/tree/v3.11.0
+   https://github.com/NordicSemiconductor/nrfx/tree/v3.12.0
 
 Status:
-   v3.11.0
+   v3.12.0
 
 Purpose:
    With added proper shims adapting it to Zephyr's APIs, nrfx will provide
@@ -32,7 +32,7 @@ URL:
    https://github.com/NordicSemiconductor/nrfx
 
 commit:
-   bacc23e5387964462e5638f0c914c2ab5802fa3c
+   db85149b1871aa09e8ff8ed240a177e8406ead58
 
 Maintained-by:
    External
@@ -41,4 +41,4 @@ License:
    BSD-3-Clause
 
 License Link:
-   https://github.com/NordicSemiconductor/nrfx/blob/v3.11.0/LICENSE
+   https://github.com/NordicSemiconductor/nrfx/blob/v3.12.0/LICENSE

nrfx/doc/drv_supp_matrix.dox

@@ -46,6 +46,8 @@ For a complete overview, see @ref nrfx_drv_supp_matrix.
 
 @ref nrf_mpc
 
+@ref nrf_mramc
+
 @ref nrf_nfct
 
 @ref nrf_pdm

nrfx/doc/nrf7120_enga.dox

@@ -50,7 +50,7 @@ PROJECT_NAME           = "nrfx"
 
 ### EDIT THIS ###
 
-PROJECT_NUMBER         = "3.11"
+PROJECT_NUMBER         = "3.12"
 
 # Using the PROJECT_BRIEF tag one can provide an optional one line description
 # for a project that appears at the top of each page and should give viewer a

nrfx/doc/nrfx.doxyfile

@@ -71,6 +71,8 @@
 
 @defgroup nrf_mpu MPU
 
+@defgroup nrf_mramc MRAMC
+
 @defgroup nrf_mutex MUTEX
 
 @defgroup nrf_mvdma MVDMA

nrfx/doc/nrfx_api.dox

@@ -52,27 +52,30 @@ extern "C" {
 /** @brief Clock events. */
 typedef enum
 {
-    NRFX_CLOCK_EVT_HFCLK_STARTED      = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_HF_STARTED_MASK),      ///< HFCLK has been started.
+    NRFX_CLOCK_EVT_HFCLK_STARTED      = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_HF_STARTED_MASK),       ///< HFCLK has been started.
 #if NRF_CLOCK_HAS_PLL
-    NRFX_CLOCK_EVT_PLL_STARTED        = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_PLL_STARTED_MASK),     ///< PLL has been started.
+    NRFX_CLOCK_EVT_PLL_STARTED        = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_PLL_STARTED_MASK),      ///< PLL has been started.
 #endif
-    NRFX_CLOCK_EVT_LFCLK_STARTED      = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_LF_STARTED_MASK),      ///< LFCLK has been started.
+    NRFX_CLOCK_EVT_LFCLK_STARTED      = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_LF_STARTED_MASK),       ///< LFCLK has been started.
 #if NRF_CLOCK_HAS_CALIBRATION_TIMER
-    NRFX_CLOCK_EVT_CTTO               = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_CTTO_MASK),            ///< Calibration timeout.
+    NRFX_CLOCK_EVT_CTTO               = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_CTTO_MASK),             ///< Calibration timeout.
 #endif
 #if NRF_CLOCK_HAS_CALIBRATION
-    NRFX_CLOCK_EVT_CAL_DONE           = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_DONE_MASK),            ///< Calibration has been done.
+    NRFX_CLOCK_EVT_CAL_DONE           = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_DONE_MASK),             ///< Calibration has been done.
 #endif
 #if NRF_CLOCK_HAS_HFCLKAUDIO
-    NRFX_CLOCK_EVT_HFCLKAUDIO_STARTED = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_HFAUDIO_STARTED_MASK), ///< HFCLKAUDIO has been started.
+    NRFX_CLOCK_EVT_HFCLKAUDIO_STARTED = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_HFAUDIO_STARTED_MASK),  ///< HFCLKAUDIO has been started.
+#endif
+#if NRF_CLOCK_HAS_HFCLK24M
+    NRFX_CLOCK_EVT_HFCLK24M_STARTED   = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_HFCLK24M_STARTED_MASK), ///< HFCLK24M has been started.
 #endif
 #if NRF_CLOCK_HAS_HFCLK192M
-    NRFX_CLOCK_EVT_HFCLK192M_STARTED  = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_HF192M_STARTED_MASK),  ///< HFCLK192M has been started.
+    NRFX_CLOCK_EVT_HFCLK192M_STARTED  = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_HF192M_STARTED_MASK),   ///< HFCLK192M has been started.
 #endif
 #if NRF_CLOCK_HAS_XO_TUNE
-    NRFX_CLOCK_EVT_XO_TUNED           = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_XOTUNED_MASK),         ///< XO tune has been done.
-    NRFX_CLOCK_EVT_XO_TUNE_ERROR      = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_XOTUNEERROR_MASK),     ///< XO is not tuned.
-    NRFX_CLOCK_EVT_XO_TUNE_FAILED     = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_XOTUNEFAILED_MASK),    ///< XO tune operation failed.
+    NRFX_CLOCK_EVT_XO_TUNED           = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_XOTUNED_MASK),          ///< XO tune has been done.
+    NRFX_CLOCK_EVT_XO_TUNE_ERROR      = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_XOTUNEERROR_MASK),      ///< XO is not tuned.
+    NRFX_CLOCK_EVT_XO_TUNE_FAILED     = NRFX_BITMASK_TO_BITPOS(NRF_CLOCK_INT_XOTUNEFAILED_MASK),     ///< XO tune operation failed.
 #endif
 } nrfx_clock_evt_type_t;
 

nrfx/drivers/include/nrfx_clock.h

@@ -239,6 +239,20 @@ nrfx_err_t nrfx_dppi_group_enable(nrfx_dppi_t const *      p_instance,
 nrfx_err_t nrfx_dppi_group_disable(nrfx_dppi_t const *      p_instance,
                                    nrf_dppi_channel_group_t group);
 
+/**
+ * @brief Function for getting a driver instance for DPPI located on the same bus
+ *        as the specified peripheral.
+ *
+ * @param[in]  peripheral_addr Address of a peripheral.
+ * @param[out] p_instance      Pointer to the DPPI driver instance structure
+ *                             to be filled.
+ *
+ * @retval NRFX_SUCCESS             DPPI driver instance was found.
+ * @retval NRFX_ERROR_INVALID_PARAM No DPPI driver instance was found
+ *                                  for a given peripheral address.
+ */
+nrfx_err_t nrfx_dppi_periph_get(uint32_t peripheral_addr, nrfx_dppi_t * p_instance);
+
 #else
 
 #if !defined(NRF_DPPIC_INDEX)

nrfx/drivers/include/nrfx_dppi.h

@@ -169,6 +169,19 @@ nrfx_err_t nrfx_grtc_sleep_configuration_get(nrfx_grtc_sleep_config_t * p_sleep_
  */
 nrfx_err_t nrfx_grtc_channel_alloc(uint8_t * p_channel);
 
+/**
+ * @brief Function for setting a callback to a channel.
+ *
+ * Function enables the interrupt for that channel.
+ *
+ * @param[in] channel   Channel.
+ * @param[in] handler   User handler called when channel expires.
+ * @param[in] p_context Context passed to the callback.
+ */
+void nrfx_grtc_channel_callback_set(uint8_t                channel,
+                                    nrfx_grtc_cc_handler_t handler,
+                                    void *                 p_context);
+
 /**
  * @brief Function for freeing the GRTC capture/compare channel.
  *
@@ -294,7 +307,6 @@ void nrfx_grtc_syscountervalid_int_disable(void);
  * @retval NRFX_ERROR_ALREADY The GRTC is already running.
  * @retval NRFX_ERROR_TIMEOUT The SYSCOUNTER failed to start due to a timeout.
  */
-
 nrfx_err_t nrfx_grtc_syscounter_start(bool busy_wait, uint8_t * p_main_cc_channel);
 
 /**
@@ -359,9 +371,29 @@ nrfx_err_t nrfx_grtc_syscounter_cc_absolute_set(nrfx_grtc_channel_t * p_chan_dat
                                                 uint64_t              val,
                                                 bool                  enable_irq);
 
+/**
+ * @brief Function for setting the absolute compare value for the SYSCOUNTER in an optimized way.
+ *
+ * Function must be called with interrupts locked. If @p safe_setting is true then
+ * it means that previous CC for that channel did not yet expire and it
+ * was set to a value earlier than @p val so there is a chance that it will
+ * expire during setting the new value. In that case compare event may be misinterpreted.
+ * Slower but safe procedure is used in that case which ensures that there will be no
+ * unexpected user callback triggered. If @p safe_setting is false then function just sets
+ * new CC value.
+ *
+ * @param[in] channel      Channel.
+ * @param[in] val          Absolute value to be set in the compare register.
+ * @param[in] safe_setting True if safe procedure is to be used, false otherwise.
+ */
+void nrfx_grtc_syscounter_cc_abs_set(uint8_t channel, uint64_t val, bool safe_setting);
+
 /**
  * @brief Function for setting the relative compare value for the SYSCOUNTER.
  *
+ * Function has no assumptions on the current channel state so channel event is cleared and
+ * interrupt can optionally be enabled for that channel.
+ *
  * @note This function marks the specified @p channel as used.
  *
  * @param[in] p_chan_data Pointer to the channel data instance structure.
@@ -379,6 +411,22 @@ nrfx_err_t nrfx_grtc_syscounter_cc_relative_set(nrfx_grtc_channel_t *
                                                 bool                              enable_irq,
                                                 nrfx_grtc_cc_relative_reference_t reference);
 
+/**
+ * @brief Function for setting the relative compare value in an optimized way.
+ *
+ * Function just sets CCADD value and does not attempt to enable or disable the interrupt.
+ * It assumes that expected channel configuration is done prior to that call.
+ * Function assumes that previously used CC value has already expired so new value
+ * can be safely set without a risk of spurious CC expiration.
+ *
+ * @param[in] channel   Channel.
+ * @param[in] val       Relative value to be set in the CCADD register.
+ * @param[in] reference Reference. Current counter value or current CC value.
+ */
+void nrfx_grtc_syscounter_cc_rel_set(uint8_t                           channel,
+                                     uint32_t                          val,
+                                     nrfx_grtc_cc_relative_reference_t reference);
+
 /**
  * @brief Function for disabling the SYSCOUNTER compare interrupt.
  *
@@ -479,7 +527,6 @@ void nrfx_grtc_active_request_set(bool active);
  * @param[out] p_counter p_counter Pointer to the variable to be filled with the SYSCOUNTER value.
  *
  * @retval NRFX_SUCCESS        The procedure was successful.
- * @retval NRFX_ERROR_INTERNAL The SYSCOUNTER (1 MHz) is not running.
  */
 nrfx_err_t nrfx_grtc_syscounter_get(uint64_t * p_counter);
 
@@ -539,6 +586,15 @@ NRFX_STATIC_INLINE bool nrfx_grtc_sys_counter_cc_enable_check(uint8_t channel);
  */
 NRFX_STATIC_INLINE bool nrfx_grtc_syscounter_compare_event_check(uint8_t channel);
 
+/**
+ * @brief Function for retrieving CC value.
+ *
+ * @param[in] channel Compare channel.
+ *
+ * @return Value read from CC register.
+ */
+NRFX_STATIC_INLINE uint64_t nrfx_grtc_sys_counter_cc_get(uint8_t channel);
+
 #if NRF_GRTC_HAS_RTCOUNTER || defined(__NRFX_DOXYGEN__)
 /**
  * @brief Function for reading the GRTC RTCOUNTER value.
@@ -590,6 +646,11 @@ NRFX_STATIC_INLINE bool nrfx_grtc_syscounter_compare_event_check(uint8_t channel
     return nrfy_grtc_sys_counter_compare_event_check(NRF_GRTC, channel);
 }
 
+NRFX_STATIC_INLINE uint64_t nrfx_grtc_sys_counter_cc_get(uint8_t channel)
+{
+    return nrfy_grtc_sys_counter_cc_get(NRF_GRTC, channel);
+}
+
 #if NRF_GRTC_HAS_RTCOUNTER
 NRFX_STATIC_INLINE uint64_t nrfx_grtc_rtcounter_get(void)
 {