nrfx: cracen: align to nrf54lm20a

Support the new HW IP version included in the 54LM20 and newer devices

Signed-off-by: Alberto Escolar Piedras <[email protected]>

Author: aescolar

nrfx/drivers/src/nrfx_cracen.c

@@ -42,10 +42,17 @@
 #include <soc/nrfx_coredep.h>
 
 /* TRNG HW chosen configuration options */
+#if defined(NRF54L15_XXAA) || defined(NRF54L10_XXAA) || defined(NRF54L05_XXAA)
 #define TRNG_CLK_DIV                0
+#else
+#define TRNG_CLK_DIV                1
+#endif
 #define TRNG_OFF_TIMER_VAL          0
 #define TRNG_INIT_WAIT_VAL        512
 #define TRNG_NUMBER_128BIT_BLOCKS   4
+#if NRF_CRACEN_RNG_HAS_BLENDING
+#define TRNG_BLENDING_METHOD      NRF_CRACEN_RNG_BLENDINGMETHOD_CONCATENATION
+#endif
 
 #define TRNG_CONDITIONING_KEY_SIZE 4 /* Size of the conditioning key: 4 words, 16 bytes */
 
@@ -89,14 +96,19 @@ static void trng_init(void)
     nrf_cracen_rng_control_set(NRF_CRACENCORE, &control_reset);
 
     /* Change from configuration defaults to what we prefer: */
+#if NRF_CRACEN_RNG_HAS_IDLETIMER
     nrf_cracen_rng_off_timer_set(NRF_CRACENCORE, TRNG_OFF_TIMER_VAL);
+#endif
     nrf_cracen_rng_clk_div_set(NRF_CRACENCORE, TRNG_CLK_DIV);
     nrf_cracen_rng_init_wait_val_set(NRF_CRACENCORE, TRNG_INIT_WAIT_VAL);
 
     /* Configure the control register and enable */
     static const nrf_cracen_rng_control_t control_enable = {
             .enable = true,
             .number_128_blocks = TRNG_NUMBER_128BIT_BLOCKS,
+#if NRF_CRACEN_RNG_HAS_BLENDING
+            .blending_method = TRNG_BLENDING_METHOD,
+#endif
     };
 
     nrf_cracen_rng_control_set(NRF_CRACENCORE, &control_enable);

nrfx/hal/nrf_cracen_rng.h

@@ -48,13 +48,41 @@ extern "C" {
  *          Random Generator (RNG) peripheral.
  */
 
+#if defined(CRACENCORE_RNGCONTROL_SWOFFTMRVAL_ResetValue) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether the TRNG FSM has an idle timer */
+#define NRF_CRACEN_RNG_HAS_IDLETIMER 1
+#else
+#define NRF_CRACEN_RNG_HAS_IDLETIMER 0
+#endif
+
+#if defined(CRACENCORE_RNGCONTROL_CONTROL_BLENDINGMETHOD_Pos) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether the TRNG has entropy blending */
+#define NRF_CRACEN_RNG_HAS_BLENDING 1
+#else
+#define NRF_CRACEN_RNG_HAS_BLENDING 0
+#endif
+
+#if NRF_CRACEN_RNG_HAS_BLENDING
+/** @brief CRACEN entropy blending methods */
+typedef enum
+{
+  NRF_CRACEN_RNG_BLENDINGMETHOD_CONCATENATION = CRACENCORE_RNGCONTROL_CONTROL_BLENDINGMETHOD_CONCATENATION, /**< Collate all rings oscillators outputs */
+  NRF_CRACEN_RNG_BLENDINGMETHOD_XORLEVEL1     = CRACENCORE_RNGCONTROL_CONTROL_BLENDINGMETHOD_XORLEVEL1,     /**< XOR bits inside each ring oscillator set */
+  NRF_CRACEN_RNG_BLENDINGMETHOD_XORLEVEL2     = CRACENCORE_RNGCONTROL_CONTROL_BLENDINGMETHOD_XORLEVEL2,     /**< Also XOR bits in-between ring oscillator sets */
+  NRF_CRACEN_RNG_BLENDINGMETHOD_VONNEUMANN    = CRACENCORE_RNGCONTROL_CONTROL_BLENDINGMETHOD_VONNEUMANN,    /**< VON-NEUMANN debiasing */
+} nrf_cracen_rng_blending_methods_t;
+#endif
+
 /** @brief CRACEN random generator configuration */
 typedef struct
 {
-    bool    enable;            /**< Enable the RNG peripheral */
-    bool    fifo_full_int_en;  /**< Enable FIFO full interrupt */
-    bool    soft_reset;        /**< Soft reset the RNG peripheral */
-    uint8_t number_128_blocks; /**< Number of 128bit blocks used for AES conditioning. Must be at least 1 */
+    bool                              enable;            /**< Enable the RNG peripheral */
+    bool                              fifo_full_int_en;  /**< Enable FIFO full interrupt */
+    bool                              soft_reset;        /**< Soft reset the RNG peripheral */
+    uint8_t                           number_128_blocks; /**< Number of 128bit blocks used for AES conditioning. Must be at least 1 */
+#if NRF_CRACEN_RNG_HAS_BLENDING
+    nrf_cracen_rng_blending_methods_t blending_method;   /**< Which blending method to use */
+#endif
 } nrf_cracen_rng_control_t;
 
 /** @brief CRACEN random generator FSM state */
@@ -63,7 +91,9 @@ typedef enum
     NRF_CRACEN_RNG_FSM_STATE_RESET        = CRACENCORE_RNGCONTROL_STATUS_STATE_RESET,    /**< RNG is not started */
     NRF_CRACEN_RNG_FSM_STATE_STARTUP      = CRACENCORE_RNGCONTROL_STATUS_STATE_STARTUP,  /**< RNG is starting */
     NRF_CRACEN_RNG_FSM_STATE_IDLE_READY   = CRACENCORE_RNGCONTROL_STATUS_STATE_IDLERON,  /**< RNG is idle, and ready to produce more data */
+#if NRF_CRACEN_RNG_HAS_IDLETIMER
     NRF_CRACEN_RNG_FSM_STATE_IDLE_STANDBY = CRACENCORE_RNGCONTROL_STATUS_STATE_IDLEROFF, /**< RNG is idle, with the ring oscillators off */
+#endif
     NRF_CRACEN_RNG_FSM_STATE_FILL_FIFO    = CRACENCORE_RNGCONTROL_STATUS_STATE_FILLFIFO, /**< RNG is filling the FIFO with entropy */
     NRF_CRACEN_RNG_FSM_STATE_ERROR        = CRACENCORE_RNGCONTROL_STATUS_STATE_ERROR,    /**< RNG has halted on an error. Reset is needed */
 } nrf_cracen_rng_fsm_state_t;
@@ -119,6 +149,7 @@ nrf_cracen_rng_fsm_state_t nrf_cracen_rng_fsm_state_get(NRF_CRACENCORE_Type cons
 NRF_STATIC_INLINE void nrf_cracen_rng_init_wait_val_set(NRF_CRACENCORE_Type * p_reg,
                                                         uint16_t              value);
 
+#if NRF_CRACEN_RNG_HAS_IDLETIMER
 /**
  * @brief Function for setting the switch off timer value
  *
@@ -127,6 +158,7 @@ NRF_STATIC_INLINE void nrf_cracen_rng_init_wait_val_set(NRF_CRACENCORE_Type * p_
  */
 NRF_STATIC_INLINE void nrf_cracen_rng_off_timer_set(NRF_CRACENCORE_Type * p_reg,
                                                     uint16_t              value);
+#endif
 
 /**
  * @brief Function for setting the entropy subsampling rate register
@@ -137,7 +169,7 @@ NRF_STATIC_INLINE void nrf_cracen_rng_off_timer_set(NRF_CRACENCORE_Type * p_reg,
  * @param[in] value Value to be written in the register.
  */
 NRF_STATIC_INLINE void nrf_cracen_rng_clk_div_set(NRF_CRACENCORE_Type * p_reg,
-                                                  uint8_t               value);
+                                                  uint16_t              value);
 
 /**
  * @brief Function for getting a word from the entropy FIFO
@@ -163,6 +195,10 @@ NRF_STATIC_INLINE void nrf_cracen_rng_control_set(NRF_CRACENCORE_Type *
             & CRACENCORE_RNGCONTROL_CONTROL_INTENFULL_Msk)
         | ((p_config->soft_reset << CRACENCORE_RNGCONTROL_CONTROL_SOFTRST_Pos)
             & CRACENCORE_RNGCONTROL_CONTROL_SOFTRST_Msk)
+#if NRF_CRACEN_RNG_HAS_BLENDING
+        | ((p_config->blending_method << CRACENCORE_RNGCONTROL_CONTROL_BLENDINGMETHOD_Pos)
+            & CRACENCORE_RNGCONTROL_CONTROL_BLENDINGMETHOD_Msk)
+#endif
         | ((p_config->number_128_blocks << CRACENCORE_RNGCONTROL_CONTROL_NB128BITBLOCKS_Pos)
             & CRACENCORE_RNGCONTROL_CONTROL_NB128BITBLOCKS_Msk);
 }
@@ -189,19 +225,29 @@ nrf_cracen_rng_fsm_state_t nrf_cracen_rng_fsm_state_get(NRF_CRACENCORE_Type cons
 NRF_STATIC_INLINE void nrf_cracen_rng_init_wait_val_set(NRF_CRACENCORE_Type * p_reg,
                                                         uint16_t              value)
 {
+#if defined(CRACENCORE_RNGCONTROL_INITWAITVAL_ResetValue)
     p_reg->RNGCONTROL.INITWAITVAL = value;
+#else
+    p_reg->RNGCONTROL.WARMUPPERIOD = value;
+#endif
 }
 
+#if NRF_CRACEN_RNG_HAS_IDLETIMER
 NRF_STATIC_INLINE void nrf_cracen_rng_off_timer_set(NRF_CRACENCORE_Type * p_reg,
                                                     uint16_t value)
 {
     p_reg->RNGCONTROL.SWOFFTMRVAL = value;
 }
+#endif
 
 NRF_STATIC_INLINE void nrf_cracen_rng_clk_div_set(NRF_CRACENCORE_Type * p_reg,
-                                                  uint8_t value)
+                                                  uint16_t value)
 {
+#if defined(CRACENCORE_RNGCONTROL_CLKDIV_ResetValue)
     p_reg->RNGCONTROL.CLKDIV = value;
+#else
+    p_reg->RNGCONTROL.SAMPLINGPERIOD = value;
+#endif
 }
 
 NRF_STATIC_INLINE uint32_t nrf_cracen_rng_fifo_get(NRF_CRACENCORE_Type const * p_reg)