diff --git a/nrfx/drivers/include/nrfx_power_compat.h b/nrfx/drivers/include/nrfx_power_compat.h index c06ae2e9..26caf804 100644 --- a/nrfx/drivers/include/nrfx_power_compat.h +++ b/nrfx/drivers/include/nrfx_power_compat.h @@ -48,18 +48,90 @@ #if NRF_REGULATORS_HAS_POF typedef nrf_regulators_pof_thr_t nrf_power_pof_thr_t; +#if defined(REGULATORS_POFCON_THRESHOLD_V090) +#define NRF_POWER_POFTHR_V09 NRF_REGULATORS_POF_THR_0V9 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V095) +#define NRF_POWER_POFTHR_V095 NRF_REGULATORS_POF_THR_0V95 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V100) +#define NRF_POWER_POFTHR_V10 NRF_REGULATORS_POF_THR_1V0 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V105) +#define NRF_POWER_POFTHR_V105 NRF_REGULATORS_POF_THR_1V05 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V110) +#define NRF_POWER_POFTHR_V11 NRF_REGULATORS_POF_THR_1V1 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V115) +#define NRF_POWER_POFTHR_V115 NRF_REGULATORS_POF_THR_1V15 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V120) +#define NRF_POWER_POFTHR_V12 NRF_REGULATORS_POF_THR_1V2 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V125) +#define NRF_POWER_POFTHR_V125 NRF_REGULATORS_POF_THR_1V25 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V130) +#define NRF_POWER_POFTHR_V13 NRF_REGULATORS_POF_THR_1V3 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V135) +#define NRF_POWER_POFTHR_V135 NRF_REGULATORS_POF_THR_1V35 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V140) +#define NRF_POWER_POFTHR_V14 NRF_REGULATORS_POF_THR_1V4 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V145) +#define NRF_POWER_POFTHR_V145 NRF_REGULATORS_POF_THR_1V45 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V150) +#define NRF_POWER_POFTHR_V15 NRF_REGULATORS_POF_THR_1V5 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V155) +#define NRF_POWER_POFTHR_V155 NRF_REGULATORS_POF_THR_1V55 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V160) +#define NRF_POWER_POFTHR_V16 NRF_REGULATORS_POF_THR_1V6 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V165) +#define NRF_POWER_POFTHR_V165 NRF_REGULATORS_POF_THR_1V65 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V17) #define NRF_POWER_POFTHR_V17 NRF_REGULATORS_POF_THR_1V7 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V18) #define NRF_POWER_POFTHR_V18 NRF_REGULATORS_POF_THR_1V8 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V19) #define NRF_POWER_POFTHR_V19 NRF_REGULATORS_POF_THR_1V9 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V20) #define NRF_POWER_POFTHR_V20 NRF_REGULATORS_POF_THR_2V0 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V21) #define NRF_POWER_POFTHR_V21 NRF_REGULATORS_POF_THR_2V1 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V22) #define NRF_POWER_POFTHR_V22 NRF_REGULATORS_POF_THR_2V2 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V23) #define NRF_POWER_POFTHR_V23 NRF_REGULATORS_POF_THR_2V3 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V24) #define NRF_POWER_POFTHR_V24 NRF_REGULATORS_POF_THR_2V4 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V25) #define NRF_POWER_POFTHR_V25 NRF_REGULATORS_POF_THR_2V5 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V26) #define NRF_POWER_POFTHR_V26 NRF_REGULATORS_POF_THR_2V6 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V27) #define NRF_POWER_POFTHR_V27 NRF_REGULATORS_POF_THR_2V7 +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V28) #define NRF_POWER_POFTHR_V28 NRF_REGULATORS_POF_THR_2V8 +#endif #if NRF_REGULATORS_HAS_POF_VDDH diff --git a/nrfx/drivers/src/nrfx_power.c b/nrfx/drivers/src/nrfx_power.c index 58c872b4..022abe41 100644 --- a/nrfx/drivers/src/nrfx_power.c +++ b/nrfx/drivers/src/nrfx_power.c @@ -224,7 +224,11 @@ void nrfx_power_pof_disable(void) #elif NRF_REGULATORS_HAS_POF nrf_regulators_pof_config_t pof_config = { .enable = false, +#if defined(REGULATORS_POFCON_THRESHOLD_V27) .thr = NRF_REGULATORS_POF_THR_2V7, +#else + .thr = NRF_REGULATORS_POF_THR_1V4, +#endif }; nrf_regulators_pof_config_set(NRF_REGULATORS, &pof_config); #endif diff --git a/nrfx/hal/nrf_regulators.h b/nrfx/hal/nrf_regulators.h index 461e423e..8136a454 100644 --- a/nrfx/hal/nrf_regulators.h +++ b/nrfx/hal/nrf_regulators.h @@ -133,6 +133,13 @@ extern "C" { #define NRF_REGULATORS_HAS_INDUCTOR_DET 0 #endif +#if defined(REGULATORS_HIBERNATOR_SYSTEMHIBERNATE_ResetValue) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether HIBERNATOR register is present. */ +#define NRF_REGULATORS_HAS_HIBERNATOR 1 +#else +#define NRF_REGULATORS_HAS_HIBERNATOR 0 +#endif + #if NRF_REGULATORS_HAS_VREG_ANY /** @brief Voltage regulators. */ typedef enum @@ -156,22 +163,90 @@ typedef enum /** @brief POF Comparator thresholds. */ typedef enum { +#if defined(REGULATORS_POFCON_THRESHOLD_V090) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_0V9 = REGULATORS_POFCON_THRESHOLD_V090, ///< Set threshold to 0.9 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V095) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_0V95 = REGULATORS_POFCON_THRESHOLD_V095, ///< Set threshold to 0.95 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V100) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_1V0 = REGULATORS_POFCON_THRESHOLD_V100, ///< Set threshold to 1.0 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V105) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_1V05 = REGULATORS_POFCON_THRESHOLD_V105, ///< Set threshold to 1.05 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V110) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_1V1 = REGULATORS_POFCON_THRESHOLD_V110, ///< Set threshold to 1.1 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V115) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_1V15 = REGULATORS_POFCON_THRESHOLD_V115, ///< Set threshold to 1.15 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V120) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_1V2 = REGULATORS_POFCON_THRESHOLD_V120, ///< Set threshold to 1.2 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V125) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_1V25 = REGULATORS_POFCON_THRESHOLD_V125, ///< Set threshold to 1.25 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V130) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_1V3 = REGULATORS_POFCON_THRESHOLD_V130, ///< Set threshold to 1.3 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V135) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_1V35 = REGULATORS_POFCON_THRESHOLD_V135, ///< Set threshold to 1.35 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V140) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_1V4 = REGULATORS_POFCON_THRESHOLD_V140, ///< Set threshold to 1.4 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V145) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_1V45 = REGULATORS_POFCON_THRESHOLD_V145, ///< Set threshold to 1.45 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V150) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_1V5 = REGULATORS_POFCON_THRESHOLD_V150, ///< Set threshold to 1.5 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V155) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_1V55 = REGULATORS_POFCON_THRESHOLD_V155, ///< Set threshold to 1.55 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V160) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_1V6 = REGULATORS_POFCON_THRESHOLD_V160, ///< Set threshold to 1.6 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V165) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_1V65 = REGULATORS_POFCON_THRESHOLD_V165, ///< Set threshold to 1.65 V. +#endif #if defined(REGULATORS_POFCON_THRESHOLD_V17) || defined(__NRFX_DOXYGEN__) - NRF_REGULATORS_POF_THR_1V7 = REGULATORS_POFCON_THRESHOLD_V17, ///< Set threshold to 1.7 V. + NRF_REGULATORS_POF_THR_1V7 = REGULATORS_POFCON_THRESHOLD_V17, ///< Set threshold to 1.7 V. #endif #if defined(REGULATORS_POFCON_THRESHOLD_V18) || defined(__NRFX_DOXYGEN__) - NRF_REGULATORS_POF_THR_1V8 = REGULATORS_POFCON_THRESHOLD_V18, ///< Set threshold to 1.8 V. -#endif - NRF_REGULATORS_POF_THR_1V9 = REGULATORS_POFCON_THRESHOLD_V19, ///< Set threshold to 1.9 V. - NRF_REGULATORS_POF_THR_2V0 = REGULATORS_POFCON_THRESHOLD_V20, ///< Set threshold to 2.0 V. - NRF_REGULATORS_POF_THR_2V1 = REGULATORS_POFCON_THRESHOLD_V21, ///< Set threshold to 2.1 V. - NRF_REGULATORS_POF_THR_2V2 = REGULATORS_POFCON_THRESHOLD_V22, ///< Set threshold to 2.2 V. - NRF_REGULATORS_POF_THR_2V3 = REGULATORS_POFCON_THRESHOLD_V23, ///< Set threshold to 2.3 V. - NRF_REGULATORS_POF_THR_2V4 = REGULATORS_POFCON_THRESHOLD_V24, ///< Set threshold to 2.4 V. - NRF_REGULATORS_POF_THR_2V5 = REGULATORS_POFCON_THRESHOLD_V25, ///< Set threshold to 2.5 V. - NRF_REGULATORS_POF_THR_2V6 = REGULATORS_POFCON_THRESHOLD_V26, ///< Set threshold to 2.6 V. - NRF_REGULATORS_POF_THR_2V7 = REGULATORS_POFCON_THRESHOLD_V27, ///< Set threshold to 2.7 V. - NRF_REGULATORS_POF_THR_2V8 = REGULATORS_POFCON_THRESHOLD_V28, ///< Set threshold to 2.8 V. + NRF_REGULATORS_POF_THR_1V8 = REGULATORS_POFCON_THRESHOLD_V18, ///< Set threshold to 1.8 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V19) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_1V9 = REGULATORS_POFCON_THRESHOLD_V19, ///< Set threshold to 1.9 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V20) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_2V0 = REGULATORS_POFCON_THRESHOLD_V20, ///< Set threshold to 2.0 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V21) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_2V1 = REGULATORS_POFCON_THRESHOLD_V21, ///< Set threshold to 2.1 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V22) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_2V2 = REGULATORS_POFCON_THRESHOLD_V22, ///< Set threshold to 2.2 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V23) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_2V3 = REGULATORS_POFCON_THRESHOLD_V23, ///< Set threshold to 2.3 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V24) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_2V4 = REGULATORS_POFCON_THRESHOLD_V24, ///< Set threshold to 2.4 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V25) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_2V5 = REGULATORS_POFCON_THRESHOLD_V25, ///< Set threshold to 2.5 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V26) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_2V6 = REGULATORS_POFCON_THRESHOLD_V26, ///< Set threshold to 2.6 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V27) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_2V7 = REGULATORS_POFCON_THRESHOLD_V27, ///< Set threshold to 2.7 V. +#endif +#if defined(REGULATORS_POFCON_THRESHOLD_V28) || defined(__NRFX_DOXYGEN__) + NRF_REGULATORS_POF_THR_2V8 = REGULATORS_POFCON_THRESHOLD_V28, ///< Set threshold to 2.8 V. +#endif } nrf_regulators_pof_thr_t; #endif @@ -346,6 +421,34 @@ NRF_STATIC_INLINE uint32_t nrf_regulators_elv_mode_allow_get(NRF_REGULATORS_Type NRF_STATIC_INLINE bool nrf_regulators_inductor_check(NRF_REGULATORS_Type const * p_reg); #endif +#if NRF_REGULATORS_HAS_HIBERNATOR +/** + * @brief Function for putting the CPU in hibernation mode. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + */ +NRF_STATIC_INLINE void nrf_regulators_system_hibernate(NRF_REGULATORS_Type * p_reg); + +/** + * @brief Function for enabling or disabling the GPIO retention release on wake up + * from hibernation mode. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] enable True if GPIO retention release is to be enabled, false otherwise. + */ +NRF_STATIC_INLINE void nrf_regulators_gpio_retention_release_set(NRF_REGULATORS_Type * p_reg, + bool enable); +/** + * @brief Function for checking the GPIO retention status. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval true GPIO retention is active. + * @retval false GPIO retention is not active. + */ +NRF_STATIC_INLINE bool nrf_regulators_gpio_retention_check(NRF_REGULATORS_Type const * p_reg); +#endif + #ifndef NRF_DECLARE_ONLY #if NRF_REGULATORS_HAS_VREG_ANY @@ -539,6 +642,31 @@ NRF_STATIC_INLINE bool nrf_regulators_inductor_check(NRF_REGULATORS_Type const * } #endif +#if NRF_REGULATORS_HAS_HIBERNATOR +NRF_STATIC_INLINE void nrf_regulators_system_hibernate(NRF_REGULATORS_Type * p_reg) +{ + p_reg->HIBERNATOR.SYSTEMHIBERNATE = + REGULATORS_HIBERNATOR_SYSTEMHIBERNATE_SYSTEMHIBERNATE_Enter; +} + +NRF_STATIC_INLINE void nrf_regulators_gpio_retention_release_set(NRF_REGULATORS_Type * p_reg, + bool enable) +{ + p_reg->HIBERNATOR.GPIORETENTIONRELEASE = (enable + ? REGULATORS_HIBERNATOR_GPIORETENTIONRELEASE_GPIORETENTIONRELEASE_Release + : REGULATORS_HIBERNATOR_GPIORETENTIONRELEASE_GPIORETENTIONRELEASE_NoRelease) + << REGULATORS_HIBERNATOR_GPIORETENTIONRELEASE_GPIORETENTIONRELEASE_Pos; +} + +NRF_STATIC_INLINE bool nrf_regulators_gpio_retention_check(NRF_REGULATORS_Type const * p_reg) +{ + return (p_reg->HIBERNATOR.GPIORETENTIONSTATUS + & REGULATORS_HIBERNATOR_GPIORETENTIONSTATUS_GPIORETENTIONSTATUS_Msk) + >> REGULATORS_HIBERNATOR_GPIORETENTIONSTATUS_GPIORETENTIONSTATUS_Pos + == REGULATORS_HIBERNATOR_GPIORETENTIONSTATUS_GPIORETENTIONSTATUS_Active; +} +#endif + #endif // NRF_DECLARE_ONLY /** @} */ diff --git a/nrfx/hal/nrf_saadc.h b/nrfx/hal/nrf_saadc.h index 5c2f5881..1037b8ff 100644 --- a/nrfx/hal/nrf_saadc.h +++ b/nrfx/hal/nrf_saadc.h @@ -448,6 +448,7 @@ typedef enum NRF_SAADC_EVENT_CH2_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITL), ///< Last result is equal or below CH[2].LIMIT.LOW. NRF_SAADC_EVENT_CH3_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITH), ///< Last result is equal or above CH[3].LIMIT.HIGH. NRF_SAADC_EVENT_CH3_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITL), ///< Last result is equal or below CH[3].LIMIT.LOW. +#if (SAADC_CH_NUM > 4) || defined(__NRFX_DOXYGEN__) NRF_SAADC_EVENT_CH4_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITH), ///< Last result is equal or above CH[4].LIMIT.HIGH. NRF_SAADC_EVENT_CH4_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITL), ///< Last result is equal or below CH[4].LIMIT.LOW. NRF_SAADC_EVENT_CH5_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITH), ///< Last result is equal or above CH[5].LIMIT.HIGH. @@ -456,6 +457,7 @@ typedef enum NRF_SAADC_EVENT_CH6_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITL), ///< Last result is equal or below CH[6].LIMIT.LOW. NRF_SAADC_EVENT_CH7_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITH), ///< Last result is equal or above CH[7].LIMIT.HIGH. NRF_SAADC_EVENT_CH7_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITL) ///< Last result is equal or below CH[7].LIMIT.LOW. +#endif } nrf_saadc_event_t; /** @brief Analog-to-digital converter interrupt masks. */ @@ -475,6 +477,7 @@ typedef enum NRF_SAADC_INT_CH2LIMITL = SAADC_INTENSET_CH2LIMITL_Msk, ///< Interrupt on EVENTS_CH[2].LIMITL event. NRF_SAADC_INT_CH3LIMITH = SAADC_INTENSET_CH3LIMITH_Msk, ///< Interrupt on EVENTS_CH[3].LIMITH event. NRF_SAADC_INT_CH3LIMITL = SAADC_INTENSET_CH3LIMITL_Msk, ///< Interrupt on EVENTS_CH[3].LIMITL event. +#if (SAADC_CH_NUM > 4) || defined(__NRFX_DOXYGEN__) NRF_SAADC_INT_CH4LIMITH = SAADC_INTENSET_CH4LIMITH_Msk, ///< Interrupt on EVENTS_CH[4].LIMITH event. NRF_SAADC_INT_CH4LIMITL = SAADC_INTENSET_CH4LIMITL_Msk, ///< Interrupt on EVENTS_CH[4].LIMITL event. NRF_SAADC_INT_CH5LIMITH = SAADC_INTENSET_CH5LIMITH_Msk, ///< Interrupt on EVENTS_CH[5].LIMITH event. @@ -483,6 +486,7 @@ typedef enum NRF_SAADC_INT_CH6LIMITL = SAADC_INTENSET_CH6LIMITL_Msk, ///< Interrupt on EVENTS_CH[6].LIMITL event. NRF_SAADC_INT_CH7LIMITH = SAADC_INTENSET_CH7LIMITH_Msk, ///< Interrupt on EVENTS_CH[7].LIMITH event. NRF_SAADC_INT_CH7LIMITL = SAADC_INTENSET_CH7LIMITL_Msk, ///< Interrupt on EVENTS_CH[7].LIMITL event. +#endif NRF_SAADC_INT_ALL = 0x7FFFFFFFUL ///< Mask of all interrupts. } nrf_saadc_int_mask_t; diff --git a/nrfx/mdk/nrf.h b/nrfx/mdk/nrf.h index f2727b60..3b61646a 100644 --- a/nrfx/mdk/nrf.h +++ b/nrfx/mdk/nrf.h @@ -38,7 +38,7 @@ POSSIBILITY OF SUCH DAMAGE. /* MDK version */ #define MDK_MAJOR_VERSION 8 #define MDK_MINOR_VERSION 72 -#define MDK_MICRO_VERSION 2 +#define MDK_MICRO_VERSION 3 /* Define coprocessor domains */ diff --git a/nrfx/mdk/nrf54l_erratas.h b/nrfx/mdk/nrf54l_erratas.h index 57b6ab48..6d772885 100644 --- a/nrfx/mdk/nrf54l_erratas.h +++ b/nrfx/mdk/nrf54l_erratas.h @@ -82,6 +82,33 @@ static bool nrf54l_errata_49(void) __UNUSED; static bool nrf54l_errata_50(void) __UNUSED; static bool nrf54l_errata_55(void) __UNUSED; static bool nrf54l_configuration_56(void) __UNUSED; +static bool nrf54l_errata_57(void) __UNUSED; +static bool nrf54l_errata_60(void) __UNUSED; +static bool nrf54l_errata_61(void) __UNUSED; +static bool nrf54l_errata_63(void) __UNUSED; +static bool nrf54l_errata_66(void) __UNUSED; +static bool nrf54l_errata_68(void) __UNUSED; +static bool nrf54l_errata_69(void) __UNUSED; +static bool nrf54l_errata_70(void) __UNUSED; +static bool nrf54l_errata_71(void) __UNUSED; +static bool nrf54l_errata_72(void) __UNUSED; +static bool nrf54l_errata_73(void) __UNUSED; +static bool nrf54l_errata_74(void) __UNUSED; +static bool nrf54l_errata_78(void) __UNUSED; +static bool nrf54l_errata_79(void) __UNUSED; +static bool nrf54l_errata_81(void) __UNUSED; +static bool nrf54l_errata_83(void) __UNUSED; +static bool nrf54l_errata_85(void) __UNUSED; +static bool nrf54l_errata_86(void) __UNUSED; +static bool nrf54l_errata_87(void) __UNUSED; +static bool nrf54l_errata_88(void) __UNUSED; +static bool nrf54l_errata_89(void) __UNUSED; +static bool nrf54l_errata_90(void) __UNUSED; +static bool nrf54l_errata_91(void) __UNUSED; +static bool nrf54l_errata_92(void) __UNUSED; +static bool nrf54l_errata_93(void) __UNUSED; +static bool nrf54l_errata_94(void) __UNUSED; +static bool nrf54l_errata_95(void) __UNUSED; /* ========= Errata 1 ========= */ #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ @@ -946,7 +973,8 @@ static bool nrf54l_errata_19(void) /* ========= Errata 20 ========= */ #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ - || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) #define NRF54L_ERRATA_20_PRESENT 1 #else #define NRF54L_ERRATA_20_PRESENT 0 @@ -963,7 +991,8 @@ static bool nrf54l_errata_20(void) #else #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ - || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -981,6 +1010,18 @@ static bool nrf54l_errata_20(void) } } #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) if (var1 == 0x2E) { @@ -1534,7 +1575,9 @@ static bool nrf54l_errata_27(void) /* ========= Errata 30 ========= */ #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ - || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ + || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) #define NRF54L_ERRATA_30_PRESENT 1 #else #define NRF54L_ERRATA_30_PRESENT 0 @@ -1551,7 +1594,9 @@ static bool nrf54l_errata_30(void) #else #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ - || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ + || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -1569,6 +1614,30 @@ static bool nrf54l_errata_30(void) } } #endif + #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + if (var1 == 0x27) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) if (var1 == 0x2E) { @@ -1942,7 +2011,8 @@ static bool nrf54l_errata_38(void) /* ========= Errata 39 ========= */ #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ - || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) #define NRF54L_ERRATA_39_PRESENT 1 #else #define NRF54L_ERRATA_39_PRESENT 0 @@ -1959,7 +2029,8 @@ static bool nrf54l_errata_39(void) #else #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ - || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -1977,6 +2048,18 @@ static bool nrf54l_errata_39(void) } } #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) if (var1 == 0x2E) { @@ -2940,7 +3023,8 @@ static bool nrf54l_errata_55(void) /* ========= Errata 56 ========= */ #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ - || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) #define NRF54L_CONFIGURATION_56_PRESENT 1 #else #define NRF54L_CONFIGURATION_56_PRESENT 0 @@ -2957,7 +3041,128 @@ static bool nrf54l_configuration_56(void) #else #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ - || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 57 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_57_PRESENT 1 +#else + #define NRF54L_ERRATA_57_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_57_ENABLE_WORKAROUND + #define NRF54L_ERRATA_57_ENABLE_WORKAROUND NRF54L_ERRATA_57_PRESENT +#endif + +static bool nrf54l_errata_57(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 60 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_60_PRESENT 1 +#else + #define NRF54L_ERRATA_60_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_60_ENABLE_WORKAROUND + #define NRF54L_ERRATA_60_ENABLE_WORKAROUND NRF54L_ERRATA_60_PRESENT +#endif + +static bool nrf54l_errata_60(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -2975,6 +3180,18 @@ static bool nrf54l_configuration_56(void) } } #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) if (var1 == 0x2E) { @@ -3007,4 +3224,1214 @@ static bool nrf54l_configuration_56(void) #endif } +/* ========= Errata 61 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ + || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #define NRF54L_ERRATA_61_PRESENT 1 +#else + #define NRF54L_ERRATA_61_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_61_ENABLE_WORKAROUND + #define NRF54L_ERRATA_61_ENABLE_WORKAROUND NRF54L_ERRATA_61_PRESENT +#endif + +static bool nrf54l_errata_61(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ + || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + if (var1 == 0x27) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 63 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_63_PRESENT 1 +#else + #define NRF54L_ERRATA_63_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_63_ENABLE_WORKAROUND + #define NRF54L_ERRATA_63_ENABLE_WORKAROUND NRF54L_ERRATA_63_PRESENT +#endif + +static bool nrf54l_errata_63(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 66 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_66_PRESENT 1 +#else + #define NRF54L_ERRATA_66_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_66_ENABLE_WORKAROUND + #define NRF54L_ERRATA_66_ENABLE_WORKAROUND NRF54L_ERRATA_66_PRESENT +#endif + +static bool nrf54l_errata_66(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 68 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ + || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #define NRF54L_ERRATA_68_PRESENT 1 +#else + #define NRF54L_ERRATA_68_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_68_ENABLE_WORKAROUND + #define NRF54L_ERRATA_68_ENABLE_WORKAROUND NRF54L_ERRATA_68_PRESENT +#endif + +static bool nrf54l_errata_68(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ + || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + if (var1 == 0x27) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 69 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ + || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #define NRF54L_ERRATA_69_PRESENT 1 +#else + #define NRF54L_ERRATA_69_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_69_ENABLE_WORKAROUND + #define NRF54L_ERRATA_69_ENABLE_WORKAROUND NRF54L_ERRATA_69_PRESENT +#endif + +static bool nrf54l_errata_69(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ + || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + if (var1 == 0x27) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 70 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_70_PRESENT 1 +#else + #define NRF54L_ERRATA_70_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_70_ENABLE_WORKAROUND + #define NRF54L_ERRATA_70_ENABLE_WORKAROUND NRF54L_ERRATA_70_PRESENT +#endif + +static bool nrf54l_errata_70(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 71 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_71_PRESENT 1 +#else + #define NRF54L_ERRATA_71_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_71_ENABLE_WORKAROUND + #define NRF54L_ERRATA_71_ENABLE_WORKAROUND NRF54L_ERRATA_71_PRESENT +#endif + +static bool nrf54l_errata_71(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 72 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ + || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #define NRF54L_ERRATA_72_PRESENT 1 +#else + #define NRF54L_ERRATA_72_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_72_ENABLE_WORKAROUND + #define NRF54L_ERRATA_72_ENABLE_WORKAROUND 0 +#endif + +static bool nrf54l_errata_72(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ + || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + if (var1 == 0x27) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 73 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ + || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #define NRF54L_ERRATA_73_PRESENT 1 +#else + #define NRF54L_ERRATA_73_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_73_ENABLE_WORKAROUND + #define NRF54L_ERRATA_73_ENABLE_WORKAROUND 0 +#endif + +static bool nrf54l_errata_73(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ + || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ + || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + if (var1 == 0x27) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 74 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_74_PRESENT 1 +#else + #define NRF54L_ERRATA_74_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_74_ENABLE_WORKAROUND + #define NRF54L_ERRATA_74_ENABLE_WORKAROUND 0 +#endif + +static bool nrf54l_errata_74(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 78 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_78_PRESENT 1 +#else + #define NRF54L_ERRATA_78_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_78_ENABLE_WORKAROUND + #define NRF54L_ERRATA_78_ENABLE_WORKAROUND NRF54L_ERRATA_78_PRESENT +#endif + +static bool nrf54l_errata_78(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 79 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_79_PRESENT 1 +#else + #define NRF54L_ERRATA_79_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_79_ENABLE_WORKAROUND + #define NRF54L_ERRATA_79_ENABLE_WORKAROUND NRF54L_ERRATA_79_PRESENT +#endif + +static bool nrf54l_errata_79(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 81 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_81_PRESENT 1 +#else + #define NRF54L_ERRATA_81_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_81_ENABLE_WORKAROUND + #define NRF54L_ERRATA_81_ENABLE_WORKAROUND NRF54L_ERRATA_81_PRESENT +#endif + +static bool nrf54l_errata_81(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 83 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_83_PRESENT 1 +#else + #define NRF54L_ERRATA_83_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_83_ENABLE_WORKAROUND + #define NRF54L_ERRATA_83_ENABLE_WORKAROUND NRF54L_ERRATA_83_PRESENT +#endif + +static bool nrf54l_errata_83(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 85 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_85_PRESENT 1 +#else + #define NRF54L_ERRATA_85_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_85_ENABLE_WORKAROUND + #define NRF54L_ERRATA_85_ENABLE_WORKAROUND NRF54L_ERRATA_85_PRESENT +#endif + +static bool nrf54l_errata_85(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 86 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_86_PRESENT 1 +#else + #define NRF54L_ERRATA_86_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_86_ENABLE_WORKAROUND + #define NRF54L_ERRATA_86_ENABLE_WORKAROUND 0 +#endif + +static bool nrf54l_errata_86(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 87 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_87_PRESENT 1 +#else + #define NRF54L_ERRATA_87_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_87_ENABLE_WORKAROUND + #define NRF54L_ERRATA_87_ENABLE_WORKAROUND 0 +#endif + +static bool nrf54l_errata_87(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 88 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_88_PRESENT 1 +#else + #define NRF54L_ERRATA_88_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_88_ENABLE_WORKAROUND + #define NRF54L_ERRATA_88_ENABLE_WORKAROUND 0 +#endif + +static bool nrf54l_errata_88(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 89 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_89_PRESENT 1 +#else + #define NRF54L_ERRATA_89_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_89_ENABLE_WORKAROUND + #define NRF54L_ERRATA_89_ENABLE_WORKAROUND NRF54L_ERRATA_89_PRESENT +#endif + +static bool nrf54l_errata_89(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 90 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_90_PRESENT 1 +#else + #define NRF54L_ERRATA_90_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_90_ENABLE_WORKAROUND + #define NRF54L_ERRATA_90_ENABLE_WORKAROUND 0 +#endif + +static bool nrf54l_errata_90(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 91 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_91_PRESENT 1 +#else + #define NRF54L_ERRATA_91_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_91_ENABLE_WORKAROUND + #define NRF54L_ERRATA_91_ENABLE_WORKAROUND NRF54L_ERRATA_91_PRESENT +#endif + +static bool nrf54l_errata_91(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 92 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_92_PRESENT 1 +#else + #define NRF54L_ERRATA_92_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_92_ENABLE_WORKAROUND + #define NRF54L_ERRATA_92_ENABLE_WORKAROUND NRF54L_ERRATA_92_PRESENT +#endif + +static bool nrf54l_errata_92(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 93 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_93_PRESENT 1 +#else + #define NRF54L_ERRATA_93_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_93_ENABLE_WORKAROUND + #define NRF54L_ERRATA_93_ENABLE_WORKAROUND NRF54L_ERRATA_93_PRESENT +#endif + +static bool nrf54l_errata_93(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 94 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_94_PRESENT 1 +#else + #define NRF54L_ERRATA_94_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_94_ENABLE_WORKAROUND + #define NRF54L_ERRATA_94_ENABLE_WORKAROUND NRF54L_ERRATA_94_PRESENT +#endif + +static bool nrf54l_errata_94(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 95 ========= */ +#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #define NRF54L_ERRATA_95_PRESENT 1 +#else + #define NRF54L_ERRATA_95_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_95_ENABLE_WORKAROUND + #define NRF54L_ERRATA_95_ENABLE_WORKAROUND 0 +#endif + +static bool nrf54l_errata_95(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + #endif /* NRF54L_ERRATAS_H */ diff --git a/nrfx/mdk/nrf54lv10a_enga_application.svd b/nrfx/mdk/nrf54lv10a_enga_application.svd index 248672d7..447cea1d 100644 --- a/nrfx/mdk/nrf54lv10a_enga_application.svd +++ b/nrfx/mdk/nrf54lv10a_enga_application.svd @@ -121,7 +121,7 @@ POSSIBILITY OF SUCH DAMAGE. UUID[%s] Description collection: 128-bit Universally Unique IDentifier (UUID). 0x00C - read-write + read-only 0xFFFFFFFF 0x20 @@ -224,7 +224,7 @@ POSSIBILITY OF SUCH DAMAGE. K192 192 kByte RAM - 0x00000080 + 0x000000C0 Unspecified @@ -614,11 +614,11 @@ POSSIBILITY OF SUCH DAMAGE. Erase Protection Registers UICR_ERASEPROTECT read-writeonce - 0x060 + 0x60 PROTECT0 Description cluster: Erase protection - 0x000 + 0x0 read-writeonce 0xFFFFFFFF 0x20 @@ -640,7 +640,7 @@ POSSIBILITY OF SUCH DAMAGE. PROTECT1 Description cluster: Erase protection - 0x01C + 0x1C read-writeonce 0xFFFFFFFF 0x20 @@ -2095,9 +2095,10 @@ POSSIBILITY OF SUCH DAMAGE. ENABLE - Start/enable the NDRNG. + Start the NDRNG. Self-clearing bit. 0 0 + write-only LFSREN @@ -2263,9 +2264,9 @@ POSSIBILITY OF SUCH DAMAGE. FIFOTHRESHOLD - FIFO level below which the module leaves the idle state to refill the FIFO, expressed in number of 128bit blocks. + FIFO level threshold below which the module leaves the idle state to refill the FIFO. Expressed in number of 128bit blocks. 0 - 31 + 2 @@ -2430,30 +2431,35 @@ POSSIBILITY OF SUCH DAMAGE. NIST repetition test(s) failure. 4 4 + read-only PROPFAIL NIST proportion test(s) failure. 5 5 + read-only ANYHEALTHTESTFAIL Any of the enabled health tests is failing. 6 6 + zeroToClear FULLINT FIFO full status. 7 7 + read-only STARTUPFAIL Start-up test(s) failure. 10 10 + zeroToClear REPTESTFAILPERSHARE @@ -2474,6 +2480,7 @@ POSSIBILITY OF SUCH DAMAGE. Conditioning consumes data slower than they are provided to it. 20 20 + zeroToClear @@ -2503,9 +2510,9 @@ POSSIBILITY OF SUCH DAMAGE. DISABLEOSC - Disable oscillator rings 0 to 7. + Disable oscillator rings. 0 - 7 + 31 @@ -2591,13 +2598,13 @@ POSSIBILITY OF SUCH DAMAGE. DLYZEROCUTOFF Auto-correlation test cut-off value for delay of 0 samples. 0 - 15 + 6 DLYONECUTOFF Auto-correlation test cut-off value for delay of +1 sample. 16 - 31 + 22 @@ -2613,13 +2620,13 @@ POSSIBILITY OF SUCH DAMAGE. DLYTWOCUTOFF Auto-correlation test cut-off value for delay of +2 samples. 0 - 15 + 6 DLYTHREECUTOFF Auto-correlation test cut-off value for delay of +3 samples. 16 - 31 + 22 @@ -2635,13 +2642,13 @@ POSSIBILITY OF SUCH DAMAGE. DLYZEROCUTOFF Correlation test cut-off value for delay of 0 samples. 0 - 15 + 6 DLYONECUTOFF Correlation test cut-off value for delay of +/-1 sample. 16 - 31 + 22 @@ -2992,7 +2999,7 @@ POSSIBILITY OF SUCH DAMAGE. TIMER - Number of clock cycles (as the number of core cycles is always even, register bit 0 is tied to zero. + Number of clock cycles (as the number of core cycles is always even, register bit 0 is tied to zero). 1 31 @@ -8483,6 +8490,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event FPUIOC 0 0 + oneToSet read @@ -8510,6 +8518,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event FPUDZC 1 1 + oneToSet read @@ -8537,6 +8546,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event FPUOFC 2 2 + oneToSet read @@ -8564,6 +8574,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event FPUUFC 3 3 + oneToSet read @@ -8591,6 +8602,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event FPUIXC 4 4 + oneToSet read @@ -8618,6 +8630,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event FPUIDC 5 5 + oneToSet read @@ -8655,6 +8668,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event FPUIOC 0 0 + oneToClear read @@ -8682,6 +8696,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event FPUDZC 1 1 + oneToClear read @@ -8709,6 +8724,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event FPUOFC 2 2 + oneToClear read @@ -8736,6 +8752,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event FPUUFC 3 3 + oneToClear read @@ -8763,6 +8780,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event FPUIXC 4 4 + oneToClear read @@ -8790,6 +8808,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event FPUIDC 5 5 + oneToClear read @@ -9434,6 +9453,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PERIPHACCERR 0 0 + oneToSet read @@ -9471,6 +9491,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event PERIPHACCERR 0 0 + oneToClear read @@ -10306,6 +10327,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event MEMACCERR 0 0 + oneToSet read @@ -10343,6 +10365,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event MEMACCERR 0 0 + oneToClear read @@ -14675,6 +14698,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event END 0 0 + oneToSet read @@ -14702,6 +14726,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event RESOLVED 1 1 + oneToSet read @@ -14729,6 +14754,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event NOTRESOLVED 2 2 + oneToSet read @@ -14756,6 +14782,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event ERROR 3 3 + oneToSet read @@ -14793,6 +14820,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event END 0 0 + oneToClear read @@ -14820,6 +14848,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event RESOLVED 1 1 + oneToClear read @@ -14847,6 +14876,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event NOTRESOLVED 2 2 + oneToClear read @@ -14874,6 +14904,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event ERROR 3 3 + oneToClear read @@ -15367,6 +15398,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event END 1 1 + oneToSet read @@ -15394,6 +15426,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event ERROR 2 2 + oneToSet read @@ -15431,6 +15464,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event END 1 1 + oneToClear read @@ -15458,6 +15492,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event ERROR 2 2 + oneToClear read @@ -16164,6 +16199,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event END 0 0 + oneToSet read @@ -16191,6 +16227,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event ERROR 1 1 + oneToSet read @@ -16228,6 +16265,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event END 0 0 + oneToClear read @@ -16255,6 +16293,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event ERROR 1 1 + oneToClear read @@ -16398,6 +16437,71 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + CSAA + Channel sounding access address scoring algorithm + ECB_CSAA + read-write + 0x53C + + REFLECTOR + Selected Channel Sounding Access Address used in the CS SYNC from Reflector to Initiator + 0x000 + read-only + 0x00000000 + 0x20 + + + PN + 0 + 31 + + + + + INITIATOR + Selected Channel Sounding Access Address used in the CS SYNC from Initiator to Reflector + 0x004 + read-only + 0x00000000 + 0x20 + + + PN + 0 + 31 + + + + + MODE + Operation modes + 0x008 + read-write + 0x00000000 + 0x20 + + + BITREVERSE + Reverse the endianness on bit level for the ECB output, INITIATOR, and REFLECTOR registers + 0 + 0 + + + Default + Default endianness + 0x0 + + + Reversed + Reversed endianness + 0x1 + + + + + + @@ -16694,6 +16798,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[16] 16 16 + oneToSet read @@ -16721,6 +16826,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[17] 17 17 + oneToSet read @@ -16748,6 +16854,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[18] 18 18 + oneToSet read @@ -16775,6 +16882,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[19] 19 19 + oneToSet read @@ -16802,6 +16910,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[20] 20 20 + oneToSet read @@ -16829,6 +16938,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[21] 21 21 + oneToSet read @@ -16856,6 +16966,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[22] 22 22 + oneToSet read @@ -16893,6 +17004,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[16] 16 16 + oneToClear read @@ -16920,6 +17032,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[17] 17 17 + oneToClear read @@ -16947,6 +17060,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[18] 18 18 + oneToClear read @@ -16974,6 +17088,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[19] 19 19 + oneToClear read @@ -17001,6 +17116,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[20] 20 20 + oneToClear read @@ -17028,6 +17144,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[21] 21 21 + oneToClear read @@ -17055,6 +17172,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[22] 22 22 + oneToClear read @@ -18827,6 +18945,29 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + TASKS_CLRWRITEBUF + Clear internal write-buffer + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_CLRWRITEBUF + Clear internal write-buffer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + TASKS_COMMITWRITEBUF Commits the data stored in internal write-buffer to RRAM @@ -18883,6 +19024,39 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + SUBSCRIBE_CLRWRITEBUF + Subscribe configuration for task CLRWRITEBUF + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLRWRITEBUF will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + SUBSCRIBE_COMMITWRITEBUF Subscribe configuration for task COMMITWRITEBUF @@ -19156,6 +19330,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event WOKENUP 0 0 + oneToSet read @@ -19183,6 +19358,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event READY 1 1 + oneToSet read @@ -19210,6 +19386,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event READYNEXT 2 2 + oneToSet read @@ -19237,6 +19414,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event ACCESSERROR 3 3 + oneToSet read @@ -19274,6 +19452,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event WOKENUP 0 0 + oneToClear read @@ -19301,6 +19480,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event READY 1 1 + oneToClear read @@ -19328,6 +19508,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event READYNEXT 2 2 + oneToClear read @@ -19355,6 +19536,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event ACCESSERROR 3 3 + oneToClear read @@ -19756,7 +19938,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x540 ERASEALL - Register for erasing whole RRAM main block, that includes the SICR and the UICR + Erase RRAM, including UICR All information in SICR, including keys, are also erased 0x000 read-write 0x00000000 @@ -19764,7 +19946,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. ERASE - Erase whole RRAM main block + Erase RRAM 0 0 @@ -20082,6 +20264,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event RXREADY 0 0 + oneToSet read @@ -20109,6 +20292,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TXDONE 1 1 + oneToSet read @@ -20146,6 +20330,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event RXREADY 0 0 + oneToClear read @@ -20173,6 +20358,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TXDONE 1 1 + oneToClear read @@ -21420,6 +21606,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[0] 16 16 + oneToSet read @@ -21447,6 +21634,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[1] 17 17 + oneToSet read @@ -21474,6 +21662,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[2] 18 18 + oneToSet read @@ -21501,6 +21690,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[3] 19 19 + oneToSet read @@ -21528,6 +21718,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[4] 20 20 + oneToSet read @@ -21555,6 +21746,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[5] 21 21 + oneToSet read @@ -21582,6 +21774,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[6] 22 22 + oneToSet read @@ -21609,6 +21802,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[7] 23 23 + oneToSet read @@ -21646,6 +21840,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[0] 16 16 + oneToClear read @@ -21673,6 +21868,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[1] 17 17 + oneToClear read @@ -21700,6 +21896,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[2] 18 18 + oneToClear read @@ -21727,6 +21924,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[3] 19 19 + oneToClear read @@ -21754,6 +21952,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[4] 20 20 + oneToClear read @@ -21781,6 +21980,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[5] 21 21 + oneToClear read @@ -21808,6 +22008,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[6] 22 22 + oneToClear read @@ -21835,6 +22036,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[7] 23 23 + oneToClear read @@ -22462,6 +22664,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[0] 0 0 + oneToSet read @@ -22489,6 +22692,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[1] 1 1 + oneToSet read @@ -22516,6 +22720,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[2] 2 2 + oneToSet read @@ -22543,6 +22748,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[3] 3 3 + oneToSet read @@ -22570,6 +22776,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[4] 4 4 + oneToSet read @@ -22597,6 +22804,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[5] 5 5 + oneToSet read @@ -22624,6 +22832,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[6] 6 6 + oneToSet read @@ -22651,6 +22860,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[7] 7 7 + oneToSet read @@ -22678,6 +22888,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[8] 8 8 + oneToSet read @@ -22705,6 +22916,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[9] 9 9 + oneToSet read @@ -22732,6 +22944,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[10] 10 10 + oneToSet read @@ -22759,6 +22972,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[11] 11 11 + oneToSet read @@ -22786,6 +23000,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[12] 12 12 + oneToSet read @@ -22813,6 +23028,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[13] 13 13 + oneToSet read @@ -22840,6 +23056,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[14] 14 14 + oneToSet read @@ -22867,6 +23084,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TRIGGERED[15] 15 15 + oneToSet read @@ -22904,6 +23122,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[0] 0 0 + oneToClear read @@ -22931,6 +23150,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[1] 1 1 + oneToClear read @@ -22958,6 +23178,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[2] 2 2 + oneToClear read @@ -22985,6 +23206,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[3] 3 3 + oneToClear read @@ -23012,6 +23234,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[4] 4 4 + oneToClear read @@ -23039,6 +23262,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[5] 5 5 + oneToClear read @@ -23066,6 +23290,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[6] 6 6 + oneToClear read @@ -23093,6 +23318,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[7] 7 7 + oneToClear read @@ -23120,6 +23346,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[8] 8 8 + oneToClear read @@ -23147,6 +23374,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[9] 9 9 + oneToClear read @@ -23174,6 +23402,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[10] 10 10 + oneToClear read @@ -23201,6 +23430,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[11] 11 11 + oneToClear read @@ -23228,6 +23458,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[12] 12 12 + oneToClear read @@ -23255,6 +23486,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[13] 13 13 + oneToClear read @@ -23282,6 +23514,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[14] 14 14 + oneToClear read @@ -23309,6 +23542,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TRIGGERED[15] 15 15 + oneToClear read @@ -23526,6 +23760,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CRYPTOMASTER 0 0 + oneToSet read @@ -23553,6 +23788,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event RNG 1 1 + oneToSet read @@ -23580,6 +23816,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PKEIKG 2 2 + oneToSet read @@ -23617,6 +23854,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CRYPTOMASTER 0 0 + oneToClear read @@ -23644,6 +23882,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event RNG 1 1 + oneToClear read @@ -23671,6 +23910,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event PKEIKG 2 2 + oneToClear read @@ -24328,6 +24568,98 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + TASKS_AUXDATADMASTART + Start DMA transaction of acquisition + 0x038 + write-only + 0x00000000 + 0x20 + + + TASKS_AUXDATADMASTART + Start DMA transaction of acquisition + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_AUXDATADMASTOP + Stop ongoing DMA transaction of acquisition + 0x03C + write-only + 0x00000000 + 0x20 + + + TASKS_AUXDATADMASTOP + Stop ongoing DMA transaction of acquisition + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PLLEN + Enable RADIO in PLL mode (standby for either TX or RX) + 0x06C + write-only + 0x00000000 + 0x20 + + + TASKS_PLLEN + Enable RADIO in PLL mode (standby for either TX or RX) + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CSTONESSTART + Start tone processing for channel sounding + 0x0A0 + write-only + 0x00000000 + 0x20 + + + TASKS_CSTONESSTART + Start tone processing for channel sounding + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + TASKS_SOFTRESET Reset all public registers, but with these exceptions: DMA registers and EVENT/INTEN/SUBSCRIBE/PUBLISH registers. Only to be used in DISABLED state. @@ -24748,16 +25080,148 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - SUBSCRIBE_SOFTRESET - Subscribe configuration for task SOFTRESET - 0x1A4 + SUBSCRIBE_AUXDATADMASTART + Subscribe configuration for task AUXDATADMASTART + 0x138 read-write 0x00000000 0x20 CHIDX - DPPI channel that task SOFTRESET will subscribe to + DPPI channel that task AUXDATADMASTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_AUXDATADMASTOP + Subscribe configuration for task AUXDATADMASTOP + 0x13C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task AUXDATADMASTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PLLEN + Subscribe configuration for task PLLEN + 0x16C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task PLLEN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CSTONESSTART + Subscribe configuration for task CSTONESSTART + 0x1A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CSTONESSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SOFTRESET + Subscribe configuration for task SOFTRESET + 0x1A4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SOFTRESET will subscribe to 0 7 @@ -25425,32 +25889,55 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - PUBLISH_READY - Publish configuration for event READY - 0x300 + EVENTS_PLLREADY + PLL has settled and RADIO is ready to be enabled in either TX or RX mode + 0x2B0 read-write 0x00000000 0x20 - CHIDX - DPPI channel that event READY will publish to + EVENTS_PLLREADY + PLL has settled and RADIO is ready to be enabled in either TX or RX mode 0 - 7 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + EVENTS_RXADDRESS + Address received + 0x2BC + read-write + 0x00000000 + 0x20 + - EN - 31 - 31 + EVENTS_RXADDRESS + Address received + 0 + 0 - Disabled - Disable publishing + NotGenerated + Event not generated 0x0 - Enabled - Enable publishing + Generated + Event generated 0x1 @@ -25458,32 +25945,55 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - PUBLISH_TXREADY - Publish configuration for event TXREADY - 0x304 + EVENTS_AUXDATADMAEND + AUXDATA DMA end + 0x2C0 read-write 0x00000000 0x20 - CHIDX - DPPI channel that event TXREADY will publish to + EVENTS_AUXDATADMAEND + AUXDATA DMA end 0 - 7 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + EVENTS_CSTONESEND + The channel sounding tone processing is complete + 0x2C8 + read-write + 0x00000000 + 0x20 + - EN - 31 - 31 + EVENTS_CSTONESEND + The channel sounding tone processing is complete + 0 + 0 - Disabled - Disable publishing + NotGenerated + Event not generated 0x0 - Enabled - Enable publishing + Generated + Event generated 0x1 @@ -25491,16 +26001,16 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - PUBLISH_RXREADY - Publish configuration for event RXREADY - 0x308 + PUBLISH_READY + Publish configuration for event READY + 0x300 read-write 0x00000000 0x20 CHIDX - DPPI channel that event RXREADY will publish to + DPPI channel that event READY will publish to 0 7 @@ -25524,16 +26034,16 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - PUBLISH_ADDRESS - Publish configuration for event ADDRESS - 0x30C + PUBLISH_TXREADY + Publish configuration for event TXREADY + 0x304 read-write 0x00000000 0x20 CHIDX - DPPI channel that event ADDRESS will publish to + DPPI channel that event TXREADY will publish to 0 7 @@ -25557,16 +26067,16 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - PUBLISH_FRAMESTART - Publish configuration for event FRAMESTART - 0x310 + PUBLISH_RXREADY + Publish configuration for event RXREADY + 0x308 read-write 0x00000000 0x20 CHIDX - DPPI channel that event FRAMESTART will publish to + DPPI channel that event RXREADY will publish to 0 7 @@ -25590,16 +26100,16 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - PUBLISH_PAYLOAD - Publish configuration for event PAYLOAD - 0x314 + PUBLISH_ADDRESS + Publish configuration for event ADDRESS + 0x30C read-write 0x00000000 0x20 CHIDX - DPPI channel that event PAYLOAD will publish to + DPPI channel that event ADDRESS will publish to 0 7 @@ -25623,16 +26133,16 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - PUBLISH_END - Publish configuration for event END - 0x318 + PUBLISH_FRAMESTART + Publish configuration for event FRAMESTART + 0x310 read-write 0x00000000 0x20 CHIDX - DPPI channel that event END will publish to + DPPI channel that event FRAMESTART will publish to 0 7 @@ -25656,16 +26166,16 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - PUBLISH_PHYEND - Publish configuration for event PHYEND - 0x31C + PUBLISH_PAYLOAD + Publish configuration for event PAYLOAD + 0x314 read-write 0x00000000 0x20 CHIDX - DPPI channel that event PHYEND will publish to + DPPI channel that event PAYLOAD will publish to 0 7 @@ -25689,16 +26199,82 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - PUBLISH_DISABLED - Publish configuration for event DISABLED - 0x320 + PUBLISH_END + Publish configuration for event END + 0x318 read-write 0x00000000 0x20 CHIDX - DPPI channel that event DISABLED will publish to + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_PHYEND + Publish configuration for event PHYEND + 0x31C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event PHYEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DISABLED + Publish configuration for event DISABLED + 0x320 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DISABLED will publish to 0 7 @@ -26183,6 +26759,138 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + PUBLISH_PLLREADY + Publish configuration for event PLLREADY + 0x3B0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event PLLREADY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXADDRESS + Publish configuration for event RXADDRESS + 0x3BC + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXADDRESS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_AUXDATADMAEND + Publish configuration for event AUXDATADMAEND + 0x3C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event AUXDATADMAEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CSTONESEND + Publish configuration for event CSTONESEND + 0x3C8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CSTONESEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + SHORTS Shortcuts between local events and tasks @@ -26512,6 +27220,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event READY 0 0 + oneToSet read @@ -26539,6 +27248,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TXREADY 1 1 + oneToSet read @@ -26566,6 +27276,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event RXREADY 2 2 + oneToSet read @@ -26593,6 +27304,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event ADDRESS 3 3 + oneToSet read @@ -26620,6 +27332,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event FRAMESTART 4 4 + oneToSet read @@ -26647,6 +27360,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PAYLOAD 5 5 + oneToSet read @@ -26674,6 +27388,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event END 6 6 + oneToSet read @@ -26701,6 +27416,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PHYEND 7 7 + oneToSet read @@ -26728,6 +27444,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DISABLED 8 8 + oneToSet read @@ -26755,6 +27472,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DEVMATCH 9 9 + oneToSet read @@ -26782,6 +27500,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DEVMISS 10 10 + oneToSet read @@ -26809,6 +27528,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CRCOK 11 11 + oneToSet read @@ -26836,6 +27556,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CRCERROR 12 12 + oneToSet read @@ -26863,6 +27584,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event BCMATCH 14 14 + oneToSet read @@ -26890,6 +27612,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event EDEND 15 15 + oneToSet read @@ -26917,6 +27640,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event EDSTOPPED 16 16 + oneToSet read @@ -26944,6 +27668,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CCAIDLE 17 17 + oneToSet read @@ -26971,6 +27696,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CCABUSY 18 18 + oneToSet read @@ -26998,6 +27724,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CCASTOPPED 19 19 + oneToSet read @@ -27025,6 +27752,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event RATEBOOST 20 20 + oneToSet read @@ -27052,6 +27780,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event MHRMATCH 21 21 + oneToSet read @@ -27079,6 +27808,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event SYNC 22 22 + oneToSet read @@ -27106,6 +27836,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CTEPRESENT 23 23 + oneToSet read @@ -27131,18 +27862,19 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - INTENCLR00 - Disable interrupt - 0x490 + INTENSET01 + Enable interrupt + 0x48C read-write 0x00000000 0x20 - READY - Write '1' to disable interrupt for event READY - 0 - 0 + PLLREADY + Write '1' to enable interrupt for event PLLREADY + 12 + 12 + oneToSet read @@ -27159,17 +27891,18 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Clear - Disable + Set + Enable 0x1 - TXREADY - Write '1' to disable interrupt for event TXREADY - 1 - 1 + RXADDRESS + Write '1' to enable interrupt for event RXADDRESS + 15 + 15 + oneToSet read @@ -27186,17 +27919,18 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Clear - Disable + Set + Enable 0x1 - RXREADY - Write '1' to disable interrupt for event RXREADY - 2 - 2 + AUXDATADMAEND + Write '1' to enable interrupt for event AUXDATADMAEND + 16 + 16 + oneToSet read @@ -27213,17 +27947,18 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Clear - Disable + Set + Enable 0x1 - ADDRESS - Write '1' to disable interrupt for event ADDRESS - 3 - 3 + CSTONESEND + Write '1' to enable interrupt for event CSTONESEND + 18 + 18 + oneToSet read @@ -27240,17 +27975,28 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Clear - Disable + Set + Enable 0x1 + + + + INTENCLR00 + Disable interrupt + 0x490 + read-write + 0x00000000 + 0x20 + - FRAMESTART - Write '1' to disable interrupt for event FRAMESTART - 4 - 4 + READY + Write '1' to disable interrupt for event READY + 0 + 0 + oneToClear read @@ -27274,10 +28020,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - PAYLOAD - Write '1' to disable interrupt for event PAYLOAD - 5 - 5 + TXREADY + Write '1' to disable interrupt for event TXREADY + 1 + 1 + oneToClear read @@ -27301,10 +28048,123 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - END - Write '1' to disable interrupt for event END - 6 - 6 + RXREADY + Write '1' to disable interrupt for event RXREADY + 2 + 2 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 3 + 3 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 4 + 4 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 5 + 5 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + oneToClear read @@ -27332,6 +28192,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event PHYEND 7 7 + oneToClear read @@ -27359,6 +28220,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DISABLED 8 8 + oneToClear read @@ -27386,6 +28248,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DEVMATCH 9 9 + oneToClear read @@ -27413,6 +28276,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DEVMISS 10 10 + oneToClear read @@ -27440,6 +28304,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CRCOK 11 11 + oneToClear read @@ -27467,6 +28332,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CRCERROR 12 12 + oneToClear read @@ -27494,6 +28360,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event BCMATCH 14 14 + oneToClear read @@ -27521,6 +28388,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event EDEND 15 15 + oneToClear read @@ -27548,6 +28416,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event EDSTOPPED 16 16 + oneToClear read @@ -27575,6 +28444,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CCAIDLE 17 17 + oneToClear read @@ -27602,6 +28472,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CCABUSY 18 18 + oneToClear read @@ -27629,6 +28500,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CCASTOPPED 19 19 + oneToClear read @@ -27656,6 +28528,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event RATEBOOST 20 20 + oneToClear read @@ -27683,6 +28556,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event MHRMATCH 21 21 + oneToClear read @@ -27710,6 +28584,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event SYNC 22 22 + oneToClear read @@ -27737,6 +28612,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CTEPRESENT 23 23 + oneToClear read @@ -27762,18 +28638,19 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - INTENSET10 - Enable interrupt - 0x4A8 + INTENCLR01 + Disable interrupt + 0x494 read-write 0x00000000 0x20 - READY - Write '1' to enable interrupt for event READY - 0 - 0 + PLLREADY + Write '1' to disable interrupt for event PLLREADY + 12 + 12 + oneToClear read @@ -27790,17 +28667,18 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Set - Enable + Clear + Disable 0x1 - TXREADY - Write '1' to enable interrupt for event TXREADY - 1 - 1 + RXADDRESS + Write '1' to disable interrupt for event RXADDRESS + 15 + 15 + oneToClear read @@ -27817,17 +28695,18 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Set - Enable + Clear + Disable 0x1 - RXREADY - Write '1' to enable interrupt for event RXREADY - 2 - 2 + AUXDATADMAEND + Write '1' to disable interrupt for event AUXDATADMAEND + 16 + 16 + oneToClear read @@ -27844,17 +28723,56 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Set - Enable + Clear + Disable 0x1 - ADDRESS - Write '1' to enable interrupt for event ADDRESS - 3 - 3 + CSTONESEND + Write '1' to disable interrupt for event CSTONESEND + 18 + 18 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTENSET10 + Enable interrupt + 0x4A8 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + oneToSet read @@ -27878,10 +28796,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - FRAMESTART - Write '1' to enable interrupt for event FRAMESTART - 4 - 4 + TXREADY + Write '1' to enable interrupt for event TXREADY + 1 + 1 + oneToSet read @@ -27905,10 +28824,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - PAYLOAD - Write '1' to enable interrupt for event PAYLOAD - 5 - 5 + RXREADY + Write '1' to enable interrupt for event RXREADY + 2 + 2 + oneToSet read @@ -27932,10 +28852,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - END - Write '1' to enable interrupt for event END - 6 - 6 + ADDRESS + Write '1' to enable interrupt for event ADDRESS + 3 + 3 + oneToSet read @@ -27959,10 +28880,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - PHYEND - Write '1' to enable interrupt for event PHYEND - 7 - 7 + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 4 + 4 + oneToSet read @@ -27986,10 +28908,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - DISABLED - Write '1' to enable interrupt for event DISABLED - 8 - 8 + PAYLOAD + Write '1' to enable interrupt for event PAYLOAD + 5 + 5 + oneToSet read @@ -28013,10 +28936,95 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - DEVMATCH - Write '1' to enable interrupt for event DEVMATCH - 9 - 9 + END + Write '1' to enable interrupt for event END + 6 + 6 + oneToSet + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PHYEND + Write '1' to enable interrupt for event PHYEND + 7 + 7 + oneToSet + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DISABLED + Write '1' to enable interrupt for event DISABLED + 8 + 8 + oneToSet + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DEVMATCH + Write '1' to enable interrupt for event DEVMATCH + 9 + 9 + oneToSet read @@ -28044,6 +29052,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DEVMISS 10 10 + oneToSet read @@ -28071,6 +29080,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CRCOK 11 11 + oneToSet read @@ -28098,6 +29108,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CRCERROR 12 12 + oneToSet read @@ -28125,6 +29136,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event BCMATCH 14 14 + oneToSet read @@ -28152,6 +29164,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event EDEND 15 15 + oneToSet read @@ -28179,6 +29192,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event EDSTOPPED 16 16 + oneToSet read @@ -28206,6 +29220,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CCAIDLE 17 17 + oneToSet read @@ -28233,6 +29248,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CCABUSY 18 18 + oneToSet read @@ -28260,6 +29276,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CCASTOPPED 19 19 + oneToSet read @@ -28287,6 +29304,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event RATEBOOST 20 20 + oneToSet read @@ -28314,6 +29332,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event MHRMATCH 21 21 + oneToSet read @@ -28341,6 +29360,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event SYNC 22 22 + oneToSet read @@ -28368,6 +29388,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CTEPRESENT 23 23 + oneToSet read @@ -28393,18 +29414,19 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - INTENCLR10 - Disable interrupt - 0x4B0 + INTENSET11 + Enable interrupt + 0x4AC read-write 0x00000000 0x20 - READY - Write '1' to disable interrupt for event READY - 0 - 0 + PLLREADY + Write '1' to enable interrupt for event PLLREADY + 12 + 12 + oneToSet read @@ -28421,17 +29443,18 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Clear - Disable + Set + Enable 0x1 - TXREADY - Write '1' to disable interrupt for event TXREADY - 1 - 1 + RXADDRESS + Write '1' to enable interrupt for event RXADDRESS + 15 + 15 + oneToSet read @@ -28448,17 +29471,18 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Clear - Disable + Set + Enable 0x1 - RXREADY - Write '1' to disable interrupt for event RXREADY - 2 - 2 + AUXDATADMAEND + Write '1' to enable interrupt for event AUXDATADMAEND + 16 + 16 + oneToSet read @@ -28475,17 +29499,56 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Clear - Disable + Set + Enable 0x1 - ADDRESS - Write '1' to disable interrupt for event ADDRESS - 3 - 3 + CSTONESEND + Write '1' to enable interrupt for event CSTONESEND + 18 + 18 + oneToSet + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR10 + Disable interrupt + 0x4B0 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + oneToClear read @@ -28509,10 +29572,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - FRAMESTART - Write '1' to disable interrupt for event FRAMESTART - 4 - 4 + TXREADY + Write '1' to disable interrupt for event TXREADY + 1 + 1 + oneToClear read @@ -28536,10 +29600,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - PAYLOAD - Write '1' to disable interrupt for event PAYLOAD - 5 - 5 + RXREADY + Write '1' to disable interrupt for event RXREADY + 2 + 2 + oneToClear read @@ -28563,10 +29628,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - END - Write '1' to disable interrupt for event END - 6 - 6 + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 3 + 3 + oneToClear read @@ -28590,10 +29656,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - PHYEND - Write '1' to disable interrupt for event PHYEND - 7 - 7 + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 4 + 4 + oneToClear read @@ -28617,10 +29684,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - DISABLED - Write '1' to disable interrupt for event DISABLED - 8 - 8 + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 5 + 5 + oneToClear read @@ -28644,10 +29712,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - DEVMATCH - Write '1' to disable interrupt for event DEVMATCH - 9 - 9 + END + Write '1' to disable interrupt for event END + 6 + 6 + oneToClear read @@ -28671,10 +29740,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - DEVMISS - Write '1' to disable interrupt for event DEVMISS - 10 - 10 + PHYEND + Write '1' to disable interrupt for event PHYEND + 7 + 7 + oneToClear read @@ -28698,10 +29768,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - CRCOK - Write '1' to disable interrupt for event CRCOK - 11 - 11 + DISABLED + Write '1' to disable interrupt for event DISABLED + 8 + 8 + oneToClear read @@ -28725,10 +29796,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - CRCERROR - Write '1' to disable interrupt for event CRCERROR - 12 - 12 + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 9 + 9 + oneToClear read @@ -28752,10 +29824,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - BCMATCH - Write '1' to disable interrupt for event BCMATCH - 14 - 14 + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 10 + 10 + oneToClear read @@ -28779,10 +29852,95 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - EDEND - Write '1' to disable interrupt for event EDEND - 15 - 15 + CRCOK + Write '1' to disable interrupt for event CRCOK + 11 + 11 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 12 + 12 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + BCMATCH + Write '1' to disable interrupt for event BCMATCH + 14 + 14 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + EDEND + Write '1' to disable interrupt for event EDEND + 15 + 15 + oneToClear read @@ -28810,6 +29968,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event EDSTOPPED 16 16 + oneToClear read @@ -28837,6 +29996,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CCAIDLE 17 17 + oneToClear read @@ -28864,6 +30024,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CCABUSY 18 18 + oneToClear read @@ -28891,6 +30052,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CCASTOPPED 19 19 + oneToClear read @@ -28918,6 +30080,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event RATEBOOST 20 20 + oneToClear read @@ -28945,6 +30108,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event MHRMATCH 21 21 + oneToClear read @@ -28972,6 +30136,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event SYNC 22 22 + oneToClear read @@ -28999,6 +30164,129 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CTEPRESENT 23 23 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTENCLR11 + Disable interrupt + 0x4B4 + read-write + 0x00000000 + 0x20 + + + PLLREADY + Write '1' to disable interrupt for event PLLREADY + 12 + 12 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXADDRESS + Write '1' to disable interrupt for event RXADDRESS + 15 + 15 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + AUXDATADMAEND + Write '1' to disable interrupt for event AUXDATADMAEND + 16 + 16 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CSTONESEND + Write '1' to disable interrupt for event CSTONESEND + 18 + 18 + oneToClear read @@ -29086,6 +30374,40 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + PHYENDTXDELAY + Configurable delay of PHYEND event for TX + 0x518 + read-write + 0x00000421 + 0x20 + + + RATE4M + For modes with 4 Mbps on-air bit rate, unit is 2 bit periods (Nrf_4Mbit0_5 and Nrf_4Mbit0_25 modes) + 0 + 2 + + + RATE2M + For modes with 2 Mbps on-air bit rate, unit is 1 bit period (Nrf_2Mbit, Ble_2Mbit, and Ieee802154_250Kbit modes) + 4 + 6 + + + RATE1M + For modes with 1 Mbps on-air bit rate, unit is 1/2 bit period (Nrf_1Mbit, Ble_1Mbit, Ble_LR125Kbit, and Ble_LR500Kbit modes) + 8 + 10 + + + RATE250K + For modes with 250 kbps on-air bit rate, unit is 1/8 bit period (Nrf_250Kbit mode) + 12 + 14 + + + STATE Current radio state @@ -29277,6 +30599,141 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + AUXDATA + Unspecified + RADIO_AUXDATA + read-write + 0x548 + + 0x2 + 0x4 + CNF[%s] + Description collection: AUXDATA configuration + 0x000 + read-write + 0x00000000 + 0x20 + + + ACQMODE + Acquisition mode (data from RADIO written to memory) + 0 + 4 + + + Rtt + Baseband Channel Sounding RTT Data + 0x07 + + + + + DIR + Data acquisition or injection + 31 + 31 + + + Acq + Peripheral to memory + 0x0 + + + Inj + Memory to peripheral + 0x1 + + + + + + + + 2 + 0x010 + AUXDATADMA[%s] + Unspecified + RADIO_AUXDATADMA + read-write + 0x550 + + ENABLE + Description cluster: Enable or disable data acquisition + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable data acquisition + 0 + 0 + + + Disabled + Data acquisition is disabled + 0x0 + + + Enabled + Data acquisition is enabled + 0x1 + + + + + + + PTR + Description cluster: ACQ DMA pointer + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of 32-bit words to transfer + 0x008 + read-write + 0x00000040 + 0x20 + + + MAXCNT + Maximum number of 32-bit words to transfer + 0 + 13 + + + + + AMOUNT + Description cluster: Number of 32-bit words transferred in the last transaction + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of 32-bit words transferred in the last transaction + 0 + 13 + + + + TIMING Timing @@ -29527,6 +30984,75 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + RXGAIN + Unspecified + RADIO_RXGAIN + read-write + 0x7D0 + + CONFIG + Override configuration of receiver gain control loop + 0x004 + read-write + 0x801230C3 + 0x20 + + + AGCAAFOVERRIDE + Override value for AAF + 17 + 20 + + + AGCMIXOVERRIDE + Override value for MIX + 21 + 21 + + + AGCLNAOVERRIDE + Override value for LNA + 22 + 23 + + + AGCOVERRIDEGAIN + Enable AGC override + 28 + 28 + + + NoOverride + AGC takes control over all gains + 0x0 + + + Override + Manual control of AAF, MIX, and LNA gain settings + 0x1 + + + + + + + + FREQFINETUNE + Fine tuning of the RF frequency + 0x0804 + read-write + 0x00000000 + 0x20 + + + FREQFINETUNE + Twos-complement number for fine-tuning the frequency. The step size is 488.28125 Hz, giving a range from -1 MHz to (one step short of) +1 MHz. + 0 + 12 + + + FECONFIG Config register @@ -29555,6 +31081,50 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + CFO_STAT + Carrier freq. offset estimate + 0xB00 + read-only + 0x00000000 + 0x20 + + + SYNCOK + SYNC ok + 12 + 12 + + + SyncNotOK + Unspecified + 0x0 + + + SyncOk + Unspecified + 0x1 + + + + + + + DBCCORR + Correlator thresholds + 0xB40 + read-write + 0x1FFFFF90 + 0x20 + + + TH + Correlation threshold + 0 + 7 + + + DFEMODE Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) @@ -31284,50 +32854,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - FFOIN - Override value of FFO (Fractional Frequency Offset) if not to be based on the frequency estimate derived from CnAcc (autocorrelation of the scaled input signal) value - 0x00C - read-write - 0x00000000 - 0x20 - - - FFFIN - Units 62.5 ppb. Max range +/-100 ppm plus margin. - 0 - 11 - - - - - FFOSOURCE - Source of FFO - 0x010 - read-write - 0x00000001 - 0x20 - - - FFOSOURCE - Use external or internal FFOSOURCE - 0 - 0 - - - External - Use FFOIN - 0x0 - - - Internal - Calc FFO from CnAcc - 0x1 - - - - - FAEPEER FAEPEER (Frequency Actuation Error) of peer if known. Used during Mode 0 steps. @@ -31458,26 +32984,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - CNACC - Output of the autocorrelation of the accumulated IQ signal - 0x030 - read-only - 0x00000000 - 0x20 - - - CNACCI - 0 - 15 - - - CNACCQ - 16 - 31 - - - FFOEST FFO estimate @@ -31540,37 +33046,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - FINETUNENEXT - Number of full ADPLL finetune steps - 0x03C - read-only - 0x00000000 - 0x20 - - - FINETUNENEXT - Units of 488.28125 Hz - 0 - 12 - - - - - CFOPHASE - Cordic output of CnAcc - 0x040 - read-only - 0x00000000 - 0x20 - - - CFOPHASE - 0 - 15 - - - FREQOFFSET Frequency offset estimate @@ -31586,44 +33061,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - PCT11 - Mean magnitude and mean phase converted to IQ. IQ values limited to [-1024,1023]. - 0x048 - read-only - 0x00000000 - 0x20 - - - PCT11I - Inphase - 0 - 10 - - - PCT11Q - Quadrature - 11 - 21 - - - - - LFAENEXT - Quantization error between ADPLL frequency and the desired value of FFO * RF Frequency. Values limited to [-64,63] with units 7.6294 Hz. - 0x04C - read-only - 0x00000000 - 0x20 - - - LFAENEXT - Inphase - 0 - 6 - - - RTT @@ -33090,6 +34527,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event STARTED 0 0 + oneToSet read @@ -33117,6 +34555,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event STOPPED 1 1 + oneToSet read @@ -33144,6 +34583,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event END 2 2 + oneToSet read @@ -33171,6 +34611,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXEND 19 19 + oneToSet read @@ -33198,6 +34639,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXREADY 20 20 + oneToSet read @@ -33225,6 +34667,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXBUSERROR 21 21 + oneToSet read @@ -33252,6 +34695,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[0] 22 22 + oneToSet read @@ -33279,6 +34723,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[1] 23 23 + oneToSet read @@ -33306,6 +34751,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[2] 24 24 + oneToSet read @@ -33333,6 +34779,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[3] 25 25 + oneToSet read @@ -33360,6 +34807,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMATXEND 26 26 + oneToSet read @@ -33387,6 +34835,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMATXREADY 27 27 + oneToSet read @@ -33414,6 +34863,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMATXBUSERROR 28 28 + oneToSet read @@ -33451,6 +34901,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event STARTED 0 0 + oneToClear read @@ -33478,6 +34929,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event STOPPED 1 1 + oneToClear read @@ -33505,6 +34957,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event END 2 2 + oneToClear read @@ -33532,6 +34985,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXEND 19 19 + oneToClear read @@ -33559,6 +35013,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXREADY 20 20 + oneToClear read @@ -33586,6 +35041,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXBUSERROR 21 21 + oneToClear read @@ -33613,6 +35069,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[0] 22 22 + oneToClear read @@ -33640,6 +35097,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[1] 23 23 + oneToClear read @@ -33667,6 +35125,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[2] 24 24 + oneToClear read @@ -33694,6 +35153,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[3] 25 25 + oneToClear read @@ -33721,6 +35181,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMATXEND 26 26 + oneToClear read @@ -33748,6 +35209,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMATXREADY 27 27 + oneToClear read @@ -33775,6 +35237,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMATXBUSERROR 28 28 + oneToClear read @@ -35711,6 +37174,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event END 1 1 + oneToSet read @@ -35738,6 +37202,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event ACQUIRED 6 6 + oneToSet read @@ -35765,6 +37230,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXEND 19 19 + oneToSet read @@ -35792,6 +37258,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXREADY 20 20 + oneToSet read @@ -35819,6 +37286,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXBUSERROR 21 21 + oneToSet read @@ -35846,6 +37314,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[0] 22 22 + oneToSet read @@ -35873,6 +37342,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[1] 23 23 + oneToSet read @@ -35900,6 +37370,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[2] 24 24 + oneToSet read @@ -35927,6 +37398,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[3] 25 25 + oneToSet read @@ -35954,6 +37426,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMATXEND 26 26 + oneToSet read @@ -35981,6 +37454,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMATXREADY 27 27 + oneToSet read @@ -36008,6 +37482,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMATXBUSERROR 28 28 + oneToSet read @@ -36045,6 +37520,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event END 1 1 + oneToClear read @@ -36072,6 +37548,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event ACQUIRED 6 6 + oneToClear read @@ -36099,6 +37576,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXEND 19 19 + oneToClear read @@ -36126,6 +37604,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXREADY 20 20 + oneToClear read @@ -36153,6 +37632,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXBUSERROR 21 21 + oneToClear read @@ -36180,6 +37660,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[0] 22 22 + oneToClear read @@ -36207,6 +37688,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[1] 23 23 + oneToClear read @@ -36234,6 +37716,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[2] 24 24 + oneToClear read @@ -36261,6 +37744,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[3] 25 25 + oneToClear read @@ -36288,6 +37772,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMATXEND 26 26 + oneToClear read @@ -36315,6 +37800,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMATXREADY 27 27 + oneToClear read @@ -36342,6 +37828,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMATXBUSERROR 28 28 + oneToClear read @@ -37869,7 +39356,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x000 END - Generated after all MAXCNT bytes have been transferred + Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed. 0x000 read-write 0x00000000 @@ -37877,7 +39364,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. END - Generated after all MAXCNT bytes have been transferred + Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed. 0 0 @@ -37990,7 +39477,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x01C END - Generated after all MAXCNT bytes have been transferred + Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed. 0x000 read-write 0x00000000 @@ -37998,7 +39485,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. END - Generated after all MAXCNT bytes have been transferred + Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed. 0 0 @@ -39030,6 +40517,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event STOPPED 1 1 + oneToSet read @@ -39057,6 +40545,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event ERROR 5 5 + oneToSet read @@ -39084,6 +40573,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event SUSPENDED 10 10 + oneToSet read @@ -39111,6 +40601,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event LASTRX 13 13 + oneToSet read @@ -39138,6 +40629,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event LASTTX 14 14 + oneToSet read @@ -39165,6 +40657,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXEND 19 19 + oneToSet read @@ -39192,6 +40685,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXREADY 20 20 + oneToSet read @@ -39219,6 +40713,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXBUSERROR 21 21 + oneToSet read @@ -39246,6 +40741,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[0] 22 22 + oneToSet read @@ -39273,6 +40769,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[1] 23 23 + oneToSet read @@ -39300,6 +40797,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[2] 24 24 + oneToSet read @@ -39327,6 +40825,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[3] 25 25 + oneToSet read @@ -39354,6 +40853,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMATXEND 26 26 + oneToSet read @@ -39381,6 +40881,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMATXREADY 27 27 + oneToSet read @@ -39408,6 +40909,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMATXBUSERROR 28 28 + oneToSet read @@ -39445,6 +40947,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event STOPPED 1 1 + oneToClear read @@ -39472,6 +40975,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event ERROR 5 5 + oneToClear read @@ -39499,6 +41003,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event SUSPENDED 10 10 + oneToClear read @@ -39526,6 +41031,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event LASTRX 13 13 + oneToClear read @@ -39553,6 +41059,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event LASTTX 14 14 + oneToClear read @@ -39580,6 +41087,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXEND 19 19 + oneToClear read @@ -39607,6 +41115,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXREADY 20 20 + oneToClear read @@ -39634,6 +41143,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXBUSERROR 21 21 + oneToClear read @@ -39661,6 +41171,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[0] 22 22 + oneToClear read @@ -39688,6 +41199,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[1] 23 23 + oneToClear read @@ -39715,6 +41227,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[2] 24 24 + oneToClear read @@ -39742,6 +41255,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[3] 25 25 + oneToClear read @@ -39769,6 +41283,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMATXEND 26 26 + oneToClear read @@ -39796,6 +41311,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMATXREADY 27 27 + oneToClear read @@ -39823,6 +41339,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMATXBUSERROR 28 28 + oneToClear read @@ -39969,6 +41486,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.400 kbps 0x06400000 + + K1000 + 1000 kbps + 0x0FF00000 + @@ -40266,7 +41788,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. ONESHOT_0 - Configure match filter 0 as one-shot or sticky + Configure match filter 0 as one-shot or continous 16 16 @@ -40284,7 +41806,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. ONESHOT_1 - Configure match filter 1 as one-shot or sticky + Configure match filter 1 as one-shot or continous 17 17 @@ -40302,7 +41824,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. ONESHOT_2 - Configure match filter 2 as one-shot or sticky + Configure match filter 2 as one-shot or continous 18 18 @@ -40320,7 +41842,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. ONESHOT_3 - Configure match filter 3 as one-shot or sticky + Configure match filter 3 as one-shot or continous 19 19 @@ -40352,7 +41874,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.DATA Data to look for 0 - 31 + 7 @@ -42088,6 +43610,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event STOPPED 1 1 + oneToSet read @@ -42115,6 +43638,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event ERROR 5 5 + oneToSet read @@ -42142,6 +43666,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event WRITE 15 15 + oneToSet read @@ -42169,6 +43694,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event READ 16 16 + oneToSet read @@ -42196,6 +43722,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXEND 19 19 + oneToSet read @@ -42223,6 +43750,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXREADY 20 20 + oneToSet read @@ -42250,6 +43778,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXBUSERROR 21 21 + oneToSet read @@ -42277,6 +43806,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[0] 22 22 + oneToSet read @@ -42304,6 +43834,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[1] 23 23 + oneToSet read @@ -42331,6 +43862,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[2] 24 24 + oneToSet read @@ -42358,6 +43890,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[3] 25 25 + oneToSet read @@ -42385,6 +43918,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMATXEND 26 26 + oneToSet read @@ -42412,6 +43946,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMATXREADY 27 27 + oneToSet read @@ -42439,6 +43974,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMATXBUSERROR 28 28 + oneToSet read @@ -42476,6 +44012,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event STOPPED 1 1 + oneToClear read @@ -42503,6 +44040,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event ERROR 5 5 + oneToClear read @@ -42530,6 +44068,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event WRITE 15 15 + oneToClear read @@ -42557,6 +44096,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event READ 16 16 + oneToClear read @@ -42584,6 +44124,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXEND 19 19 + oneToClear read @@ -42611,6 +44152,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXREADY 20 20 + oneToClear read @@ -42638,6 +44180,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXBUSERROR 21 21 + oneToClear read @@ -42665,6 +44208,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[0] 22 22 + oneToClear read @@ -42692,6 +44236,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[1] 23 23 + oneToClear read @@ -42719,6 +44264,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[2] 24 24 + oneToClear read @@ -42746,6 +44292,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[3] 25 25 + oneToClear read @@ -42773,6 +44320,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMATXEND 26 26 + oneToClear read @@ -42800,6 +44348,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMATXREADY 27 27 + oneToClear read @@ -42827,6 +44376,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMATXBUSERROR 28 28 + oneToClear read @@ -43144,7 +44694,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.RAM buffer start address 0x004 read-write - 0x00000000 + 0x20000000 0x20 @@ -43218,7 +44768,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.BUSERRORADDRESS Address of transaction that generated the last BUSERROR event. 0x020 - read-write + read-only 0x00000000 0x20 @@ -43420,7 +44970,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.RAM buffer start address 0x004 read-write - 0x00000000 + 0x20000000 0x20 @@ -43494,7 +45044,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.BUSERRORADDRESS Address of transaction that generated the last BUSERROR event. 0x020 - read-write + read-only 0x00000000 0x20 @@ -45505,6 +47055,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CTS 0 0 + oneToSet read @@ -45532,6 +47083,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event NCTS 1 1 + oneToSet read @@ -45559,6 +47111,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TXDRDY 3 3 + oneToSet read @@ -45586,6 +47139,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event RXDRDY 4 4 + oneToSet read @@ -45613,6 +47167,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event ERROR 5 5 + oneToSet read @@ -45640,6 +47195,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event RXTO 9 9 + oneToSet read @@ -45667,6 +47223,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TXSTOPPED 12 12 + oneToSet read @@ -45694,6 +47251,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXEND 19 19 + oneToSet read @@ -45721,6 +47279,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXREADY 20 20 + oneToSet read @@ -45748,6 +47307,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXBUSERROR 21 21 + oneToSet read @@ -45775,6 +47335,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[0] 22 22 + oneToSet read @@ -45802,6 +47363,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[1] 23 23 + oneToSet read @@ -45829,6 +47391,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[2] 24 24 + oneToSet read @@ -45856,6 +47419,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMARXMATCH[3] 25 25 + oneToSet read @@ -45883,6 +47447,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMATXEND 26 26 + oneToSet read @@ -45910,6 +47475,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMATXREADY 27 27 + oneToSet read @@ -45937,6 +47503,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DMATXBUSERROR 28 28 + oneToSet read @@ -45964,6 +47531,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event FRAMETIMEOUT 29 29 + oneToSet read @@ -46001,6 +47569,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CTS 0 0 + oneToClear read @@ -46028,6 +47597,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event NCTS 1 1 + oneToClear read @@ -46055,6 +47625,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TXDRDY 3 3 + oneToClear read @@ -46082,6 +47653,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event RXDRDY 4 4 + oneToClear read @@ -46109,6 +47681,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event ERROR 5 5 + oneToClear read @@ -46136,6 +47709,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event RXTO 9 9 + oneToClear read @@ -46163,6 +47737,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TXSTOPPED 12 12 + oneToClear read @@ -46190,6 +47765,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXEND 19 19 + oneToClear read @@ -46217,6 +47793,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXREADY 20 20 + oneToClear read @@ -46244,6 +47821,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXBUSERROR 21 21 + oneToClear read @@ -46271,6 +47849,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[0] 22 22 + oneToClear read @@ -46298,6 +47877,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[1] 23 23 + oneToClear read @@ -46325,6 +47905,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[2] 24 24 + oneToClear read @@ -46352,6 +47933,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMARXMATCH[3] 25 25 + oneToClear read @@ -46379,6 +47961,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMATXEND 26 26 + oneToClear read @@ -46406,6 +47989,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMATXREADY 27 27 + oneToClear read @@ -46433,6 +48017,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DMATXBUSERROR 28 28 + oneToClear read @@ -46460,6 +48045,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event FRAMETIMEOUT 29 29 + oneToClear read @@ -49380,7 +50966,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - 8 + 4 0x008 EVENTS_CH[%s] Peripheral events. @@ -49643,7 +51229,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - 8 + 4 0x008 PUBLISH_CH[%s] Publish configuration for events @@ -49977,150 +51563,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - CH4LIMITH - Enable or disable interrupt for event CH4LIMITH - 14 - 14 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - CH4LIMITL - Enable or disable interrupt for event CH4LIMITL - 15 - 15 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - CH5LIMITH - Enable or disable interrupt for event CH5LIMITH - 16 - 16 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - CH5LIMITL - Enable or disable interrupt for event CH5LIMITL - 17 - 17 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - CH6LIMITH - Enable or disable interrupt for event CH6LIMITH - 18 - 18 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - CH6LIMITL - Enable or disable interrupt for event CH6LIMITL - 19 - 19 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - CH7LIMITH - Enable or disable interrupt for event CH7LIMITH - 20 - 20 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - CH7LIMITL - Enable or disable interrupt for event CH7LIMITL - 21 - 21 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - @@ -50136,6 +51578,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event STARTED 0 0 + oneToSet read @@ -50163,6 +51606,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event END 1 1 + oneToSet read @@ -50190,6 +51634,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DONE 2 2 + oneToSet read @@ -50217,6 +51662,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event RESULTDONE 3 3 + oneToSet read @@ -50244,6 +51690,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CALIBRATEDONE 4 4 + oneToSet read @@ -50271,6 +51718,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event STOPPED 5 5 + oneToSet read @@ -50298,6 +51746,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CH0LIMITH 6 6 + oneToSet read @@ -50325,6 +51774,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CH0LIMITL 7 7 + oneToSet read @@ -50352,6 +51802,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CH1LIMITH 8 8 + oneToSet read @@ -50379,6 +51830,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CH1LIMITL 9 9 + oneToSet read @@ -50406,6 +51858,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CH2LIMITH 10 10 + oneToSet read @@ -50433,6 +51886,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CH2LIMITL 11 11 + oneToSet read @@ -50460,6 +51914,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CH3LIMITH 12 12 + oneToSet read @@ -50487,222 +51942,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CH3LIMITL 13 13 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - CH4LIMITH - Write '1' to enable interrupt for event CH4LIMITH - 14 - 14 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - CH4LIMITL - Write '1' to enable interrupt for event CH4LIMITL - 15 - 15 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - CH5LIMITH - Write '1' to enable interrupt for event CH5LIMITH - 16 - 16 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - CH5LIMITL - Write '1' to enable interrupt for event CH5LIMITL - 17 - 17 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - CH6LIMITH - Write '1' to enable interrupt for event CH6LIMITH - 18 - 18 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - CH6LIMITL - Write '1' to enable interrupt for event CH6LIMITL - 19 - 19 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - CH7LIMITH - Write '1' to enable interrupt for event CH7LIMITH - 20 - 20 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - CH7LIMITL - Write '1' to enable interrupt for event CH7LIMITL - 21 - 21 + oneToSet read @@ -50740,6 +51980,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event STARTED 0 0 + oneToClear read @@ -50767,6 +52008,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event END 1 1 + oneToClear read @@ -50794,6 +52036,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DONE 2 2 + oneToClear read @@ -50821,6 +52064,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event RESULTDONE 3 3 + oneToClear read @@ -50848,6 +52092,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CALIBRATEDONE 4 4 + oneToClear read @@ -50871,226 +52116,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - STOPPED - Write '1' to disable interrupt for event STOPPED - 5 - 5 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - CH0LIMITH - Write '1' to disable interrupt for event CH0LIMITH - 6 - 6 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - CH0LIMITL - Write '1' to disable interrupt for event CH0LIMITL - 7 - 7 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - CH1LIMITH - Write '1' to disable interrupt for event CH1LIMITH - 8 - 8 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - CH1LIMITL - Write '1' to disable interrupt for event CH1LIMITL - 9 - 9 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - CH2LIMITH - Write '1' to disable interrupt for event CH2LIMITH - 10 - 10 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - CH2LIMITL - Write '1' to disable interrupt for event CH2LIMITL - 11 - 11 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - CH3LIMITH - Write '1' to disable interrupt for event CH3LIMITH - 12 - 12 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - CH3LIMITL - Write '1' to disable interrupt for event CH3LIMITL - 13 - 13 + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + oneToClear read @@ -51114,10 +52144,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - CH4LIMITH - Write '1' to disable interrupt for event CH4LIMITH - 14 - 14 + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + oneToClear read @@ -51141,10 +52172,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - CH4LIMITL - Write '1' to disable interrupt for event CH4LIMITL - 15 - 15 + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + oneToClear read @@ -51168,10 +52200,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - CH5LIMITH - Write '1' to disable interrupt for event CH5LIMITH - 16 - 16 + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + oneToClear read @@ -51195,10 +52228,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - CH5LIMITL - Write '1' to disable interrupt for event CH5LIMITL - 17 - 17 + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + oneToClear read @@ -51222,10 +52256,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - CH6LIMITH - Write '1' to disable interrupt for event CH6LIMITH - 18 - 18 + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + oneToClear read @@ -51249,10 +52284,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - CH6LIMITL - Write '1' to disable interrupt for event CH6LIMITL - 19 - 19 + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + oneToClear read @@ -51276,10 +52312,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - CH7LIMITH - Write '1' to disable interrupt for event CH7LIMITH - 20 - 20 + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + oneToClear read @@ -51303,10 +52340,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - CH7LIMITL - Write '1' to disable interrupt for event CH7LIMITL - 21 - 21 + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + oneToClear read @@ -51388,7 +52426,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - 8 + 4 0x010 CH[%s] Unspecified @@ -51397,7 +52435,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x510 PSELP - Description cluster: Input positive pin selection for CH[n] + Description cluster: Input positive pin selection for CH[m] 0x000 read-write 0x00000000 @@ -51417,10 +52455,15 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. INTERNAL - Internal input selection for analog positive input when CH[n].PSELP.CONNECT = Internal + Internal input selection for analog positive input when CH[m].PSELP.CONNECT = Internal 12 14 + + Dvdd + Connected to the internal 0.9 V digital supply rail + 0x0 + VddL Connected to VDDL @@ -51460,7 +52503,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. PSELN - Description cluster: Input negative pin selection for CH[n] + Description cluster: Input negative pin selection for CH[m] 0x004 read-write 0x00000000 @@ -51480,7 +52523,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. INTERNAL - Internal input selection for Analog negative input when CH[n].PSELN.CONNECT = Internal + Internal input selection for Analog negative input when CH[m].PSELN.CONNECT = Internal 12 14 @@ -51494,11 +52537,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Connected to VDDL 0x1 - - Vdd - Connected to VDD - 0x2 - Vss Unspecified @@ -51528,7 +52566,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. CONFIG - Description cluster: Input configuration for CH[n] + Description cluster: Input configuration for CH[m] 0x008 read-write 0x00020000 @@ -51597,11 +52635,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Reference given at VDDL 0x2 - - Vdd - Reference given at VDD - 0x3 - @@ -52111,6 +53144,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DATARDY 0 0 + oneToSet read @@ -52148,6 +53182,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DATARDY 0 0 + oneToClear read @@ -52194,7 +53229,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Slope of 1st piece wise linear function 0x520 read-write - 0x000002D6 + 0x0000038C 0x20 @@ -52210,7 +53245,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Slope of 2nd piece wise linear function 0x524 read-write - 0x0000032D + 0x000003B3 0x20 @@ -52226,7 +53261,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Slope of 3rd piece wise linear function 0x528 read-write - 0x00000384 + 0x000003FA 0x20 @@ -52242,7 +53277,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Slope of 4th piece wise linear function 0x52C read-write - 0x000003E9 + 0x00000451 0x20 @@ -52258,7 +53293,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Slope of 5th piece wise linear function 0x530 read-write - 0x0000046F + 0x000004AA 0x20 @@ -52274,7 +53309,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Slope of 6th piece wise linear function 0x534 read-write - 0x00000522 + 0x00000539 0x20 @@ -52290,7 +53325,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Slope of 7th piece wise linear function 0x538 read-write - 0x000005B7 + 0x00000578 0x20 @@ -52306,7 +53341,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.y-intercept of 1st piece wise linear function 0x540 read-write - 0x00000FD6 + 0x00000037 0x20 @@ -52322,7 +53357,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.y-intercept of 2nd piece wise linear function 0x544 read-write - 0x00000F76 + 0x00000011 0x20 @@ -52338,7 +53373,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.y-intercept of 3rd piece wise linear function 0x548 read-write - 0x00000F8A + 0x00000005 0x20 @@ -52354,7 +53389,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.y-intercept of 4th piece wise linear function 0x54C read-write - 0x00000FF8 + 0x0000002B 0x20 @@ -52370,7 +53405,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.y-intercept of 5th piece wise linear function 0x550 read-write - 0x000000CC + 0x0000008F 0x20 @@ -52386,7 +53421,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.y-intercept of 6th piece wise linear function 0x554 read-write - 0x00000207 + 0x0000015D 0x20 @@ -52402,7 +53437,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.y-intercept of 7th piece wise linear function 0x558 read-write - 0x00000558 + 0x000001C0 0x20 @@ -52418,7 +53453,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.End point of 1st piece wise linear function 0x560 read-write - 0x000000E2 + 0x000000E5 0x20 @@ -52434,7 +53469,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.End point of 2nd piece wise linear function 0x564 read-write - 0x00000002 + 0x000000FB 0x20 @@ -52450,7 +53485,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.End point of 3rd piece wise linear function 0x568 read-write - 0x0000001F + 0x00000010 0x20 @@ -52466,7 +53501,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.End point of 4th piece wise linear function 0x56C read-write - 0x00000038 + 0x0000002B 0x20 @@ -52482,7 +53517,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.End point of 5th piece wise linear function 0x570 read-write - 0x0000004F + 0x00000041 0x20 @@ -52498,7 +53533,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.End point of 6th piece wise linear function 0x574 read-write - 0x00000066 + 0x00000050 0x20 @@ -58838,7 +59873,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x140 NONSECURE - Description cluster: Non-secure port event from owner n + Description cluster: Non-secure port event 0x000 read-write 0x00000000 @@ -58847,7 +59882,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. NONSECURE - Non-secure port event from owner n + Non-secure port event 0 0 @@ -58867,7 +59902,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. SECURE - Description cluster: Secure port event from owner n + Description cluster: Secure port event 0x004 read-write 0x00000000 @@ -58876,7 +59911,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. SECURE - Secure port event from owner n + Secure port event 0 0 @@ -59020,6 +60055,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event IN[0] 0 0 + oneToSet read @@ -59047,6 +60083,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event IN[1] 1 1 + oneToSet read @@ -59074,6 +60111,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event IN[2] 2 2 + oneToSet read @@ -59101,6 +60139,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event IN[3] 3 3 + oneToSet read @@ -59128,6 +60167,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event IN[4] 4 4 + oneToSet read @@ -59155,6 +60195,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event IN[5] 5 5 + oneToSet read @@ -59182,6 +60223,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event IN[6] 6 6 + oneToSet read @@ -59209,6 +60251,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event IN[7] 7 7 + oneToSet read @@ -59236,6 +60279,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PORT0NONSECURE 16 16 + oneToSet read @@ -59263,6 +60307,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PORT0SECURE 17 17 + oneToSet read @@ -59300,6 +60345,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event IN[0] 0 0 + oneToClear read @@ -59327,6 +60373,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event IN[1] 1 1 + oneToClear read @@ -59354,6 +60401,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event IN[2] 2 2 + oneToClear read @@ -59381,6 +60429,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event IN[3] 3 3 + oneToClear read @@ -59408,6 +60457,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event IN[4] 4 4 + oneToClear read @@ -59435,6 +60485,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event IN[5] 5 5 + oneToClear read @@ -59462,6 +60513,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event IN[6] 6 6 + oneToClear read @@ -59489,6 +60541,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event IN[7] 7 7 + oneToClear read @@ -59516,6 +60569,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event PORT0NONSECURE 16 16 + oneToClear read @@ -59543,6 +60597,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event PORT0SECURE 17 17 + oneToClear read @@ -59580,6 +60635,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event IN[0] 0 0 + oneToSet read @@ -59607,6 +60663,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event IN[1] 1 1 + oneToSet read @@ -59634,6 +60691,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event IN[2] 2 2 + oneToSet read @@ -59661,6 +60719,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event IN[3] 3 3 + oneToSet read @@ -59688,6 +60747,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event IN[4] 4 4 + oneToSet read @@ -59715,6 +60775,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event IN[5] 5 5 + oneToSet read @@ -59742,6 +60803,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event IN[6] 6 6 + oneToSet read @@ -59769,6 +60831,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event IN[7] 7 7 + oneToSet read @@ -59796,6 +60859,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PORT0NONSECURE 16 16 + oneToSet read @@ -59823,6 +60887,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PORT0SECURE 17 17 + oneToSet read @@ -59860,6 +60925,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event IN[0] 0 0 + oneToClear read @@ -59887,6 +60953,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event IN[1] 1 1 + oneToClear read @@ -59914,6 +60981,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event IN[2] 2 2 + oneToClear read @@ -59941,6 +61009,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event IN[3] 3 3 + oneToClear read @@ -59968,6 +61037,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event IN[4] 4 4 + oneToClear read @@ -59995,6 +61065,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event IN[5] 5 5 + oneToClear read @@ -60022,6 +61093,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event IN[6] 6 6 + oneToClear read @@ -60049,6 +61121,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event IN[7] 7 7 + oneToClear read @@ -60076,6 +61149,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event PORT0NONSECURE 16 16 + oneToClear read @@ -60103,6 +61177,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event PORT0SECURE 17 17 + oneToClear read @@ -61027,6 +62102,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[0] 0 0 + oneToSet read @@ -61054,6 +62130,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[1] 1 1 + oneToSet read @@ -61081,6 +62158,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[2] 2 2 + oneToSet read @@ -61108,6 +62186,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[3] 3 3 + oneToSet read @@ -61135,6 +62214,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[4] 4 4 + oneToSet read @@ -61162,6 +62242,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[5] 5 5 + oneToSet read @@ -61189,6 +62270,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[6] 6 6 + oneToSet read @@ -61216,6 +62298,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[7] 7 7 + oneToSet read @@ -61243,6 +62326,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[8] 8 8 + oneToSet read @@ -61270,6 +62354,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[9] 9 9 + oneToSet read @@ -61297,6 +62382,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[10] 10 10 + oneToSet read @@ -61324,6 +62410,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[11] 11 11 + oneToSet read @@ -61351,6 +62438,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event RTCOMPARESYNC 25 25 + oneToSet read @@ -61378,6 +62466,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PWMPERIODEND 27 27 + oneToSet read @@ -61405,6 +62494,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PWMREADY 29 29 + oneToSet read @@ -61432,6 +62522,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CLKOUTREADY 30 30 + oneToSet read @@ -61469,6 +62560,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[0] 0 0 + oneToClear read @@ -61496,6 +62588,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[1] 1 1 + oneToClear read @@ -61523,6 +62616,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[2] 2 2 + oneToClear read @@ -61550,6 +62644,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[3] 3 3 + oneToClear read @@ -61577,6 +62672,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[4] 4 4 + oneToClear read @@ -61604,6 +62700,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[5] 5 5 + oneToClear read @@ -61631,6 +62728,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[6] 6 6 + oneToClear read @@ -61658,6 +62756,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[7] 7 7 + oneToClear read @@ -61685,6 +62784,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[8] 8 8 + oneToClear read @@ -61712,6 +62812,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[9] 9 9 + oneToClear read @@ -61739,6 +62840,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[10] 10 10 + oneToClear read @@ -61766,6 +62868,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[11] 11 11 + oneToClear read @@ -61793,6 +62896,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event RTCOMPARESYNC 25 25 + oneToClear read @@ -61820,6 +62924,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event PWMPERIODEND 27 27 + oneToClear read @@ -61847,6 +62952,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event PWMREADY 29 29 + oneToClear read @@ -61874,6 +62980,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CLKOUTREADY 30 30 + oneToClear read @@ -62523,6 +63630,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[0] 0 0 + oneToSet read @@ -62550,6 +63658,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[1] 1 1 + oneToSet read @@ -62577,6 +63686,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[2] 2 2 + oneToSet read @@ -62604,6 +63714,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[3] 3 3 + oneToSet read @@ -62631,6 +63742,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[4] 4 4 + oneToSet read @@ -62658,6 +63770,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[5] 5 5 + oneToSet read @@ -62685,6 +63798,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[6] 6 6 + oneToSet read @@ -62712,6 +63826,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[7] 7 7 + oneToSet read @@ -62739,6 +63854,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[8] 8 8 + oneToSet read @@ -62766,6 +63882,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[9] 9 9 + oneToSet read @@ -62793,6 +63910,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[10] 10 10 + oneToSet read @@ -62820,6 +63938,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[11] 11 11 + oneToSet read @@ -62847,6 +63966,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event RTCOMPARESYNC 25 25 + oneToSet read @@ -62874,6 +63994,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PWMPERIODEND 27 27 + oneToSet read @@ -62901,6 +64022,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PWMREADY 29 29 + oneToSet read @@ -62928,6 +64050,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CLKOUTREADY 30 30 + oneToSet read @@ -62965,6 +64088,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[0] 0 0 + oneToClear read @@ -62992,6 +64116,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[1] 1 1 + oneToClear read @@ -63019,6 +64144,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[2] 2 2 + oneToClear read @@ -63046,6 +64172,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[3] 3 3 + oneToClear read @@ -63073,6 +64200,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[4] 4 4 + oneToClear read @@ -63100,6 +64228,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[5] 5 5 + oneToClear read @@ -63127,6 +64256,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[6] 6 6 + oneToClear read @@ -63154,6 +64284,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[7] 7 7 + oneToClear read @@ -63181,6 +64312,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[8] 8 8 + oneToClear read @@ -63208,6 +64340,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[9] 9 9 + oneToClear read @@ -63235,6 +64368,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[10] 10 10 + oneToClear read @@ -63262,6 +64396,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[11] 11 11 + oneToClear read @@ -63289,6 +64424,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event RTCOMPARESYNC 25 25 + oneToClear read @@ -63316,6 +64452,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event PWMPERIODEND 27 27 + oneToClear read @@ -63343,6 +64480,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event PWMREADY 29 29 + oneToClear read @@ -63370,6 +64508,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CLKOUTREADY 30 30 + oneToClear read @@ -64019,6 +65158,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[0] 0 0 + oneToSet read @@ -64046,6 +65186,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[1] 1 1 + oneToSet read @@ -64073,6 +65214,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[2] 2 2 + oneToSet read @@ -64100,6 +65242,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[3] 3 3 + oneToSet read @@ -64127,6 +65270,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[4] 4 4 + oneToSet read @@ -64154,6 +65298,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[5] 5 5 + oneToSet read @@ -64181,6 +65326,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[6] 6 6 + oneToSet read @@ -64208,6 +65354,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[7] 7 7 + oneToSet read @@ -64235,6 +65382,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[8] 8 8 + oneToSet read @@ -64262,6 +65410,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[9] 9 9 + oneToSet read @@ -64289,6 +65438,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[10] 10 10 + oneToSet read @@ -64316,6 +65466,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[11] 11 11 + oneToSet read @@ -64343,6 +65494,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event RTCOMPARESYNC 25 25 + oneToSet read @@ -64370,6 +65522,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PWMPERIODEND 27 27 + oneToSet read @@ -64397,6 +65550,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PWMREADY 29 29 + oneToSet read @@ -64424,6 +65578,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CLKOUTREADY 30 30 + oneToSet read @@ -64461,6 +65616,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[0] 0 0 + oneToClear read @@ -64488,6 +65644,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[1] 1 1 + oneToClear read @@ -64515,6 +65672,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[2] 2 2 + oneToClear read @@ -64542,6 +65700,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[3] 3 3 + oneToClear read @@ -64569,6 +65728,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[4] 4 4 + oneToClear read @@ -64596,6 +65756,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[5] 5 5 + oneToClear read @@ -64623,6 +65784,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[6] 6 6 + oneToClear read @@ -64650,6 +65812,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[7] 7 7 + oneToClear read @@ -64677,6 +65840,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[8] 8 8 + oneToClear read @@ -64704,6 +65868,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[9] 9 9 + oneToClear read @@ -64731,6 +65896,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[10] 10 10 + oneToClear read @@ -64758,6 +65924,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[11] 11 11 + oneToClear read @@ -64785,6 +65952,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event RTCOMPARESYNC 25 25 + oneToClear read @@ -64812,6 +65980,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event PWMPERIODEND 27 27 + oneToClear read @@ -64839,6 +66008,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event PWMREADY 29 29 + oneToClear read @@ -64866,6 +66036,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CLKOUTREADY 30 30 + oneToClear read @@ -65515,6 +66686,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[0] 0 0 + oneToSet read @@ -65542,6 +66714,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[1] 1 1 + oneToSet read @@ -65569,6 +66742,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[2] 2 2 + oneToSet read @@ -65596,6 +66770,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[3] 3 3 + oneToSet read @@ -65623,6 +66798,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[4] 4 4 + oneToSet read @@ -65650,6 +66826,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[5] 5 5 + oneToSet read @@ -65677,6 +66854,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[6] 6 6 + oneToSet read @@ -65704,6 +66882,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[7] 7 7 + oneToSet read @@ -65731,6 +66910,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[8] 8 8 + oneToSet read @@ -65758,6 +66938,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[9] 9 9 + oneToSet read @@ -65785,6 +66966,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[10] 10 10 + oneToSet read @@ -65812,6 +66994,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event COMPARE[11] 11 11 + oneToSet read @@ -65839,6 +67022,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event RTCOMPARESYNC 25 25 + oneToSet read @@ -65866,6 +67050,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PWMPERIODEND 27 27 + oneToSet read @@ -65893,6 +67078,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PWMREADY 29 29 + oneToSet read @@ -65920,6 +67106,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CLKOUTREADY 30 30 + oneToSet read @@ -65957,6 +67144,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[0] 0 0 + oneToClear read @@ -65984,6 +67172,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[1] 1 1 + oneToClear read @@ -66011,6 +67200,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[2] 2 2 + oneToClear read @@ -66038,6 +67228,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[3] 3 3 + oneToClear read @@ -66065,6 +67256,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[4] 4 4 + oneToClear read @@ -66092,6 +67284,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[5] 5 5 + oneToClear read @@ -66119,6 +67312,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[6] 6 6 + oneToClear read @@ -66146,6 +67340,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[7] 7 7 + oneToClear read @@ -66173,6 +67368,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[8] 8 8 + oneToClear read @@ -66200,6 +67396,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[9] 9 9 + oneToClear read @@ -66227,6 +67424,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[10] 10 10 + oneToClear read @@ -66254,6 +67452,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event COMPARE[11] 11 11 + oneToClear read @@ -66281,6 +67480,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event RTCOMPARESYNC 25 25 + oneToClear read @@ -66308,6 +67508,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event PWMPERIODEND 27 27 + oneToClear read @@ -66335,6 +67536,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event PWMREADY 29 29 + oneToClear read @@ -66362,6 +67564,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CLKOUTREADY 30 30 + oneToClear read @@ -66892,7 +68095,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.CCADD Description cluster: Count to add to CC[n] when this register is written. 0x008 - read-write + write-only 0x00000000 0x20 @@ -67496,6 +68699,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TAMPER 0 0 + oneToSet read @@ -67523,6 +68727,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event WRITEERROR 1 1 + oneToSet read @@ -67560,6 +68765,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TAMPER 0 0 + oneToClear read @@ -67587,6 +68793,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event WRITEERROR 1 1 + oneToClear read @@ -67903,12 +69110,12 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. Low - Signal is logic 0. + Signal is logic 0, indicating that invasive debug is disabled. 0x0 High - Signal is logic 1. + Signal is logic 1, indicating that invasive debug is enabled. 0x1 @@ -68024,12 +69231,12 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. Low - Signal is logic 0. + Signal is logic 0, indicating that non-invasive debug is disabled. 0x0 High - Signal is logic 1. + Signal is logic 1, indicating that non-invasive debug is enabled. 0x1 @@ -68145,12 +69352,12 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. Low - Signal is logic 0. + Signal is logic 0, indicating that secure priviliged invasive debug is disabled. 0x0 High - Signal is logic 1. + Signal is logic 1, indicating that secure priviliged invasive debug is enabled. 0x1 @@ -68266,12 +69473,12 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. Low - Signal is logic 0. + Signal is logic 0, indicating that secure priviliged non-invasive debug is disabled. 0x0 High - Signal is logic 1. + Signal is logic 1, indicating that secure priviliged non-invasive debug is enabled. 0x1 @@ -68382,7 +69589,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x000 CTRL - Description cluster: Control register to enable invasive (halting) debug in domain n's access port. + Description cluster: Control register to enable invasive (halting) debug in domain ns access port. 0x000 read-write 0x00000010 @@ -68396,12 +69603,12 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. Low - Signal is logic 0. + Signal is logic 0, indicating that invasive debug is disabled. 0x0 High - Signal is logic 1. + Signal is logic 1, indicating that invasive debug is enabled. 0x1 @@ -68467,7 +69674,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. STATUS - Description cluster: Status register for invasive (halting) debug enable for domain n's access port. + Description cluster: Status register for invasive (halting) debug enable for domain ns access port. 0x004 read-write 0x00000000 @@ -70131,6 +71338,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event READY 0 0 + oneToSet read @@ -70158,6 +71366,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DOWN 1 1 + oneToSet read @@ -70185,6 +71394,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event UP 2 2 + oneToSet read @@ -70212,6 +71422,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CROSS 3 3 + oneToSet read @@ -70249,6 +71460,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event READY 0 0 + oneToClear read @@ -70276,6 +71488,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DOWN 1 1 + oneToClear read @@ -70303,6 +71516,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event UP 2 2 + oneToClear read @@ -70330,6 +71544,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CROSS 3 3 + oneToClear read @@ -71336,6 +72551,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event READY 0 0 + oneToSet read @@ -71363,6 +72579,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DOWN 1 1 + oneToSet read @@ -71390,6 +72607,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event UP 2 2 + oneToSet read @@ -71417,6 +72635,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event CROSS 3 3 + oneToSet read @@ -71454,6 +72673,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event READY 0 0 + oneToClear read @@ -71481,6 +72701,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DOWN 1 1 + oneToClear read @@ -71508,6 +72729,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event UP 2 2 + oneToClear read @@ -71535,6 +72757,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event CROSS 3 3 + oneToClear read @@ -72195,6 +73418,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TIMEOUT 0 0 + oneToSet read @@ -72222,6 +73446,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event STOPPED 1 1 + oneToSet read @@ -72259,6 +73484,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TIMEOUT 0 0 + oneToClear read @@ -72286,6 +73512,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event STOPPED 1 1 + oneToClear read @@ -72323,6 +73550,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event TIMEOUT 0 0 + oneToSet read @@ -72350,6 +73578,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event STOPPED 1 1 + oneToSet read @@ -72387,6 +73616,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event TIMEOUT 0 0 + oneToClear read @@ -72414,6 +73644,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event STOPPED 1 1 + oneToClear read @@ -74073,6 +75304,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event XOSTARTED 0 0 + oneToSet read @@ -74100,6 +75332,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event PLLSTARTED 1 1 + oneToSet read @@ -74127,6 +75360,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event LFCLKSTARTED 2 2 + oneToSet read @@ -74154,6 +75388,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event DONE 3 3 + oneToSet read @@ -74181,6 +75416,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event XOTUNED 4 4 + oneToSet read @@ -74208,6 +75444,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event XOTUNEERROR 5 5 + oneToSet read @@ -74235,6 +75472,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event XOTUNEFAILED 6 6 + oneToSet read @@ -74272,6 +75510,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event XOSTARTED 0 0 + oneToClear read @@ -74299,6 +75538,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event PLLSTARTED 1 1 + oneToClear read @@ -74326,6 +75566,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event LFCLKSTARTED 2 2 + oneToClear read @@ -74353,6 +75594,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event DONE 3 3 + oneToClear read @@ -74380,6 +75622,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event XOTUNED 4 4 + oneToClear read @@ -74407,6 +75650,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event XOTUNEERROR 5 5 + oneToClear read @@ -74434,6 +75678,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event XOTUNEFAILED 6 6 + oneToClear read @@ -75273,6 +76518,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event POFWARN 12 12 + oneToSet read @@ -75300,6 +76546,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event SLEEPENTER 13 13 + oneToSet read @@ -75327,6 +76574,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to enable interrupt for event SLEEPEXIT 14 14 + oneToSet read @@ -75364,6 +76612,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event POFWARN 12 12 + oneToClear read @@ -75391,6 +76640,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event SLEEPENTER 13 13 + oneToClear read @@ -75418,6 +76668,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Write '1' to disable interrupt for event SLEEPEXIT 14 14 + oneToClear read @@ -75915,6 +77166,34 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.OSCILLATORS_XOSC32KI read-write 0x900 + + BYPASS + Enable or disable bypass of LFCLK crystal oscillator with external clock source + 0x000 + read-write + 0x00000000 + 0x20 + + + BYPASS + Enable or disable bypass of LFCLK crystal oscillator with external clock source + 0 + 0 + + + Disabled + Disable (use crystal) + 0x0 + + + Enabled + Enable (use rail-to-rail external source) + 0x1 + + + + + INTCAP Programmable capacitance of XL1 and XL2 @@ -76091,161 +77370,81 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.1 4 - - V17 - Set threshold to 1.7 V for VDD - 0x0 - V090 Set threshold to 0.90 V for VDDL 0x0 - - V18 - Set threshold to 1.8 V for VDD - 0x1 - V095 Set threshold to 0.95 V for VDDL 0x1 - - V19 - Set threshold to 1.9 V for VDD - 0x2 - V100 Set threshold to 1.00 V for VDDL 0x2 - - V20 - Set threshold to 2.0 V for VDD - 0x3 - V105 Set threshold to 1.05 V for VDDL 0x3 - - V21 - Set threshold to 2.1 V for VDD - 0x4 - V110 Set threshold to 1.10 V for VDDL 0x4 - - V22 - Set threshold to 2.2 V for VDD - 0x5 - V115 Set threshold to 1.15 V for VDDL 0x5 - - V23 - Set threshold to 2.3 V for VDD - 0x6 - V120 Set threshold to 1.20 V for VDDL 0x6 - - V24 - Set threshold to 2.4 V for VDD - 0x7 - V125 Set threshold to 1.25 V for VDDL 0x7 - - V25 - Set threshold to 2.5 V for VDD - 0x8 - V130 Set threshold to 1.30 V for VDDL 0x8 - - V26 - Set threshold to 2.6 V for VDD - 0x9 - V135 Set threshold to 1.35 V for VDDL 0x9 - - V27 - Set threshold to 2.7 V for VDD - 0xA - V140 Set threshold to 1.40 V for VDDL 0xA - - V28 - Set threshold to 2.8 V for VDD - 0xB - V145 Set threshold to 1.45 V for VDDL 0xB - - V29 - Set threshold to 2.9 V for VDD - 0xC - V150 Set threshold to 1.50 V for VDDL 0xC - - V30 - Set threshold to 3.0 V for VDD - 0xD - V155 Set threshold to 1.55 V for VDDL 0xD - - V31 - Set threshold to 3.1 V for VDD - 0xE - V160 Set threshold to 1.60 V for VDDL 0xE - - V32 - Set threshold to 3.2 V for VDD - 0xF - V165 Set threshold to 1.65 V for VDDL @@ -76277,14 +77476,9 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.16 16 - - Vdd - POF input connected to VDD - 0x0 - VddL - POF input connected to VDDL + POF input connected to VDDL 0x1 diff --git a/nrfx/mdk/nrf54lv10a_enga_application_peripherals.h b/nrfx/mdk/nrf54lv10a_enga_application_peripherals.h index 6d747b0f..e4eb84cb 100644 --- a/nrfx/mdk/nrf54lv10a_enga_application_peripherals.h +++ b/nrfx/mdk/nrf54lv10a_enga_application_peripherals.h @@ -97,6 +97,12 @@ POSSIBILITY OF SUCH DAMAGE. #define ICACHE_VIRTUALCACHE 0 /*!< (unspecified) */ #define ICACHE_FLUSH 0 /*!< (unspecified) */ #define ICACHE_CLEAN 0 /*!< (unspecified) */ +#define ICACHE_INVALIDATELINE 1 /*!< (unspecified) */ +#define ICACHE_ERASE 1 /*!< (unspecified) */ +#define ICACHE_LINEMAINTAIN 1 /*!< (unspecified) */ +#define ICACHE_EXTENDEDPROFILING 1 /*!< (unspecified) */ +#define ICACHE_DEBUGLOCK 1 /*!< (unspecified) */ +#define ICACHE_WRITELOCK 1 /*!< (unspecified) */ #define ICACHE_NONCACHEABLEMISS 0 /*!< (unspecified) */ #define ICACHE_BUSWIDTH_MIN 0 /*!< Data bus width : 0..63 */ #define ICACHE_BUSWIDTH_MAX 63 /*!< Data bus width : 0..63 */ @@ -349,9 +355,9 @@ POSSIBILITY OF SUCH DAMAGE. #define VPR00_VEVIF_NTASKS_MAX 22 /*!< VEVIF tasks: 16..22 */ #define VPR00_VEVIF_NTASKS_SIZE 23 /*!< VEVIF tasks: 16..22 */ #define VPR00_VEVIF_TASKS_MASK 0x007F0000 /*!< Mask of supported VEVIF tasks: 0x007F0000 */ -#define VPR00_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..3 */ -#define VPR00_VEVIF_NDPPI_MAX 3 /*!< VEVIF DPPI channels: 0..3 */ -#define VPR00_VEVIF_NDPPI_SIZE 4 /*!< VEVIF DPPI channels: 0..3 */ +#define VPR00_VEVIF_NDPPI_MIN 16 /*!< VEVIF DPPI indices: 16..19 */ +#define VPR00_VEVIF_NDPPI_MAX 19 /*!< VEVIF DPPI indices: 16..19 */ +#define VPR00_VEVIF_NDPPI_SIZE 20 /*!< VEVIF DPPI indices: 16..19 */ #define VPR00_VEVIF_DPPI_MASK 0x000F0000 /*!< Mask of supported VEVIF DPPI channels: 0x000F0000 */ #define VPR00_VEVIF_NEVENTS_MIN 16 /*!< VEVIF events: 16..22 */ #define VPR00_VEVIF_NEVENTS_MAX 22 /*!< VEVIF events: 16..22 */ @@ -575,9 +581,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CRACEN_ONLYPROTECTEDRAMLOCK 0 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_SEED 0x51810000 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_SEED_SIZE 64 /*!< (unspecified) */ -#define CRACEN_PROTECTED_RAM_AES_KEY0 0x51810040 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_AES_KEY0 0x2002FF00 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_AES_KEY0_SIZE 32 /*!< (unspecified) */ -#define CRACEN_PROTECTED_RAM_AES_KEY1 0x51810060 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_AES_KEY1 0x2002FF20 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_AES_KEY1_SIZE 32 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_SM4_KEY0 0x51810080 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_SM4_KEY0_SIZE 16 /*!< (unspecified) */ @@ -668,7 +674,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ #define SPIM30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define SPIM30_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ -#define SPIM30_FEATURE_HARDWARE_DCX_PRESENT 0 /*!< (unspecified) */ +#define SPIM30_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ #define SPIM30_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ #define SPIM30_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ #define SPIM30_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ @@ -793,7 +799,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_PSEL_V2 1 /*!< (unspecified) */ #define SAADC_TASKS_CALIBRATEGAIN 0 /*!< (unspecified) */ -#define SAADC_SAMPLERATE_CC_VALUERANGE_MIN 8 /*!< (unspecified) */ +#define SAADC_SAMPLERATE_CC_VALUERANGE_MIN 16 /*!< (unspecified) */ #define SAADC_SAMPLERATE_CC_VALUERANGE_MAX 2047 /*!< (unspecified) */ #define SAADC_SAMPLERATE_CC_VALUERANGE_SIZE 2048 /*!< (unspecified) */ #define SAADC_TACQ_VALUE_RANGE_MIN 1 /*!< (unspecified) */ @@ -802,6 +808,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_TCONV_VALUE_RANGE_MIN 1 /*!< (unspecified) */ #define SAADC_TCONV_VALUE_RANGE_MAX 7 /*!< (unspecified) */ #define SAADC_TCONV_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ /*Temperature Sensor*/ #define TEMP_PRESENT 1 @@ -815,6 +822,7 @@ POSSIBILITY OF SUCH DAMAGE. #define P1_CTRLSEL_MAP2 1 /*!< (unspecified) */ #define P1_CTRLSEL_MAP3 0 /*!< (unspecified) */ #define P1_CTRLSEL_MAP4 0 /*!< (unspecified) */ +#define P1_CTRLSEL_MAP5 0 /*!< (unspecified) */ #define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ #define P1_PIN_NUM_MAX 25 /*!< (unspecified) */ #define P1_PIN_NUM_SIZE 26 /*!< (unspecified) */ @@ -834,6 +842,7 @@ POSSIBILITY OF SUCH DAMAGE. #define P0_CTRLSEL_MAP2 1 /*!< (unspecified) */ #define P0_CTRLSEL_MAP3 0 /*!< (unspecified) */ #define P0_CTRLSEL_MAP4 0 /*!< (unspecified) */ +#define P0_CTRLSEL_MAP5 0 /*!< (unspecified) */ #define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ #define P0_PIN_NUM_MAX 4 /*!< (unspecified) */ #define P0_PIN_NUM_SIZE 5 /*!< (unspecified) */ @@ -901,7 +910,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GRTC_CLKOUTREG 1 /*!< (unspecified) */ #define GRTC_CLKSELREG 1 /*!< (unspecified) */ #define GRTC_CLKSELLFLPRC 1 /*!< (unspecified) */ -#define GRTC_CCADD_WRITE_ONLY 0 /*!< (unspecified) */ +#define GRTC_CCADD_WRITE_ONLY 1 /*!< (unspecified) */ #define GRTC_READY_STATUS_AND_EVENTS 1 /*!< (unspecified) */ #define GRTC_SYSCOUNTER_LOADED_STATUS 1 /*!< (unspecified) */ #define GRTC_CC_PAST_STATUS 1 /*!< (unspecified) */ @@ -916,6 +925,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TAMPC_TAMPERSWITCH 0 /*!< (unspecified) */ #define TAMPC_SM4DISABLECM 0 /*!< (unspecified) */ #define TAMPC_PROTECTRESETBEHAVIOR 0 /*!< (unspecified) */ +#define TAMPC_SPIDEN 1 /*!< (unspecified) */ +#define TAMPC_SPNIDEN 1 /*!< (unspecified) */ +#define TAMPC_ACTIVESHIELD 1 /*!< (unspecified) */ /*Comparator*/ #define COMP_PRESENT 1 @@ -960,6 +972,8 @@ POSSIBILITY OF SUCH DAMAGE. #define REGULATORS_PRESENT 1 #define REGULATORS_COUNT 1 +#define REGULATORS_POF 1 /*!< (unspecified) */ + /* ==================================================== Baudrate settings ==================================================== */ /** * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency diff --git a/nrfx/mdk/nrf54lv10a_enga_flpr.svd b/nrfx/mdk/nrf54lv10a_enga_flpr.svd index a34358d0..6f316a37 100644 --- a/nrfx/mdk/nrf54lv10a_enga_flpr.svd +++ b/nrfx/mdk/nrf54lv10a_enga_flpr.svd @@ -110,7 +110,7 @@ POSSIBILITY OF SUCH DAMAGE. UUID[%s] Description collection: 128-bit Universally Unique IDentifier (UUID). 0x00C - read-write + read-only 0xFFFFFFFF 0x20 @@ -213,7 +213,7 @@ POSSIBILITY OF SUCH DAMAGE. K192 192 kByte RAM - 0x00000080 + 0x000000C0 Unspecified @@ -603,11 +603,11 @@ POSSIBILITY OF SUCH DAMAGE. Erase Protection Registers UICR_ERASEPROTECT read-writeonce - 0x060 + 0x60 PROTECT0 Description cluster: Erase protection - 0x000 + 0x0 read-writeonce 0xFFFFFFFF 0x20 @@ -629,7 +629,7 @@ POSSIBILITY OF SUCH DAMAGE. PROTECT1 Description cluster: Erase protection - 0x01C + 0x1C read-writeonce 0xFFFFFFFF 0x20 @@ -1855,9 +1855,10 @@ POSSIBILITY OF SUCH DAMAGE. ENABLE - Start/enable the NDRNG. + Start the NDRNG. Self-clearing bit. 0 0 + write-only LFSREN @@ -2023,9 +2024,9 @@ POSSIBILITY OF SUCH DAMAGE. FIFOTHRESHOLD - FIFO level below which the module leaves the idle state to refill the FIFO, expressed in number of 128bit blocks. + FIFO level threshold below which the module leaves the idle state to refill the FIFO. Expressed in number of 128bit blocks. 0 - 31 + 2 @@ -2190,30 +2191,35 @@ POSSIBILITY OF SUCH DAMAGE. NIST repetition test(s) failure. 4 4 + read-only PROPFAIL NIST proportion test(s) failure. 5 5 + read-only ANYHEALTHTESTFAIL Any of the enabled health tests is failing. 6 6 + zeroToClear FULLINT FIFO full status. 7 7 + read-only STARTUPFAIL Start-up test(s) failure. 10 10 + zeroToClear REPTESTFAILPERSHARE @@ -2234,6 +2240,7 @@ POSSIBILITY OF SUCH DAMAGE. Conditioning consumes data slower than they are provided to it. 20 20 + zeroToClear @@ -2263,9 +2270,9 @@ POSSIBILITY OF SUCH DAMAGE. DISABLEOSC - Disable oscillator rings 0 to 7. + Disable oscillator rings. 0 - 7 + 31 @@ -2351,13 +2358,13 @@ POSSIBILITY OF SUCH DAMAGE. DLYZEROCUTOFF Auto-correlation test cut-off value for delay of 0 samples. 0 - 15 + 6 DLYONECUTOFF Auto-correlation test cut-off value for delay of +1 sample. 16 - 31 + 22 @@ -2373,13 +2380,13 @@ POSSIBILITY OF SUCH DAMAGE. DLYTWOCUTOFF Auto-correlation test cut-off value for delay of +2 samples. 0 - 15 + 6 DLYTHREECUTOFF Auto-correlation test cut-off value for delay of +3 samples. 16 - 31 + 22 @@ -2395,13 +2402,13 @@ POSSIBILITY OF SUCH DAMAGE. DLYZEROCUTOFF Correlation test cut-off value for delay of 0 samples. 0 - 15 + 6 DLYONECUTOFF Correlation test cut-off value for delay of +/-1 sample. 16 - 31 + 22 @@ -2752,7 +2759,7 @@ POSSIBILITY OF SUCH DAMAGE. TIMER - Number of clock cycles (as the number of core cycles is always even, register bit 0 is tied to zero. + Number of clock cycles (as the number of core cycles is always even, register bit 0 is tied to zero). 1 31 @@ -3962,6 +3969,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PERIPHACCERR 0 0 + oneToSet read @@ -3999,6 +4007,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event PERIPHACCERR 0 0 + oneToClear read @@ -4834,6 +4843,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event MEMACCERR 0 0 + oneToSet read @@ -4871,6 +4881,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event MEMACCERR 0 0 + oneToClear read @@ -9203,6 +9214,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event END 0 0 + oneToSet read @@ -9230,6 +9242,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event RESOLVED 1 1 + oneToSet read @@ -9257,6 +9270,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event NOTRESOLVED 2 2 + oneToSet read @@ -9284,6 +9298,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event ERROR 3 3 + oneToSet read @@ -9321,6 +9336,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event END 0 0 + oneToClear read @@ -9348,6 +9364,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event RESOLVED 1 1 + oneToClear read @@ -9375,6 +9392,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event NOTRESOLVED 2 2 + oneToClear read @@ -9402,6 +9420,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event ERROR 3 3 + oneToClear read @@ -9895,6 +9914,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event END 1 1 + oneToSet read @@ -9922,6 +9942,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event ERROR 2 2 + oneToSet read @@ -9959,6 +9980,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event END 1 1 + oneToClear read @@ -9986,6 +10008,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event ERROR 2 2 + oneToClear read @@ -10692,6 +10715,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event END 0 0 + oneToSet read @@ -10719,6 +10743,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event ERROR 1 1 + oneToSet read @@ -10756,6 +10781,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event END 0 0 + oneToClear read @@ -10783,6 +10809,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event ERROR 1 1 + oneToClear read @@ -10926,6 +10953,71 @@ POSSIBILITY OF SUCH DAMAGE. + + CSAA + Channel sounding access address scoring algorithm + ECB_CSAA + read-write + 0x53C + + REFLECTOR + Selected Channel Sounding Access Address used in the CS SYNC from Reflector to Initiator + 0x000 + read-only + 0x00000000 + 0x20 + + + PN + 0 + 31 + + + + + INITIATOR + Selected Channel Sounding Access Address used in the CS SYNC from Initiator to Reflector + 0x004 + read-only + 0x00000000 + 0x20 + + + PN + 0 + 31 + + + + + MODE + Operation modes + 0x008 + read-write + 0x00000000 + 0x20 + + + BITREVERSE + Reverse the endianness on bit level for the ECB output, INITIATOR, and REFLECTOR registers + 0 + 0 + + + Default + Default endianness + 0x0 + + + Reversed + Reversed endianness + 0x1 + + + + + + @@ -11222,6 +11314,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[16] 16 16 + oneToSet read @@ -11249,6 +11342,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[17] 17 17 + oneToSet read @@ -11276,6 +11370,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[18] 18 18 + oneToSet read @@ -11303,6 +11398,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[19] 19 19 + oneToSet read @@ -11330,6 +11426,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[20] 20 20 + oneToSet read @@ -11357,6 +11454,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[21] 21 21 + oneToSet read @@ -11384,6 +11482,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[22] 22 22 + oneToSet read @@ -11421,6 +11520,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[16] 16 16 + oneToClear read @@ -11448,6 +11548,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[17] 17 17 + oneToClear read @@ -11475,6 +11576,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[18] 18 18 + oneToClear read @@ -11502,6 +11604,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[19] 19 19 + oneToClear read @@ -11529,6 +11632,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[20] 20 20 + oneToClear read @@ -11556,6 +11660,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[21] 21 21 + oneToClear read @@ -11583,6 +11688,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[22] 22 22 + oneToClear read @@ -13355,6 +13461,29 @@ POSSIBILITY OF SUCH DAMAGE. + + TASKS_CLRWRITEBUF + Clear internal write-buffer + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_CLRWRITEBUF + Clear internal write-buffer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + TASKS_COMMITWRITEBUF Commits the data stored in internal write-buffer to RRAM @@ -13411,6 +13540,39 @@ POSSIBILITY OF SUCH DAMAGE. + + SUBSCRIBE_CLRWRITEBUF + Subscribe configuration for task CLRWRITEBUF + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLRWRITEBUF will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + SUBSCRIBE_COMMITWRITEBUF Subscribe configuration for task COMMITWRITEBUF @@ -13684,6 +13846,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event WOKENUP 0 0 + oneToSet read @@ -13711,6 +13874,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event READY 1 1 + oneToSet read @@ -13738,6 +13902,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event READYNEXT 2 2 + oneToSet read @@ -13765,6 +13930,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event ACCESSERROR 3 3 + oneToSet read @@ -13802,6 +13968,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event WOKENUP 0 0 + oneToClear read @@ -13829,6 +13996,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event READY 1 1 + oneToClear read @@ -13856,6 +14024,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event READYNEXT 2 2 + oneToClear read @@ -13883,6 +14052,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event ACCESSERROR 3 3 + oneToClear read @@ -14284,7 +14454,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x540 ERASEALL - Register for erasing whole RRAM main block, that includes the SICR and the UICR + Erase RRAM, including UICR All information in SICR, including keys, are also erased 0x000 read-write 0x00000000 @@ -14292,7 +14462,7 @@ POSSIBILITY OF SUCH DAMAGE. ERASE - Erase whole RRAM main block + Erase RRAM 0 0 @@ -14610,6 +14780,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event RXREADY 0 0 + oneToSet read @@ -14637,6 +14808,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TXDONE 1 1 + oneToSet read @@ -14674,6 +14846,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event RXREADY 0 0 + oneToClear read @@ -14701,6 +14874,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TXDONE 1 1 + oneToClear read @@ -15948,6 +16122,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[0] 16 16 + oneToSet read @@ -15975,6 +16150,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[1] 17 17 + oneToSet read @@ -16002,6 +16178,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[2] 18 18 + oneToSet read @@ -16029,6 +16206,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[3] 19 19 + oneToSet read @@ -16056,6 +16234,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[4] 20 20 + oneToSet read @@ -16083,6 +16262,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[5] 21 21 + oneToSet read @@ -16110,6 +16290,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[6] 22 22 + oneToSet read @@ -16137,6 +16318,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[7] 23 23 + oneToSet read @@ -16174,6 +16356,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[0] 16 16 + oneToClear read @@ -16201,6 +16384,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[1] 17 17 + oneToClear read @@ -16228,6 +16412,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[2] 18 18 + oneToClear read @@ -16255,6 +16440,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[3] 19 19 + oneToClear read @@ -16282,6 +16468,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[4] 20 20 + oneToClear read @@ -16309,6 +16496,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[5] 21 21 + oneToClear read @@ -16336,6 +16524,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[6] 22 22 + oneToClear read @@ -16363,6 +16552,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[7] 23 23 + oneToClear read @@ -16990,6 +17180,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[0] 0 0 + oneToSet read @@ -17017,6 +17208,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[1] 1 1 + oneToSet read @@ -17044,6 +17236,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[2] 2 2 + oneToSet read @@ -17071,6 +17264,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[3] 3 3 + oneToSet read @@ -17098,6 +17292,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[4] 4 4 + oneToSet read @@ -17125,6 +17320,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[5] 5 5 + oneToSet read @@ -17152,6 +17348,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[6] 6 6 + oneToSet read @@ -17179,6 +17376,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[7] 7 7 + oneToSet read @@ -17206,6 +17404,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[8] 8 8 + oneToSet read @@ -17233,6 +17432,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[9] 9 9 + oneToSet read @@ -17260,6 +17460,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[10] 10 10 + oneToSet read @@ -17287,6 +17488,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[11] 11 11 + oneToSet read @@ -17314,6 +17516,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[12] 12 12 + oneToSet read @@ -17341,6 +17544,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[13] 13 13 + oneToSet read @@ -17368,6 +17572,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[14] 14 14 + oneToSet read @@ -17395,6 +17600,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TRIGGERED[15] 15 15 + oneToSet read @@ -17432,6 +17638,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[0] 0 0 + oneToClear read @@ -17459,6 +17666,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[1] 1 1 + oneToClear read @@ -17486,6 +17694,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[2] 2 2 + oneToClear read @@ -17513,6 +17722,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[3] 3 3 + oneToClear read @@ -17540,6 +17750,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[4] 4 4 + oneToClear read @@ -17567,6 +17778,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[5] 5 5 + oneToClear read @@ -17594,6 +17806,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[6] 6 6 + oneToClear read @@ -17621,6 +17834,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[7] 7 7 + oneToClear read @@ -17648,6 +17862,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[8] 8 8 + oneToClear read @@ -17675,6 +17890,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[9] 9 9 + oneToClear read @@ -17702,6 +17918,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[10] 10 10 + oneToClear read @@ -17729,6 +17946,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[11] 11 11 + oneToClear read @@ -17756,6 +17974,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[12] 12 12 + oneToClear read @@ -17783,6 +18002,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[13] 13 13 + oneToClear read @@ -17810,6 +18030,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[14] 14 14 + oneToClear read @@ -17837,6 +18058,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TRIGGERED[15] 15 15 + oneToClear read @@ -18054,6 +18276,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CRYPTOMASTER 0 0 + oneToSet read @@ -18081,6 +18304,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event RNG 1 1 + oneToSet read @@ -18108,6 +18332,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PKEIKG 2 2 + oneToSet read @@ -18145,6 +18370,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event CRYPTOMASTER 0 0 + oneToClear read @@ -18172,6 +18398,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event RNG 1 1 + oneToClear read @@ -18199,6 +18426,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event PKEIKG 2 2 + oneToClear read @@ -18857,16 +19085,16 @@ POSSIBILITY OF SUCH DAMAGE. - TASKS_SOFTRESET - Reset all public registers, but with these exceptions: DMA registers and EVENT/INTEN/SUBSCRIBE/PUBLISH registers. Only to be used in DISABLED state. - 0x0A4 + TASKS_AUXDATADMASTART + Start DMA transaction of acquisition + 0x038 write-only 0x00000000 0x20 - TASKS_SOFTRESET - Reset all public registers, but with these exceptions: DMA registers and EVENT/INTEN/SUBSCRIBE/PUBLISH registers. Only to be used in DISABLED state. + TASKS_AUXDATADMASTART + Start DMA transaction of acquisition 0 0 @@ -18880,32 +19108,68 @@ POSSIBILITY OF SUCH DAMAGE. - SUBSCRIBE_TXEN - Subscribe configuration for task TXEN - 0x100 - read-write + TASKS_AUXDATADMASTOP + Stop ongoing DMA transaction of acquisition + 0x03C + write-only 0x00000000 0x20 - CHIDX - DPPI channel that task TXEN will subscribe to + TASKS_AUXDATADMASTOP + Stop ongoing DMA transaction of acquisition 0 - 7 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + TASKS_PLLEN + Enable RADIO in PLL mode (standby for either TX or RX) + 0x06C + write-only + 0x00000000 + 0x20 + - EN - 31 - 31 + TASKS_PLLEN + Enable RADIO in PLL mode (standby for either TX or RX) + 0 + 0 - Disabled - Disable subscription - 0x0 + Trigger + Trigger task + 0x1 + + + + + + TASKS_CSTONESSTART + Start tone processing for channel sounding + 0x0A0 + write-only + 0x00000000 + 0x20 + + + TASKS_CSTONESSTART + Start tone processing for channel sounding + 0 + 0 + - Enabled - Enable subscription + Trigger + Trigger task 0x1 @@ -18913,16 +19177,72 @@ POSSIBILITY OF SUCH DAMAGE. - SUBSCRIBE_RXEN - Subscribe configuration for task RXEN - 0x104 + TASKS_SOFTRESET + Reset all public registers, but with these exceptions: DMA registers and EVENT/INTEN/SUBSCRIBE/PUBLISH registers. Only to be used in DISABLED state. + 0x0A4 + write-only + 0x00000000 + 0x20 + + + TASKS_SOFTRESET + Reset all public registers, but with these exceptions: DMA registers and EVENT/INTEN/SUBSCRIBE/PUBLISH registers. Only to be used in DISABLED state. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_TXEN + Subscribe configuration for task TXEN + 0x100 read-write 0x00000000 0x20 CHIDX - DPPI channel that task RXEN will subscribe to + DPPI channel that task TXEN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RXEN + Subscribe configuration for task RXEN + 0x104 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RXEN will subscribe to 0 7 @@ -19275,6 +19595,138 @@ POSSIBILITY OF SUCH DAMAGE. + + SUBSCRIBE_AUXDATADMASTART + Subscribe configuration for task AUXDATADMASTART + 0x138 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task AUXDATADMASTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_AUXDATADMASTOP + Subscribe configuration for task AUXDATADMASTOP + 0x13C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task AUXDATADMASTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PLLEN + Subscribe configuration for task PLLEN + 0x16C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task PLLEN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CSTONESSTART + Subscribe configuration for task CSTONESSTART + 0x1A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CSTONESSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + SUBSCRIBE_SOFTRESET Subscribe configuration for task SOFTRESET @@ -19953,32 +20405,55 @@ POSSIBILITY OF SUCH DAMAGE. - PUBLISH_READY - Publish configuration for event READY - 0x300 + EVENTS_PLLREADY + PLL has settled and RADIO is ready to be enabled in either TX or RX mode + 0x2B0 read-write 0x00000000 0x20 - CHIDX - DPPI channel that event READY will publish to + EVENTS_PLLREADY + PLL has settled and RADIO is ready to be enabled in either TX or RX mode 0 - 7 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + EVENTS_RXADDRESS + Address received + 0x2BC + read-write + 0x00000000 + 0x20 + - EN - 31 - 31 + EVENTS_RXADDRESS + Address received + 0 + 0 - Disabled - Disable publishing + NotGenerated + Event not generated 0x0 - Enabled - Enable publishing + Generated + Event generated 0x1 @@ -19986,16 +20461,72 @@ POSSIBILITY OF SUCH DAMAGE. - PUBLISH_TXREADY - Publish configuration for event TXREADY - 0x304 + EVENTS_AUXDATADMAEND + AUXDATA DMA end + 0x2C0 + read-write + 0x00000000 + 0x20 + + + EVENTS_AUXDATADMAEND + AUXDATA DMA end + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CSTONESEND + The channel sounding tone processing is complete + 0x2C8 + read-write + 0x00000000 + 0x20 + + + EVENTS_CSTONESEND + The channel sounding tone processing is complete + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x300 read-write 0x00000000 0x20 CHIDX - DPPI channel that event TXREADY will publish to + DPPI channel that event READY will publish to 0 7 @@ -20019,16 +20550,16 @@ POSSIBILITY OF SUCH DAMAGE. - PUBLISH_RXREADY - Publish configuration for event RXREADY - 0x308 + PUBLISH_TXREADY + Publish configuration for event TXREADY + 0x304 read-write 0x00000000 0x20 CHIDX - DPPI channel that event RXREADY will publish to + DPPI channel that event TXREADY will publish to 0 7 @@ -20052,16 +20583,49 @@ POSSIBILITY OF SUCH DAMAGE. - PUBLISH_ADDRESS - Publish configuration for event ADDRESS - 0x30C + PUBLISH_RXREADY + Publish configuration for event RXREADY + 0x308 read-write 0x00000000 0x20 CHIDX - DPPI channel that event ADDRESS will publish to + DPPI channel that event RXREADY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ADDRESS + Publish configuration for event ADDRESS + 0x30C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ADDRESS will publish to 0 7 @@ -20711,6 +21275,138 @@ POSSIBILITY OF SUCH DAMAGE. + + PUBLISH_PLLREADY + Publish configuration for event PLLREADY + 0x3B0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event PLLREADY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXADDRESS + Publish configuration for event RXADDRESS + 0x3BC + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXADDRESS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_AUXDATADMAEND + Publish configuration for event AUXDATADMAEND + 0x3C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event AUXDATADMAEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CSTONESEND + Publish configuration for event CSTONESEND + 0x3C8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CSTONESEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + SHORTS Shortcuts between local events and tasks @@ -21040,6 +21736,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event READY 0 0 + oneToSet read @@ -21067,6 +21764,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TXREADY 1 1 + oneToSet read @@ -21094,6 +21792,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event RXREADY 2 2 + oneToSet read @@ -21121,6 +21820,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event ADDRESS 3 3 + oneToSet read @@ -21148,6 +21848,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event FRAMESTART 4 4 + oneToSet read @@ -21175,6 +21876,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PAYLOAD 5 5 + oneToSet read @@ -21202,6 +21904,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event END 6 6 + oneToSet read @@ -21229,6 +21932,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PHYEND 7 7 + oneToSet read @@ -21256,6 +21960,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DISABLED 8 8 + oneToSet read @@ -21283,6 +21988,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DEVMATCH 9 9 + oneToSet read @@ -21310,6 +22016,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DEVMISS 10 10 + oneToSet read @@ -21337,6 +22044,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CRCOK 11 11 + oneToSet read @@ -21364,6 +22072,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CRCERROR 12 12 + oneToSet read @@ -21391,6 +22100,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event BCMATCH 14 14 + oneToSet read @@ -21418,6 +22128,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event EDEND 15 15 + oneToSet read @@ -21445,6 +22156,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event EDSTOPPED 16 16 + oneToSet read @@ -21472,6 +22184,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CCAIDLE 17 17 + oneToSet read @@ -21499,6 +22212,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CCABUSY 18 18 + oneToSet read @@ -21526,6 +22240,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CCASTOPPED 19 19 + oneToSet read @@ -21553,6 +22268,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event RATEBOOST 20 20 + oneToSet read @@ -21580,6 +22296,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event MHRMATCH 21 21 + oneToSet read @@ -21607,6 +22324,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event SYNC 22 22 + oneToSet read @@ -21634,6 +22352,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CTEPRESENT 23 23 + oneToSet read @@ -21659,18 +22378,19 @@ POSSIBILITY OF SUCH DAMAGE. - INTENCLR00 - Disable interrupt - 0x490 + INTENSET01 + Enable interrupt + 0x48C read-write 0x00000000 0x20 - READY - Write '1' to disable interrupt for event READY - 0 - 0 + PLLREADY + Write '1' to enable interrupt for event PLLREADY + 12 + 12 + oneToSet read @@ -21687,17 +22407,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 - TXREADY - Write '1' to disable interrupt for event TXREADY - 1 - 1 + RXADDRESS + Write '1' to enable interrupt for event RXADDRESS + 15 + 15 + oneToSet read @@ -21714,17 +22435,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 - RXREADY - Write '1' to disable interrupt for event RXREADY - 2 - 2 + AUXDATADMAEND + Write '1' to enable interrupt for event AUXDATADMAEND + 16 + 16 + oneToSet read @@ -21741,17 +22463,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 - ADDRESS - Write '1' to disable interrupt for event ADDRESS - 3 - 3 + CSTONESEND + Write '1' to enable interrupt for event CSTONESEND + 18 + 18 + oneToSet read @@ -21768,17 +22491,28 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 + + + + INTENCLR00 + Disable interrupt + 0x490 + read-write + 0x00000000 + 0x20 + - FRAMESTART - Write '1' to disable interrupt for event FRAMESTART - 4 - 4 + READY + Write '1' to disable interrupt for event READY + 0 + 0 + oneToClear read @@ -21802,10 +22536,11 @@ POSSIBILITY OF SUCH DAMAGE. - PAYLOAD - Write '1' to disable interrupt for event PAYLOAD - 5 - 5 + TXREADY + Write '1' to disable interrupt for event TXREADY + 1 + 1 + oneToClear read @@ -21829,10 +22564,11 @@ POSSIBILITY OF SUCH DAMAGE. - END - Write '1' to disable interrupt for event END - 6 - 6 + RXREADY + Write '1' to disable interrupt for event RXREADY + 2 + 2 + oneToClear read @@ -21856,10 +22592,11 @@ POSSIBILITY OF SUCH DAMAGE. - PHYEND - Write '1' to disable interrupt for event PHYEND - 7 - 7 + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 3 + 3 + oneToClear read @@ -21883,10 +22620,11 @@ POSSIBILITY OF SUCH DAMAGE. - DISABLED - Write '1' to disable interrupt for event DISABLED - 8 - 8 + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 4 + 4 + oneToClear read @@ -21910,10 +22648,11 @@ POSSIBILITY OF SUCH DAMAGE. - DEVMATCH - Write '1' to disable interrupt for event DEVMATCH - 9 - 9 + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 5 + 5 + oneToClear read @@ -21937,10 +22676,11 @@ POSSIBILITY OF SUCH DAMAGE. - DEVMISS - Write '1' to disable interrupt for event DEVMISS - 10 - 10 + END + Write '1' to disable interrupt for event END + 6 + 6 + oneToClear read @@ -21964,10 +22704,11 @@ POSSIBILITY OF SUCH DAMAGE. - CRCOK - Write '1' to disable interrupt for event CRCOK - 11 - 11 + PHYEND + Write '1' to disable interrupt for event PHYEND + 7 + 7 + oneToClear read @@ -21991,10 +22732,11 @@ POSSIBILITY OF SUCH DAMAGE. - CRCERROR - Write '1' to disable interrupt for event CRCERROR - 12 - 12 + DISABLED + Write '1' to disable interrupt for event DISABLED + 8 + 8 + oneToClear read @@ -22018,10 +22760,11 @@ POSSIBILITY OF SUCH DAMAGE. - BCMATCH - Write '1' to disable interrupt for event BCMATCH - 14 - 14 + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 9 + 9 + oneToClear read @@ -22045,10 +22788,11 @@ POSSIBILITY OF SUCH DAMAGE. - EDEND - Write '1' to disable interrupt for event EDEND - 15 - 15 + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 10 + 10 + oneToClear read @@ -22072,10 +22816,11 @@ POSSIBILITY OF SUCH DAMAGE. - EDSTOPPED - Write '1' to disable interrupt for event EDSTOPPED - 16 - 16 + CRCOK + Write '1' to disable interrupt for event CRCOK + 11 + 11 + oneToClear read @@ -22099,10 +22844,11 @@ POSSIBILITY OF SUCH DAMAGE. - CCAIDLE - Write '1' to disable interrupt for event CCAIDLE - 17 - 17 + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 12 + 12 + oneToClear read @@ -22126,10 +22872,11 @@ POSSIBILITY OF SUCH DAMAGE. - CCABUSY - Write '1' to disable interrupt for event CCABUSY - 18 - 18 + BCMATCH + Write '1' to disable interrupt for event BCMATCH + 14 + 14 + oneToClear read @@ -22153,10 +22900,11 @@ POSSIBILITY OF SUCH DAMAGE. - CCASTOPPED - Write '1' to disable interrupt for event CCASTOPPED - 19 - 19 + EDEND + Write '1' to disable interrupt for event EDEND + 15 + 15 + oneToClear read @@ -22180,10 +22928,11 @@ POSSIBILITY OF SUCH DAMAGE. - RATEBOOST - Write '1' to disable interrupt for event RATEBOOST - 20 - 20 + EDSTOPPED + Write '1' to disable interrupt for event EDSTOPPED + 16 + 16 + oneToClear read @@ -22207,10 +22956,11 @@ POSSIBILITY OF SUCH DAMAGE. - MHRMATCH - Write '1' to disable interrupt for event MHRMATCH - 21 - 21 + CCAIDLE + Write '1' to disable interrupt for event CCAIDLE + 17 + 17 + oneToClear read @@ -22234,10 +22984,11 @@ POSSIBILITY OF SUCH DAMAGE. - SYNC - Write '1' to disable interrupt for event SYNC - 22 - 22 + CCABUSY + Write '1' to disable interrupt for event CCABUSY + 18 + 18 + oneToClear read @@ -22261,10 +23012,11 @@ POSSIBILITY OF SUCH DAMAGE. - CTEPRESENT - Write '1' to disable interrupt for event CTEPRESENT - 23 - 23 + CCASTOPPED + Write '1' to disable interrupt for event CCASTOPPED + 19 + 19 + oneToClear read @@ -22287,21 +23039,12 @@ POSSIBILITY OF SUCH DAMAGE. - - - - INTENSET10 - Enable interrupt - 0x4A8 - read-write - 0x00000000 - 0x20 - - READY - Write '1' to enable interrupt for event READY - 0 - 0 + RATEBOOST + Write '1' to disable interrupt for event RATEBOOST + 20 + 20 + oneToClear read @@ -22318,17 +23061,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Set - Enable + Clear + Disable 0x1 - TXREADY - Write '1' to enable interrupt for event TXREADY - 1 - 1 + MHRMATCH + Write '1' to disable interrupt for event MHRMATCH + 21 + 21 + oneToClear read @@ -22345,17 +23089,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Set - Enable + Clear + Disable 0x1 - RXREADY - Write '1' to enable interrupt for event RXREADY - 2 - 2 + SYNC + Write '1' to disable interrupt for event SYNC + 22 + 22 + oneToClear read @@ -22372,17 +23117,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Set - Enable + Clear + Disable 0x1 - ADDRESS - Write '1' to enable interrupt for event ADDRESS - 3 - 3 + CTEPRESENT + Write '1' to disable interrupt for event CTEPRESENT + 23 + 23 + oneToClear read @@ -22399,17 +23145,28 @@ POSSIBILITY OF SUCH DAMAGE. write - Set - Enable + Clear + Disable 0x1 + + + + INTENCLR01 + Disable interrupt + 0x494 + read-write + 0x00000000 + 0x20 + - FRAMESTART - Write '1' to enable interrupt for event FRAMESTART - 4 - 4 + PLLREADY + Write '1' to disable interrupt for event PLLREADY + 12 + 12 + oneToClear read @@ -22426,17 +23183,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Set - Enable + Clear + Disable 0x1 - PAYLOAD - Write '1' to enable interrupt for event PAYLOAD - 5 - 5 + RXADDRESS + Write '1' to disable interrupt for event RXADDRESS + 15 + 15 + oneToClear read @@ -22453,17 +23211,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Set - Enable + Clear + Disable 0x1 - END - Write '1' to enable interrupt for event END - 6 - 6 + AUXDATADMAEND + Write '1' to disable interrupt for event AUXDATADMAEND + 16 + 16 + oneToClear read @@ -22480,17 +23239,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Set - Enable + Clear + Disable 0x1 - PHYEND - Write '1' to enable interrupt for event PHYEND - 7 - 7 + CSTONESEND + Write '1' to disable interrupt for event CSTONESEND + 18 + 18 + oneToClear read @@ -22507,17 +23267,28 @@ POSSIBILITY OF SUCH DAMAGE. write - Set - Enable + Clear + Disable 0x1 + + + + INTENSET10 + Enable interrupt + 0x4A8 + read-write + 0x00000000 + 0x20 + - DISABLED - Write '1' to enable interrupt for event DISABLED - 8 - 8 + READY + Write '1' to enable interrupt for event READY + 0 + 0 + oneToSet read @@ -22541,10 +23312,11 @@ POSSIBILITY OF SUCH DAMAGE. - DEVMATCH - Write '1' to enable interrupt for event DEVMATCH - 9 - 9 + TXREADY + Write '1' to enable interrupt for event TXREADY + 1 + 1 + oneToSet read @@ -22568,10 +23340,11 @@ POSSIBILITY OF SUCH DAMAGE. - DEVMISS - Write '1' to enable interrupt for event DEVMISS - 10 - 10 + RXREADY + Write '1' to enable interrupt for event RXREADY + 2 + 2 + oneToSet read @@ -22595,10 +23368,11 @@ POSSIBILITY OF SUCH DAMAGE. - CRCOK - Write '1' to enable interrupt for event CRCOK - 11 - 11 + ADDRESS + Write '1' to enable interrupt for event ADDRESS + 3 + 3 + oneToSet read @@ -22622,10 +23396,11 @@ POSSIBILITY OF SUCH DAMAGE. - CRCERROR - Write '1' to enable interrupt for event CRCERROR - 12 - 12 + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 4 + 4 + oneToSet read @@ -22649,10 +23424,11 @@ POSSIBILITY OF SUCH DAMAGE. - BCMATCH - Write '1' to enable interrupt for event BCMATCH - 14 - 14 + PAYLOAD + Write '1' to enable interrupt for event PAYLOAD + 5 + 5 + oneToSet read @@ -22676,10 +23452,11 @@ POSSIBILITY OF SUCH DAMAGE. - EDEND - Write '1' to enable interrupt for event EDEND - 15 - 15 + END + Write '1' to enable interrupt for event END + 6 + 6 + oneToSet read @@ -22703,10 +23480,11 @@ POSSIBILITY OF SUCH DAMAGE. - EDSTOPPED - Write '1' to enable interrupt for event EDSTOPPED - 16 - 16 + PHYEND + Write '1' to enable interrupt for event PHYEND + 7 + 7 + oneToSet read @@ -22730,10 +23508,11 @@ POSSIBILITY OF SUCH DAMAGE. - CCAIDLE - Write '1' to enable interrupt for event CCAIDLE - 17 - 17 + DISABLED + Write '1' to enable interrupt for event DISABLED + 8 + 8 + oneToSet read @@ -22757,10 +23536,11 @@ POSSIBILITY OF SUCH DAMAGE. - CCABUSY - Write '1' to enable interrupt for event CCABUSY - 18 - 18 + DEVMATCH + Write '1' to enable interrupt for event DEVMATCH + 9 + 9 + oneToSet read @@ -22784,10 +23564,11 @@ POSSIBILITY OF SUCH DAMAGE. - CCASTOPPED - Write '1' to enable interrupt for event CCASTOPPED - 19 - 19 + DEVMISS + Write '1' to enable interrupt for event DEVMISS + 10 + 10 + oneToSet read @@ -22811,10 +23592,11 @@ POSSIBILITY OF SUCH DAMAGE. - RATEBOOST - Write '1' to enable interrupt for event RATEBOOST - 20 - 20 + CRCOK + Write '1' to enable interrupt for event CRCOK + 11 + 11 + oneToSet read @@ -22838,10 +23620,11 @@ POSSIBILITY OF SUCH DAMAGE. - MHRMATCH - Write '1' to enable interrupt for event MHRMATCH - 21 - 21 + CRCERROR + Write '1' to enable interrupt for event CRCERROR + 12 + 12 + oneToSet read @@ -22865,10 +23648,11 @@ POSSIBILITY OF SUCH DAMAGE. - SYNC - Write '1' to enable interrupt for event SYNC - 22 - 22 + BCMATCH + Write '1' to enable interrupt for event BCMATCH + 14 + 14 + oneToSet read @@ -22892,10 +23676,11 @@ POSSIBILITY OF SUCH DAMAGE. - CTEPRESENT - Write '1' to enable interrupt for event CTEPRESENT - 23 - 23 + EDEND + Write '1' to enable interrupt for event EDEND + 15 + 15 + oneToSet read @@ -22918,21 +23703,12 @@ POSSIBILITY OF SUCH DAMAGE. - - - - INTENCLR10 - Disable interrupt - 0x4B0 - read-write - 0x00000000 - 0x20 - - READY - Write '1' to disable interrupt for event READY - 0 - 0 + EDSTOPPED + Write '1' to enable interrupt for event EDSTOPPED + 16 + 16 + oneToSet read @@ -22949,17 +23725,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 - TXREADY - Write '1' to disable interrupt for event TXREADY - 1 - 1 + CCAIDLE + Write '1' to enable interrupt for event CCAIDLE + 17 + 17 + oneToSet read @@ -22976,17 +23753,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 - RXREADY - Write '1' to disable interrupt for event RXREADY - 2 - 2 + CCABUSY + Write '1' to enable interrupt for event CCABUSY + 18 + 18 + oneToSet read @@ -23003,17 +23781,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 - ADDRESS - Write '1' to disable interrupt for event ADDRESS - 3 - 3 + CCASTOPPED + Write '1' to enable interrupt for event CCASTOPPED + 19 + 19 + oneToSet read @@ -23030,17 +23809,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 - FRAMESTART - Write '1' to disable interrupt for event FRAMESTART - 4 - 4 + RATEBOOST + Write '1' to enable interrupt for event RATEBOOST + 20 + 20 + oneToSet read @@ -23057,17 +23837,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 - PAYLOAD - Write '1' to disable interrupt for event PAYLOAD - 5 - 5 + MHRMATCH + Write '1' to enable interrupt for event MHRMATCH + 21 + 21 + oneToSet read @@ -23084,17 +23865,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 - END - Write '1' to disable interrupt for event END - 6 - 6 + SYNC + Write '1' to enable interrupt for event SYNC + 22 + 22 + oneToSet read @@ -23111,17 +23893,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 - PHYEND - Write '1' to disable interrupt for event PHYEND - 7 - 7 + CTEPRESENT + Write '1' to enable interrupt for event CTEPRESENT + 23 + 23 + oneToSet read @@ -23138,17 +23921,28 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 + + + + INTENSET11 + Enable interrupt + 0x4AC + read-write + 0x00000000 + 0x20 + - DISABLED - Write '1' to disable interrupt for event DISABLED - 8 - 8 + PLLREADY + Write '1' to enable interrupt for event PLLREADY + 12 + 12 + oneToSet read @@ -23165,17 +23959,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 - DEVMATCH - Write '1' to disable interrupt for event DEVMATCH - 9 - 9 + RXADDRESS + Write '1' to enable interrupt for event RXADDRESS + 15 + 15 + oneToSet read @@ -23192,17 +23987,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 - DEVMISS - Write '1' to disable interrupt for event DEVMISS - 10 - 10 + AUXDATADMAEND + Write '1' to enable interrupt for event AUXDATADMAEND + 16 + 16 + oneToSet read @@ -23219,17 +24015,18 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 - CRCOK - Write '1' to disable interrupt for event CRCOK - 11 - 11 + CSTONESEND + Write '1' to enable interrupt for event CSTONESEND + 18 + 18 + oneToSet read @@ -23246,17 +24043,364 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 + + + + INTENCLR10 + Disable interrupt + 0x4B0 + read-write + 0x00000000 + 0x20 + - CRCERROR - Write '1' to disable interrupt for event CRCERROR - 12 - 12 + READY + Write '1' to disable interrupt for event READY + 0 + 0 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXREADY + Write '1' to disable interrupt for event TXREADY + 1 + 1 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXREADY + Write '1' to disable interrupt for event RXREADY + 2 + 2 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 3 + 3 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 4 + 4 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 5 + 5 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PHYEND + Write '1' to disable interrupt for event PHYEND + 7 + 7 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DISABLED + Write '1' to disable interrupt for event DISABLED + 8 + 8 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 9 + 9 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 10 + 10 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CRCOK + Write '1' to disable interrupt for event CRCOK + 11 + 11 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 12 + 12 + oneToClear read @@ -23284,6 +24428,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event BCMATCH 14 14 + oneToClear read @@ -23311,6 +24456,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event EDEND 15 15 + oneToClear read @@ -23338,6 +24484,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event EDSTOPPED 16 16 + oneToClear read @@ -23365,6 +24512,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event CCAIDLE 17 17 + oneToClear read @@ -23392,6 +24540,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event CCABUSY 18 18 + oneToClear read @@ -23419,6 +24568,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event CCASTOPPED 19 19 + oneToClear read @@ -23446,6 +24596,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event RATEBOOST 20 20 + oneToClear read @@ -23473,6 +24624,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event MHRMATCH 21 21 + oneToClear read @@ -23500,6 +24652,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event SYNC 22 22 + oneToClear read @@ -23527,6 +24680,129 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event CTEPRESENT 23 23 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTENCLR11 + Disable interrupt + 0x4B4 + read-write + 0x00000000 + 0x20 + + + PLLREADY + Write '1' to disable interrupt for event PLLREADY + 12 + 12 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXADDRESS + Write '1' to disable interrupt for event RXADDRESS + 15 + 15 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + AUXDATADMAEND + Write '1' to disable interrupt for event AUXDATADMAEND + 16 + 16 + oneToClear + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CSTONESEND + Write '1' to disable interrupt for event CSTONESEND + 18 + 18 + oneToClear read @@ -23614,6 +24890,40 @@ POSSIBILITY OF SUCH DAMAGE. + + PHYENDTXDELAY + Configurable delay of PHYEND event for TX + 0x518 + read-write + 0x00000421 + 0x20 + + + RATE4M + For modes with 4 Mbps on-air bit rate, unit is 2 bit periods (Nrf_4Mbit0_5 and Nrf_4Mbit0_25 modes) + 0 + 2 + + + RATE2M + For modes with 2 Mbps on-air bit rate, unit is 1 bit period (Nrf_2Mbit, Ble_2Mbit, and Ieee802154_250Kbit modes) + 4 + 6 + + + RATE1M + For modes with 1 Mbps on-air bit rate, unit is 1/2 bit period (Nrf_1Mbit, Ble_1Mbit, Ble_LR125Kbit, and Ble_LR500Kbit modes) + 8 + 10 + + + RATE250K + For modes with 250 kbps on-air bit rate, unit is 1/8 bit period (Nrf_250Kbit mode) + 12 + 14 + + + STATE Current radio state @@ -23805,6 +25115,141 @@ POSSIBILITY OF SUCH DAMAGE. + + AUXDATA + Unspecified + RADIO_AUXDATA + read-write + 0x548 + + 0x2 + 0x4 + CNF[%s] + Description collection: AUXDATA configuration + 0x000 + read-write + 0x00000000 + 0x20 + + + ACQMODE + Acquisition mode (data from RADIO written to memory) + 0 + 4 + + + Rtt + Baseband Channel Sounding RTT Data + 0x07 + + + + + DIR + Data acquisition or injection + 31 + 31 + + + Acq + Peripheral to memory + 0x0 + + + Inj + Memory to peripheral + 0x1 + + + + + + + + 2 + 0x010 + AUXDATADMA[%s] + Unspecified + RADIO_AUXDATADMA + read-write + 0x550 + + ENABLE + Description cluster: Enable or disable data acquisition + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable data acquisition + 0 + 0 + + + Disabled + Data acquisition is disabled + 0x0 + + + Enabled + Data acquisition is enabled + 0x1 + + + + + + + PTR + Description cluster: ACQ DMA pointer + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of 32-bit words to transfer + 0x008 + read-write + 0x00000040 + 0x20 + + + MAXCNT + Maximum number of 32-bit words to transfer + 0 + 13 + + + + + AMOUNT + Description cluster: Number of 32-bit words transferred in the last transaction + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of 32-bit words transferred in the last transaction + 0 + 13 + + + + TIMING Timing @@ -24055,6 +25500,75 @@ POSSIBILITY OF SUCH DAMAGE. + + RXGAIN + Unspecified + RADIO_RXGAIN + read-write + 0x7D0 + + CONFIG + Override configuration of receiver gain control loop + 0x004 + read-write + 0x801230C3 + 0x20 + + + AGCAAFOVERRIDE + Override value for AAF + 17 + 20 + + + AGCMIXOVERRIDE + Override value for MIX + 21 + 21 + + + AGCLNAOVERRIDE + Override value for LNA + 22 + 23 + + + AGCOVERRIDEGAIN + Enable AGC override + 28 + 28 + + + NoOverride + AGC takes control over all gains + 0x0 + + + Override + Manual control of AAF, MIX, and LNA gain settings + 0x1 + + + + + + + + FREQFINETUNE + Fine tuning of the RF frequency + 0x0804 + read-write + 0x00000000 + 0x20 + + + FREQFINETUNE + Twos-complement number for fine-tuning the frequency. The step size is 488.28125 Hz, giving a range from -1 MHz to (one step short of) +1 MHz. + 0 + 12 + + + FECONFIG Config register @@ -24083,6 +25597,50 @@ POSSIBILITY OF SUCH DAMAGE. + + CFO_STAT + Carrier freq. offset estimate + 0xB00 + read-only + 0x00000000 + 0x20 + + + SYNCOK + SYNC ok + 12 + 12 + + + SyncNotOK + Unspecified + 0x0 + + + SyncOk + Unspecified + 0x1 + + + + + + + DBCCORR + Correlator thresholds + 0xB40 + read-write + 0x1FFFFF90 + 0x20 + + + TH + Correlation threshold + 0 + 7 + + + DFEMODE Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) @@ -25812,50 +27370,6 @@ POSSIBILITY OF SUCH DAMAGE. - - FFOIN - Override value of FFO (Fractional Frequency Offset) if not to be based on the frequency estimate derived from CnAcc (autocorrelation of the scaled input signal) value - 0x00C - read-write - 0x00000000 - 0x20 - - - FFFIN - Units 62.5 ppb. Max range +/-100 ppm plus margin. - 0 - 11 - - - - - FFOSOURCE - Source of FFO - 0x010 - read-write - 0x00000001 - 0x20 - - - FFOSOURCE - Use external or internal FFOSOURCE - 0 - 0 - - - External - Use FFOIN - 0x0 - - - Internal - Calc FFO from CnAcc - 0x1 - - - - - FAEPEER FAEPEER (Frequency Actuation Error) of peer if known. Used during Mode 0 steps. @@ -25986,26 +27500,6 @@ POSSIBILITY OF SUCH DAMAGE. - - CNACC - Output of the autocorrelation of the accumulated IQ signal - 0x030 - read-only - 0x00000000 - 0x20 - - - CNACCI - 0 - 15 - - - CNACCQ - 16 - 31 - - - FFOEST FFO estimate @@ -26068,37 +27562,6 @@ POSSIBILITY OF SUCH DAMAGE. - - FINETUNENEXT - Number of full ADPLL finetune steps - 0x03C - read-only - 0x00000000 - 0x20 - - - FINETUNENEXT - Units of 488.28125 Hz - 0 - 12 - - - - - CFOPHASE - Cordic output of CnAcc - 0x040 - read-only - 0x00000000 - 0x20 - - - CFOPHASE - 0 - 15 - - - FREQOFFSET Frequency offset estimate @@ -26114,44 +27577,6 @@ POSSIBILITY OF SUCH DAMAGE. - - PCT11 - Mean magnitude and mean phase converted to IQ. IQ values limited to [-1024,1023]. - 0x048 - read-only - 0x00000000 - 0x20 - - - PCT11I - Inphase - 0 - 10 - - - PCT11Q - Quadrature - 11 - 21 - - - - - LFAENEXT - Quantization error between ADPLL frequency and the desired value of FFO * RF Frequency. Values limited to [-64,63] with units 7.6294 Hz. - 0x04C - read-only - 0x00000000 - 0x20 - - - LFAENEXT - Inphase - 0 - 6 - - - RTT @@ -27618,6 +29043,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event STARTED 0 0 + oneToSet read @@ -27645,6 +29071,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event STOPPED 1 1 + oneToSet read @@ -27672,6 +29099,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event END 2 2 + oneToSet read @@ -27699,6 +29127,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXEND 19 19 + oneToSet read @@ -27726,6 +29155,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXREADY 20 20 + oneToSet read @@ -27753,6 +29183,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXBUSERROR 21 21 + oneToSet read @@ -27780,6 +29211,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[0] 22 22 + oneToSet read @@ -27807,6 +29239,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[1] 23 23 + oneToSet read @@ -27834,6 +29267,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[2] 24 24 + oneToSet read @@ -27861,6 +29295,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[3] 25 25 + oneToSet read @@ -27888,6 +29323,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMATXEND 26 26 + oneToSet read @@ -27915,6 +29351,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMATXREADY 27 27 + oneToSet read @@ -27942,6 +29379,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMATXBUSERROR 28 28 + oneToSet read @@ -27979,6 +29417,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event STARTED 0 0 + oneToClear read @@ -28006,6 +29445,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event STOPPED 1 1 + oneToClear read @@ -28033,6 +29473,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event END 2 2 + oneToClear read @@ -28060,6 +29501,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXEND 19 19 + oneToClear read @@ -28087,6 +29529,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXREADY 20 20 + oneToClear read @@ -28114,6 +29557,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXBUSERROR 21 21 + oneToClear read @@ -28141,6 +29585,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[0] 22 22 + oneToClear read @@ -28168,6 +29613,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[1] 23 23 + oneToClear read @@ -28195,6 +29641,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[2] 24 24 + oneToClear read @@ -28222,6 +29669,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[3] 25 25 + oneToClear read @@ -28249,6 +29697,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMATXEND 26 26 + oneToClear read @@ -28276,6 +29725,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMATXREADY 27 27 + oneToClear read @@ -28303,6 +29753,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMATXBUSERROR 28 28 + oneToClear read @@ -30239,6 +31690,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event END 1 1 + oneToSet read @@ -30266,6 +31718,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event ACQUIRED 6 6 + oneToSet read @@ -30293,6 +31746,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXEND 19 19 + oneToSet read @@ -30320,6 +31774,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXREADY 20 20 + oneToSet read @@ -30347,6 +31802,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXBUSERROR 21 21 + oneToSet read @@ -30374,6 +31830,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[0] 22 22 + oneToSet read @@ -30401,6 +31858,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[1] 23 23 + oneToSet read @@ -30428,6 +31886,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[2] 24 24 + oneToSet read @@ -30455,6 +31914,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[3] 25 25 + oneToSet read @@ -30482,6 +31942,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMATXEND 26 26 + oneToSet read @@ -30509,6 +31970,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMATXREADY 27 27 + oneToSet read @@ -30536,6 +31998,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMATXBUSERROR 28 28 + oneToSet read @@ -30573,6 +32036,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event END 1 1 + oneToClear read @@ -30600,6 +32064,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event ACQUIRED 6 6 + oneToClear read @@ -30627,6 +32092,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXEND 19 19 + oneToClear read @@ -30654,6 +32120,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXREADY 20 20 + oneToClear read @@ -30681,6 +32148,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXBUSERROR 21 21 + oneToClear read @@ -30708,6 +32176,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[0] 22 22 + oneToClear read @@ -30735,6 +32204,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[1] 23 23 + oneToClear read @@ -30762,6 +32232,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[2] 24 24 + oneToClear read @@ -30789,6 +32260,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[3] 25 25 + oneToClear read @@ -30816,6 +32288,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMATXEND 26 26 + oneToClear read @@ -30843,6 +32316,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMATXREADY 27 27 + oneToClear read @@ -30870,6 +32344,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMATXBUSERROR 28 28 + oneToClear read @@ -32397,7 +33872,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x000 END - Generated after all MAXCNT bytes have been transferred + Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed. 0x000 read-write 0x00000000 @@ -32405,7 +33880,7 @@ POSSIBILITY OF SUCH DAMAGE. END - Generated after all MAXCNT bytes have been transferred + Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed. 0 0 @@ -32518,7 +33993,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x01C END - Generated after all MAXCNT bytes have been transferred + Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed. 0x000 read-write 0x00000000 @@ -32526,7 +34001,7 @@ POSSIBILITY OF SUCH DAMAGE. END - Generated after all MAXCNT bytes have been transferred + Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed. 0 0 @@ -33558,6 +35033,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event STOPPED 1 1 + oneToSet read @@ -33585,6 +35061,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event ERROR 5 5 + oneToSet read @@ -33612,6 +35089,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event SUSPENDED 10 10 + oneToSet read @@ -33639,6 +35117,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event LASTRX 13 13 + oneToSet read @@ -33666,6 +35145,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event LASTTX 14 14 + oneToSet read @@ -33693,6 +35173,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXEND 19 19 + oneToSet read @@ -33720,6 +35201,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXREADY 20 20 + oneToSet read @@ -33747,6 +35229,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXBUSERROR 21 21 + oneToSet read @@ -33774,6 +35257,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[0] 22 22 + oneToSet read @@ -33801,6 +35285,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[1] 23 23 + oneToSet read @@ -33828,6 +35313,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[2] 24 24 + oneToSet read @@ -33855,6 +35341,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[3] 25 25 + oneToSet read @@ -33882,6 +35369,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMATXEND 26 26 + oneToSet read @@ -33909,6 +35397,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMATXREADY 27 27 + oneToSet read @@ -33936,6 +35425,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMATXBUSERROR 28 28 + oneToSet read @@ -33973,6 +35463,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event STOPPED 1 1 + oneToClear read @@ -34000,6 +35491,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event ERROR 5 5 + oneToClear read @@ -34027,6 +35519,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event SUSPENDED 10 10 + oneToClear read @@ -34054,6 +35547,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event LASTRX 13 13 + oneToClear read @@ -34081,6 +35575,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event LASTTX 14 14 + oneToClear read @@ -34108,6 +35603,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXEND 19 19 + oneToClear read @@ -34135,6 +35631,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXREADY 20 20 + oneToClear read @@ -34162,6 +35659,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXBUSERROR 21 21 + oneToClear read @@ -34189,6 +35687,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[0] 22 22 + oneToClear read @@ -34216,6 +35715,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[1] 23 23 + oneToClear read @@ -34243,6 +35743,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[2] 24 24 + oneToClear read @@ -34270,6 +35771,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[3] 25 25 + oneToClear read @@ -34297,6 +35799,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMATXEND 26 26 + oneToClear read @@ -34324,6 +35827,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMATXREADY 27 27 + oneToClear read @@ -34351,6 +35855,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMATXBUSERROR 28 28 + oneToClear read @@ -34497,6 +36002,11 @@ POSSIBILITY OF SUCH DAMAGE. 400 kbps 0x06400000 + + K1000 + 1000 kbps + 0x0FF00000 + @@ -34794,7 +36304,7 @@ POSSIBILITY OF SUCH DAMAGE. ONESHOT_0 - Configure match filter 0 as one-shot or sticky + Configure match filter 0 as one-shot or continous 16 16 @@ -34812,7 +36322,7 @@ POSSIBILITY OF SUCH DAMAGE. ONESHOT_1 - Configure match filter 1 as one-shot or sticky + Configure match filter 1 as one-shot or continous 17 17 @@ -34830,7 +36340,7 @@ POSSIBILITY OF SUCH DAMAGE. ONESHOT_2 - Configure match filter 2 as one-shot or sticky + Configure match filter 2 as one-shot or continous 18 18 @@ -34848,7 +36358,7 @@ POSSIBILITY OF SUCH DAMAGE. ONESHOT_3 - Configure match filter 3 as one-shot or sticky + Configure match filter 3 as one-shot or continous 19 19 @@ -34880,7 +36390,7 @@ POSSIBILITY OF SUCH DAMAGE. DATA Data to look for 0 - 31 + 7 @@ -36616,6 +38126,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event STOPPED 1 1 + oneToSet read @@ -36643,6 +38154,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event ERROR 5 5 + oneToSet read @@ -36670,6 +38182,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event WRITE 15 15 + oneToSet read @@ -36697,6 +38210,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event READ 16 16 + oneToSet read @@ -36724,6 +38238,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXEND 19 19 + oneToSet read @@ -36751,6 +38266,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXREADY 20 20 + oneToSet read @@ -36778,6 +38294,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXBUSERROR 21 21 + oneToSet read @@ -36805,6 +38322,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[0] 22 22 + oneToSet read @@ -36832,6 +38350,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[1] 23 23 + oneToSet read @@ -36859,6 +38378,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[2] 24 24 + oneToSet read @@ -36886,6 +38406,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[3] 25 25 + oneToSet read @@ -36913,6 +38434,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMATXEND 26 26 + oneToSet read @@ -36940,6 +38462,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMATXREADY 27 27 + oneToSet read @@ -36967,6 +38490,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMATXBUSERROR 28 28 + oneToSet read @@ -37004,6 +38528,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event STOPPED 1 1 + oneToClear read @@ -37031,6 +38556,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event ERROR 5 5 + oneToClear read @@ -37058,6 +38584,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event WRITE 15 15 + oneToClear read @@ -37085,6 +38612,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event READ 16 16 + oneToClear read @@ -37112,6 +38640,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXEND 19 19 + oneToClear read @@ -37139,6 +38668,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXREADY 20 20 + oneToClear read @@ -37166,6 +38696,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXBUSERROR 21 21 + oneToClear read @@ -37193,6 +38724,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[0] 22 22 + oneToClear read @@ -37220,6 +38752,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[1] 23 23 + oneToClear read @@ -37247,6 +38780,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[2] 24 24 + oneToClear read @@ -37274,6 +38808,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[3] 25 25 + oneToClear read @@ -37301,6 +38836,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMATXEND 26 26 + oneToClear read @@ -37328,6 +38864,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMATXREADY 27 27 + oneToClear read @@ -37355,6 +38892,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMATXBUSERROR 28 28 + oneToClear read @@ -37672,7 +39210,7 @@ POSSIBILITY OF SUCH DAMAGE. RAM buffer start address 0x004 read-write - 0x00000000 + 0x20000000 0x20 @@ -37746,7 +39284,7 @@ POSSIBILITY OF SUCH DAMAGE. BUSERRORADDRESS Address of transaction that generated the last BUSERROR event. 0x020 - read-write + read-only 0x00000000 0x20 @@ -37948,7 +39486,7 @@ POSSIBILITY OF SUCH DAMAGE. RAM buffer start address 0x004 read-write - 0x00000000 + 0x20000000 0x20 @@ -38022,7 +39560,7 @@ POSSIBILITY OF SUCH DAMAGE. BUSERRORADDRESS Address of transaction that generated the last BUSERROR event. 0x020 - read-write + read-only 0x00000000 0x20 @@ -40033,6 +41571,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CTS 0 0 + oneToSet read @@ -40060,6 +41599,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event NCTS 1 1 + oneToSet read @@ -40087,6 +41627,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TXDRDY 3 3 + oneToSet read @@ -40114,6 +41655,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event RXDRDY 4 4 + oneToSet read @@ -40141,6 +41683,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event ERROR 5 5 + oneToSet read @@ -40168,6 +41711,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event RXTO 9 9 + oneToSet read @@ -40195,6 +41739,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TXSTOPPED 12 12 + oneToSet read @@ -40222,6 +41767,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXEND 19 19 + oneToSet read @@ -40249,6 +41795,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXREADY 20 20 + oneToSet read @@ -40276,6 +41823,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXBUSERROR 21 21 + oneToSet read @@ -40303,6 +41851,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[0] 22 22 + oneToSet read @@ -40330,6 +41879,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[1] 23 23 + oneToSet read @@ -40357,6 +41907,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[2] 24 24 + oneToSet read @@ -40384,6 +41935,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMARXMATCH[3] 25 25 + oneToSet read @@ -40411,6 +41963,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMATXEND 26 26 + oneToSet read @@ -40438,6 +41991,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMATXREADY 27 27 + oneToSet read @@ -40465,6 +42019,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DMATXBUSERROR 28 28 + oneToSet read @@ -40492,6 +42047,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event FRAMETIMEOUT 29 29 + oneToSet read @@ -40529,6 +42085,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event CTS 0 0 + oneToClear read @@ -40556,6 +42113,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event NCTS 1 1 + oneToClear read @@ -40583,6 +42141,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TXDRDY 3 3 + oneToClear read @@ -40610,6 +42169,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event RXDRDY 4 4 + oneToClear read @@ -40637,6 +42197,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event ERROR 5 5 + oneToClear read @@ -40664,6 +42225,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event RXTO 9 9 + oneToClear read @@ -40691,6 +42253,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TXSTOPPED 12 12 + oneToClear read @@ -40718,6 +42281,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXEND 19 19 + oneToClear read @@ -40745,6 +42309,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXREADY 20 20 + oneToClear read @@ -40772,6 +42337,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXBUSERROR 21 21 + oneToClear read @@ -40799,6 +42365,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[0] 22 22 + oneToClear read @@ -40826,6 +42393,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[1] 23 23 + oneToClear read @@ -40853,6 +42421,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[2] 24 24 + oneToClear read @@ -40880,6 +42449,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMARXMATCH[3] 25 25 + oneToClear read @@ -40907,6 +42477,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMATXEND 26 26 + oneToClear read @@ -40934,6 +42505,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMATXREADY 27 27 + oneToClear read @@ -40961,6 +42533,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DMATXBUSERROR 28 28 + oneToClear read @@ -40988,6 +42561,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event FRAMETIMEOUT 29 29 + oneToClear read @@ -43908,7 +45482,7 @@ POSSIBILITY OF SUCH DAMAGE. - 8 + 4 0x008 EVENTS_CH[%s] Peripheral events. @@ -44171,7 +45745,7 @@ POSSIBILITY OF SUCH DAMAGE. - 8 + 4 0x008 PUBLISH_CH[%s] Publish configuration for events @@ -44255,153 +45829,9 @@ POSSIBILITY OF SUCH DAMAGE. STARTED - Enable or disable interrupt for event STARTED - 0 - 0 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - END - Enable or disable interrupt for event END - 1 - 1 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - DONE - Enable or disable interrupt for event DONE - 2 - 2 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - RESULTDONE - Enable or disable interrupt for event RESULTDONE - 3 - 3 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - CALIBRATEDONE - Enable or disable interrupt for event CALIBRATEDONE - 4 - 4 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - STOPPED - Enable or disable interrupt for event STOPPED - 5 - 5 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - CH0LIMITH - Enable or disable interrupt for event CH0LIMITH - 6 - 6 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - CH0LIMITL - Enable or disable interrupt for event CH0LIMITL - 7 - 7 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - CH1LIMITH - Enable or disable interrupt for event CH1LIMITH - 8 - 8 + Enable or disable interrupt for event STARTED + 0 + 0 Disabled @@ -44416,10 +45846,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH1LIMITL - Enable or disable interrupt for event CH1LIMITL - 9 - 9 + END + Enable or disable interrupt for event END + 1 + 1 Disabled @@ -44434,10 +45864,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH2LIMITH - Enable or disable interrupt for event CH2LIMITH - 10 - 10 + DONE + Enable or disable interrupt for event DONE + 2 + 2 Disabled @@ -44452,10 +45882,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH2LIMITL - Enable or disable interrupt for event CH2LIMITL - 11 - 11 + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 Disabled @@ -44470,10 +45900,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH3LIMITH - Enable or disable interrupt for event CH3LIMITH - 12 - 12 + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 Disabled @@ -44488,10 +45918,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH3LIMITL - Enable or disable interrupt for event CH3LIMITL - 13 - 13 + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 Disabled @@ -44506,10 +45936,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH4LIMITH - Enable or disable interrupt for event CH4LIMITH - 14 - 14 + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 Disabled @@ -44524,10 +45954,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH4LIMITL - Enable or disable interrupt for event CH4LIMITL - 15 - 15 + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 Disabled @@ -44542,10 +45972,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH5LIMITH - Enable or disable interrupt for event CH5LIMITH - 16 - 16 + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 Disabled @@ -44560,10 +45990,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH5LIMITL - Enable or disable interrupt for event CH5LIMITL - 17 - 17 + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 Disabled @@ -44578,10 +46008,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH6LIMITH - Enable or disable interrupt for event CH6LIMITH - 18 - 18 + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 Disabled @@ -44596,10 +46026,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH6LIMITL - Enable or disable interrupt for event CH6LIMITL - 19 - 19 + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 Disabled @@ -44614,10 +46044,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH7LIMITH - Enable or disable interrupt for event CH7LIMITH - 20 - 20 + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 Disabled @@ -44632,10 +46062,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH7LIMITL - Enable or disable interrupt for event CH7LIMITL - 21 - 21 + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 Disabled @@ -44664,6 +46094,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event STARTED 0 0 + oneToSet read @@ -44691,6 +46122,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event END 1 1 + oneToSet read @@ -44718,6 +46150,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DONE 2 2 + oneToSet read @@ -44745,6 +46178,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event RESULTDONE 3 3 + oneToSet read @@ -44772,6 +46206,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CALIBRATEDONE 4 4 + oneToSet read @@ -44799,6 +46234,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event STOPPED 5 5 + oneToSet read @@ -44826,6 +46262,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CH0LIMITH 6 6 + oneToSet read @@ -44853,6 +46290,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CH0LIMITL 7 7 + oneToSet read @@ -44880,6 +46318,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CH1LIMITH 8 8 + oneToSet read @@ -44907,6 +46346,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CH1LIMITL 9 9 + oneToSet read @@ -44934,6 +46374,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CH2LIMITH 10 10 + oneToSet read @@ -44961,6 +46402,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CH2LIMITL 11 11 + oneToSet read @@ -44988,6 +46430,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CH3LIMITH 12 12 + oneToSet read @@ -45015,222 +46458,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CH3LIMITL 13 13 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - CH4LIMITH - Write '1' to enable interrupt for event CH4LIMITH - 14 - 14 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - CH4LIMITL - Write '1' to enable interrupt for event CH4LIMITL - 15 - 15 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - CH5LIMITH - Write '1' to enable interrupt for event CH5LIMITH - 16 - 16 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - CH5LIMITL - Write '1' to enable interrupt for event CH5LIMITL - 17 - 17 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - CH6LIMITH - Write '1' to enable interrupt for event CH6LIMITH - 18 - 18 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - CH6LIMITL - Write '1' to enable interrupt for event CH6LIMITL - 19 - 19 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - CH7LIMITH - Write '1' to enable interrupt for event CH7LIMITH - 20 - 20 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - CH7LIMITL - Write '1' to enable interrupt for event CH7LIMITL - 21 - 21 + oneToSet read @@ -45268,6 +46496,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event STARTED 0 0 + oneToClear read @@ -45295,6 +46524,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event END 1 1 + oneToClear read @@ -45322,6 +46552,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DONE 2 2 + oneToClear read @@ -45349,6 +46580,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event RESULTDONE 3 3 + oneToClear read @@ -45376,6 +46608,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event CALIBRATEDONE 4 4 + oneToClear read @@ -45399,226 +46632,11 @@ POSSIBILITY OF SUCH DAMAGE. - STOPPED - Write '1' to disable interrupt for event STOPPED - 5 - 5 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - CH0LIMITH - Write '1' to disable interrupt for event CH0LIMITH - 6 - 6 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - CH0LIMITL - Write '1' to disable interrupt for event CH0LIMITL - 7 - 7 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - CH1LIMITH - Write '1' to disable interrupt for event CH1LIMITH - 8 - 8 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - CH1LIMITL - Write '1' to disable interrupt for event CH1LIMITL - 9 - 9 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - CH2LIMITH - Write '1' to disable interrupt for event CH2LIMITH - 10 - 10 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - CH2LIMITL - Write '1' to disable interrupt for event CH2LIMITL - 11 - 11 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - CH3LIMITH - Write '1' to disable interrupt for event CH3LIMITH - 12 - 12 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - CH3LIMITL - Write '1' to disable interrupt for event CH3LIMITL - 13 - 13 + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + oneToClear read @@ -45642,10 +46660,11 @@ POSSIBILITY OF SUCH DAMAGE. - CH4LIMITH - Write '1' to disable interrupt for event CH4LIMITH - 14 - 14 + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + oneToClear read @@ -45669,10 +46688,11 @@ POSSIBILITY OF SUCH DAMAGE. - CH4LIMITL - Write '1' to disable interrupt for event CH4LIMITL - 15 - 15 + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + oneToClear read @@ -45696,10 +46716,11 @@ POSSIBILITY OF SUCH DAMAGE. - CH5LIMITH - Write '1' to disable interrupt for event CH5LIMITH - 16 - 16 + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + oneToClear read @@ -45723,10 +46744,11 @@ POSSIBILITY OF SUCH DAMAGE. - CH5LIMITL - Write '1' to disable interrupt for event CH5LIMITL - 17 - 17 + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + oneToClear read @@ -45750,10 +46772,11 @@ POSSIBILITY OF SUCH DAMAGE. - CH6LIMITH - Write '1' to disable interrupt for event CH6LIMITH - 18 - 18 + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + oneToClear read @@ -45777,10 +46800,11 @@ POSSIBILITY OF SUCH DAMAGE. - CH6LIMITL - Write '1' to disable interrupt for event CH6LIMITL - 19 - 19 + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + oneToClear read @@ -45804,10 +46828,11 @@ POSSIBILITY OF SUCH DAMAGE. - CH7LIMITH - Write '1' to disable interrupt for event CH7LIMITH - 20 - 20 + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + oneToClear read @@ -45831,10 +46856,11 @@ POSSIBILITY OF SUCH DAMAGE. - CH7LIMITL - Write '1' to disable interrupt for event CH7LIMITL - 21 - 21 + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + oneToClear read @@ -45916,7 +46942,7 @@ POSSIBILITY OF SUCH DAMAGE. - 8 + 4 0x010 CH[%s] Unspecified @@ -45925,7 +46951,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x510 PSELP - Description cluster: Input positive pin selection for CH[n] + Description cluster: Input positive pin selection for CH[m] 0x000 read-write 0x00000000 @@ -45945,10 +46971,15 @@ POSSIBILITY OF SUCH DAMAGE. INTERNAL - Internal input selection for analog positive input when CH[n].PSELP.CONNECT = Internal + Internal input selection for analog positive input when CH[m].PSELP.CONNECT = Internal 12 14 + + Dvdd + Connected to the internal 0.9 V digital supply rail + 0x0 + VddL Connected to VDDL @@ -45988,7 +47019,7 @@ POSSIBILITY OF SUCH DAMAGE. PSELN - Description cluster: Input negative pin selection for CH[n] + Description cluster: Input negative pin selection for CH[m] 0x004 read-write 0x00000000 @@ -46008,7 +47039,7 @@ POSSIBILITY OF SUCH DAMAGE. INTERNAL - Internal input selection for Analog negative input when CH[n].PSELN.CONNECT = Internal + Internal input selection for Analog negative input when CH[m].PSELN.CONNECT = Internal 12 14 @@ -46022,11 +47053,6 @@ POSSIBILITY OF SUCH DAMAGE. Connected to VDDL 0x1 - - Vdd - Connected to VDD - 0x2 - Vss Unspecified @@ -46056,7 +47082,7 @@ POSSIBILITY OF SUCH DAMAGE. CONFIG - Description cluster: Input configuration for CH[n] + Description cluster: Input configuration for CH[m] 0x008 read-write 0x00020000 @@ -46125,11 +47151,6 @@ POSSIBILITY OF SUCH DAMAGE. Reference given at VDDL 0x2 - - Vdd - Reference given at VDD - 0x3 - @@ -46639,6 +47660,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DATARDY 0 0 + oneToSet read @@ -46676,6 +47698,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DATARDY 0 0 + oneToClear read @@ -46722,7 +47745,7 @@ POSSIBILITY OF SUCH DAMAGE. Slope of 1st piece wise linear function 0x520 read-write - 0x000002D6 + 0x0000038C 0x20 @@ -46738,7 +47761,7 @@ POSSIBILITY OF SUCH DAMAGE. Slope of 2nd piece wise linear function 0x524 read-write - 0x0000032D + 0x000003B3 0x20 @@ -46754,7 +47777,7 @@ POSSIBILITY OF SUCH DAMAGE. Slope of 3rd piece wise linear function 0x528 read-write - 0x00000384 + 0x000003FA 0x20 @@ -46770,7 +47793,7 @@ POSSIBILITY OF SUCH DAMAGE. Slope of 4th piece wise linear function 0x52C read-write - 0x000003E9 + 0x00000451 0x20 @@ -46786,7 +47809,7 @@ POSSIBILITY OF SUCH DAMAGE. Slope of 5th piece wise linear function 0x530 read-write - 0x0000046F + 0x000004AA 0x20 @@ -46802,7 +47825,7 @@ POSSIBILITY OF SUCH DAMAGE. Slope of 6th piece wise linear function 0x534 read-write - 0x00000522 + 0x00000539 0x20 @@ -46818,7 +47841,7 @@ POSSIBILITY OF SUCH DAMAGE. Slope of 7th piece wise linear function 0x538 read-write - 0x000005B7 + 0x00000578 0x20 @@ -46834,7 +47857,7 @@ POSSIBILITY OF SUCH DAMAGE. y-intercept of 1st piece wise linear function 0x540 read-write - 0x00000FD6 + 0x00000037 0x20 @@ -46850,7 +47873,7 @@ POSSIBILITY OF SUCH DAMAGE. y-intercept of 2nd piece wise linear function 0x544 read-write - 0x00000F76 + 0x00000011 0x20 @@ -46866,7 +47889,7 @@ POSSIBILITY OF SUCH DAMAGE. y-intercept of 3rd piece wise linear function 0x548 read-write - 0x00000F8A + 0x00000005 0x20 @@ -46882,7 +47905,7 @@ POSSIBILITY OF SUCH DAMAGE. y-intercept of 4th piece wise linear function 0x54C read-write - 0x00000FF8 + 0x0000002B 0x20 @@ -46898,7 +47921,7 @@ POSSIBILITY OF SUCH DAMAGE. y-intercept of 5th piece wise linear function 0x550 read-write - 0x000000CC + 0x0000008F 0x20 @@ -46914,7 +47937,7 @@ POSSIBILITY OF SUCH DAMAGE. y-intercept of 6th piece wise linear function 0x554 read-write - 0x00000207 + 0x0000015D 0x20 @@ -46930,7 +47953,7 @@ POSSIBILITY OF SUCH DAMAGE. y-intercept of 7th piece wise linear function 0x558 read-write - 0x00000558 + 0x000001C0 0x20 @@ -46946,7 +47969,7 @@ POSSIBILITY OF SUCH DAMAGE. End point of 1st piece wise linear function 0x560 read-write - 0x000000E2 + 0x000000E5 0x20 @@ -46962,7 +47985,7 @@ POSSIBILITY OF SUCH DAMAGE. End point of 2nd piece wise linear function 0x564 read-write - 0x00000002 + 0x000000FB 0x20 @@ -46978,7 +48001,7 @@ POSSIBILITY OF SUCH DAMAGE. End point of 3rd piece wise linear function 0x568 read-write - 0x0000001F + 0x00000010 0x20 @@ -46994,7 +48017,7 @@ POSSIBILITY OF SUCH DAMAGE. End point of 4th piece wise linear function 0x56C read-write - 0x00000038 + 0x0000002B 0x20 @@ -47010,7 +48033,7 @@ POSSIBILITY OF SUCH DAMAGE. End point of 5th piece wise linear function 0x570 read-write - 0x0000004F + 0x00000041 0x20 @@ -47026,7 +48049,7 @@ POSSIBILITY OF SUCH DAMAGE. End point of 6th piece wise linear function 0x574 read-write - 0x00000066 + 0x00000050 0x20 @@ -53366,7 +54389,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x140 NONSECURE - Description cluster: Non-secure port event from owner n + Description cluster: Non-secure port event 0x000 read-write 0x00000000 @@ -53375,7 +54398,7 @@ POSSIBILITY OF SUCH DAMAGE. NONSECURE - Non-secure port event from owner n + Non-secure port event 0 0 @@ -53395,7 +54418,7 @@ POSSIBILITY OF SUCH DAMAGE. SECURE - Description cluster: Secure port event from owner n + Description cluster: Secure port event 0x004 read-write 0x00000000 @@ -53404,7 +54427,7 @@ POSSIBILITY OF SUCH DAMAGE. SECURE - Secure port event from owner n + Secure port event 0 0 @@ -53548,6 +54571,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event IN[0] 0 0 + oneToSet read @@ -53575,6 +54599,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event IN[1] 1 1 + oneToSet read @@ -53602,6 +54627,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event IN[2] 2 2 + oneToSet read @@ -53629,6 +54655,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event IN[3] 3 3 + oneToSet read @@ -53656,6 +54683,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event IN[4] 4 4 + oneToSet read @@ -53683,6 +54711,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event IN[5] 5 5 + oneToSet read @@ -53710,6 +54739,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event IN[6] 6 6 + oneToSet read @@ -53737,6 +54767,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event IN[7] 7 7 + oneToSet read @@ -53764,6 +54795,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PORT0NONSECURE 16 16 + oneToSet read @@ -53791,6 +54823,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PORT0SECURE 17 17 + oneToSet read @@ -53828,6 +54861,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event IN[0] 0 0 + oneToClear read @@ -53855,6 +54889,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event IN[1] 1 1 + oneToClear read @@ -53882,6 +54917,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event IN[2] 2 2 + oneToClear read @@ -53909,6 +54945,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event IN[3] 3 3 + oneToClear read @@ -53936,6 +54973,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event IN[4] 4 4 + oneToClear read @@ -53963,6 +55001,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event IN[5] 5 5 + oneToClear read @@ -53990,6 +55029,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event IN[6] 6 6 + oneToClear read @@ -54017,6 +55057,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event IN[7] 7 7 + oneToClear read @@ -54044,6 +55085,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event PORT0NONSECURE 16 16 + oneToClear read @@ -54071,6 +55113,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event PORT0SECURE 17 17 + oneToClear read @@ -54108,6 +55151,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event IN[0] 0 0 + oneToSet read @@ -54135,6 +55179,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event IN[1] 1 1 + oneToSet read @@ -54162,6 +55207,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event IN[2] 2 2 + oneToSet read @@ -54189,6 +55235,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event IN[3] 3 3 + oneToSet read @@ -54216,6 +55263,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event IN[4] 4 4 + oneToSet read @@ -54243,6 +55291,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event IN[5] 5 5 + oneToSet read @@ -54270,6 +55319,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event IN[6] 6 6 + oneToSet read @@ -54297,6 +55347,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event IN[7] 7 7 + oneToSet read @@ -54324,6 +55375,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PORT0NONSECURE 16 16 + oneToSet read @@ -54351,6 +55403,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PORT0SECURE 17 17 + oneToSet read @@ -54388,6 +55441,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event IN[0] 0 0 + oneToClear read @@ -54415,6 +55469,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event IN[1] 1 1 + oneToClear read @@ -54442,6 +55497,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event IN[2] 2 2 + oneToClear read @@ -54469,6 +55525,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event IN[3] 3 3 + oneToClear read @@ -54496,6 +55553,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event IN[4] 4 4 + oneToClear read @@ -54523,6 +55581,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event IN[5] 5 5 + oneToClear read @@ -54550,6 +55609,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event IN[6] 6 6 + oneToClear read @@ -54577,6 +55637,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event IN[7] 7 7 + oneToClear read @@ -54604,6 +55665,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event PORT0NONSECURE 16 16 + oneToClear read @@ -54631,6 +55693,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event PORT0SECURE 17 17 + oneToClear read @@ -55555,6 +56618,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[0] 0 0 + oneToSet read @@ -55582,6 +56646,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[1] 1 1 + oneToSet read @@ -55609,6 +56674,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[2] 2 2 + oneToSet read @@ -55636,6 +56702,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[3] 3 3 + oneToSet read @@ -55663,6 +56730,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[4] 4 4 + oneToSet read @@ -55690,6 +56758,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[5] 5 5 + oneToSet read @@ -55717,6 +56786,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[6] 6 6 + oneToSet read @@ -55744,6 +56814,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[7] 7 7 + oneToSet read @@ -55771,6 +56842,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[8] 8 8 + oneToSet read @@ -55798,6 +56870,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[9] 9 9 + oneToSet read @@ -55825,6 +56898,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[10] 10 10 + oneToSet read @@ -55852,6 +56926,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[11] 11 11 + oneToSet read @@ -55879,6 +56954,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event RTCOMPARESYNC 25 25 + oneToSet read @@ -55906,6 +56982,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PWMPERIODEND 27 27 + oneToSet read @@ -55933,6 +57010,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PWMREADY 29 29 + oneToSet read @@ -55960,6 +57038,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CLKOUTREADY 30 30 + oneToSet read @@ -55997,6 +57076,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[0] 0 0 + oneToClear read @@ -56024,6 +57104,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[1] 1 1 + oneToClear read @@ -56051,6 +57132,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[2] 2 2 + oneToClear read @@ -56078,6 +57160,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[3] 3 3 + oneToClear read @@ -56105,6 +57188,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[4] 4 4 + oneToClear read @@ -56132,6 +57216,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[5] 5 5 + oneToClear read @@ -56159,6 +57244,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[6] 6 6 + oneToClear read @@ -56186,6 +57272,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[7] 7 7 + oneToClear read @@ -56213,6 +57300,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[8] 8 8 + oneToClear read @@ -56240,6 +57328,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[9] 9 9 + oneToClear read @@ -56267,6 +57356,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[10] 10 10 + oneToClear read @@ -56294,6 +57384,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[11] 11 11 + oneToClear read @@ -56321,6 +57412,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event RTCOMPARESYNC 25 25 + oneToClear read @@ -56348,6 +57440,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event PWMPERIODEND 27 27 + oneToClear read @@ -56375,6 +57468,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event PWMREADY 29 29 + oneToClear read @@ -56402,6 +57496,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event CLKOUTREADY 30 30 + oneToClear read @@ -57051,6 +58146,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[0] 0 0 + oneToSet read @@ -57078,6 +58174,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[1] 1 1 + oneToSet read @@ -57105,6 +58202,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[2] 2 2 + oneToSet read @@ -57132,6 +58230,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[3] 3 3 + oneToSet read @@ -57159,6 +58258,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[4] 4 4 + oneToSet read @@ -57186,6 +58286,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[5] 5 5 + oneToSet read @@ -57213,6 +58314,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[6] 6 6 + oneToSet read @@ -57240,6 +58342,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[7] 7 7 + oneToSet read @@ -57267,6 +58370,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[8] 8 8 + oneToSet read @@ -57294,6 +58398,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[9] 9 9 + oneToSet read @@ -57321,6 +58426,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[10] 10 10 + oneToSet read @@ -57348,6 +58454,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[11] 11 11 + oneToSet read @@ -57375,6 +58482,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event RTCOMPARESYNC 25 25 + oneToSet read @@ -57402,6 +58510,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PWMPERIODEND 27 27 + oneToSet read @@ -57429,6 +58538,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PWMREADY 29 29 + oneToSet read @@ -57456,6 +58566,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CLKOUTREADY 30 30 + oneToSet read @@ -57493,6 +58604,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[0] 0 0 + oneToClear read @@ -57520,6 +58632,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[1] 1 1 + oneToClear read @@ -57547,6 +58660,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[2] 2 2 + oneToClear read @@ -57574,6 +58688,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[3] 3 3 + oneToClear read @@ -57601,6 +58716,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[4] 4 4 + oneToClear read @@ -57628,6 +58744,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[5] 5 5 + oneToClear read @@ -57655,6 +58772,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[6] 6 6 + oneToClear read @@ -57682,6 +58800,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[7] 7 7 + oneToClear read @@ -57709,6 +58828,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[8] 8 8 + oneToClear read @@ -57736,6 +58856,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[9] 9 9 + oneToClear read @@ -57763,6 +58884,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[10] 10 10 + oneToClear read @@ -57790,6 +58912,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[11] 11 11 + oneToClear read @@ -57817,6 +58940,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event RTCOMPARESYNC 25 25 + oneToClear read @@ -57844,6 +58968,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event PWMPERIODEND 27 27 + oneToClear read @@ -57871,6 +58996,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event PWMREADY 29 29 + oneToClear read @@ -57898,6 +59024,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event CLKOUTREADY 30 30 + oneToClear read @@ -58547,6 +59674,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[0] 0 0 + oneToSet read @@ -58574,6 +59702,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[1] 1 1 + oneToSet read @@ -58601,6 +59730,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[2] 2 2 + oneToSet read @@ -58628,6 +59758,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[3] 3 3 + oneToSet read @@ -58655,6 +59786,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[4] 4 4 + oneToSet read @@ -58682,6 +59814,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[5] 5 5 + oneToSet read @@ -58709,6 +59842,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[6] 6 6 + oneToSet read @@ -58736,6 +59870,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[7] 7 7 + oneToSet read @@ -58763,6 +59898,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[8] 8 8 + oneToSet read @@ -58790,6 +59926,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[9] 9 9 + oneToSet read @@ -58817,6 +59954,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[10] 10 10 + oneToSet read @@ -58844,6 +59982,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[11] 11 11 + oneToSet read @@ -58871,6 +60010,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event RTCOMPARESYNC 25 25 + oneToSet read @@ -58898,6 +60038,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PWMPERIODEND 27 27 + oneToSet read @@ -58925,6 +60066,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PWMREADY 29 29 + oneToSet read @@ -58952,6 +60094,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CLKOUTREADY 30 30 + oneToSet read @@ -58989,6 +60132,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[0] 0 0 + oneToClear read @@ -59016,6 +60160,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[1] 1 1 + oneToClear read @@ -59043,6 +60188,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[2] 2 2 + oneToClear read @@ -59070,6 +60216,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[3] 3 3 + oneToClear read @@ -59097,6 +60244,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[4] 4 4 + oneToClear read @@ -59124,6 +60272,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[5] 5 5 + oneToClear read @@ -59151,6 +60300,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[6] 6 6 + oneToClear read @@ -59178,6 +60328,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[7] 7 7 + oneToClear read @@ -59205,6 +60356,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[8] 8 8 + oneToClear read @@ -59232,6 +60384,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[9] 9 9 + oneToClear read @@ -59259,6 +60412,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[10] 10 10 + oneToClear read @@ -59286,6 +60440,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[11] 11 11 + oneToClear read @@ -59313,6 +60468,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event RTCOMPARESYNC 25 25 + oneToClear read @@ -59340,6 +60496,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event PWMPERIODEND 27 27 + oneToClear read @@ -59367,6 +60524,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event PWMREADY 29 29 + oneToClear read @@ -59394,6 +60552,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event CLKOUTREADY 30 30 + oneToClear read @@ -60043,6 +61202,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[0] 0 0 + oneToSet read @@ -60070,6 +61230,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[1] 1 1 + oneToSet read @@ -60097,6 +61258,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[2] 2 2 + oneToSet read @@ -60124,6 +61286,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[3] 3 3 + oneToSet read @@ -60151,6 +61314,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[4] 4 4 + oneToSet read @@ -60178,6 +61342,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[5] 5 5 + oneToSet read @@ -60205,6 +61370,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[6] 6 6 + oneToSet read @@ -60232,6 +61398,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[7] 7 7 + oneToSet read @@ -60259,6 +61426,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[8] 8 8 + oneToSet read @@ -60286,6 +61454,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[9] 9 9 + oneToSet read @@ -60313,6 +61482,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[10] 10 10 + oneToSet read @@ -60340,6 +61510,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event COMPARE[11] 11 11 + oneToSet read @@ -60367,6 +61538,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event RTCOMPARESYNC 25 25 + oneToSet read @@ -60394,6 +61566,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PWMPERIODEND 27 27 + oneToSet read @@ -60421,6 +61594,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PWMREADY 29 29 + oneToSet read @@ -60448,6 +61622,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CLKOUTREADY 30 30 + oneToSet read @@ -60485,6 +61660,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[0] 0 0 + oneToClear read @@ -60512,6 +61688,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[1] 1 1 + oneToClear read @@ -60539,6 +61716,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[2] 2 2 + oneToClear read @@ -60566,6 +61744,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[3] 3 3 + oneToClear read @@ -60593,6 +61772,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[4] 4 4 + oneToClear read @@ -60620,6 +61800,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[5] 5 5 + oneToClear read @@ -60647,6 +61828,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[6] 6 6 + oneToClear read @@ -60674,6 +61856,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[7] 7 7 + oneToClear read @@ -60701,6 +61884,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[8] 8 8 + oneToClear read @@ -60728,6 +61912,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[9] 9 9 + oneToClear read @@ -60755,6 +61940,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[10] 10 10 + oneToClear read @@ -60782,6 +61968,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event COMPARE[11] 11 11 + oneToClear read @@ -60809,6 +61996,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event RTCOMPARESYNC 25 25 + oneToClear read @@ -60836,6 +62024,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event PWMPERIODEND 27 27 + oneToClear read @@ -60863,6 +62052,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event PWMREADY 29 29 + oneToClear read @@ -60890,6 +62080,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event CLKOUTREADY 30 30 + oneToClear read @@ -61420,7 +62611,7 @@ POSSIBILITY OF SUCH DAMAGE. CCADD Description cluster: Count to add to CC[n] when this register is written. 0x008 - read-write + write-only 0x00000000 0x20 @@ -62024,6 +63215,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TAMPER 0 0 + oneToSet read @@ -62051,6 +63243,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event WRITEERROR 1 1 + oneToSet read @@ -62088,6 +63281,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TAMPER 0 0 + oneToClear read @@ -62115,6 +63309,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event WRITEERROR 1 1 + oneToClear read @@ -62431,12 +63626,12 @@ POSSIBILITY OF SUCH DAMAGE. Low - Signal is logic 0. + Signal is logic 0, indicating that invasive debug is disabled. 0x0 High - Signal is logic 1. + Signal is logic 1, indicating that invasive debug is enabled. 0x1 @@ -62552,12 +63747,12 @@ POSSIBILITY OF SUCH DAMAGE. Low - Signal is logic 0. + Signal is logic 0, indicating that non-invasive debug is disabled. 0x0 High - Signal is logic 1. + Signal is logic 1, indicating that non-invasive debug is enabled. 0x1 @@ -62673,12 +63868,12 @@ POSSIBILITY OF SUCH DAMAGE. Low - Signal is logic 0. + Signal is logic 0, indicating that secure priviliged invasive debug is disabled. 0x0 High - Signal is logic 1. + Signal is logic 1, indicating that secure priviliged invasive debug is enabled. 0x1 @@ -62794,12 +63989,12 @@ POSSIBILITY OF SUCH DAMAGE. Low - Signal is logic 0. + Signal is logic 0, indicating that secure priviliged non-invasive debug is disabled. 0x0 High - Signal is logic 1. + Signal is logic 1, indicating that secure priviliged non-invasive debug is enabled. 0x1 @@ -62910,7 +64105,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x000 CTRL - Description cluster: Control register to enable invasive (halting) debug in domain n's access port. + Description cluster: Control register to enable invasive (halting) debug in domain ns access port. 0x000 read-write 0x00000010 @@ -62924,12 +64119,12 @@ POSSIBILITY OF SUCH DAMAGE. Low - Signal is logic 0. + Signal is logic 0, indicating that invasive debug is disabled. 0x0 High - Signal is logic 1. + Signal is logic 1, indicating that invasive debug is enabled. 0x1 @@ -62995,7 +64190,7 @@ POSSIBILITY OF SUCH DAMAGE. STATUS - Description cluster: Status register for invasive (halting) debug enable for domain n's access port. + Description cluster: Status register for invasive (halting) debug enable for domain ns access port. 0x004 read-write 0x00000000 @@ -64659,6 +65854,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event READY 0 0 + oneToSet read @@ -64686,6 +65882,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DOWN 1 1 + oneToSet read @@ -64713,6 +65910,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event UP 2 2 + oneToSet read @@ -64740,6 +65938,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CROSS 3 3 + oneToSet read @@ -64777,6 +65976,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event READY 0 0 + oneToClear read @@ -64804,6 +66004,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DOWN 1 1 + oneToClear read @@ -64831,6 +66032,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event UP 2 2 + oneToClear read @@ -64858,6 +66060,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event CROSS 3 3 + oneToClear read @@ -65864,6 +67067,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event READY 0 0 + oneToSet read @@ -65891,6 +67095,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DOWN 1 1 + oneToSet read @@ -65918,6 +67123,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event UP 2 2 + oneToSet read @@ -65945,6 +67151,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event CROSS 3 3 + oneToSet read @@ -65982,6 +67189,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event READY 0 0 + oneToClear read @@ -66009,6 +67217,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DOWN 1 1 + oneToClear read @@ -66036,6 +67245,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event UP 2 2 + oneToClear read @@ -66063,6 +67273,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event CROSS 3 3 + oneToClear read @@ -66723,6 +67934,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TIMEOUT 0 0 + oneToSet read @@ -66750,6 +67962,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event STOPPED 1 1 + oneToSet read @@ -66787,6 +68000,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TIMEOUT 0 0 + oneToClear read @@ -66814,6 +68028,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event STOPPED 1 1 + oneToClear read @@ -66851,6 +68066,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event TIMEOUT 0 0 + oneToSet read @@ -66878,6 +68094,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event STOPPED 1 1 + oneToSet read @@ -66915,6 +68132,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event TIMEOUT 0 0 + oneToClear read @@ -66942,6 +68160,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event STOPPED 1 1 + oneToClear read @@ -68601,6 +69820,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event XOSTARTED 0 0 + oneToSet read @@ -68628,6 +69848,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event PLLSTARTED 1 1 + oneToSet read @@ -68655,6 +69876,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event LFCLKSTARTED 2 2 + oneToSet read @@ -68682,6 +69904,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event DONE 3 3 + oneToSet read @@ -68709,6 +69932,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event XOTUNED 4 4 + oneToSet read @@ -68736,6 +69960,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event XOTUNEERROR 5 5 + oneToSet read @@ -68763,6 +69988,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event XOTUNEFAILED 6 6 + oneToSet read @@ -68800,6 +70026,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event XOSTARTED 0 0 + oneToClear read @@ -68827,6 +70054,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event PLLSTARTED 1 1 + oneToClear read @@ -68854,6 +70082,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event LFCLKSTARTED 2 2 + oneToClear read @@ -68881,6 +70110,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event DONE 3 3 + oneToClear read @@ -68908,6 +70138,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event XOTUNED 4 4 + oneToClear read @@ -68935,6 +70166,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event XOTUNEERROR 5 5 + oneToClear read @@ -68962,6 +70194,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event XOTUNEFAILED 6 6 + oneToClear read @@ -69801,6 +71034,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event POFWARN 12 12 + oneToSet read @@ -69828,6 +71062,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event SLEEPENTER 13 13 + oneToSet read @@ -69855,6 +71090,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to enable interrupt for event SLEEPEXIT 14 14 + oneToSet read @@ -69892,6 +71128,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event POFWARN 12 12 + oneToClear read @@ -69919,6 +71156,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event SLEEPENTER 13 13 + oneToClear read @@ -69946,6 +71184,7 @@ POSSIBILITY OF SUCH DAMAGE. Write '1' to disable interrupt for event SLEEPEXIT 14 14 + oneToClear read @@ -70443,6 +71682,34 @@ POSSIBILITY OF SUCH DAMAGE. OSCILLATORS_XOSC32KI read-write 0x900 + + BYPASS + Enable or disable bypass of LFCLK crystal oscillator with external clock source + 0x000 + read-write + 0x00000000 + 0x20 + + + BYPASS + Enable or disable bypass of LFCLK crystal oscillator with external clock source + 0 + 0 + + + Disabled + Disable (use crystal) + 0x0 + + + Enabled + Enable (use rail-to-rail external source) + 0x1 + + + + + INTCAP Programmable capacitance of XL1 and XL2 @@ -70619,161 +71886,81 @@ POSSIBILITY OF SUCH DAMAGE. 1 4 - - V17 - Set threshold to 1.7 V for VDD - 0x0 - V090 Set threshold to 0.90 V for VDDL 0x0 - - V18 - Set threshold to 1.8 V for VDD - 0x1 - V095 Set threshold to 0.95 V for VDDL 0x1 - - V19 - Set threshold to 1.9 V for VDD - 0x2 - V100 Set threshold to 1.00 V for VDDL 0x2 - - V20 - Set threshold to 2.0 V for VDD - 0x3 - V105 Set threshold to 1.05 V for VDDL 0x3 - - V21 - Set threshold to 2.1 V for VDD - 0x4 - V110 Set threshold to 1.10 V for VDDL 0x4 - - V22 - Set threshold to 2.2 V for VDD - 0x5 - V115 Set threshold to 1.15 V for VDDL 0x5 - - V23 - Set threshold to 2.3 V for VDD - 0x6 - V120 Set threshold to 1.20 V for VDDL 0x6 - - V24 - Set threshold to 2.4 V for VDD - 0x7 - V125 Set threshold to 1.25 V for VDDL 0x7 - - V25 - Set threshold to 2.5 V for VDD - 0x8 - V130 Set threshold to 1.30 V for VDDL 0x8 - - V26 - Set threshold to 2.6 V for VDD - 0x9 - V135 Set threshold to 1.35 V for VDDL 0x9 - - V27 - Set threshold to 2.7 V for VDD - 0xA - V140 Set threshold to 1.40 V for VDDL 0xA - - V28 - Set threshold to 2.8 V for VDD - 0xB - V145 Set threshold to 1.45 V for VDDL 0xB - - V29 - Set threshold to 2.9 V for VDD - 0xC - V150 Set threshold to 1.50 V for VDDL 0xC - - V30 - Set threshold to 3.0 V for VDD - 0xD - V155 Set threshold to 1.55 V for VDDL 0xD - - V31 - Set threshold to 3.1 V for VDD - 0xE - V160 Set threshold to 1.60 V for VDDL 0xE - - V32 - Set threshold to 3.2 V for VDD - 0xF - V165 Set threshold to 1.65 V for VDDL @@ -70805,14 +71992,9 @@ POSSIBILITY OF SUCH DAMAGE. 16 16 - - Vdd - POF input connected to VDD - 0x0 - VddL - POF input connected to VDDL + POF input connected to VDDL 0x1 diff --git a/nrfx/mdk/nrf54lv10a_enga_flpr_peripherals.h b/nrfx/mdk/nrf54lv10a_enga_flpr_peripherals.h index 8320792d..45d0a155 100644 --- a/nrfx/mdk/nrf54lv10a_enga_flpr_peripherals.h +++ b/nrfx/mdk/nrf54lv10a_enga_flpr_peripherals.h @@ -58,9 +58,9 @@ POSSIBILITY OF SUCH DAMAGE. #define VPRCSR_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ #define VPRCSR_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ #define VPRCSR_VEVIF_TASKS_MASK 0xFFFFFFFF /*!< Mask of supported VEVIF tasks: 0xFFFFFFFF */ -#define VPRCSR_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..3 */ -#define VPRCSR_VEVIF_NDPPI_MAX 3 /*!< VEVIF DPPI channels: 0..3 */ -#define VPRCSR_VEVIF_NDPPI_SIZE 4 /*!< VEVIF DPPI channels: 0..3 */ +#define VPRCSR_VEVIF_NDPPI_MIN 16 /*!< VEVIF DPPI indices: 16..19 */ +#define VPRCSR_VEVIF_NDPPI_MAX 19 /*!< VEVIF DPPI indices: 16..19 */ +#define VPRCSR_VEVIF_NDPPI_SIZE 20 /*!< VEVIF DPPI indices: 16..19 */ #define VPRCSR_VEVIF_NEVENTS_MIN 0 /*!< VEVIF events: 0..31 */ #define VPRCSR_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 0..31 */ #define VPRCSR_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 0..31 */ @@ -332,9 +332,9 @@ POSSIBILITY OF SUCH DAMAGE. #define VPR00_VEVIF_NTASKS_MAX 22 /*!< VEVIF tasks: 16..22 */ #define VPR00_VEVIF_NTASKS_SIZE 23 /*!< VEVIF tasks: 16..22 */ #define VPR00_VEVIF_TASKS_MASK 0x007F0000 /*!< Mask of supported VEVIF tasks: 0x007F0000 */ -#define VPR00_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..3 */ -#define VPR00_VEVIF_NDPPI_MAX 3 /*!< VEVIF DPPI channels: 0..3 */ -#define VPR00_VEVIF_NDPPI_SIZE 4 /*!< VEVIF DPPI channels: 0..3 */ +#define VPR00_VEVIF_NDPPI_MIN 16 /*!< VEVIF DPPI indices: 16..19 */ +#define VPR00_VEVIF_NDPPI_MAX 19 /*!< VEVIF DPPI indices: 16..19 */ +#define VPR00_VEVIF_NDPPI_SIZE 20 /*!< VEVIF DPPI indices: 16..19 */ #define VPR00_VEVIF_DPPI_MASK 0x000F0000 /*!< Mask of supported VEVIF DPPI channels: 0x000F0000 */ #define VPR00_VEVIF_NEVENTS_MIN 16 /*!< VEVIF events: 16..22 */ #define VPR00_VEVIF_NEVENTS_MAX 22 /*!< VEVIF events: 16..22 */ @@ -558,9 +558,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CRACEN_ONLYPROTECTEDRAMLOCK 0 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_SEED 0x51810000 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_SEED_SIZE 64 /*!< (unspecified) */ -#define CRACEN_PROTECTED_RAM_AES_KEY0 0x51810040 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_AES_KEY0 0x2002FF00 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_AES_KEY0_SIZE 32 /*!< (unspecified) */ -#define CRACEN_PROTECTED_RAM_AES_KEY1 0x51810060 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_AES_KEY1 0x2002FF20 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_AES_KEY1_SIZE 32 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_SM4_KEY0 0x51810080 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_SM4_KEY0_SIZE 16 /*!< (unspecified) */ @@ -651,7 +651,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ #define SPIM30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define SPIM30_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ -#define SPIM30_FEATURE_HARDWARE_DCX_PRESENT 0 /*!< (unspecified) */ +#define SPIM30_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ #define SPIM30_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ #define SPIM30_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ #define SPIM30_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ @@ -776,7 +776,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_PSEL_V2 1 /*!< (unspecified) */ #define SAADC_TASKS_CALIBRATEGAIN 0 /*!< (unspecified) */ -#define SAADC_SAMPLERATE_CC_VALUERANGE_MIN 8 /*!< (unspecified) */ +#define SAADC_SAMPLERATE_CC_VALUERANGE_MIN 16 /*!< (unspecified) */ #define SAADC_SAMPLERATE_CC_VALUERANGE_MAX 2047 /*!< (unspecified) */ #define SAADC_SAMPLERATE_CC_VALUERANGE_SIZE 2048 /*!< (unspecified) */ #define SAADC_TACQ_VALUE_RANGE_MIN 1 /*!< (unspecified) */ @@ -785,6 +785,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_TCONV_VALUE_RANGE_MIN 1 /*!< (unspecified) */ #define SAADC_TCONV_VALUE_RANGE_MAX 7 /*!< (unspecified) */ #define SAADC_TCONV_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ /*Temperature Sensor*/ #define TEMP_PRESENT 1 @@ -798,6 +799,7 @@ POSSIBILITY OF SUCH DAMAGE. #define P1_CTRLSEL_MAP2 1 /*!< (unspecified) */ #define P1_CTRLSEL_MAP3 0 /*!< (unspecified) */ #define P1_CTRLSEL_MAP4 0 /*!< (unspecified) */ +#define P1_CTRLSEL_MAP5 0 /*!< (unspecified) */ #define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ #define P1_PIN_NUM_MAX 25 /*!< (unspecified) */ #define P1_PIN_NUM_SIZE 26 /*!< (unspecified) */ @@ -817,6 +819,7 @@ POSSIBILITY OF SUCH DAMAGE. #define P0_CTRLSEL_MAP2 1 /*!< (unspecified) */ #define P0_CTRLSEL_MAP3 0 /*!< (unspecified) */ #define P0_CTRLSEL_MAP4 0 /*!< (unspecified) */ +#define P0_CTRLSEL_MAP5 0 /*!< (unspecified) */ #define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ #define P0_PIN_NUM_MAX 4 /*!< (unspecified) */ #define P0_PIN_NUM_SIZE 5 /*!< (unspecified) */ @@ -884,7 +887,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GRTC_CLKOUTREG 1 /*!< (unspecified) */ #define GRTC_CLKSELREG 1 /*!< (unspecified) */ #define GRTC_CLKSELLFLPRC 1 /*!< (unspecified) */ -#define GRTC_CCADD_WRITE_ONLY 0 /*!< (unspecified) */ +#define GRTC_CCADD_WRITE_ONLY 1 /*!< (unspecified) */ #define GRTC_READY_STATUS_AND_EVENTS 1 /*!< (unspecified) */ #define GRTC_SYSCOUNTER_LOADED_STATUS 1 /*!< (unspecified) */ #define GRTC_CC_PAST_STATUS 1 /*!< (unspecified) */ @@ -899,6 +902,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TAMPC_TAMPERSWITCH 0 /*!< (unspecified) */ #define TAMPC_SM4DISABLECM 0 /*!< (unspecified) */ #define TAMPC_PROTECTRESETBEHAVIOR 0 /*!< (unspecified) */ +#define TAMPC_SPIDEN 1 /*!< (unspecified) */ +#define TAMPC_SPNIDEN 1 /*!< (unspecified) */ +#define TAMPC_ACTIVESHIELD 1 /*!< (unspecified) */ /*Comparator*/ #define COMP_PRESENT 1 @@ -943,6 +949,8 @@ POSSIBILITY OF SUCH DAMAGE. #define REGULATORS_PRESENT 1 #define REGULATORS_COUNT 1 +#define REGULATORS_POF 1 /*!< (unspecified) */ + /* ==================================================== Baudrate settings ==================================================== */ /** * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency diff --git a/nrfx/mdk/nrf54lv10a_enga_types.h b/nrfx/mdk/nrf54lv10a_enga_types.h index 418bb441..6366da4d 100644 --- a/nrfx/mdk/nrf54lv10a_enga_types.h +++ b/nrfx/mdk/nrf54lv10a_enga_types.h @@ -4243,7 +4243,7 @@ typedef struct { /* CRACENCORE_RNGCONTROL_CONTROL: Control register */ #define CRACENCORE_RNGCONTROL_CONTROL_ResetValue (0x00040000UL) /*!< Reset value of CONTROL register. */ -/* ENABLE @Bit 0 : Start/enable the NDRNG. */ +/* ENABLE @Bit 0 : Start the NDRNG. Self-clearing bit. */ #define CRACENCORE_RNGCONTROL_CONTROL_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define CRACENCORE_RNGCONTROL_CONTROL_ENABLE_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_ENABLE_Pos) /*!< Bit mask of ENABLE field.*/ @@ -4356,11 +4356,11 @@ typedef struct { /* CRACENCORE_RNGCONTROL_FIFOTHRESHOLD: FIFO threshold register. */ #define CRACENCORE_RNGCONTROL_FIFOTHRESHOLD_ResetValue (0x00000003UL) /*!< Reset value of FIFOTHRESHOLD register. */ -/* FIFOTHRESHOLD @Bits 0..31 : FIFO level below which the module leaves the idle state to refill the FIFO, expressed in number - of 128bit blocks. */ +/* FIFOTHRESHOLD @Bits 0..2 : FIFO level threshold below which the module leaves the idle state to refill the FIFO. Expressed in + number of 128bit blocks. */ #define CRACENCORE_RNGCONTROL_FIFOTHRESHOLD_FIFOTHRESHOLD_Pos (0UL) /*!< Position of FIFOTHRESHOLD field. */ - #define CRACENCORE_RNGCONTROL_FIFOTHRESHOLD_FIFOTHRESHOLD_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_FIFOTHRESHOLD_FIFOTHRESHOLD_Pos) + #define CRACENCORE_RNGCONTROL_FIFOTHRESHOLD_FIFOTHRESHOLD_Msk (0x7UL << CRACENCORE_RNGCONTROL_FIFOTHRESHOLD_FIFOTHRESHOLD_Pos) /*!< Bit mask of FIFOTHRESHOLD field.*/ @@ -4498,10 +4498,10 @@ typedef struct { /* CRACENCORE_RNGCONTROL_DISABLEOSC: DisableOsc register. */ #define CRACENCORE_RNGCONTROL_DISABLEOSC_ResetValue (0x00000000UL) /*!< Reset value of DISABLEOSC register. */ -/* DISABLEOSC @Bits 0..7 : Disable oscillator rings 0 to 7. */ +/* DISABLEOSC @Bits 0..31 : Disable oscillator rings. */ #define CRACENCORE_RNGCONTROL_DISABLEOSC_DISABLEOSC_Pos (0UL) /*!< Position of DISABLEOSC field. */ - #define CRACENCORE_RNGCONTROL_DISABLEOSC_DISABLEOSC_Msk (0xFFUL << CRACENCORE_RNGCONTROL_DISABLEOSC_DISABLEOSC_Pos) /*!< Bit - mask of DISABLEOSC field.*/ + #define CRACENCORE_RNGCONTROL_DISABLEOSC_DISABLEOSC_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_DISABLEOSC_DISABLEOSC_Pos) /*!< + Bit mask of DISABLEOSC field.*/ /* CRACENCORE_RNGCONTROL_SAMPLINGPERIOD: Number of clock cycles between sampling moments. */ @@ -4551,42 +4551,42 @@ typedef struct { /* CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0: AutoCorrTestCutoff register 0 */ #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_ResetValue (0x007F007FUL) /*!< Reset value of AUTOCORRTESTCUTOFF0 register.*/ -/* DLYZEROCUTOFF @Bits 0..15 : Auto-correlation test cut-off value for delay of 0 samples. */ +/* DLYZEROCUTOFF @Bits 0..6 : Auto-correlation test cut-off value for delay of 0 samples. */ #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_DLYZEROCUTOFF_Pos (0UL) /*!< Position of DLYZEROCUTOFF field. */ - #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_DLYZEROCUTOFF_Msk (0xFFFFUL << CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_DLYZEROCUTOFF_Pos) + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_DLYZEROCUTOFF_Msk (0x7FUL << CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_DLYZEROCUTOFF_Pos) /*!< Bit mask of DLYZEROCUTOFF field.*/ -/* DLYONECUTOFF @Bits 16..31 : Auto-correlation test cut-off value for delay of +1 sample. */ +/* DLYONECUTOFF @Bits 16..22 : Auto-correlation test cut-off value for delay of +1 sample. */ #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_DLYONECUTOFF_Pos (16UL) /*!< Position of DLYONECUTOFF field. */ - #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_DLYONECUTOFF_Msk (0xFFFFUL << CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_DLYONECUTOFF_Pos) + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_DLYONECUTOFF_Msk (0x7FUL << CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_DLYONECUTOFF_Pos) /*!< Bit mask of DLYONECUTOFF field.*/ /* CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1: AutoCorrTestCutoff register 1 */ #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_ResetValue (0x007F007FUL) /*!< Reset value of AUTOCORRTESTCUTOFF1 register.*/ -/* DLYTWOCUTOFF @Bits 0..15 : Auto-correlation test cut-off value for delay of +2 samples. */ +/* DLYTWOCUTOFF @Bits 0..6 : Auto-correlation test cut-off value for delay of +2 samples. */ #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_DLYTWOCUTOFF_Pos (0UL) /*!< Position of DLYTWOCUTOFF field. */ - #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_DLYTWOCUTOFF_Msk (0xFFFFUL << CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_DLYTWOCUTOFF_Pos) + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_DLYTWOCUTOFF_Msk (0x7FUL << CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_DLYTWOCUTOFF_Pos) /*!< Bit mask of DLYTWOCUTOFF field.*/ -/* DLYTHREECUTOFF @Bits 16..31 : Auto-correlation test cut-off value for delay of +3 samples. */ +/* DLYTHREECUTOFF @Bits 16..22 : Auto-correlation test cut-off value for delay of +3 samples. */ #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_DLYTHREECUTOFF_Pos (16UL) /*!< Position of DLYTHREECUTOFF field. */ - #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_DLYTHREECUTOFF_Msk (0xFFFFUL << CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_DLYTHREECUTOFF_Pos) + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_DLYTHREECUTOFF_Msk (0x7FUL << CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_DLYTHREECUTOFF_Pos) /*!< Bit mask of DLYTHREECUTOFF field.*/ /* CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0: CorrTestCutoff register 0 */ #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_ResetValue (0x007F007FUL) /*!< Reset value of CORRTESTCUTOFF0 register. */ -/* DLYZEROCUTOFF @Bits 0..15 : Correlation test cut-off value for delay of 0 samples. */ +/* DLYZEROCUTOFF @Bits 0..6 : Correlation test cut-off value for delay of 0 samples. */ #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_DLYZEROCUTOFF_Pos (0UL) /*!< Position of DLYZEROCUTOFF field. */ - #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_DLYZEROCUTOFF_Msk (0xFFFFUL << CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_DLYZEROCUTOFF_Pos) + #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_DLYZEROCUTOFF_Msk (0x7FUL << CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_DLYZEROCUTOFF_Pos) /*!< Bit mask of DLYZEROCUTOFF field.*/ -/* DLYONECUTOFF @Bits 16..31 : Correlation test cut-off value for delay of +/-1 sample. */ +/* DLYONECUTOFF @Bits 16..22 : Correlation test cut-off value for delay of +/-1 sample. */ #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_DLYONECUTOFF_Pos (16UL) /*!< Position of DLYONECUTOFF field. */ - #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_DLYONECUTOFF_Msk (0xFFFFUL << CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_DLYONECUTOFF_Pos) + #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_DLYONECUTOFF_Msk (0x7FUL << CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_DLYONECUTOFF_Pos) /*!< Bit mask of DLYONECUTOFF field.*/ @@ -4802,7 +4802,7 @@ typedef struct { /* CRACENCORE_PK_TIMER: Timer register. */ #define CRACENCORE_PK_TIMER_ResetValue (0x00000000UL) /*!< Reset value of TIMER register. */ -/* TIMER @Bits 1..31 : Number of clock cycles (as the number of core cycles is always even, register bit 0 is tied to zero. */ +/* TIMER @Bits 1..31 : Number of clock cycles (as the number of core cycles is always even, register bit 0 is tied to zero). */ #define CRACENCORE_PK_TIMER_TIMER_Pos (1UL) /*!< Position of TIMER field. */ #define CRACENCORE_PK_TIMER_TIMER_Msk (0x7FFFFFFFUL << CRACENCORE_PK_TIMER_TIMER_Pos) /*!< Bit mask of TIMER field. */ @@ -6500,6 +6500,47 @@ typedef struct { #define ECB_OUT_PTR_PTR_Msk (0xFFFFFFFFUL << ECB_OUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* ===================================================== Struct ECB_CSAA ===================================================== */ +/** + * @brief CSAA [ECB_CSAA] Channel sounding access address scoring algorithm + */ +typedef struct { + __IM uint32_t REFLECTOR; /*!< (@ 0x00000000) Selected Channel Sounding Access Address used in the CS + SYNC from Reflector to Initiator*/ + __IM uint32_t INITIATOR; /*!< (@ 0x00000004) Selected Channel Sounding Access Address used in the CS + SYNC from Initiator to Reflector*/ + __IOM uint32_t MODE; /*!< (@ 0x00000008) Operation modes */ +} NRF_ECB_CSAA_Type; /*!< Size = 12 (0x00C) */ + +/* ECB_CSAA_REFLECTOR: Selected Channel Sounding Access Address used in the CS SYNC from Reflector to Initiator */ + #define ECB_CSAA_REFLECTOR_ResetValue (0x00000000UL) /*!< Reset value of REFLECTOR register. */ + +/* PN @Bits 0..31 : (unspecified) */ + #define ECB_CSAA_REFLECTOR_PN_Pos (0UL) /*!< Position of PN field. */ + #define ECB_CSAA_REFLECTOR_PN_Msk (0xFFFFFFFFUL << ECB_CSAA_REFLECTOR_PN_Pos) /*!< Bit mask of PN field. */ + + +/* ECB_CSAA_INITIATOR: Selected Channel Sounding Access Address used in the CS SYNC from Initiator to Reflector */ + #define ECB_CSAA_INITIATOR_ResetValue (0x00000000UL) /*!< Reset value of INITIATOR register. */ + +/* PN @Bits 0..31 : (unspecified) */ + #define ECB_CSAA_INITIATOR_PN_Pos (0UL) /*!< Position of PN field. */ + #define ECB_CSAA_INITIATOR_PN_Msk (0xFFFFFFFFUL << ECB_CSAA_INITIATOR_PN_Pos) /*!< Bit mask of PN field. */ + + +/* ECB_CSAA_MODE: Operation modes */ + #define ECB_CSAA_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* BITREVERSE @Bit 0 : Reverse the endianness on bit level for the ECB output, INITIATOR, and REFLECTOR registers */ + #define ECB_CSAA_MODE_BITREVERSE_Pos (0UL) /*!< Position of BITREVERSE field. */ + #define ECB_CSAA_MODE_BITREVERSE_Msk (0x1UL << ECB_CSAA_MODE_BITREVERSE_Pos) /*!< Bit mask of BITREVERSE field. */ + #define ECB_CSAA_MODE_BITREVERSE_Min (0x0UL) /*!< Min enumerator value of BITREVERSE field. */ + #define ECB_CSAA_MODE_BITREVERSE_Max (0x1UL) /*!< Max enumerator value of BITREVERSE field. */ + #define ECB_CSAA_MODE_BITREVERSE_Default (0x0UL) /*!< Default endianness */ + #define ECB_CSAA_MODE_BITREVERSE_Reversed (0x1UL) /*!< Reversed endianness */ + + /* ======================================================= Struct ECB ======================================================== */ /** * @brief AES ECB Mode Encryption @@ -6528,7 +6569,8 @@ typedef struct { __IOM NRF_ECB_IN_Type IN; /*!< (@ 0x00000530) IN EasyDMA channel */ __IM uint32_t RESERVED7; __IOM NRF_ECB_OUT_Type OUT; /*!< (@ 0x00000538) OUT EasyDMA channel */ - } NRF_ECB_Type; /*!< Size = 1340 (0x53C) */ + __IOM NRF_ECB_CSAA_Type CSAA; /*!< (@ 0x0000053C) Channel sounding access address scoring algorithm */ + } NRF_ECB_Type; /*!< Size = 1352 (0x548) */ /* ECB_TASKS_START: Start ECB block encrypt */ #define ECB_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ @@ -9845,7 +9887,7 @@ typedef struct { typedef struct { __IM uint32_t CONFIGID; /*!< (@ 0x00000000) Configuration identifier */ __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Device identifier */ - __IOM uint32_t UUID[4]; /*!< (@ 0x0000000C) 128-bit Universally Unique IDentifier (UUID). */ + __IM uint32_t UUID[4]; /*!< (@ 0x0000000C) 128-bit Universally Unique IDentifier (UUID). */ __IM uint32_t PART; /*!< (@ 0x0000001C) Part code */ __IM uint32_t VARIANT; /*!< (@ 0x00000020) Part Variant, Hardware version and Production configuration*/ @@ -9924,9 +9966,9 @@ typedef struct { /* RAM @Bits 0..31 : RAM size (KB) */ #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ - #define FICR_INFO_RAM_RAM_Min (0x80UL) /*!< Min enumerator value of RAM field. */ + #define FICR_INFO_RAM_RAM_Min (0xC0UL) /*!< Min enumerator value of RAM field. */ #define FICR_INFO_RAM_RAM_Max (0xFFFFFFFFUL) /*!< Max enumerator value of RAM field. */ - #define FICR_INFO_RAM_RAM_K192 (0x00000080UL) /*!< 192 kByte RAM */ + #define FICR_INFO_RAM_RAM_K192 (0x000000C0UL) /*!< 192 kByte RAM */ #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ @@ -12414,81 +12456,6 @@ typedef struct { #define GPIO_PIN_CNF_CTRLSEL_GRTC (0x4UL) /*!< GRTC peripheral */ -#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ - -/* =========================================================================================================================== */ -/* ================ GPIOHSPADCTRL ================ */ -/* =========================================================================================================================== */ - -#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ -/* ================================================== Struct GPIOHSPADCTRL =================================================== */ -/** - * @brief GPIO high-speed pad control - */ - typedef struct { /*!< GPIOHSPADCTRL Structure */ - __IM uint32_t RESERVED[12]; - __IOM uint32_t BIAS; /*!< (@ 0x00000030) Bias control */ - __IM uint32_t RESERVED1; - __IOM uint32_t CTRL; /*!< (@ 0x00000038) Input sampling and buffering control (used by the VPR - coprocessor for emulating a QSPI peripheral)*/ - } NRF_GPIOHSPADCTRL_Type; /*!< Size = 60 (0x03C) */ - -/* GPIOHSPADCTRL_BIAS: Bias control */ - #define GPIOHSPADCTRL_BIAS_ResetValue (0x00000000UL) /*!< Reset value of BIAS register. */ - -/* HSBIAS @Bits 0..1 : Slew setting for high-speed pad (higher value is faster) */ - #define GPIOHSPADCTRL_BIAS_HSBIAS_Pos (0UL) /*!< Position of HSBIAS field. */ - #define GPIOHSPADCTRL_BIAS_HSBIAS_Msk (0x3UL << GPIOHSPADCTRL_BIAS_HSBIAS_Pos) /*!< Bit mask of HSBIAS field. */ - #define GPIOHSPADCTRL_BIAS_HSBIAS_Min (0x0UL) /*!< Min value of HSBIAS field. */ - #define GPIOHSPADCTRL_BIAS_HSBIAS_Max (0x3UL) /*!< Max size of HSBIAS field. */ - -/* REPLICABIAS @Bit 2 : Slew setting for replica clock (used by the VPR coprocessor for emulating a QSPI peripheral) */ - #define GPIOHSPADCTRL_BIAS_REPLICABIAS_Pos (2UL) /*!< Position of REPLICABIAS field. */ - #define GPIOHSPADCTRL_BIAS_REPLICABIAS_Msk (0x1UL << GPIOHSPADCTRL_BIAS_REPLICABIAS_Pos) /*!< Bit mask of REPLICABIAS field. */ - #define GPIOHSPADCTRL_BIAS_REPLICABIAS_Min (0x0UL) /*!< Min value of REPLICABIAS field. */ - #define GPIOHSPADCTRL_BIAS_REPLICABIAS_Max (0x1UL) /*!< Max size of REPLICABIAS field. */ - - -/* GPIOHSPADCTRL_CTRL: Input sampling and buffering control (used by the VPR coprocessor for emulating a QSPI peripheral) */ - #define GPIOHSPADCTRL_CTRL_ResetValue (0x00000000UL) /*!< Reset value of CTRL register. */ - -/* RXDELAY @Bits 0..2 : Delay selection */ - #define GPIOHSPADCTRL_CTRL_RXDELAY_Pos (0UL) /*!< Position of RXDELAY field. */ - #define GPIOHSPADCTRL_CTRL_RXDELAY_Msk (0x7UL << GPIOHSPADCTRL_CTRL_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */ - -/* SCKEN @Bit 3 : Enable SCK */ - #define GPIOHSPADCTRL_CTRL_SCKEN_Pos (3UL) /*!< Position of SCKEN field. */ - #define GPIOHSPADCTRL_CTRL_SCKEN_Msk (0x1UL << GPIOHSPADCTRL_CTRL_SCKEN_Pos) /*!< Bit mask of SCKEN field. */ - #define GPIOHSPADCTRL_CTRL_SCKEN_Min (0x0UL) /*!< Min enumerator value of SCKEN field. */ - #define GPIOHSPADCTRL_CTRL_SCKEN_Max (0x1UL) /*!< Max enumerator value of SCKEN field. */ - #define GPIOHSPADCTRL_CTRL_SCKEN_Disabled (0x0UL) /*!< Delay chain is reset and delayed sampling is disabled */ - #define GPIOHSPADCTRL_CTRL_SCKEN_Enabled (0x1UL) /*!< Delay chain and delayed sampling is active */ - -/* SCKPHASE @Bit 4 : SCK phase */ - #define GPIOHSPADCTRL_CTRL_SCKPHASE_Pos (4UL) /*!< Position of SCKPHASE field. */ - #define GPIOHSPADCTRL_CTRL_SCKPHASE_Msk (0x1UL << GPIOHSPADCTRL_CTRL_SCKPHASE_Pos) /*!< Bit mask of SCKPHASE field. */ - #define GPIOHSPADCTRL_CTRL_SCKPHASE_Min (0x0UL) /*!< Min enumerator value of SCKPHASE field. */ - #define GPIOHSPADCTRL_CTRL_SCKPHASE_Max (0x1UL) /*!< Max enumerator value of SCKPHASE field. */ - #define GPIOHSPADCTRL_CTRL_SCKPHASE_Inverted (0x0UL) /*!< Invert SCK phase */ - #define GPIOHSPADCTRL_CTRL_SCKPHASE_NonInverted (0x1UL) /*!< Non-inverted SCK phase */ - -/* CSNEN @Bit 5 : Enable CSN synchronization of sampling */ - #define GPIOHSPADCTRL_CTRL_CSNEN_Pos (5UL) /*!< Position of CSNEN field. */ - #define GPIOHSPADCTRL_CTRL_CSNEN_Msk (0x1UL << GPIOHSPADCTRL_CTRL_CSNEN_Pos) /*!< Bit mask of CSNEN field. */ - #define GPIOHSPADCTRL_CTRL_CSNEN_Min (0x0UL) /*!< Min enumerator value of CSNEN field. */ - #define GPIOHSPADCTRL_CTRL_CSNEN_Max (0x1UL) /*!< Max enumerator value of CSNEN field. */ - #define GPIOHSPADCTRL_CTRL_CSNEN_Enabled (0x0UL) /*!< Delay chain is reset on active edge of CSN */ - #define GPIOHSPADCTRL_CTRL_CSNEN_Disabled (0x1UL) /*!< Delay chain is not reset on active edge of CSN */ - -/* DATAENABLE @Bits 6..9 : Enable delayed sampling */ - #define GPIOHSPADCTRL_CTRL_DATAENABLE_Pos (6UL) /*!< Position of DATAENABLE field. */ - #define GPIOHSPADCTRL_CTRL_DATAENABLE_Msk (0xFUL << GPIOHSPADCTRL_CTRL_DATAENABLE_Pos) /*!< Bit mask of DATAENABLE field. */ - #define GPIOHSPADCTRL_CTRL_DATAENABLE_Min (0x0UL) /*!< Min enumerator value of DATAENABLE field. */ - #define GPIOHSPADCTRL_CTRL_DATAENABLE_Max (0xFUL) /*!< Max enumerator value of DATAENABLE field. */ - #define GPIOHSPADCTRL_CTRL_DATAENABLE_Disabled (0x0UL) /*!< Delayed sampling is disabled */ - #define GPIOHSPADCTRL_CTRL_DATAENABLE_Enabled (0xFUL) /*!< Delayed sampling is enabled */ - - #endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ /* =========================================================================================================================== */ @@ -12517,17 +12484,17 @@ typedef struct { * @brief EVENTS_PORT [GPIOTE_EVENTS_PORT] Peripheral events. */ typedef struct { - __IOM uint32_t NONSECURE; /*!< (@ 0x00000000) Non-secure port event from owner n */ - __IOM uint32_t SECURE; /*!< (@ 0x00000004) Secure port event from owner n */ + __IOM uint32_t NONSECURE; /*!< (@ 0x00000000) Non-secure port event */ + __IOM uint32_t SECURE; /*!< (@ 0x00000004) Secure port event */ } NRF_GPIOTE_EVENTS_PORT_Type; /*!< Size = 8 (0x008) */ #define GPIOTE_EVENTS_PORT_MaxCount (1UL) /*!< Size of EVENTS_PORT[1] array. */ #define GPIOTE_EVENTS_PORT_MaxIndex (0UL) /*!< Max index of EVENTS_PORT[1] array. */ #define GPIOTE_EVENTS_PORT_MinIndex (0UL) /*!< Min index of EVENTS_PORT[1] array. */ -/* GPIOTE_EVENTS_PORT_NONSECURE: Non-secure port event from owner n */ +/* GPIOTE_EVENTS_PORT_NONSECURE: Non-secure port event */ #define GPIOTE_EVENTS_PORT_NONSECURE_ResetValue (0x00000000UL) /*!< Reset value of NONSECURE register. */ -/* NONSECURE @Bit 0 : Non-secure port event from owner n */ +/* NONSECURE @Bit 0 : Non-secure port event */ #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Pos (0UL) /*!< Position of NONSECURE field. */ #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Msk (0x1UL << GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Pos) /*!< Bit mask of NONSECURE field.*/ @@ -12537,10 +12504,10 @@ typedef struct { #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Generated (0x1UL) /*!< Event generated */ -/* GPIOTE_EVENTS_PORT_SECURE: Secure port event from owner n */ +/* GPIOTE_EVENTS_PORT_SECURE: Secure port event */ #define GPIOTE_EVENTS_PORT_SECURE_ResetValue (0x00000000UL) /*!< Reset value of SECURE register. */ -/* SECURE @Bit 0 : Secure port event from owner n */ +/* SECURE @Bit 0 : Secure port event */ #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Pos (0UL) /*!< Position of SECURE field. */ #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Msk (0x1UL << GPIOTE_EVENTS_PORT_SECURE_SECURE_Pos) /*!< Bit mask of SECURE field. */ #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Min (0x0UL) /*!< Min enumerator value of SECURE field. */ @@ -13226,7 +13193,7 @@ typedef struct { typedef struct { __IOM uint32_t CCL; /*!< (@ 0x00000000) The lower 32-bits of Capture/Compare register CC[n] */ __IOM uint32_t CCH; /*!< (@ 0x00000004) The higher 32-bits of Capture/Compare register CC[n] */ - __IOM uint32_t CCADD; /*!< (@ 0x00000008) Count to add to CC[n] when this register is written. */ + __OM uint32_t CCADD; /*!< (@ 0x00000008) Count to add to CC[n] when this register is written. */ __IOM uint32_t CCEN; /*!< (@ 0x0000000C) Configure Capture/Compare register CC[n] */ } NRF_GRTC_CC_Type; /*!< Size = 16 (0x010) */ #define GRTC_CC_MaxCount (12UL) /*!< Size of CC[12] array. */ @@ -17790,10 +17757,24 @@ typedef struct { * @brief XOSC32KI [OSCILLATORS_XOSC32KI] 32.768 kHz oscillator control */ typedef struct { - __IM uint32_t RESERVED; + __IOM uint32_t BYPASS; /*!< (@ 0x00000000) Enable or disable bypass of LFCLK crystal oscillator + with external clock source*/ __IOM uint32_t INTCAP; /*!< (@ 0x00000004) Programmable capacitance of XL1 and XL2 */ } NRF_OSCILLATORS_XOSC32KI_Type; /*!< Size = 8 (0x008) */ +/* OSCILLATORS_XOSC32KI_BYPASS: Enable or disable bypass of LFCLK crystal oscillator with external clock source */ + #define OSCILLATORS_XOSC32KI_BYPASS_ResetValue (0x00000000UL) /*!< Reset value of BYPASS register. */ + +/* BYPASS @Bit 0 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ + #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Pos (0UL) /*!< Position of BYPASS field. */ + #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Msk (0x1UL << OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Pos) /*!< Bit mask of BYPASS + field.*/ + #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Min (0x0UL) /*!< Min enumerator value of BYPASS field. */ + #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Max (0x1UL) /*!< Max enumerator value of BYPASS field. */ + #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Disabled (0x0UL) /*!< Disable (use crystal) */ + #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Enabled (0x1UL) /*!< Enable (use rail-to-rail external source) */ + + /* OSCILLATORS_XOSC32KI_INTCAP: Programmable capacitance of XL1 and XL2 */ #define OSCILLATORS_XOSC32KI_INTCAP_ResetValue (0x00000017UL) /*!< Reset value of INTCAP register. */ @@ -18491,6 +18472,127 @@ typedef struct { #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ================================================== Struct RADIO_AUXDATA =================================================== */ +/** + * @brief AUXDATA [RADIO_AUXDATA] (unspecified) + */ +typedef struct { + __IOM uint32_t CNF[2]; /*!< (@ 0x00000000) AUXDATA configuration */ +} NRF_RADIO_AUXDATA_Type; /*!< Size = 8 (0x008) */ + +/* RADIO_AUXDATA_CNF: AUXDATA configuration */ + #define RADIO_AUXDATA_CNF_MaxCount (2UL) /*!< Max size of CNF[2] array. */ + #define RADIO_AUXDATA_CNF_MaxIndex (1UL) /*!< Max index of CNF[2] array. */ + #define RADIO_AUXDATA_CNF_MinIndex (0UL) /*!< Min index of CNF[2] array. */ + #define RADIO_AUXDATA_CNF_ResetValue (0x00000000UL) /*!< Reset value of CNF[2] register. */ + +/* ACQMODE @Bits 0..4 : Acquisition mode (data from RADIO written to memory) */ + #define RADIO_AUXDATA_CNF_ACQMODE_Pos (0UL) /*!< Position of ACQMODE field. */ + #define RADIO_AUXDATA_CNF_ACQMODE_Msk (0x1FUL << RADIO_AUXDATA_CNF_ACQMODE_Pos) /*!< Bit mask of ACQMODE field. */ + #define RADIO_AUXDATA_CNF_ACQMODE_Min (0x7UL) /*!< Min enumerator value of ACQMODE field. */ + #define RADIO_AUXDATA_CNF_ACQMODE_Max (0x7UL) /*!< Max enumerator value of ACQMODE field. */ + #define RADIO_AUXDATA_CNF_ACQMODE_Rtt (0x07UL) /*!< Baseband Channel Sounding RTT Data */ + +/* DIR @Bit 31 : Data acquisition or injection */ + #define RADIO_AUXDATA_CNF_DIR_Pos (31UL) /*!< Position of DIR field. */ + #define RADIO_AUXDATA_CNF_DIR_Msk (0x1UL << RADIO_AUXDATA_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ + #define RADIO_AUXDATA_CNF_DIR_Min (0x0UL) /*!< Min enumerator value of DIR field. */ + #define RADIO_AUXDATA_CNF_DIR_Max (0x1UL) /*!< Max enumerator value of DIR field. */ + #define RADIO_AUXDATA_CNF_DIR_Acq (0x0UL) /*!< Peripheral to memory */ + #define RADIO_AUXDATA_CNF_DIR_Inj (0x1UL) /*!< Memory to peripheral */ + + + +/* ================================================= Struct RADIO_AUXDATADMA ================================================= */ +/** + * @brief AUXDATADMA [RADIO_AUXDATADMA] (unspecified) + */ +typedef struct { + __IOM uint32_t ENABLE; /*!< (@ 0x00000000) Enable or disable data acquisition */ + __IOM uint32_t PTR; /*!< (@ 0x00000004) ACQ DMA pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of 32-bit words to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of 32-bit words transferred in the last + transaction*/ +} NRF_RADIO_AUXDATADMA_Type; /*!< Size = 16 (0x010) */ + #define RADIO_AUXDATADMA_MaxCount (2UL) /*!< Size of AUXDATADMA[2] array. */ + #define RADIO_AUXDATADMA_MaxIndex (1UL) /*!< Max index of AUXDATADMA[2] array. */ + #define RADIO_AUXDATADMA_MinIndex (0UL) /*!< Min index of AUXDATADMA[2] array. */ + +/* RADIO_AUXDATADMA_ENABLE: Enable or disable data acquisition */ + #define RADIO_AUXDATADMA_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable or disable data acquisition */ + #define RADIO_AUXDATADMA_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define RADIO_AUXDATADMA_ENABLE_ENABLE_Msk (0x1UL << RADIO_AUXDATADMA_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define RADIO_AUXDATADMA_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define RADIO_AUXDATADMA_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define RADIO_AUXDATADMA_ENABLE_ENABLE_Disabled (0x0UL) /*!< Data acquisition is disabled */ + #define RADIO_AUXDATADMA_ENABLE_ENABLE_Enabled (0x1UL) /*!< Data acquisition is enabled */ + + +/* RADIO_AUXDATADMA_PTR: ACQ DMA pointer */ + #define RADIO_AUXDATADMA_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Data pointer */ + #define RADIO_AUXDATADMA_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define RADIO_AUXDATADMA_PTR_PTR_Msk (0xFFFFFFFFUL << RADIO_AUXDATADMA_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* RADIO_AUXDATADMA_MAXCNT: Maximum number of 32-bit words to transfer */ + #define RADIO_AUXDATADMA_MAXCNT_ResetValue (0x00000040UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..13 : Maximum number of 32-bit words to transfer */ + #define RADIO_AUXDATADMA_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define RADIO_AUXDATADMA_MAXCNT_MAXCNT_Msk (0x3FFFUL << RADIO_AUXDATADMA_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + + +/* RADIO_AUXDATADMA_AMOUNT: Number of 32-bit words transferred in the last transaction */ + #define RADIO_AUXDATADMA_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..13 : Number of 32-bit words transferred in the last transaction */ + #define RADIO_AUXDATADMA_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define RADIO_AUXDATADMA_AMOUNT_AMOUNT_Msk (0x3FFFUL << RADIO_AUXDATADMA_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + + +/* =================================================== Struct RADIO_RXGAIN =================================================== */ +/** + * @brief RXGAIN [RADIO_RXGAIN] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t CONFIG; /*!< (@ 0x00000004) Override configuration of receiver gain control loop */ +} NRF_RADIO_RXGAIN_Type; /*!< Size = 8 (0x008) */ + +/* RADIO_RXGAIN_CONFIG: Override configuration of receiver gain control loop */ + #define RADIO_RXGAIN_CONFIG_ResetValue (0x801230C3UL) /*!< Reset value of CONFIG register. */ + +/* AGCAAFOVERRIDE @Bits 17..20 : Override value for AAF */ + #define RADIO_RXGAIN_CONFIG_AGCAAFOVERRIDE_Pos (17UL) /*!< Position of AGCAAFOVERRIDE field. */ + #define RADIO_RXGAIN_CONFIG_AGCAAFOVERRIDE_Msk (0xFUL << RADIO_RXGAIN_CONFIG_AGCAAFOVERRIDE_Pos) /*!< Bit mask of + AGCAAFOVERRIDE field.*/ + +/* AGCMIXOVERRIDE @Bit 21 : Override value for MIX */ + #define RADIO_RXGAIN_CONFIG_AGCMIXOVERRIDE_Pos (21UL) /*!< Position of AGCMIXOVERRIDE field. */ + #define RADIO_RXGAIN_CONFIG_AGCMIXOVERRIDE_Msk (0x1UL << RADIO_RXGAIN_CONFIG_AGCMIXOVERRIDE_Pos) /*!< Bit mask of + AGCMIXOVERRIDE field.*/ + +/* AGCLNAOVERRIDE @Bits 22..23 : Override value for LNA */ + #define RADIO_RXGAIN_CONFIG_AGCLNAOVERRIDE_Pos (22UL) /*!< Position of AGCLNAOVERRIDE field. */ + #define RADIO_RXGAIN_CONFIG_AGCLNAOVERRIDE_Msk (0x3UL << RADIO_RXGAIN_CONFIG_AGCLNAOVERRIDE_Pos) /*!< Bit mask of + AGCLNAOVERRIDE field.*/ + +/* AGCOVERRIDEGAIN @Bit 28 : Enable AGC override */ + #define RADIO_RXGAIN_CONFIG_AGCOVERRIDEGAIN_Pos (28UL) /*!< Position of AGCOVERRIDEGAIN field. */ + #define RADIO_RXGAIN_CONFIG_AGCOVERRIDEGAIN_Msk (0x1UL << RADIO_RXGAIN_CONFIG_AGCOVERRIDEGAIN_Pos) /*!< Bit mask of + AGCOVERRIDEGAIN field.*/ + #define RADIO_RXGAIN_CONFIG_AGCOVERRIDEGAIN_Min (0x0UL) /*!< Min enumerator value of AGCOVERRIDEGAIN field. */ + #define RADIO_RXGAIN_CONFIG_AGCOVERRIDEGAIN_Max (0x1UL) /*!< Max enumerator value of AGCOVERRIDEGAIN field. */ + #define RADIO_RXGAIN_CONFIG_AGCOVERRIDEGAIN_NoOverride (0x0UL) /*!< AGC takes control over all gains */ + #define RADIO_RXGAIN_CONFIG_AGCOVERRIDEGAIN_Override (0x1UL) /*!< Manual control of AAF, MIX, and LNA gain settings */ + + + /* ==================================================== Struct RADIO_PSEL ==================================================== */ /** * @brief PSEL [RADIO_PSEL] (unspecified) @@ -18582,11 +18684,7 @@ typedef struct { __IOM uint32_t NUMSAMPLES; /*!< (@ 0x00000004) Number of input samples at 2MHz sample rate */ __IOM uint32_t NEXTFREQUENCY; /*!< (@ 0x00000008) The value of FREQUENCY that will be used in the next step*/ - __IOM uint32_t FFOIN; /*!< (@ 0x0000000C) Override value of FFO (Fractional Frequency Offset) if - not to be based on the frequency estimate derived from - CnAcc (autocorrelation of the scaled input signal) - value*/ - __IOM uint32_t FFOSOURCE; /*!< (@ 0x00000010) Source of FFO */ + __IM uint32_t RESERVED[2]; __IOM uint32_t FAEPEER; /*!< (@ 0x00000014) FAEPEER (Frequency Actuation Error) of peer if known. Used during Mode 0 steps.*/ __IOM uint32_t PHASESHIFT; /*!< (@ 0x00000018) Parameter used in TPM, provided by software */ @@ -18596,19 +18694,12 @@ typedef struct { converted to PCT16*/ __IM uint32_t IQRAWMEAN; /*!< (@ 0x00000028) Mean of IQ values */ __IM uint32_t MAGSTD; /*!< (@ 0x0000002C) Magnitude standard deviation approximation */ - __IM uint32_t CNACC; /*!< (@ 0x00000030) Output of the autocorrelation of the accumulated IQ - signal*/ + __IM uint32_t RESERVED1; __IM uint32_t FFOEST; /*!< (@ 0x00000034) FFO estimate */ __IOM uint32_t DOWNSAMPLE; /*!< (@ 0x00000038) Turn on/off down sample of input IQ-signals */ - __IM uint32_t FINETUNENEXT; /*!< (@ 0x0000003C) Number of full ADPLL finetune steps */ - __IM uint32_t CFOPHASE; /*!< (@ 0x00000040) Cordic output of CnAcc */ + __IM uint32_t RESERVED2[2]; __IM uint32_t FREQOFFSET; /*!< (@ 0x00000044) Frequency offset estimate */ - __IM uint32_t PCT11; /*!< (@ 0x00000048) Mean magnitude and mean phase converted to IQ. IQ - values limited to [-1024,1023].*/ - __IM uint32_t LFAENEXT; /*!< (@ 0x0000004C) Quantization error between ADPLL frequency and the - desired value of FFO * RF Frequency. Values limited to - [-64,63] with units 7.6294 Hz.*/ -} NRF_RADIO_CSTONES_Type; /*!< Size = 80 (0x050) */ +} NRF_RADIO_CSTONES_Type; /*!< Size = 72 (0x048) */ /* RADIO_CSTONES_MODE: Selects the mode(s) that are activated on the start signal */ #define RADIO_CSTONES_MODE_ResetValue (0x00000003UL) /*!< Reset value of MODE register. */ @@ -18648,29 +18739,6 @@ typedef struct { of NEXTFREQUENCY field.*/ -/* RADIO_CSTONES_FFOIN: Override value of FFO (Fractional Frequency Offset) if not to be based on the frequency estimate derived - from CnAcc (autocorrelation of the scaled input signal) value */ - - #define RADIO_CSTONES_FFOIN_ResetValue (0x00000000UL) /*!< Reset value of FFOIN register. */ - -/* FFFIN @Bits 0..11 : Units 62.5 ppb. Max range +/-100 ppm plus margin. */ - #define RADIO_CSTONES_FFOIN_FFFIN_Pos (0UL) /*!< Position of FFFIN field. */ - #define RADIO_CSTONES_FFOIN_FFFIN_Msk (0xFFFUL << RADIO_CSTONES_FFOIN_FFFIN_Pos) /*!< Bit mask of FFFIN field. */ - - -/* RADIO_CSTONES_FFOSOURCE: Source of FFO */ - #define RADIO_CSTONES_FFOSOURCE_ResetValue (0x00000001UL) /*!< Reset value of FFOSOURCE register. */ - -/* FFOSOURCE @Bit 0 : Use external or internal FFOSOURCE */ - #define RADIO_CSTONES_FFOSOURCE_FFOSOURCE_Pos (0UL) /*!< Position of FFOSOURCE field. */ - #define RADIO_CSTONES_FFOSOURCE_FFOSOURCE_Msk (0x1UL << RADIO_CSTONES_FFOSOURCE_FFOSOURCE_Pos) /*!< Bit mask of FFOSOURCE - field.*/ - #define RADIO_CSTONES_FFOSOURCE_FFOSOURCE_Min (0x0UL) /*!< Min enumerator value of FFOSOURCE field. */ - #define RADIO_CSTONES_FFOSOURCE_FFOSOURCE_Max (0x1UL) /*!< Max enumerator value of FFOSOURCE field. */ - #define RADIO_CSTONES_FFOSOURCE_FFOSOURCE_External (0x0UL) /*!< Use FFOIN */ - #define RADIO_CSTONES_FFOSOURCE_FFOSOURCE_Internal (0x1UL) /*!< Calc FFO from CnAcc */ - - /* RADIO_CSTONES_FAEPEER: FAEPEER (Frequency Actuation Error) of peer if known. Used during Mode 0 steps. */ #define RADIO_CSTONES_FAEPEER_ResetValue (0x00000000UL) /*!< Reset value of FAEPEER register. */ @@ -18743,18 +18811,6 @@ typedef struct { #define RADIO_CSTONES_MAGSTD_MAGSTD_Msk (0xFFFFUL << RADIO_CSTONES_MAGSTD_MAGSTD_Pos) /*!< Bit mask of MAGSTD field. */ -/* RADIO_CSTONES_CNACC: Output of the autocorrelation of the accumulated IQ signal */ - #define RADIO_CSTONES_CNACC_ResetValue (0x00000000UL) /*!< Reset value of CNACC register. */ - -/* CNACCI @Bits 0..15 : (unspecified) */ - #define RADIO_CSTONES_CNACC_CNACCI_Pos (0UL) /*!< Position of CNACCI field. */ - #define RADIO_CSTONES_CNACC_CNACCI_Msk (0xFFFFUL << RADIO_CSTONES_CNACC_CNACCI_Pos) /*!< Bit mask of CNACCI field. */ - -/* CNACCQ @Bits 16..31 : (unspecified) */ - #define RADIO_CSTONES_CNACC_CNACCQ_Pos (16UL) /*!< Position of CNACCQ field. */ - #define RADIO_CSTONES_CNACC_CNACCQ_Msk (0xFFFFUL << RADIO_CSTONES_CNACC_CNACCQ_Pos) /*!< Bit mask of CNACCQ field. */ - - /* RADIO_CSTONES_FFOEST: FFO estimate */ #define RADIO_CSTONES_FFOEST_ResetValue (0x00000000UL) /*!< Reset value of FFOEST register. */ @@ -18784,24 +18840,6 @@ typedef struct { #define RADIO_CSTONES_DOWNSAMPLE_RATE_BLE2m (0x1UL) /*!< Radio mode BLE2M is used */ -/* RADIO_CSTONES_FINETUNENEXT: Number of full ADPLL finetune steps */ - #define RADIO_CSTONES_FINETUNENEXT_ResetValue (0x00000000UL) /*!< Reset value of FINETUNENEXT register. */ - -/* FINETUNENEXT @Bits 0..12 : Units of 488.28125 Hz */ - #define RADIO_CSTONES_FINETUNENEXT_FINETUNENEXT_Pos (0UL) /*!< Position of FINETUNENEXT field. */ - #define RADIO_CSTONES_FINETUNENEXT_FINETUNENEXT_Msk (0x1FFFUL << RADIO_CSTONES_FINETUNENEXT_FINETUNENEXT_Pos) /*!< Bit mask of - FINETUNENEXT field.*/ - - -/* RADIO_CSTONES_CFOPHASE: Cordic output of CnAcc */ - #define RADIO_CSTONES_CFOPHASE_ResetValue (0x00000000UL) /*!< Reset value of CFOPHASE register. */ - -/* CFOPHASE @Bits 0..15 : (unspecified) */ - #define RADIO_CSTONES_CFOPHASE_CFOPHASE_Pos (0UL) /*!< Position of CFOPHASE field. */ - #define RADIO_CSTONES_CFOPHASE_CFOPHASE_Msk (0xFFFFUL << RADIO_CSTONES_CFOPHASE_CFOPHASE_Pos) /*!< Bit mask of CFOPHASE - field.*/ - - /* RADIO_CSTONES_FREQOFFSET: Frequency offset estimate */ #define RADIO_CSTONES_FREQOFFSET_ResetValue (0x00000000UL) /*!< Reset value of FREQOFFSET register. */ @@ -18811,28 +18849,6 @@ typedef struct { FREQOFFSET field.*/ -/* RADIO_CSTONES_PCT11: Mean magnitude and mean phase converted to IQ. IQ values limited to [-1024,1023]. */ - #define RADIO_CSTONES_PCT11_ResetValue (0x00000000UL) /*!< Reset value of PCT11 register. */ - -/* PCT11I @Bits 0..10 : Inphase */ - #define RADIO_CSTONES_PCT11_PCT11I_Pos (0UL) /*!< Position of PCT11I field. */ - #define RADIO_CSTONES_PCT11_PCT11I_Msk (0x7FFUL << RADIO_CSTONES_PCT11_PCT11I_Pos) /*!< Bit mask of PCT11I field. */ - -/* PCT11Q @Bits 11..21 : Quadrature */ - #define RADIO_CSTONES_PCT11_PCT11Q_Pos (11UL) /*!< Position of PCT11Q field. */ - #define RADIO_CSTONES_PCT11_PCT11Q_Msk (0x7FFUL << RADIO_CSTONES_PCT11_PCT11Q_Pos) /*!< Bit mask of PCT11Q field. */ - - -/* RADIO_CSTONES_LFAENEXT: Quantization error between ADPLL frequency and the desired value of FFO * RF Frequency. Values - limited to [-64,63] with units 7.6294 Hz. */ - - #define RADIO_CSTONES_LFAENEXT_ResetValue (0x00000000UL) /*!< Reset value of LFAENEXT register. */ - -/* LFAENEXT @Bits 0..6 : Inphase */ - #define RADIO_CSTONES_LFAENEXT_LFAENEXT_Pos (0UL) /*!< Position of LFAENEXT field. */ - #define RADIO_CSTONES_LFAENEXT_LFAENEXT_Msk (0x7FUL << RADIO_CSTONES_LFAENEXT_LFAENEXT_Pos) /*!< Bit mask of LFAENEXT field. */ - - /* ==================================================== Struct RADIO_RTT ===================================================== */ /** @@ -18937,11 +18953,17 @@ typedef struct { __OM uint32_t TASKS_CCASTART; /*!< (@ 0x00000028) Start the clear channel assessment used in IEEE 802.15.4 mode*/ __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x0000002C) Stop the clear channel assessment */ - __IM uint32_t RESERVED[29]; + __IM uint32_t RESERVED[2]; + __OM uint32_t TASKS_AUXDATADMASTART; /*!< (@ 0x00000038) Start DMA transaction of acquisition */ + __OM uint32_t TASKS_AUXDATADMASTOP; /*!< (@ 0x0000003C) Stop ongoing DMA transaction of acquisition */ + __IM uint32_t RESERVED1[11]; + __OM uint32_t TASKS_PLLEN; /*!< (@ 0x0000006C) Enable RADIO in PLL mode (standby for either TX or RX)*/ + __IM uint32_t RESERVED2[12]; + __OM uint32_t TASKS_CSTONESSTART; /*!< (@ 0x000000A0) Start tone processing for channel sounding */ __OM uint32_t TASKS_SOFTRESET; /*!< (@ 0x000000A4) Reset all public registers, but with these exceptions: DMA registers and EVENT/INTEN/SUBSCRIBE/PUBLISH registers. Only to be used in DISABLED state.*/ - __IM uint32_t RESERVED1[22]; + __IM uint32_t RESERVED3[22]; __IOM uint32_t SUBSCRIBE_TXEN; /*!< (@ 0x00000100) Subscribe configuration for task TXEN */ __IOM uint32_t SUBSCRIBE_RXEN; /*!< (@ 0x00000104) Subscribe configuration for task RXEN */ __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000108) Subscribe configuration for task START */ @@ -18954,9 +18976,15 @@ typedef struct { __IOM uint32_t SUBSCRIBE_EDSTOP; /*!< (@ 0x00000124) Subscribe configuration for task EDSTOP */ __IOM uint32_t SUBSCRIBE_CCASTART; /*!< (@ 0x00000128) Subscribe configuration for task CCASTART */ __IOM uint32_t SUBSCRIBE_CCASTOP; /*!< (@ 0x0000012C) Subscribe configuration for task CCASTOP */ - __IM uint32_t RESERVED2[29]; + __IM uint32_t RESERVED4[2]; + __IOM uint32_t SUBSCRIBE_AUXDATADMASTART; /*!< (@ 0x00000138) Subscribe configuration for task AUXDATADMASTART */ + __IOM uint32_t SUBSCRIBE_AUXDATADMASTOP; /*!< (@ 0x0000013C) Subscribe configuration for task AUXDATADMASTOP */ + __IM uint32_t RESERVED5[11]; + __IOM uint32_t SUBSCRIBE_PLLEN; /*!< (@ 0x0000016C) Subscribe configuration for task PLLEN */ + __IM uint32_t RESERVED6[12]; + __IOM uint32_t SUBSCRIBE_CSTONESSTART; /*!< (@ 0x000001A0) Subscribe configuration for task CSTONESSTART */ __IOM uint32_t SUBSCRIBE_SOFTRESET; /*!< (@ 0x000001A4) Subscribe configuration for task SOFTRESET */ - __IM uint32_t RESERVED3[22]; + __IM uint32_t RESERVED7[22]; __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000200) RADIO has ramped up and is ready to be started */ __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000204) RADIO has ramped up and is ready to be started TX path*/ __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000208) RADIO has ramped up and is ready to be started RX path*/ @@ -18972,7 +19000,7 @@ typedef struct { packet*/ __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x0000022C) Packet received with CRC ok */ __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000230) Packet received with CRC error */ - __IM uint32_t RESERVED4; + __IM uint32_t RESERVED8; __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000238) Bit counter reached bit count value */ __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000023C) Sampling of energy detection complete (a new ED sample is ready for readout from the RADIO.EDSAMPLE register)*/ @@ -18985,7 +19013,15 @@ typedef struct { __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x00000254) MAC header match found */ __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000258) Initial sync detected */ __IOM uint32_t EVENTS_CTEPRESENT; /*!< (@ 0x0000025C) CTEInfo byte is received */ - __IM uint32_t RESERVED5[40]; + __IM uint32_t RESERVED9[20]; + __IOM uint32_t EVENTS_PLLREADY; /*!< (@ 0x000002B0) PLL has settled and RADIO is ready to be enabled in + either TX or RX mode*/ + __IM uint32_t RESERVED10[2]; + __IOM uint32_t EVENTS_RXADDRESS; /*!< (@ 0x000002BC) Address received */ + __IOM uint32_t EVENTS_AUXDATADMAEND; /*!< (@ 0x000002C0) AUXDATA DMA end */ + __IM uint32_t RESERVED11; + __IOM uint32_t EVENTS_CSTONESEND; /*!< (@ 0x000002C8) The channel sounding tone processing is complete */ + __IM uint32_t RESERVED12[13]; __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000300) Publish configuration for event READY */ __IOM uint32_t PUBLISH_TXREADY; /*!< (@ 0x00000304) Publish configuration for event TXREADY */ __IOM uint32_t PUBLISH_RXREADY; /*!< (@ 0x00000308) Publish configuration for event RXREADY */ @@ -18999,7 +19035,7 @@ typedef struct { __IOM uint32_t PUBLISH_DEVMISS; /*!< (@ 0x00000328) Publish configuration for event DEVMISS */ __IOM uint32_t PUBLISH_CRCOK; /*!< (@ 0x0000032C) Publish configuration for event CRCOK */ __IOM uint32_t PUBLISH_CRCERROR; /*!< (@ 0x00000330) Publish configuration for event CRCERROR */ - __IM uint32_t RESERVED6; + __IM uint32_t RESERVED13; __IOM uint32_t PUBLISH_BCMATCH; /*!< (@ 0x00000338) Publish configuration for event BCMATCH */ __IOM uint32_t PUBLISH_EDEND; /*!< (@ 0x0000033C) Publish configuration for event EDEND */ __IOM uint32_t PUBLISH_EDSTOPPED; /*!< (@ 0x00000340) Publish configuration for event EDSTOPPED */ @@ -19010,56 +19046,78 @@ typedef struct { __IOM uint32_t PUBLISH_MHRMATCH; /*!< (@ 0x00000354) Publish configuration for event MHRMATCH */ __IOM uint32_t PUBLISH_SYNC; /*!< (@ 0x00000358) Publish configuration for event SYNC */ __IOM uint32_t PUBLISH_CTEPRESENT; /*!< (@ 0x0000035C) Publish configuration for event CTEPRESENT */ - __IM uint32_t RESERVED7[40]; + __IM uint32_t RESERVED14[20]; + __IOM uint32_t PUBLISH_PLLREADY; /*!< (@ 0x000003B0) Publish configuration for event PLLREADY */ + __IM uint32_t RESERVED15[2]; + __IOM uint32_t PUBLISH_RXADDRESS; /*!< (@ 0x000003BC) Publish configuration for event RXADDRESS */ + __IOM uint32_t PUBLISH_AUXDATADMAEND; /*!< (@ 0x000003C0) Publish configuration for event AUXDATADMAEND */ + __IM uint32_t RESERVED16; + __IOM uint32_t PUBLISH_CSTONESEND; /*!< (@ 0x000003C8) Publish configuration for event CSTONESEND */ + __IM uint32_t RESERVED17[13]; __IOM uint32_t SHORTS; /*!< (@ 0x00000400) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED8[33]; + __IM uint32_t RESERVED18[33]; __IOM uint32_t INTENSET00; /*!< (@ 0x00000488) Enable interrupt */ - __IM uint32_t RESERVED9; + __IOM uint32_t INTENSET01; /*!< (@ 0x0000048C) Enable interrupt */ __IOM uint32_t INTENCLR00; /*!< (@ 0x00000490) Disable interrupt */ - __IM uint32_t RESERVED10[5]; + __IOM uint32_t INTENCLR01; /*!< (@ 0x00000494) Disable interrupt */ + __IM uint32_t RESERVED19[4]; __IOM uint32_t INTENSET10; /*!< (@ 0x000004A8) Enable interrupt */ - __IM uint32_t RESERVED11; + __IOM uint32_t INTENSET11; /*!< (@ 0x000004AC) Enable interrupt */ __IOM uint32_t INTENCLR10; /*!< (@ 0x000004B0) Disable interrupt */ - __IM uint32_t RESERVED12[19]; + __IOM uint32_t INTENCLR11; /*!< (@ 0x000004B4) Disable interrupt */ + __IM uint32_t RESERVED20[18]; __IOM uint32_t MODE; /*!< (@ 0x00000500) Data rate and modulation */ - __IM uint32_t RESERVED13[7]; + __IM uint32_t RESERVED21[5]; + __IOM uint32_t PHYENDTXDELAY; /*!< (@ 0x00000518) Configurable delay of PHYEND event for TX */ + __IM uint32_t RESERVED22; __IM uint32_t STATE; /*!< (@ 0x00000520) Current radio state */ - __IM uint32_t RESERVED14[3]; + __IM uint32_t RESERVED23[3]; __IOM uint32_t EDCTRL; /*!< (@ 0x00000530) IEEE 802.15.4 energy detect control */ __IM uint32_t EDSAMPLE; /*!< (@ 0x00000534) IEEE 802.15.4 energy detect level */ __IOM uint32_t CCACTRL; /*!< (@ 0x00000538) IEEE 802.15.4 clear channel assessment control */ - __IM uint32_t RESERVED15; + __IM uint32_t RESERVED24; __IOM uint32_t DATAWHITE; /*!< (@ 0x00000540) Data whitening configuration */ - __IM uint32_t RESERVED16[112]; + __IM uint32_t RESERVED25; + __IOM NRF_RADIO_AUXDATA_Type AUXDATA; /*!< (@ 0x00000548) (unspecified) */ + __IOM NRF_RADIO_AUXDATADMA_Type AUXDATADMA[2]; /*!< (@ 0x00000550) (unspecified) */ + __IM uint32_t RESERVED26[101]; __IOM uint32_t TIMING; /*!< (@ 0x00000704) Timing */ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000708) Frequency */ - __IM uint32_t RESERVED17; + __IM uint32_t RESERVED27; __IOM uint32_t TXPOWER; /*!< (@ 0x00000710) Output power */ __IOM uint32_t TIFS; /*!< (@ 0x00000714) Interframe spacing in us */ __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000718) RSSI sample */ - __IM uint32_t RESERVED18[123]; + __IM uint32_t RESERVED28[45]; + __IOM NRF_RADIO_RXGAIN_Type RXGAIN; /*!< (@ 0x000007D0) (unspecified) */ + __IM uint32_t RESERVED29[11]; + __IOM uint32_t FREQFINETUNE; /*!< (@ 0x00000804) Fine tuning of the RF frequency */ + __IM uint32_t RESERVED30[64]; __IOM uint32_t FECONFIG; /*!< (@ 0x00000908) Config register */ - __IM uint32_t RESERVED19[253]; + __IM uint32_t RESERVED31[125]; + __IM uint32_t CFO_STAT; /*!< (@ 0x00000B00) Carrier freq. offset estimate */ + __IM uint32_t RESERVED32[15]; + __IOM uint32_t DBCCORR; /*!< (@ 0x00000B40) Correlator thresholds */ + __IM uint32_t RESERVED33[111]; __IOM uint32_t DFEMODE; /*!< (@ 0x00000D00) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)*/ __IM uint32_t DFESTATUS; /*!< (@ 0x00000D04) DFE status information */ - __IM uint32_t RESERVED20[2]; + __IM uint32_t RESERVED34[2]; __IOM uint32_t DFECTRL1; /*!< (@ 0x00000D10) Various configuration for Direction finding */ __IOM uint32_t DFECTRL2; /*!< (@ 0x00000D14) Start offset for Direction finding */ - __IM uint32_t RESERVED21[4]; + __IM uint32_t RESERVED35[4]; __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000D28) GPIO patterns to be used for each antenna */ __OM uint32_t CLEARPATTERN; /*!< (@ 0x00000D2C) Clear the GPIO pattern array for antenna control */ __IOM NRF_RADIO_PSEL_Type PSEL; /*!< (@ 0x00000D30) (unspecified) */ - __IM uint32_t RESERVED22; + __IM uint32_t RESERVED36; __IOM NRF_RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000D50) DFE packet EasyDMA channel */ - __IM uint32_t RESERVED23[43]; + __IM uint32_t RESERVED37[43]; __IM uint32_t CRCSTATUS; /*!< (@ 0x00000E0C) CRC status */ __IM uint32_t RXMATCH; /*!< (@ 0x00000E10) Received address */ __IM uint32_t RXCRC; /*!< (@ 0x00000E14) CRC field of previously received packet */ __IM uint32_t DAI; /*!< (@ 0x00000E18) Device address match index */ __IM uint32_t PDUSTAT; /*!< (@ 0x00000E1C) Payload status */ __IOM uint32_t PCNF0; /*!< (@ 0x00000E20) Packet configuration register 0 */ - __IM uint32_t RESERVED24; + __IM uint32_t RESERVED38; __IOM uint32_t PCNF1; /*!< (@ 0x00000E28) Packet configuration register 1 */ __IOM uint32_t BASE0; /*!< (@ 0x00000E2C) Base address 0 */ __IOM uint32_t BASE1; /*!< (@ 0x00000E30) Base address 1 */ @@ -19074,17 +19132,18 @@ typedef struct { __IOM uint32_t DAP[8]; /*!< (@ 0x00000E70) Device address prefix n */ __IOM uint32_t DACNF; /*!< (@ 0x00000E90) Device address match configuration */ __IOM uint32_t BCC; /*!< (@ 0x00000E94) Bit counter compare */ - __IM uint32_t RESERVED25[3]; + __IM uint32_t RESERVED39[3]; __IM uint32_t CTESTATUS; /*!< (@ 0x00000EA4) CTEInfo parsed from received packet */ - __IM uint32_t RESERVED26[3]; + __IM uint32_t RESERVED40[3]; __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000EB4) Search pattern configuration */ __IOM uint32_t MHRMATCHMASK; /*!< (@ 0x00000EB8) Pattern mask */ __IOM uint32_t SFD; /*!< (@ 0x00000EBC) IEEE 802.15.4 start of frame delimiter */ __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000EC0) Configuration for CTE inline mode */ - __IM uint32_t RESERVED27[3]; + __IM uint32_t RESERVED41[3]; __IOM uint32_t PACKETPTR; /*!< (@ 0x00000ED0) Packet pointer */ - __IM uint32_t RESERVED28[75]; + __IM uint32_t RESERVED42[75]; __IOM NRF_RADIO_CSTONES_Type CSTONES; /*!< (@ 0x00001000) (unspecified) */ + __IM uint32_t RESERVED43[2]; __IOM NRF_RADIO_RTT_Type RTT; /*!< (@ 0x00001050) (unspecified) */ } NRF_RADIO_Type; /*!< Size = 4196 (0x1064) */ @@ -19228,6 +19287,55 @@ typedef struct { #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (0x1UL) /*!< Trigger task */ +/* RADIO_TASKS_AUXDATADMASTART: Start DMA transaction of acquisition */ + #define RADIO_TASKS_AUXDATADMASTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_AUXDATADMASTART register. */ + +/* TASKS_AUXDATADMASTART @Bit 0 : Start DMA transaction of acquisition */ + #define RADIO_TASKS_AUXDATADMASTART_TASKS_AUXDATADMASTART_Pos (0UL) /*!< Position of TASKS_AUXDATADMASTART field. */ + #define RADIO_TASKS_AUXDATADMASTART_TASKS_AUXDATADMASTART_Msk (0x1UL << RADIO_TASKS_AUXDATADMASTART_TASKS_AUXDATADMASTART_Pos) + /*!< Bit mask of TASKS_AUXDATADMASTART field.*/ + #define RADIO_TASKS_AUXDATADMASTART_TASKS_AUXDATADMASTART_Min (0x1UL) /*!< Min enumerator value of TASKS_AUXDATADMASTART + field.*/ + #define RADIO_TASKS_AUXDATADMASTART_TASKS_AUXDATADMASTART_Max (0x1UL) /*!< Max enumerator value of TASKS_AUXDATADMASTART + field.*/ + #define RADIO_TASKS_AUXDATADMASTART_TASKS_AUXDATADMASTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_AUXDATADMASTOP: Stop ongoing DMA transaction of acquisition */ + #define RADIO_TASKS_AUXDATADMASTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_AUXDATADMASTOP register. */ + +/* TASKS_AUXDATADMASTOP @Bit 0 : Stop ongoing DMA transaction of acquisition */ + #define RADIO_TASKS_AUXDATADMASTOP_TASKS_AUXDATADMASTOP_Pos (0UL) /*!< Position of TASKS_AUXDATADMASTOP field. */ + #define RADIO_TASKS_AUXDATADMASTOP_TASKS_AUXDATADMASTOP_Msk (0x1UL << RADIO_TASKS_AUXDATADMASTOP_TASKS_AUXDATADMASTOP_Pos) + /*!< Bit mask of TASKS_AUXDATADMASTOP field.*/ + #define RADIO_TASKS_AUXDATADMASTOP_TASKS_AUXDATADMASTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_AUXDATADMASTOP field. */ + #define RADIO_TASKS_AUXDATADMASTOP_TASKS_AUXDATADMASTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_AUXDATADMASTOP field. */ + #define RADIO_TASKS_AUXDATADMASTOP_TASKS_AUXDATADMASTOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_PLLEN: Enable RADIO in PLL mode (standby for either TX or RX) */ + #define RADIO_TASKS_PLLEN_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PLLEN register. */ + +/* TASKS_PLLEN @Bit 0 : Enable RADIO in PLL mode (standby for either TX or RX) */ + #define RADIO_TASKS_PLLEN_TASKS_PLLEN_Pos (0UL) /*!< Position of TASKS_PLLEN field. */ + #define RADIO_TASKS_PLLEN_TASKS_PLLEN_Msk (0x1UL << RADIO_TASKS_PLLEN_TASKS_PLLEN_Pos) /*!< Bit mask of TASKS_PLLEN field. */ + #define RADIO_TASKS_PLLEN_TASKS_PLLEN_Min (0x1UL) /*!< Min enumerator value of TASKS_PLLEN field. */ + #define RADIO_TASKS_PLLEN_TASKS_PLLEN_Max (0x1UL) /*!< Max enumerator value of TASKS_PLLEN field. */ + #define RADIO_TASKS_PLLEN_TASKS_PLLEN_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_CSTONESSTART: Start tone processing for channel sounding */ + #define RADIO_TASKS_CSTONESSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CSTONESSTART register. */ + +/* TASKS_CSTONESSTART @Bit 0 : Start tone processing for channel sounding */ + #define RADIO_TASKS_CSTONESSTART_TASKS_CSTONESSTART_Pos (0UL) /*!< Position of TASKS_CSTONESSTART field. */ + #define RADIO_TASKS_CSTONESSTART_TASKS_CSTONESSTART_Msk (0x1UL << RADIO_TASKS_CSTONESSTART_TASKS_CSTONESSTART_Pos) /*!< Bit + mask of TASKS_CSTONESSTART field.*/ + #define RADIO_TASKS_CSTONESSTART_TASKS_CSTONESSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_CSTONESSTART field. */ + #define RADIO_TASKS_CSTONESSTART_TASKS_CSTONESSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_CSTONESSTART field. */ + #define RADIO_TASKS_CSTONESSTART_TASKS_CSTONESSTART_Trigger (0x1UL) /*!< Trigger task */ + + /* RADIO_TASKS_SOFTRESET: Reset all public registers, but with these exceptions: DMA registers and EVENT/INTEN/SUBSCRIBE/PUBLISH registers. Only to be used in DISABLED state. */ @@ -19460,6 +19568,81 @@ typedef struct { #define RADIO_SUBSCRIBE_CCASTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ +/* RADIO_SUBSCRIBE_AUXDATADMASTART: Subscribe configuration for task AUXDATADMASTART */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_AUXDATADMASTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task AUXDATADMASTART will subscribe to */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_AUXDATADMASTART_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_AUXDATADMASTART_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_AUXDATADMASTOP: Subscribe configuration for task AUXDATADMASTOP */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_AUXDATADMASTOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task AUXDATADMASTOP will subscribe to */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_AUXDATADMASTOP_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_AUXDATADMASTOP_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_PLLEN: Subscribe configuration for task PLLEN */ + #define RADIO_SUBSCRIBE_PLLEN_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_PLLEN register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task PLLEN will subscribe to */ + #define RADIO_SUBSCRIBE_PLLEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_PLLEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_PLLEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_PLLEN_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_PLLEN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_PLLEN_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_PLLEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_PLLEN_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_PLLEN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_PLLEN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_PLLEN_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_PLLEN_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_CSTONESSTART: Subscribe configuration for task CSTONESSTART */ + #define RADIO_SUBSCRIBE_CSTONESSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CSTONESSTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CSTONESSTART will subscribe to */ + #define RADIO_SUBSCRIBE_CSTONESSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_CSTONESSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CSTONESSTART_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define RADIO_SUBSCRIBE_CSTONESSTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_CSTONESSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_CSTONESSTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_CSTONESSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CSTONESSTART_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_CSTONESSTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_CSTONESSTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_CSTONESSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_CSTONESSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ + + /* RADIO_SUBSCRIBE_SOFTRESET: Subscribe configuration for task SOFTRESET */ #define RADIO_SUBSCRIBE_SOFTRESET_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SOFTRESET register. */ @@ -19779,6 +19962,58 @@ typedef struct { #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Generated (0x1UL) /*!< Event generated */ +/* RADIO_EVENTS_PLLREADY: PLL has settled and RADIO is ready to be enabled in either TX or RX mode */ + #define RADIO_EVENTS_PLLREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PLLREADY register. */ + +/* EVENTS_PLLREADY @Bit 0 : PLL has settled and RADIO is ready to be enabled in either TX or RX mode */ + #define RADIO_EVENTS_PLLREADY_EVENTS_PLLREADY_Pos (0UL) /*!< Position of EVENTS_PLLREADY field. */ + #define RADIO_EVENTS_PLLREADY_EVENTS_PLLREADY_Msk (0x1UL << RADIO_EVENTS_PLLREADY_EVENTS_PLLREADY_Pos) /*!< Bit mask of + EVENTS_PLLREADY field.*/ + #define RADIO_EVENTS_PLLREADY_EVENTS_PLLREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_PLLREADY field. */ + #define RADIO_EVENTS_PLLREADY_EVENTS_PLLREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_PLLREADY field. */ + #define RADIO_EVENTS_PLLREADY_EVENTS_PLLREADY_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_PLLREADY_EVENTS_PLLREADY_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_RXADDRESS: Address received */ + #define RADIO_EVENTS_RXADDRESS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXADDRESS register. */ + +/* EVENTS_RXADDRESS @Bit 0 : Address received */ + #define RADIO_EVENTS_RXADDRESS_EVENTS_RXADDRESS_Pos (0UL) /*!< Position of EVENTS_RXADDRESS field. */ + #define RADIO_EVENTS_RXADDRESS_EVENTS_RXADDRESS_Msk (0x1UL << RADIO_EVENTS_RXADDRESS_EVENTS_RXADDRESS_Pos) /*!< Bit mask of + EVENTS_RXADDRESS field.*/ + #define RADIO_EVENTS_RXADDRESS_EVENTS_RXADDRESS_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXADDRESS field. */ + #define RADIO_EVENTS_RXADDRESS_EVENTS_RXADDRESS_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXADDRESS field. */ + #define RADIO_EVENTS_RXADDRESS_EVENTS_RXADDRESS_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_RXADDRESS_EVENTS_RXADDRESS_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_AUXDATADMAEND: AUXDATA DMA end */ + #define RADIO_EVENTS_AUXDATADMAEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_AUXDATADMAEND register. */ + +/* EVENTS_AUXDATADMAEND @Bit 0 : AUXDATA DMA end */ + #define RADIO_EVENTS_AUXDATADMAEND_EVENTS_AUXDATADMAEND_Pos (0UL) /*!< Position of EVENTS_AUXDATADMAEND field. */ + #define RADIO_EVENTS_AUXDATADMAEND_EVENTS_AUXDATADMAEND_Msk (0x1UL << RADIO_EVENTS_AUXDATADMAEND_EVENTS_AUXDATADMAEND_Pos) + /*!< Bit mask of EVENTS_AUXDATADMAEND field.*/ + #define RADIO_EVENTS_AUXDATADMAEND_EVENTS_AUXDATADMAEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_AUXDATADMAEND field. */ + #define RADIO_EVENTS_AUXDATADMAEND_EVENTS_AUXDATADMAEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_AUXDATADMAEND field. */ + #define RADIO_EVENTS_AUXDATADMAEND_EVENTS_AUXDATADMAEND_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_AUXDATADMAEND_EVENTS_AUXDATADMAEND_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_CSTONESEND: The channel sounding tone processing is complete */ + #define RADIO_EVENTS_CSTONESEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CSTONESEND register. */ + +/* EVENTS_CSTONESEND @Bit 0 : The channel sounding tone processing is complete */ + #define RADIO_EVENTS_CSTONESEND_EVENTS_CSTONESEND_Pos (0UL) /*!< Position of EVENTS_CSTONESEND field. */ + #define RADIO_EVENTS_CSTONESEND_EVENTS_CSTONESEND_Msk (0x1UL << RADIO_EVENTS_CSTONESEND_EVENTS_CSTONESEND_Pos) /*!< Bit mask + of EVENTS_CSTONESEND field.*/ + #define RADIO_EVENTS_CSTONESEND_EVENTS_CSTONESEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_CSTONESEND field. */ + #define RADIO_EVENTS_CSTONESEND_EVENTS_CSTONESEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_CSTONESEND field. */ + #define RADIO_EVENTS_CSTONESEND_EVENTS_CSTONESEND_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_CSTONESEND_EVENTS_CSTONESEND_Generated (0x1UL) /*!< Event generated */ + + /* RADIO_PUBLISH_READY: Publish configuration for event READY */ #define RADIO_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY register. */ @@ -20193,6 +20428,78 @@ typedef struct { #define RADIO_PUBLISH_CTEPRESENT_EN_Enabled (0x1UL) /*!< Enable publishing */ +/* RADIO_PUBLISH_PLLREADY: Publish configuration for event PLLREADY */ + #define RADIO_PUBLISH_PLLREADY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PLLREADY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event PLLREADY will publish to */ + #define RADIO_PUBLISH_PLLREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_PLLREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PLLREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_PLLREADY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_PLLREADY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_PLLREADY_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_PLLREADY_EN_Msk (0x1UL << RADIO_PUBLISH_PLLREADY_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_PLLREADY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_PLLREADY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_PLLREADY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_PLLREADY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_RXADDRESS: Publish configuration for event RXADDRESS */ + #define RADIO_PUBLISH_RXADDRESS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXADDRESS register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RXADDRESS will publish to */ + #define RADIO_PUBLISH_RXADDRESS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_RXADDRESS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RXADDRESS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_RXADDRESS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_RXADDRESS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_RXADDRESS_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_RXADDRESS_EN_Msk (0x1UL << RADIO_PUBLISH_RXADDRESS_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_RXADDRESS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_RXADDRESS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_RXADDRESS_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_RXADDRESS_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_AUXDATADMAEND: Publish configuration for event AUXDATADMAEND */ + #define RADIO_PUBLISH_AUXDATADMAEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_AUXDATADMAEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event AUXDATADMAEND will publish to */ + #define RADIO_PUBLISH_AUXDATADMAEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_AUXDATADMAEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_AUXDATADMAEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define RADIO_PUBLISH_AUXDATADMAEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_AUXDATADMAEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_AUXDATADMAEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_AUXDATADMAEND_EN_Msk (0x1UL << RADIO_PUBLISH_AUXDATADMAEND_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_AUXDATADMAEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_AUXDATADMAEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_AUXDATADMAEND_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_AUXDATADMAEND_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_CSTONESEND: Publish configuration for event CSTONESEND */ + #define RADIO_PUBLISH_CSTONESEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CSTONESEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CSTONESEND will publish to */ + #define RADIO_PUBLISH_CSTONESEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_CSTONESEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CSTONESEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_CSTONESEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_CSTONESEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_CSTONESEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_CSTONESEND_EN_Msk (0x1UL << RADIO_PUBLISH_CSTONESEND_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_CSTONESEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_CSTONESEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_CSTONESEND_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_CSTONESEND_EN_Enabled (0x1UL) /*!< Enable publishing */ + + /* RADIO_SHORTS: Shortcuts between local events and tasks */ #define RADIO_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ @@ -20547,6 +20854,47 @@ typedef struct { #define RADIO_INTENSET00_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled */ +/* RADIO_INTENSET01: Enable interrupt */ + #define RADIO_INTENSET01_ResetValue (0x00000000UL) /*!< Reset value of INTENSET01 register. */ + +/* PLLREADY @Bit 12 : Write '1' to enable interrupt for event PLLREADY */ + #define RADIO_INTENSET01_PLLREADY_Pos (12UL) /*!< Position of PLLREADY field. */ + #define RADIO_INTENSET01_PLLREADY_Msk (0x1UL << RADIO_INTENSET01_PLLREADY_Pos) /*!< Bit mask of PLLREADY field. */ + #define RADIO_INTENSET01_PLLREADY_Min (0x0UL) /*!< Min enumerator value of PLLREADY field. */ + #define RADIO_INTENSET01_PLLREADY_Max (0x1UL) /*!< Max enumerator value of PLLREADY field. */ + #define RADIO_INTENSET01_PLLREADY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET01_PLLREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET01_PLLREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXADDRESS @Bit 15 : Write '1' to enable interrupt for event RXADDRESS */ + #define RADIO_INTENSET01_RXADDRESS_Pos (15UL) /*!< Position of RXADDRESS field. */ + #define RADIO_INTENSET01_RXADDRESS_Msk (0x1UL << RADIO_INTENSET01_RXADDRESS_Pos) /*!< Bit mask of RXADDRESS field. */ + #define RADIO_INTENSET01_RXADDRESS_Min (0x0UL) /*!< Min enumerator value of RXADDRESS field. */ + #define RADIO_INTENSET01_RXADDRESS_Max (0x1UL) /*!< Max enumerator value of RXADDRESS field. */ + #define RADIO_INTENSET01_RXADDRESS_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET01_RXADDRESS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET01_RXADDRESS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* AUXDATADMAEND @Bit 16 : Write '1' to enable interrupt for event AUXDATADMAEND */ + #define RADIO_INTENSET01_AUXDATADMAEND_Pos (16UL) /*!< Position of AUXDATADMAEND field. */ + #define RADIO_INTENSET01_AUXDATADMAEND_Msk (0x1UL << RADIO_INTENSET01_AUXDATADMAEND_Pos) /*!< Bit mask of AUXDATADMAEND + field.*/ + #define RADIO_INTENSET01_AUXDATADMAEND_Min (0x0UL) /*!< Min enumerator value of AUXDATADMAEND field. */ + #define RADIO_INTENSET01_AUXDATADMAEND_Max (0x1UL) /*!< Max enumerator value of AUXDATADMAEND field. */ + #define RADIO_INTENSET01_AUXDATADMAEND_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET01_AUXDATADMAEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET01_AUXDATADMAEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CSTONESEND @Bit 18 : Write '1' to enable interrupt for event CSTONESEND */ + #define RADIO_INTENSET01_CSTONESEND_Pos (18UL) /*!< Position of CSTONESEND field. */ + #define RADIO_INTENSET01_CSTONESEND_Msk (0x1UL << RADIO_INTENSET01_CSTONESEND_Pos) /*!< Bit mask of CSTONESEND field. */ + #define RADIO_INTENSET01_CSTONESEND_Min (0x0UL) /*!< Min enumerator value of CSTONESEND field. */ + #define RADIO_INTENSET01_CSTONESEND_Max (0x1UL) /*!< Max enumerator value of CSTONESEND field. */ + #define RADIO_INTENSET01_CSTONESEND_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET01_CSTONESEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET01_CSTONESEND_Enabled (0x1UL) /*!< Read: Enabled */ + + /* RADIO_INTENCLR00: Disable interrupt */ #define RADIO_INTENCLR00_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR00 register. */ @@ -20758,6 +21106,47 @@ typedef struct { #define RADIO_INTENCLR00_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled */ +/* RADIO_INTENCLR01: Disable interrupt */ + #define RADIO_INTENCLR01_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR01 register. */ + +/* PLLREADY @Bit 12 : Write '1' to disable interrupt for event PLLREADY */ + #define RADIO_INTENCLR01_PLLREADY_Pos (12UL) /*!< Position of PLLREADY field. */ + #define RADIO_INTENCLR01_PLLREADY_Msk (0x1UL << RADIO_INTENCLR01_PLLREADY_Pos) /*!< Bit mask of PLLREADY field. */ + #define RADIO_INTENCLR01_PLLREADY_Min (0x0UL) /*!< Min enumerator value of PLLREADY field. */ + #define RADIO_INTENCLR01_PLLREADY_Max (0x1UL) /*!< Max enumerator value of PLLREADY field. */ + #define RADIO_INTENCLR01_PLLREADY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR01_PLLREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR01_PLLREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXADDRESS @Bit 15 : Write '1' to disable interrupt for event RXADDRESS */ + #define RADIO_INTENCLR01_RXADDRESS_Pos (15UL) /*!< Position of RXADDRESS field. */ + #define RADIO_INTENCLR01_RXADDRESS_Msk (0x1UL << RADIO_INTENCLR01_RXADDRESS_Pos) /*!< Bit mask of RXADDRESS field. */ + #define RADIO_INTENCLR01_RXADDRESS_Min (0x0UL) /*!< Min enumerator value of RXADDRESS field. */ + #define RADIO_INTENCLR01_RXADDRESS_Max (0x1UL) /*!< Max enumerator value of RXADDRESS field. */ + #define RADIO_INTENCLR01_RXADDRESS_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR01_RXADDRESS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR01_RXADDRESS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* AUXDATADMAEND @Bit 16 : Write '1' to disable interrupt for event AUXDATADMAEND */ + #define RADIO_INTENCLR01_AUXDATADMAEND_Pos (16UL) /*!< Position of AUXDATADMAEND field. */ + #define RADIO_INTENCLR01_AUXDATADMAEND_Msk (0x1UL << RADIO_INTENCLR01_AUXDATADMAEND_Pos) /*!< Bit mask of AUXDATADMAEND + field.*/ + #define RADIO_INTENCLR01_AUXDATADMAEND_Min (0x0UL) /*!< Min enumerator value of AUXDATADMAEND field. */ + #define RADIO_INTENCLR01_AUXDATADMAEND_Max (0x1UL) /*!< Max enumerator value of AUXDATADMAEND field. */ + #define RADIO_INTENCLR01_AUXDATADMAEND_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR01_AUXDATADMAEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR01_AUXDATADMAEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CSTONESEND @Bit 18 : Write '1' to disable interrupt for event CSTONESEND */ + #define RADIO_INTENCLR01_CSTONESEND_Pos (18UL) /*!< Position of CSTONESEND field. */ + #define RADIO_INTENCLR01_CSTONESEND_Msk (0x1UL << RADIO_INTENCLR01_CSTONESEND_Pos) /*!< Bit mask of CSTONESEND field. */ + #define RADIO_INTENCLR01_CSTONESEND_Min (0x0UL) /*!< Min enumerator value of CSTONESEND field. */ + #define RADIO_INTENCLR01_CSTONESEND_Max (0x1UL) /*!< Max enumerator value of CSTONESEND field. */ + #define RADIO_INTENCLR01_CSTONESEND_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR01_CSTONESEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR01_CSTONESEND_Enabled (0x1UL) /*!< Read: Enabled */ + + /* RADIO_INTENSET10: Enable interrupt */ #define RADIO_INTENSET10_ResetValue (0x00000000UL) /*!< Reset value of INTENSET10 register. */ @@ -20969,6 +21358,47 @@ typedef struct { #define RADIO_INTENSET10_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled */ +/* RADIO_INTENSET11: Enable interrupt */ + #define RADIO_INTENSET11_ResetValue (0x00000000UL) /*!< Reset value of INTENSET11 register. */ + +/* PLLREADY @Bit 12 : Write '1' to enable interrupt for event PLLREADY */ + #define RADIO_INTENSET11_PLLREADY_Pos (12UL) /*!< Position of PLLREADY field. */ + #define RADIO_INTENSET11_PLLREADY_Msk (0x1UL << RADIO_INTENSET11_PLLREADY_Pos) /*!< Bit mask of PLLREADY field. */ + #define RADIO_INTENSET11_PLLREADY_Min (0x0UL) /*!< Min enumerator value of PLLREADY field. */ + #define RADIO_INTENSET11_PLLREADY_Max (0x1UL) /*!< Max enumerator value of PLLREADY field. */ + #define RADIO_INTENSET11_PLLREADY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET11_PLLREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET11_PLLREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXADDRESS @Bit 15 : Write '1' to enable interrupt for event RXADDRESS */ + #define RADIO_INTENSET11_RXADDRESS_Pos (15UL) /*!< Position of RXADDRESS field. */ + #define RADIO_INTENSET11_RXADDRESS_Msk (0x1UL << RADIO_INTENSET11_RXADDRESS_Pos) /*!< Bit mask of RXADDRESS field. */ + #define RADIO_INTENSET11_RXADDRESS_Min (0x0UL) /*!< Min enumerator value of RXADDRESS field. */ + #define RADIO_INTENSET11_RXADDRESS_Max (0x1UL) /*!< Max enumerator value of RXADDRESS field. */ + #define RADIO_INTENSET11_RXADDRESS_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET11_RXADDRESS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET11_RXADDRESS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* AUXDATADMAEND @Bit 16 : Write '1' to enable interrupt for event AUXDATADMAEND */ + #define RADIO_INTENSET11_AUXDATADMAEND_Pos (16UL) /*!< Position of AUXDATADMAEND field. */ + #define RADIO_INTENSET11_AUXDATADMAEND_Msk (0x1UL << RADIO_INTENSET11_AUXDATADMAEND_Pos) /*!< Bit mask of AUXDATADMAEND + field.*/ + #define RADIO_INTENSET11_AUXDATADMAEND_Min (0x0UL) /*!< Min enumerator value of AUXDATADMAEND field. */ + #define RADIO_INTENSET11_AUXDATADMAEND_Max (0x1UL) /*!< Max enumerator value of AUXDATADMAEND field. */ + #define RADIO_INTENSET11_AUXDATADMAEND_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET11_AUXDATADMAEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET11_AUXDATADMAEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CSTONESEND @Bit 18 : Write '1' to enable interrupt for event CSTONESEND */ + #define RADIO_INTENSET11_CSTONESEND_Pos (18UL) /*!< Position of CSTONESEND field. */ + #define RADIO_INTENSET11_CSTONESEND_Msk (0x1UL << RADIO_INTENSET11_CSTONESEND_Pos) /*!< Bit mask of CSTONESEND field. */ + #define RADIO_INTENSET11_CSTONESEND_Min (0x0UL) /*!< Min enumerator value of CSTONESEND field. */ + #define RADIO_INTENSET11_CSTONESEND_Max (0x1UL) /*!< Max enumerator value of CSTONESEND field. */ + #define RADIO_INTENSET11_CSTONESEND_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET11_CSTONESEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET11_CSTONESEND_Enabled (0x1UL) /*!< Read: Enabled */ + + /* RADIO_INTENCLR10: Disable interrupt */ #define RADIO_INTENCLR10_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR10 register. */ @@ -21180,6 +21610,47 @@ typedef struct { #define RADIO_INTENCLR10_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled */ +/* RADIO_INTENCLR11: Disable interrupt */ + #define RADIO_INTENCLR11_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR11 register. */ + +/* PLLREADY @Bit 12 : Write '1' to disable interrupt for event PLLREADY */ + #define RADIO_INTENCLR11_PLLREADY_Pos (12UL) /*!< Position of PLLREADY field. */ + #define RADIO_INTENCLR11_PLLREADY_Msk (0x1UL << RADIO_INTENCLR11_PLLREADY_Pos) /*!< Bit mask of PLLREADY field. */ + #define RADIO_INTENCLR11_PLLREADY_Min (0x0UL) /*!< Min enumerator value of PLLREADY field. */ + #define RADIO_INTENCLR11_PLLREADY_Max (0x1UL) /*!< Max enumerator value of PLLREADY field. */ + #define RADIO_INTENCLR11_PLLREADY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR11_PLLREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR11_PLLREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXADDRESS @Bit 15 : Write '1' to disable interrupt for event RXADDRESS */ + #define RADIO_INTENCLR11_RXADDRESS_Pos (15UL) /*!< Position of RXADDRESS field. */ + #define RADIO_INTENCLR11_RXADDRESS_Msk (0x1UL << RADIO_INTENCLR11_RXADDRESS_Pos) /*!< Bit mask of RXADDRESS field. */ + #define RADIO_INTENCLR11_RXADDRESS_Min (0x0UL) /*!< Min enumerator value of RXADDRESS field. */ + #define RADIO_INTENCLR11_RXADDRESS_Max (0x1UL) /*!< Max enumerator value of RXADDRESS field. */ + #define RADIO_INTENCLR11_RXADDRESS_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR11_RXADDRESS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR11_RXADDRESS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* AUXDATADMAEND @Bit 16 : Write '1' to disable interrupt for event AUXDATADMAEND */ + #define RADIO_INTENCLR11_AUXDATADMAEND_Pos (16UL) /*!< Position of AUXDATADMAEND field. */ + #define RADIO_INTENCLR11_AUXDATADMAEND_Msk (0x1UL << RADIO_INTENCLR11_AUXDATADMAEND_Pos) /*!< Bit mask of AUXDATADMAEND + field.*/ + #define RADIO_INTENCLR11_AUXDATADMAEND_Min (0x0UL) /*!< Min enumerator value of AUXDATADMAEND field. */ + #define RADIO_INTENCLR11_AUXDATADMAEND_Max (0x1UL) /*!< Max enumerator value of AUXDATADMAEND field. */ + #define RADIO_INTENCLR11_AUXDATADMAEND_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR11_AUXDATADMAEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR11_AUXDATADMAEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CSTONESEND @Bit 18 : Write '1' to disable interrupt for event CSTONESEND */ + #define RADIO_INTENCLR11_CSTONESEND_Pos (18UL) /*!< Position of CSTONESEND field. */ + #define RADIO_INTENCLR11_CSTONESEND_Msk (0x1UL << RADIO_INTENCLR11_CSTONESEND_Pos) /*!< Bit mask of CSTONESEND field. */ + #define RADIO_INTENCLR11_CSTONESEND_Min (0x0UL) /*!< Min enumerator value of CSTONESEND field. */ + #define RADIO_INTENCLR11_CSTONESEND_Max (0x1UL) /*!< Max enumerator value of CSTONESEND field. */ + #define RADIO_INTENCLR11_CSTONESEND_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR11_CSTONESEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR11_CSTONESEND_Enabled (0x1UL) /*!< Read: Enabled */ + + /* RADIO_MODE: Data rate and modulation */ #define RADIO_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ @@ -21199,6 +21670,30 @@ typedef struct { #define RADIO_MODE_MODE_Ieee802154_250Kbit (0xFUL) /*!< IEEE 802.15.4-2006 250 kbps */ +/* RADIO_PHYENDTXDELAY: Configurable delay of PHYEND event for TX */ + #define RADIO_PHYENDTXDELAY_ResetValue (0x00000421UL) /*!< Reset value of PHYENDTXDELAY register. */ + +/* RATE4M @Bits 0..2 : For modes with 4 Mbps on-air bit rate, unit is 2 bit periods (Nrf_4Mbit0_5 and Nrf_4Mbit0_25 modes) */ + #define RADIO_PHYENDTXDELAY_RATE4M_Pos (0UL) /*!< Position of RATE4M field. */ + #define RADIO_PHYENDTXDELAY_RATE4M_Msk (0x7UL << RADIO_PHYENDTXDELAY_RATE4M_Pos) /*!< Bit mask of RATE4M field. */ + +/* RATE2M @Bits 4..6 : For modes with 2 Mbps on-air bit rate, unit is 1 bit period (Nrf_2Mbit, Ble_2Mbit, and Ieee802154_250Kbit + modes) */ + + #define RADIO_PHYENDTXDELAY_RATE2M_Pos (4UL) /*!< Position of RATE2M field. */ + #define RADIO_PHYENDTXDELAY_RATE2M_Msk (0x7UL << RADIO_PHYENDTXDELAY_RATE2M_Pos) /*!< Bit mask of RATE2M field. */ + +/* RATE1M @Bits 8..10 : For modes with 1 Mbps on-air bit rate, unit is 1/2 bit period (Nrf_1Mbit, Ble_1Mbit, Ble_LR125Kbit, and + Ble_LR500Kbit modes) */ + + #define RADIO_PHYENDTXDELAY_RATE1M_Pos (8UL) /*!< Position of RATE1M field. */ + #define RADIO_PHYENDTXDELAY_RATE1M_Msk (0x7UL << RADIO_PHYENDTXDELAY_RATE1M_Pos) /*!< Bit mask of RATE1M field. */ + +/* RATE250K @Bits 12..14 : For modes with 250 kbps on-air bit rate, unit is 1/8 bit period (Nrf_250Kbit mode) */ + #define RADIO_PHYENDTXDELAY_RATE250K_Pos (12UL) /*!< Position of RATE250K field. */ + #define RADIO_PHYENDTXDELAY_RATE250K_Msk (0x7UL << RADIO_PHYENDTXDELAY_RATE250K_Pos) /*!< Bit mask of RATE250K field. */ + + /* RADIO_STATE: Current radio state */ #define RADIO_STATE_ResetValue (0x00000000UL) /*!< Reset value of STATE register. */ @@ -21377,6 +21872,17 @@ typedef struct { #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ +/* RADIO_FREQFINETUNE: Fine tuning of the RF frequency */ + #define RADIO_FREQFINETUNE_ResetValue (0x00000000UL) /*!< Reset value of FREQFINETUNE register. */ + +/* FREQFINETUNE @Bits 0..12 : Twos-complement number for fine-tuning the frequency. The step size is 488.28125 Hz, giving a + range from -1 MHz to (one step short of) +1 MHz. */ + + #define RADIO_FREQFINETUNE_FREQFINETUNE_Pos (0UL) /*!< Position of FREQFINETUNE field. */ + #define RADIO_FREQFINETUNE_FREQFINETUNE_Msk (0x1FFFUL << RADIO_FREQFINETUNE_FREQFINETUNE_Pos) /*!< Bit mask of FREQFINETUNE + field.*/ + + /* RADIO_FECONFIG: Config register */ #define RADIO_FECONFIG_ResetValue (0x10800005UL) /*!< Reset value of FECONFIG register. */ @@ -21389,6 +21895,26 @@ typedef struct { #define RADIO_FECONFIG_SCALERMODE_Enabled (0x1UL) /*!< LUT based scaling mode. */ +/* RADIO_CFO_STAT: Carrier freq. offset estimate */ + #define RADIO_CFO_STAT_ResetValue (0x00000000UL) /*!< Reset value of CFO_STAT register. */ + +/* SYNCOK @Bit 12 : SYNC ok */ + #define RADIO_CFO_STAT_SYNCOK_Pos (12UL) /*!< Position of SYNCOK field. */ + #define RADIO_CFO_STAT_SYNCOK_Msk (0x1UL << RADIO_CFO_STAT_SYNCOK_Pos) /*!< Bit mask of SYNCOK field. */ + #define RADIO_CFO_STAT_SYNCOK_Min (0x0UL) /*!< Min enumerator value of SYNCOK field. */ + #define RADIO_CFO_STAT_SYNCOK_Max (0x1UL) /*!< Max enumerator value of SYNCOK field. */ + #define RADIO_CFO_STAT_SYNCOK_SyncNotOK (0x0UL) /*!< (unspecified) */ + #define RADIO_CFO_STAT_SYNCOK_SyncOk (0x1UL) /*!< (unspecified) */ + + +/* RADIO_DBCCORR: Correlator thresholds */ + #define RADIO_DBCCORR_ResetValue (0x1FFFFF90UL) /*!< Reset value of DBCCORR register. */ + +/* TH @Bits 0..7 : Correlation threshold */ + #define RADIO_DBCCORR_TH_Pos (0UL) /*!< Position of TH field. */ + #define RADIO_DBCCORR_TH_Msk (0xFFUL << RADIO_DBCCORR_TH_Pos) /*!< Bit mask of TH field. */ + + /* RADIO_DFEMODE: Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) */ #define RADIO_DFEMODE_ResetValue (0x00000000UL) /*!< Reset value of DFEMODE register. */ @@ -22256,37 +22782,21 @@ typedef struct { #define REGULATORS_POFCON_THRESHOLD_Msk (0xFUL << REGULATORS_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ #define REGULATORS_POFCON_THRESHOLD_Min (0x0UL) /*!< Min enumerator value of THRESHOLD field. */ #define REGULATORS_POFCON_THRESHOLD_Max (0xFUL) /*!< Max enumerator value of THRESHOLD field. */ - #define REGULATORS_POFCON_THRESHOLD_V17 (0x0UL) /*!< Set threshold to 1.7 V for VDD */ #define REGULATORS_POFCON_THRESHOLD_V090 (0x0UL) /*!< Set threshold to 0.90 V for VDDL */ - #define REGULATORS_POFCON_THRESHOLD_V18 (0x1UL) /*!< Set threshold to 1.8 V for VDD */ #define REGULATORS_POFCON_THRESHOLD_V095 (0x1UL) /*!< Set threshold to 0.95 V for VDDL */ - #define REGULATORS_POFCON_THRESHOLD_V19 (0x2UL) /*!< Set threshold to 1.9 V for VDD */ #define REGULATORS_POFCON_THRESHOLD_V100 (0x2UL) /*!< Set threshold to 1.00 V for VDDL */ - #define REGULATORS_POFCON_THRESHOLD_V20 (0x3UL) /*!< Set threshold to 2.0 V for VDD */ #define REGULATORS_POFCON_THRESHOLD_V105 (0x3UL) /*!< Set threshold to 1.05 V for VDDL */ - #define REGULATORS_POFCON_THRESHOLD_V21 (0x4UL) /*!< Set threshold to 2.1 V for VDD */ #define REGULATORS_POFCON_THRESHOLD_V110 (0x4UL) /*!< Set threshold to 1.10 V for VDDL */ - #define REGULATORS_POFCON_THRESHOLD_V22 (0x5UL) /*!< Set threshold to 2.2 V for VDD */ #define REGULATORS_POFCON_THRESHOLD_V115 (0x5UL) /*!< Set threshold to 1.15 V for VDDL */ - #define REGULATORS_POFCON_THRESHOLD_V23 (0x6UL) /*!< Set threshold to 2.3 V for VDD */ #define REGULATORS_POFCON_THRESHOLD_V120 (0x6UL) /*!< Set threshold to 1.20 V for VDDL */ - #define REGULATORS_POFCON_THRESHOLD_V24 (0x7UL) /*!< Set threshold to 2.4 V for VDD */ #define REGULATORS_POFCON_THRESHOLD_V125 (0x7UL) /*!< Set threshold to 1.25 V for VDDL */ - #define REGULATORS_POFCON_THRESHOLD_V25 (0x8UL) /*!< Set threshold to 2.5 V for VDD */ #define REGULATORS_POFCON_THRESHOLD_V130 (0x8UL) /*!< Set threshold to 1.30 V for VDDL */ - #define REGULATORS_POFCON_THRESHOLD_V26 (0x9UL) /*!< Set threshold to 2.6 V for VDD */ #define REGULATORS_POFCON_THRESHOLD_V135 (0x9UL) /*!< Set threshold to 1.35 V for VDDL */ - #define REGULATORS_POFCON_THRESHOLD_V27 (0xAUL) /*!< Set threshold to 2.7 V for VDD */ #define REGULATORS_POFCON_THRESHOLD_V140 (0xAUL) /*!< Set threshold to 1.40 V for VDDL */ - #define REGULATORS_POFCON_THRESHOLD_V28 (0xBUL) /*!< Set threshold to 2.8 V for VDD */ #define REGULATORS_POFCON_THRESHOLD_V145 (0xBUL) /*!< Set threshold to 1.45 V for VDDL */ - #define REGULATORS_POFCON_THRESHOLD_V29 (0xCUL) /*!< Set threshold to 2.9 V for VDD */ #define REGULATORS_POFCON_THRESHOLD_V150 (0xCUL) /*!< Set threshold to 1.50 V for VDDL */ - #define REGULATORS_POFCON_THRESHOLD_V30 (0xDUL) /*!< Set threshold to 3.0 V for VDD */ #define REGULATORS_POFCON_THRESHOLD_V155 (0xDUL) /*!< Set threshold to 1.55 V for VDDL */ - #define REGULATORS_POFCON_THRESHOLD_V31 (0xEUL) /*!< Set threshold to 3.1 V for VDD */ #define REGULATORS_POFCON_THRESHOLD_V160 (0xEUL) /*!< Set threshold to 1.60 V for VDDL */ - #define REGULATORS_POFCON_THRESHOLD_V32 (0xFUL) /*!< Set threshold to 3.2 V for VDD */ #define REGULATORS_POFCON_THRESHOLD_V165 (0xFUL) /*!< Set threshold to 1.65 V for VDDL */ /* EVENTDISABLE @Bit 7 : Disable the POFWARN power-fail warning event */ @@ -22300,9 +22810,8 @@ typedef struct { /* PSEL @Bit 16 : Power-fail comparator input selector */ #define REGULATORS_POFCON_PSEL_Pos (16UL) /*!< Position of PSEL field. */ #define REGULATORS_POFCON_PSEL_Msk (0x1UL << REGULATORS_POFCON_PSEL_Pos) /*!< Bit mask of PSEL field. */ - #define REGULATORS_POFCON_PSEL_Min (0x0UL) /*!< Min enumerator value of PSEL field. */ + #define REGULATORS_POFCON_PSEL_Min (0x1UL) /*!< Min enumerator value of PSEL field. */ #define REGULATORS_POFCON_PSEL_Max (0x1UL) /*!< Max enumerator value of PSEL field. */ - #define REGULATORS_POFCON_PSEL_Vdd (0x0UL) /*!< POF input connected to VDD */ #define REGULATORS_POFCON_PSEL_VddL (0x1UL) /*!< POF input connected to VDDL */ @@ -22550,14 +23059,14 @@ typedef struct { * @brief ERASE [RRAMC_ERASE] (unspecified) */ typedef struct { - __IOM uint32_t ERASEALL; /*!< (@ 0x00000000) Register for erasing whole RRAM main block, that - includes the SICR and the UICR*/ + __IOM uint32_t ERASEALL; /*!< (@ 0x00000000) Erase RRAM, including UICR All information in SICR, + including keys, are also erased*/ } NRF_RRAMC_ERASE_Type; /*!< Size = 4 (0x004) */ -/* RRAMC_ERASE_ERASEALL: Register for erasing whole RRAM main block, that includes the SICR and the UICR */ +/* RRAMC_ERASE_ERASEALL: Erase RRAM, including UICR All information in SICR, including keys, are also erased */ #define RRAMC_ERASE_ERASEALL_ResetValue (0x00000000UL) /*!< Reset value of ERASEALL register. */ -/* ERASE @Bit 0 : Erase whole RRAM main block */ +/* ERASE @Bit 0 : Erase RRAM */ #define RRAMC_ERASE_ERASEALL_ERASE_Pos (0UL) /*!< Position of ERASE field. */ #define RRAMC_ERASE_ERASEALL_ERASE_Msk (0x1UL << RRAMC_ERASE_ERASEALL_ERASE_Pos) /*!< Bit mask of ERASE field. */ #define RRAMC_ERASE_ERASEALL_ERASE_Min (0x0UL) /*!< Min enumerator value of ERASE field. */ @@ -22659,42 +23168,42 @@ typedef struct { */ typedef struct { /*!< RRAMC Structure */ __OM uint32_t TASKS_WAKEUP; /*!< (@ 0x00000000) Wakeup the RRAM from low power mode */ - __IM uint32_t RESERVED; + __OM uint32_t TASKS_CLRWRITEBUF; /*!< (@ 0x00000004) Clear internal write-buffer */ __OM uint32_t TASKS_COMMITWRITEBUF; /*!< (@ 0x00000008) Commits the data stored in internal write-buffer to RRAM*/ - __IM uint32_t RESERVED1[29]; + __IM uint32_t RESERVED[29]; __IOM uint32_t SUBSCRIBE_WAKEUP; /*!< (@ 0x00000080) Subscribe configuration for task WAKEUP */ - __IM uint32_t RESERVED2; + __IOM uint32_t SUBSCRIBE_CLRWRITEBUF; /*!< (@ 0x00000084) Subscribe configuration for task CLRWRITEBUF */ __IOM uint32_t SUBSCRIBE_COMMITWRITEBUF; /*!< (@ 0x00000088) Subscribe configuration for task COMMITWRITEBUF */ - __IM uint32_t RESERVED3[29]; + __IM uint32_t RESERVED1[29]; __IOM uint32_t EVENTS_WOKENUP; /*!< (@ 0x00000100) RRAMC is woken up from low power mode */ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000104) RRAMC is ready */ __IOM uint32_t EVENTS_READYNEXT; /*!< (@ 0x00000108) Ready to accept a new write operation */ __IOM uint32_t EVENTS_ACCESSERROR; /*!< (@ 0x0000010C) RRAM access error */ - __IM uint32_t RESERVED4[28]; + __IM uint32_t RESERVED2[28]; __IOM uint32_t PUBLISH_WOKENUP; /*!< (@ 0x00000180) Publish configuration for event WOKENUP */ - __IM uint32_t RESERVED5[95]; + __IM uint32_t RESERVED3[95]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ - __IM uint32_t RESERVED6[60]; + __IM uint32_t RESERVED4[60]; __IM uint32_t READY; /*!< (@ 0x00000400) RRAMC ready status */ __IM uint32_t READYNEXT; /*!< (@ 0x00000404) Ready next flag */ __IM uint32_t ACCESSERRORADDR; /*!< (@ 0x00000408) Address of the first access error */ - __IM uint32_t RESERVED7; + __IM uint32_t RESERVED5; __IOM NRF_RRAMC_BUFSTATUS_Type BUFSTATUS; /*!< (@ 0x00000410) (unspecified) */ - __IM uint32_t RESERVED8; + __IM uint32_t RESERVED6; __IOM NRF_RRAMC_ECC_Type ECC; /*!< (@ 0x00000420) (unspecified) */ - __IM uint32_t RESERVED9[55]; + __IM uint32_t RESERVED7[55]; __IOM uint32_t CONFIG; /*!< (@ 0x00000500) Configuration register */ - __IM uint32_t RESERVED10[2]; + __IM uint32_t RESERVED8[2]; __IOM uint32_t READYNEXTTIMEOUT; /*!< (@ 0x0000050C) Configuration for ready next timeout counter, in units of AXI clock frequency*/ __IOM NRF_RRAMC_POWER_Type POWER; /*!< (@ 0x00000510) (unspecified) */ - __IM uint32_t RESERVED11[9]; + __IM uint32_t RESERVED9[9]; __IOM NRF_RRAMC_ERASE_Type ERASE; /*!< (@ 0x00000540) (unspecified) */ - __IM uint32_t RESERVED12[3]; + __IM uint32_t RESERVED10[3]; __IOM NRF_RRAMC_REGION_Type REGION[6]; /*!< (@ 0x00000550) RRAMC can apply access privileges to regions of the RRAM. Some regions are dedicated for system use and are not available for configuration - refer to the @@ -22713,6 +23222,18 @@ typedef struct { #define RRAMC_TASKS_WAKEUP_TASKS_WAKEUP_Trigger (0x1UL) /*!< Trigger task */ +/* RRAMC_TASKS_CLRWRITEBUF: Clear internal write-buffer */ + #define RRAMC_TASKS_CLRWRITEBUF_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLRWRITEBUF register. */ + +/* TASKS_CLRWRITEBUF @Bit 0 : Clear internal write-buffer */ + #define RRAMC_TASKS_CLRWRITEBUF_TASKS_CLRWRITEBUF_Pos (0UL) /*!< Position of TASKS_CLRWRITEBUF field. */ + #define RRAMC_TASKS_CLRWRITEBUF_TASKS_CLRWRITEBUF_Msk (0x1UL << RRAMC_TASKS_CLRWRITEBUF_TASKS_CLRWRITEBUF_Pos) /*!< Bit mask + of TASKS_CLRWRITEBUF field.*/ + #define RRAMC_TASKS_CLRWRITEBUF_TASKS_CLRWRITEBUF_Min (0x1UL) /*!< Min enumerator value of TASKS_CLRWRITEBUF field. */ + #define RRAMC_TASKS_CLRWRITEBUF_TASKS_CLRWRITEBUF_Max (0x1UL) /*!< Max enumerator value of TASKS_CLRWRITEBUF field. */ + #define RRAMC_TASKS_CLRWRITEBUF_TASKS_CLRWRITEBUF_Trigger (0x1UL) /*!< Trigger task */ + + /* RRAMC_TASKS_COMMITWRITEBUF: Commits the data stored in internal write-buffer to RRAM */ #define RRAMC_TASKS_COMMITWRITEBUF_ResetValue (0x00000000UL) /*!< Reset value of TASKS_COMMITWRITEBUF register. */ @@ -22743,6 +23264,24 @@ typedef struct { #define RRAMC_SUBSCRIBE_WAKEUP_EN_Enabled (0x1UL) /*!< Enable subscription */ +/* RRAMC_SUBSCRIBE_CLRWRITEBUF: Subscribe configuration for task CLRWRITEBUF */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CLRWRITEBUF register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CLRWRITEBUF will subscribe to */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_CHIDX_Msk (0xFFUL << RRAMC_SUBSCRIBE_CLRWRITEBUF_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_EN_Pos (31UL) /*!< Position of EN field. */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_EN_Msk (0x1UL << RRAMC_SUBSCRIBE_CLRWRITEBUF_EN_Pos) /*!< Bit mask of EN field. */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_EN_Enabled (0x1UL) /*!< Enable subscription */ + + /* RRAMC_SUBSCRIBE_COMMITWRITEBUF: Subscribe configuration for task COMMITWRITEBUF */ #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_COMMITWRITEBUF register. */ @@ -23069,9 +23608,9 @@ typedef struct { __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Last results is equal or above CH[n].LIMIT.HIGH */ __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Last results is equal or below CH[n].LIMIT.LOW */ } NRF_SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x008) */ - #define SAADC_EVENTS_CH_MaxCount (8UL) /*!< Size of EVENTS_CH[8] array. */ - #define SAADC_EVENTS_CH_MaxIndex (7UL) /*!< Max index of EVENTS_CH[8] array. */ - #define SAADC_EVENTS_CH_MinIndex (0UL) /*!< Min index of EVENTS_CH[8] array. */ + #define SAADC_EVENTS_CH_MaxCount (4UL) /*!< Size of EVENTS_CH[4] array. */ + #define SAADC_EVENTS_CH_MaxIndex (3UL) /*!< Max index of EVENTS_CH[4] array. */ + #define SAADC_EVENTS_CH_MinIndex (0UL) /*!< Min index of EVENTS_CH[4] array. */ /* SAADC_EVENTS_CH_LIMITH: Last results is equal or above CH[n].LIMIT.HIGH */ #define SAADC_EVENTS_CH_LIMITH_ResetValue (0x00000000UL) /*!< Reset value of LIMITH register. */ @@ -23106,9 +23645,9 @@ typedef struct { __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Publish configuration for event CH[n].LIMITH */ __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Publish configuration for event CH[n].LIMITL */ } NRF_SAADC_PUBLISH_CH_Type; /*!< Size = 8 (0x008) */ - #define SAADC_PUBLISH_CH_MaxCount (8UL) /*!< Size of PUBLISH_CH[8] array. */ - #define SAADC_PUBLISH_CH_MaxIndex (7UL) /*!< Max index of PUBLISH_CH[8] array. */ - #define SAADC_PUBLISH_CH_MinIndex (0UL) /*!< Min index of PUBLISH_CH[8] array. */ + #define SAADC_PUBLISH_CH_MaxCount (4UL) /*!< Size of PUBLISH_CH[4] array. */ + #define SAADC_PUBLISH_CH_MaxIndex (3UL) /*!< Max index of PUBLISH_CH[4] array. */ + #define SAADC_PUBLISH_CH_MinIndex (0UL) /*!< Min index of PUBLISH_CH[4] array. */ /* SAADC_PUBLISH_CH_LIMITH: Publish configuration for event CH[n].LIMITH */ #define SAADC_PUBLISH_CH_LIMITH_ResetValue (0x00000000UL) /*!< Reset value of LIMITH register. */ @@ -23152,16 +23691,16 @@ typedef struct { * @brief CH [SAADC_CH] (unspecified) */ typedef struct { - __IOM uint32_t PSELP; /*!< (@ 0x00000000) Input positive pin selection for CH[n] */ - __IOM uint32_t PSELN; /*!< (@ 0x00000004) Input negative pin selection for CH[n] */ - __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Input configuration for CH[n] */ + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Input positive pin selection for CH[m] */ + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Input negative pin selection for CH[m] */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Input configuration for CH[m] */ __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) High/low limits for event monitoring a channel */ } NRF_SAADC_CH_Type; /*!< Size = 16 (0x010) */ - #define SAADC_CH_MaxCount (8UL) /*!< Size of CH[8] array. */ - #define SAADC_CH_MaxIndex (7UL) /*!< Max index of CH[8] array. */ - #define SAADC_CH_MinIndex (0UL) /*!< Min index of CH[8] array. */ + #define SAADC_CH_MaxCount (4UL) /*!< Size of CH[4] array. */ + #define SAADC_CH_MaxIndex (3UL) /*!< Max index of CH[4] array. */ + #define SAADC_CH_MinIndex (0UL) /*!< Min index of CH[4] array. */ -/* SAADC_CH_PSELP: Input positive pin selection for CH[n] */ +/* SAADC_CH_PSELP: Input positive pin selection for CH[m] */ #define SAADC_CH_PSELP_ResetValue (0x00000000UL) /*!< Reset value of PSELP register. */ /* PIN @Bits 0..4 : GPIO pin selection. */ @@ -23172,11 +23711,12 @@ typedef struct { #define SAADC_CH_PSELP_PORT_Pos (8UL) /*!< Position of PORT field. */ #define SAADC_CH_PSELP_PORT_Msk (0xFUL << SAADC_CH_PSELP_PORT_Pos) /*!< Bit mask of PORT field. */ -/* INTERNAL @Bits 12..14 : Internal input selection for analog positive input when CH[n].PSELP.CONNECT = Internal */ +/* INTERNAL @Bits 12..14 : Internal input selection for analog positive input when CH[m].PSELP.CONNECT = Internal */ #define SAADC_CH_PSELP_INTERNAL_Pos (12UL) /*!< Position of INTERNAL field. */ #define SAADC_CH_PSELP_INTERNAL_Msk (0x7UL << SAADC_CH_PSELP_INTERNAL_Pos) /*!< Bit mask of INTERNAL field. */ - #define SAADC_CH_PSELP_INTERNAL_Min (0x1UL) /*!< Min enumerator value of INTERNAL field. */ + #define SAADC_CH_PSELP_INTERNAL_Min (0x0UL) /*!< Min enumerator value of INTERNAL field. */ #define SAADC_CH_PSELP_INTERNAL_Max (0x4UL) /*!< Max enumerator value of INTERNAL field. */ + #define SAADC_CH_PSELP_INTERNAL_Dvdd (0x0UL) /*!< Connected to the internal 0.9 V digital supply rail */ #define SAADC_CH_PSELP_INTERNAL_VddL (0x1UL) /*!< Connected to VDDL */ #define SAADC_CH_PSELP_INTERNAL_Vss (0x4UL) /*!< (unspecified) */ @@ -23190,7 +23730,7 @@ typedef struct { #define SAADC_CH_PSELP_CONNECT_Internal (0x2UL) /*!< Selects internal inputs. */ -/* SAADC_CH_PSELN: Input negative pin selection for CH[n] */ +/* SAADC_CH_PSELN: Input negative pin selection for CH[m] */ #define SAADC_CH_PSELN_ResetValue (0x00000000UL) /*!< Reset value of PSELN register. */ /* PIN @Bits 0..4 : GPIO pin selection. */ @@ -23201,14 +23741,13 @@ typedef struct { #define SAADC_CH_PSELN_PORT_Pos (8UL) /*!< Position of PORT field. */ #define SAADC_CH_PSELN_PORT_Msk (0xFUL << SAADC_CH_PSELN_PORT_Pos) /*!< Bit mask of PORT field. */ -/* INTERNAL @Bits 12..14 : Internal input selection for Analog negative input when CH[n].PSELN.CONNECT = Internal */ +/* INTERNAL @Bits 12..14 : Internal input selection for Analog negative input when CH[m].PSELN.CONNECT = Internal */ #define SAADC_CH_PSELN_INTERNAL_Pos (12UL) /*!< Position of INTERNAL field. */ #define SAADC_CH_PSELN_INTERNAL_Msk (0x7UL << SAADC_CH_PSELN_INTERNAL_Pos) /*!< Bit mask of INTERNAL field. */ #define SAADC_CH_PSELN_INTERNAL_Min (0x0UL) /*!< Min enumerator value of INTERNAL field. */ #define SAADC_CH_PSELN_INTERNAL_Max (0x4UL) /*!< Max enumerator value of INTERNAL field. */ #define SAADC_CH_PSELN_INTERNAL_Dvdd (0x0UL) /*!< Connected to the internal 0.9 V digital supply rail */ #define SAADC_CH_PSELN_INTERNAL_VddL (0x1UL) /*!< Connected to VDDL */ - #define SAADC_CH_PSELN_INTERNAL_Vdd (0x2UL) /*!< Connected to VDD */ #define SAADC_CH_PSELN_INTERNAL_Vss (0x4UL) /*!< (unspecified) */ /* CONNECT @Bits 30..31 : Connection */ @@ -23220,7 +23759,7 @@ typedef struct { #define SAADC_CH_PSELN_CONNECT_AnalogInput (0x1UL) /*!< Select analog input */ -/* SAADC_CH_CONFIG: Input configuration for CH[n] */ +/* SAADC_CH_CONFIG: Input configuration for CH[m] */ #define SAADC_CH_CONFIG_ResetValue (0x00020000UL) /*!< Reset value of CONFIG register. */ /* CHOPPING @Bit 0 : Enable chopping */ @@ -23248,11 +23787,10 @@ typedef struct { #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ #define SAADC_CH_CONFIG_REFSEL_Msk (0x7UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ #define SAADC_CH_CONFIG_REFSEL_Min (0x0UL) /*!< Min enumerator value of REFSEL field. */ - #define SAADC_CH_CONFIG_REFSEL_Max (0x3UL) /*!< Max enumerator value of REFSEL field. */ + #define SAADC_CH_CONFIG_REFSEL_Max (0x2UL) /*!< Max enumerator value of REFSEL field. */ #define SAADC_CH_CONFIG_REFSEL_Internal (0x0UL) /*!< Internal 1.3 V reference */ #define SAADC_CH_CONFIG_REFSEL_External (0x1UL) /*!< External reference voltage */ #define SAADC_CH_CONFIG_REFSEL_VddL (0x2UL) /*!< Reference given at VDDL */ - #define SAADC_CH_CONFIG_REFSEL_Vdd (0x3UL) /*!< Reference given at VDD */ /* MODE @Bit 15 : Enable differential mode */ #define SAADC_CH_CONFIG_MODE_Pos (15UL) /*!< Position of MODE field. */ @@ -23364,16 +23902,16 @@ typedef struct { __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ - __IOM NRF_SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ - __IM uint32_t RESERVED2[10]; + __IOM NRF_SAADC_EVENTS_CH_Type EVENTS_CH[4]; /*!< (@ 0x00000118) Peripheral events. */ + __IM uint32_t RESERVED2[18]; __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x00000188) Publish configuration for event DONE */ __IOM uint32_t PUBLISH_RESULTDONE; /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE */ __IOM uint32_t PUBLISH_CALIBRATEDONE; /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE */ __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000194) Publish configuration for event STOPPED */ - __IOM NRF_SAADC_PUBLISH_CH_Type PUBLISH_CH[8]; /*!< (@ 0x00000198) Publish configuration for events */ - __IM uint32_t RESERVED3[74]; + __IOM NRF_SAADC_PUBLISH_CH_Type PUBLISH_CH[4]; /*!< (@ 0x00000198) Publish configuration for events */ + __IM uint32_t RESERVED3[82]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -23382,8 +23920,8 @@ typedef struct { __IM uint32_t RESERVED5[63]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ __IM uint32_t RESERVED6[3]; - __IOM NRF_SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) (unspecified) */ - __IM uint32_t RESERVED7[22]; + __IOM NRF_SAADC_CH_Type CH[4]; /*!< (@ 0x00000510) (unspecified) */ + __IM uint32_t RESERVED7[38]; __IOM uint32_t BURST; /*!< (@ 0x000005E8) Enable burst mode */ __IM uint32_t RESERVED8; __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ @@ -23824,70 +24362,6 @@ typedef struct { #define SAADC_INTEN_CH3LIMITL_Disabled (0x0UL) /*!< Disable */ #define SAADC_INTEN_CH3LIMITL_Enabled (0x1UL) /*!< Enable */ -/* CH4LIMITH @Bit 14 : Enable or disable interrupt for event CH4LIMITH */ - #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ - #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ - #define SAADC_INTEN_CH4LIMITH_Min (0x0UL) /*!< Min enumerator value of CH4LIMITH field. */ - #define SAADC_INTEN_CH4LIMITH_Max (0x1UL) /*!< Max enumerator value of CH4LIMITH field. */ - #define SAADC_INTEN_CH4LIMITH_Disabled (0x0UL) /*!< Disable */ - #define SAADC_INTEN_CH4LIMITH_Enabled (0x1UL) /*!< Enable */ - -/* CH4LIMITL @Bit 15 : Enable or disable interrupt for event CH4LIMITL */ - #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ - #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ - #define SAADC_INTEN_CH4LIMITL_Min (0x0UL) /*!< Min enumerator value of CH4LIMITL field. */ - #define SAADC_INTEN_CH4LIMITL_Max (0x1UL) /*!< Max enumerator value of CH4LIMITL field. */ - #define SAADC_INTEN_CH4LIMITL_Disabled (0x0UL) /*!< Disable */ - #define SAADC_INTEN_CH4LIMITL_Enabled (0x1UL) /*!< Enable */ - -/* CH5LIMITH @Bit 16 : Enable or disable interrupt for event CH5LIMITH */ - #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ - #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ - #define SAADC_INTEN_CH5LIMITH_Min (0x0UL) /*!< Min enumerator value of CH5LIMITH field. */ - #define SAADC_INTEN_CH5LIMITH_Max (0x1UL) /*!< Max enumerator value of CH5LIMITH field. */ - #define SAADC_INTEN_CH5LIMITH_Disabled (0x0UL) /*!< Disable */ - #define SAADC_INTEN_CH5LIMITH_Enabled (0x1UL) /*!< Enable */ - -/* CH5LIMITL @Bit 17 : Enable or disable interrupt for event CH5LIMITL */ - #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ - #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ - #define SAADC_INTEN_CH5LIMITL_Min (0x0UL) /*!< Min enumerator value of CH5LIMITL field. */ - #define SAADC_INTEN_CH5LIMITL_Max (0x1UL) /*!< Max enumerator value of CH5LIMITL field. */ - #define SAADC_INTEN_CH5LIMITL_Disabled (0x0UL) /*!< Disable */ - #define SAADC_INTEN_CH5LIMITL_Enabled (0x1UL) /*!< Enable */ - -/* CH6LIMITH @Bit 18 : Enable or disable interrupt for event CH6LIMITH */ - #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ - #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ - #define SAADC_INTEN_CH6LIMITH_Min (0x0UL) /*!< Min enumerator value of CH6LIMITH field. */ - #define SAADC_INTEN_CH6LIMITH_Max (0x1UL) /*!< Max enumerator value of CH6LIMITH field. */ - #define SAADC_INTEN_CH6LIMITH_Disabled (0x0UL) /*!< Disable */ - #define SAADC_INTEN_CH6LIMITH_Enabled (0x1UL) /*!< Enable */ - -/* CH6LIMITL @Bit 19 : Enable or disable interrupt for event CH6LIMITL */ - #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ - #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ - #define SAADC_INTEN_CH6LIMITL_Min (0x0UL) /*!< Min enumerator value of CH6LIMITL field. */ - #define SAADC_INTEN_CH6LIMITL_Max (0x1UL) /*!< Max enumerator value of CH6LIMITL field. */ - #define SAADC_INTEN_CH6LIMITL_Disabled (0x0UL) /*!< Disable */ - #define SAADC_INTEN_CH6LIMITL_Enabled (0x1UL) /*!< Enable */ - -/* CH7LIMITH @Bit 20 : Enable or disable interrupt for event CH7LIMITH */ - #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ - #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ - #define SAADC_INTEN_CH7LIMITH_Min (0x0UL) /*!< Min enumerator value of CH7LIMITH field. */ - #define SAADC_INTEN_CH7LIMITH_Max (0x1UL) /*!< Max enumerator value of CH7LIMITH field. */ - #define SAADC_INTEN_CH7LIMITH_Disabled (0x0UL) /*!< Disable */ - #define SAADC_INTEN_CH7LIMITH_Enabled (0x1UL) /*!< Enable */ - -/* CH7LIMITL @Bit 21 : Enable or disable interrupt for event CH7LIMITL */ - #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ - #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ - #define SAADC_INTEN_CH7LIMITL_Min (0x0UL) /*!< Min enumerator value of CH7LIMITL field. */ - #define SAADC_INTEN_CH7LIMITL_Max (0x1UL) /*!< Max enumerator value of CH7LIMITL field. */ - #define SAADC_INTEN_CH7LIMITL_Disabled (0x0UL) /*!< Disable */ - #define SAADC_INTEN_CH7LIMITL_Enabled (0x1UL) /*!< Enable */ - /* SAADC_INTENSET: Enable interrupt */ #define SAADC_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ @@ -24018,78 +24492,6 @@ typedef struct { #define SAADC_INTENSET_CH3LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH3LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ -/* CH4LIMITH @Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */ - #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ - #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ - #define SAADC_INTENSET_CH4LIMITH_Min (0x0UL) /*!< Min enumerator value of CH4LIMITH field. */ - #define SAADC_INTENSET_CH4LIMITH_Max (0x1UL) /*!< Max enumerator value of CH4LIMITH field. */ - #define SAADC_INTENSET_CH4LIMITH_Set (0x1UL) /*!< Enable */ - #define SAADC_INTENSET_CH4LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ - #define SAADC_INTENSET_CH4LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ - -/* CH4LIMITL @Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */ - #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ - #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ - #define SAADC_INTENSET_CH4LIMITL_Min (0x0UL) /*!< Min enumerator value of CH4LIMITL field. */ - #define SAADC_INTENSET_CH4LIMITL_Max (0x1UL) /*!< Max enumerator value of CH4LIMITL field. */ - #define SAADC_INTENSET_CH4LIMITL_Set (0x1UL) /*!< Enable */ - #define SAADC_INTENSET_CH4LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ - #define SAADC_INTENSET_CH4LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ - -/* CH5LIMITH @Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */ - #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ - #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ - #define SAADC_INTENSET_CH5LIMITH_Min (0x0UL) /*!< Min enumerator value of CH5LIMITH field. */ - #define SAADC_INTENSET_CH5LIMITH_Max (0x1UL) /*!< Max enumerator value of CH5LIMITH field. */ - #define SAADC_INTENSET_CH5LIMITH_Set (0x1UL) /*!< Enable */ - #define SAADC_INTENSET_CH5LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ - #define SAADC_INTENSET_CH5LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ - -/* CH5LIMITL @Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */ - #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ - #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ - #define SAADC_INTENSET_CH5LIMITL_Min (0x0UL) /*!< Min enumerator value of CH5LIMITL field. */ - #define SAADC_INTENSET_CH5LIMITL_Max (0x1UL) /*!< Max enumerator value of CH5LIMITL field. */ - #define SAADC_INTENSET_CH5LIMITL_Set (0x1UL) /*!< Enable */ - #define SAADC_INTENSET_CH5LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ - #define SAADC_INTENSET_CH5LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ - -/* CH6LIMITH @Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */ - #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ - #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ - #define SAADC_INTENSET_CH6LIMITH_Min (0x0UL) /*!< Min enumerator value of CH6LIMITH field. */ - #define SAADC_INTENSET_CH6LIMITH_Max (0x1UL) /*!< Max enumerator value of CH6LIMITH field. */ - #define SAADC_INTENSET_CH6LIMITH_Set (0x1UL) /*!< Enable */ - #define SAADC_INTENSET_CH6LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ - #define SAADC_INTENSET_CH6LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ - -/* CH6LIMITL @Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */ - #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ - #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ - #define SAADC_INTENSET_CH6LIMITL_Min (0x0UL) /*!< Min enumerator value of CH6LIMITL field. */ - #define SAADC_INTENSET_CH6LIMITL_Max (0x1UL) /*!< Max enumerator value of CH6LIMITL field. */ - #define SAADC_INTENSET_CH6LIMITL_Set (0x1UL) /*!< Enable */ - #define SAADC_INTENSET_CH6LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ - #define SAADC_INTENSET_CH6LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ - -/* CH7LIMITH @Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */ - #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ - #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ - #define SAADC_INTENSET_CH7LIMITH_Min (0x0UL) /*!< Min enumerator value of CH7LIMITH field. */ - #define SAADC_INTENSET_CH7LIMITH_Max (0x1UL) /*!< Max enumerator value of CH7LIMITH field. */ - #define SAADC_INTENSET_CH7LIMITH_Set (0x1UL) /*!< Enable */ - #define SAADC_INTENSET_CH7LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ - #define SAADC_INTENSET_CH7LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ - -/* CH7LIMITL @Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */ - #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ - #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ - #define SAADC_INTENSET_CH7LIMITL_Min (0x0UL) /*!< Min enumerator value of CH7LIMITL field. */ - #define SAADC_INTENSET_CH7LIMITL_Max (0x1UL) /*!< Max enumerator value of CH7LIMITL field. */ - #define SAADC_INTENSET_CH7LIMITL_Set (0x1UL) /*!< Enable */ - #define SAADC_INTENSET_CH7LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ - #define SAADC_INTENSET_CH7LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ - /* SAADC_INTENCLR: Disable interrupt */ #define SAADC_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ @@ -24220,78 +24622,6 @@ typedef struct { #define SAADC_INTENCLR_CH3LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH3LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ -/* CH4LIMITH @Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */ - #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ - #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ - #define SAADC_INTENCLR_CH4LIMITH_Min (0x0UL) /*!< Min enumerator value of CH4LIMITH field. */ - #define SAADC_INTENCLR_CH4LIMITH_Max (0x1UL) /*!< Max enumerator value of CH4LIMITH field. */ - #define SAADC_INTENCLR_CH4LIMITH_Clear (0x1UL) /*!< Disable */ - #define SAADC_INTENCLR_CH4LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ - #define SAADC_INTENCLR_CH4LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ - -/* CH4LIMITL @Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */ - #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ - #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ - #define SAADC_INTENCLR_CH4LIMITL_Min (0x0UL) /*!< Min enumerator value of CH4LIMITL field. */ - #define SAADC_INTENCLR_CH4LIMITL_Max (0x1UL) /*!< Max enumerator value of CH4LIMITL field. */ - #define SAADC_INTENCLR_CH4LIMITL_Clear (0x1UL) /*!< Disable */ - #define SAADC_INTENCLR_CH4LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ - #define SAADC_INTENCLR_CH4LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ - -/* CH5LIMITH @Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */ - #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ - #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ - #define SAADC_INTENCLR_CH5LIMITH_Min (0x0UL) /*!< Min enumerator value of CH5LIMITH field. */ - #define SAADC_INTENCLR_CH5LIMITH_Max (0x1UL) /*!< Max enumerator value of CH5LIMITH field. */ - #define SAADC_INTENCLR_CH5LIMITH_Clear (0x1UL) /*!< Disable */ - #define SAADC_INTENCLR_CH5LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ - #define SAADC_INTENCLR_CH5LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ - -/* CH5LIMITL @Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */ - #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ - #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ - #define SAADC_INTENCLR_CH5LIMITL_Min (0x0UL) /*!< Min enumerator value of CH5LIMITL field. */ - #define SAADC_INTENCLR_CH5LIMITL_Max (0x1UL) /*!< Max enumerator value of CH5LIMITL field. */ - #define SAADC_INTENCLR_CH5LIMITL_Clear (0x1UL) /*!< Disable */ - #define SAADC_INTENCLR_CH5LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ - #define SAADC_INTENCLR_CH5LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ - -/* CH6LIMITH @Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */ - #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ - #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ - #define SAADC_INTENCLR_CH6LIMITH_Min (0x0UL) /*!< Min enumerator value of CH6LIMITH field. */ - #define SAADC_INTENCLR_CH6LIMITH_Max (0x1UL) /*!< Max enumerator value of CH6LIMITH field. */ - #define SAADC_INTENCLR_CH6LIMITH_Clear (0x1UL) /*!< Disable */ - #define SAADC_INTENCLR_CH6LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ - #define SAADC_INTENCLR_CH6LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ - -/* CH6LIMITL @Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */ - #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ - #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ - #define SAADC_INTENCLR_CH6LIMITL_Min (0x0UL) /*!< Min enumerator value of CH6LIMITL field. */ - #define SAADC_INTENCLR_CH6LIMITL_Max (0x1UL) /*!< Max enumerator value of CH6LIMITL field. */ - #define SAADC_INTENCLR_CH6LIMITL_Clear (0x1UL) /*!< Disable */ - #define SAADC_INTENCLR_CH6LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ - #define SAADC_INTENCLR_CH6LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ - -/* CH7LIMITH @Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */ - #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ - #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ - #define SAADC_INTENCLR_CH7LIMITH_Min (0x0UL) /*!< Min enumerator value of CH7LIMITH field. */ - #define SAADC_INTENCLR_CH7LIMITH_Max (0x1UL) /*!< Max enumerator value of CH7LIMITH field. */ - #define SAADC_INTENCLR_CH7LIMITH_Clear (0x1UL) /*!< Disable */ - #define SAADC_INTENCLR_CH7LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ - #define SAADC_INTENCLR_CH7LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ - -/* CH7LIMITL @Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */ - #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ - #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ - #define SAADC_INTENCLR_CH7LIMITL_Min (0x0UL) /*!< Min enumerator value of CH7LIMITL field. */ - #define SAADC_INTENCLR_CH7LIMITL_Max (0x1UL) /*!< Max enumerator value of CH7LIMITL field. */ - #define SAADC_INTENCLR_CH7LIMITL_Clear (0x1UL) /*!< Disable */ - #define SAADC_INTENCLR_CH7LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ - #define SAADC_INTENCLR_CH7LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ - /* SAADC_STATUS: Status */ #define SAADC_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ @@ -24371,7 +24701,7 @@ typedef struct { /* CC @Bits 0..10 : Capture and compare value. Sample rate is 16 MHz/CC */ #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ - #define SAADC_SAMPLERATE_CC_Min (0x008UL) /*!< Min value of CC field. */ + #define SAADC_SAMPLERATE_CC_Min (0x010UL) /*!< Min value of CC field. */ #define SAADC_SAMPLERATE_CC_Max (0x7FFUL) /*!< Max size of CC field. */ /* MODE @Bit 12 : Select mode for sample rate control */ @@ -27992,8 +28322,8 @@ typedef struct { field.*/ #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ - #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0. */ - #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0, indicating that invasive debug is disabled.*/ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1, indicating that invasive debug is enabled.*/ /* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ @@ -28059,8 +28389,10 @@ typedef struct { field.*/ #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ - #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0. */ - #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0, indicating that non-invasive debug is + disabled.*/ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1, indicating that non-invasive debug is + enabled.*/ /* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ @@ -28127,8 +28459,10 @@ typedef struct { VALUE field.*/ #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ - #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0. */ - #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0, indicating that secure priviliged invasive + debug is disabled.*/ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1, indicating that secure priviliged invasive + debug is enabled.*/ /* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ @@ -28195,8 +28529,10 @@ typedef struct { VALUE field.*/ #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ - #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0. */ - #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0, indicating that secure priviliged + non-invasive debug is disabled.*/ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1, indicating that secure priviliged + non-invasive debug is enabled.*/ /* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ @@ -28261,12 +28597,12 @@ typedef struct { */ typedef struct { __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register to enable invasive (halting) debug in - domain n's access port.*/ + domain ns access port.*/ __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for invasive (halting) debug enable for - domain n's access port.*/ + domain ns access port.*/ } NRF_TAMPC_PROTECT_AP_DBGEN_Type; /*!< Size = 8 (0x008) */ -/* TAMPC_PROTECT_AP_DBGEN_CTRL: Control register to enable invasive (halting) debug in domain n's access port. */ +/* TAMPC_PROTECT_AP_DBGEN_CTRL: Control register to enable invasive (halting) debug in domain ns access port. */ #define TAMPC_PROTECT_AP_DBGEN_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register. */ /* VALUE @Bit 0 : Set value of dbgen signal. */ @@ -28274,8 +28610,8 @@ typedef struct { #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Pos) /*!< Bit mask of VALUE field. */ #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ - #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0. */ - #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0, indicating that invasive debug is disabled. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1, indicating that invasive debug is enabled. */ /* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ #define TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ @@ -28303,7 +28639,7 @@ typedef struct { #define TAMPC_PROTECT_AP_DBGEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ -/* TAMPC_PROTECT_AP_DBGEN_STATUS: Status register for invasive (halting) debug enable for domain n's access port. */ +/* TAMPC_PROTECT_AP_DBGEN_STATUS: Status register for invasive (halting) debug enable for domain ns access port. */ #define TAMPC_PROTECT_AP_DBGEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ /* ERROR @Bit 0 : Error detection status. */ @@ -28783,25 +29119,23 @@ typedef struct { /** * @brief PROTECT [TAMPC_PROTECT] (unspecified) */ -typedef union { - struct { - __IOM NRF_TAMPC_PROTECT_DOMAIN_Type DOMAIN[1]; /*!< (@ 0x00000000) (unspecified) */ - __IM uint32_t RESERVED[120]; - __IOM NRF_TAMPC_PROTECT_AP_Type AP[1]; /*!< (@ 0x00000200) (unspecified) */ - __IM uint32_t RESERVED1[124]; - __IOM NRF_TAMPC_PROTECT_ACTIVESHIELD_Type ACTIVESHIELD; /*!< (@ 0x00000400) Enable active shield detector. */ - __IM uint32_t RESERVED2[12]; - __IOM NRF_TAMPC_PROTECT_CRACENTAMP_Type CRACENTAMP; /*!< (@ 0x00000438) Enable tamper detector from CRACEN. */ - __IOM NRF_TAMPC_PROTECT_GLITCHSLOWDOMAIN_Type GLITCHSLOWDOMAIN; /*!< (@ 0x00000440) Enable slow domain glitch detectors. */ - __IOM NRF_TAMPC_PROTECT_GLITCHFASTDOMAIN_Type GLITCHFASTDOMAIN; /*!< (@ 0x00000448) Enable fast domain glitch detectors. */ - __IM uint32_t RESERVED3[8]; - __IOM NRF_TAMPC_PROTECT_EXTRESETEN_Type EXTRESETEN; /*!< (@ 0x00000470) Trigger a reset when tamper is detected by the - external tamper detectors.*/ - __IOM NRF_TAMPC_PROTECT_INTRESETEN_Type INTRESETEN; /*!< (@ 0x00000478) Trigger a reset when tamper is detected by the - glitch detectors, signal protector or CRACEN tamper - detector.*/ - __IOM NRF_TAMPC_PROTECT_ERASEPROTECT_Type ERASEPROTECT; /*!< (@ 0x00000480) Device erase protection. */ - }; +typedef struct { + __IOM NRF_TAMPC_PROTECT_DOMAIN_Type DOMAIN[1]; /*!< (@ 0x00000000) (unspecified) */ + __IM uint32_t RESERVED[120]; + __IOM NRF_TAMPC_PROTECT_AP_Type AP[1]; /*!< (@ 0x00000200) (unspecified) */ + __IM uint32_t RESERVED1[124]; + __IOM NRF_TAMPC_PROTECT_ACTIVESHIELD_Type ACTIVESHIELD; /*!< (@ 0x00000400) Enable active shield detector. */ + __IM uint32_t RESERVED2[12]; + __IOM NRF_TAMPC_PROTECT_CRACENTAMP_Type CRACENTAMP; /*!< (@ 0x00000438) Enable tamper detector from CRACEN. */ + __IOM NRF_TAMPC_PROTECT_GLITCHSLOWDOMAIN_Type GLITCHSLOWDOMAIN; /*!< (@ 0x00000440) Enable slow domain glitch detectors. */ + __IOM NRF_TAMPC_PROTECT_GLITCHFASTDOMAIN_Type GLITCHFASTDOMAIN; /*!< (@ 0x00000448) Enable fast domain glitch detectors. */ + __IM uint32_t RESERVED3[8]; + __IOM NRF_TAMPC_PROTECT_EXTRESETEN_Type EXTRESETEN; /*!< (@ 0x00000470) Trigger a reset when tamper is detected by the + external tamper detectors.*/ + __IOM NRF_TAMPC_PROTECT_INTRESETEN_Type INTRESETEN; /*!< (@ 0x00000478) Trigger a reset when tamper is detected by the glitch + detectors, signal protector or CRACEN tamper + detector.*/ + __IOM NRF_TAMPC_PROTECT_ERASEPROTECT_Type ERASEPROTECT; /*!< (@ 0x00000480) Device erase protection. */ } NRF_TAMPC_PROTECT_Type; /*!< Size = 1160 (0x488) */ /* ====================================================== Struct TAMPC ======================================================= */ @@ -29183,7 +29517,7 @@ typedef union { /* TEMP_A0: Slope of 1st piece wise linear function */ - #define TEMP_A0_ResetValue (0x000002D6UL) /*!< Reset value of A0 register. */ + #define TEMP_A0_ResetValue (0x0000038CUL) /*!< Reset value of A0 register. */ /* A0 @Bits 0..11 : Slope of 1st piece wise linear function */ #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ @@ -29191,7 +29525,7 @@ typedef union { /* TEMP_A1: Slope of 2nd piece wise linear function */ - #define TEMP_A1_ResetValue (0x0000032DUL) /*!< Reset value of A1 register. */ + #define TEMP_A1_ResetValue (0x000003B3UL) /*!< Reset value of A1 register. */ /* A1 @Bits 0..11 : Slope of 2nd piece wise linear function */ #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ @@ -29199,7 +29533,7 @@ typedef union { /* TEMP_A2: Slope of 3rd piece wise linear function */ - #define TEMP_A2_ResetValue (0x00000384UL) /*!< Reset value of A2 register. */ + #define TEMP_A2_ResetValue (0x000003FAUL) /*!< Reset value of A2 register. */ /* A2 @Bits 0..11 : Slope of 3rd piece wise linear function */ #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ @@ -29207,7 +29541,7 @@ typedef union { /* TEMP_A3: Slope of 4th piece wise linear function */ - #define TEMP_A3_ResetValue (0x000003E9UL) /*!< Reset value of A3 register. */ + #define TEMP_A3_ResetValue (0x00000451UL) /*!< Reset value of A3 register. */ /* A3 @Bits 0..11 : Slope of 4th piece wise linear function */ #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ @@ -29215,7 +29549,7 @@ typedef union { /* TEMP_A4: Slope of 5th piece wise linear function */ - #define TEMP_A4_ResetValue (0x0000046FUL) /*!< Reset value of A4 register. */ + #define TEMP_A4_ResetValue (0x000004AAUL) /*!< Reset value of A4 register. */ /* A4 @Bits 0..11 : Slope of 5th piece wise linear function */ #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ @@ -29223,7 +29557,7 @@ typedef union { /* TEMP_A5: Slope of 6th piece wise linear function */ - #define TEMP_A5_ResetValue (0x00000522UL) /*!< Reset value of A5 register. */ + #define TEMP_A5_ResetValue (0x00000539UL) /*!< Reset value of A5 register. */ /* A5 @Bits 0..11 : Slope of 6th piece wise linear function */ #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ @@ -29231,7 +29565,7 @@ typedef union { /* TEMP_A6: Slope of 7th piece wise linear function */ - #define TEMP_A6_ResetValue (0x000005B7UL) /*!< Reset value of A6 register. */ + #define TEMP_A6_ResetValue (0x00000578UL) /*!< Reset value of A6 register. */ /* A6 @Bits 0..11 : Slope of 7th piece wise linear function */ #define TEMP_A6_A6_Pos (0UL) /*!< Position of A6 field. */ @@ -29239,7 +29573,7 @@ typedef union { /* TEMP_B0: y-intercept of 1st piece wise linear function */ - #define TEMP_B0_ResetValue (0x00000FD6UL) /*!< Reset value of B0 register. */ + #define TEMP_B0_ResetValue (0x00000037UL) /*!< Reset value of B0 register. */ /* B0 @Bits 0..11 : y-intercept of 1st piece wise linear function */ #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ @@ -29247,7 +29581,7 @@ typedef union { /* TEMP_B1: y-intercept of 2nd piece wise linear function */ - #define TEMP_B1_ResetValue (0x00000F76UL) /*!< Reset value of B1 register. */ + #define TEMP_B1_ResetValue (0x00000011UL) /*!< Reset value of B1 register. */ /* B1 @Bits 0..11 : y-intercept of 2nd piece wise linear function */ #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ @@ -29255,7 +29589,7 @@ typedef union { /* TEMP_B2: y-intercept of 3rd piece wise linear function */ - #define TEMP_B2_ResetValue (0x00000F8AUL) /*!< Reset value of B2 register. */ + #define TEMP_B2_ResetValue (0x00000005UL) /*!< Reset value of B2 register. */ /* B2 @Bits 0..11 : y-intercept of 3rd piece wise linear function */ #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ @@ -29263,7 +29597,7 @@ typedef union { /* TEMP_B3: y-intercept of 4th piece wise linear function */ - #define TEMP_B3_ResetValue (0x00000FF8UL) /*!< Reset value of B3 register. */ + #define TEMP_B3_ResetValue (0x0000002BUL) /*!< Reset value of B3 register. */ /* B3 @Bits 0..11 : y-intercept of 4th piece wise linear function */ #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ @@ -29271,7 +29605,7 @@ typedef union { /* TEMP_B4: y-intercept of 5th piece wise linear function */ - #define TEMP_B4_ResetValue (0x000000CCUL) /*!< Reset value of B4 register. */ + #define TEMP_B4_ResetValue (0x0000008FUL) /*!< Reset value of B4 register. */ /* B4 @Bits 0..11 : y-intercept of 5th piece wise linear function */ #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ @@ -29279,7 +29613,7 @@ typedef union { /* TEMP_B5: y-intercept of 6th piece wise linear function */ - #define TEMP_B5_ResetValue (0x00000207UL) /*!< Reset value of B5 register. */ + #define TEMP_B5_ResetValue (0x0000015DUL) /*!< Reset value of B5 register. */ /* B5 @Bits 0..11 : y-intercept of 6th piece wise linear function */ #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ @@ -29287,7 +29621,7 @@ typedef union { /* TEMP_B6: y-intercept of 7th piece wise linear function */ - #define TEMP_B6_ResetValue (0x00000558UL) /*!< Reset value of B6 register. */ + #define TEMP_B6_ResetValue (0x000001C0UL) /*!< Reset value of B6 register. */ /* B6 @Bits 0..11 : y-intercept of 7th piece wise linear function */ #define TEMP_B6_B6_Pos (0UL) /*!< Position of B6 field. */ @@ -29295,7 +29629,7 @@ typedef union { /* TEMP_T0: End point of 1st piece wise linear function */ - #define TEMP_T0_ResetValue (0x000000E2UL) /*!< Reset value of T0 register. */ + #define TEMP_T0_ResetValue (0x000000E5UL) /*!< Reset value of T0 register. */ /* T0 @Bits 0..7 : End point of 1st piece wise linear function */ #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ @@ -29303,7 +29637,7 @@ typedef union { /* TEMP_T1: End point of 2nd piece wise linear function */ - #define TEMP_T1_ResetValue (0x00000002UL) /*!< Reset value of T1 register. */ + #define TEMP_T1_ResetValue (0x000000FBUL) /*!< Reset value of T1 register. */ /* T1 @Bits 0..7 : End point of 2nd piece wise linear function */ #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ @@ -29311,7 +29645,7 @@ typedef union { /* TEMP_T2: End point of 3rd piece wise linear function */ - #define TEMP_T2_ResetValue (0x0000001FUL) /*!< Reset value of T2 register. */ + #define TEMP_T2_ResetValue (0x00000010UL) /*!< Reset value of T2 register. */ /* T2 @Bits 0..7 : End point of 3rd piece wise linear function */ #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ @@ -29319,7 +29653,7 @@ typedef union { /* TEMP_T3: End point of 4th piece wise linear function */ - #define TEMP_T3_ResetValue (0x00000038UL) /*!< Reset value of T3 register. */ + #define TEMP_T3_ResetValue (0x0000002BUL) /*!< Reset value of T3 register. */ /* T3 @Bits 0..7 : End point of 4th piece wise linear function */ #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ @@ -29327,7 +29661,7 @@ typedef union { /* TEMP_T4: End point of 5th piece wise linear function */ - #define TEMP_T4_ResetValue (0x0000004FUL) /*!< Reset value of T4 register. */ + #define TEMP_T4_ResetValue (0x00000041UL) /*!< Reset value of T4 register. */ /* T4 @Bits 0..7 : End point of 5th piece wise linear function */ #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ @@ -29335,7 +29669,7 @@ typedef union { /* TEMP_T5: End point of 6th piece wise linear function */ - #define TEMP_T5_ResetValue (0x00000066UL) /*!< Reset value of T5 register. */ + #define TEMP_T5_ResetValue (0x00000050UL) /*!< Reset value of T5 register. */ /* T5 @Bits 0..7 : End point of 6th piece wise linear function */ #define TEMP_T5_T5_Pos (0UL) /*!< Position of T5 field. */ @@ -30287,7 +30621,8 @@ typedef struct { * @brief RX [TWIM_EVENTS_DMA_RX] Peripheral events. */ typedef struct { - __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t END; /*!< (@ 0x00000000) Indicates that the transfer of MAXCNT bytes between + memory and the peripheral has been fully completed.*/ __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.*/ @@ -30295,10 +30630,12 @@ typedef struct { __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus. */ } NRF_TWIM_EVENTS_DMA_RX_Type; /*!< Size = 28 (0x01C) */ -/* TWIM_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */ +/* TWIM_EVENTS_DMA_RX_END: Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully + completed. */ + #define TWIM_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ -/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ +/* END @Bit 0 : Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed. */ #define TWIM_EVENTS_DMA_RX_END_END_Pos (0UL) /*!< Position of END field. */ #define TWIM_EVENTS_DMA_RX_END_END_Msk (0x1UL << TWIM_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field. */ #define TWIM_EVENTS_DMA_RX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ @@ -30357,17 +30694,20 @@ typedef struct { * @brief TX [TWIM_EVENTS_DMA_TX] Peripheral events. */ typedef struct { - __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t END; /*!< (@ 0x00000000) Indicates that the transfer of MAXCNT bytes between + memory and the peripheral has been fully completed.*/ __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.*/ __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ } NRF_TWIM_EVENTS_DMA_TX_Type; /*!< Size = 12 (0x00C) */ -/* TWIM_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */ +/* TWIM_EVENTS_DMA_TX_END: Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully + completed. */ + #define TWIM_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ -/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ +/* END @Bit 0 : Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed. */ #define TWIM_EVENTS_DMA_TX_END_END_Pos (0UL) /*!< Position of END field. */ #define TWIM_EVENTS_DMA_TX_END_END_Msk (0x1UL << TWIM_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field. */ #define TWIM_EVENTS_DMA_TX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ @@ -30683,7 +31023,7 @@ typedef struct { #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled (0x0UL) /*!< Match filter disabled */ #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled (0x1UL) /*!< Match filter enabled */ -/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or sticky */ +/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or continous */ #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos (16UL) /*!< Position of ONESHOT0 field. */ #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) /*!< Bit mask of ONESHOT0 field.*/ @@ -30692,7 +31032,7 @@ typedef struct { #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ -/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or sticky */ +/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or continous */ #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos (17UL) /*!< Position of ONESHOT1 field. */ #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) /*!< Bit mask of ONESHOT1 field.*/ @@ -30701,7 +31041,7 @@ typedef struct { #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ -/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or sticky */ +/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or continous */ #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos (18UL) /*!< Position of ONESHOT2 field. */ #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) /*!< Bit mask of ONESHOT2 field.*/ @@ -30710,7 +31050,7 @@ typedef struct { #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ -/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or sticky */ +/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or continous */ #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos (19UL) /*!< Position of ONESHOT3 field. */ #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) /*!< Bit mask of ONESHOT3 field.*/ @@ -30726,10 +31066,9 @@ typedef struct { #define TWIM_DMA_RX_MATCH_CANDIDATE_MinIndex (0UL) /*!< Min index of CANDIDATE[4] array. */ #define TWIM_DMA_RX_MATCH_CANDIDATE_ResetValue (0x00000000UL) /*!< Reset value of CANDIDATE[4] register. */ -/* DATA @Bits 0..31 : Data to look for */ +/* DATA @Bits 0..7 : Data to look for */ #define TWIM_DMA_RX_MATCH_CANDIDATE_DATA_Pos (0UL) /*!< Position of DATA field. */ - #define TWIM_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFFFFFFFUL << TWIM_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA - field.*/ + #define TWIM_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFUL << TWIM_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA field. */ @@ -31791,10 +32130,11 @@ typedef struct { #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ #define TWIM_FREQUENCY_FREQUENCY_Min (0x1980000UL) /*!< Min enumerator value of FREQUENCY field. */ - #define TWIM_FREQUENCY_FREQUENCY_Max (0x6400000UL) /*!< Max enumerator value of FREQUENCY field. */ + #define TWIM_FREQUENCY_FREQUENCY_Max (0xFF00000UL) /*!< Max enumerator value of FREQUENCY field. */ #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ + #define TWIM_FREQUENCY_FREQUENCY_K1000 (0x0FF00000UL) /*!< 1000 kbps */ /* TWIM_ADDRESS: Address used in the TWI transfer */ @@ -32394,14 +32734,14 @@ typedef struct { __IM uint32_t RESERVED1[3]; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ - __IOM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR event.*/ __IOM NRF_TWIS_DMA_RX_MATCH_Type MATCH; /*!< (@ 0x00000024) Registers to control the behavior of the pattern matcher engine*/ } NRF_TWIS_DMA_RX_Type; /*!< Size = 56 (0x038) */ /* TWIS_DMA_RX_PTR: RAM buffer start address */ - #define TWIS_DMA_RX_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + #define TWIS_DMA_RX_PTR_ResetValue (0x20000000UL) /*!< Reset value of PTR register. */ /* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ #define TWIS_DMA_RX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ @@ -32467,12 +32807,12 @@ typedef struct { __IM uint32_t RESERVED1[3]; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ - __IOM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR event.*/ } NRF_TWIS_DMA_TX_Type; /*!< Size = 36 (0x024) */ /* TWIS_DMA_TX_PTR: RAM buffer start address */ - #define TWIS_DMA_TX_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + #define TWIS_DMA_TX_PTR_ResetValue (0x20000000UL) /*!< Reset value of PTR register. */ /* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ #define TWIS_DMA_TX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ @@ -36655,12 +36995,12 @@ typedef struct { typedef struct { /*!< VPR Structure */ __OM uint32_t TASKS_TRIGGER[23]; /*!< (@ 0x00000000) VPR task [n] register */ __IM uint32_t RESERVED[9]; - __IOM uint32_t SUBSCRIBE_TRIGGER[4]; /*!< (@ 0x00000080) Subscribe configuration for task TASKS_TRIGGER[n] */ - __IM uint32_t RESERVED1[28]; + __IOM uint32_t SUBSCRIBE_TRIGGER[20]; /*!< (@ 0x00000080) Subscribe configuration for task TASKS_TRIGGER[n] */ + __IM uint32_t RESERVED1[12]; __IOM uint32_t EVENTS_TRIGGERED[23]; /*!< (@ 0x00000100) VPR event [n] register */ __IM uint32_t RESERVED2[9]; - __IOM uint32_t PUBLISH_TRIGGERED[4]; /*!< (@ 0x00000180) Publish configuration for event EVENTS_TRIGGERED[n] */ - __IM uint32_t RESERVED3[92]; + __IOM uint32_t PUBLISH_TRIGGERED[20]; /*!< (@ 0x00000180) Publish configuration for event EVENTS_TRIGGERED[n] */ + __IM uint32_t RESERVED3[76]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -36689,10 +37029,10 @@ typedef struct { /* VPR_SUBSCRIBE_TRIGGER: Subscribe configuration for task TASKS_TRIGGER[n] */ - #define VPR_SUBSCRIBE_TRIGGER_MaxCount (4UL) /*!< Max size of SUBSCRIBE_TRIGGER[4] array. */ - #define VPR_SUBSCRIBE_TRIGGER_MaxIndex (3UL) /*!< Max index of SUBSCRIBE_TRIGGER[4] array. */ - #define VPR_SUBSCRIBE_TRIGGER_MinIndex (0UL) /*!< Min index of SUBSCRIBE_TRIGGER[4] array. */ - #define VPR_SUBSCRIBE_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TRIGGER[4] register. */ + #define VPR_SUBSCRIBE_TRIGGER_MaxCount (4UL) /*!< Max size of SUBSCRIBE_TRIGGER[20] array. */ + #define VPR_SUBSCRIBE_TRIGGER_MaxIndex (19UL) /*!< Max index of SUBSCRIBE_TRIGGER[20] array. */ + #define VPR_SUBSCRIBE_TRIGGER_MinIndex (16UL) /*!< Min index of SUBSCRIBE_TRIGGER[20] array. */ + #define VPR_SUBSCRIBE_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TRIGGER[20] register. */ /* EN @Bit 31 : Subscription enable bit */ #define VPR_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */ @@ -36720,10 +37060,10 @@ typedef struct { /* VPR_PUBLISH_TRIGGERED: Publish configuration for event EVENTS_TRIGGERED[n] */ - #define VPR_PUBLISH_TRIGGERED_MaxCount (4UL) /*!< Max size of PUBLISH_TRIGGERED[4] array. */ - #define VPR_PUBLISH_TRIGGERED_MaxIndex (3UL) /*!< Max index of PUBLISH_TRIGGERED[4] array. */ - #define VPR_PUBLISH_TRIGGERED_MinIndex (0UL) /*!< Min index of PUBLISH_TRIGGERED[4] array. */ - #define VPR_PUBLISH_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TRIGGERED[4] register. */ + #define VPR_PUBLISH_TRIGGERED_MaxCount (4UL) /*!< Max size of PUBLISH_TRIGGERED[20] array. */ + #define VPR_PUBLISH_TRIGGERED_MaxIndex (19UL) /*!< Max index of PUBLISH_TRIGGERED[20] array. */ + #define VPR_PUBLISH_TRIGGERED_MinIndex (16UL) /*!< Min index of PUBLISH_TRIGGERED[20] array. */ + #define VPR_PUBLISH_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TRIGGERED[20] register. */ /* EN @Bit 31 : Publication enable bit */ #define VPR_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */ @@ -38520,41 +38860,41 @@ typedef struct { #define VPRCSR_NORDIC_SUBSCRIBE (0x000007E1ul) #define VPRCSR_NORDIC_SUBSCRIBE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE register. */ -/* SUBSCRIBE0 @Bit 0 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Pos (0UL) /*!< Position of SUBSCRIBE0 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Pos) /*!< Bit mask of SUBSCRIBE0 - field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE0 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE0 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Disabled (0x0UL) /*!< Subscribe disabled for TASK[0] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Enabled (0x1UL) /*!< Subscribe enabled for TASK[0] */ - -/* SUBSCRIBE1 @Bit 1 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Pos (1UL) /*!< Position of SUBSCRIBE1 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Pos) /*!< Bit mask of SUBSCRIBE1 - field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE1 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE1 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Disabled (0x0UL) /*!< Subscribe disabled for TASK[1] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Enabled (0x1UL) /*!< Subscribe enabled for TASK[1] */ - -/* SUBSCRIBE2 @Bit 2 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Pos (2UL) /*!< Position of SUBSCRIBE2 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Pos) /*!< Bit mask of SUBSCRIBE2 - field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE2 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE2 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Disabled (0x0UL) /*!< Subscribe disabled for TASK[2] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Enabled (0x1UL) /*!< Subscribe enabled for TASK[2] */ - -/* SUBSCRIBE3 @Bit 3 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Pos (3UL) /*!< Position of SUBSCRIBE3 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Pos) /*!< Bit mask of SUBSCRIBE3 - field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE3 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE3 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Disabled (0x0UL) /*!< Subscribe disabled for TASK[3] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Enabled (0x1UL) /*!< Subscribe enabled for TASK[3] */ +/* SUBSCRIBE16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Pos (16UL) /*!< Position of SUBSCRIBE16 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Pos) /*!< Bit mask of + SUBSCRIBE16 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE16 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE16 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Disabled (0x0UL) /*!< Subscribe disabled for TASK[16] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Enabled (0x1UL) /*!< Subscribe enabled for TASK[16] */ + +/* SUBSCRIBE17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Pos (17UL) /*!< Position of SUBSCRIBE17 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Pos) /*!< Bit mask of + SUBSCRIBE17 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE17 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE17 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Disabled (0x0UL) /*!< Subscribe disabled for TASK[17] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Enabled (0x1UL) /*!< Subscribe enabled for TASK[17] */ + +/* SUBSCRIBE18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Pos (18UL) /*!< Position of SUBSCRIBE18 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Pos) /*!< Bit mask of + SUBSCRIBE18 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE18 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE18 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Disabled (0x0UL) /*!< Subscribe disabled for TASK[18] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Enabled (0x1UL) /*!< Subscribe enabled for TASK[18] */ + +/* SUBSCRIBE19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Pos (19UL) /*!< Position of SUBSCRIBE19 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Pos) /*!< Bit mask of + SUBSCRIBE19 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE19 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE19 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Disabled (0x0UL) /*!< Subscribe disabled for TASK[19] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Enabled (0x1UL) /*!< Subscribe enabled for TASK[19] */ /** @@ -38826,37 +39166,37 @@ typedef struct { #define VPRCSR_NORDIC_PUBLISH (0x000007E3ul) #define VPRCSR_NORDIC_PUBLISH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH register. */ -/* PUBLISH0 @Bit 0 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Pos (0UL) /*!< Position of PUBLISH0 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH0_Pos) /*!< Bit mask of PUBLISH0 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Min (0x0UL) /*!< Min enumerator value of PUBLISH0 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Max (0x1UL) /*!< Max enumerator value of PUBLISH0 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Disabled (0x0UL) /*!< Publish disabled for EVENTS[0] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Enabled (0x1UL) /*!< Publish enabled for EVENTS[0] */ - -/* PUBLISH1 @Bit 1 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Pos (1UL) /*!< Position of PUBLISH1 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH1_Pos) /*!< Bit mask of PUBLISH1 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Min (0x0UL) /*!< Min enumerator value of PUBLISH1 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Max (0x1UL) /*!< Max enumerator value of PUBLISH1 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Disabled (0x0UL) /*!< Publish disabled for EVENTS[1] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Enabled (0x1UL) /*!< Publish enabled for EVENTS[1] */ - -/* PUBLISH2 @Bit 2 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Pos (2UL) /*!< Position of PUBLISH2 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH2_Pos) /*!< Bit mask of PUBLISH2 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Min (0x0UL) /*!< Min enumerator value of PUBLISH2 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Max (0x1UL) /*!< Max enumerator value of PUBLISH2 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Disabled (0x0UL) /*!< Publish disabled for EVENTS[2] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Enabled (0x1UL) /*!< Publish enabled for EVENTS[2] */ - -/* PUBLISH3 @Bit 3 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Pos (3UL) /*!< Position of PUBLISH3 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH3_Pos) /*!< Bit mask of PUBLISH3 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Min (0x0UL) /*!< Min enumerator value of PUBLISH3 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Max (0x1UL) /*!< Max enumerator value of PUBLISH3 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Disabled (0x0UL) /*!< Publish disabled for EVENTS[3] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Enabled (0x1UL) /*!< Publish enabled for EVENTS[3] */ +/* PUBLISH16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Pos (16UL) /*!< Position of PUBLISH16 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH16_Pos) /*!< Bit mask of PUBLISH16 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Min (0x0UL) /*!< Min enumerator value of PUBLISH16 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Max (0x1UL) /*!< Max enumerator value of PUBLISH16 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Disabled (0x0UL) /*!< Publish disabled for EVENTS[16] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Enabled (0x1UL) /*!< Publish enabled for EVENTS[16] */ + +/* PUBLISH17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Pos (17UL) /*!< Position of PUBLISH17 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH17_Pos) /*!< Bit mask of PUBLISH17 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Min (0x0UL) /*!< Min enumerator value of PUBLISH17 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Max (0x1UL) /*!< Max enumerator value of PUBLISH17 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Disabled (0x0UL) /*!< Publish disabled for EVENTS[17] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Enabled (0x1UL) /*!< Publish enabled for EVENTS[17] */ + +/* PUBLISH18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Pos (18UL) /*!< Position of PUBLISH18 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH18_Pos) /*!< Bit mask of PUBLISH18 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Min (0x0UL) /*!< Min enumerator value of PUBLISH18 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Max (0x1UL) /*!< Max enumerator value of PUBLISH18 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Disabled (0x0UL) /*!< Publish disabled for EVENTS[18] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Enabled (0x1UL) /*!< Publish enabled for EVENTS[18] */ + +/* PUBLISH19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Pos (19UL) /*!< Position of PUBLISH19 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH19_Pos) /*!< Bit mask of PUBLISH19 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Min (0x0UL) /*!< Min enumerator value of PUBLISH19 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Max (0x1UL) /*!< Max enumerator value of PUBLISH19 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Disabled (0x0UL) /*!< Publish disabled for EVENTS[19] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Enabled (0x1UL) /*!< Publish enabled for EVENTS[19] */ /** diff --git a/nrfx/mdk/nrf54lv10a_enga_version.h b/nrfx/mdk/nrf54lv10a_enga_version.h index 09f78eab..e4d65e30 100644 --- a/nrfx/mdk/nrf54lv10a_enga_version.h +++ b/nrfx/mdk/nrf54lv10a_enga_version.h @@ -40,9 +40,9 @@ POSSIBILITY OF SUCH DAMAGE. #endif -#define MDK_SOURCE_VERSION_MAJOR 0 /*!< Major version of product specification. */ -#define MDK_SOURCE_VERSION_MINOR 5rc1 /*!< Minor version of product specification. */ -#define MDK_SOURCE_VERSION_MICRO /*!< Micro version of product specification. */ +#define MDK_SOURCE_VERSION_MAJOR 0 /*!< Major version of the datasheet. */ +#define MDK_SOURCE_VERSION_MINOR 6a /*!< Minor version of the datasheet. */ +#define MDK_SOURCE_VERSION_MICRO /*!< Micro version of the datasheet. */ #ifdef __cplusplus diff --git a/nrfx/mdk/system_nrf54l.c b/nrfx/mdk/system_nrf54l.c index 99d81051..eb5df79e 100644 --- a/nrfx/mdk/system_nrf54l.c +++ b/nrfx/mdk/system_nrf54l.c @@ -37,11 +37,21 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #define __SYSTEM_CLOCK_DEFAULT (64000000ul) /* Trace configuration */ +#if defined (NRF54LV10A_ENGA_XXAA) +#define TRACE_PORT NRF_P1_S +#define TRACE_TRACECLK_PIN (10ul) +#define TRACE_TRACEDATA0_PIN (11ul) +#define TRACE_TRACEDATA1_PIN (12ul) +#define TRACE_TRACEDATA2_PIN (13ul) +#define TRACE_TRACEDATA3_PIN (14ul) +#else +#define TRACE_PORT NRF_P2_S #define TRACE_TRACECLK_PIN (6ul) #define TRACE_TRACEDATA0_PIN (7ul) #define TRACE_TRACEDATA1_PIN (8ul) #define TRACE_TRACEDATA2_PIN (9ul) #define TRACE_TRACEDATA3_PIN (10ul) +#endif #define TRACE_PIN_CLEAR (~(GPIO_PIN_CNF_CTRLSEL_Msk | GPIO_PIN_CNF_DRIVE0_Msk | GPIO_PIN_CNF_DRIVE1_Msk)) @@ -234,11 +244,11 @@ void SystemInit(void) NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk; // Configure trace port pads - NRF_P2_S->PIN_CNF[TRACE_TRACECLK_PIN] &= TRACE_PIN_CLEAR; - NRF_P2_S->PIN_CNF[TRACE_TRACEDATA0_PIN] &= TRACE_PIN_CLEAR; + TRACE_PORT->PIN_CNF[TRACE_TRACECLK_PIN] &= TRACE_PIN_CLEAR; + TRACE_PORT->PIN_CNF[TRACE_TRACEDATA0_PIN] &= TRACE_PIN_CLEAR; - NRF_P2_S->PIN_CNF[TRACE_TRACECLK_PIN] |= TRACE_PIN_CONFIG; - NRF_P2_S->PIN_CNF[TRACE_TRACEDATA0_PIN] |= TRACE_PIN_CONFIG; + TRACE_PORT->PIN_CNF[TRACE_TRACECLK_PIN] |= TRACE_PIN_CONFIG; + TRACE_PORT->PIN_CNF[TRACE_TRACEDATA0_PIN] |= TRACE_PIN_CONFIG; // Configure trace port speed NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_DIV2; @@ -251,17 +261,17 @@ void SystemInit(void) NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk; // Configure trace port pads - NRF_P2_S->PIN_CNF[TRACE_TRACECLK_PIN] &= TRACE_PIN_CLEAR; - NRF_P2_S->PIN_CNF[TRACE_TRACEDATA0_PIN] &= TRACE_PIN_CLEAR; - NRF_P2_S->PIN_CNF[TRACE_TRACEDATA1_PIN] &= TRACE_PIN_CLEAR; - NRF_P2_S->PIN_CNF[TRACE_TRACEDATA2_PIN] &= TRACE_PIN_CLEAR; - NRF_P2_S->PIN_CNF[TRACE_TRACEDATA3_PIN] &= TRACE_PIN_CLEAR; - - NRF_P2_S->PIN_CNF[TRACE_TRACECLK_PIN] |= TRACE_PIN_CONFIG; - NRF_P2_S->PIN_CNF[TRACE_TRACEDATA0_PIN] |= TRACE_PIN_CONFIG; - NRF_P2_S->PIN_CNF[TRACE_TRACEDATA1_PIN] |= TRACE_PIN_CONFIG; - NRF_P2_S->PIN_CNF[TRACE_TRACEDATA2_PIN] |= TRACE_PIN_CONFIG; - NRF_P2_S->PIN_CNF[TRACE_TRACEDATA3_PIN] |= TRACE_PIN_CONFIG; + TRACE_PORT->PIN_CNF[TRACE_TRACECLK_PIN] &= TRACE_PIN_CLEAR; + TRACE_PORT->PIN_CNF[TRACE_TRACEDATA0_PIN] &= TRACE_PIN_CLEAR; + TRACE_PORT->PIN_CNF[TRACE_TRACEDATA1_PIN] &= TRACE_PIN_CLEAR; + TRACE_PORT->PIN_CNF[TRACE_TRACEDATA2_PIN] &= TRACE_PIN_CLEAR; + TRACE_PORT->PIN_CNF[TRACE_TRACEDATA3_PIN] &= TRACE_PIN_CLEAR; + + TRACE_PORT->PIN_CNF[TRACE_TRACECLK_PIN] |= TRACE_PIN_CONFIG; + TRACE_PORT->PIN_CNF[TRACE_TRACEDATA0_PIN] |= TRACE_PIN_CONFIG; + TRACE_PORT->PIN_CNF[TRACE_TRACEDATA1_PIN] |= TRACE_PIN_CONFIG; + TRACE_PORT->PIN_CNF[TRACE_TRACEDATA2_PIN] |= TRACE_PIN_CONFIG; + TRACE_PORT->PIN_CNF[TRACE_TRACEDATA3_PIN] |= TRACE_PIN_CONFIG; // Configure trace port speed NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_DIV2;