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s32: drivers: s32ze: add ADC peripheral driver
Add sources code driver for ADC Signed-off-by: Ha Duong Quang <[email protected]>
1 parent 7e6109c commit 0a5be97

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‎s32/drivers/s32ze/Adc/CMakeLists.txt

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# Copyright 2024 NXP
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# SPDX-License-Identifier: BSD-3-Clause
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zephyr_include_directories(include)
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zephyr_library_sources(src/Adc_Sar_Ip.c)
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zephyr_library_sources(src/Adc_Sar_Ip_Irq.c)

‎s32/drivers/s32ze/Adc/include/Adc_Sar_Ip.h

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‎s32/drivers/s32ze/Adc/include/Adc_Sar_Ip_HeaderWrapper_S32XX.h

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/*
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* Copyright 2021-2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ADC_SAR_IP_HEADERWRAPPER_S32XX_H
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#define ADC_SAR_IP_HEADERWRAPPER_S32XX_H
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/**
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* @file
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*
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* @addtogroup adc_sar_ip Adc Sar IPL
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* @{
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*/
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#ifdef __cplusplus
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extern "C"{
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#endif
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/* Important Note: This file cannot be used independently.
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* It depends on platform header files to be included before including it */
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/*==================================================================================================
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* SOURCE FILE VERSION INFORMATION
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==================================================================================================*/
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#define ADC_SAR_IP_VENDOR_ID_HEADERWRAPPER_S32XX 43
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#define ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_HEADERWRAPPER_S32XX 4
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#define ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_HEADERWRAPPER_S32XX 7
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#define ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_HEADERWRAPPER_S32XX 0
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#define ADC_SAR_IP_SW_MAJOR_VERSION_HEADERWRAPPER_S32XX 2
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#define ADC_SAR_IP_SW_MINOR_VERSION_HEADERWRAPPER_S32XX 0
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#define ADC_SAR_IP_SW_PATCH_VERSION_HEADERWRAPPER_S32XX 0
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/*==================================================================================================
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* DEFINITIONS
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==================================================================================================*/
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#define ADC_SAR_IP_NUM_GROUP_CHAN (2U)
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#define ADC_SAR_IP_CDR_COUNT (39U)
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#define ADC_SAR_IP_INSTANCE_COUNT ADC_INSTANCE_COUNT
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#define ADC_SAR_IP_THRHLR_COUNT (8U)
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#define ADC_SAR_IP_CWSELR_COUNT (2U)
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#define ADC_SAR_IP_MAX_RESOLUTION (12U)
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#define ADC_SAR_IP_HAS_THRHLR_ARRAY (0U)
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#define ADC_SAR_IP_HAS_CWSELR_UNROLLED (1U)
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#define ADC_SAR_IP_CALIBRATION_USES_MCR (1U)
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#define ADC_SAR_IP_PRESAMPLE_DVDD_EVAL (0U)
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#define ADC_SAR_IP_PRESAMPLE_AVDD_EVAL (1U)
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#define ADC_SAR_IP_PRESAMPLE_VREFL_EVAL (2U)
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#define ADC_SAR_IP_PRESAMPLE_VREFH_EVAL (3U)
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#define ADC_SAR_IP_HAS_CWSELR0 (1U)
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#define ADC_SAR_IP_HAS_CWSELR1 (0U)
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#define ADC_SAR_IP_HAS_CWSELR2 (0U)
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#define ADC_SAR_IP_HAS_CWSELR3 (0U)
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#define ADC_SAR_IP_HAS_CWSELR4 (1U)
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#define ADC_SAR_IP_HAS_CWSELR5 (0U)
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#define ADC_SAR_IP_HAS_CWSELR6 (0U)
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#define ADC_SAR_IP_HAS_CWSELR7 (0U)
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#define ADC_SAR_IP_HAS_CWSELR8 (0U)
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#define ADC_SAR_IP_HAS_CWSELR9 (0U)
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#define ADC_SAR_IP_HAS_CWSELR10 (0U)
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#define ADC_SAR_IP_HAS_CWSELR11 (0U)
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#define ADC_SAR_IP_HAS_ADCLKSEL (1U)
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#define ADC_SAR_IP_MSR_ADCSTATUS_POWER_DOWN (1U)
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#define ADC_SAR_IP_MSR_ADCSTATUS_IDLE (0U)
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#define ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE (1U)
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#define ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL (1U)
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#define ADC_SAR_IP_HAS_CTU_TRIGGER_MODE (1U)
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#define ADC_SAR_IP_HAS_CTU (1U)
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#define ADC_SAR_IP_HAS_CLKSEL_EXTENDED (0U)
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#define ADC_SAR_IP_W1C_ABORT (0U)
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#define ADC_SAR_IP_HAS_TEMPSENSE_CHN (0U)
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#define ADC_SAR_IP_SELFTEST_FULL_CLK (1U)
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#define ADC_SAR_IP_HAS_SELFTEST_STCR1 (1U)
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#define ADC_SAR_IP_HAS_SELFTEST_STCR3 (1U)
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#define ADC_SAR_IP_HAS_BANDGAP_STATUS (0U)
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#define ADC_SAR_IP_HAS_SELFTEST_USE_CH32 (0U)
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#define ADC_SAR_IP_ABORTCHAIN_WORKAROUND (1U)
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#if (ADC_SAR_IP_INSTANCE_COUNT == 2U)
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/* 31-28 3-0 63-60 35-32 95-92 67-64
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\_/ \_/ \_/ \_/ \_/ \_/
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|......| |......| |......| */
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#define FEATURE_ADC_CHN_AVAIL_BITMAP {{0x000000FFU, 0x00000079U}, /* 0 */ \
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{0x000000FFU, 0x00000079U}, /* 1 */ \
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}
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/* Adc Channels are divided into 2 Groups. */
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/* This array shows max number of channels of each group. */
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/* There are some registers that relate to this one: CEOCFR, CIMR, DMAR, PSR, NCMR, JCMR,... */
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/* Should be same with ADC_CDRx_COUNT in header file (from Base) */
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#define FEATURE_ADC_MAX_CHN_COUNT {{8U, 8U}, /* 0 */ \
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{8U, 8U}, /* 1 */ \
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}
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/* Number of group channels of each unit*/
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/* Unit 0 / 1 */
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#define FEATURE_ADC_MAX_GROUP_COUNT { 2U, 2U }
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/* Bit0: DSDR is available
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Bit1: PSCR is available
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Bit2: CTU is available
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Bit3: CTU trigger mode is available */
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#define FEATURE_ADC_FEAT_AVAIL_BITMAP {0x0000000EU, /* 0 */ \
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0x0000000EU, /* 1 */ \
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}
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#else
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/* 31-28 3-0 63-60 35-32 95-92 67-64
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\_/ \_/ \_/ \_/ \_/ \_/
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|......| |......| |......| */
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#define FEATURE_ADC_CHN_AVAIL_BITMAP {{0x000000FFU, 0x00000079U}, /* 0 */ \
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}
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/* Adc Channels are divided into 2 Groups. */
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/* This array shows max number of channels of each group. */
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/* There are some registers that relate to this one: CEOCFR, CIMR, DMAR, PSR, NCMR, JCMR,... */
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/* Should be same with ADC_CDRx_COUNT in header file (from Base) */
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#define FEATURE_ADC_MAX_CHN_COUNT {{8U, 8U}, /* 0 */ \
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}
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/* Number of group channels of each unit*/
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/* Unit 0 */
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#define FEATURE_ADC_MAX_GROUP_COUNT { 2U }
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/* Bit0: DSDR is available
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Bit1: PSCR is available
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Bit2: CTU is available
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Bit3: CTU trigger mode is available */
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#define FEATURE_ADC_FEAT_AVAIL_BITMAP {0x0000000EU, /* 0 */ \
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}
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#endif /* (ADC_SAR_IP_INSTANCE_COUNT == 2U) */
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/* Register access defines */
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#define REG_ACCESS(reg, index) (*(volatile uint32*)(&(((&(reg))[(index)]))))
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#define REG_READ(reg, index) (*(volatile const uint32*)(&(((&(reg))[(index)]))))
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#define CEOCFR(base, regIndex) REG_ACCESS((base)->CEOCFR0, (regIndex))
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#define CIMR(base, regIndex) REG_ACCESS((base)->CIMR0, (regIndex))
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#define DMAR(base, regIndex) REG_ACCESS((base)->DMAR0, (regIndex))
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#define PSR(base, regIndex) REG_ACCESS((base)->PSR0, (regIndex))
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#define CTR(base, regIndex) REG_ACCESS((base)->CTR0, (regIndex))
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#define NCMR(base, regIndex) REG_ACCESS((base)->NCMR0, (regIndex))
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#define JCMR(base, regIndex) REG_ACCESS((base)->JCMR0, (regIndex))
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#define CWSELR(base, regIndex) REG_ACCESS((base)->CWSELR, (regIndex))
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#define CWENR(base, regIndex) REG_ACCESS((base)->CWENR0, (regIndex))
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#define AWORR(base, regIndex) REG_ACCESS((base)->AWORR0, (regIndex))
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#define CDR(base, chanIndex) REG_READ((base)->PCDR[0U], (chanIndex))
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/* MCR */
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#define ADC_MCR_ADCLKSEL_MASK ADC_MCR_ADCLKSE_MASK
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#define ADC_MCR_ADCLKSEL(x) ADC_MCR_ADCLKSE(x)
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/* CTR */
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#define ADC_CTR_INPSAMP(x) ADC_CTR0_INPSAMP(x)
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/* NCMR */
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#define ADC_NCMR_CH0(x) ADC_NCMR0_CH0(x)
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/* CDR */
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#define ADC_CDR_CDATA_MASK ADC_PCDR_CDATA_MASK
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#define ADC_CDR_CDATA_SHIFT ADC_PCDR_CDATA_SHIFT
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#define ADC_CDR_RESULT_MASK ADC_PCDR_RESULT_MASK
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#define ADC_CDR_RESULT(x) ADC_PCDR_RESULT(x)
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#define ADC_CDR_OVERW_MASK ADC_PCDR_OVERW_MASK
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#define ADC_CDR_OVERW_SHIFT ADC_PCDR_OVERW_SHIFT
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#define ADC_CDR_VALID_MASK ADC_PCDR_VALID_MASK
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/* USROFSGN - Offset and Gain User */
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#define ADC_USER_OFFSET_GAIN_REG USROFSGN
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#define ADC_USER_OFFSET(x) ADC_USROFSGN_OFFSUSER(x)
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#define ADC_USER_GAIN(x) ADC_USROFSGN_GAINUSER(x)
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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#endif /* ADC_SAR_IP_HEADERWRAPPER_S32XX_H */

‎s32/drivers/s32ze/Adc/include/Adc_Sar_Ip_HeaderWrapper_S32XX_AE.h

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/*
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* Copyright 2021-2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ADC_SAR_IP_HEADERWRAPPER_S32XX_AE_H
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#define ADC_SAR_IP_HEADERWRAPPER_S32XX_AE_H
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/**
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* @file
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*
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* @addtogroup adc_sar_ip Adc Sar IPL
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* @{
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*/
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#ifdef __cplusplus
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extern "C"{
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#endif
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/* Important Note: This file cannot be used independently.
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* It depends on platform header files to be included before including it */
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/*==================================================================================================
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* SOURCE FILE VERSION INFORMATION
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==================================================================================================*/
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#define ADC_SAR_IP_VENDOR_ID_HEADERWRAPPER_S32XX_AE 43
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#define ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_HEADERWRAPPER_S32XX_AE 4
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#define ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_HEADERWRAPPER_S32XX_AE 7
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#define ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_HEADERWRAPPER_S32XX_AE 0
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#define ADC_SAR_IP_SW_MAJOR_VERSION_HEADERWRAPPER_S32XX_AE 2
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#define ADC_SAR_IP_SW_MINOR_VERSION_HEADERWRAPPER_S32XX_AE 0
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#define ADC_SAR_IP_SW_PATCH_VERSION_HEADERWRAPPER_S32XX_AE 0
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/*==================================================================================================
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* DEFINITIONS
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==================================================================================================*/
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#define ADC_SAR_IP_NUM_GROUP_CHAN (2U)
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#define ADC_SAR_IP_CDR_COUNT (39U)
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#define ADC_SAR_IP_INSTANCE_COUNT (ADC_INSTANCE_COUNT + SAR_ADC_AE_INSTANCE_COUNT)
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#define ADC_SAR_IP_THRHLR_COUNT (8U)
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#define ADC_SAR_AE_IP_THRHLR_COUNT (16U)
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#define ADC_SAR_IP_CWSELR_COUNT (2U)
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#define ADC_SAR_AE_IP_CWSELR_COUNT (3U)
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#define ADC_SAR_IP_MAX_RESOLUTION (12U)
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#define ADC_SAR_IP_HAS_THRHLR_ARRAY (0U)
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#define ADC_SAR_IP_HAS_CWSELR_UNROLLED (1U)
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#define ADC_SAR_IP_CALIBRATION_USES_MCR (1U)
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#define ADC_SAR_IP_PRESAMPLE_DVDD_EVAL (0U)
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#define ADC_SAR_IP_PRESAMPLE_AVDD_EVAL (1U)
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#define ADC_SAR_IP_PRESAMPLE_VREFL_EVAL (2U)
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#define ADC_SAR_IP_PRESAMPLE_VREFH_EVAL (3U)
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#define ADC_SAR_IP_HAS_CWSELR0 (1U)
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#define ADC_SAR_IP_HAS_CWSELR1 (0U)
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#define ADC_SAR_IP_HAS_CWSELR2 (0U)
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#define ADC_SAR_IP_HAS_CWSELR3 (0U)
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#define ADC_SAR_IP_HAS_CWSELR4 (1U)
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#define ADC_SAR_IP_HAS_CWSELR5 (0U)
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#define ADC_SAR_IP_HAS_CWSELR6 (0U)
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#define ADC_SAR_IP_HAS_CWSELR7 (0U)
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#define ADC_SAR_IP_HAS_CWSELR8 (0U)
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#define ADC_SAR_IP_HAS_CWSELR9 (0U)
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#define ADC_SAR_IP_HAS_CWSELR10 (0U)
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#define ADC_SAR_IP_HAS_CWSELR11 (0U)
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#define ADC_SAR_IP_HAS_ADCLKSEL (1U)
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#define ADC_SAR_IP_MSR_ADCSTATUS_POWER_DOWN (1U)
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#define ADC_SAR_IP_MSR_ADCSTATUS_IDLE (0U)
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#define ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE (1U)
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#define ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL (1U)
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#define ADC_SAR_IP_HAS_CTU_TRIGGER_MODE (1U)
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#define ADC_SAR_IP_HAS_CTU (1U)
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#define ADC_SAR_IP_HAS_CLKSEL_EXTENDED (0U)
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#define ADC_SAR_IP_W1C_ABORT (0U)
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#define ADC_SAR_IP_HAS_TEMPSENSE_CHN (0U)
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#define ADC_SAR_IP_SELFTEST_FULL_CLK (1U)
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#define ADC_SAR_IP_HAS_SELFTEST_STCR1 (1U)
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#define ADC_SAR_IP_HAS_SELFTEST_STCR3 (1U)
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#define ADC_SAR_IP_HAS_BANDGAP_STATUS (0U)
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#define ADC_SAR_IP_HAS_SELFTEST_USE_CH32 (0U)
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#define ADC_SAR_IP_ABORTCHAIN_WORKAROUND (1U)
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/* 31-28 3-0 63-60 35-32 95-92 67-64
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\_/ \_/ \_/ \_/ \_/ \_/
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|......| |......| |......| */
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#define FEATURE_ADC_CHN_AVAIL_BITMAP {{0x000000FFU, 0x00000079U}, /* 0 */ \
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{0x000000FFU, 0x00000079U}, /* 1 */ \
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{0x00FFFFFFU, 0x00000000U}, /* 2 (ADC_AE_0_0) */ \
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{0x00001FFFU, 0x00000000U}, /* 3 (ADC_AE_1_0) */ \
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{0x00001FFFU, 0x00000000U}, /* 4 (ADC_AE_1_1) */ \
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{0x00001FFFU, 0x00000000U}, /* 5 (ADC_AE_2_0) */ \
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{0x00001FFFU, 0x00000000U}, /* 6 (ADC_AE_2_1) */ \
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}
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/* Adc Channels are divided into 2 Groups. */
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/* This array shows max number of channels of each group. */
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/* There are some registers that relate to this one: CEOCFR, CIMR, DMAR, PSR, NCMR, JCMR,... */
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/* Should be same with ADC_CDRx_COUNT in header file (from Base) */
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#define FEATURE_ADC_MAX_CHN_COUNT {{8U, 8U}, /* 0 */ \
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{8U, 8U}, /* 1 */ \
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{24U, 0U}, /* 2 (ADC_AE_0_0) */ \
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{13U, 0U}, /* 3 (ADC_AE_1_0) */ \
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{13U, 0U}, /* 4 (ADC_AE_1_1) */ \
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{13U, 0U}, /* 5 (ADC_AE_2_0) */ \
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{13U, 0U}, /* 6 (ADC_AE_2_1) */ \
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}
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/* Number of group channels of each unit */
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/* Unit 0 / 1 / 2 (ADC_AE_0_0)/ 3 (ADC_AE_1_0)/ 4 (ADC_AE_1_1)/ 5 (ADC_AE_2_0)/ 6 (ADC_AE_2_1) */
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#define FEATURE_ADC_MAX_GROUP_COUNT { 2U, 2U, 1U, 1U, 1U, 1U, 1U }
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/* Bit0: DSDR is available
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Bit1: PSCR is available
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Bit2: CTU is available
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Bit3: CTU trigger mode is available */
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#define FEATURE_ADC_FEAT_AVAIL_BITMAP {0x0000000EU, /* 0 */ \
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0x0000000EU, /* 1 */ \
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0x00000002U, /* 2 (ADC_AE_0_0) */ \
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0x00000006U, /* 3 (ADC_AE_1_0) */ \
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0x00000006U, /* 4 (ADC_AE_1_1) */ \
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0x00000006U, /* 5 (ADC_AE_2_0) */ \
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0x00000006U, /* 6 (ADC_AE_2_1) */ \
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}
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/* Register access defines */
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#define REG_ACCESS(reg, index) (*(volatile uint32*)(&(((&(reg))[(index)]))))
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#define REG_READ(reg, index) (*(volatile const uint32*)(&(((&(reg))[(index)]))))
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#define CEOCFR(base, regIndex) REG_ACCESS((base)->CEOCFR0, (regIndex))
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#define CIMR(base, regIndex) REG_ACCESS((base)->CIMR0, (regIndex))
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#define DMAR(base, regIndex) REG_ACCESS((base)->DMAR0, (regIndex))
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#define PSR(base, regIndex) REG_ACCESS((base)->PSR0, (regIndex))
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#define CTR(base, regIndex) REG_ACCESS((base)->CTR0, (regIndex))
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#define NCMR(base, regIndex) REG_ACCESS((base)->NCMR0, (regIndex))
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#define JCMR(base, regIndex) REG_ACCESS((base)->JCMR0, (regIndex))
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#define CWSELR(base, regIndex) REG_ACCESS((base)->CWSELR, (regIndex))
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#define CWENR(base, regIndex) REG_ACCESS((base)->CWENR0, (regIndex))
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#define AWORR(base, regIndex) REG_ACCESS((base)->AWORR0, (regIndex))
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#define CDR(base, chanIndex) REG_READ((base)->PCDR[0U], (chanIndex))
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#define CDR_AE(base, chanIndex) REG_READ((base)->CDR[0U], (chanIndex))
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/* MCR */
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#define ADC_MCR_ADCLKSEL_MASK ADC_MCR_ADCLKSE_MASK
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#define ADC_MCR_ADCLKSEL(x) ADC_MCR_ADCLKSE(x)
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/* CTR */
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#define ADC_CTR_INPSAMP(x) ADC_CTR0_INPSAMP(x)
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/* NCMR */
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#define ADC_NCMR_CH0(x) ADC_NCMR0_CH0(x)
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/* CDR */
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#define ADC_CDR_CDATA_MASK ADC_PCDR_CDATA_MASK
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#define ADC_CDR_CDATA_SHIFT ADC_PCDR_CDATA_SHIFT
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#define ADC_CDR_RESULT_MASK ADC_PCDR_RESULT_MASK
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#define ADC_CDR_RESULT(x) ADC_PCDR_RESULT(x)
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#define ADC_CDR_OVERW_MASK ADC_PCDR_OVERW_MASK
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#define ADC_CDR_OVERW_SHIFT ADC_PCDR_OVERW_SHIFT
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#define ADC_CDR_VALID_MASK ADC_PCDR_VALID_MASK
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/* USROFSGN - Offset and Gain User */
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#define ADC_USER_OFFSET_GAIN_REG USROFSGN
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#define ADC_USER_OFFSET(x) ADC_USROFSGN_OFFSUSER(x)
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#define ADC_USER_GAIN(x) ADC_USROFSGN_GAINUSER(x)
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#define ADC_AE_USER_OFFSET_GAIN_REG OFSGNUSR
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#define ADC_AE_USER_OFFSET(x) SAR_ADC_AE_OFSGNUSR_OFFSET_USER(x)
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#define ADC_AE_USER_GAIN(x) SAR_ADC_AE_OFSGNUSR_GAIN_USER(x)
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/*! @name CALBISTREG - Control And Calibration Status */
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/*! @{ */
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#define ADC_SAR_IP_CALBISTREG_TEST_EN_MASK SAR_ADC_AE_CALBISTREG_TEST_EN_MASK
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#define ADC_SAR_IP_CALBISTREG_TEST_EN(x) SAR_ADC_AE_CALBISTREG_TEST_EN(x)
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#define ADC_SAR_IP_CALBISTREG_TEST_FAIL_MASK SAR_ADC_AE_CALBISTREG_TEST_FAIL_MASK
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#define ADC_SAR_IP_CALBISTREG_AVG_EN_MASK SAR_ADC_AE_CALBISTREG_AVG_EN_MASK
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#define ADC_SAR_IP_CALBISTREG_AVG_EN(x) SAR_ADC_AE_CALBISTREG_AVG_EN(x)
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#define ADC_SAR_IP_CALBISTREG_NR_SMPL_MASK SAR_ADC_AE_CALBISTREG_NR_SMPL_MASK
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#define ADC_SAR_IP_CALBISTREG_NR_SMPL(x) SAR_ADC_AE_CALBISTREG_NR_SMPL(x)
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#define ADC_SAR_IP_CALBISTREG_C_T_BUSY_MASK SAR_ADC_AE_CALBISTREG_C_T_BUSY_MASK
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#define ADC_SAR_IP_CALBISTREG_TSAMP_MASK SAR_ADC_AE_CALBISTREG_TSAMP_MASK
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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#endif /* ADC_SAR_IP_HEADERWRAPPER_S32XX_H */

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