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s32: soc: s32z2: add QSPI soc specific code
Code autogenerated with S32 Design Studio for s32ze Signed-off-by: Cong Nguyen Huu <[email protected]>
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‎s32/soc/s32z270/include/Qspi_Ip_Cfg.h

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QSPI_IP_CFG_H
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#define QSPI_IP_CFG_H
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/**
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* @file Qspi_Ip_Cfg.h
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*
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* @addtogroup MEM_EXFLS
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* Qspi_Ip_Cfg.h_Artifact
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* @{
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*/
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#ifdef __cplusplus
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extern "C"{
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#endif
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/*==================================================================================================
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* INCLUDE FILES
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* 1) system and project includes
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* 2) needed interfaces from external units
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* 3) internal and external interfaces from this unit
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==================================================================================================*/
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#include "Qspi_Ip_Types.h"
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/*==================================================================================================
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* SOURCE FILE VERSION INFORMATION
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==================================================================================================*/
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#define QSPI_IP_VENDOR_ID_CFG 43
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#define QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG 4
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#define QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG 7
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#define QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG 0
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#define QSPI_IP_SW_MAJOR_VERSION_CFG 2
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#define QSPI_IP_SW_MINOR_VERSION_CFG 0
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#define QSPI_IP_SW_PATCH_VERSION_CFG 0
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/*==================================================================================================
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* FILE VERSION CHECKS
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==================================================================================================*/
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/*==================================================================================================
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DEFINES AND MACROS
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==================================================================================================*/
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/* Number of serial flash devices */
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#define QSPI_IP_MEM_INSTANCE_COUNT (1U)
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/* Maximum number of retries for Write Enable command */
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#define QSPI_IP_MAX_RETRY (3U)
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/* Development error detection for QSPI Ip API */
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#define QSPI_IP_DEV_ERROR_DETECT (STD_OFF)
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/* Timeout for DLL lock sequence */
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#define QSPI_IP_DLL_LOCK_TIMEOUT (10000000U)
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/* Timeout for QSPI command completion */
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#define QSPI_IP_CMD_COMPLETE_TIMEOUT (10000000U)
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/* After the FRAD checks pass we wait for QSPI to become idle */
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#define QSPI_IP_QSPI_IDLE_TIMEOUT (100U)
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/* Timeout for external flash software reset completion */
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#define QSPI_IP_RESET_TIMEOUT (2000000U)
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/* Timeout for external flash startup initialization sequence completion */
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#define QSPI_IP_FLS_INIT_TIMEOUT (2000000U)
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/* Timeout for a complete read operation */
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#define QSPI_IP_READ_TIMEOUT (2147483647U)
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/* OsIf counter type used in timeout detection for QSPI IP operations */
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#define QSPI_IP_TIMEOUT_TYPE (OSIF_COUNTER_DUMMY)
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/* Delay after changing the value of the QSPI software reset bits */
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#define QSPI_IP_SOFTWARE_RESET_DELAY (21U)
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/*! @brief Minimum delay in CPU cycles between Tx FIFO reset and Tx FIFO push */
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#define QSPI_IP_TX_BUFFER_RESET_DELAY (0U)
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/* QSPI user mode support macro */
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#define QSPI_IP_ENABLE_USER_MODE_SUPPORT (STD_OFF)
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#ifndef MCAL_ENABLE_USER_MODE_SUPPORT
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#if (STD_ON == QSPI_IP_ENABLE_USER_MODE_SUPPORT)
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#error MCAL_ENABLE_USER_MODE_SUPPORT is not enabled. For running Fls in user mode the MCAL_ENABLE_USER_MODE_SUPPORT needs to be defined.
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#endif
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#endif
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#define QSPI_PERFORM_DEVICE_CONFIG (STD_ON)
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/*==================================================================================================
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DEFINES AND MACROS
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==================================================================================================*/
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/*==================================================================================================
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* GLOBAL VARIABLE DECLARATIONS
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==================================================================================================*/
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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#endif /* QSPI_IP_CFG_H */

‎s32/soc/s32z270/include/Qspi_Ip_CfgDefines.h

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QSPI_IP_CFG_DEFINES_H
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#define QSPI_IP_CFG_DEFINES_H
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/**
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* @file Qspi_Ip_CfgDefines.h
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*
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* @addtogroup IPV_QSPI
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* Qspi_Ip_CfgDefines.h_Artifact
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* @{
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*/
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#ifdef __cplusplus
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extern "C"{
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#endif
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/*==================================================================================================
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* INCLUDE FILES
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* 1) system and project includes
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* 2) needed interfaces from external units
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* 3) internal and external interfaces from this unit
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==================================================================================================*/
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/*==================================================================================================
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* SOURCE FILE VERSION INFORMATION
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==================================================================================================*/
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#define QSPI_IP_VENDOR_ID_CFG_DEFINES 43
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#define QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG_DEFINES 4
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#define QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG_DEFINES 7
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#define QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG_DEFINES 0
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#define QSPI_IP_SW_MAJOR_VERSION_CFG_DEFINES 2
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#define QSPI_IP_SW_MINOR_VERSION_CFG_DEFINES 0
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#define QSPI_IP_SW_PATCH_VERSION_CFG_DEFINES 0
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/*==================================================================================================
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* FILE VERSION CHECKS
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==================================================================================================*/
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/*==================================================================================================
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DEFINES AND MACROS
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==================================================================================================*/
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#define QSPI_IP_SFP_ENABLE_GLOBAL (STD_ON)
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#define QSPI_IP_SFP_ENABLE_MDAD (STD_ON)
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#define QSPI_IP_SFP_ENABLE_FRAD (STD_ON)
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/* Enable Multicore support when using MemAcc*/
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#define QSPI_IP_MULTICORE_ENABLED (STD_OFF)
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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#endif /* QSPI_IP_CFG_DEFINES_H */

‎s32/soc/s32z270/include/Qspi_Ip_Features.h

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#if !defined(QSPI_IP_FEATURES_H)
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#define QSPI_IP_FEATURES_H
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/**
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* @file Qspi_Ip_Features.h
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*
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* @addtogroup IPV_QSPI
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* Qspi_Ip_Features.h_Artifact
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* @{
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*/
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#ifdef __cplusplus
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extern "C"{
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#endif
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/*==================================================================================================
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* INCLUDE FILES
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* 1) system and project includes
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* 2) needed interfaces from external units
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* 3) internal and external interfaces from this unit
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==================================================================================================*/
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#include "S32Z2_QUADSPI.h"
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/*==================================================================================================
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* SOURCE FILE VERSION INFORMATION
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==================================================================================================*/
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#define QSPI_IP_FEATURES_VENDOR_ID_CFG 43
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#define QSPI_IP_FEATURES_AR_RELEASE_MAJOR_VERSION_CFG 4
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#define QSPI_IP_FEATURES_AR_RELEASE_MINOR_VERSION_CFG 7
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#define QSPI_IP_FEATURES_AR_RELEASE_REVISION_VERSION_CFG 0
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#define QSPI_IP_FEATURES_SW_MAJOR_VERSION_CFG 2
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#define QSPI_IP_FEATURES_SW_MINOR_VERSION_CFG 0
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#define QSPI_IP_FEATURES_SW_PATCH_VERSION_CFG 0
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/*==================================================================================================
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* DEFINES AND MACROS
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==================================================================================================*/
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/* QuadSPI module features */
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/*! @brief First address of the serial flash device on the AHB bus for QuadSPI instances */
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#define FEATURE_QSPI_AMBA_BASE {0x00000000UL,0x10000000UL}
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/*! @brief Size of AHB buffer. */
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#define FEATURE_QSPI_AHB_BUF_SIZE 1024U
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/*! @brief Size of Tx FIFO. */
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#define FEATURE_QSPI_TX_BUF_SIZE 1024U
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/*! @brief Size of Rx FIFO. */
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#define FEATURE_QSPI_RX_BUF_SIZE 256U
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/*! @brief Number of LUT registers that make up a LUT sequence */
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#define FEATURE_QSPI_LUT_SEQUENCE_SIZE 5U
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/* Minimum entries of 4 bytes fill needed to allow Tx operation to start */
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#define FEATURE_QSPI_TX_MIN_BUF_FILL 1U
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/*! @brief Supports Double Data Rate operation */
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#define FEATURE_QSPI_DDR 1
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/*! @brief QSPI side B is available */
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#define FEATURE_QSPI_HAS_SIDE_B 1
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/*! @brief Configurable Idle Signal Drive */
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#define FEATURE_QSPI_CONFIGURABLE_ISD 1
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/*! @brief Supports addr. config options (column address, word addressable) */
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#define FEATURE_QSPI_ADDR_CFG 1
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/*! @brief Supports byte swap */
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#define FEATURE_QSPI_BYTES_SWAP_ADDR 1
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/*! @brief Supports center-aligned read strobe */
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#define FEATURE_QSPI_CENTER_ALIGNED_READ_STROBE 1
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/*! @brief Supports differential clock */
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#define FEATURE_QSPI_DIFFERENTIAL_CLOCK 1
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/*! @brief Supports internal DQS sampling mode */
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#define FEATURE_QSPI_INTERNAL_DQS 0
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/*! @brief Supports loopback sampling mode */
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#define FEATURE_QSPI_LOOPBACK 1
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/*! @brief Supports DQS loopback sampling mode */
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#define FEATURE_QSPI_LOOPBACK_DQS 0
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/*! @brief Supports external DQS sampling mode */
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#define FEATURE_QSPI_EXTERNAL_DQS 1
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/*! @brief Supports DQS_FA_SEL/DQS_FB_SEL field in MCR register for DQS selection */
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#define FEATURE_QSPI_SELECT_DQS 1
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/*! @brief Supports Dll feature */
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#define FEATURE_QSPI_HAS_DLL 1
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/*! @brief Supports full DLL features (as opposed to bypass mode only) */
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#define FEATURE_QSPI_EXTERNAL_DLL_FULL 1
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/*! @brief Supports DLL reference counter and DLL resolution */
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#define FEATURE_QSPI_DLL_LOOPCONTROL 1
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/*! @brief Supports secure flash protection feature */
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#define FEATURE_QSPI_HAS_SFP 1
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/*! @brief The maximum size of manufacturer & device ID that flash memories can have */
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#define FEATURE_EXFLS_FLASH_MDID_SIZE 10U
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/*! @brief AHB base pointers initializer for all QSPI units */
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#define QuadSPI_AHB_PTRS FEATURE_QSPI_AMBA_BASE
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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#endif /* QSPI_IP_FEATURES_H */

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