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haduongquangmanuargue
haduongquang
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manuargue
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s32: drivers: s32ze: update drivers to RTD 2.0.0
Update headers and baremetal drivers device to NXP S32 RTD 2.0.0 Signed-off-by: Ha Duong Quang <[email protected]>
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‎s32/drivers/s32ze/BaseNXP/header/S32Z2.h

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/*
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* Copyright 1997-2016 Freescale Semiconductor, Inc.
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* Copyright 2016-2023 NXP
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* Copyright 2016-2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*!
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* @file S32Z2.h
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* @version 2.1
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* @date 2023-07-20
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* @version 2.3
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* @date 2024-05-03
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* @brief Peripheral Access Layer for S32Z2
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*
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* This file contains register definitions and macros for easy access to their
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#include "S32Z2_LLC_CSR.h"
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#include "S32Z2_LLC_FSC.h"
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#include "S32Z2_LMEM64.h"
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#include "S32Z2_LPI2C.h"
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#include "S32Z2_LSTCU.h"
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#include "S32Z2_LSTCU_14_15_17_18.h"
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#include "S32Z2_L_VFCCU.h"

‎s32/drivers/s32ze/BaseNXP/header/S32Z2_ACCESS_PROTECTION.h

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/*
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* Copyright 1997-2016 Freescale Semiconductor, Inc.
3-
* Copyright 2016-2023 NXP
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* Copyright 2016-2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*!
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* @file S32Z2_ACCESS_PROTECTION.h
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* @version 2.1
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* @date 2023-07-20
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* @version 2.3
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* @date 2024-05-03
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* @brief Peripheral Access Layer for S32Z2_ACCESS_PROTECTION
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*
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* This file contains register definitions and macros for easy access to their

‎s32/drivers/s32ze/BaseNXP/header/S32Z2_ACE.h

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/*
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* Copyright 1997-2016 Freescale Semiconductor, Inc.
3-
* Copyright 2016-2023 NXP
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* Copyright 2016-2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*!
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* @file S32Z2_ACE.h
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* @version 2.1
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* @date 2023-07-20
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* @version 2.3
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* @date 2024-05-03
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* @brief Peripheral Access Layer for S32Z2_ACE
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*
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* This file contains register definitions and macros for easy access to their

‎s32/drivers/s32ze/BaseNXP/header/S32Z2_ADC.h

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/*
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* Copyright 1997-2016 Freescale Semiconductor, Inc.
3-
* Copyright 2016-2023 NXP
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* Copyright 2016-2024 NXP
44
*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*!
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* @file S32Z2_ADC.h
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* @version 2.1
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* @date 2023-07-20
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* @version 2.3
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* @date 2024-05-03
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* @brief Peripheral Access Layer for S32Z2_ADC
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*
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* This file contains register definitions and macros for easy access to their

‎s32/drivers/s32ze/BaseNXP/header/S32Z2_AES_ACCEL.h

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/*
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* Copyright 1997-2016 Freescale Semiconductor, Inc.
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* Copyright 2016-2023 NXP
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* Copyright 2016-2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*!
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* @file S32Z2_AES_ACCEL.h
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* @version 2.1
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* @date 2023-07-20
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* @version 2.3
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* @date 2024-05-03
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* @brief Peripheral Access Layer for S32Z2_AES_ACCEL
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*
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* This file contains register definitions and macros for easy access to their
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/** AES_ACCEL - Register Layout Typedef */
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typedef struct {
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struct { /* offset: 0x0, array step: 0x1000 */
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struct AES_ACCEL_ACCEL { /* offset: 0x0, array step: 0x1000 */
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__IO uint32_t LEN; /**< LEN, array offset: 0x0, array step: 0x1000 */
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__IO uint32_t AILEN; /**< AAD/IV length, array offset: 0x4, array step: 0x1000 */
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__IO uint32_t CRYPT; /**< CRYPT, array offset: 0x8, array step: 0x1000 */

‎s32/drivers/s32ze/BaseNXP/header/S32Z2_ATP.h

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/*
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* Copyright 1997-2016 Freescale Semiconductor, Inc.
3-
* Copyright 2016-2023 NXP
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* Copyright 2016-2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
66
*/
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/*!
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* @file S32Z2_ATP.h
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* @version 2.1
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* @date 2023-07-20
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* @version 2.3
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* @date 2024-05-03
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* @brief Peripheral Access Layer for S32Z2_ATP
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*
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* This file contains register definitions and macros for easy access to their

‎s32/drivers/s32ze/BaseNXP/header/S32Z2_AXBS.h

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/*
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* Copyright 1997-2016 Freescale Semiconductor, Inc.
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* Copyright 2016-2023 NXP
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* Copyright 2016-2024 NXP
44
*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*!
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* @file S32Z2_AXBS.h
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* @version 2.1
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* @date 2023-07-20
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* @version 2.3
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* @date 2024-05-03
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* @brief Peripheral Access Layer for S32Z2_AXBS
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*
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* This file contains register definitions and macros for easy access to their
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/** AXBS - Register Layout Typedef */
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typedef struct {
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struct { /* offset: 0x0, array step: 0x100 */
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struct AXBS_PORT { /* offset: 0x0, array step: 0x100 */
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__IO uint32_t PRS; /**< Priority Slave Registers, array offset: 0x0, array step: 0x100, irregular array, not all indices are valid */
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uint8_t RESERVED_0[12];
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__IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100, irregular array, not all indices are valid */

‎s32/drivers/s32ze/BaseNXP/header/S32Z2_BOOT.h

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/*
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* Copyright 1997-2016 Freescale Semiconductor, Inc.
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* Copyright 2016-2023 NXP
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* Copyright 2016-2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*!
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* @file S32Z2_Boot.h
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* @version 2.1
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* @date 2023-07-20
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* @version 2.3
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* @date 2024-05-03
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* @brief Peripheral Access Layer for S32Z2_Boot
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*
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* This file contains register definitions and macros for easy access to their

‎s32/drivers/s32ze/BaseNXP/header/S32Z2_CANXL_DSC_CONTROL.h

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/*
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* Copyright 1997-2016 Freescale Semiconductor, Inc.
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* Copyright 2016-2022 NXP
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* Copyright 2016-2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
66
*/
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/*!
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* @file S32Z2_CANXL_DSC_CONTROL.h
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* @version 1.8
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* @date 2022-07-13
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* @version 2.3
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* @date 2024-05-03
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* @brief Peripheral Access Layer for S32Z2_CANXL_DSC_CONTROL
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*
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* This file contains register definitions and macros for easy access to their
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/** CANXL_DSC_CONTROL - Register Layout Typedef */
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typedef struct {
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struct { /* offset: 0x0, array step: 0x20 */
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union { /* offset: 0x0, array step: 0x20 */
78-
__I uint32_t DCSTA; /**< Descriptor Control Status, array offset: 0x0, array step: 0x20 */
79-
} STA;
80-
union { /* offset: 0x4, array step: 0x20 */
81-
__IO uint32_t DCSYSPUSH; /**< Descriptor Control System Push, array offset: 0x4, array step: 0x20 */
82-
} PUSHPOP;
83-
union { /* offset: 0x8, array step: 0x20 */
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__IO uint32_t DCSYSLOCK; /**< Descriptor Control System Lock, array offset: 0x8, array step: 0x20 */
85-
} SYSLOCK;
76+
struct CANXL_DSC_CONTROL_DSCMBCTRLAR { /* offset: 0x0, array step: 0x20 */
77+
__I uint32_t DCSTA; /**< Descriptor Control Status, array offset: 0x0, array step: 0x20 */
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__IO uint32_t DCSYSPUSH; /**< Descriptor Control System Push, array offset: 0x4, array step: 0x20 */
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__IO uint32_t DCSYSLOCK; /**< Descriptor Control System Lock, array offset: 0x8, array step: 0x20 */
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uint8_t RESERVED_0[8];
87-
union { /* offset: 0x14, array step: 0x20 */
88-
__IO uint32_t DCACT; /**< Descriptor Control Activation, array offset: 0x14, array step: 0x20 */
89-
} ACT;
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__IO uint32_t DCACT; /**< Descriptor Control Activation, array offset: 0x14, array step: 0x20 */
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uint8_t RESERVED_1[8];
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} DSCMBCTRLAR[CANXL_DSC_CONTROL_DSCMBCTRLAR_COUNT];
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} CANXL_DSC_CONTROL_Type, *CANXL_DSC_CONTROL_MemMapPtr;

‎s32/drivers/s32ze/BaseNXP/header/S32Z2_CANXL_FILTER_BANK.h

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/*
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* Copyright 1997-2016 Freescale Semiconductor, Inc.
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* Copyright 2016-2022 NXP
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* Copyright 2016-2024 NXP
44
*
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* SPDX-License-Identifier: BSD-3-Clause
66
*/
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/*!
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* @file S32Z2_CANXL_FILTER_BANK.h
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* @version 1.8
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* @date 2022-07-13
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* @version 2.3
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* @date 2024-05-03
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* @brief Peripheral Access Layer for S32Z2_CANXL_FILTER_BANK
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*
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* This file contains register definitions and macros for easy access to their

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