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s32: drivers: s32ze: relocate non-cacheable variables
Relocate uninitialized non-cacheable variables into .nocache (NOLOAD) section defined by Zephyr. Signed-off-by: Tu Nguyen Van <[email protected]>
1 parent 2d95b60 commit 3c1e938

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20 files changed

+751
-735
lines changed

20 files changed

+751
-735
lines changed

‎s32/drivers/s32ze/BaseNXP/include/Compiler.h‎

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -479,7 +479,23 @@ extern "C"{
479479
* definition of functions returning a pointer to a variable.
480480
*/
481481
#define FUNC_P2VAR(rettype, ptrclass, memclass) ptrclass rettype * memclass
482-
482+
483+
/**
484+
* @brief Compiler abstraction for allocating variables to nocache section
485+
*/
486+
#ifdef CONFIG_NOCACHE_MEMORY
487+
#ifdef __ZEPHYR__
488+
#include <zephyr/toolchain.h>
489+
#else
490+
#ifndef STRINGIFY
491+
#define STRINGIFY(x) #x
492+
#endif /* STRINGIFY */
493+
#endif /* __ZEPHYR__ */
494+
#define VAR_SEC_NOCACHE(name) __attribute__((section(".nocache." STRINGIFY(name))))
495+
#else
496+
#define VAR_SEC_NOCACHE(name)
497+
#endif /* CONFIG_NOCACHE_MEMORY */
498+
483499
/*==================================================================================================
484500
* ENUMS
485501
==================================================================================================*/

‎s32/drivers/s32ze/EthSwt_NETC/src/Netc_EthSwt_Ip.c‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -264,25 +264,25 @@ static uint16 Netc_EthSwt_Ip_FdbTableEntryTimeout[FEATURE_NETC_ETHSWT_IP_NUMBER_
264264
#include "EthSwt_43_NETC_MemMap.h"
265265

266266
/* A shadow buffer for the mirroring configuration to be used when the application is reading the active configuration */
267-
static Netc_EthSwt_Ip_SwitchMirrorCfgType MirrorCfgBackup;
267+
VAR_SEC_NOCACHE(MirrorCfgBackup) static Netc_EthSwt_Ip_SwitchMirrorCfgType MirrorCfgBackup;
268268

269269
/* Structure used for filling in the actual command buffer descriptor used in table operations */
270-
static volatile Netc_EthSwt_Ip_CmdBDType CmdBDRConfig[NETC_ETHSWT_IP_CBDR_NUM];
270+
VAR_SEC_NOCACHE(CmdBDRConfig) static volatile Netc_EthSwt_Ip_CmdBDType CmdBDRConfig[NETC_ETHSWT_IP_CBDR_NUM];
271271

272272
/* Key element data for ingress port filter table */
273-
static volatile uint32 Netc_EthSwt_Ip_IPFKeyeData[NETC_ETHSWT_IP_INGRESSPORTFILTERTABLE_KEYE_DATA_LEN];
273+
VAR_SEC_NOCACHE(Netc_EthSwt_Ip_IPFKeyeData) static volatile uint32 Netc_EthSwt_Ip_IPFKeyeData[NETC_ETHSWT_IP_INGRESSPORTFILTERTABLE_KEYE_DATA_LEN];
274274

275275
/* a 128 bytes aligned command ring descriptor buffer */
276-
VAR_ALIGN(static Netc_EthSwt_Ip_NTMPMessageHeaderFormatType SwtcommandRingDescriptor0[NETC_ETHSWT_IP_ACTUAL_CBDR0_LENGTH], NETC_ETHSWT_IP_CBD_ALIGNED_SIZE)
276+
VAR_SEC_NOCACHE(SwtcommandRingDescriptor0) VAR_ALIGN(static Netc_EthSwt_Ip_NTMPMessageHeaderFormatType SwtcommandRingDescriptor0[NETC_ETHSWT_IP_ACTUAL_CBDR0_LENGTH], NETC_ETHSWT_IP_CBD_ALIGNED_SIZE)
277277

278278
/* a 16 bytes aligned FDB table request data buffer */
279-
VAR_ALIGN(static volatile Netc_EthSwt_Ip_SwitchTableDataType TableDataBuffer, NETC_ETHSWT_IP_TABLE_ALIGNED_SIZE)
279+
VAR_SEC_NOCACHE(TableDataBuffer) VAR_ALIGN(static volatile Netc_EthSwt_Ip_SwitchTableDataType TableDataBuffer, NETC_ETHSWT_IP_TABLE_ALIGNED_SIZE)
280280

281281
/* a 16 bytes aligned request header table data buffer */
282-
VAR_ALIGN(static Netc_EthSwt_Ip_ReqHeaderTableOperationDataType Netc_EthSwt_Ip_OperationData, NETC_ETHSWT_IP_TABLE_ALIGNED_SIZE)
282+
VAR_SEC_NOCACHE(Netc_EthSwt_Ip_OperationData) VAR_ALIGN(static Netc_EthSwt_Ip_ReqHeaderTableOperationDataType Netc_EthSwt_Ip_OperationData, NETC_ETHSWT_IP_TABLE_ALIGNED_SIZE)
283283

284284
/* Local copy of the pointer to the configuration data. */
285-
static const Netc_EthSwt_Ip_ConfigType * Netc_EthSwt_Ip_ConfigPtr[FEATURE_NETC_ETHSWT_IP_NUMBER_OF_SWTS];
285+
VAR_SEC_NOCACHE(Netc_EthSwt_Ip_ConfigPtr) static const Netc_EthSwt_Ip_ConfigType * Netc_EthSwt_Ip_ConfigPtr[FEATURE_NETC_ETHSWT_IP_NUMBER_OF_SWTS];
286286

287287
#define ETHSWT_43_NETC_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
288288
#include "EthSwt_43_NETC_MemMap.h"

‎s32/drivers/s32ze/Eth_NETC/src/Netc_Eth_Ip.c‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -174,7 +174,7 @@ static boolean Netc_Eth_Ip_TGSAdminListRegistered;
174174
#if (NETC_ETH_IP_MAX_NUMBER_OF_MULTICAST_MAC_HASH_FILTER_ENTRIES > 0)
175175
#define ETH_43_NETC_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
176176
#include "Eth_43_NETC_MemMap.h"
177-
extern Netc_Eth_Ip_MACFilterHashTableEntryType *MACFilterHashTableAddrs[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
177+
VAR_SEC_NOCACHE(MACFilterHashTableAddrs) extern Netc_Eth_Ip_MACFilterHashTableEntryType *MACFilterHashTableAddrs[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
178178

179179
#define ETH_43_NETC_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
180180
#include "Eth_43_NETC_MemMap.h"
@@ -234,45 +234,45 @@ extern volatile Netc_Eth_Ip_RxTimestampInfoType Netc_Eth_Ip_RxTimestampInfoBuff[
234234
#if defined(NETC_ETH_IP_FILL_LEVEL_API_ENABLE)
235235
#if (STD_ON == NETC_ETH_IP_FILL_LEVEL_API_ENABLE)
236236
/** @brief Structures used to measure the usage of the FIFOs*/
237-
volatile uint16 Netc_Eth_Ip_RxFifo_MaxNumberOfUsedBuff[FEATURE_NETC_ETH_NUMBER_OF_CTRLS][NETC_ETH_IP_MAX_NUMBER_OF_RXRINGS];
238-
volatile Netc_Eth_Ip_FillLevelInfo Netc_Eth_Ip_Tx_FillLevelInfo[FEATURE_NETC_ETH_NUMBER_OF_CTRLS][NETC_ETH_IP_MAX_NUMBER_OF_TXRINGS];
237+
VAR_SEC_NOCACHE(Netc_Eth_Ip_RxFifo_MaxNumberOfUsedBuff) volatile uint16 Netc_Eth_Ip_RxFifo_MaxNumberOfUsedBuff[FEATURE_NETC_ETH_NUMBER_OF_CTRLS][NETC_ETH_IP_MAX_NUMBER_OF_RXRINGS];
238+
VAR_SEC_NOCACHE(Netc_Eth_Ip_Tx_FillLevelInfo) volatile Netc_Eth_Ip_FillLevelInfo Netc_Eth_Ip_Tx_FillLevelInfo[FEATURE_NETC_ETH_NUMBER_OF_CTRLS][NETC_ETH_IP_MAX_NUMBER_OF_TXRINGS];
239239
#endif /* STD_ON == NETC_ETH_IP_FILL_LEVEL_API_ENABLE */
240240
#endif /* defined(NETC_ETH_IP_FILL_LEVEL_API_ENABLE) */
241241

242242

243243
/** @brief Pointers to NETC internal driver state for each controller(SI). */
244-
Netc_Eth_Ip_StateType *Netc_Eth_Ip_apxState[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
244+
VAR_SEC_NOCACHE(Netc_Eth_Ip_apxState) Netc_Eth_Ip_StateType *Netc_Eth_Ip_apxState[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
245245

246246
/** @brief List of Error Reporting structures that aggregate information for each Pcie function in case of an error reported to the Event Collector. EMDIO, TIMER, SWITCH, ENETC, PSI0, VSI1-7*/
247-
static volatile Netc_Eth_Ip_PcieFunctionErrorsReported Netc_Eth_Ip_ErrorStatus[FEATURE_NETC_NUMBER_OF_FUNC + FEATURE_NETC_ETH_NUM_OF_VIRTUAL_CTRLS];
247+
VAR_SEC_NOCACHE(Netc_Eth_Ip_ErrorStatus) static volatile Netc_Eth_Ip_PcieFunctionErrorsReported Netc_Eth_Ip_ErrorStatus[FEATURE_NETC_NUMBER_OF_FUNC + FEATURE_NETC_ETH_NUM_OF_VIRTUAL_CTRLS];
248248

249249
/* Enabled status for Time Aware Shaper for PSI */
250-
static boolean Netc_Eth_Ip_PortTimeAwareShaperEnabled = FALSE;
250+
VAR_SEC_NOCACHE(Netc_Eth_Ip_PortTimeAwareShaperEnabled) static boolean Netc_Eth_Ip_PortTimeAwareShaperEnabled = FALSE;
251251

252252
/* Table entries for Time Aware Shaping configuration */
253-
static Netc_Eth_Ip_TimeGateSchedulingEntryDataType Netc_Eth_Ip_EthTimeGateSchedulingEntryData;
253+
VAR_SEC_NOCACHE(Netc_Eth_Ip_EthTimeGateSchedulingEntryData) static Netc_Eth_Ip_TimeGateSchedulingEntryDataType Netc_Eth_Ip_EthTimeGateSchedulingEntryData;
254254

255255
/* The frequency of the NETC module for computing CBS parameters */
256-
static uint32 Netc_Eth_Ip_NetcClockFrequency = 0U;
256+
VAR_SEC_NOCACHE(Netc_Eth_Ip_NetcClockFrequency) static uint32 Netc_Eth_Ip_NetcClockFrequency = 0U;
257257

258258
/* a 16 bytes aligned table request data buffer */
259-
VAR_ALIGN(static volatile Netc_Eth_Ip_EnetcTableDataType Netc_Eth_Ip_EnetcTableDataBuffer, NETC_ETH_IP_TABLE_ALIGNED_SIZE)
260-
static VAR_ALIGN(Netc_Eth_Ip_ReqHeaderTableOperationDataType Netc_Eth_Ip_OperationData, NETC_ETH_IP_TABLE_ALIGNED_SIZE)
259+
VAR_SEC_NOCACHE(Netc_Eth_Ip_EnetcTableDataBuffer) VAR_ALIGN(static volatile Netc_Eth_Ip_EnetcTableDataType Netc_Eth_Ip_EnetcTableDataBuffer, NETC_ETH_IP_TABLE_ALIGNED_SIZE)
260+
VAR_SEC_NOCACHE(Netc_Eth_Ip_OperationData) static VAR_ALIGN(Netc_Eth_Ip_ReqHeaderTableOperationDataType Netc_Eth_Ip_OperationData, NETC_ETH_IP_TABLE_ALIGNED_SIZE)
261261

262-
static VAR_ALIGN(Netc_Eth_Ip_SetMessageHeaderTableOperationDataType Netc_Eth_Ip_TableData, NETC_ETH_IP_TABLE_ALIGNED_SIZE)
262+
VAR_SEC_NOCACHE(Netc_Eth_Ip_TableData) static VAR_ALIGN(Netc_Eth_Ip_SetMessageHeaderTableOperationDataType Netc_Eth_Ip_TableData, NETC_ETH_IP_TABLE_ALIGNED_SIZE)
263263

264264
/* Local copy of the pointer to the configuration data. */
265-
static const Netc_Eth_Ip_ConfigType * Netc_Eth_Ip_ConfigPtr[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
265+
VAR_SEC_NOCACHE(Netc_Eth_Ip_ConfigPtr) static const Netc_Eth_Ip_ConfigType * Netc_Eth_Ip_ConfigPtr[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
266266

267267
#define ETH_43_NETC_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
268268
#include "Eth_43_NETC_MemMap.h"
269269

270270
#define ETH_43_NETC_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
271271
#include "Eth_43_NETC_MemMap.h"
272272

273-
static VAR_ALIGN(uint32 Netc_Eth_Ip_RfsSetDataBuffer[NETC_ETH_RFS_ENTRY_SET_DATA_BUFFER_SIZE], NETC_ETH_IP_TABLE_ALIGNED_SIZE)
273+
VAR_SEC_NOCACHE(Netc_Eth_Ip_RfsSetDataBuffer) static VAR_ALIGN(uint32 Netc_Eth_Ip_RfsSetDataBuffer[NETC_ETH_RFS_ENTRY_SET_DATA_BUFFER_SIZE], NETC_ETH_IP_TABLE_ALIGNED_SIZE)
274274
/* Key element data for ingress port filter table */
275-
static volatile VAR_ALIGN(uint32 Netc_Eth_Ip_IPFKeyeData[NETC_ETH_IP_INGRESSPORTFILTERTABLE_KEYE_DATA_LEN], NETC_ETH_IP_TABLE_ALIGNED_SIZE)
275+
VAR_SEC_NOCACHE(Netc_Eth_Ip_IPFKeyeData) static volatile VAR_ALIGN(uint32 Netc_Eth_Ip_IPFKeyeData[NETC_ETH_IP_INGRESSPORTFILTERTABLE_KEYE_DATA_LEN], NETC_ETH_IP_TABLE_ALIGNED_SIZE)
276276

277277
#define ETH_43_NETC_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
278278
#include "Eth_43_NETC_MemMap.h"

‎s32/drivers/s32ze/Mcl/include/Emios_Mcl_Ip.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,7 @@ extern "C"{
9595
/*==================================================================================================
9696
* CONSTANTS
9797
==================================================================================================*/
98-
extern eMIOS_Type* Emios_Ip_paxBase[eMIOS_INSTANCE_COUNT];
98+
extern eMIOS_Type *const Emios_Ip_paxBase[eMIOS_INSTANCE_COUNT];
9999

100100
/*==================================================================================================
101101
* DEFINES AND MACROS

‎s32/drivers/s32ze/Mcl/src/Emios_Mcl_Ip.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,7 @@ extern "C"{
7676
#define MCL_START_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE
7777
#include "Mcl_MemMap.h"
7878

79-
eMIOS_Type* Emios_Ip_paxBase[eMIOS_INSTANCE_COUNT] = IP_eMIOS_BASE_PTRS;
79+
eMIOS_Type *const Emios_Ip_paxBase[eMIOS_INSTANCE_COUNT] = IP_eMIOS_BASE_PTRS;
8080

8181
#define MCL_STOP_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE
8282
#include "Mcl_MemMap.h"
@@ -99,7 +99,7 @@ eMIOS_Type* Emios_Ip_paxBase[eMIOS_INSTANCE_COUNT] = IP_eMIOS_BASE_PTRS;
9999
#define MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
100100
#include "Mcl_MemMap.h"
101101

102-
static Emios_Ip_InstStateType Emios_Ip_axIpIsInitialized[eMIOS_INSTANCE_COUNT];
102+
VAR_SEC_NOCACHE(Emios_Ip_axIpIsInitialized) static Emios_Ip_InstStateType Emios_Ip_axIpIsInitialized[eMIOS_INSTANCE_COUNT];
103103

104104
#define MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
105105
#include "Mcl_MemMap.h"
@@ -110,7 +110,7 @@ eMIOS_Type* Emios_Ip_paxBase[eMIOS_INSTANCE_COUNT] = IP_eMIOS_BASE_PTRS;
110110
#define MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
111111
#include "Mcl_MemMap.h"
112112

113-
static Emios_Ip_ChStateType Emios_Ip_axChState[eMIOS_INSTANCE_COUNT][eMIOS_CH_UC_UC_COUNT];
113+
VAR_SEC_NOCACHE(Emios_Ip_axChState) static Emios_Ip_ChStateType Emios_Ip_axChState[eMIOS_INSTANCE_COUNT][eMIOS_CH_UC_UC_COUNT];
114114

115115
#define MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
116116
#include "Mcl_MemMap.h"

‎s32/drivers/s32ze/Mem_EXFLS/src/Qspi_Ip.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -145,7 +145,7 @@ extern "C"{
145145
#include "Mem_43_EXFLS_MemMap.h"
146146

147147
/* Pointer to runtime state structures */
148-
Qspi_Ip_StateType Qspi_Ip_MemoryStateStructure[QSPI_IP_MEM_INSTANCE_COUNT];
148+
VAR_SEC_NOCACHE(Qspi_Ip_MemoryStateStructure) Qspi_Ip_StateType Qspi_Ip_MemoryStateStructure[QSPI_IP_MEM_INSTANCE_COUNT];
149149

150150
#if (QSPI_IP_MULTICORE_ENABLED == STD_ON)
151151
#define MEM_43_EXFLS_STOP_SEC_VAR_SHARED_CLEARED_UNSPECIFIED_NO_CACHEABLE

‎s32/drivers/s32ze/Platform/src/Mru_Ip.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -175,9 +175,9 @@ extern "C"
175175
#define PLATFORM_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
176176
#include "Platform_MemMap.h"
177177

178-
Mru_Ip_StateStructureType Mru_Ip_axStateStructure[MRU_IP_NUMBER_OF_INSTANCES];
178+
VAR_SEC_NOCACHE(Mru_Ip_axStateStructure) Mru_Ip_StateStructureType Mru_Ip_axStateStructure[MRU_IP_NUMBER_OF_INSTANCES];
179179

180-
Mru_Ip_StateStructureType* Mru_Ip_apxStateStructureArray[MRU_IP_NUMBER_OF_INSTANCES];
180+
VAR_SEC_NOCACHE(Mru_Ip_apxStateStructureArray) Mru_Ip_StateStructureType* Mru_Ip_apxStateStructureArray[MRU_IP_NUMBER_OF_INSTANCES];
181181

182182
#define PLATFORM_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
183183
#include "Platform_MemMap.h"

‎s32/drivers/s32ze/Rte/src/SchM_Can_43_CANEXCEL.c‎

Lines changed: 42 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -99,48 +99,48 @@ extern "C"{
9999
==================================================================================================*/
100100
#define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
101101
#include "Rte_MemMap.h"
102-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
112-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
113-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
114-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
115-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
116-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
117-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
118-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
119-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
120-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
121-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
122-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
123-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
124-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
125-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
126-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
127-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
128-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
129-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
130-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
131-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
132-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
133-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
134-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
135-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
136-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
137-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
138-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
139-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
140-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
141-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
142-
static volatile uint32 msr_CAN_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
143-
static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
102+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_00) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_01) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_02) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_03) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_04) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
112+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_05) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
113+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
114+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_06) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
115+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
116+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_07) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
117+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_07)static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
118+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_08)static volatile uint32 msr_CAN_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
119+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_08)static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
120+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_09)static volatile uint32 msr_CAN_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
121+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_09)static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
122+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_10)static volatile uint32 msr_CAN_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
123+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_10)static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
124+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_11)static volatile uint32 msr_CAN_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
125+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_11)static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
126+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_12)static volatile uint32 msr_CAN_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
127+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_12)static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
128+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_13)static volatile uint32 msr_CAN_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
129+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_13)static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
130+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_14)static volatile uint32 msr_CAN_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
131+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_14)static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
132+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_15)static volatile uint32 msr_CAN_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
133+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_15)static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
134+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_16)static volatile uint32 msr_CAN_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
135+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_16)static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
136+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_17)static volatile uint32 msr_CAN_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
137+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_17)static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
138+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_18)static volatile uint32 msr_CAN_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
139+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_18)static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
140+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_19)static volatile uint32 msr_CAN_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
141+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_19)static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
142+
VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_20)static volatile uint32 msr_CAN_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
143+
VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_20)static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
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#define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
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#include "Rte_MemMap.h"

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