drivers: irqsteer: adjust CHn_MASK index computation

For IRQ_STEER, lower CHn_MASK register indexes are used
to mask higher interrupt IDs. For instance, in the case
of i.MX8MP, the mapping is as follows:

	CHn_MASK4 => masks interrupts [31:0]
	CHn_MASK3 => masks interrupts [63:32]
	CHn_MASK2 => masks interrupts [95:64]
	CHn_MASK1 => masks interrupts [127:96]
	CHn_MASK0 => masks interrupts [159:128]

The `IRQSTEER_GetRegIndex()` function is used to fetch
the CHn_MASK register index based on a given slice. The term
"slice" is used to refer to an index of a CHn_MASK register in
the set of CHn_MASK registers assigned to a certain master. Assuming
the following partition scheme (i.MX8MP):

	{ CHn_MASK4 } is assigned to MASTER0
	{ CHn_MASK3, CHn_MASK2 } is assigned to MASTER1
	{ CHn_MASK1, CHn_MASK0 } is assiged to MASTER2

CHn_MASK3 would be at slice (index) 0, CHn_MASK2 would be at
slice 1, CHn_MASK1 would be at slice 0 and so on.

To compute the CHn_MASK register index found at a given slice,
`IRQSTEER_GetRegIndex()` uses a base index, which is either
the lowest or the highest CHn_MASK register index in a master's
partition (for instance, for MASTER1 the higher would be 3 and
the lowest would be 2).

For IRQ_STEER instances with an uneven number of CHn_MASK registers
the base is the lowest index, while in the case of instances with
an even number of CHn_MASK registers it's exactly the opposite. This
is an issue because the software using this function might expect
the base to either be the lowest or the highest index ALL THE TIME
(since this affects the order in which the CHn_MASK register indexes
are returned).

As such, fix this problem by making the base the highest CHn_MASK
register index.

Signed-off-by: Laurentiu Mihalcea <[email protected]>

Author: LaurentiuM1234

mcux/mcux-sdk-ng/README

@@ -45,3 +45,4 @@ Patch List:
   - drivers/s3mu/fsl_s3mu.c: rename _BIT macro to avoid collision from util_macro.h in Zephyr
   - drivers/adc12/fsl_adc12.c: add guards to avoid compilation warnings when building
       with SDK clock control driver disabled.
+  - drivers: irqsteer: adjust CHn_MASK index computation

mcux/mcux-sdk-ng/drivers/irqsteer/fsl_irqsteer.c

@@ -171,18 +171,17 @@ uint32_t IRQSTEER_GetMasterIrqCount(IRQSTEER_Type *base, irqsteer_int_master_t i
     return count;
 }
 
-static uint32_t IRQSTEER_GetRegIndex(irqsteer_int_master_t intMasterIndex, uint32_t slice)
+static uint32_t IRQSTEER_GetRegIndex(irqsteer_int_master_t intMasterIndex,
+				     uint32_t slice, uint32_t sliceNum)
 {
     uint32_t base = (uint32_t)FSL_FEATURE_IRQSTEER_CHn_MASK_COUNT - 1u - ((uint32_t)intMasterIndex * 2u);
 
     if (0u != ((uint32_t)FSL_FEATURE_IRQSTEER_CHn_MASK_COUNT % 2u))
     {
-        return base + slice;
-    }
-    else
-    {
-        return base - slice;
+        base += sliceNum - 1;
     }
+
+    return base - slice;
 }
 
 /*!
@@ -231,7 +230,7 @@ IRQn_Type IRQSTEER_GetMasterNextInterrupt(IRQSTEER_Type *base, irqsteer_int_mast
         bitOffset = 0;
 
         /* compute the index of the register to be queried */
-        regIndex = IRQSTEER_GetRegIndex(intMasterIndex, i);
+        regIndex = IRQSTEER_GetRegIndex(intMasterIndex, i, sliceNum + 1);
 
         /* get register's value */
         chanStatus = base->CHn_STATUS[regIndex];
@@ -261,7 +260,7 @@ uint64_t IRQSTEER_GetMasterInterruptsStatus(IRQSTEER_Type *base, irqsteer_int_ma
     sliceNum = IRQSTEER_GetMasterIrqCount(base, intMasterIndex) / 32u - 1u;
 
     for (i = 0; i <= sliceNum; i++) {
-        regIndex = IRQSTEER_GetRegIndex(intMasterIndex, i);
+        regIndex = IRQSTEER_GetRegIndex(intMasterIndex, i, sliceNum + 1);
 
         chanStatus = base->CHn_STATUS[regIndex];