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1 | 1 | /*! *********************************************************************************
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2 |
| -* Copyright 2023-2024 NXP |
| 2 | +* Copyright 2023-2025 NXP |
3 | 3 | * All rights reserved.
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4 | 4 | *
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5 | 5 | * \file Platform specific definitions. This file contains the default values for
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34 | 34 | #endif
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35 | 35 |
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36 | 36 | // TODO Should be moved to platform file
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37 |
| -#if defined(KW45B41Z83_NBU_SERIES) |
| 37 | +#if defined(KW45B41Z83_NBU_SERIES) || \ |
| 38 | + defined(MCXW727C_cm33_core1_SERIES) || \ |
| 39 | + defined(KW43B43ZC7_NBU_SERIES) |
38 | 40 | #define gPhyIrqNo_d (ZIGBEE_INT_IRQn)
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39 |
| -#elif defined(K32W1480_SERIES) || defined(MCXW716C_SERIES) || defined(MCXW716A_SERIES) |
| 41 | +#elif defined(K32W1480_SERIES) || \ |
| 42 | + defined(MCXW716C_SERIES) || defined(MCXW716A_SERIES) || \ |
| 43 | + defined(MCXW727C_cm33_core0_SERIES) |
40 | 44 | #define gPhyIrqNo_d (RF_802_15_4_IRQn)
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41 |
| -#elif defined(MCXW72BD_cm33_core0_SERIES) |
42 |
| - #define gPhyIrqNo_d ((IRQn_Type)53) |
43 |
| -#elif defined(MCXW72BD_cm33_core1_SERIES) |
44 |
| - #define gPhyIrqNo_d ((IRQn_Type)ZIGBEE_INT_IRQn) |
| 45 | +#elif defined(KW43B43ZC7_SERIES) |
| 46 | + #define gPhyIrqNo_d (RF_ZIGBEE_IRQn) |
45 | 47 | #endif
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46 | 48 |
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47 |
| -/* |
48 |
| - The channel number corresponds to the number of all the channels, between 11 to 26. |
49 |
| - It is used in the PhyUpdateTxPowerLimit() function which updates the power limit of |
50 |
| - all the channels in the case a Front-end module is mounted with a power amplifier on |
51 |
| - the narrow band path. |
52 |
| - */ |
53 |
| -#define CHANNEL_NUMBER (16) |
54 |
| - |
55 | 49 | /*
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56 | 50 | * MIN_ENERGY_LEVEL, MAX_ENERGY_LEVEL are parameters used to scale
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57 | 51 | * energy level between values 0x00-0xFF
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153 | 147 | #define gPhyMaxTxPowerLevelInt8_d (63)
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154 | 148 | #endif
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155 | 149 |
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156 |
| -#else /* FFU_CNS_TX_PWR_TABLE_CALIBRATION */ |
157 |
| -#ifndef gPhyDefaultTxPowerLevel_d |
158 |
| -#define gPhyDefaultTxPowerLevel_d (22) |
159 |
| -#endif |
160 |
| - |
161 |
| -#ifndef gPhyMaxTxPowerLevel_d |
162 |
| -#define gPhyMaxTxPowerLevel_d (32) |
163 |
| -#endif |
164 |
| -#endif /* FFU_CNS_TX_PWR_TABLE_CALIBRATION */ |
165 |
| - |
166 | 150 | /* Tx Power level limit for each individual channel */
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167 | 151 | #ifndef gChannelTxPowerLimit_c
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168 | 152 | #define gChannelTxPowerLimit_c { gPhyMaxTxPowerLevel_d, /* 11 */ \
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183 | 167 | gPhyMaxTxPowerLevel_d } /* 26 */
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184 | 168 | #endif
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185 | 169 |
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| 170 | +#else /* FFU_CNS_TX_PWR_TABLE_CALIBRATION */ |
| 171 | + |
| 172 | +/* |
| 173 | + * Following defines are used when Tx Power is in dBm (signed value) |
| 174 | + * |
| 175 | + * the output TX Power is depending on PA_PWR settings, Analog settings and temperature |
| 176 | + * |
| 177 | + * there are defined 3 sets of defines all of them for 25 C: |
| 178 | + * - low rf output power = analog setting LDO_ANT_TRIM is at minimum voltage |
| 179 | + * - medium rf output power = analog setting LDO_ANT_TRIM is at medium voltage |
| 180 | + * - high rf output power = analog setting LDO_ANT_TRIM is at highiest voltage |
| 181 | + */ |
| 182 | +#ifndef gPhyMinTxPower_low_rf_dBm_Int8_d |
| 183 | +#define gPhyMinTxPower_low_rf_dBm_Int8_d (-32) // dBm |
| 184 | +#endif |
| 185 | + |
| 186 | +#ifndef gPhyMaxTxPower_low_rf_dBm_Int8_d |
| 187 | +#define gPhyMaxTxPower_low_rf_dBm_Int8_d (+1) // dBm |
| 188 | +#endif |
| 189 | + |
| 190 | +#ifndef gPhyMinTxPower_medium_rf_dBm_Int8_d |
| 191 | +#define gPhyMinTxPower_medium_rf_dBm_Int8_d (-24) // dBm |
| 192 | +#endif |
| 193 | + |
| 194 | +#ifndef gPhyMaxTxPower_medium_rf_dBm_Int8_d |
| 195 | +#define gPhyMaxTxPower_medium_rf_dBm_Int8_d (+8) // dBm |
| 196 | +#endif |
| 197 | + |
| 198 | +#ifndef gPhyMinTxPower_high_rf_dBm_Int8_d |
| 199 | +#define gPhyMinTxPower_high_rf_dBm_Int8_d (-22) // dBm |
| 200 | +#endif |
| 201 | + |
| 202 | +#ifndef gPhyMaxTxPower_high_rf_dBm_Int8_d |
| 203 | +#define gPhyMaxTxPower_high_rf_dBm_Int8_d (+10) // dBm |
| 204 | +#endif |
| 205 | + |
| 206 | +/* |
| 207 | + * Following defines are used when Tx Power is in number of PA slices (unsigned value) |
| 208 | + * PA slices are used for PA_PWR register settings according with datasheet |
| 209 | + * |
| 210 | + * Note: Odd & Even values |
| 211 | + * In Ref manual/datasheet are listed mostly even values: 0,1,2,4,6,8,...,62. |
| 212 | + * However despite all values odd and even are valid and should be legal, |
| 213 | + * will prefer and try to use only even values except 1. |
| 214 | + */ |
| 215 | +#ifndef gPhyMinTxPowerLevel_d |
| 216 | +#define gPhyMinTxPowerLevel_d (0x00) // PA slice 0, minimum no output power |
| 217 | +#endif |
| 218 | + |
| 219 | +#ifndef gPhyMaxTxPowerLevel_d |
| 220 | +#define gPhyMaxTxPowerLevel_d (0x3F) // PA slice 63, maximum output power |
| 221 | +#endif |
| 222 | + |
| 223 | +/* |
| 224 | + * Default values |
| 225 | + */ |
| 226 | +#ifndef gPhyDefaultTxPower_dBm_Int8_d |
| 227 | +#define gPhyDefaultTxPower_dBm_Int8_d (0) // set default tx power to 0 dBm (signed value) |
| 228 | +#endif |
| 229 | + |
| 230 | +#ifndef gPhyDefaultTxPowerLevel_d |
| 231 | +#define gPhyDefaultTxPowerLevel_d (gPhyDefaultTxPower_dBm_Int8_d) |
| 232 | +#endif |
| 233 | + |
| 234 | +#ifndef gPhyMaxTxPowerLimit_dBm_Int8_d |
| 235 | +#ifdef gAppMaxTxPowerDbm_c |
| 236 | +#define gPhyMaxTxPowerLimit_dBm_Int8_d (gAppMaxTxPowerDbm_c) // dBm (signed value) |
| 237 | +#else |
| 238 | +#define gPhyMaxTxPowerLimit_dBm_Int8_d (10) // dBm (signed value) |
| 239 | +#endif /* gAppMaxTxPowerDbm_c */ |
| 240 | +#endif |
| 241 | + |
| 242 | +/* Tx Power level limit for each individual channel */ |
| 243 | +#ifndef gChannelTxPowerLimit_c |
| 244 | +#define gChannelTxPowerLimit_c { gPhyMaxTxPowerLimit_dBm_Int8_d, /* 11 */ \ |
| 245 | + gPhyMaxTxPowerLimit_dBm_Int8_d, /* 12 */ \ |
| 246 | + gPhyMaxTxPowerLimit_dBm_Int8_d, /* 13 */ \ |
| 247 | + gPhyMaxTxPowerLimit_dBm_Int8_d, /* 14 */ \ |
| 248 | + gPhyMaxTxPowerLimit_dBm_Int8_d, /* 15 */ \ |
| 249 | + gPhyMaxTxPowerLimit_dBm_Int8_d, /* 16 */ \ |
| 250 | + gPhyMaxTxPowerLimit_dBm_Int8_d, /* 17 */ \ |
| 251 | + gPhyMaxTxPowerLimit_dBm_Int8_d, /* 18 */ \ |
| 252 | + gPhyMaxTxPowerLimit_dBm_Int8_d, /* 19 */ \ |
| 253 | + gPhyMaxTxPowerLimit_dBm_Int8_d, /* 20 */ \ |
| 254 | + gPhyMaxTxPowerLimit_dBm_Int8_d, /* 21 */ \ |
| 255 | + gPhyMaxTxPowerLimit_dBm_Int8_d, /* 22 */ \ |
| 256 | + gPhyMaxTxPowerLimit_dBm_Int8_d, /* 23 */ \ |
| 257 | + gPhyMaxTxPowerLimit_dBm_Int8_d, /* 24 */ \ |
| 258 | + gPhyMaxTxPowerLimit_dBm_Int8_d, /* 25 */ \ |
| 259 | + gPhyMaxTxPowerLimit_dBm_Int8_d } /* 26 */ |
| 260 | +#endif |
| 261 | + |
| 262 | +#endif /* FFU_CNS_TX_PWR_TABLE_CALIBRATION */ |
| 263 | + |
186 | 264 | #ifndef mPhyOverhead_d
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187 | 265 | #define mPhyOverhead_d (10) /* [sym] */
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188 | 266 | #endif
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214 | 292 | #define FE_POWER_AMPLIFIER_ENABLE 0
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215 | 293 | #endif
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216 | 294 |
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| 295 | +/* External maximum internal power level Front End Module acceptable (dBm) */ |
| 296 | +#ifndef FEM_INPUT_MAX_GAIN |
| 297 | +#define FEM_INPUT_MAX_GAIN 0 |
| 298 | +#endif |
| 299 | + |
217 | 300 | /* External Front End module Power Amplifier gain (dB) */
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218 | 301 | #ifndef FE_POWER_AMPLIFIER_GAIN
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219 | 302 | #define FE_POWER_AMPLIFIER_GAIN 0
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220 | 303 | #endif
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221 | 304 |
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222 | 305 | /* External Front End module LNA (Low Noise Attenuator) enable */
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223 |
| -#ifndef FE_LNA_ENABLE |
224 |
| -#define FE_LNA_ENABLE 0 |
| 306 | +#ifndef FEM_LNA_ENABLE |
| 307 | +#define FEM_LNA_ENABLE 0 |
225 | 308 | #endif
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226 | 309 |
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227 | 310 | /* External Front End module LNA (Low Noise Attenuator) gain (dB) */
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228 |
| -#ifndef FE_LNA_GAIN |
229 |
| -#define FE_LNA_GAIN 0 |
| 311 | +#ifndef FEM_LNA_GAIN |
| 312 | +#define FEM_LNA_GAIN 0 |
230 | 313 | #endif
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231 | 314 |
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232 | 315 |
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