Skip to content

Commit 6b1cfed

Browse files
ZhaoQiang-b45475ZhaoQiang-b45475
committed
mcux-sdk-ng: sar_adc: update sar_adc driver
Update sar_adc driver Signed-off-by: Qiang Zhao <[email protected]>
1 parent 771f23e commit 6b1cfed

File tree

2 files changed

+457
-44
lines changed

2 files changed

+457
-44
lines changed

‎mcux/mcux-sdk-ng/drivers/sar_adc/fsl_sar_adc.c

Lines changed: 215 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,5 @@
11
/*
2-
* Copyright 2023-2024 NXP
3-
* All rights reserved.
2+
* Copyright 2023-2025 NXP
43
*
54
* SPDX-License-Identifier: BSD-3-Clause
65
*/
@@ -30,6 +29,8 @@ static ADC_Type *s_adcBases[] = ADC_BASE_PTRS;
3029
static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS;
3130
#endif /* !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) */
3231

32+
static adc_clock_frequency_t adcClockFreq;
33+
3334
/*******************************************************************************
3435
* Code
3536
******************************************************************************/
@@ -73,17 +74,46 @@ void ADC_GetDefaultConfig(adc_config_t *config)
7374
/* Initializes the configure structure to zero. */
7475
(void)memset(config, 0, sizeof(*config));
7576

76-
config->enableAutoClockOff = false;
77-
config->enableOverWrite = true;
78-
config->enableConvertPresampleVal = false;
79-
config->clockFrequency = kADC_FullBusFrequency;
80-
config->convDataAlign = kADC_ConvDataRightAlign;
81-
config->dmaRequestClearSrc = kADC_DMARequestClearByAck;
77+
config->enableAutoClockOff = false;
78+
config->enableOverWrite = true;
79+
config->enableConvertPresampleVal = false;
80+
#if defined(FSL_FEATURE_ADC_HAS_MCR_XSTARTEN) && (FSL_FEATURE_ADC_HAS_MCR_XSTARTEN==1U)
81+
config->enableAuxiliaryTrig = false;
82+
#endif /* FSL_FEATURE_ADC_HAS_MCR_XSTARTEN */
83+
84+
#if defined(FSL_FEATURE_ADC_HAS_AMSIO) && (FSL_FEATURE_ADC_HAS_AMSIO==1U)
85+
config->speedMode = kADC_SpeedModeNormal;
86+
#endif /* FSL_FEATURE_ADC_HAS_AMSIO */
87+
#if defined(FSL_FEATURE_ADC_HAS_DSDR) && (FSL_FEATURE_ADC_HAS_DSDR==1U)
88+
config->convDelay = 0x00U;
89+
#endif /* FSL_FEATURE_ADC_HAS_DSDR */
90+
#if defined(FSL_FEATURE_ADC_HAS_BCTUMODE) && (FSL_FEATURE_ADC_HAS_BCTUMODE==1U)
91+
config->bctuMode = kADC_BctuModeDisable;
92+
#endif /* FSL_FEATURE_ADC_HAS_BCTUMODE */
93+
#if (defined(FSL_FEATURE_ADC_HAS_CALBISTREG) && (FSL_FEATURE_ADC_HAS_CALBISTREG==1U))
94+
config->convRes = kADC_ConvRes14Bit;
95+
#endif /* FSL_FEATURE_ADC_HAS_CALBISTREG */
96+
#if defined(FSL_FEATURE_ADC_HAS_MCR_AVGS) && (FSL_FEATURE_ADC_HAS_MCR_AVGS==1U)
97+
config->convAvg = kADC_ConvAvgDisable;
98+
#endif /* FSL_FEATURE_ADC_HAS_MCR_AVGS */
99+
config->extTrig = kADC_ExtTrigDisable;
100+
#if !(defined(FSL_FEATURE_ADC_HAS_MCR_ADCLKSE) && (FSL_FEATURE_ADC_HAS_MCR_ADCLKSE==0U))
101+
config->clockFrequency = kADC_FullBusFrequency;
102+
#endif /* FSL_FEATURE_ADC_HAS_MCR_ADCLKSE */
103+
#if (defined(FSL_FEATURE_ADC_HAS_MCR_ADCLKSEL) && (FSL_FEATURE_ADC_HAS_MCR_ADCLKSEL==1U))
104+
config->clockFrequency = kADC_ModuleClockFreq;
105+
#endif /* FSL_FEATURE_ADC_HAS_MCR_ADCLKSEL */
106+
config->convDataAlign = kADC_ConvDataRightAlign;
107+
config->dmaRequestClearSrc = kADC_DMARequestClearByAck;
82108

83109
for (uint8_t index = 0U; index < (uint8_t)ADC_GROUP_COUNTS; ++index)
84110
{
85111
config->samplePhaseDuration[index] = 0x14U;
112+
#if(ADC_GROUP_COUNTS==2U)
86113
config->presampleVoltageSrc[index] = kADC_PresampleVoltageSrcDVDD;
114+
#else /* ADC_GROUP_COUNTS==3U */
115+
config->presampleVoltageSrc[index] = kADC_PresampleVoltageSrcVREL;
116+
#endif /* ADC_GROUP_COUNTS */
87117
}
88118
}
89119

@@ -102,26 +132,79 @@ void ADC_Init(ADC_Type *base, const adc_config_t *config)
102132
CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]);
103133
#endif /* !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) */
104134

105-
/* 1. Set auto-clock-off, overwrite and conversion data align. */
106-
base->MCR = ((base->MCR & (~(ADC_MCR_ACKO_MASK | ADC_MCR_OWREN_MASK | ADC_MCR_WLSIDE_MASK))) |
107-
(ADC_MCR_ACKO(config->enableAutoClockOff ? 1U : 0U) |
108-
ADC_MCR_OWREN(config->enableOverWrite ? 1U : 0U) | ADC_MCR_WLSIDE(config->convDataAlign)));
109-
110-
/* 2. Set the operating clock. */
135+
base->MCR = ((base->MCR & (~(ADC_MCR_ACKO_MASK | ADC_MCR_OWREN_MASK | ADC_MCR_WLSIDE_MASK
136+
#if defined(FSL_FEATURE_ADC_HAS_EXTERNAL_TRIGGER) && (FSL_FEATURE_ADC_HAS_EXTERNAL_TRIGGER==1U)
137+
| ADC_MCR_TRGEN_MASK | ADC_MCR_EDGE_MASK
138+
#endif /* FSL_FEATURE_ADC_HAS_EXTERNAL_TRIGGER */
139+
#if defined(FSL_FEATURE_ADC_HAS_MCR_XSTARTEN) && (FSL_FEATURE_ADC_HAS_MCR_XSTARTEN==1U)
140+
| ADC_MCR_XSTRTEN_MASK
141+
#endif /* FSL_FEATURE_ADC_HAS_MCR_XSTARTEN */
142+
#if defined(FSL_FEATURE_ADC_HAS_BCTUMODE) && (FSL_FEATURE_ADC_HAS_BCTUMODE==1U)
143+
| ADC_MCR_BCTUEN_MASK | ADC_MCR_BCTU_MODE_MASK
144+
#endif /* FSL_FEATURE_ADC_HAS_BCTUMODE */
145+
#if defined(FSL_FEATURE_ADC_HAS_MCR_AVGS) && (FSL_FEATURE_ADC_HAS_MCR_AVGS==1U)
146+
| ADC_MCR_AVGEN_MASK | ADC_MCR_AVGS_MASK
147+
#endif /* FSL_FEATURE_ADC_HAS_MCR_AVGS */
148+
)))
149+
| (ADC_MCR_ACKO(config->enableAutoClockOff ? 1U : 0U) | ADC_MCR_OWREN(config->enableOverWrite ? 1U : 0U)
150+
| ADC_MCR_WLSIDE(config->convDataAlign)
151+
#if defined(FSL_FEATURE_ADC_HAS_EXTERNAL_TRIGGER) && (FSL_FEATURE_ADC_HAS_EXTERNAL_TRIGGER==1U)
152+
| ADC_MCR_TRGEN(((uint32_t)config->extTrig & 0x2U) >> 1U) | ADC_MCR_EDGE((uint32_t)config->extTrig & 0x1U)
153+
#endif /* FSL_FEATURE_ADC_HAS_EXTERNAL_TRIGGER */
154+
#if defined(FSL_FEATURE_ADC_HAS_MCR_XSTARTEN) && FSL_FEATURE_ADC_HAS_MCR_XSTARTEN==1U
155+
| ADC_MCR_XSTRTEN(config->enableAuxiliaryTrig)
156+
#endif /* FSL_FEATURE_ADC_HAS_MCR_XSTARTEN */
157+
#if defined(FSL_FEATURE_ADC_HAS_BCTUMODE) && (FSL_FEATURE_ADC_HAS_BCTUMODE==1U)
158+
| ADC_MCR_BCTUEN((bool)((uint32_t)config->bctuMode & 0x2U)) | ADC_MCR_BCTU_MODE((bool)((uint32_t)config->bctuMode & 0x1U))
159+
#endif /* FSL_FEATURE_ADC_HAS_BCTUMODE */
160+
#if defined(FSL_FEATURE_ADC_HAS_MCR_AVGS) && (FSL_FEATURE_ADC_HAS_MCR_AVGS==1U)
161+
| ADC_MCR_AVGEN(((uint32_t)config->convAvg & 0x4U) >> 2U) | ADC_MCR_AVGS((uint32_t)config->convAvg & 0x3U)
162+
#endif /* FSL_FEATURE_ADC_HAS_MCR_AVGS */
163+
));
164+
165+
#if defined(FSL_FEATURE_ADC_HAS_AMSIO) && (FSL_FEATURE_ADC_HAS_AMSIO==1U)
166+
ADC_SetAdcSpeedMode(base, config->speedMode);
167+
#endif /* FSL_FEATURE_ADC_HAS_AMSIO */
168+
169+
#if (defined(FSL_FEATURE_ADC_HAS_CALBISTREG) && (FSL_FEATURE_ADC_HAS_CALBISTREG==1U))
170+
base->CALBISTREG = ((base->CALBISTREG & ~ADC_CALBISTREG_RESN_MASK) | ADC_CALBISTREG_RESN(config->convRes));
171+
#endif /* FSL_FEATURE_ADC_HAS_CALBISTREG */
172+
173+
/* Set the operating clock. */
174+
ADC_SetPowerDownMode(base, true);
175+
while (ADC_GetAdcState(base) != kADC_AdcPowerdown);
176+
111177
ADC_SetOperatingClock(base, config->clockFrequency);
178+
adcClockFreq = config->clockFrequency;
179+
__ISB();
180+
181+
ADC_SetPowerDownMode(base, false);
182+
while (ADC_GetAdcState(base) != kADC_AdcIdle);
112183

113-
/* 3. Set DMA transfer. */
184+
/* Set DMA transfer. */
114185
base->DMAE = ((base->DMAE & (~ADC_DMAE_DCLR_MASK)) | ADC_DMAE_DCLR(config->dmaRequestClearSrc));
115186

116-
/* 4. Set group 0 and group 1 sample phase duration. */
187+
/* Set GROUPn sample phase duration. */
117188
base->CTR0 = ((base->CTR0 & (~ADC_CTR0_INPSAMP_MASK)) | ADC_CTR0_INPSAMP(config->samplePhaseDuration[0U]));
118189
base->CTR1 = ((base->CTR1 & (~ADC_CTR1_INPSAMP_MASK)) | ADC_CTR1_INPSAMP(config->samplePhaseDuration[1U]));
190+
#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3)
191+
if(1U == FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3(base))
192+
{
193+
base->CTR2 = ((base->CTR2 & (~ADC_CTR2_INPSAMP_MASK)) | ADC_CTR2_INPSAMP(config->samplePhaseDuration[2U]));
194+
}
195+
#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3 */
119196

120-
/* 5. Set Group 0 and Group 32 pre-sample voltage sources and decide whether to convert the pre-sample value. */
121-
base->PSCR =
122-
((base->PSCR & (~(ADC_PSCR_PREVAL0_MASK | ADC_PSCR_PREVAL1_MASK | ADC_PSCR_PRECONV_MASK))) |
123-
(ADC_PSCR_PREVAL0(config->presampleVoltageSrc[0U]) | ADC_PSCR_PREVAL1(config->presampleVoltageSrc[1U]) |
124-
ADC_PSCR_PRECONV(config->enableConvertPresampleVal ? 1U : 0U)));
197+
/* Set GROUPn pre-sample voltage sources and decide whether to convert the pre-sample value. */
198+
base->PSCR = ((base->PSCR & (~(ADC_PSCR_PREVAL0_MASK | ADC_PSCR_PREVAL1_MASK | ADC_PSCR_PRECONV_MASK)))
199+
| (ADC_PSCR_PREVAL0(config->presampleVoltageSrc[0U]) | ADC_PSCR_PREVAL1(config->presampleVoltageSrc[1U])
200+
| ADC_PSCR_PRECONV(config->enableConvertPresampleVal ? 1U : 0U)));
201+
202+
#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3)
203+
if(1U == FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3(base))
204+
{
205+
base->PSCR = ((base->PSCR & (~ADC_PSCR_PREVAL2_MASK)) | ADC_PSCR_PREVAL1(config->presampleVoltageSrc[2U]));
206+
}
207+
#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3 */
125208
}
126209

127210
/*!
@@ -173,15 +256,22 @@ void ADC_SetConvChainConfig(ADC_Type *base, const adc_chain_config_t *config)
173256
if (chanConf->enableWdg)
174257
{
175258
CWSELR_IO(base,
176-
((GET_REGINDEX(chanConf->channelIndex) * 4U) + (GET_BITINDEX(chanConf->channelIndex) >> 3U))) |=
177-
WDG_SELECT(chanConf->wdgIndex, ((uint32_t)(chanConf->channelIndex) % 8U));
259+
((GET_REGINDEX(chanConf->channelIndex) * 4U) + (GET_BITINDEX(chanConf->channelIndex) >> 3U))) |=
260+
WDG_SELECT(chanConf->wdgIndex, ((uint32_t)(chanConf->channelIndex) % 8U));
178261
}
179262

180263
chanConf += 1U;
181264
}
182265

183266
for (uint8_t index = 0U; index < (uint8_t)ADC_GROUP_COUNTS; ++index)
184267
{
268+
#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3)
269+
if(1U != FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3(base))
270+
{
271+
break;
272+
}
273+
#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3 */
274+
185275
/* 1. Set conversion channel's interrupt.*/
186276
*(((volatile uint32_t *)(&(base->CIMR0))) + index) = convChannelIntMask[index];
187277
/* 2. Set the conversion channel's pre-sample feature.*/
@@ -201,6 +291,12 @@ void ADC_SetConvChainConfig(ADC_Type *base, const adc_chain_config_t *config)
201291
{
202292
for (uint8_t index = 0U; index < (uint8_t)ADC_GROUP_COUNTS; ++index)
203293
{
294+
#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3)
295+
if(1U != FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3(base))
296+
{
297+
break;
298+
}
299+
#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3 */
204300
*(((volatile uint32_t *)(&(base->JCMR0))) + index) = convChannelMask[index];
205301
}
206302

@@ -217,6 +313,12 @@ void ADC_SetConvChainConfig(ADC_Type *base, const adc_chain_config_t *config)
217313
{
218314
for (uint8_t index = 0U; index < (uint8_t)ADC_GROUP_COUNTS; ++index)
219315
{
316+
#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3)
317+
if(1U != FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3(base))
318+
{
319+
break;
320+
}
321+
#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3 */
220322
*(((volatile uint32_t *)(&(base->NCMR0))) + index) = convChannelMask[index];
221323
}
222324

@@ -248,14 +350,18 @@ void ADC_SetAnalogWdgConfig(ADC_Type *base, const adc_wdg_config_t *config)
248350
{
249351
assert(config != NULL);
250352

353+
#if (defined(ADC_THRESHOLD_COUNTS) && (ADC_THRESHOLD_COUNTS==8U))
251354
volatile uint32_t *THRHLR[ADC_THRESHOLD_COUNTS] = {&(base->THRHLR0), &(base->THRHLR1), &(base->THRHLR2),
252355
&(base->THRHLR3), &(base->THRHLR4), &(base->THRHLR5),
253356
&(base->THRHLR6), &(base->THRHLR7)};
357+
#else /* ADC_THRESHOLD_COUNTS=4U */
358+
volatile uint32_t *THRHLR[ADC_THRESHOLD_COUNTS] = {&(base->THRHLR[0]), &(base->THRHLR[1]),
359+
&(base->THRHLR[2]), &(base->THRHLR[3])};
360+
#endif /* ADC_THRESHOLD_COUNTS */
254361

255362
/* Set low/high threshold values for selected channels. */
256-
*(THRHLR[config->wdgIndex]) =
257-
(((*(THRHLR[config->wdgIndex])) & (~(ADC_THRHLR_THRL_MASK | ADC_THRHLR_THRH_MASK))) |
258-
(ADC_THRHLR_THRL(config->lowThresholdVal) | ADC_THRHLR_THRH(config->highThresholdVal)));
363+
*(THRHLR[config->wdgIndex]) = (((*(THRHLR[config->wdgIndex])) & (~(ADC_THRHLR_THRL_MASK | ADC_THRHLR_THRH_MASK))) |
364+
(ADC_THRHLR_THRL(config->lowThresholdVal) | ADC_THRHLR_THRH(config->highThresholdVal)));
259365

260366
/* Enable analog watchdog low/high threshold interrupts. */
261367
ADC_EnableWdgThresholdInt(base, (uint32_t)(((uint32_t)config->wdgThresholdInt) << (2U * (config->wdgIndex))));
@@ -291,25 +397,79 @@ bool ADC_DoCalibration(ADC_Type *base, const adc_calibration_config_t *config)
291397
assert(config != NULL);
292398

293399
bool calibrationStatus = true;
400+
bool clockNeedRecovery = false;
401+
402+
#if (defined(FSL_FEATURE_ADC_HAS_CALBISTREG) && (FSL_FEATURE_ADC_HAS_CALBISTREG==1U))
403+
/* Clear the bits and set to calibration values */
404+
base->CALBISTREG = ((base->CALBISTREG & (~(ADC_CALBISTREG_AVG_EN_MASK |
405+
ADC_CALBISTREG_TSAMP_MASK |
406+
ADC_CALBISTREG_NR_SMPL_MASK))) |
407+
(ADC_CALBISTREG_TSAMP(config->sampleTime) |
408+
ADC_CALBISTREG_NR_SMPL(config->averageSampleNumbers) |
409+
ADC_CALBISTREG_AVG_EN(config->enableAverage ? 1U : 0U)));
410+
411+
#if defined(FSL_FEATURE_ADC_HAS_AMSIO) && (FSL_FEATURE_ADC_HAS_AMSIO==1U)
412+
ADC_SetAdcSpeedMode(base, kADC_SpeedModeNormal);
413+
#endif /* FSL_FEATURE_ADC_HAS_AMSIO */
414+
415+
#if defined(FSL_FEATURE_ADC_HAS_CAL2) && (FSL_FEATURE_ADC_HAS_CAL2==1U)
416+
base->CAL2 &= ~ADC_CAL2_ENX_MASK;
417+
#endif /* FSL_FEATURE_ADC_HAS_CAL2 */
418+
419+
/* Slow down ADC functional clock frequency. */
420+
if(adcClockFreq != kADC_ModuleClockFreqDivide8)
421+
{
422+
ADC_SetPowerDownMode(base, true);
423+
while (ADC_GetAdcState(base) != kADC_AdcPowerdown);
424+
425+
ADC_SetOperatingClock(base, kADC_ModuleClockFreqDivide8);
426+
__ISB();
427+
428+
ADC_SetPowerDownMode(base, false);
429+
while (ADC_GetAdcState(base) != kADC_AdcIdle);
430+
431+
clockNeedRecovery = true;
432+
}
433+
434+
/* Start calibration. */
435+
base->CALBISTREG |= ADC_CALBISTREG_TEST_EN_MASK;
294436

437+
#else
295438
/* Clear the bits and set to calibration values */
296439
base->MCR = ((base->MCR & (~(ADC_MCR_AVGEN_MASK | ADC_MCR_TSAMP_MASK | ADC_MCR_NRSMPL_MASK))) |
297440
(ADC_MCR_AVGEN(config->enableAverage ? 1U : 0U) | ADC_MCR_TSAMP(config->sampleTime) |
298441
ADC_MCR_NRSMPL(config->averageSampleNumbers)));
299442

443+
/* Slow down ADC functional clock frequency. */
444+
if(adcClockFreq != kADC_HalfBusFrequency)
445+
{
446+
ADC_SetPowerDownMode(base, true);
447+
while (ADC_GetAdcState(base) != kADC_AdcPowerdown);
448+
449+
ADC_SetOperatingClock(base, kADC_HalfBusFrequency);
450+
__ISB();
451+
452+
ADC_SetPowerDownMode(base, false);
453+
while (ADC_GetAdcState(base) != kADC_AdcIdle);
454+
455+
clockNeedRecovery = true;
456+
}
457+
300458
/* Start calibration. */
301459
base->MCR |= ADC_MCR_CALSTART_MASK;
460+
#endif /* FSL_FEATURE_ADC_HAS_CALBISTREG */
302461

303462
/* Wait for calibration to finish. */
304463
while (ADC_CheckCalibrationBusy(base))
305464
{
306465
}
466+
307467
/* Check the status of calibration. If calibration failed, check the pass/fail status of each calibration step
308468
* in the CALSTAT register look for failures, if calibration passes, double-check the MSR[CALIBRTD] bitfield.
309469
*/
310470
if (ADC_CheckCalibrationFailed(base))
311471
{
312-
base->MSR = ADC_MSR_CALFAIL_MASK;
472+
ADC_ClearCalibrationFailedFlag(base);
313473
calibrationStatus = false;
314474
}
315475
else
@@ -324,9 +484,23 @@ bool ADC_DoCalibration(ADC_Type *base, const adc_calibration_config_t *config)
324484
}
325485
}
326486

487+
/* ADC functional clock recovery. */
488+
if(clockNeedRecovery)
489+
{
490+
ADC_SetPowerDownMode(base, true);
491+
while (ADC_GetAdcState(base) != kADC_AdcPowerdown);
492+
493+
ADC_SetOperatingClock(base, adcClockFreq);
494+
__ISB();
495+
496+
ADC_SetPowerDownMode(base, false);
497+
while (ADC_GetAdcState(base) != kADC_AdcIdle);
498+
}
499+
327500
return calibrationStatus;
328501
}
329502

503+
#if !(defined(FSL_FEATURE_ADC_HAS_CALSTAT) && (FSL_FEATURE_ADC_HAS_CALSTAT==0U))
330504
/*!
331505
* brief This function is used to get the test result for the last failed test.
332506
*
@@ -347,6 +521,7 @@ void ADC_GetCalibrationLastFailedTestResult(ADC_Type *base, int16_t *result)
347521

348522
*result = (int16_t)tempResult;
349523
}
524+
#endif /* FSL_FEATURE_ADC_HAS_CALSTAT */
350525

351526
/*!
352527
* brief This function is used to configure the user gain and offset.
@@ -358,9 +533,14 @@ void ADC_GetCalibrationLastFailedTestResult(ADC_Type *base, int16_t *result)
358533
void ADC_SetUserOffsetAndGainConfig(ADC_Type *base, const adc_user_offset_gain_config_t *config)
359534
{
360535
assert(config != NULL);
361-
536+
#if !(defined(FSL_FEATURE_ADC_HAS_USROFSGN) && (FSL_FEATURE_ADC_HAS_USROFSGN==0U))
362537
base->USROFSGN = ((base->USROFSGN & (~(ADC_USROFSGN_GAINUSER_MASK | ADC_USROFSGN_OFFSUSER_MASK))) |
363538
(ADC_USROFSGN_OFFSUSER(config->userOffset) | ADC_USROFSGN_GAINUSER(config->userGain)));
539+
#endif /* FSL_FEATURE_ADC_HAS_USROFSGN */
540+
#if defined(FSL_FEATURE_ADC_HAS_OFSGNUSR) && (FSL_FEATURE_ADC_HAS_OFSGNUSR==1U)
541+
base->OFSGNUSR = ((base->OFSGNUSR & (~(ADC_OFSGNUSR_GAIN_USER_MASK | ADC_OFSGNUSR_OFFSET_USER_MASK))) |
542+
(ADC_OFSGNUSR_OFFSET_USER(config->userOffset) | ADC_OFSGNUSR_GAIN_USER(config->userGain)));
543+
#endif /* FSL_FEATURE_ADC_HAS_OFSGNUSR */
364544
}
365545

366546
/*!
@@ -427,8 +607,13 @@ void ADC_SetSelfTestWdgConfig(ADC_Type *base, const adc_self_test_wdg_config_t *
427607
{
428608
assert(config != NULL);
429609

610+
#if(ADC_SELF_TEST_THRESHOLD_COUNTS==6U)
430611
volatile uint32_t *STAWR[ADC_SELF_TEST_THRESHOLD_COUNTS] = {&(base->STAW0R), &(base->STAW1AR), &(base->STAW1BR),
431612
&(base->STAW2R), &(base->STAW4R), &(base->STAW5R)};
613+
#else /* ADC_SELF_TEST_THRESHOLD_COUNTS==5U */
614+
volatile uint32_t *STAWR[ADC_SELF_TEST_THRESHOLD_COUNTS] = {&(base->STAW0R), &(base->STAW1R), &(base->STAW2R),
615+
&(base->STAW4R), &(base->STAW5R)};
616+
#endif /* ADC_SELF_TEST_THRESHOLD_COUNTS */
432617

433618
/* Set low/high threshold values for selected watchdog. */
434619
if (config->wdgThresholdId == kADC_SelfTestWdgThresholdForAlgSStep2)
@@ -513,6 +698,7 @@ bool ADC_GetSelfTestChannelConvData(ADC_Type *base, adc_self_test_conv_result_t
513698
return true;
514699
}
515700

701+
#if !(defined(FSL_FEATURE_ADC_HAS_STDR2) && (FSL_FEATURE_ADC_HAS_STDR2==0U))
516702
/*!
517703
* brief This function is used to get the test channel converted data when algorithm S step 1 executes.
518704
*
@@ -544,3 +730,4 @@ bool ADC_GetSelfTestChannelConvDataForAlgSStep1(ADC_Type *base, adc_self_test_co
544730

545731
return true;
546732
}
733+
#endif /* FSL_FEATURE_ADC_HAS_STDR2 */

0 commit comments

Comments
 (0)