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ZhaoxiangJindecsny
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mcux-sdk-ng/driver: Roll back the cache64 driver version
After updating the hal_nxp driver to SDK 25.03.00 release, the cache64 driver will cause the MCXN947 flash test cases to fail on the zephyr side. Signed-off-by: Zhaoxiang Jin <[email protected]>
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mcux/mcux-sdk-ng/drivers/cache/cache64/fsl_cache.c

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ volatile uint8_t g_cache64MemPhyAliasId = 0U;
5757
******************************************************************************/
5858
#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
5959
/*!
60-
* brief Returns an instance number given peripheral base address.
60+
* brief Returns an instance number given periphearl base address.
6161
*
6262
* param base The peripheral base address.
6363
* return CACHE64_POLSEL instance number starting from 0.
@@ -239,10 +239,10 @@ void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte)
239239
{
240240
if (size_byte > 0UL)
241241
{
242-
uint32_t endAddr = MSDK_REG_SECURE_ADDR(address + size_byte - 0x01U);
242+
uint32_t endAddr = MSDK_REG_NONSECURE_ADDR(address + size_byte - 0x01U);
243243
uint32_t pccReg = 0;
244244
/* Align address to cache line size. */
245-
uint32_t startAddr = MSDK_REG_SECURE_ADDR(address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U));
245+
uint32_t startAddr = MSDK_REG_NONSECURE_ADDR(address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U));
246246
uint32_t instance = CACHE64_GetInstanceByAddr(address);
247247
uint32_t endLim;
248248
CACHE64_CTRL_Type *base;
@@ -256,7 +256,7 @@ void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte)
256256
return;
257257
}
258258
base = s_cache64ctrlBases[instance];
259-
endLim = MSDK_REG_SECURE_ADDR(phyMemBase[instance][g_cache64MemPhyAliasId] + phyMemSize[instance][g_cache64MemPhyAliasId] - 0x01U);
259+
endLim = MSDK_REG_NONSECURE_ADDR(phyMemBase[instance][g_cache64MemPhyAliasId] + phyMemSize[instance][g_cache64MemPhyAliasId] - 0x01U);
260260
endAddr = endAddr > endLim ? endLim : endAddr;
261261

262262
/* Set the invalidate by line command and use the physical address. */
@@ -309,10 +309,10 @@ void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte)
309309
{
310310
if (size_byte > 0UL)
311311
{
312-
uint32_t endAddr = MSDK_REG_SECURE_ADDR(address + size_byte - 0x01U);
312+
uint32_t endAddr = MSDK_REG_NONSECURE_ADDR(address + size_byte - 0x01U);
313313
uint32_t pccReg = 0;
314314
/* Align address to cache line size. */
315-
uint32_t startAddr = MSDK_REG_SECURE_ADDR(address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U));
315+
uint32_t startAddr = MSDK_REG_NONSECURE_ADDR(address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U));
316316
uint32_t instance = CACHE64_GetInstanceByAddr(address);
317317
uint32_t endLim;
318318
CACHE64_CTRL_Type *base;
@@ -326,7 +326,7 @@ void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte)
326326
return;
327327
}
328328
base = s_cache64ctrlBases[instance];
329-
endLim = MSDK_REG_SECURE_ADDR(phyMemBase[instance][g_cache64MemPhyAliasId] + phyMemSize[instance][g_cache64MemPhyAliasId] - 0x01U);
329+
endLim = MSDK_REG_NONSECURE_ADDR(phyMemBase[instance][g_cache64MemPhyAliasId] + phyMemSize[instance][g_cache64MemPhyAliasId] - 0x01U);
330330
endAddr = endAddr > endLim ? endLim : endAddr;
331331

332332
/* Set the push by line command. */
@@ -381,10 +381,10 @@ void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte)
381381
{
382382
if (size_byte > 0UL)
383383
{
384-
uint32_t endAddr = MSDK_REG_SECURE_ADDR(address + size_byte - 0x01U);
384+
uint32_t endAddr = MSDK_REG_NONSECURE_ADDR(address + size_byte - 0x01U);
385385
uint32_t pccReg = 0;
386386
/* Align address to cache line size. */
387-
uint32_t startAddr = MSDK_REG_SECURE_ADDR(address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U));
387+
uint32_t startAddr = MSDK_REG_NONSECURE_ADDR(address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U));
388388
uint32_t instance = CACHE64_GetInstanceByAddr(address);
389389
uint32_t endLim;
390390
CACHE64_CTRL_Type *base;
@@ -398,7 +398,7 @@ void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte)
398398
return;
399399
}
400400
base = s_cache64ctrlBases[instance];
401-
endLim = MSDK_REG_SECURE_ADDR(phyMemBase[instance][g_cache64MemPhyAliasId] + phyMemSize[instance][g_cache64MemPhyAliasId] - 0x01U);
401+
endLim = MSDK_REG_NONSECURE_ADDR(phyMemBase[instance][g_cache64MemPhyAliasId] + phyMemSize[instance][g_cache64MemPhyAliasId] - 0x01U);
402402
endAddr = endAddr > endLim ? endLim : endAddr;
403403

404404
/* Set the push by line command. */

mcux/mcux-sdk-ng/drivers/cache/cache64/fsl_cache.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222
/*! @name Driver version */
2323
/*! @{ */
2424
/*! @brief cache driver version. */
25-
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 9))
25+
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 8))
2626
/*! @} */
2727

2828
/*! @brief cache line size. */
@@ -70,7 +70,7 @@ extern "C" {
7070

7171
#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
7272
/*!
73-
* @brief Returns an instance number given peripheral base address.
73+
* @brief Returns an instance number given periphearl base address.
7474
*
7575
* @param base The peripheral base address.
7676
* @return CACHE64_POLSEL instance number starting from 0.

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