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ZhaoxiangJinZhaoxiangJin
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hal_nxp: Sync 25.06 driver to hal_nxp
Signed-off-by: Zhaoxiang Jin <[email protected]>
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‎mcux/mcux-sdk-ng/drivers/adc12/CMakeLists.txt

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
1-
# Copyright 2024 NXP
1+
# Copyright 2024-2025 NXP
22
#
33
# SPDX-License-Identifier: BSD-3-Clause
44

55
if(CONFIG_MCUX_COMPONENT_driver.adc12)
6-
mcux_component_version(2.0.6)
6+
mcux_component_version(2.0.8)
77

88
mcux_add_source(SOURCES fsl_adc12.c fsl_adc12.h)
99

‎mcux/mcux-sdk-ng/drivers/adc12/fsl_adc12.c

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,6 @@
11
/*
22
* Copyright (c) 2015, Freescale Semiconductor, Inc.
3-
* Copyright 2016-2019, 2021 NXP
4-
* All rights reserved.
3+
* Copyright 2016-2019, 2021, 2024-2025 NXP
54
*
65
* SPDX-License-Identifier: BSD-3-Clause
76
*/
@@ -25,12 +24,12 @@
2524
/*******************************************************************************
2625
* Prototypes
2726
******************************************************************************/
27+
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
2828
/*!
2929
* @brief Get instance number for ADC12 module.
3030
*
3131
* @param base ADC12 peripheral base address
3232
*/
33-
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
3433
static uint32_t ADC12_GetInstance(ADC_Type *base);
3534
#endif
3635

@@ -63,8 +62,8 @@ static status_t ADC12_GetCalibrationStatus(ADC_Type *base);
6362
/*******************************************************************************
6463
* Variables
6564
******************************************************************************/
66-
/*! @brief Pointers to ADC12 bases for each instance. */
6765
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
66+
/*! @brief Pointers to ADC12 bases for each instance. */
6867
static ADC_Type *const s_adc12Bases[] = ADC_BASE_PTRS;
6968
/*! @brief Pointers to ADC12 clocks for each instance. */
7069
static const clock_ip_name_t s_adc12Clocks[] = ADC12_CLOCKS;
@@ -322,10 +321,13 @@ status_t ADC12_DoAutoCalibration(ADC_Type *base)
322321
tmp32 |= (ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(((uint32_t)ADC_SC3_AVGS_MASK >> (uint32_t)ADC_SC3_AVGS_SHIFT)));
323322

324323
/* Trigger calibration and wait until it complete. */
324+
base->SC1[0] &= ~ADC_SC1_COCO_MASK; /* Clear SC1A[COCO] before calibration. */
325+
325326
tmp32 |= ADC_SC3_CAL_MASK;
326327
base->SC3 = tmp32;
327-
while ((uint32_t)kADC12_ChannelConversionCompletedFlag !=
328-
(ADC12_GetChannelStatusFlags(base, 0U) & (uint32_t)kADC12_ChannelConversionCompletedFlag))
328+
__ISB();
329+
330+
while ((base->SC3 & ADC_SC3_CAL_MASK) == ADC_SC3_CAL_MASK)
329331
{
330332
}
331333

‎mcux/mcux-sdk-ng/drivers/adc12/fsl_adc12.h

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,6 @@
11
/*
22
* Copyright (c) 2015, Freescale Semiconductor, Inc.
3-
* Copyright 2016-2021 NXP
4-
* All rights reserved.
3+
* Copyright 2016-2021, 2024-2025 NXP
54
*
65
* SPDX-License-Identifier: BSD-3-Clause
76
*/
@@ -20,7 +19,7 @@
2019
* Definitions
2120
******************************************************************************/
2221
/*! @brief ADC12 driver version */
23-
#define FSL_ADC12_DRIVER_VERSION (MAKE_VERSION(2, 0, 6)) /*!< Version 2.0.6. */
22+
#define FSL_ADC12_DRIVER_VERSION (MAKE_VERSION(2, 0, 8))
2423

2524
/*!
2625
* @brief Channel status flags' mask.

‎mcux/mcux-sdk-ng/drivers/adc_etc/CMakeLists.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
# SPDX-License-Identifier: BSD-3-Clause
44

55
if(CONFIG_MCUX_COMPONENT_driver.adc_etc)
6-
mcux_component_version(2.3.0)
6+
mcux_component_version(2.3.2)
77

88
mcux_add_source(SOURCES fsl_adc_etc.c fsl_adc_etc.h)
99

‎mcux/mcux-sdk-ng/drivers/adc_etc/fsl_adc_etc.c

Lines changed: 20 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 2016, Freescale Semiconductor, Inc.
3-
* Copyright 2016-2021 NXP
3+
* Copyright 2016-2021, 2025 NXP
44
* All rights reserved.
55
*
66
* SPDX-License-Identifier: BSD-3-Clause
@@ -84,34 +84,42 @@ void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)
8484
#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
8585
ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(config->TSC0triggerPriority) |
8686
#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
87-
#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
87+
#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG)
8888
ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(config->TSC1triggerPriority) |
89-
#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
89+
#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG */
9090
ADC_ETC_CTRL_PRE_DIVIDER(config->clockPreDivider) | ADC_ETC_CTRL_TRIG_ENABLE(config->XBARtriggerMask)
9191
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
9292
| ADC_ETC_CTRL_DMA_MODE_SEL(config->dmaMode)
9393
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
9494
;
9595

9696
#if (!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)) || \
97-
(!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG))
97+
(!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG))
9898
if (config->enableTSCBypass)
9999
{
100100
tmp32 |= ADC_ETC_CTRL_TSC_BYPASS_MASK;
101101
}
102+
#else
103+
/* For ADC_ETC without TSC trigger source, CTRL [bit 30] shall be cleared explicitly.
104+
* Otherwise the ADC instance 2 can not work correctly.
105+
*/
106+
#if ((FSL_FEATURE_SOC_ADC_COUNT > 1U) || (FSL_FEATURE_SOC_LPADC_COUNT > 1U))
107+
tmp32 &= ~(1UL << 30UL);
108+
#endif
102109
#endif
110+
103111
#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
104112
if (config->enableTSC0Trigger)
105113
{
106114
tmp32 |= ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK;
107115
}
108116
#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
109-
#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
117+
#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG)
110118
if (config->enableTSC1Trigger)
111119
{
112120
tmp32 |= ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK;
113121
}
114-
#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
122+
#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG */
115123
base->CTRL = tmp32;
116124
}
117125

@@ -154,29 +162,29 @@ void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)
154162
(void)memset(config, 0, sizeof(*config));
155163

156164
#if (!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)) || \
157-
(!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG))
165+
(!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG))
158166
config->enableTSCBypass = true;
159167
#endif
160168

161169
#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
162170
config->enableTSC0Trigger = false;
163171
#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
164172

165-
#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
173+
#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG)
166174
config->enableTSC1Trigger = false;
167-
#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
175+
#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG */
168176

169177
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
170-
config->dmaMode = kADC_ETC_TrigDMAWithLatchedSignal;
178+
config->dmaMode = kADC_ETC_TrigDMAWithPulsedSignal;
171179
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
172180

173181
#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
174182
config->TSC0triggerPriority = 0U;
175183
#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
176184

177-
#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
185+
#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG)
178186
config->TSC1triggerPriority = 0U;
179-
#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
187+
#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG */
180188
config->clockPreDivider = 0U;
181189
config->XBARtriggerMask = 0U;
182190
}

‎mcux/mcux-sdk-ng/drivers/adc_etc/fsl_adc_etc.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 2016, Freescale Semiconductor, Inc.
3-
* Copyright 2016-2021, 2024 NXP
3+
* Copyright 2016-2021, 2024-2025 NXP
44
*
55
* SPDX-License-Identifier: BSD-3-Clause
66
*/
@@ -19,7 +19,7 @@
1919
* Definitions
2020
******************************************************************************/
2121
/*! @brief ADC_ETC driver version */
22-
#define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */
22+
#define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) /*!< Version 2.3.2. */
2323
/*! @brief The mask of status flags cleared by writing 1. */
2424
#define ADC_ETC_DMA_CTRL_TRGn_REQ_MASK 0xFF0000U
2525

‎mcux/mcux-sdk-ng/drivers/afe/CMakeLists.txt

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
1-
# Copyright 2024 NXP
1+
# Copyright 2024-2025 NXP
22
#
33
# SPDX-License-Identifier: BSD-3-Clause
44

55
if(CONFIG_MCUX_COMPONENT_driver.afe)
6-
mcux_component_version(2.0.2)
6+
mcux_component_version(2.0.3)
77

88
mcux_add_source(SOURCES fsl_afe.c fsl_afe.h)
99

‎mcux/mcux-sdk-ng/drivers/afe/fsl_afe.c

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,6 @@
11
/*
22
* Copyright (c) 2015, Freescale Semiconductor, Inc.
3-
* Copyright 2016-2020 NXP
4-
* All rights reserved.
3+
* Copyright 2016-2020, 2025 NXP
54
*
65
* SPDX-License-Identifier: BSD-3-Clause
76
*/
@@ -72,7 +71,7 @@ void AFE_Init(AFE_Type *base, const afe_config_t *config)
7271
regData = base->CR & ~(AFE_CR_STRTUP_CNT_MASK | AFE_CR_RESULT_FORMAT_MASK | AFE_CR_RST_B_MASK | AFE_CR_LPM_EN_MASK);
7372
/* Set new startup time, result format, low power mode value */
7473
regData |= AFE_CR_STRTUP_CNT((uint8_t)config->startupCount) | AFE_CR_RESULT_FORMAT(config->resultFormat) |
75-
AFE_CR_LPM_EN(config->enableLowPower);
74+
AFE_CR_LPM_EN(config->enableLowPower ? 1U : 0U);
7675
/* Write value to CR register */
7776
base->CR = regData;
7877

@@ -171,7 +170,7 @@ void AFE_SetChannelConfig(AFE_Type *base, uint32_t channel, const afe_channel_co
171170
regData &= ~(AFE_CFR_DEC_OSR_MASK | AFE_CFR_HW_TRG_MASK | AFE_CFR_CC_MASK);
172171
/* Set new Decimator OverSampling Ratio, Conversion Mode, Trigger Select value */
173172
regData |= AFE_CFR_DEC_OSR((uint32_t)config->decimatorOversampleRatio) |
174-
AFE_CFR_CC(config->enableContinuousConversion) | AFE_CFR_HW_TRG(config->enableHardwareTrigger);
173+
AFE_CFR_CC(config->enableContinuousConversion ? 1U : 0U) | AFE_CFR_HW_TRG(config->enableHardwareTrigger ? 1U : 0U);
175174

176175
base->CFR[channel] = regData;
177176
}

‎mcux/mcux-sdk-ng/drivers/afe/fsl_afe.h

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,6 @@
11
/*
22
* Copyright (c) 2015, Freescale Semiconductor, Inc.
3-
* Copyright 2016-2020 NXP
4-
* All rights reserved.
3+
* Copyright 2016-2020, 2025 NXP
54
*
65
* SPDX-License-Identifier: BSD-3-Clause
76
*/
@@ -21,7 +20,7 @@
2120

2221
/*! @name Driver version */
2322
/*! @{ */
24-
#define FSL_AFE_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */
23+
#define FSL_AFE_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */
2524
/*! @} */
2625

2726
/*!

‎mcux/mcux-sdk-ng/drivers/anactrl/CMakeLists.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
# SPDX-License-Identifier: BSD-3-Clause
44

55
if(CONFIG_MCUX_COMPONENT_driver.anactrl)
6-
mcux_component_version(2.3.1)
6+
mcux_component_version(2.4.0)
77

88
mcux_add_source(SOURCES fsl_anactrl.h fsl_anactrl.c)
99

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