drivers: usdhc: change the driver to be aarch64 compatible

JiafeiPan · dleach02 · commit a961ce3ba3fa · 2025-05-14T19:36:51.000+01:00
Make the driver to work on Cortex-A Core.

Signed-off-by: Jiafei Pan &lt;Jiafei.Pan@nxp.com&gt;
diff --git a/mcux/mcux-sdk-ng/drivers/usdhc/fsl_usdhc.c b/mcux/mcux-sdk-ng/drivers/usdhc/fsl_usdhc.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2021, 2025 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -1222,11 +1222,11 @@ status_t USDHC_SetADMA1Descriptor(
 
     uint32_t miniEntries, startEntries = 0UL,
                           maxEntries = (admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma1_descriptor_t);
-    usdhc_adma1_descriptor_t *adma1EntryAddress = (usdhc_adma1_descriptor_t *)(uint32_t)(admaTable);
+    usdhc_adma1_descriptor_t *adma1EntryAddress = (usdhc_adma1_descriptor_t *)(uintptr_t)(admaTable);
     uint32_t i, dmaBufferLen = 0UL;
     const uint32_t *data = dataBufferAddr;
 
-    if (((uint32_t)data % USDHC_ADMA1_ADDRESS_ALIGN) != 0UL)
+    if (((uintptr_t)data % USDHC_ADMA1_ADDRESS_ALIGN) != 0UL)
     {
         return kStatus_USDHC_DMADataAddrNotAlign;
     }
@@ -1277,10 +1277,10 @@ status_t USDHC_SetADMA1Descriptor(
 
         adma1EntryAddress[i] = (dmaBufferLen << USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT);
         adma1EntryAddress[i] |= (uint32_t)kUSDHC_Adma1DescriptorTypeSetLength;
-        adma1EntryAddress[i + 1UL] = (uint32_t)(data);
+        adma1EntryAddress[i + 1UL] = (uintptr_t)(data);
         adma1EntryAddress[i + 1UL] |=
             (uint32_t)kUSDHC_Adma1DescriptorTypeTransfer | (uint32_t)kUSDHC_Adma1DescriptorInterrupFlag;
-        data = (uint32_t *)((uint32_t)data + dmaBufferLen);
+        data = (uint32_t *)((uintptr_t)data + dmaBufferLen);
         dataBytes -= dmaBufferLen;
     }
     /* the end of the descriptor */
@@ -1309,11 +1309,11 @@ status_t USDHC_SetADMA2Descriptor(
 
     uint32_t miniEntries, startEntries = 0UL,
                           maxEntries = (admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma2_descriptor_t);
-    usdhc_adma2_descriptor_t *adma2EntryAddress = (usdhc_adma2_descriptor_t *)(uint32_t)(admaTable);
+    usdhc_adma2_descriptor_t *adma2EntryAddress = (usdhc_adma2_descriptor_t *)(uintptr_t)(admaTable);
     uint32_t i, dmaBufferLen = 0UL;
     const uint32_t *data = dataBufferAddr;
 
-    if (((uint32_t)data % USDHC_ADMA2_ADDRESS_ALIGN) != 0UL)
+    if (((uintptr_t)data % USDHC_ADMA2_ADDRESS_ALIGN) != 0UL)
     {
         return kStatus_USDHC_DMADataAddrNotAlign;
     }
@@ -1371,13 +1371,17 @@ status_t USDHC_SetADMA2Descriptor(
         }
 
         /* Each descriptor for ADMA2 is 64-bit in length */
+#if INTPTR_MAX == INT64_MAX
+        adma2EntryAddress[i].address   = (uintptr_t)((dataBytes == 0UL) ? &s_usdhcBootDummy : data);
+#else
         adma2EntryAddress[i].address   = (dataBytes == 0UL) ? &s_usdhcBootDummy : data;
+#endif
         adma2EntryAddress[i].attribute = (dmaBufferLen << USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT);
         adma2EntryAddress[i].attribute |=
             (dataBytes == 0UL) ?
                 0UL :
                 ((uint32_t)kUSDHC_Adma2DescriptorTypeTransfer | (uint32_t)kUSDHC_Adma2DescriptorInterruptFlag);
-        data = (uint32_t *)((uint32_t)data + dmaBufferLen);
+        data = (uint32_t *)((uintptr_t)data + dmaBufferLen);
 
         if (dataBytes != 0UL)
         {
@@ -1420,7 +1424,7 @@ status_t USDHC_SetInternalDmaConfig(USDHC_Type *base,
     assert(dmaConfig != NULL);
     assert(dataAddr != NULL);
     assert((NULL != dmaConfig->admaTable) &&
-           (((USDHC_ADMA_TABLE_ADDRESS_ALIGN - 1U) & (uint32_t)dmaConfig->admaTable) == 0UL));
+           (((USDHC_ADMA_TABLE_ADDRESS_ALIGN - 1U) & (uintptr_t)dmaConfig->admaTable) == 0UL));
 
 #if FSL_FEATURE_USDHC_HAS_EXT_DMA
     /* disable the external DMA if support */
@@ -1430,26 +1434,26 @@ status_t USDHC_SetInternalDmaConfig(USDHC_Type *base,
     if (dmaConfig->dmaMode == kUSDHC_DmaModeSimple)
     {
         /* check DMA data buffer address align or not */
-        if (((uint32_t)dataAddr % USDHC_ADMA2_ADDRESS_ALIGN) != 0UL)
+        if (((uintptr_t)dataAddr % USDHC_ADMA2_ADDRESS_ALIGN) != 0UL)
         {
             return kStatus_USDHC_DMADataAddrNotAlign;
         }
         /* in simple DMA mode if use auto CMD23, address should load to ADMA addr,
              and block count should load to DS_ADDR*/
         if (enAutoCmd23)
         {
-            base->ADMA_SYS_ADDR = USDHC_ADDR_CPU_2_DMA((uint32_t)dataAddr);
+            base->ADMA_SYS_ADDR = USDHC_ADDR_CPU_2_DMA((uintptr_t)dataAddr);
         }
         else
         {
-            base->DS_ADDR = USDHC_ADDR_CPU_2_DMA((uint32_t)dataAddr);
+            base->DS_ADDR = USDHC_ADDR_CPU_2_DMA((uintptr_t)dataAddr);
         }
     }
     else
     {
         /* When use ADMA, disable simple DMA */
         base->DS_ADDR       = 0UL;
-        base->ADMA_SYS_ADDR = USDHC_ADDR_CPU_2_DMA((uint32_t)(dmaConfig->admaTable));
+        base->ADMA_SYS_ADDR = USDHC_ADDR_CPU_2_DMA((uintptr_t)(dmaConfig->admaTable));
     }
 
 #if (defined(FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN) && FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN)
@@ -1485,14 +1489,14 @@ status_t USDHC_SetAdmaTableConfig(USDHC_Type *base,
 {
     assert(NULL != dmaConfig);
     assert((NULL != dmaConfig->admaTable) &&
-           (((USDHC_ADMA_TABLE_ADDRESS_ALIGN - 1U) & (uint32_t)dmaConfig->admaTable) == 0UL));
+           (((USDHC_ADMA_TABLE_ADDRESS_ALIGN - 1U) & (uintptr_t)dmaConfig->admaTable) == 0UL));
     assert(NULL != dataConfig);
 
     status_t error = kStatus_Fail;
     uint32_t bootDummyOffset =
         dataConfig->dataType == (uint32_t)kUSDHC_TransferDataBootcontinous ? sizeof(uint32_t) : 0UL;
-    const uint32_t *data = (const uint32_t *)USDHC_ADDR_CPU_2_DMA((uint32_t)(
-        (uint32_t)((dataConfig->rxData == NULL) ? dataConfig->txData : dataConfig->rxData) + bootDummyOffset));
+    const uint32_t *data = (const uint32_t *)USDHC_ADDR_CPU_2_DMA((uintptr_t)(
+        (uintptr_t)((dataConfig->rxData == NULL) ? dataConfig->txData : dataConfig->rxData) + bootDummyOffset));
     uint32_t blockSize   = dataConfig->blockSize * dataConfig->blockCount - bootDummyOffset;
 
 #if FSL_FEATURE_USDHC_HAS_EXT_DMA
@@ -1605,12 +1609,12 @@ status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig
         if (data->txData != NULL)
         {
             /* clear the DCACHE */
-            DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount));
+            DCACHE_CleanByRange((uintptr_t)data->txData, (data->blockSize) * (data->blockCount));
         }
         else
         {
             /* clear the DCACHE */
-            DCACHE_CleanInvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount));
+            DCACHE_CleanInvalidateByRange((uintptr_t)data->rxData, (data->blockSize) * (data->blockCount));
         }
     }
 #endif
@@ -1926,12 +1930,12 @@ status_t USDHC_TransferNonBlocking(USDHC_Type *base,
         if (data->txData != NULL)
         {
             /* clear the DCACHE */
-            DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount));
+            DCACHE_CleanByRange((uintptr_t)data->txData, (data->blockSize) * (data->blockCount));
         }
         else
         {
             /* clear the DCACHE */
-            DCACHE_CleanInvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount));
+            DCACHE_CleanInvalidateByRange((uintptr_t)data->rxData, (data->blockSize) * (data->blockCount));
         }
     }
 #endif
@@ -2345,7 +2349,7 @@ static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, u
 #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
                 if (handle->data->rxData != NULL)
                 {
-                    DCACHE_InvalidateByRange((uint32_t)(handle->data->rxData),
+                    DCACHE_InvalidateByRange((uintptr_t)(handle->data->rxData),
                                              (handle->data->blockSize) * (handle->data->blockCount));
                 }
 #endif
diff --git a/mcux/mcux-sdk-ng/drivers/usdhc/fsl_usdhc.h b/mcux/mcux-sdk-ng/drivers/usdhc/fsl_usdhc.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2021, 2025 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -587,7 +587,11 @@ typedef uint32_t usdhc_adma1_descriptor_t;
 typedef struct _usdhc_adma2_descriptor
 {
     uint32_t attribute;      /*!< The control and status field. */
+#if INTPTR_MAX == INT64_MAX
+    uint32_t address;        /*!< The address field. */
+#else
     const uint32_t *address; /*!< The address field. */
+#endif
 } usdhc_adma2_descriptor_t;
 
 /*!

Original file line number	Diff line number	Diff line change
`@@ -1,6 +1,6 @@`
`1`	`1`	`/*`
`2`	`2`	`* Copyright (c) 2016, Freescale Semiconductor, Inc.`
`3`		`- * Copyright 2016-2021 NXP`
	`3`	`+ * Copyright 2016-2021, 2025 NXP`
`4`	`4`	`* All rights reserved.`
`5`	`5`	`*`
`6`	`6`	`* SPDX-License-Identifier: BSD-3-Clause`
`@@ -1222,11 +1222,11 @@ status_t USDHC_SetADMA1Descriptor(`
`1222`	`1222`
`1223`	`1223`	`uint32_t miniEntries, startEntries = 0UL,`
`1224`	`1224`	`maxEntries = (admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma1_descriptor_t);`
`1225`		`- usdhc_adma1_descriptor_t adma1EntryAddress = (usdhc_adma1_descriptor_t )(uint32_t)(admaTable);`
	`1225`	`+ usdhc_adma1_descriptor_t adma1EntryAddress = (usdhc_adma1_descriptor_t )(uintptr_t)(admaTable);`
`1226`	`1226`	`uint32_t i, dmaBufferLen = 0UL;`
`1227`	`1227`	`const uint32_t *data = dataBufferAddr;`
`1228`	`1228`
`1229`		`- if (((uint32_t)data % USDHC_ADMA1_ADDRESS_ALIGN) != 0UL)`
	`1229`	`+ if (((uintptr_t)data % USDHC_ADMA1_ADDRESS_ALIGN) != 0UL)`
`1230`	`1230`	`{`
`1231`	`1231`	`return kStatus_USDHC_DMADataAddrNotAlign;`
`1232`	`1232`	`}`
`@@ -1277,10 +1277,10 @@ status_t USDHC_SetADMA1Descriptor(`
`1277`	`1277`
`1278`	`1278`	`adma1EntryAddress[i] = (dmaBufferLen << USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT);`
`1279`	`1279`	`adma1EntryAddress[i] \|= (uint32_t)kUSDHC_Adma1DescriptorTypeSetLength;`
`1280`		`- adma1EntryAddress[i + 1UL] = (uint32_t)(data);`
	`1280`	`+ adma1EntryAddress[i + 1UL] = (uintptr_t)(data);`
`1281`	`1281`	`adma1EntryAddress[i + 1UL] \|=`
`1282`	`1282`	`(uint32_t)kUSDHC_Adma1DescriptorTypeTransfer \| (uint32_t)kUSDHC_Adma1DescriptorInterrupFlag;`
`1283`		`- data = (uint32_t *)((uint32_t)data + dmaBufferLen);`
	`1283`	`+ data = (uint32_t *)((uintptr_t)data + dmaBufferLen);`
`1284`	`1284`	`dataBytes -= dmaBufferLen;`
`1285`	`1285`	`}`
`1286`	`1286`	`/* the end of the descriptor */`
`@@ -1309,11 +1309,11 @@ status_t USDHC_SetADMA2Descriptor(`
`1309`	`1309`
`1310`	`1310`	`uint32_t miniEntries, startEntries = 0UL,`
`1311`	`1311`	`maxEntries = (admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma2_descriptor_t);`
`1312`		`- usdhc_adma2_descriptor_t adma2EntryAddress = (usdhc_adma2_descriptor_t )(uint32_t)(admaTable);`
	`1312`	`+ usdhc_adma2_descriptor_t adma2EntryAddress = (usdhc_adma2_descriptor_t )(uintptr_t)(admaTable);`
`1313`	`1313`	`uint32_t i, dmaBufferLen = 0UL;`
`1314`	`1314`	`const uint32_t *data = dataBufferAddr;`
`1315`	`1315`
`1316`		`- if (((uint32_t)data % USDHC_ADMA2_ADDRESS_ALIGN) != 0UL)`
	`1316`	`+ if (((uintptr_t)data % USDHC_ADMA2_ADDRESS_ALIGN) != 0UL)`
`1317`	`1317`	`{`
`1318`	`1318`	`return kStatus_USDHC_DMADataAddrNotAlign;`
`1319`	`1319`	`}`
`@@ -1371,13 +1371,17 @@ status_t USDHC_SetADMA2Descriptor(`
`1371`	`1371`	`}`
`1372`	`1372`
`1373`	`1373`	`/* Each descriptor for ADMA2 is 64-bit in length */`
	`1374`	`+#if INTPTR_MAX == INT64_MAX`
	`1375`	`+ adma2EntryAddress[i].address = (uintptr_t)((dataBytes == 0UL) ? &s_usdhcBootDummy : data);`
	`1376`	`+#else`
`1374`	`1377`	`adma2EntryAddress[i].address = (dataBytes == 0UL) ? &s_usdhcBootDummy : data;`
	`1378`	`+#endif`
`1375`	`1379`	`adma2EntryAddress[i].attribute = (dmaBufferLen << USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT);`
`1376`	`1380`	`adma2EntryAddress[i].attribute \|=`
`1377`	`1381`	`(dataBytes == 0UL) ?`
`1378`	`1382`	`0UL :`
`1379`	`1383`	`((uint32_t)kUSDHC_Adma2DescriptorTypeTransfer \| (uint32_t)kUSDHC_Adma2DescriptorInterruptFlag);`
`1380`		`- data = (uint32_t *)((uint32_t)data + dmaBufferLen);`
	`1384`	`+ data = (uint32_t *)((uintptr_t)data + dmaBufferLen);`
`1381`	`1385`
`1382`	`1386`	`if (dataBytes != 0UL)`
`1383`	`1387`	`{`
`@@ -1420,7 +1424,7 @@ status_t USDHC_SetInternalDmaConfig(USDHC_Type *base,`
`1420`	`1424`	`assert(dmaConfig != NULL);`
`1421`	`1425`	`assert(dataAddr != NULL);`
`1422`	`1426`	`assert((NULL != dmaConfig->admaTable) &&`
`1423`		`- (((USDHC_ADMA_TABLE_ADDRESS_ALIGN - 1U) & (uint32_t)dmaConfig->admaTable) == 0UL));`
	`1427`	`+ (((USDHC_ADMA_TABLE_ADDRESS_ALIGN - 1U) & (uintptr_t)dmaConfig->admaTable) == 0UL));`
`1424`	`1428`
`1425`	`1429`	`#if FSL_FEATURE_USDHC_HAS_EXT_DMA`
`1426`	`1430`	`/* disable the external DMA if support */`
`@@ -1430,26 +1434,26 @@ status_t USDHC_SetInternalDmaConfig(USDHC_Type *base,`
`1430`	`1434`	`if (dmaConfig->dmaMode == kUSDHC_DmaModeSimple)`
`1431`	`1435`	`{`
`1432`	`1436`	`/* check DMA data buffer address align or not */`
`1433`		`- if (((uint32_t)dataAddr % USDHC_ADMA2_ADDRESS_ALIGN) != 0UL)`
	`1437`	`+ if (((uintptr_t)dataAddr % USDHC_ADMA2_ADDRESS_ALIGN) != 0UL)`
`1434`	`1438`	`{`
`1435`	`1439`	`return kStatus_USDHC_DMADataAddrNotAlign;`
`1436`	`1440`	`}`
`1437`	`1441`	`/* in simple DMA mode if use auto CMD23, address should load to ADMA addr,`
`1438`	`1442`	`and block count should load to DS_ADDR*/`
`1439`	`1443`	`if (enAutoCmd23)`
`1440`	`1444`	`{`
`1441`		`- base->ADMA_SYS_ADDR = USDHC_ADDR_CPU_2_DMA((uint32_t)dataAddr);`
	`1445`	`+ base->ADMA_SYS_ADDR = USDHC_ADDR_CPU_2_DMA((uintptr_t)dataAddr);`
`1442`	`1446`	`}`
`1443`	`1447`	`else`
`1444`	`1448`	`{`
`1445`		`- base->DS_ADDR = USDHC_ADDR_CPU_2_DMA((uint32_t)dataAddr);`
	`1449`	`+ base->DS_ADDR = USDHC_ADDR_CPU_2_DMA((uintptr_t)dataAddr);`
`1446`	`1450`	`}`
`1447`	`1451`	`}`
`1448`	`1452`	`else`
`1449`	`1453`	`{`
`1450`	`1454`	`/* When use ADMA, disable simple DMA */`
`1451`	`1455`	`base->DS_ADDR = 0UL;`
`1452`		`- base->ADMA_SYS_ADDR = USDHC_ADDR_CPU_2_DMA((uint32_t)(dmaConfig->admaTable));`
	`1456`	`+ base->ADMA_SYS_ADDR = USDHC_ADDR_CPU_2_DMA((uintptr_t)(dmaConfig->admaTable));`
`1453`	`1457`	`}`
`1454`	`1458`
`1455`	`1459`	`#if (defined(FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN) && FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN)`
`@@ -1485,14 +1489,14 @@ status_t USDHC_SetAdmaTableConfig(USDHC_Type *base,`
`1485`	`1489`	`{`
`1486`	`1490`	`assert(NULL != dmaConfig);`
`1487`	`1491`	`assert((NULL != dmaConfig->admaTable) &&`
`1488`		`- (((USDHC_ADMA_TABLE_ADDRESS_ALIGN - 1U) & (uint32_t)dmaConfig->admaTable) == 0UL));`
	`1492`	`+ (((USDHC_ADMA_TABLE_ADDRESS_ALIGN - 1U) & (uintptr_t)dmaConfig->admaTable) == 0UL));`
`1489`	`1493`	`assert(NULL != dataConfig);`
`1490`	`1494`
`1491`	`1495`	`status_t error = kStatus_Fail;`
`1492`	`1496`	`uint32_t bootDummyOffset =`
`1493`	`1497`	`dataConfig->dataType == (uint32_t)kUSDHC_TransferDataBootcontinous ? sizeof(uint32_t) : 0UL;`
`1494`		`- const uint32_t data = (const uint32_t )USDHC_ADDR_CPU_2_DMA((uint32_t)(`
`1495`		`- (uint32_t)((dataConfig->rxData == NULL) ? dataConfig->txData : dataConfig->rxData) + bootDummyOffset));`
	`1498`	`+ const uint32_t data = (const uint32_t )USDHC_ADDR_CPU_2_DMA((uintptr_t)(`
	`1499`	`+ (uintptr_t)((dataConfig->rxData == NULL) ? dataConfig->txData : dataConfig->rxData) + bootDummyOffset));`
`1496`	`1500`	`uint32_t blockSize = dataConfig->blockSize * dataConfig->blockCount - bootDummyOffset;`
`1497`	`1501`
`1498`	`1502`	`#if FSL_FEATURE_USDHC_HAS_EXT_DMA`
`@@ -1605,12 +1609,12 @@ status_t USDHC_TransferBlocking(USDHC_Type base, usdhc_adma_config_t dmaConfig`
`1605`	`1609`	`if (data->txData != NULL)`
`1606`	`1610`	`{`
`1607`	`1611`	`/* clear the DCACHE */`
`1608`		`- DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount));`
	`1612`	`+ DCACHE_CleanByRange((uintptr_t)data->txData, (data->blockSize) * (data->blockCount));`
`1609`	`1613`	`}`
`1610`	`1614`	`else`
`1611`	`1615`	`{`
`1612`	`1616`	`/* clear the DCACHE */`
`1613`		`- DCACHE_CleanInvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount));`
	`1617`	`+ DCACHE_CleanInvalidateByRange((uintptr_t)data->rxData, (data->blockSize) * (data->blockCount));`
`1614`	`1618`	`}`
`1615`	`1619`	`}`
`1616`	`1620`	`#endif`
`@@ -1926,12 +1930,12 @@ status_t USDHC_TransferNonBlocking(USDHC_Type *base,`
`1926`	`1930`	`if (data->txData != NULL)`
`1927`	`1931`	`{`
`1928`	`1932`	`/* clear the DCACHE */`
`1929`		`- DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount));`
	`1933`	`+ DCACHE_CleanByRange((uintptr_t)data->txData, (data->blockSize) * (data->blockCount));`
`1930`	`1934`	`}`
`1931`	`1935`	`else`
`1932`	`1936`	`{`
`1933`	`1937`	`/* clear the DCACHE */`
`1934`		`- DCACHE_CleanInvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount));`
	`1938`	`+ DCACHE_CleanInvalidateByRange((uintptr_t)data->rxData, (data->blockSize) * (data->blockCount));`
`1935`	`1939`	`}`
`1936`	`1940`	`}`
`1937`	`1941`	`#endif`
`@@ -2345,7 +2349,7 @@ static void USDHC_TransferHandleData(USDHC_Type base, usdhc_handle_t handle, u`
`2345`	`2349`	`#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL`
`2346`	`2350`	`if (handle->data->rxData != NULL)`
`2347`	`2351`	`{`
`2348`		`- DCACHE_InvalidateByRange((uint32_t)(handle->data->rxData),`
	`2352`	`+ DCACHE_InvalidateByRange((uintptr_t)(handle->data->rxData),`
`2349`	`2353`	`(handle->data->blockSize) * (handle->data->blockCount));`
`2350`	`2354`	`}`
`2351`	`2355`	`#endif`