From 771f23ec58d459133b1065d26d7a618eedd92260 Mon Sep 17 00:00:00 2001 From: Qiang Zhao Date: Thu, 3 Jul 2025 11:52:50 +0530 Subject: [PATCH 1/2] mcux-sdk-ng: i.MX93: update headers for i.MX93 Update header files for i.MX93. Signed-off-by: Qiang Zhao --- .../i.MX/i.MX93/MIMX9301/CMakeLists.txt | 2 +- .../i.MX/i.MX93/MIMX9301/MIMX9301_cm33.h | 13 +- .../i.MX93/MIMX9301/MIMX9301_cm33_COMMON.h | 31 +- .../i.MX93/MIMX9301/MIMX9301_cm33_features.h | 85 +- .../i.MX93/MIMX9301/fsl_device_registers.h | 2 +- .../i.MX93/MIMX9301/system_MIMX9301_cm33.c | 20 +- .../i.MX93/MIMX9301/system_MIMX9301_cm33.h | 13 +- .../i.MX/i.MX93/MIMX9301/variable.cmake | 1 + .../i.MX/i.MX93/MIMX9302/CMakeLists.txt | 2 +- .../i.MX/i.MX93/MIMX9302/MIMX9302_cm33.h | 13 +- .../i.MX93/MIMX9302/MIMX9302_cm33_COMMON.h | 31 +- .../i.MX93/MIMX9302/MIMX9302_cm33_features.h | 85 +- .../i.MX93/MIMX9302/fsl_device_registers.h | 2 +- .../i.MX93/MIMX9302/system_MIMX9302_cm33.c | 20 +- .../i.MX93/MIMX9302/system_MIMX9302_cm33.h | 13 +- .../i.MX/i.MX93/MIMX9302/variable.cmake | 1 + .../i.MX/i.MX93/MIMX9311/CMakeLists.txt | 2 +- .../i.MX/i.MX93/MIMX9311/MIMX9311_cm33.h | 13 +- .../i.MX93/MIMX9311/MIMX9311_cm33_COMMON.h | 31 +- .../i.MX93/MIMX9311/MIMX9311_cm33_features.h | 85 +- .../i.MX93/MIMX9311/fsl_device_registers.h | 2 +- .../i.MX93/MIMX9311/system_MIMX9311_cm33.c | 20 +- .../i.MX93/MIMX9311/system_MIMX9311_cm33.h | 13 +- .../i.MX/i.MX93/MIMX9311/variable.cmake | 1 + .../i.MX/i.MX93/MIMX9312/CMakeLists.txt | 2 +- .../i.MX/i.MX93/MIMX9312/MIMX9312_cm33.h | 13 +- .../i.MX93/MIMX9312/MIMX9312_cm33_COMMON.h | 31 +- .../i.MX93/MIMX9312/MIMX9312_cm33_features.h | 85 +- .../i.MX93/MIMX9312/fsl_device_registers.h | 2 +- .../i.MX93/MIMX9312/system_MIMX9312_cm33.c | 20 +- .../i.MX93/MIMX9312/system_MIMX9312_cm33.h | 13 +- .../i.MX/i.MX93/MIMX9312/variable.cmake | 1 + .../i.MX/i.MX93/MIMX9321/CMakeLists.txt | 2 +- .../i.MX/i.MX93/MIMX9321/MIMX9321_cm33.h | 13 +- .../i.MX93/MIMX9321/MIMX9321_cm33_COMMON.h | 31 +- .../i.MX93/MIMX9321/MIMX9321_cm33_features.h | 85 +- .../i.MX93/MIMX9321/fsl_device_registers.h | 2 +- .../i.MX93/MIMX9321/system_MIMX9321_cm33.c | 20 +- .../i.MX93/MIMX9321/system_MIMX9321_cm33.h | 13 +- .../i.MX/i.MX93/MIMX9321/variable.cmake | 1 + .../i.MX/i.MX93/MIMX9322/CMakeLists.txt | 2 +- .../i.MX/i.MX93/MIMX9322/MIMX9322_cm33.h | 13 +- .../i.MX93/MIMX9322/MIMX9322_cm33_COMMON.h | 31 +- .../i.MX93/MIMX9322/MIMX9322_cm33_features.h | 85 +- .../i.MX93/MIMX9322/fsl_device_registers.h | 2 +- .../i.MX93/MIMX9322/system_MIMX9322_cm33.c | 20 +- .../i.MX93/MIMX9322/system_MIMX9322_cm33.h | 13 +- .../i.MX/i.MX93/MIMX9322/variable.cmake | 1 + .../i.MX/i.MX93/MIMX9331/CMakeLists.txt | 2 +- .../i.MX/i.MX93/MIMX9331/MIMX9331_cm33.h | 13 +- .../i.MX93/MIMX9331/MIMX9331_cm33_COMMON.h | 31 +- .../i.MX93/MIMX9331/MIMX9331_cm33_features.h | 85 +- .../i.MX93/MIMX9331/fsl_device_registers.h | 2 +- .../i.MX93/MIMX9331/system_MIMX9331_cm33.c | 20 +- .../i.MX93/MIMX9331/system_MIMX9331_cm33.h | 13 +- .../i.MX/i.MX93/MIMX9331/variable.cmake | 1 + .../i.MX/i.MX93/MIMX9332/CMakeLists.txt | 2 +- .../i.MX/i.MX93/MIMX9332/MIMX9332_cm33.h | 13 +- .../i.MX93/MIMX9332/MIMX9332_cm33_COMMON.h | 31 +- .../i.MX93/MIMX9332/MIMX9332_cm33_features.h | 85 +- .../i.MX93/MIMX9332/fsl_device_registers.h | 2 +- .../i.MX93/MIMX9332/system_MIMX9332_cm33.c | 20 +- .../i.MX93/MIMX9332/system_MIMX9332_cm33.h | 13 +- .../i.MX/i.MX93/MIMX9332/variable.cmake | 1 + .../i.MX/i.MX93/MIMX9351/CMakeLists.txt | 2 +- .../i.MX/i.MX93/MIMX9351/MIMX9351_cm33.h | 13 +- .../i.MX93/MIMX9351/MIMX9351_cm33_COMMON.h | 31 +- .../i.MX93/MIMX9351/MIMX9351_cm33_features.h | 85 +- .../i.MX93/MIMX9351/fsl_device_registers.h | 2 +- .../i.MX93/MIMX9351/system_MIMX9351_cm33.c | 20 +- .../i.MX93/MIMX9351/system_MIMX9351_cm33.h | 13 +- .../i.MX/i.MX93/MIMX9351/variable.cmake | 1 + .../i.MX/i.MX93/MIMX9352/CMakeLists.txt | 2 +- .../i.MX/i.MX93/MIMX9352/MIMX9352_cm33.h | 13 +- .../i.MX93/MIMX9352/MIMX9352_cm33_COMMON.h | 31 +- .../i.MX93/MIMX9352/MIMX9352_cm33_features.h | 85 +- .../i.MX/i.MX93/MIMX9352/drivers/fsl_clock.h | 18 +- .../i.MX93/MIMX9352/drivers/fsl_sentinel.c | 33 - .../i.MX93/MIMX9352/drivers/fsl_sentinel.h | 2 - .../i.MX93/MIMX9352/fsl_device_registers.h | 2 +- .../i.MX93/MIMX9352/system_MIMX9352_cm33.c | 20 +- .../i.MX93/MIMX9352/system_MIMX9352_cm33.h | 13 +- .../i.MX/i.MX93/MIMX9352/variable.cmake | 1 + .../devices/i.MX/i.MX93/periph/PERI_ADC.h | 165 ++-- .../devices/i.MX/i.MX93/periph/PERI_ANA_OSC.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_AXBS.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_BBNSM.h | 33 +- .../i.MX/i.MX93/periph/PERI_BLK_CTRL_MLMIX.h | 21 +- .../i.MX/i.MX93/periph/PERI_BLK_CTRL_NICMIX.h | 21 +- .../i.MX93/periph/PERI_BLK_CTRL_NS_AONMIX.h | 53 +- .../i.MX93/periph/PERI_BLK_CTRL_S_AONMIX.h | 31 +- .../i.MX93/periph/PERI_BLK_CTRL_WAKEUPMIX.h | 197 ++-- .../i.MX/i.MX93/periph/PERI_CACHE_ECC_MCM.h | 25 +- .../devices/i.MX/i.MX93/periph/PERI_CAN.h | 23 +- .../devices/i.MX/i.MX93/periph/PERI_CCM.h | 39 +- .../devices/i.MX/i.MX93/periph/PERI_DDRC.h | 32 +- .../i.MX/i.MX93/periph/PERI_DDRMIX_BLK_CTRL.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_DMA.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_DMA4.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_ENET.h | 21 +- .../i.MX/i.MX93/periph/PERI_ENET_QOS.h | 857 +++++++++--------- .../devices/i.MX/i.MX93/periph/PERI_FLEXIO.h | 29 +- .../devices/i.MX/i.MX93/periph/PERI_FLEXSPI.h | 49 +- .../devices/i.MX/i.MX93/periph/PERI_FSB.h | 21 +- .../i.MX/i.MX93/periph/PERI_GPC_CPU_CTRL.h | 21 +- .../i.MX/i.MX93/periph/PERI_GPC_GLOBAL.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_I2S.h | 23 +- .../devices/i.MX/i.MX93/periph/PERI_I3C.h | 286 +++--- .../devices/i.MX/i.MX93/periph/PERI_IOMUXC1.h | 23 +- .../devices/i.MX/i.MX93/periph/PERI_IPC.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_ISI.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_LCDIF.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_LPI2C.h | 53 +- .../devices/i.MX/i.MX93/periph/PERI_LPIT.h | 39 +- .../devices/i.MX/i.MX93/periph/PERI_LPSPI.h | 22 +- .../devices/i.MX/i.MX93/periph/PERI_LPTMR.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_LPUART.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_MCM.h | 21 +- .../i.MX93/periph/PERI_MEDIAMIX_BLK_CTRL.h | 63 +- .../i.MX/i.MX93/periph/PERI_MIPI_CSI.h | 31 +- .../i.MX/i.MX93/periph/PERI_MIPI_DSI.h | 37 +- .../devices/i.MX/i.MX93/periph/PERI_MU.h | 23 +- .../devices/i.MX/i.MX93/periph/PERI_NPU.h | 21 +- .../i.MX/i.MX93/periph/PERI_OCRAM_MECC.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_OTFAD.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_PDM.h | 65 +- .../devices/i.MX/i.MX93/periph/PERI_PLL.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_PXP.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_RGPIO.h | 31 +- .../devices/i.MX/i.MX93/periph/PERI_S3MU.h | 23 +- .../devices/i.MX/i.MX93/periph/PERI_SEMA42.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_SPDIF.h | 21 +- .../i.MX/i.MX93/periph/PERI_SRC_GENERAL_REG.h | 21 +- .../i.MX/i.MX93/periph/PERI_SRC_MEM_SLICE.h | 21 +- .../i.MX/i.MX93/periph/PERI_SRC_MIX_SLICE.h | 29 +- .../devices/i.MX/i.MX93/periph/PERI_SYSPM.h | 21 +- .../i.MX/i.MX93/periph/PERI_SYS_CTR_COMPARE.h | 21 +- .../i.MX/i.MX93/periph/PERI_SYS_CTR_CONTROL.h | 21 +- .../i.MX/i.MX93/periph/PERI_SYS_CTR_READ.h | 21 +- .../i.MX/i.MX93/periph/PERI_TCM_ECC_MCM.h | 25 +- .../devices/i.MX/i.MX93/periph/PERI_TMU.h | 107 +-- .../devices/i.MX/i.MX93/periph/PERI_TPM.h | 21 +- .../i.MX/i.MX93/periph/PERI_TRDC_MBC0.h | 21 +- .../i.MX/i.MX93/periph/PERI_TRDC_MBC2.h | 37 +- .../i.MX/i.MX93/periph/PERI_TRDC_MBC4.h | 37 +- .../devices/i.MX/i.MX93/periph/PERI_TRGMUX.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_TSTMR.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_USB.h | 33 +- .../devices/i.MX/i.MX93/periph/PERI_USBNC.h | 41 +- .../devices/i.MX/i.MX93/periph/PERI_USDHC.h | 325 +++---- .../i.MX/i.MX93/periph/PERI_WAKEUP_AHBRM.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_WDOG.h | 21 +- .../devices/i.MX/i.MX93/periph/PERI_XCACHE.h | 21 +- 153 files changed, 3164 insertions(+), 2222 deletions(-) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/CMakeLists.txt index 75c60332d0..d6c1b6062c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/CMakeLists.txt @@ -5,7 +5,7 @@ #### device spepcific drivers include(${SdkRootDirPath}/devices/arm/device_header.cmake) -mcux_add_cmakelists(${SdkRootDirPath}/devices/i.MX/i.MX93/MIMX9301/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/i.MX/i.MX93/MIMX9301/drivers) #### i.MX shared drivers/components/middlewares, project segments include(${SdkRootDirPath}/devices/i.MX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33.h index 7de51d816b..3f827eea55 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33.h @@ -8,14 +8,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240814 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9301_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -24,14 +24,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9301_cm33.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9301_cm33 * * CMSIS Peripheral Access Layer for MIMX9301_cm33 diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33_COMMON.h index 20c9dd5624..f08c80dd9d 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33_COMMON.h @@ -8,14 +8,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240823 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9301_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -24,14 +24,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9301_cm33_COMMON.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9301_cm33 * * CMSIS Peripheral Access Layer for MIMX9301_cm33 @@ -42,7 +45,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U +#define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -375,7 +378,9 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +#ifndef MIMX9301_cm33_SERIES #define MIMX9301_cm33_SERIES +#endif /* CPU specific feature definitions */ #include "MIMX9301_cm33_features.h" @@ -2980,13 +2985,13 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6_NS ((TPM_Type *)TPM6_BASE_NS) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS_NS { TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } + #define TPM_BASE_ADDRS_NS { 0u, TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS_NS { TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } + #define TPM_BASE_PTRS_NS { (TPM_Type *)0u, TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } #else /** Peripheral TPM1 base address */ #define TPM1_BASE (0x44310000u) @@ -3013,12 +3018,12 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6 ((TPM_Type *)TPM6_BASE) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } #endif /** Interrupt vectors for the TPM peripheral type */ -#define TPM_IRQS { TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } +#define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } /* TRDC_MBC0 - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33_features.h index 1064ffb4c2..596956da0b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b241030 +** Build: b250623 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,6 +25,8 @@ /* SOC module features */ +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) /* @brief AXBS availability on the SoC. */ #define FSL_FEATURE_SOC_AXBS_COUNT (1) /* @brief BBNSM availability on the SoC. */ @@ -100,10 +102,17 @@ /* @brief XCACHE availability on the SoC. */ #define FSL_FEATURE_SOC_XCACHE_COUNT (2) +/* ADC module features */ + +/* @brief Channel group counts of ADC. */ +#define FSL_FEATURE_ADC_CHANNEL_GROUPS_COUNT (2) +/* @brief Threshold counts of ADC. */ +#define FSL_FEATURE_ADC_THRESHOLDS_COUNT (8) +/* @brief Self-test threshold counts of ADC. */ +#define FSL_FEATURE_ADC_SELF_TEST_THRESHOLDS_COUNT (6) + /* FLEXCAN module features */ -/* @brief Has more than 64 MBs. */ -#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) /* @brief Message buffer size */ #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (96) /* @brief Has doze mode support (register bit field MCR[DOZE]). */ @@ -152,12 +161,36 @@ #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) /* @brief Has Enhanced Rx FIFO. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (20) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (128) /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (1) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (1) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (1) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (0) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* EDMA module features */ @@ -294,12 +327,14 @@ /* FLEXIO module features */ +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) -/* @brief Has pin input output related registers */ -#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ @@ -316,10 +351,12 @@ #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) /* @brief Reset value of the FLEXIO_PARAM register */ #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808) -/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ -#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Flexio DMA request base channel */ #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* FLEXSPI module features */ @@ -377,6 +414,18 @@ #define FSL_FEATURE_I3C_HAS_HDROK (1) /* @brief SOC doesn't support slave IBI/MR/HJ. */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* XCACHE module features */ @@ -391,6 +440,8 @@ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -403,15 +454,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (1) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (1) /* LPTMR module features */ @@ -497,12 +548,18 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (1) /* @brief Has register Half Duplex Control. */ #define FSL_FEATURE_LPUART_HAS_HDCR (1) /* @brief Has register Timeout. */ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -621,12 +678,16 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) +/* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ +#define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/fsl_device_registers.h index 8f20e8920c..02a1625c42 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/fsl_device_registers.h @@ -1,6 +1,6 @@ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2024 NXP + * Copyright 2016-2025 NXP * SPDX-License-Identifier: BSD-3-Clause * */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/system_MIMX9301_cm33.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/system_MIMX9301_cm33.c index 7ecd455f35..672e1224a0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/system_MIMX9301_cm33.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/system_MIMX9301_cm33.c @@ -8,8 +8,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -17,7 +17,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -26,10 +26,14 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ + #include "system_MIMX9301_cm33.h" /* ---------------------------------------------------------------------------- @@ -44,11 +48,11 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; void SystemInit(void) { #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ SystemInitHook(); } diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/system_MIMX9301_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/system_MIMX9301_cm33.h index ebc87afc4a..cf63186e27 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/system_MIMX9301_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/system_MIMX9301_cm33.h @@ -8,8 +8,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -17,7 +17,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -26,12 +26,15 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ #ifndef _SYSTEM_MIMX9301_cm33_H_ -#define _SYSTEM_MIMX9301_cm33_H_ /**< Symbol preventing repeated inclusion */ +#define _SYSTEM_MIMX9301_cm33_H_ /**< Symbol preventing repeated inclusion */ #ifdef __cplusplus extern "C" { @@ -87,4 +90,4 @@ void SystemCoreClockUpdate(void); } #endif -#endif /* _SYSTEM_MIMX9301_cm33_H_ */ +#endif /* _SYSTEM_MIMX9301_cm33_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/variable.cmake b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/variable.cmake index b8eecd7de1..645739f294 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/variable.cmake +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/variable.cmake @@ -6,6 +6,7 @@ #### chip related include(${SdkRootDirPath}/devices/i.MX/variable.cmake) mcux_set_variable(device MIMX9301) +mcux_set_variable(device_root devices) mcux_set_variable(soc_series i.MX93) mcux_set_variable(soc_periph periph) mcux_set_variable(core_id_suffix_name "_cm33") diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/CMakeLists.txt index 9047db24bb..5765156ca2 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/CMakeLists.txt @@ -5,7 +5,7 @@ #### device spepcific drivers include(${SdkRootDirPath}/devices/arm/device_header.cmake) -mcux_add_cmakelists(${SdkRootDirPath}/devices/i.MX/i.MX93/MIMX9302/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/i.MX/i.MX93/MIMX9302/drivers) #### i.MX shared drivers/components/middlewares, project segments include(${SdkRootDirPath}/devices/i.MX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33.h index d331716257..9cc6a0a4ad 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33.h @@ -8,14 +8,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240814 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9302_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -24,14 +24,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9302_cm33.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9302_cm33 * * CMSIS Peripheral Access Layer for MIMX9302_cm33 diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33_COMMON.h index 6c8f2435e1..76209860f8 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33_COMMON.h @@ -8,14 +8,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240823 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9302_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -24,14 +24,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9302_cm33_COMMON.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9302_cm33 * * CMSIS Peripheral Access Layer for MIMX9302_cm33 @@ -42,7 +45,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U +#define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -375,7 +378,9 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +#ifndef MIMX9302_cm33_SERIES #define MIMX9302_cm33_SERIES +#endif /* CPU specific feature definitions */ #include "MIMX9302_cm33_features.h" @@ -2980,13 +2985,13 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6_NS ((TPM_Type *)TPM6_BASE_NS) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS_NS { TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } + #define TPM_BASE_ADDRS_NS { 0u, TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS_NS { TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } + #define TPM_BASE_PTRS_NS { (TPM_Type *)0u, TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } #else /** Peripheral TPM1 base address */ #define TPM1_BASE (0x44310000u) @@ -3013,12 +3018,12 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6 ((TPM_Type *)TPM6_BASE) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } #endif /** Interrupt vectors for the TPM peripheral type */ -#define TPM_IRQS { TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } +#define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } /* TRDC_MBC0 - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33_features.h index 50e06636c1..6c27011c8f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b241030 +** Build: b250623 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,6 +25,8 @@ /* SOC module features */ +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) /* @brief AXBS availability on the SoC. */ #define FSL_FEATURE_SOC_AXBS_COUNT (1) /* @brief BBNSM availability on the SoC. */ @@ -100,10 +102,17 @@ /* @brief XCACHE availability on the SoC. */ #define FSL_FEATURE_SOC_XCACHE_COUNT (2) +/* ADC module features */ + +/* @brief Channel group counts of ADC. */ +#define FSL_FEATURE_ADC_CHANNEL_GROUPS_COUNT (2) +/* @brief Threshold counts of ADC. */ +#define FSL_FEATURE_ADC_THRESHOLDS_COUNT (8) +/* @brief Self-test threshold counts of ADC. */ +#define FSL_FEATURE_ADC_SELF_TEST_THRESHOLDS_COUNT (6) + /* FLEXCAN module features */ -/* @brief Has more than 64 MBs. */ -#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) /* @brief Message buffer size */ #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (96) /* @brief Has doze mode support (register bit field MCR[DOZE]). */ @@ -152,12 +161,36 @@ #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) /* @brief Has Enhanced Rx FIFO. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (20) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (128) /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (1) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (1) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (1) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (0) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* EDMA module features */ @@ -294,12 +327,14 @@ /* FLEXIO module features */ +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) -/* @brief Has pin input output related registers */ -#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ @@ -316,10 +351,12 @@ #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) /* @brief Reset value of the FLEXIO_PARAM register */ #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808) -/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ -#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Flexio DMA request base channel */ #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* FLEXSPI module features */ @@ -377,6 +414,18 @@ #define FSL_FEATURE_I3C_HAS_HDROK (1) /* @brief SOC doesn't support slave IBI/MR/HJ. */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* XCACHE module features */ @@ -391,6 +440,8 @@ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -403,15 +454,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (1) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (1) /* LPTMR module features */ @@ -497,12 +548,18 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (1) /* @brief Has register Half Duplex Control. */ #define FSL_FEATURE_LPUART_HAS_HDCR (1) /* @brief Has register Timeout. */ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -621,12 +678,16 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) +/* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ +#define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/fsl_device_registers.h index e514132f69..7588b24e85 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/fsl_device_registers.h @@ -1,6 +1,6 @@ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2024 NXP + * Copyright 2016-2025 NXP * SPDX-License-Identifier: BSD-3-Clause * */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/system_MIMX9302_cm33.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/system_MIMX9302_cm33.c index a2417762ff..c7829375bc 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/system_MIMX9302_cm33.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/system_MIMX9302_cm33.c @@ -8,8 +8,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -17,7 +17,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -26,10 +26,14 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ + #include "system_MIMX9302_cm33.h" /* ---------------------------------------------------------------------------- @@ -44,11 +48,11 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; void SystemInit(void) { #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ SystemInitHook(); } diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/system_MIMX9302_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/system_MIMX9302_cm33.h index cb810d7360..4d74a4b1b8 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/system_MIMX9302_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/system_MIMX9302_cm33.h @@ -8,8 +8,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -17,7 +17,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -26,12 +26,15 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ #ifndef _SYSTEM_MIMX9302_cm33_H_ -#define _SYSTEM_MIMX9302_cm33_H_ /**< Symbol preventing repeated inclusion */ +#define _SYSTEM_MIMX9302_cm33_H_ /**< Symbol preventing repeated inclusion */ #ifdef __cplusplus extern "C" { @@ -87,4 +90,4 @@ void SystemCoreClockUpdate(void); } #endif -#endif /* _SYSTEM_MIMX9302_cm33_H_ */ +#endif /* _SYSTEM_MIMX9302_cm33_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/variable.cmake b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/variable.cmake index ac59eaa16d..eb1d651095 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/variable.cmake +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/variable.cmake @@ -6,6 +6,7 @@ #### chip related include(${SdkRootDirPath}/devices/i.MX/variable.cmake) mcux_set_variable(device MIMX9302) +mcux_set_variable(device_root devices) mcux_set_variable(soc_series i.MX93) mcux_set_variable(soc_periph periph) mcux_set_variable(core_id_suffix_name "_cm33") diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/CMakeLists.txt index 4af1656fea..bb834694ae 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/CMakeLists.txt @@ -5,7 +5,7 @@ #### device spepcific drivers include(${SdkRootDirPath}/devices/arm/device_header.cmake) -mcux_add_cmakelists(${SdkRootDirPath}/devices/i.MX/i.MX93/MIMX9311/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/i.MX/i.MX93/MIMX9311/drivers) #### i.MX shared drivers/components/middlewares, project segments include(${SdkRootDirPath}/devices/i.MX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33.h index 4ac03a8888..26ae4e5829 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33.h @@ -9,14 +9,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240814 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9311_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,14 +25,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9311_cm33.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9311_cm33 * * CMSIS Peripheral Access Layer for MIMX9311_cm33 diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33_COMMON.h index 58694e9cd3..5c7ec5b8ff 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33_COMMON.h @@ -9,14 +9,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240823 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9311_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,14 +25,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9311_cm33_COMMON.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9311_cm33 * * CMSIS Peripheral Access Layer for MIMX9311_cm33 @@ -43,7 +46,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U +#define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -376,7 +379,9 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +#ifndef MIMX9311_cm33_SERIES #define MIMX9311_cm33_SERIES +#endif /* CPU specific feature definitions */ #include "MIMX9311_cm33_features.h" @@ -2981,13 +2986,13 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6_NS ((TPM_Type *)TPM6_BASE_NS) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS_NS { TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } + #define TPM_BASE_ADDRS_NS { 0u, TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS_NS { TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } + #define TPM_BASE_PTRS_NS { (TPM_Type *)0u, TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } #else /** Peripheral TPM1 base address */ #define TPM1_BASE (0x44310000u) @@ -3014,12 +3019,12 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6 ((TPM_Type *)TPM6_BASE) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } #endif /** Interrupt vectors for the TPM peripheral type */ -#define TPM_IRQS { TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } +#define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } /* TRDC_MBC0 - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33_features.h index 46d12711c3..1b00203791 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b241030 +** Build: b250623 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,6 +25,8 @@ /* SOC module features */ +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) /* @brief AXBS availability on the SoC. */ #define FSL_FEATURE_SOC_AXBS_COUNT (1) /* @brief BBNSM availability on the SoC. */ @@ -100,10 +102,17 @@ /* @brief XCACHE availability on the SoC. */ #define FSL_FEATURE_SOC_XCACHE_COUNT (2) +/* ADC module features */ + +/* @brief Channel group counts of ADC. */ +#define FSL_FEATURE_ADC_CHANNEL_GROUPS_COUNT (2) +/* @brief Threshold counts of ADC. */ +#define FSL_FEATURE_ADC_THRESHOLDS_COUNT (8) +/* @brief Self-test threshold counts of ADC. */ +#define FSL_FEATURE_ADC_SELF_TEST_THRESHOLDS_COUNT (6) + /* FLEXCAN module features */ -/* @brief Has more than 64 MBs. */ -#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) /* @brief Message buffer size */ #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (96) /* @brief Has doze mode support (register bit field MCR[DOZE]). */ @@ -152,12 +161,36 @@ #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) /* @brief Has Enhanced Rx FIFO. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (20) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (128) /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (1) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (1) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (1) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (0) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* EDMA module features */ @@ -294,12 +327,14 @@ /* FLEXIO module features */ +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) -/* @brief Has pin input output related registers */ -#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ @@ -316,10 +351,12 @@ #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) /* @brief Reset value of the FLEXIO_PARAM register */ #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808) -/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ -#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Flexio DMA request base channel */ #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* FLEXSPI module features */ @@ -377,6 +414,18 @@ #define FSL_FEATURE_I3C_HAS_HDROK (1) /* @brief SOC doesn't support slave IBI/MR/HJ. */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* XCACHE module features */ @@ -391,6 +440,8 @@ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -403,15 +454,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (1) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (1) /* LPTMR module features */ @@ -497,12 +548,18 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (1) /* @brief Has register Half Duplex Control. */ #define FSL_FEATURE_LPUART_HAS_HDCR (1) /* @brief Has register Timeout. */ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -621,12 +678,16 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) +/* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ +#define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/fsl_device_registers.h index 91547b0172..9be274f97f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/fsl_device_registers.h @@ -1,6 +1,6 @@ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2024 NXP + * Copyright 2016-2025 NXP * SPDX-License-Identifier: BSD-3-Clause * */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/system_MIMX9311_cm33.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/system_MIMX9311_cm33.c index 9e62d0c5dd..569589c6ee 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/system_MIMX9311_cm33.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/system_MIMX9311_cm33.c @@ -9,8 +9,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -18,7 +18,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -27,10 +27,14 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ + #include "system_MIMX9311_cm33.h" /* ---------------------------------------------------------------------------- @@ -45,11 +49,11 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; void SystemInit(void) { #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ SystemInitHook(); } diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/system_MIMX9311_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/system_MIMX9311_cm33.h index e8dcab8a74..0206cca283 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/system_MIMX9311_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/system_MIMX9311_cm33.h @@ -9,8 +9,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -18,7 +18,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -27,12 +27,15 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ #ifndef _SYSTEM_MIMX9311_cm33_H_ -#define _SYSTEM_MIMX9311_cm33_H_ /**< Symbol preventing repeated inclusion */ +#define _SYSTEM_MIMX9311_cm33_H_ /**< Symbol preventing repeated inclusion */ #ifdef __cplusplus extern "C" { @@ -88,4 +91,4 @@ void SystemCoreClockUpdate(void); } #endif -#endif /* _SYSTEM_MIMX9311_cm33_H_ */ +#endif /* _SYSTEM_MIMX9311_cm33_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/variable.cmake b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/variable.cmake index 09c7754f2e..29ef7ab45a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/variable.cmake +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/variable.cmake @@ -6,6 +6,7 @@ #### chip related include(${SdkRootDirPath}/devices/i.MX/variable.cmake) mcux_set_variable(device MIMX9311) +mcux_set_variable(device_root devices) mcux_set_variable(soc_series i.MX93) mcux_set_variable(soc_periph periph) mcux_set_variable(core_id_suffix_name "_cm33") diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/CMakeLists.txt index 53057cbd95..c417a498ea 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/CMakeLists.txt @@ -5,7 +5,7 @@ #### device spepcific drivers include(${SdkRootDirPath}/devices/arm/device_header.cmake) -mcux_add_cmakelists(${SdkRootDirPath}/devices/i.MX/i.MX93/MIMX9312/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/i.MX/i.MX93/MIMX9312/drivers) #### i.MX shared drivers/components/middlewares, project segments include(${SdkRootDirPath}/devices/i.MX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33.h index 500de51105..1efd5d233d 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33.h @@ -9,14 +9,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240814 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9312_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,14 +25,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9312_cm33.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9312_cm33 * * CMSIS Peripheral Access Layer for MIMX9312_cm33 diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33_COMMON.h index 9a05cb4b42..6ec84f5908 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33_COMMON.h @@ -9,14 +9,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240823 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9312_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,14 +25,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9312_cm33_COMMON.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9312_cm33 * * CMSIS Peripheral Access Layer for MIMX9312_cm33 @@ -43,7 +46,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U +#define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -376,7 +379,9 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +#ifndef MIMX9312_cm33_SERIES #define MIMX9312_cm33_SERIES +#endif /* CPU specific feature definitions */ #include "MIMX9312_cm33_features.h" @@ -2981,13 +2986,13 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6_NS ((TPM_Type *)TPM6_BASE_NS) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS_NS { TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } + #define TPM_BASE_ADDRS_NS { 0u, TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS_NS { TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } + #define TPM_BASE_PTRS_NS { (TPM_Type *)0u, TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } #else /** Peripheral TPM1 base address */ #define TPM1_BASE (0x44310000u) @@ -3014,12 +3019,12 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6 ((TPM_Type *)TPM6_BASE) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } #endif /** Interrupt vectors for the TPM peripheral type */ -#define TPM_IRQS { TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } +#define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } /* TRDC_MBC0 - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33_features.h index 3badf8ea1f..f0d1d1291c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b241030 +** Build: b250623 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,6 +25,8 @@ /* SOC module features */ +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) /* @brief AXBS availability on the SoC. */ #define FSL_FEATURE_SOC_AXBS_COUNT (1) /* @brief BBNSM availability on the SoC. */ @@ -100,10 +102,17 @@ /* @brief XCACHE availability on the SoC. */ #define FSL_FEATURE_SOC_XCACHE_COUNT (2) +/* ADC module features */ + +/* @brief Channel group counts of ADC. */ +#define FSL_FEATURE_ADC_CHANNEL_GROUPS_COUNT (2) +/* @brief Threshold counts of ADC. */ +#define FSL_FEATURE_ADC_THRESHOLDS_COUNT (8) +/* @brief Self-test threshold counts of ADC. */ +#define FSL_FEATURE_ADC_SELF_TEST_THRESHOLDS_COUNT (6) + /* FLEXCAN module features */ -/* @brief Has more than 64 MBs. */ -#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) /* @brief Message buffer size */ #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (96) /* @brief Has doze mode support (register bit field MCR[DOZE]). */ @@ -152,12 +161,36 @@ #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) /* @brief Has Enhanced Rx FIFO. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (20) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (128) /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (1) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (1) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (1) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (0) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* EDMA module features */ @@ -294,12 +327,14 @@ /* FLEXIO module features */ +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) -/* @brief Has pin input output related registers */ -#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ @@ -316,10 +351,12 @@ #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) /* @brief Reset value of the FLEXIO_PARAM register */ #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808) -/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ -#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Flexio DMA request base channel */ #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* FLEXSPI module features */ @@ -377,6 +414,18 @@ #define FSL_FEATURE_I3C_HAS_HDROK (1) /* @brief SOC doesn't support slave IBI/MR/HJ. */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* XCACHE module features */ @@ -391,6 +440,8 @@ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -403,15 +454,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (1) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (1) /* LPTMR module features */ @@ -497,12 +548,18 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (1) /* @brief Has register Half Duplex Control. */ #define FSL_FEATURE_LPUART_HAS_HDCR (1) /* @brief Has register Timeout. */ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -621,12 +678,16 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) +/* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ +#define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/fsl_device_registers.h index 53208bc4ac..977e357190 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/fsl_device_registers.h @@ -1,6 +1,6 @@ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2024 NXP + * Copyright 2016-2025 NXP * SPDX-License-Identifier: BSD-3-Clause * */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/system_MIMX9312_cm33.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/system_MIMX9312_cm33.c index 227877c586..9e16821ac8 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/system_MIMX9312_cm33.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/system_MIMX9312_cm33.c @@ -9,8 +9,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -18,7 +18,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -27,10 +27,14 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ + #include "system_MIMX9312_cm33.h" /* ---------------------------------------------------------------------------- @@ -45,11 +49,11 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; void SystemInit(void) { #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ SystemInitHook(); } diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/system_MIMX9312_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/system_MIMX9312_cm33.h index d520c2bea0..dcaec33057 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/system_MIMX9312_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/system_MIMX9312_cm33.h @@ -9,8 +9,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -18,7 +18,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -27,12 +27,15 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ #ifndef _SYSTEM_MIMX9312_cm33_H_ -#define _SYSTEM_MIMX9312_cm33_H_ /**< Symbol preventing repeated inclusion */ +#define _SYSTEM_MIMX9312_cm33_H_ /**< Symbol preventing repeated inclusion */ #ifdef __cplusplus extern "C" { @@ -88,4 +91,4 @@ void SystemCoreClockUpdate(void); } #endif -#endif /* _SYSTEM_MIMX9312_cm33_H_ */ +#endif /* _SYSTEM_MIMX9312_cm33_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/variable.cmake b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/variable.cmake index a9968796fa..cdfb9446aa 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/variable.cmake +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/variable.cmake @@ -6,6 +6,7 @@ #### chip related include(${SdkRootDirPath}/devices/i.MX/variable.cmake) mcux_set_variable(device MIMX9312) +mcux_set_variable(device_root devices) mcux_set_variable(soc_series i.MX93) mcux_set_variable(soc_periph periph) mcux_set_variable(core_id_suffix_name "_cm33") diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/CMakeLists.txt index 7a0a9de211..cbb044f4fe 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/CMakeLists.txt @@ -5,7 +5,7 @@ #### device spepcific drivers include(${SdkRootDirPath}/devices/arm/device_header.cmake) -mcux_add_cmakelists(${SdkRootDirPath}/devices/i.MX/i.MX93/MIMX9321/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/i.MX/i.MX93/MIMX9321/drivers) #### i.MX shared drivers/components/middlewares, project segments include(${SdkRootDirPath}/devices/i.MX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33.h index 23fde9f9e5..3f96413fef 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33.h @@ -9,14 +9,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240814 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9321_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,14 +25,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9321_cm33.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9321_cm33 * * CMSIS Peripheral Access Layer for MIMX9321_cm33 diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33_COMMON.h index 28c2138f17..c0098ab72c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33_COMMON.h @@ -9,14 +9,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240823 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9321_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,14 +25,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9321_cm33_COMMON.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9321_cm33 * * CMSIS Peripheral Access Layer for MIMX9321_cm33 @@ -43,7 +46,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U +#define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -376,7 +379,9 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +#ifndef MIMX9321_cm33_SERIES #define MIMX9321_cm33_SERIES +#endif /* CPU specific feature definitions */ #include "MIMX9321_cm33_features.h" @@ -2981,13 +2986,13 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6_NS ((TPM_Type *)TPM6_BASE_NS) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS_NS { TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } + #define TPM_BASE_ADDRS_NS { 0u, TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS_NS { TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } + #define TPM_BASE_PTRS_NS { (TPM_Type *)0u, TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } #else /** Peripheral TPM1 base address */ #define TPM1_BASE (0x44310000u) @@ -3014,12 +3019,12 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6 ((TPM_Type *)TPM6_BASE) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } #endif /** Interrupt vectors for the TPM peripheral type */ -#define TPM_IRQS { TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } +#define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } /* TRDC_MBC0 - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33_features.h index a0e49de308..c9f8256d5e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b241030 +** Build: b250623 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,6 +25,8 @@ /* SOC module features */ +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) /* @brief AXBS availability on the SoC. */ #define FSL_FEATURE_SOC_AXBS_COUNT (1) /* @brief BBNSM availability on the SoC. */ @@ -100,10 +102,17 @@ /* @brief XCACHE availability on the SoC. */ #define FSL_FEATURE_SOC_XCACHE_COUNT (2) +/* ADC module features */ + +/* @brief Channel group counts of ADC. */ +#define FSL_FEATURE_ADC_CHANNEL_GROUPS_COUNT (2) +/* @brief Threshold counts of ADC. */ +#define FSL_FEATURE_ADC_THRESHOLDS_COUNT (8) +/* @brief Self-test threshold counts of ADC. */ +#define FSL_FEATURE_ADC_SELF_TEST_THRESHOLDS_COUNT (6) + /* FLEXCAN module features */ -/* @brief Has more than 64 MBs. */ -#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) /* @brief Message buffer size */ #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (96) /* @brief Has doze mode support (register bit field MCR[DOZE]). */ @@ -152,12 +161,36 @@ #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) /* @brief Has Enhanced Rx FIFO. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (20) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (128) /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (1) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (1) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (1) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (0) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* EDMA module features */ @@ -294,12 +327,14 @@ /* FLEXIO module features */ +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) -/* @brief Has pin input output related registers */ -#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ @@ -316,10 +351,12 @@ #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) /* @brief Reset value of the FLEXIO_PARAM register */ #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808) -/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ -#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Flexio DMA request base channel */ #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* FLEXSPI module features */ @@ -377,6 +414,18 @@ #define FSL_FEATURE_I3C_HAS_HDROK (1) /* @brief SOC doesn't support slave IBI/MR/HJ. */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* XCACHE module features */ @@ -391,6 +440,8 @@ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -403,15 +454,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (1) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (1) /* LPTMR module features */ @@ -497,12 +548,18 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (1) /* @brief Has register Half Duplex Control. */ #define FSL_FEATURE_LPUART_HAS_HDCR (1) /* @brief Has register Timeout. */ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -621,12 +678,16 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) +/* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ +#define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/fsl_device_registers.h index f3354e829f..c59285913e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/fsl_device_registers.h @@ -1,6 +1,6 @@ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2024 NXP + * Copyright 2016-2025 NXP * SPDX-License-Identifier: BSD-3-Clause * */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/system_MIMX9321_cm33.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/system_MIMX9321_cm33.c index 92542e7834..7865c37c92 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/system_MIMX9321_cm33.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/system_MIMX9321_cm33.c @@ -9,8 +9,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -18,7 +18,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -27,10 +27,14 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ + #include "system_MIMX9321_cm33.h" /* ---------------------------------------------------------------------------- @@ -45,11 +49,11 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; void SystemInit(void) { #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ SystemInitHook(); } diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/system_MIMX9321_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/system_MIMX9321_cm33.h index 7ff6f0ac02..96a9fa2fb6 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/system_MIMX9321_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/system_MIMX9321_cm33.h @@ -9,8 +9,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -18,7 +18,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -27,12 +27,15 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ #ifndef _SYSTEM_MIMX9321_cm33_H_ -#define _SYSTEM_MIMX9321_cm33_H_ /**< Symbol preventing repeated inclusion */ +#define _SYSTEM_MIMX9321_cm33_H_ /**< Symbol preventing repeated inclusion */ #ifdef __cplusplus extern "C" { @@ -88,4 +91,4 @@ void SystemCoreClockUpdate(void); } #endif -#endif /* _SYSTEM_MIMX9321_cm33_H_ */ +#endif /* _SYSTEM_MIMX9321_cm33_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/variable.cmake b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/variable.cmake index bd6e961fe8..85344e92c9 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/variable.cmake +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/variable.cmake @@ -6,6 +6,7 @@ #### chip related include(${SdkRootDirPath}/devices/i.MX/variable.cmake) mcux_set_variable(device MIMX9321) +mcux_set_variable(device_root devices) mcux_set_variable(soc_series i.MX93) mcux_set_variable(soc_periph periph) mcux_set_variable(core_id_suffix_name "_cm33") diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/CMakeLists.txt index 56e26079a7..81bf351ddc 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/CMakeLists.txt @@ -5,7 +5,7 @@ #### device spepcific drivers include(${SdkRootDirPath}/devices/arm/device_header.cmake) -mcux_add_cmakelists(${SdkRootDirPath}/devices/i.MX/i.MX93/MIMX9322/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/i.MX/i.MX93/MIMX9322/drivers) #### i.MX shared drivers/components/middlewares, project segments include(${SdkRootDirPath}/devices/i.MX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33.h index df0972c883..5b0956c7a6 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33.h @@ -9,14 +9,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240814 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9322_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,14 +25,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9322_cm33.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9322_cm33 * * CMSIS Peripheral Access Layer for MIMX9322_cm33 diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33_COMMON.h index 15a633c37f..0a151e67b7 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33_COMMON.h @@ -9,14 +9,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240823 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9322_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,14 +25,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9322_cm33_COMMON.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9322_cm33 * * CMSIS Peripheral Access Layer for MIMX9322_cm33 @@ -43,7 +46,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U +#define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -376,7 +379,9 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +#ifndef MIMX9322_cm33_SERIES #define MIMX9322_cm33_SERIES +#endif /* CPU specific feature definitions */ #include "MIMX9322_cm33_features.h" @@ -2981,13 +2986,13 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6_NS ((TPM_Type *)TPM6_BASE_NS) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS_NS { TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } + #define TPM_BASE_ADDRS_NS { 0u, TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS_NS { TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } + #define TPM_BASE_PTRS_NS { (TPM_Type *)0u, TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } #else /** Peripheral TPM1 base address */ #define TPM1_BASE (0x44310000u) @@ -3014,12 +3019,12 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6 ((TPM_Type *)TPM6_BASE) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } #endif /** Interrupt vectors for the TPM peripheral type */ -#define TPM_IRQS { TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } +#define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } /* TRDC_MBC0 - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33_features.h index bfeb51f310..aeecc7387f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b241030 +** Build: b250623 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,6 +25,8 @@ /* SOC module features */ +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) /* @brief AXBS availability on the SoC. */ #define FSL_FEATURE_SOC_AXBS_COUNT (1) /* @brief BBNSM availability on the SoC. */ @@ -100,10 +102,17 @@ /* @brief XCACHE availability on the SoC. */ #define FSL_FEATURE_SOC_XCACHE_COUNT (2) +/* ADC module features */ + +/* @brief Channel group counts of ADC. */ +#define FSL_FEATURE_ADC_CHANNEL_GROUPS_COUNT (2) +/* @brief Threshold counts of ADC. */ +#define FSL_FEATURE_ADC_THRESHOLDS_COUNT (8) +/* @brief Self-test threshold counts of ADC. */ +#define FSL_FEATURE_ADC_SELF_TEST_THRESHOLDS_COUNT (6) + /* FLEXCAN module features */ -/* @brief Has more than 64 MBs. */ -#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) /* @brief Message buffer size */ #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (96) /* @brief Has doze mode support (register bit field MCR[DOZE]). */ @@ -152,12 +161,36 @@ #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) /* @brief Has Enhanced Rx FIFO. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (20) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (128) /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (1) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (1) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (1) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (0) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* EDMA module features */ @@ -294,12 +327,14 @@ /* FLEXIO module features */ +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) -/* @brief Has pin input output related registers */ -#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ @@ -316,10 +351,12 @@ #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) /* @brief Reset value of the FLEXIO_PARAM register */ #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808) -/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ -#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Flexio DMA request base channel */ #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* FLEXSPI module features */ @@ -377,6 +414,18 @@ #define FSL_FEATURE_I3C_HAS_HDROK (1) /* @brief SOC doesn't support slave IBI/MR/HJ. */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* XCACHE module features */ @@ -391,6 +440,8 @@ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -403,15 +454,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (1) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (1) /* LPTMR module features */ @@ -497,12 +548,18 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (1) /* @brief Has register Half Duplex Control. */ #define FSL_FEATURE_LPUART_HAS_HDCR (1) /* @brief Has register Timeout. */ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -621,12 +678,16 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) +/* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ +#define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/fsl_device_registers.h index 7023f17f3f..6031a785bf 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/fsl_device_registers.h @@ -1,6 +1,6 @@ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2024 NXP + * Copyright 2016-2025 NXP * SPDX-License-Identifier: BSD-3-Clause * */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/system_MIMX9322_cm33.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/system_MIMX9322_cm33.c index 078e582b75..5df5f7cc22 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/system_MIMX9322_cm33.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/system_MIMX9322_cm33.c @@ -9,8 +9,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -18,7 +18,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -27,10 +27,14 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ + #include "system_MIMX9322_cm33.h" /* ---------------------------------------------------------------------------- @@ -45,11 +49,11 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; void SystemInit(void) { #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ SystemInitHook(); } diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/system_MIMX9322_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/system_MIMX9322_cm33.h index 26bbb8df69..63282a273e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/system_MIMX9322_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/system_MIMX9322_cm33.h @@ -9,8 +9,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -18,7 +18,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -27,12 +27,15 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ #ifndef _SYSTEM_MIMX9322_cm33_H_ -#define _SYSTEM_MIMX9322_cm33_H_ /**< Symbol preventing repeated inclusion */ +#define _SYSTEM_MIMX9322_cm33_H_ /**< Symbol preventing repeated inclusion */ #ifdef __cplusplus extern "C" { @@ -88,4 +91,4 @@ void SystemCoreClockUpdate(void); } #endif -#endif /* _SYSTEM_MIMX9322_cm33_H_ */ +#endif /* _SYSTEM_MIMX9322_cm33_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/variable.cmake b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/variable.cmake index e57076d882..f8a0a74bdf 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/variable.cmake +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/variable.cmake @@ -6,6 +6,7 @@ #### chip related include(${SdkRootDirPath}/devices/i.MX/variable.cmake) mcux_set_variable(device MIMX9322) +mcux_set_variable(device_root devices) mcux_set_variable(soc_series i.MX93) mcux_set_variable(soc_periph periph) mcux_set_variable(core_id_suffix_name "_cm33") diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/CMakeLists.txt index 7c9ac554be..bdbcca592e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/CMakeLists.txt @@ -5,7 +5,7 @@ #### device spepcific drivers include(${SdkRootDirPath}/devices/arm/device_header.cmake) -mcux_add_cmakelists(${SdkRootDirPath}/devices/i.MX/i.MX93/MIMX9331/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/i.MX/i.MX93/MIMX9331/drivers) #### i.MX shared drivers/components/middlewares, project segments include(${SdkRootDirPath}/devices/i.MX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33.h index 30eaa93f37..4d84dd6130 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33.h @@ -10,14 +10,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240814 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9331_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -26,14 +26,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9331_cm33.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9331_cm33 * * CMSIS Peripheral Access Layer for MIMX9331_cm33 diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33_COMMON.h index adba896ceb..a0dde74235 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33_COMMON.h @@ -10,14 +10,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240823 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9331_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -26,14 +26,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9331_cm33_COMMON.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9331_cm33 * * CMSIS Peripheral Access Layer for MIMX9331_cm33 @@ -44,7 +47,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U +#define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -377,7 +380,9 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +#ifndef MIMX9331_cm33_SERIES #define MIMX9331_cm33_SERIES +#endif /* CPU specific feature definitions */ #include "MIMX9331_cm33_features.h" @@ -2982,13 +2987,13 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6_NS ((TPM_Type *)TPM6_BASE_NS) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS_NS { TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } + #define TPM_BASE_ADDRS_NS { 0u, TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS_NS { TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } + #define TPM_BASE_PTRS_NS { (TPM_Type *)0u, TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } #else /** Peripheral TPM1 base address */ #define TPM1_BASE (0x44310000u) @@ -3015,12 +3020,12 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6 ((TPM_Type *)TPM6_BASE) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } #endif /** Interrupt vectors for the TPM peripheral type */ -#define TPM_IRQS { TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } +#define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } /* TRDC_MBC0 - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33_features.h index 2a40a53a20..45383ef865 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b241030 +** Build: b250623 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,6 +25,8 @@ /* SOC module features */ +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) /* @brief AXBS availability on the SoC. */ #define FSL_FEATURE_SOC_AXBS_COUNT (1) /* @brief BBNSM availability on the SoC. */ @@ -100,10 +102,17 @@ /* @brief XCACHE availability on the SoC. */ #define FSL_FEATURE_SOC_XCACHE_COUNT (2) +/* ADC module features */ + +/* @brief Channel group counts of ADC. */ +#define FSL_FEATURE_ADC_CHANNEL_GROUPS_COUNT (2) +/* @brief Threshold counts of ADC. */ +#define FSL_FEATURE_ADC_THRESHOLDS_COUNT (8) +/* @brief Self-test threshold counts of ADC. */ +#define FSL_FEATURE_ADC_SELF_TEST_THRESHOLDS_COUNT (6) + /* FLEXCAN module features */ -/* @brief Has more than 64 MBs. */ -#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) /* @brief Message buffer size */ #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (96) /* @brief Has doze mode support (register bit field MCR[DOZE]). */ @@ -152,12 +161,36 @@ #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) /* @brief Has Enhanced Rx FIFO. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (20) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (128) /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (1) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (1) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (1) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (0) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* EDMA module features */ @@ -294,12 +327,14 @@ /* FLEXIO module features */ +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) -/* @brief Has pin input output related registers */ -#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ @@ -316,10 +351,12 @@ #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) /* @brief Reset value of the FLEXIO_PARAM register */ #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808) -/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ -#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Flexio DMA request base channel */ #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* FLEXSPI module features */ @@ -377,6 +414,18 @@ #define FSL_FEATURE_I3C_HAS_HDROK (1) /* @brief SOC doesn't support slave IBI/MR/HJ. */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* XCACHE module features */ @@ -391,6 +440,8 @@ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -403,15 +454,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (1) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (1) /* LPTMR module features */ @@ -497,12 +548,18 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (1) /* @brief Has register Half Duplex Control. */ #define FSL_FEATURE_LPUART_HAS_HDCR (1) /* @brief Has register Timeout. */ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -621,12 +678,16 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) +/* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ +#define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/fsl_device_registers.h index fb1d1615c1..babed49598 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/fsl_device_registers.h @@ -1,6 +1,6 @@ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2024 NXP + * Copyright 2016-2025 NXP * SPDX-License-Identifier: BSD-3-Clause * */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/system_MIMX9331_cm33.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/system_MIMX9331_cm33.c index 166188d161..05ef163740 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/system_MIMX9331_cm33.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/system_MIMX9331_cm33.c @@ -10,8 +10,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -19,7 +19,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -28,10 +28,14 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ + #include "system_MIMX9331_cm33.h" /* ---------------------------------------------------------------------------- @@ -46,11 +50,11 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; void SystemInit(void) { #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ SystemInitHook(); } diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/system_MIMX9331_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/system_MIMX9331_cm33.h index 3d37b8f5f4..eecde79301 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/system_MIMX9331_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/system_MIMX9331_cm33.h @@ -10,8 +10,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -19,7 +19,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -28,12 +28,15 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ #ifndef _SYSTEM_MIMX9331_cm33_H_ -#define _SYSTEM_MIMX9331_cm33_H_ /**< Symbol preventing repeated inclusion */ +#define _SYSTEM_MIMX9331_cm33_H_ /**< Symbol preventing repeated inclusion */ #ifdef __cplusplus extern "C" { @@ -89,4 +92,4 @@ void SystemCoreClockUpdate(void); } #endif -#endif /* _SYSTEM_MIMX9331_cm33_H_ */ +#endif /* _SYSTEM_MIMX9331_cm33_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/variable.cmake b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/variable.cmake index 18327f7670..a4b6f10dda 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/variable.cmake +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/variable.cmake @@ -6,6 +6,7 @@ #### chip related include(${SdkRootDirPath}/devices/i.MX/variable.cmake) mcux_set_variable(device MIMX9331) +mcux_set_variable(device_root devices) mcux_set_variable(soc_series i.MX93) mcux_set_variable(soc_periph periph) mcux_set_variable(core_id_suffix_name "_cm33") diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/CMakeLists.txt index 5041e4f2fb..e40d97986e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/CMakeLists.txt @@ -5,7 +5,7 @@ #### device spepcific drivers include(${SdkRootDirPath}/devices/arm/device_header.cmake) -mcux_add_cmakelists(${SdkRootDirPath}/devices/i.MX/i.MX93/MIMX9332/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/i.MX/i.MX93/MIMX9332/drivers) #### i.MX shared drivers/components/middlewares, project segments include(${SdkRootDirPath}/devices/i.MX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33.h index 2359092103..e463276306 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33.h @@ -10,14 +10,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240814 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9332_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -26,14 +26,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9332_cm33.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9332_cm33 * * CMSIS Peripheral Access Layer for MIMX9332_cm33 diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33_COMMON.h index 9c805e1bae..42dfa431b2 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33_COMMON.h @@ -10,14 +10,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240823 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9332_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -26,14 +26,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9332_cm33_COMMON.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9332_cm33 * * CMSIS Peripheral Access Layer for MIMX9332_cm33 @@ -44,7 +47,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U +#define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -377,7 +380,9 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +#ifndef MIMX9332_cm33_SERIES #define MIMX9332_cm33_SERIES +#endif /* CPU specific feature definitions */ #include "MIMX9332_cm33_features.h" @@ -2982,13 +2987,13 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6_NS ((TPM_Type *)TPM6_BASE_NS) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS_NS { TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } + #define TPM_BASE_ADDRS_NS { 0u, TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS_NS { TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } + #define TPM_BASE_PTRS_NS { (TPM_Type *)0u, TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } #else /** Peripheral TPM1 base address */ #define TPM1_BASE (0x44310000u) @@ -3015,12 +3020,12 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6 ((TPM_Type *)TPM6_BASE) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } #endif /** Interrupt vectors for the TPM peripheral type */ -#define TPM_IRQS { TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } +#define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } /* TRDC_MBC0 - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33_features.h index 9ef59a5999..e5c7f60c8b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b241030 +** Build: b250623 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,6 +25,8 @@ /* SOC module features */ +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) /* @brief AXBS availability on the SoC. */ #define FSL_FEATURE_SOC_AXBS_COUNT (1) /* @brief BBNSM availability on the SoC. */ @@ -100,10 +102,17 @@ /* @brief XCACHE availability on the SoC. */ #define FSL_FEATURE_SOC_XCACHE_COUNT (2) +/* ADC module features */ + +/* @brief Channel group counts of ADC. */ +#define FSL_FEATURE_ADC_CHANNEL_GROUPS_COUNT (2) +/* @brief Threshold counts of ADC. */ +#define FSL_FEATURE_ADC_THRESHOLDS_COUNT (8) +/* @brief Self-test threshold counts of ADC. */ +#define FSL_FEATURE_ADC_SELF_TEST_THRESHOLDS_COUNT (6) + /* FLEXCAN module features */ -/* @brief Has more than 64 MBs. */ -#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) /* @brief Message buffer size */ #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (96) /* @brief Has doze mode support (register bit field MCR[DOZE]). */ @@ -152,12 +161,36 @@ #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) /* @brief Has Enhanced Rx FIFO. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (20) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (128) /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (1) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (1) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (1) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (0) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* EDMA module features */ @@ -294,12 +327,14 @@ /* FLEXIO module features */ +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) -/* @brief Has pin input output related registers */ -#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ @@ -316,10 +351,12 @@ #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) /* @brief Reset value of the FLEXIO_PARAM register */ #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808) -/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ -#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Flexio DMA request base channel */ #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* FLEXSPI module features */ @@ -377,6 +414,18 @@ #define FSL_FEATURE_I3C_HAS_HDROK (1) /* @brief SOC doesn't support slave IBI/MR/HJ. */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* XCACHE module features */ @@ -391,6 +440,8 @@ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -403,15 +454,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (1) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (1) /* LPTMR module features */ @@ -497,12 +548,18 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (1) /* @brief Has register Half Duplex Control. */ #define FSL_FEATURE_LPUART_HAS_HDCR (1) /* @brief Has register Timeout. */ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -621,12 +678,16 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) +/* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ +#define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/fsl_device_registers.h index 8c2d358bf5..c4d0655e6c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/fsl_device_registers.h @@ -1,6 +1,6 @@ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2024 NXP + * Copyright 2016-2025 NXP * SPDX-License-Identifier: BSD-3-Clause * */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/system_MIMX9332_cm33.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/system_MIMX9332_cm33.c index d345395e18..2b5f0c3577 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/system_MIMX9332_cm33.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/system_MIMX9332_cm33.c @@ -10,8 +10,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -19,7 +19,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -28,10 +28,14 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ + #include "system_MIMX9332_cm33.h" /* ---------------------------------------------------------------------------- @@ -46,11 +50,11 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; void SystemInit(void) { #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ SystemInitHook(); } diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/system_MIMX9332_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/system_MIMX9332_cm33.h index 7a28ac977c..fcfd122a9e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/system_MIMX9332_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/system_MIMX9332_cm33.h @@ -10,8 +10,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -19,7 +19,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -28,12 +28,15 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ #ifndef _SYSTEM_MIMX9332_cm33_H_ -#define _SYSTEM_MIMX9332_cm33_H_ /**< Symbol preventing repeated inclusion */ +#define _SYSTEM_MIMX9332_cm33_H_ /**< Symbol preventing repeated inclusion */ #ifdef __cplusplus extern "C" { @@ -89,4 +92,4 @@ void SystemCoreClockUpdate(void); } #endif -#endif /* _SYSTEM_MIMX9332_cm33_H_ */ +#endif /* _SYSTEM_MIMX9332_cm33_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/variable.cmake b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/variable.cmake index 4c9598b722..fb2a728645 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/variable.cmake +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/variable.cmake @@ -6,6 +6,7 @@ #### chip related include(${SdkRootDirPath}/devices/i.MX/variable.cmake) mcux_set_variable(device MIMX9332) +mcux_set_variable(device_root devices) mcux_set_variable(soc_series i.MX93) mcux_set_variable(soc_periph periph) mcux_set_variable(core_id_suffix_name "_cm33") diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/CMakeLists.txt index 891bf028f1..42dbea09b7 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/CMakeLists.txt @@ -5,7 +5,7 @@ #### device spepcific drivers include(${SdkRootDirPath}/devices/arm/device_header.cmake) -mcux_add_cmakelists(${SdkRootDirPath}/devices/i.MX/i.MX93/MIMX9351/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/i.MX/i.MX93/MIMX9351/drivers) #### i.MX shared drivers/components/middlewares, project segments include(${SdkRootDirPath}/devices/i.MX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33.h index a77fe2e929..158136d726 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33.h @@ -10,14 +10,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240814 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9351_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -26,14 +26,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9351_cm33.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9351_cm33 * * CMSIS Peripheral Access Layer for MIMX9351_cm33 diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33_COMMON.h index 6e96903c89..c2dfa6c9ef 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33_COMMON.h @@ -10,14 +10,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240823 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9351_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -26,14 +26,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9351_cm33_COMMON.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9351_cm33 * * CMSIS Peripheral Access Layer for MIMX9351_cm33 @@ -44,7 +47,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U +#define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -377,7 +380,9 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +#ifndef MIMX9351_cm33_SERIES #define MIMX9351_cm33_SERIES +#endif /* CPU specific feature definitions */ #include "MIMX9351_cm33_features.h" @@ -2982,13 +2987,13 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6_NS ((TPM_Type *)TPM6_BASE_NS) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS_NS { TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } + #define TPM_BASE_ADDRS_NS { 0u, TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS_NS { TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } + #define TPM_BASE_PTRS_NS { (TPM_Type *)0u, TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } #else /** Peripheral TPM1 base address */ #define TPM1_BASE (0x44310000u) @@ -3015,12 +3020,12 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6 ((TPM_Type *)TPM6_BASE) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } #endif /** Interrupt vectors for the TPM peripheral type */ -#define TPM_IRQS { TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } +#define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } /* TRDC_MBC0 - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33_features.h index bd9e036089..7b53b92773 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b241030 +** Build: b250623 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,6 +25,8 @@ /* SOC module features */ +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) /* @brief AXBS availability on the SoC. */ #define FSL_FEATURE_SOC_AXBS_COUNT (1) /* @brief BBNSM availability on the SoC. */ @@ -100,10 +102,17 @@ /* @brief XCACHE availability on the SoC. */ #define FSL_FEATURE_SOC_XCACHE_COUNT (2) +/* ADC module features */ + +/* @brief Channel group counts of ADC. */ +#define FSL_FEATURE_ADC_CHANNEL_GROUPS_COUNT (2) +/* @brief Threshold counts of ADC. */ +#define FSL_FEATURE_ADC_THRESHOLDS_COUNT (8) +/* @brief Self-test threshold counts of ADC. */ +#define FSL_FEATURE_ADC_SELF_TEST_THRESHOLDS_COUNT (6) + /* FLEXCAN module features */ -/* @brief Has more than 64 MBs. */ -#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) /* @brief Message buffer size */ #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (96) /* @brief Has doze mode support (register bit field MCR[DOZE]). */ @@ -152,12 +161,36 @@ #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) /* @brief Has Enhanced Rx FIFO. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (20) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (128) /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (1) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (1) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (1) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (0) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* EDMA module features */ @@ -294,12 +327,14 @@ /* FLEXIO module features */ +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) -/* @brief Has pin input output related registers */ -#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ @@ -316,10 +351,12 @@ #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) /* @brief Reset value of the FLEXIO_PARAM register */ #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808) -/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ -#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Flexio DMA request base channel */ #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* FLEXSPI module features */ @@ -377,6 +414,18 @@ #define FSL_FEATURE_I3C_HAS_HDROK (1) /* @brief SOC doesn't support slave IBI/MR/HJ. */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* XCACHE module features */ @@ -391,6 +440,8 @@ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -403,15 +454,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (1) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (1) /* LPTMR module features */ @@ -497,12 +548,18 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (1) /* @brief Has register Half Duplex Control. */ #define FSL_FEATURE_LPUART_HAS_HDCR (1) /* @brief Has register Timeout. */ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -621,12 +678,16 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) +/* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ +#define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/fsl_device_registers.h index f49b958875..7d1bd545da 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/fsl_device_registers.h @@ -1,6 +1,6 @@ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2024 NXP + * Copyright 2016-2025 NXP * SPDX-License-Identifier: BSD-3-Clause * */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/system_MIMX9351_cm33.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/system_MIMX9351_cm33.c index 95eb978d6b..fd0703ca45 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/system_MIMX9351_cm33.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/system_MIMX9351_cm33.c @@ -10,8 +10,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -19,7 +19,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -28,10 +28,14 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ + #include "system_MIMX9351_cm33.h" /* ---------------------------------------------------------------------------- @@ -46,11 +50,11 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; void SystemInit(void) { #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ SystemInitHook(); } diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/system_MIMX9351_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/system_MIMX9351_cm33.h index 2d19cf7480..186cef9b4a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/system_MIMX9351_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/system_MIMX9351_cm33.h @@ -10,8 +10,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -19,7 +19,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -28,12 +28,15 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ #ifndef _SYSTEM_MIMX9351_cm33_H_ -#define _SYSTEM_MIMX9351_cm33_H_ /**< Symbol preventing repeated inclusion */ +#define _SYSTEM_MIMX9351_cm33_H_ /**< Symbol preventing repeated inclusion */ #ifdef __cplusplus extern "C" { @@ -89,4 +92,4 @@ void SystemCoreClockUpdate(void); } #endif -#endif /* _SYSTEM_MIMX9351_cm33_H_ */ +#endif /* _SYSTEM_MIMX9351_cm33_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/variable.cmake b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/variable.cmake index 5b628bb6d5..27163944ec 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/variable.cmake +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/variable.cmake @@ -6,6 +6,7 @@ #### chip related include(${SdkRootDirPath}/devices/i.MX/variable.cmake) mcux_set_variable(device MIMX9351) +mcux_set_variable(device_root devices) mcux_set_variable(soc_series i.MX93) mcux_set_variable(soc_periph periph) mcux_set_variable(core_id_suffix_name "_cm33") diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/CMakeLists.txt index 6016982ff0..9bcfd4dce4 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/CMakeLists.txt @@ -5,7 +5,7 @@ #### device spepcific drivers include(${SdkRootDirPath}/devices/arm/device_header.cmake) -mcux_add_cmakelists(${SdkRootDirPath}/devices/i.MX/i.MX93/MIMX9352/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/i.MX/i.MX93/MIMX9352/drivers) #### i.MX shared drivers/components/middlewares, project segments include(${SdkRootDirPath}/devices/i.MX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33.h index 5622124788..6246071aaf 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33.h @@ -10,14 +10,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240814 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9352_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -26,14 +26,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9352_cm33.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9352_cm33 * * CMSIS Peripheral Access Layer for MIMX9352_cm33 diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33_COMMON.h index efc5efe0b8..f201891f7b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33_COMMON.h @@ -10,14 +10,14 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b240823 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9352_cm33 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -26,14 +26,17 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX9352_cm33_COMMON.h - * @version 1.0 - * @date 2021-11-16 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX9352_cm33 * * CMSIS Peripheral Access Layer for MIMX9352_cm33 @@ -44,7 +47,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U +#define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -377,7 +380,9 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +#ifndef MIMX9352_cm33_SERIES #define MIMX9352_cm33_SERIES +#endif /* CPU specific feature definitions */ #include "MIMX9352_cm33_features.h" @@ -2982,13 +2987,13 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6_NS ((TPM_Type *)TPM6_BASE_NS) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS_NS { TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } + #define TPM_BASE_ADDRS_NS { 0u, TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS, TPM4_BASE_NS, TPM5_BASE_NS, TPM6_BASE_NS } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS_NS { TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } + #define TPM_BASE_PTRS_NS { (TPM_Type *)0u, TPM1_NS, TPM2_NS, TPM3_NS, TPM4_NS, TPM5_NS, TPM6_NS } #else /** Peripheral TPM1 base address */ #define TPM1_BASE (0x44310000u) @@ -3015,12 +3020,12 @@ typedef enum IRQn { /** Peripheral TPM6 base pointer */ #define TPM6 ((TPM_Type *)TPM6_BASE) /** Array initializer of TPM peripheral base addresses */ - #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } + #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ - #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } + #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } #endif /** Interrupt vectors for the TPM peripheral type */ -#define TPM_IRQS { TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } +#define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } /* TRDC_MBC0 - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33_features.h index 097ed64e8c..6df740e81c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b241030 +** Build: b250623 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -25,6 +25,8 @@ /* SOC module features */ +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) /* @brief AXBS availability on the SoC. */ #define FSL_FEATURE_SOC_AXBS_COUNT (1) /* @brief BBNSM availability on the SoC. */ @@ -100,10 +102,17 @@ /* @brief XCACHE availability on the SoC. */ #define FSL_FEATURE_SOC_XCACHE_COUNT (2) +/* ADC module features */ + +/* @brief Channel group counts of ADC. */ +#define FSL_FEATURE_ADC_CHANNEL_GROUPS_COUNT (2) +/* @brief Threshold counts of ADC. */ +#define FSL_FEATURE_ADC_THRESHOLDS_COUNT (8) +/* @brief Self-test threshold counts of ADC. */ +#define FSL_FEATURE_ADC_SELF_TEST_THRESHOLDS_COUNT (6) + /* FLEXCAN module features */ -/* @brief Has more than 64 MBs. */ -#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) /* @brief Message buffer size */ #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (96) /* @brief Has doze mode support (register bit field MCR[DOZE]). */ @@ -152,12 +161,36 @@ #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) /* @brief Has Enhanced Rx FIFO. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (20) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (128) /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (1) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (1) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (1) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (0) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* EDMA module features */ @@ -294,12 +327,14 @@ /* FLEXIO module features */ +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) -/* @brief Has pin input output related registers */ -#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ @@ -316,10 +351,12 @@ #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) /* @brief Reset value of the FLEXIO_PARAM register */ #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808) -/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ -#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Flexio DMA request base channel */ #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* FLEXSPI module features */ @@ -377,6 +414,18 @@ #define FSL_FEATURE_I3C_HAS_HDROK (1) /* @brief SOC doesn't support slave IBI/MR/HJ. */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* XCACHE module features */ @@ -391,6 +440,8 @@ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -403,15 +454,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (1) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (1) /* LPTMR module features */ @@ -497,12 +548,18 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (1) /* @brief Has register Half Duplex Control. */ #define FSL_FEATURE_LPUART_HAS_HDCR (1) /* @brief Has register Timeout. */ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -621,12 +678,16 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) +/* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ +#define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/drivers/fsl_clock.h index 44ab6e24b0..c88950d574 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/drivers/fsl_clock.h @@ -999,6 +999,12 @@ typedef enum _clock_lpcg #define clock_ip_name_t clock_lpcg_t +/*! @brief Clock ip name array for ADC. */ +#define ADC_CLOCKS \ + { \ + kCLOCK_Adc1 \ + } + /*! @brief Clock ip name array for EDMA. */ #define EDMA_CLOCKS \ { \ @@ -1041,9 +1047,9 @@ typedef enum _clock_lpcg } /*! @brief Clock ip name array for TPM. */ -#define TPM_CLOCKS \ - { \ - kCLOCK_Tpm1, kCLOCK_Tpm2, kCLOCK_Tpm3, kCLOCK_Tpm4, kCLOCK_Tpm5, kCLOCK_Tpm6, \ +#define TPM_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Tpm1, kCLOCK_Tpm2, kCLOCK_Tpm3, kCLOCK_Tpm4, kCLOCK_Tpm5, kCLOCK_Tpm6, \ } /*! @brief Clock ip name array for FLEXIO. */ @@ -1089,6 +1095,12 @@ typedef enum _clock_lpcg kCLOCK_Pdm \ } +/*! @brief Clock ip name array for USDHC. */ +#define USDHC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2, kCLOCK_Usdhc3 \ + } + /*! @brief Clock ip name array for ENET QOS. */ #define ENETQOS_CLOCKS \ { \ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/drivers/fsl_sentinel.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/drivers/fsl_sentinel.c index b94c8f1086..3c4504c027 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/drivers/fsl_sentinel.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/drivers/fsl_sentinel.c @@ -5,7 +5,6 @@ */ #include "fsl_sentinel.h" -#include "fsl_debug_console.h" #ifdef FSL_RTOS_FREE_RTOS #include "FreeRTOS.h" #include "task.h" @@ -542,38 +541,6 @@ uint32_t SENTINEL_RngGetRandom(uint32_t *pRngHandle, uint32_t outAddr, uint32_t return respParam.rsp.rsp_code.bridge_rsp_code.status; } -uint32_t SENTINEL_DumpDebugBuffer(void) -{ - struct dump_debug_buffer_msg_cmd cmdParam; - struct dump_debug_buffer_msg_cmd_rsp respParam; - uint32_t respParamCount = sizeof(respParam) / sizeof(uint32_t); - - (void)memset((void *)&cmdParam, 0, sizeof(cmdParam)); - cmdParam.hdr.cmd = SENTINEL_BASELINE_API_CMD_DUMP_DEBUG_BUFFER; - cmdParam.hdr.tag = SENTINEL_MSG_HDR_CMD_TAG; - cmdParam.hdr.size = sizeof(cmdParam) / sizeof(uint32_t); - cmdParam.hdr.ver = SENTINEL_BASELINE_API_VER; - - (void)SENTINEL_Command((uint32_t *)(void *)&cmdParam, sizeof(cmdParam) / sizeof(uint32_t), - (uint32_t *)(void *)&respParam, &respParamCount); - assert(respParamCount > 0U); - - if (respParam.rsp.rsp_code.baseline_rsp_code.status == BASELINE_SUCCESS_IND) /* Successful */ - { - uint32_t i = 0U; - assert(respParamCount == sizeof(respParam) / sizeof(uint32_t)); - for (i = 0U; i < sizeof(respParam.debug_words) / sizeof(uint32_t); i++) - { - (void)PRINTF("\r\n respParam.debug_words[%d] = 0x%x\r\n", i, respParam.debug_words[i]); - } - } - else - { - } - - return respParam.rsp.rsp_code.baseline_rsp_code.status; -} - status_t SENTINEL_RNG_GetRandomData(uint32_t output, uint32_t len) { uint32_t sessionHandle = 0; diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/drivers/fsl_sentinel.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/drivers/fsl_sentinel.h index 9013793c6e..969f112421 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/drivers/fsl_sentinel.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/drivers/fsl_sentinel.h @@ -365,8 +365,6 @@ uint32_t SENTINEL_RngClose(uint32_t *pRngHandle); uint32_t SENTINEL_RngGetRandom(uint32_t *pRngHandle, uint32_t outAddr, uint32_t outSize); -uint32_t SENTINEL_DumpDebugBuffer(void); - status_t SENTINEL_RNG_GetRandomData(uint32_t output, uint32_t len); uint32_t SENTINEL_ReleaseRDC(enum rdc_type type); diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/fsl_device_registers.h index ce7dfcd195..f9df37e69c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/fsl_device_registers.h @@ -1,6 +1,6 @@ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2024 NXP + * Copyright 2016-2025 NXP * SPDX-License-Identifier: BSD-3-Clause * */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/system_MIMX9352_cm33.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/system_MIMX9352_cm33.c index 34c50a2d78..b31c35403f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/system_MIMX9352_cm33.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/system_MIMX9352_cm33.c @@ -10,8 +10,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -19,7 +19,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -28,10 +28,14 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ + #include "system_MIMX9352_cm33.h" /* ---------------------------------------------------------------------------- @@ -46,11 +50,11 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; void SystemInit(void) { #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ SystemInitHook(); } diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/system_MIMX9352_cm33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/system_MIMX9352_cm33.h index 4b573cd800..2f0ec040ec 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/system_MIMX9352_cm33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/system_MIMX9352_cm33.h @@ -10,8 +10,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX93RM, Internal, November. 2021 -** Version: rev. 1.0, 2021-11-16 -** Build: b231019 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -19,7 +19,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -28,12 +28,15 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ #ifndef _SYSTEM_MIMX9352_cm33_H_ -#define _SYSTEM_MIMX9352_cm33_H_ /**< Symbol preventing repeated inclusion */ +#define _SYSTEM_MIMX9352_cm33_H_ /**< Symbol preventing repeated inclusion */ #ifdef __cplusplus extern "C" { @@ -89,4 +92,4 @@ void SystemCoreClockUpdate(void); } #endif -#endif /* _SYSTEM_MIMX9352_cm33_H_ */ +#endif /* _SYSTEM_MIMX9352_cm33_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/variable.cmake b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/variable.cmake index 403adf104d..898878e41f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/variable.cmake +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/variable.cmake @@ -6,6 +6,7 @@ #### chip related include(${SdkRootDirPath}/devices/i.MX/variable.cmake) mcux_set_variable(device MIMX9352) +mcux_set_variable(device_root devices) mcux_set_variable(soc_series i.MX93) mcux_set_variable(soc_periph periph) mcux_set_variable(core_id_suffix_name "_cm33") diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ADC.h index cffb8a0349..8c6d311db7 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ADC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ADC.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240814 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ADC.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_ADC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ADC * * CMSIS Peripheral Access Layer for ADC */ -#if !defined(ADC_H_) -#define ADC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ADC_H_) +#define PERI_ADC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -421,10 +424,10 @@ typedef struct { /*! ADCSTATUS - ADC Status * 0b000..Idle * 0b001..Power-down - * 0b100..Sample - * 0b110..Conversion * 0b010..Wait state (waiting to start conversion after [external trigger]). * 0b011..Busy in calibration + * 0b100..Sample + * 0b110..Conversion */ #define ADC_MSR_ADCSTATUS(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_ADCSTATUS_SHIFT)) & ADC_MSR_ADCSTATUS_MASK) @@ -502,8 +505,8 @@ typedef struct { #define ADC_MSR_CALFAIL_SHIFT (30U) /*! CALFAIL - Calibration Failed * 0b0..Calibration passed (must be checked with CALBUSY = 0b) - * 0b1..Calibration failed * 0b0..No effect + * 0b1..Calibration failed * 0b1..Clear the flag */ #define ADC_MSR_CALFAIL(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CALFAIL_SHIFT)) & ADC_MSR_CALFAIL_MASK) @@ -524,9 +527,9 @@ typedef struct { #define ADC_ISR_ECH_SHIFT (0U) /*! ECH - End of Conversion Chain * 0b0..End of conversion chain has not occurred - * 0b1..End of conversion chain has occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..End of conversion chain has occurred */ #define ADC_ISR_ECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_ECH_SHIFT)) & ADC_ISR_ECH_MASK) @@ -534,8 +537,8 @@ typedef struct { #define ADC_ISR_EOC_SHIFT (1U) /*! EOC - End of Channel Conversion * 0b0..Channel end of conversion has not occurred - * 0b1..Channel end of conversion has occurred * 0b0..No effect + * 0b1..Channel end of conversion has occurred * 0b1..Clear the flag */ #define ADC_ISR_EOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_EOC_SHIFT)) & ADC_ISR_EOC_MASK) @@ -544,9 +547,9 @@ typedef struct { #define ADC_ISR_JECH_SHIFT (2U) /*! JECH - Injected End of Conversion Chain * 0b0..Injected channel end of conversion chain has not occurred - * 0b1..Injected channel end of conversion chain has occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..Injected channel end of conversion chain has occurred */ #define ADC_ISR_JECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_JECH_SHIFT)) & ADC_ISR_JECH_MASK) @@ -554,9 +557,9 @@ typedef struct { #define ADC_ISR_JEOC_SHIFT (3U) /*! JEOC - Injected Channel End of Conversion * 0b0..Injected channel end of conversion has not occurred - * 0b1..Injected channel end of conversion has occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..Injected channel end of conversion has occurred */ #define ADC_ISR_JEOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_JEOC_SHIFT)) & ADC_ISR_JEOC_MASK) /*! @} */ @@ -568,9 +571,9 @@ typedef struct { #define ADC_CEOCFR0_EOC_CH0_SHIFT (0U) /*! EOC_CH0 - Channel 0 EOC Status * 0b0..Conversion not complete - * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag + * 0b1..Conversion complete */ #define ADC_CEOCFR0_EOC_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH0_SHIFT)) & ADC_CEOCFR0_EOC_CH0_MASK) @@ -578,9 +581,9 @@ typedef struct { #define ADC_CEOCFR0_EOC_CH1_SHIFT (1U) /*! EOC_CH1 - Channel 1 EOC Status * 0b0..Conversion not complete - * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag + * 0b1..Conversion complete */ #define ADC_CEOCFR0_EOC_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH1_SHIFT)) & ADC_CEOCFR0_EOC_CH1_MASK) @@ -588,9 +591,9 @@ typedef struct { #define ADC_CEOCFR0_EOC_CH2_SHIFT (2U) /*! EOC_CH2 - Channel 2 EOC Status * 0b0..Conversion not complete - * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag + * 0b1..Conversion complete */ #define ADC_CEOCFR0_EOC_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH2_SHIFT)) & ADC_CEOCFR0_EOC_CH2_MASK) @@ -598,9 +601,9 @@ typedef struct { #define ADC_CEOCFR0_EOC_CH3_SHIFT (3U) /*! EOC_CH3 - Channel 3 EOC Status * 0b0..Conversion not complete - * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag + * 0b1..Conversion complete */ #define ADC_CEOCFR0_EOC_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH3_SHIFT)) & ADC_CEOCFR0_EOC_CH3_MASK) @@ -608,9 +611,9 @@ typedef struct { #define ADC_CEOCFR0_EOC_CH4_SHIFT (4U) /*! EOC_CH4 - Channel 4 EOC Status * 0b0..Conversion not complete - * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag + * 0b1..Conversion complete */ #define ADC_CEOCFR0_EOC_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH4_SHIFT)) & ADC_CEOCFR0_EOC_CH4_MASK) @@ -618,9 +621,9 @@ typedef struct { #define ADC_CEOCFR0_EOC_CH5_SHIFT (5U) /*! EOC_CH5 - Channel 5 EOC Status * 0b0..Conversion not complete - * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag + * 0b1..Conversion complete */ #define ADC_CEOCFR0_EOC_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH5_SHIFT)) & ADC_CEOCFR0_EOC_CH5_MASK) @@ -628,9 +631,9 @@ typedef struct { #define ADC_CEOCFR0_EOC_CH6_SHIFT (6U) /*! EOC_CH6 - Channel 6 EOC Status * 0b0..Conversion not complete - * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag + * 0b1..Conversion complete */ #define ADC_CEOCFR0_EOC_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH6_SHIFT)) & ADC_CEOCFR0_EOC_CH6_MASK) @@ -638,9 +641,9 @@ typedef struct { #define ADC_CEOCFR0_EOC_CH7_SHIFT (7U) /*! EOC_CH7 - Channel 7 EOC Status * 0b0..Conversion not complete - * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag + * 0b1..Conversion complete */ #define ADC_CEOCFR0_EOC_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH7_SHIFT)) & ADC_CEOCFR0_EOC_CH7_MASK) /*! @} */ @@ -652,9 +655,9 @@ typedef struct { #define ADC_CEOCFR1_EOC_CH32_SHIFT (0U) /*! EOC_CH32 - Channel 32 EOC Status * 0b0..Conversion not complete - * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag + * 0b1..Conversion complete */ #define ADC_CEOCFR1_EOC_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH32_SHIFT)) & ADC_CEOCFR1_EOC_CH32_MASK) @@ -662,9 +665,9 @@ typedef struct { #define ADC_CEOCFR1_EOC_CH33_SHIFT (1U) /*! EOC_CH33 - Channel 33 EOC Status * 0b0..Conversion not complete - * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag + * 0b1..Conversion complete */ #define ADC_CEOCFR1_EOC_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH33_SHIFT)) & ADC_CEOCFR1_EOC_CH33_MASK) @@ -672,9 +675,9 @@ typedef struct { #define ADC_CEOCFR1_EOC_CH34_SHIFT (2U) /*! EOC_CH34 - Channel 34 EOC Status * 0b0..Conversion not complete - * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag + * 0b1..Conversion complete */ #define ADC_CEOCFR1_EOC_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH34_SHIFT)) & ADC_CEOCFR1_EOC_CH34_MASK) @@ -682,9 +685,9 @@ typedef struct { #define ADC_CEOCFR1_EOC_CH35_SHIFT (3U) /*! EOC_CH35 - Channel 35 EOC Status * 0b0..Conversion not complete - * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag + * 0b1..Conversion complete */ #define ADC_CEOCFR1_EOC_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH35_SHIFT)) & ADC_CEOCFR1_EOC_CH35_MASK) @@ -692,9 +695,9 @@ typedef struct { #define ADC_CEOCFR1_EOC_CH36_SHIFT (4U) /*! EOC_CH36 - Channel 36 EOC Status * 0b0..Conversion not complete - * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag + * 0b1..Conversion complete */ #define ADC_CEOCFR1_EOC_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH36_SHIFT)) & ADC_CEOCFR1_EOC_CH36_MASK) @@ -702,9 +705,9 @@ typedef struct { #define ADC_CEOCFR1_EOC_CH37_SHIFT (5U) /*! EOC_CH37 - Channel 37 EOC Status * 0b0..Conversion not complete - * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag + * 0b1..Conversion complete */ #define ADC_CEOCFR1_EOC_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH37_SHIFT)) & ADC_CEOCFR1_EOC_CH37_MASK) @@ -712,9 +715,9 @@ typedef struct { #define ADC_CEOCFR1_EOC_CH38_SHIFT (6U) /*! EOC_CH38 - Channel 38 EOC Status * 0b0..Conversion not complete - * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag + * 0b1..Conversion complete */ #define ADC_CEOCFR1_EOC_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH38_SHIFT)) & ADC_CEOCFR1_EOC_CH38_MASK) @@ -722,9 +725,9 @@ typedef struct { #define ADC_CEOCFR1_EOC_CH39_SHIFT (7U) /*! EOC_CH39 - Channel 39 EOC Status * 0b0..Conversion not complete - * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag + * 0b1..Conversion complete */ #define ADC_CEOCFR1_EOC_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH39_SHIFT)) & ADC_CEOCFR1_EOC_CH39_MASK) /*! @} */ @@ -908,9 +911,9 @@ typedef struct { #define ADC_WTISR_WDG0L_SHIFT (0U) /*! WDG0L - Channel 0 Watchdog Low Threshold Interrupt * 0b0..Interrupt not asserted - * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt asserted */ #define ADC_WTISR_WDG0L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG0L_SHIFT)) & ADC_WTISR_WDG0L_MASK) @@ -918,9 +921,9 @@ typedef struct { #define ADC_WTISR_WDG0H_SHIFT (1U) /*! WDG0H - Channel 0 Watchdog High Threshold Interrupt * 0b0..Interrupt not asserted - * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt asserted */ #define ADC_WTISR_WDG0H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG0H_SHIFT)) & ADC_WTISR_WDG0H_MASK) @@ -928,9 +931,9 @@ typedef struct { #define ADC_WTISR_WDG1L_SHIFT (2U) /*! WDG1L - Channel 1 Watchdog Low Threshold Interrupt * 0b0..Interrupt not asserted - * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt asserted */ #define ADC_WTISR_WDG1L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG1L_SHIFT)) & ADC_WTISR_WDG1L_MASK) @@ -938,9 +941,9 @@ typedef struct { #define ADC_WTISR_WDG1H_SHIFT (3U) /*! WDG1H - Channel 1 Watchdog High Threshold Interrupt * 0b0..Interrupt not asserted - * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt asserted */ #define ADC_WTISR_WDG1H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG1H_SHIFT)) & ADC_WTISR_WDG1H_MASK) @@ -948,9 +951,9 @@ typedef struct { #define ADC_WTISR_WDG2L_SHIFT (4U) /*! WDG2L - Channel 2 Watchdog Low Threshold Interrupt * 0b0..Interrupt not asserted - * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt asserted */ #define ADC_WTISR_WDG2L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG2L_SHIFT)) & ADC_WTISR_WDG2L_MASK) @@ -958,9 +961,9 @@ typedef struct { #define ADC_WTISR_WDG2H_SHIFT (5U) /*! WDG2H - Channel 2 Watchdog High Threshold Interrupt * 0b0..Interrupt not asserted - * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt asserted */ #define ADC_WTISR_WDG2H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG2H_SHIFT)) & ADC_WTISR_WDG2H_MASK) @@ -968,9 +971,9 @@ typedef struct { #define ADC_WTISR_WDG3L_SHIFT (6U) /*! WDG3L - Channel 3 Watchdog Low Threshold Interrupt * 0b0..Interrupt not asserted - * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt asserted */ #define ADC_WTISR_WDG3L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG3L_SHIFT)) & ADC_WTISR_WDG3L_MASK) @@ -978,9 +981,9 @@ typedef struct { #define ADC_WTISR_WDG3H_SHIFT (7U) /*! WDG3H - Channel 3 Watchdog High Threshold Interrupt * 0b0..Interrupt not asserted - * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt asserted */ #define ADC_WTISR_WDG3H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG3H_SHIFT)) & ADC_WTISR_WDG3H_MASK) @@ -988,9 +991,9 @@ typedef struct { #define ADC_WTISR_WDG4L_SHIFT (8U) /*! WDG4L - Channel 4 Watchdog Low Threshold Interrupt * 0b0..Interrupt not asserted - * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt asserted */ #define ADC_WTISR_WDG4L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG4L_SHIFT)) & ADC_WTISR_WDG4L_MASK) @@ -998,9 +1001,9 @@ typedef struct { #define ADC_WTISR_WDG4H_SHIFT (9U) /*! WDG4H - Channel 4 Watchdog High Threshold Interrupt * 0b0..Interrupt not asserted - * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt asserted */ #define ADC_WTISR_WDG4H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG4H_SHIFT)) & ADC_WTISR_WDG4H_MASK) @@ -1008,9 +1011,9 @@ typedef struct { #define ADC_WTISR_WDG5L_SHIFT (10U) /*! WDG5L - Channel 5 Watchdog Low Threshold Interrupt * 0b0..Interrupt not asserted - * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt asserted */ #define ADC_WTISR_WDG5L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG5L_SHIFT)) & ADC_WTISR_WDG5L_MASK) @@ -1018,9 +1021,9 @@ typedef struct { #define ADC_WTISR_WDG5H_SHIFT (11U) /*! WDG5H - Channel 5 Watchdog High Threshold Interrupt * 0b0..Interrupt not asserted - * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt asserted */ #define ADC_WTISR_WDG5H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG5H_SHIFT)) & ADC_WTISR_WDG5H_MASK) @@ -1028,9 +1031,9 @@ typedef struct { #define ADC_WTISR_WDG6L_SHIFT (12U) /*! WDG6L - Channel 6 Watchdog Low Threshold Interrupt * 0b0..Interrupt not asserted - * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt asserted */ #define ADC_WTISR_WDG6L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG6L_SHIFT)) & ADC_WTISR_WDG6L_MASK) @@ -1038,9 +1041,9 @@ typedef struct { #define ADC_WTISR_WDG6H_SHIFT (13U) /*! WDG6H - Channel 6 Watchdog High Threshold Interrupt * 0b0..Interrupt not asserted - * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt asserted */ #define ADC_WTISR_WDG6H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG6H_SHIFT)) & ADC_WTISR_WDG6H_MASK) @@ -1048,9 +1051,9 @@ typedef struct { #define ADC_WTISR_WDG7L_SHIFT (14U) /*! WDG7L - Channel 7 Watchdog Low Threshold Interrupt * 0b0..Interrupt not asserted - * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt asserted */ #define ADC_WTISR_WDG7L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG7L_SHIFT)) & ADC_WTISR_WDG7L_MASK) @@ -1058,9 +1061,9 @@ typedef struct { #define ADC_WTISR_WDG7H_SHIFT (15U) /*! WDG7H - Channel 7 Watchdog High Threshold Interrupt * 0b0..Interrupt not asserted - * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt asserted */ #define ADC_WTISR_WDG7H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG7H_SHIFT)) & ADC_WTISR_WDG7H_MASK) /*! @} */ @@ -2243,9 +2246,9 @@ typedef struct { #define ADC_AWORR0_AWOR_CH0_SHIFT (0U) /*! AWOR_CH0 - Analog Watchdog Out of Range for Channel 0 * 0b0..Converted data is in range - * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag + * 0b1..Converted data is out of range */ #define ADC_AWORR0_AWOR_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH0_SHIFT)) & ADC_AWORR0_AWOR_CH0_MASK) @@ -2253,9 +2256,9 @@ typedef struct { #define ADC_AWORR0_AWOR_CH1_SHIFT (1U) /*! AWOR_CH1 - Analog Watchdog Out of Range for Channel 1 * 0b0..Converted data is in range - * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag + * 0b1..Converted data is out of range */ #define ADC_AWORR0_AWOR_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH1_SHIFT)) & ADC_AWORR0_AWOR_CH1_MASK) @@ -2263,9 +2266,9 @@ typedef struct { #define ADC_AWORR0_AWOR_CH2_SHIFT (2U) /*! AWOR_CH2 - Analog Watchdog Out of Range for Channel 2 * 0b0..Converted data is in range - * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag + * 0b1..Converted data is out of range */ #define ADC_AWORR0_AWOR_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH2_SHIFT)) & ADC_AWORR0_AWOR_CH2_MASK) @@ -2273,9 +2276,9 @@ typedef struct { #define ADC_AWORR0_AWOR_CH3_SHIFT (3U) /*! AWOR_CH3 - Analog Watchdog Out of Range for Channel 3 * 0b0..Converted data is in range - * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag + * 0b1..Converted data is out of range */ #define ADC_AWORR0_AWOR_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH3_SHIFT)) & ADC_AWORR0_AWOR_CH3_MASK) @@ -2283,9 +2286,9 @@ typedef struct { #define ADC_AWORR0_AWOR_CH4_SHIFT (4U) /*! AWOR_CH4 - Analog Watchdog Out of Range for Channel 4 * 0b0..Converted data is in range - * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag + * 0b1..Converted data is out of range */ #define ADC_AWORR0_AWOR_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH4_SHIFT)) & ADC_AWORR0_AWOR_CH4_MASK) @@ -2293,9 +2296,9 @@ typedef struct { #define ADC_AWORR0_AWOR_CH5_SHIFT (5U) /*! AWOR_CH5 - Analog Watchdog Out of Range for Channel 5 * 0b0..Converted data is in range - * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag + * 0b1..Converted data is out of range */ #define ADC_AWORR0_AWOR_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH5_SHIFT)) & ADC_AWORR0_AWOR_CH5_MASK) @@ -2303,9 +2306,9 @@ typedef struct { #define ADC_AWORR0_AWOR_CH6_SHIFT (6U) /*! AWOR_CH6 - Analog Watchdog Out of Range for Channel 6 * 0b0..Converted data is in range - * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag + * 0b1..Converted data is out of range */ #define ADC_AWORR0_AWOR_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH6_SHIFT)) & ADC_AWORR0_AWOR_CH6_MASK) @@ -2313,9 +2316,9 @@ typedef struct { #define ADC_AWORR0_AWOR_CH7_SHIFT (7U) /*! AWOR_CH7 - Analog Watchdog Out of Range for Channel 7 * 0b0..Converted data is in range - * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag + * 0b1..Converted data is out of range */ #define ADC_AWORR0_AWOR_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH7_SHIFT)) & ADC_AWORR0_AWOR_CH7_MASK) /*! @} */ @@ -2327,9 +2330,9 @@ typedef struct { #define ADC_AWORR1_AWOR_CH32_SHIFT (0U) /*! AWOR_CH32 - Analog Watchdog Out of Range for Channel 32 * 0b0..Converted data is in range - * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag + * 0b1..Converted data is out of range */ #define ADC_AWORR1_AWOR_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH32_SHIFT)) & ADC_AWORR1_AWOR_CH32_MASK) @@ -2337,9 +2340,9 @@ typedef struct { #define ADC_AWORR1_AWOR_CH33_SHIFT (1U) /*! AWOR_CH33 - Analog Watchdog Out of Range for Channel 33 * 0b0..Converted data is in range - * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag + * 0b1..Converted data is out of range */ #define ADC_AWORR1_AWOR_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH33_SHIFT)) & ADC_AWORR1_AWOR_CH33_MASK) @@ -2347,9 +2350,9 @@ typedef struct { #define ADC_AWORR1_AWOR_CH34_SHIFT (2U) /*! AWOR_CH34 - Analog Watchdog Out of Range for Channel 34 * 0b0..Converted data is in range - * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag + * 0b1..Converted data is out of range */ #define ADC_AWORR1_AWOR_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH34_SHIFT)) & ADC_AWORR1_AWOR_CH34_MASK) @@ -2357,9 +2360,9 @@ typedef struct { #define ADC_AWORR1_AWOR_CH35_SHIFT (3U) /*! AWOR_CH35 - Analog Watchdog Out of Range for Channel 35 * 0b0..Converted data is in range - * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag + * 0b1..Converted data is out of range */ #define ADC_AWORR1_AWOR_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH35_SHIFT)) & ADC_AWORR1_AWOR_CH35_MASK) @@ -2367,9 +2370,9 @@ typedef struct { #define ADC_AWORR1_AWOR_CH36_SHIFT (4U) /*! AWOR_CH36 - Analog Watchdog Out of Range for Channel 36 * 0b0..Converted data is in range - * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag + * 0b1..Converted data is out of range */ #define ADC_AWORR1_AWOR_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH36_SHIFT)) & ADC_AWORR1_AWOR_CH36_MASK) @@ -2377,9 +2380,9 @@ typedef struct { #define ADC_AWORR1_AWOR_CH37_SHIFT (5U) /*! AWOR_CH37 - Analog Watchdog Out of Range for Channel 37 * 0b0..Converted data is in range - * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag + * 0b1..Converted data is out of range */ #define ADC_AWORR1_AWOR_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH37_SHIFT)) & ADC_AWORR1_AWOR_CH37_MASK) @@ -2387,9 +2390,9 @@ typedef struct { #define ADC_AWORR1_AWOR_CH38_SHIFT (6U) /*! AWOR_CH38 - Analog Watchdog Out of Range for Channel 38 * 0b0..Converted data is in range - * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag + * 0b1..Converted data is out of range */ #define ADC_AWORR1_AWOR_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH38_SHIFT)) & ADC_AWORR1_AWOR_CH38_MASK) @@ -2397,9 +2400,9 @@ typedef struct { #define ADC_AWORR1_AWOR_CH39_SHIFT (7U) /*! AWOR_CH39 - Analog Watchdog Out of Range for Channel 39 * 0b0..Converted data is in range - * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag + * 0b1..Converted data is out of range */ #define ADC_AWORR1_AWOR_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH39_SHIFT)) & ADC_AWORR1_AWOR_CH39_MASK) /*! @} */ @@ -2593,9 +2596,9 @@ typedef struct { #define ADC_STSR1_ERR_S0_SHIFT (11U) /*! ERR_S0 - Algorithm S0 Error * 0b0..No VREF error - * 0b1..VREF error occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..VREF error occurred */ #define ADC_STSR1_ERR_S0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S0_SHIFT)) & ADC_STSR1_ERR_S0_MASK) @@ -2603,19 +2606,19 @@ typedef struct { #define ADC_STSR1_ERR_S1_SHIFT (12U) /*! ERR_S1 - Algorithm S1 Error * 0b0..No VDD ERROR - * 0b1..VDD ERROR occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..VDD ERROR occurred */ #define ADC_STSR1_ERR_S1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S1_SHIFT)) & ADC_STSR1_ERR_S1_MASK) #define ADC_STSR1_ERR_S2_MASK (0x2000U) #define ADC_STSR1_ERR_S2_SHIFT (13U) /*! ERR_S2 - Algorithm S2 Error - * 0b0..No error occurred on the sampled signal - * 0b1..Error occurred on the sampled signal * 0b0..No effect + * 0b0..No error occurred on the sampled signal * 0b1..Clear the flag + * 0b1..Error occurred on the sampled signal */ #define ADC_STSR1_ERR_S2(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S2_SHIFT)) & ADC_STSR1_ERR_S2_MASK) @@ -2623,8 +2626,8 @@ typedef struct { #define ADC_STSR1_ERR_C_SHIFT (15U) /*! ERR_C - Algorithm C Error * 0b0..No Algorithm C error - * 0b1..Algorithm C error occurred * 0b0..No effect + * 0b1..Algorithm C error occurred * 0b1..Clear the flag */ #define ADC_STSR1_ERR_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_C_SHIFT)) & ADC_STSR1_ERR_C_MASK) @@ -2632,60 +2635,60 @@ typedef struct { #define ADC_STSR1_WDG_EOA_S_MASK (0x10000U) #define ADC_STSR1_WDG_EOA_S_SHIFT (16U) /*! WDG_EOA_S - Watchdog End of Algorithm S - * 0b0..Self-test end of Algorithm S conversion is not complete. - * 0b1..Self-test end of Algorithm S conversion is complete. * 0b0..No effect + * 0b0..Self-test end of Algorithm S conversion is not complete. * 0b1..Clear the flag + * 0b1..Self-test end of Algorithm S conversion is complete. */ #define ADC_STSR1_WDG_EOA_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDG_EOA_S_SHIFT)) & ADC_STSR1_WDG_EOA_S_MASK) #define ADC_STSR1_WDG_EOA_C_MASK (0x40000U) #define ADC_STSR1_WDG_EOA_C_SHIFT (18U) /*! WDG_EOA_C - Watchdog End of Algorithm C - * 0b0..Self-test end of Algorithm C conversion is not complete - * 0b1..Self-test end of Algorithm C conversion is complete * 0b0..No effect + * 0b0..Self-test end of Algorithm C conversion is not complete * 0b1..Clear the flag + * 0b1..Self-test end of Algorithm C conversion is complete */ #define ADC_STSR1_WDG_EOA_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDG_EOA_C_SHIFT)) & ADC_STSR1_WDG_EOA_C_MASK) #define ADC_STSR1_ST_EOC_MASK (0x800000U) #define ADC_STSR1_ST_EOC_SHIFT (23U) /*! ST_EOC - Self-Test EOC - * 0b0..Self-test end of conversion is not complete - * 0b1..Self-test end of conversion is complete * 0b0..No effect + * 0b0..Self-test end of conversion is not complete * 0b1..Clear the flag + * 0b1..Self-test end of conversion is complete */ #define ADC_STSR1_ST_EOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ST_EOC_SHIFT)) & ADC_STSR1_ST_EOC_MASK) #define ADC_STSR1_OVERWR_MASK (0x1000000U) #define ADC_STSR1_OVERWR_SHIFT (24U) /*! OVERWR - Overwrite Error - * 0b0..No overwrite error - * 0b1..Overwrite error occurred * 0b0..No effect + * 0b0..No overwrite error * 0b1..Clear the flag + * 0b1..Overwrite error occurred */ #define ADC_STSR1_OVERWR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_OVERWR_SHIFT)) & ADC_STSR1_OVERWR_MASK) #define ADC_STSR1_WDTERR_MASK (0x2000000U) #define ADC_STSR1_WDTERR_SHIFT (25U) /*! WDTERR - Watchdog Timer Error - * 0b0..No failure - * 0b1..Failure occurred * 0b0..No effect + * 0b0..No failure * 0b1..Clear the flag + * 0b1..Failure occurred */ #define ADC_STSR1_WDTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDTERR_SHIFT)) & ADC_STSR1_WDTERR_MASK) #define ADC_STSR1_WDSERR_MASK (0x8000000U) #define ADC_STSR1_WDSERR_SHIFT (27U) /*! WDSERR - Watchdog Sequence Errors - * 0b0..No failure - * 0b1..Failure occurred * 0b0..No effect + * 0b0..No failure * 0b1..Clear the flag + * 0b1..Failure occurred */ #define ADC_STSR1_WDSERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDSERR_SHIFT)) & ADC_STSR1_WDSERR_MASK) /*! @} */ @@ -3056,5 +3059,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ADC_H_ */ +#endif /* PERI_ADC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ANA_OSC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ANA_OSC.h index 24c7ce64e4..0e9d8da3dc 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ANA_OSC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ANA_OSC.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANA_OSC ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ANA_OSC.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_ANA_OSC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ANA_OSC * * CMSIS Peripheral Access Layer for ANA_OSC */ -#if !defined(ANA_OSC_H_) -#define ANA_OSC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ANA_OSC_H_) +#define PERI_ANA_OSC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -247,5 +250,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ANA_OSC_H_ */ +#endif /* PERI_ANA_OSC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_AXBS.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_AXBS.h index 438d391fc8..0c5df9de35 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_AXBS.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_AXBS.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for AXBS ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file AXBS.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_AXBS.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for AXBS * * CMSIS Peripheral Access Layer for AXBS */ -#if !defined(AXBS_H_) -#define AXBS_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_AXBS_H_) +#define PERI_AXBS_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -2081,5 +2084,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* AXBS_H_ */ +#endif /* PERI_AXBS_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BBNSM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BBNSM.h index 8f6e9638d9..de55ccd1ce 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BBNSM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BBNSM.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for BBNSM ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file BBNSM.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_BBNSM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for BBNSM * * CMSIS Peripheral Access Layer for BBNSM */ -#if !defined(BBNSM_H_) -#define BBNSM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_BBNSM_H_) +#define PERI_BBNSM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -272,14 +275,14 @@ typedef struct { #define BBNSM_BBNSM_CTRL_CAL_VAL_MASK (0x1F00U) #define BBNSM_BBNSM_CTRL_CAL_VAL_SHIFT (8U) /*! CAL_VAL - Calibration Value - * 0b01111..+15 counts per each 32768 ticks of the counter clock. - * 0b00010..+2 counts per each 32768 ticks of the counter clock. - * 0b00001..+1 counts per each 32768 ticks of the counter clock. * 0b00000..+0 counts per each 32768 ticks of the counter clock. - * 0b11111..-1 counts per each 32768 ticks of the counter clock. - * 0b11110..-2 counts per each 32768 ticks of the counter clock. - * 0b10001..-15 counts per each 32768 ticks of the counter clock. + * 0b00001..+1 counts per each 32768 ticks of the counter clock. + * 0b00010..+2 counts per each 32768 ticks of the counter clock. + * 0b01111..+15 counts per each 32768 ticks of the counter clock. * 0b10000..-16 counts per each 32768 ticks of the counter clock. + * 0b10001..-15 counts per each 32768 ticks of the counter clock. + * 0b11110..-2 counts per each 32768 ticks of the counter clock. + * 0b11111..-1 counts per each 32768 ticks of the counter clock. */ #define BBNSM_BBNSM_CTRL_CAL_VAL(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_CAL_VAL_SHIFT)) & BBNSM_BBNSM_CTRL_CAL_VAL_MASK) @@ -623,5 +626,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* BBNSM_H_ */ +#endif /* PERI_BBNSM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_MLMIX.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_MLMIX.h index e293926e18..aa88ea273b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_MLMIX.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_MLMIX.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for BLK_CTRL_MLMIX ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file BLK_CTRL_MLMIX.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_BLK_CTRL_MLMIX.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for BLK_CTRL_MLMIX * * CMSIS Peripheral Access Layer for BLK_CTRL_MLMIX */ -#if !defined(BLK_CTRL_MLMIX_H_) -#define BLK_CTRL_MLMIX_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_BLK_CTRL_MLMIX_H_) +#define PERI_BLK_CTRL_MLMIX_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -239,5 +242,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* BLK_CTRL_MLMIX_H_ */ +#endif /* PERI_BLK_CTRL_MLMIX_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_NICMIX.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_NICMIX.h index 2222c81636..7787f48933 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_NICMIX.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_NICMIX.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for BLK_CTRL_NICMIX ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file BLK_CTRL_NICMIX.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_BLK_CTRL_NICMIX.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for BLK_CTRL_NICMIX * * CMSIS Peripheral Access Layer for BLK_CTRL_NICMIX */ -#if !defined(BLK_CTRL_NICMIX_H_) -#define BLK_CTRL_NICMIX_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_BLK_CTRL_NICMIX_H_) +#define PERI_BLK_CTRL_NICMIX_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -585,5 +588,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* BLK_CTRL_NICMIX_H_ */ +#endif /* PERI_BLK_CTRL_NICMIX_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_NS_AONMIX.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_NS_AONMIX.h index 4f0bf4fe7e..9bed03481d 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_NS_AONMIX.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_NS_AONMIX.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for BLK_CTRL_NS_AONMIX ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file BLK_CTRL_NS_AONMIX.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_BLK_CTRL_NS_AONMIX.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for BLK_CTRL_NS_AONMIX * * CMSIS Peripheral Access Layer for BLK_CTRL_NS_AONMIX */ -#if !defined(BLK_CTRL_NS_AONMIX_H_) -#define BLK_CTRL_NS_AONMIX_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_BLK_CTRL_NS_AONMIX_H_) +#define PERI_BLK_CTRL_NS_AONMIX_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -229,120 +232,120 @@ typedef struct { #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_CAN1_MASK (0x1U) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_CAN1_SHIFT (0U) /*! CAN1 - Mask bit for debug halted mode - * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_CAN1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_CAN1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_CAN1_MASK) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_EDMA1_MASK (0x2U) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_EDMA1_SHIFT (1U) /*! EDMA1 - Mask bit for debug halted mode - * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_EDMA1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_EDMA1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_EDMA1_MASK) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C1_MASK (0x4U) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C1_SHIFT (2U) /*! LPI2C1 - Mask bit for debug halted mode - * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C1_MASK) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C2_MASK (0x8U) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C2_SHIFT (3U) /*! LPI2C2 - Mask bit for debug halted mode - * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C2_MASK) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPIT1_MASK (0x10U) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPIT1_SHIFT (4U) /*! LPIT1 - Mask bit for debug halted mode - * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPIT1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPIT1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPIT1_MASK) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI1_MASK (0x20U) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI1_SHIFT (5U) /*! LPSPI1 - Mask bit for debug halted mode - * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI1_MASK) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI2_MASK (0x40U) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI2_SHIFT (6U) /*! LPSPI2 - Mask bit for debug halted mode - * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI2_MASK) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPTMR1_MASK (0x80U) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPTMR1_SHIFT (7U) /*! LPTMR1 - Mask bit for debug halted mode - * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPTMR1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPTMR1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPTMR1_MASK) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_SAI1_MASK (0x100U) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_SAI1_SHIFT (8U) /*! SAI1 - Mask bit for debug halted mode - * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_SAI1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_SAI1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_SAI1_MASK) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM1_MASK (0x200U) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM1_SHIFT (9U) /*! TPM1 - Mask bit for debug halted mode - * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM1_MASK) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM2_MASK (0x400U) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM2_SHIFT (10U) /*! TPM2 - Mask bit for debug halted mode - * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM2_MASK) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG1_MASK (0x800U) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG1_SHIFT (11U) /*! WDOG1 - Mask bit for debug halted mode - * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG1_MASK) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG2_MASK (0x1000U) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG2_SHIFT (12U) /*! WDOG2 - Mask bit for debug halted mode - * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG2_MASK) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_I3C1_MASK (0x2000U) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_I3C1_SHIFT (13U) /*! I3C1 - Mask bit for debug halted mode - * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_I3C1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_I3C1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_I3C1_MASK) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_PDM_MASK (0x4000U) #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_PDM_SHIFT (14U) /*! PDM - Mask bit for debug halted mode - * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_PDM(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_PDM_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_PDM_MASK) /*! @} */ @@ -594,8 +597,8 @@ typedef struct { #define BLK_CTRL_NS_AONMIX_OCOTP_STATUS_BUSY_MASK (0x1U) #define BLK_CTRL_NS_AONMIX_OCOTP_STATUS_BUSY_SHIFT (0U) /*! BUSY - OCOTP controller busy bit - * 0b1..OCOTP is Busy * 0b0..Idle + * 0b1..OCOTP is Busy */ #define BLK_CTRL_NS_AONMIX_OCOTP_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_STATUS_BUSY_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_STATUS_BUSY_MASK) /*! @} */ @@ -681,5 +684,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* BLK_CTRL_NS_AONMIX_H_ */ +#endif /* PERI_BLK_CTRL_NS_AONMIX_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_S_AONMIX.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_S_AONMIX.h index bfa258ee2d..e00dc30d46 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_S_AONMIX.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_S_AONMIX.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for BLK_CTRL_S_AONMIX ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file BLK_CTRL_S_AONMIX.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_BLK_CTRL_S_AONMIX.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for BLK_CTRL_S_AONMIX * * CMSIS Peripheral Access Layer for BLK_CTRL_S_AONMIX */ -#if !defined(BLK_CTRL_S_AONMIX_H_) -#define BLK_CTRL_S_AONMIX_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_BLK_CTRL_S_AONMIX_H_) +#define PERI_BLK_CTRL_S_AONMIX_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -425,10 +428,10 @@ typedef struct { #define BLK_CTRL_S_AONMIX_M33_CFG_TCM_SIZE_MASK (0x18U) #define BLK_CTRL_S_AONMIX_M33_CFG_TCM_SIZE_SHIFT (3U) /*! TCM_SIZE - M33 TCM SIZE - * 0b11..Reserved - * 0b10..Double Sys TCM, 256KB Sys TCM - * 0b01..Double Code TCM, 256KB Code TCM * 0b00..Regular TCM, 128KB Code TCM and 128KB Sys TCM + * 0b01..Double Code TCM, 256KB Code TCM + * 0b10..Double Sys TCM, 256KB Sys TCM + * 0b11..Reserved */ #define BLK_CTRL_S_AONMIX_M33_CFG_TCM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_M33_CFG_TCM_SIZE_SHIFT)) & BLK_CTRL_S_AONMIX_M33_CFG_TCM_SIZE_MASK) /*! @} */ @@ -439,16 +442,16 @@ typedef struct { #define BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_M33_MASK (0x1U) #define BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_M33_SHIFT (0U) /*! M33 - M33 DAP_ACCESS_STKY - * 0b1..M33 core cannot be accessed by DAPCore0 works normally * 0b0..M33 core can be accessed by DAP + * 0b1..M33 core cannot be accessed by DAPCore0 works normally */ #define BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_M33(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_M33_SHIFT)) & BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_M33_MASK) #define BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55_MASK (0x2U) #define BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55_SHIFT (1U) /*! A55 - A55 DAP_ACCESS_STKY - * 0b1..A55 core cannot be accessed by DAPCore0 works normally * 0b0..A55 core can be accessed by DAP + * 0b1..A55 core cannot be accessed by DAPCore0 works normally */ #define BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55_SHIFT)) & BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55_MASK) /*! @} */ @@ -999,5 +1002,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* BLK_CTRL_S_AONMIX_H_ */ +#endif /* PERI_BLK_CTRL_S_AONMIX_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_WAKEUPMIX.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_WAKEUPMIX.h index e6cb440b37..1e2500c8f9 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_WAKEUPMIX.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_BLK_CTRL_WAKEUPMIX.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for BLK_CTRL_WAKEUPMIX ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file BLK_CTRL_WAKEUPMIX.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_BLK_CTRL_WAKEUPMIX.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for BLK_CTRL_WAKEUPMIX * * CMSIS Peripheral Access Layer for BLK_CTRL_WAKEUPMIX */ -#if !defined(BLK_CTRL_WAKEUPMIX_H_) -#define BLK_CTRL_WAKEUPMIX_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_BLK_CTRL_WAKEUPMIX_H_) +#define PERI_BLK_CTRL_WAKEUPMIX_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -215,232 +218,232 @@ typedef struct { #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_CAN2_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_CAN2_SHIFT (0U) /*! CAN2 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_CAN2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_CAN2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_CAN2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_EDMA2_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_EDMA2_SHIFT (1U) /*! EDMA2 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_EDMA2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_EDMA2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_EDMA2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_FLEXIO1_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_FLEXIO1_SHIFT (2U) /*! FLEXIO1 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_FLEXIO1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_FLEXIO1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_FLEXIO1_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_FLEXIO2_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_FLEXIO2_SHIFT (3U) /*! FLEXIO2 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_FLEXIO2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_FLEXIO2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_FLEXIO2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C3_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C3_SHIFT (4U) /*! LPI2C3 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C4_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C4_SHIFT (5U) /*! LPI2C4 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C5_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C5_SHIFT (6U) /*! LPI2C5 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C6_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C6_SHIFT (7U) /*! LPI2C6 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C7_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C7_SHIFT (8U) /*! LPI2C7 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C8_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C8_SHIFT (9U) /*! LPI2C8 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPI2C8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPIT2_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPIT2_SHIFT (10U) /*! LPIT2 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPIT2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPIT2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPIT2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI3_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI3_SHIFT (11U) /*! LPSPI3 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI4_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI4_SHIFT (12U) /*! LPSPI4 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI5_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI5_SHIFT (13U) /*! LPSPI5 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI6_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI6_SHIFT (14U) /*! LPSPI6 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI7_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI7_SHIFT (15U) /*! LPSPI7 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI8_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI8_SHIFT (16U) /*! LPSPI8 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPSPI8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPTMR2_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPTMR2_SHIFT (17U) /*! LPTMR2 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPTMR2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPTMR2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_LPTMR2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM3_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM3_SHIFT (18U) /*! TPM3 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM4_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM4_SHIFT (19U) /*! TPM4 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM5_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM5_SHIFT (20U) /*! TPM5 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM6_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM6_SHIFT (21U) /*! TPM6 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_TPM6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_WDOG3_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_WDOG3_SHIFT (22U) /*! WDOG3 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_WDOG3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_WDOG3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_WDOG3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_WDOG4_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_WDOG4_SHIFT (23U) /*! WDOG4 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_WDOG4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_WDOG4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_WDOG4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_WDOG5_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_WDOG5_SHIFT (24U) /*! WDOG5 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_WDOG5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_WDOG5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_WDOG5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_I3C2_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_I3C2_SHIFT (25U) /*! I3C2 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_I3C2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_I3C2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_I3C2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_SAI2_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_SAI2_SHIFT (26U) /*! SAI2 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_SAI2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_SAI2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_SAI2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_SAI3_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_SAI3_SHIFT (27U) /*! SAI3 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_SAI3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_SAI3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_SAI3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_ENET1_MASK (0x10000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_ENET1_SHIFT (28U) /*! ENET1 - * 0b1..Module enters debug halted mode when CM33 is debug halted * 0b0..Module does not enter debug halted mode with CM33 + * 0b1..Module enters debug halted mode when CM33 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_ENET1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_ENET1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_ENET1_MASK) /*! @} */ @@ -675,8 +678,8 @@ typedef struct { #define BLK_CTRL_WAKEUPMIX_GPR_ENABLE_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_GPR_ENABLE_SHIFT (0U) /*! ENABLE - ENET QOS enable - * 0b1..ENET QoS is enabled * 0b0..ENET QoS is disabled + * 0b1..ENET QoS is enabled */ #define BLK_CTRL_WAKEUPMIX_GPR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPR_ENABLE_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPR_ENABLE_MASK) @@ -684,8 +687,8 @@ typedef struct { #define BLK_CTRL_WAKEUPMIX_GPR_MODE_SHIFT (1U) /*! MODE - ENET QOS mode selection * 0b000..MII mode is selected - * 0b100..RMII mode is selected * 0b001..RGMII mode is selected + * 0b100..RMII mode is selected */ #define BLK_CTRL_WAKEUPMIX_GPR_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPR_MODE_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPR_MODE_MASK) @@ -768,104 +771,104 @@ typedef struct { #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_CAN2_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_CAN2_SHIFT (0U) /*! CAN2 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_CAN2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_CAN2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_CAN2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_EDMA2_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_EDMA2_SHIFT (1U) /*! EDMA2 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_EDMA2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_EDMA2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_EDMA2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_FLEXIO1_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_FLEXIO1_SHIFT (2U) /*! FLEXIO1 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_FLEXIO1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_FLEXIO1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_FLEXIO1_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_FLEXIO2_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_FLEXIO2_SHIFT (3U) /*! FLEXIO2 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_FLEXIO2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_FLEXIO2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_FLEXIO2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C3_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C3_SHIFT (4U) /*! LPI2C3 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C4_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C4_SHIFT (5U) /*! LPI2C4 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C5_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C5_SHIFT (6U) /*! LPI2C5 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C6_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C6_SHIFT (7U) /*! LPI2C6 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C7_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C7_SHIFT (8U) /*! LPI2C7 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C8_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C8_SHIFT (9U) /*! LPI2C8 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPIT2_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPIT2_SHIFT (10U) /*! LPIT2 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPIT2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPIT2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPIT2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI3_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI3_SHIFT (11U) /*! LPSPI3 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI4_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI4_SHIFT (12U) /*! LPSPI4 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI4_MASK) @@ -876,120 +879,120 @@ typedef struct { #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI6_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI6_SHIFT (14U) /*! LPSPI6 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI7_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI7_SHIFT (15U) /*! LPSPI7 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI8_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI8_SHIFT (16U) /*! LPSPI8 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPTMR2_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPTMR2_SHIFT (17U) /*! LPTMR2 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPTMR2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPTMR2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPTMR2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM3_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM3_SHIFT (18U) /*! TPM3 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM4_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM4_SHIFT (19U) /*! TPM4 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM5_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM5_SHIFT (20U) /*! TPM5 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM6_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM6_SHIFT (21U) /*! TPM6 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG3_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG3_SHIFT (22U) /*! WDOG3 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG4_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG4_SHIFT (23U) /*! WDOG4 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG5_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG5_SHIFT (24U) /*! WDOG5 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_I3C2_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_I3C2_SHIFT (25U) /*! I3C2 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_I3C2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_I3C2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_I3C2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI2_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI2_SHIFT (26U) /*! SAI2 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI3_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI3_SHIFT (27U) /*! SAI3 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_ENET1_MASK (0x10000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_ENET1_SHIFT (28U) /*! ENET1 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_ENET1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_ENET1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_ENET1_MASK) /*! @} */ @@ -1000,232 +1003,232 @@ typedef struct { #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_CAN2_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_CAN2_SHIFT (0U) /*! CAN2 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_CAN2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_CAN2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_CAN2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_EDMA2_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_EDMA2_SHIFT (1U) /*! EDMA2 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_EDMA2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_EDMA2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_EDMA2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_FLEXIO1_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_FLEXIO1_SHIFT (2U) /*! FLEXIO1 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_FLEXIO1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_FLEXIO1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_FLEXIO1_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_FLEXIO2_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_FLEXIO2_SHIFT (3U) /*! FLEXIO2 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_FLEXIO2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_FLEXIO2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_FLEXIO2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C3_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C3_SHIFT (4U) /*! LPI2C3 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C4_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C4_SHIFT (5U) /*! LPI2C4 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C5_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C5_SHIFT (6U) /*! LPI2C5 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C6_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C6_SHIFT (7U) /*! LPI2C6 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C7_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C7_SHIFT (8U) /*! LPI2C7 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C8_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C8_SHIFT (9U) /*! LPI2C8 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPI2C8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPIT2_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPIT2_SHIFT (10U) /*! LPIT2 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPIT2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPIT2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPIT2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI3_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI3_SHIFT (11U) /*! LPSPI3 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI4_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI4_SHIFT (12U) /*! LPSPI4 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI5_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI5_SHIFT (13U) /*! LPSPI5 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI6_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI6_SHIFT (14U) /*! LPSPI6 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI7_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI7_SHIFT (15U) /*! LPSPI7 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI8_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI8_SHIFT (16U) /*! LPSPI8 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPSPI8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPTMR2_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPTMR2_SHIFT (17U) /*! LPTMR2 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPTMR2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPTMR2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_LPTMR2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM3_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM3_SHIFT (18U) /*! TPM3 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM4_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM4_SHIFT (19U) /*! TPM4 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM5_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM5_SHIFT (20U) /*! TPM5 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM6_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM6_SHIFT (21U) /*! TPM6 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_TPM6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_WDOG3_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_WDOG3_SHIFT (22U) /*! WDOG3 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_WDOG3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_WDOG3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_WDOG3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_WDOG4_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_WDOG4_SHIFT (23U) /*! WDOG4 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_WDOG4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_WDOG4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_WDOG4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_WDOG5_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_WDOG5_SHIFT (24U) /*! WDOG5 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_WDOG5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_WDOG5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_WDOG5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_I3C2_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_I3C2_SHIFT (25U) /*! I3C2 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_I3C2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_I3C2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_I3C2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_SAI2_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_SAI2_SHIFT (26U) /*! SAI2 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_SAI2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_SAI2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_SAI2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_SAI3_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_SAI3_SHIFT (27U) /*! SAI3 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_SAI3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_SAI3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_SAI3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_ENET1_MASK (0x10000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_ENET1_SHIFT (28U) /*! ENET1 - * 0b1..Module enters debug halted mode when A55 is debug halted * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_ENET1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_ENET1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_ENET1_MASK) /*! @} */ @@ -1310,5 +1313,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* BLK_CTRL_WAKEUPMIX_H_ */ +#endif /* PERI_BLK_CTRL_WAKEUPMIX_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_CACHE_ECC_MCM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_CACHE_ECC_MCM.h index 8151d636b9..cffa9b30d8 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_CACHE_ECC_MCM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_CACHE_ECC_MCM.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for CACHE_ECC_MCM ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file CACHE_ECC_MCM.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_CACHE_ECC_MCM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for CACHE_ECC_MCM * * CMSIS Peripheral Access Layer for CACHE_ECC_MCM */ -#if !defined(CACHE_ECC_MCM_H_) -#define CACHE_ECC_MCM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_CACHE_ECC_MCM_H_) +#define PERI_CACHE_ECC_MCM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -223,16 +226,16 @@ typedef struct { #define CACHE_ECC_MCM_CACHE_ECCR_WECC_DIS_MASK (0x1U) #define CACHE_ECC_MCM_CACHE_ECCR_WECC_DIS_SHIFT (0U) /*! WECC_DIS - Disable CACHE ECC Write Generation - * 0b1..Disable ECC generation on CACHE write data * 0b0..Enable ECC generation on CACHE write data + * 0b1..Disable ECC generation on CACHE write data */ #define CACHE_ECC_MCM_CACHE_ECCR_WECC_DIS(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CACHE_ECCR_WECC_DIS_SHIFT)) & CACHE_ECC_MCM_CACHE_ECCR_WECC_DIS_MASK) #define CACHE_ECC_MCM_CACHE_ECCR_RECC_DIS_MASK (0x2U) #define CACHE_ECC_MCM_CACHE_ECCR_RECC_DIS_SHIFT (1U) /*! RECC_DIS - Disable Cache ECC Read Check - * 0b1..Disable ECC check on CACHE read data * 0b0..Enable ECC check on CACHE read data + * 0b1..Disable ECC check on CACHE read data */ #define CACHE_ECC_MCM_CACHE_ECCR_RECC_DIS(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CACHE_ECCR_RECC_DIS_SHIFT)) & CACHE_ECC_MCM_CACHE_ECCR_RECC_DIS_MASK) /*! @} */ @@ -914,5 +917,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* CACHE_ECC_MCM_H_ */ +#endif /* PERI_CACHE_ECC_MCM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_CAN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_CAN.h index 0a3000d818..3454dcec99 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_CAN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_CAN.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for CAN ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file CAN.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_CAN.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for CAN * * CMSIS Peripheral Access Layer for CAN */ -#if !defined(CAN_H_) -#define CAN_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_CAN_H_) +#define PERI_CAN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -323,8 +326,8 @@ typedef struct { #define CAN_MCR_FDEN_MASK (0x800U) #define CAN_MCR_FDEN_SHIFT (11U) /*! FDEN - CAN FD Operation Enable - * 0b1..Enable * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) @@ -2409,5 +2412,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* CAN_H_ */ +#endif /* PERI_CAN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_CCM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_CCM.h index e54565a60a..f210bd5e96 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_CCM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_CCM.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for CCM ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file CCM.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_CCM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for CCM * * CMSIS Peripheral Access Layer for CCM */ -#if !defined(CCM_H_) -#define CCM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_CCM_H_) +#define PERI_CCM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -326,9 +329,9 @@ typedef struct { #define CCM_CLOCK_ROOT_MUX_MASK (0x300U) #define CCM_CLOCK_ROOT_MUX_SHIFT (8U) /*! MUX - Clock multiplexer. - * 0b10..Select clock source 2 * 0b00..Select clock source 0 * 0b01..Select clock source 1 + * 0b10..Select clock source 2 * 0b11..Select clock source 3 */ #define CCM_CLOCK_ROOT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_MUX_SHIFT)) & CCM_CLOCK_ROOT_MUX_MASK) @@ -389,8 +392,8 @@ typedef struct { #define CCM_CLOCK_ROOT_TZ_USER_MASK (0x100U) #define CCM_CLOCK_ROOT_TZ_USER_SHIFT (8U) /*! TZ_USER - User access permission - * 0b1..Clock Root settings can be changed in user mode. * 0b0..Clock Root settings cannot be changed in user mode. + * 0b1..Clock Root settings can be changed in user mode. */ #define CCM_CLOCK_ROOT_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_TZ_USER_MASK) @@ -430,8 +433,8 @@ typedef struct { #define CCM_GPR_SHARED0_AUTHEN_TZ_USER_MASK (0x100U) #define CCM_GPR_SHARED0_AUTHEN_TZ_USER_SHIFT (8U) /*! TZ_USER - User access permission - * 0b1..Registers of shared GPR slice can be changed in user mode. * 0b0..Registers of shared GPR slice cannot be changed in user mode. + * 0b1..Registers of shared GPR slice can be changed in user mode. */ #define CCM_GPR_SHARED0_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_TZ_USER_MASK) @@ -483,8 +486,8 @@ typedef struct { #define CCM_GPR_SHARED1_AUTHEN_TZ_USER_MASK (0x100U) #define CCM_GPR_SHARED1_AUTHEN_TZ_USER_SHIFT (8U) /*! TZ_USER - User access permission - * 0b1..Registers of shared GPR slice can be changed in user mode. * 0b0..Registers of shared GPR slice cannot be changed in user mode. + * 0b1..Registers of shared GPR slice can be changed in user mode. */ #define CCM_GPR_SHARED1_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_TZ_USER_MASK) @@ -536,8 +539,8 @@ typedef struct { #define CCM_GPR_SHARED2_AUTHEN_TZ_USER_MASK (0x100U) #define CCM_GPR_SHARED2_AUTHEN_TZ_USER_SHIFT (8U) /*! TZ_USER - User access permission - * 0b1..Registers of shared GPR slice can be changed in user mode. * 0b0..Registers of shared GPR slice cannot be changed in user mode. + * 0b1..Registers of shared GPR slice can be changed in user mode. */ #define CCM_GPR_SHARED2_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_TZ_USER_MASK) @@ -577,8 +580,8 @@ typedef struct { #define CCM_GPR_SHARED_TZ_USER_MASK (0x100U) #define CCM_GPR_SHARED_TZ_USER_SHIFT (8U) /*! TZ_USER - User access permission - * 0b1..Registers of shared GPR slice can be changed in user mode. * 0b0..Registers of shared GPR slice cannot be changed in user mode. + * 0b1..Registers of shared GPR slice can be changed in user mode. */ #define CCM_GPR_SHARED_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_TZ_USER_SHIFT)) & CCM_GPR_SHARED_TZ_USER_MASK) @@ -627,8 +630,8 @@ typedef struct { #define CCM_GPR_PRIVATE_TZ_USER_MASK (0x100U) #define CCM_GPR_PRIVATE_TZ_USER_SHIFT (8U) /*! TZ_USER - User access permission - * 0b1..Registers of private GPR can be changed in user mode. * 0b0..Registers of privat GPR cannot be changed in user mode. + * 0b1..Registers of private GPR can be changed in user mode. */ #define CCM_GPR_PRIVATE_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE_TZ_USER_MASK) @@ -1211,8 +1214,8 @@ typedef struct { #define CCM_OSCPLL_AUTHEN_TZ_USER_MASK (0x100U) #define CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT (8U) /*! TZ_USER - User access permission - * 0b1..Clock Source settings can be changed in user mode. * 0b0..Clock Source settings cannot be changed in user mode. + * 0b1..Clock Source settings can be changed in user mode. */ #define CCM_OSCPLL_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_USER_MASK) @@ -1779,8 +1782,8 @@ typedef struct { #define CCM_LPCG_AUTHEN_TZ_USER_MASK (0x100U) #define CCM_LPCG_AUTHEN_TZ_USER_SHIFT (8U) /*! TZ_USER - User access permission - * 0b1..LPCG settings can be changed in user mode. * 0b0..LPCG settings cannot be changed in user mode. + * 0b1..LPCG settings can be changed in user mode. */ #define CCM_LPCG_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_USER_SHIFT)) & CCM_LPCG_AUTHEN_TZ_USER_MASK) @@ -1851,5 +1854,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* CCM_H_ */ +#endif /* PERI_CCM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_DDRC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_DDRC.h index cdb063748f..24be94d2c2 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_DDRC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_DDRC.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for DDRC ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file DDRC.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_DDRC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for DDRC * * CMSIS Peripheral Access Layer for DDRC */ -#if !defined(DDRC_H_) -#define DDRC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_DDRC_H_) +#define PERI_DDRC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -723,7 +726,6 @@ typedef struct { * 0b010..10 * 0b011..11 * 0b111..7 - * *.. */ #define DDRC_CS_CONFIG_COL_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_COL_BITS_CS_SHIFT)) & DDRC_CS_CONFIG_COL_BITS_CS_MASK) @@ -746,7 +748,6 @@ typedef struct { * 0b011..15 * 0b100..16 * 0b101..17 - * *.. */ #define DDRC_CS_CONFIG_ROW_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_ROW_BITS_CS_SHIFT)) & DDRC_CS_CONFIG_ROW_BITS_CS_MASK) @@ -1004,7 +1005,6 @@ typedef struct { /*! BA_INTLV_CTL - Rank Interleaving Control * 0b0000000..No external ranks are interleaved. * 0b1000000..External ranks 0 and 1 are interleaved. - * *.. */ #define DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_SHIFT)) & DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_MASK) @@ -1012,7 +1012,6 @@ typedef struct { #define DDRC_DDR_SDRAM_CFG_DBW_SHIFT (19U) /*! DBW - DDR SDRAM Data Bus Width * 0b10..16 bits - * *.. */ #define DDRC_DDR_SDRAM_CFG_DBW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_DBW_SHIFT)) & DDRC_DDR_SDRAM_CFG_DBW_MASK) @@ -1028,7 +1027,6 @@ typedef struct { #define DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_SHIFT (24U) /*! SDRAM_TYPE - DDR SDRAM Type * 0b100..LPDDR4X SDRAM - * *.. */ #define DDRC_DDR_SDRAM_CFG_SDRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_SHIFT)) & DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_MASK) @@ -1071,7 +1069,6 @@ typedef struct { * 0b0110..6 * 0b0111..7 * 0b1000..8 - * *.. */ #define DDRC_DDR_SDRAM_CFG_2_NUM_PR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_NUM_PR_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_NUM_PR_MASK) @@ -1139,7 +1136,6 @@ typedef struct { * 0b000..0 * 0b001..1 * 0b100..0 and 1 - * *.. */ #define DDRC_DDR_SDRAM_MD_CNTL_CS_SEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_MASK) @@ -1183,7 +1179,6 @@ typedef struct { /*! DLL_LOCK - DDR SDRAM DLL Lock Time * 0b10..1024 clocks * 0b11..2048 clocks - * *.. */ #define DDRC_TIMING_CFG_4_DLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_DLL_LOCK_SHIFT)) & DDRC_TIMING_CFG_4_DLL_LOCK_MASK) @@ -1310,7 +1305,6 @@ typedef struct { * 0b1001..16384 * 0b1010..32768 * 0b1111..ZQCS calibration disabled - * *.. */ #define DDRC_DDR_ZQ_CNTL_ZQCS_INT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQCS_INT_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQCS_INT_MASK) @@ -1486,7 +1480,6 @@ typedef struct { * 0b010..DBI * 0b011..Neither data masks nor DBI * 0b100..DBI with data masks - * *.. */ #define DDRC_DDR_SDRAM_CFG_3_DM_CFG(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DM_CFG_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DM_CFG_MASK) @@ -1702,7 +1695,6 @@ typedef struct { * 0b0001..Total write and read streams are one transaction each. * 0b0010..Total write and read streams are two transactions each. * 0b0011..Total write and read streams are four transactions each. - * *.. */ #define DDRC_DDR_MTCR_MT_TRNARND(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_TRNARND_SHIFT)) & DDRC_DDR_MTCR_MT_TRNARND_MASK) @@ -3547,5 +3539,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* DDRC_H_ */ +#endif /* PERI_DDRC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_DDRMIX_BLK_CTRL.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_DDRMIX_BLK_CTRL.h index ea5b0bc49b..af493f4d9f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_DDRMIX_BLK_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_DDRMIX_BLK_CTRL.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for DDRMIX_BLK_CTRL ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file DDRMIX_BLK_CTRL.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_DDRMIX_BLK_CTRL.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for DDRMIX_BLK_CTRL * * CMSIS Peripheral Access Layer for DDRMIX_BLK_CTRL */ -#if !defined(DDRMIX_BLK_CTRL_H_) -#define DDRMIX_BLK_CTRL_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_DDRMIX_BLK_CTRL_H_) +#define PERI_DDRMIX_BLK_CTRL_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -320,5 +323,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* DDRMIX_BLK_CTRL_H_ */ +#endif /* PERI_DDRMIX_BLK_CTRL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_DMA.h index 6ecf10bab2..40bb1dc20c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_DMA.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file DMA.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_DMA.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for DMA * * CMSIS Peripheral Access Layer for DMA */ -#if !defined(DMA_H_) -#define DMA_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_DMA_H_) +#define PERI_DMA_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -1096,5 +1099,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* DMA_H_ */ +#endif /* PERI_DMA_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_DMA4.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_DMA4.h index 1b5228b8ff..fdd23e0faa 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_DMA4.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_DMA4.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA4 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file DMA4.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_DMA4.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for DMA4 * * CMSIS Peripheral Access Layer for DMA4 */ -#if !defined(DMA4_H_) -#define DMA4_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_DMA4_H_) +#define PERI_DMA4_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -1242,5 +1245,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* DMA4_H_ */ +#endif /* PERI_DMA4_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ENET.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ENET.h index 4dc787c83b..01cf1d7518 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ENET.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ENET.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENET ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ENET.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_ENET.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ENET * * CMSIS Peripheral Access Layer for ENET */ -#if !defined(ENET_H_) -#define ENET_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ENET_H_) +#define PERI_ENET_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -2342,5 +2345,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ENET_H_ */ +#endif /* PERI_ENET_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ENET_QOS.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ENET_QOS.h index 230bba0583..d2c89b8fa3 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ENET_QOS.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ENET_QOS.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENET_QOS ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ENET_QOS.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_ENET_QOS.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ENET_QOS * * CMSIS Peripheral Access Layer for ENET_QOS */ -#if !defined(ENET_QOS_H_) -#define ENET_QOS_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ENET_QOS_H_) +#define PERI_ENET_QOS_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -599,9 +602,9 @@ typedef struct { #define ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK (0xCU) #define ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT (2U) /*! PRELEN - Preamble Length for Transmit packets - * 0b10..3 bytes of preamble - * 0b01..5 bytes of preamble * 0b00..7 bytes of preamble + * 0b01..5 bytes of preamble + * 0b10..3 bytes of preamble * 0b11..Reserved */ #define ENET_QOS_MAC_CONFIGURATION_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK) @@ -617,34 +620,34 @@ typedef struct { #define ENET_QOS_MAC_CONFIGURATION_BL_MASK (0x60U) #define ENET_QOS_MAC_CONFIGURATION_BL_SHIFT (5U) /*! BL - Back-Off Limit - * 0b11..k = min(n,1) * 0b00..k = min(n,10) - * 0b10..k = min(n,4) * 0b01..k = min(n,8) + * 0b10..k = min(n,4) + * 0b11..k = min(n,1) */ #define ENET_QOS_MAC_CONFIGURATION_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BL_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BL_MASK) #define ENET_QOS_MAC_CONFIGURATION_DR_MASK (0x100U) #define ENET_QOS_MAC_CONFIGURATION_DR_SHIFT (8U) /*! DR - Disable Retry - * 0b1..Disable Retry * 0b0..Enable Retry + * 0b1..Disable Retry */ #define ENET_QOS_MAC_CONFIGURATION_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DR_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DR_MASK) #define ENET_QOS_MAC_CONFIGURATION_DCRS_MASK (0x200U) #define ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT (9U) /*! DCRS - Disable Carrier Sense During Transmission - * 0b1..Disable Carrier Sense During Transmission * 0b0..Enable Carrier Sense During Transmission + * 0b1..Disable Carrier Sense During Transmission */ #define ENET_QOS_MAC_CONFIGURATION_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DCRS_MASK) #define ENET_QOS_MAC_CONFIGURATION_DO_MASK (0x400U) #define ENET_QOS_MAC_CONFIGURATION_DO_SHIFT (10U) /*! DO - Disable Receive Own - * 0b1..Disable Receive Own * 0b0..Enable Receive Own + * 0b1..Disable Receive Own */ #define ENET_QOS_MAC_CONFIGURATION_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DO_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DO_MASK) @@ -667,16 +670,16 @@ typedef struct { #define ENET_QOS_MAC_CONFIGURATION_DM_MASK (0x2000U) #define ENET_QOS_MAC_CONFIGURATION_DM_SHIFT (13U) /*! DM - Duplex Mode - * 0b1..Full-duplex mode * 0b0..Half-duplex mode + * 0b1..Full-duplex mode */ #define ENET_QOS_MAC_CONFIGURATION_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DM_MASK) #define ENET_QOS_MAC_CONFIGURATION_FES_MASK (0x4000U) #define ENET_QOS_MAC_CONFIGURATION_FES_SHIFT (14U) /*! FES - Speed - * 0b1..100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0 * 0b0..10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0 + * 0b1..100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0 */ #define ENET_QOS_MAC_CONFIGURATION_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_FES_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_FES_MASK) @@ -701,8 +704,8 @@ typedef struct { #define ENET_QOS_MAC_CONFIGURATION_JD_MASK (0x20000U) #define ENET_QOS_MAC_CONFIGURATION_JD_SHIFT (17U) /*! JD - Jabber Disable - * 0b1..Jabber is disabled * 0b0..Jabber is enabled + * 0b1..Jabber is disabled */ #define ENET_QOS_MAC_CONFIGURATION_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JD_MASK) @@ -718,8 +721,8 @@ typedef struct { #define ENET_QOS_MAC_CONFIGURATION_WD_MASK (0x80000U) #define ENET_QOS_MAC_CONFIGURATION_WD_SHIFT (19U) /*! WD - Watchdog Disable - * 0b1..Watchdog is disabled * 0b0..Watchdog is enabled + * 0b1..Watchdog is disabled */ #define ENET_QOS_MAC_CONFIGURATION_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_WD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_WD_MASK) @@ -761,14 +764,14 @@ typedef struct { #define ENET_QOS_MAC_CONFIGURATION_IPG_MASK (0x7000000U) #define ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT (24U) /*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission. - * 0b111..40 bit times IPG - * 0b110..48 bit times IPG - * 0b101..56 bit times IPG - * 0b100..64 bit times IPG - * 0b011..72 bit times IPG - * 0b010..80 bit times IPG - * 0b001..88 bit times IPG * 0b000..96 bit times IPG + * 0b001..88 bit times IPG + * 0b010..80 bit times IPG + * 0b011..72 bit times IPG + * 0b100..64 bit times IPG + * 0b101..56 bit times IPG + * 0b110..48 bit times IPG + * 0b111..40 bit times IPG */ #define ENET_QOS_MAC_CONFIGURATION_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPG_MASK) @@ -783,11 +786,11 @@ typedef struct { #define ENET_QOS_MAC_CONFIGURATION_SARC_MASK (0x70000000U) #define ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT (28U) /*! SARC - Source Address Insertion or Replacement Control + * 0b000..mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation * 0b010..Contents of MAC Addr-0 inserted in SA field * 0b011..Contents of MAC Addr-0 replaces SA field * 0b110..Contents of MAC Addr-1 inserted in SA field * 0b111..Contents of MAC Addr-1 replaces SA field - * 0b000..mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation */ #define ENET_QOS_MAC_CONFIGURATION_SARC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_SARC_MASK) /*! @} */ @@ -803,8 +806,8 @@ typedef struct { #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK (0x10000U) #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT (16U) /*! DCRCC - Disable CRC Checking for Received Packets - * 0b1..CRC Checking is disabled * 0b0..CRC Checking is enabled + * 0b1..CRC Checking is disabled */ #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK) @@ -892,8 +895,8 @@ typedef struct { #define ENET_QOS_MAC_PACKET_FILTER_DBF_MASK (0x20U) #define ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT (5U) /*! DBF - Disable Broadcast Packets - * 0b1..Disable Broadcast Packets * 0b0..Enable Broadcast Packets + * 0b1..Disable Broadcast Packets */ #define ENET_QOS_MAC_PACKET_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DBF_MASK) @@ -902,9 +905,9 @@ typedef struct { /*! PCF - Pass Control Packets These bits control the forwarding of all control packets (including * unicast and multicast Pause packets). * 0b00..MAC filters all control packets from reaching the application + * 0b01..MAC forwards all control packets except Pause packets to the application even if they fail the Address filter * 0b10..MAC forwards all control packets to the application even if they fail the Address filter * 0b11..MAC forwards the control packets that pass the Address filter - * 0b01..MAC forwards all control packets except Pause packets to the application even if they fail the Address filter */ #define ENET_QOS_MAC_PACKET_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PCF_MASK) @@ -951,8 +954,8 @@ typedef struct { #define ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK (0x200000U) #define ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT (21U) /*! DNTU - Drop Non-TCP/UDP over IP Packets - * 0b1..Drop Non-TCP/UDP over IP Packets * 0b0..Forward Non-TCP/UDP over IP Packets + * 0b1..Drop Non-TCP/UDP over IP Packets */ #define ENET_QOS_MAC_PACKET_FILTER_DNTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK) @@ -971,13 +974,6 @@ typedef struct { #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xFU) #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT (0U) /*! WTO - Watchdog Timeout - * 0b1000..10 KB - * 0b1001..11 KB - * 0b1010..12 KB - * 0b1011..13 KB - * 0b1100..14 KB - * 0b1101..15 KB - * 0b1110..16383 Bytes * 0b0000..2 KB * 0b0001..3 KB * 0b0010..4 KB @@ -986,6 +982,13 @@ typedef struct { * 0b0101..7 KB * 0b0110..8 KB * 0b0111..9 KB + * 0b1000..10 KB + * 0b1001..11 KB + * 0b1010..12 KB + * 0b1011..13 KB + * 0b1100..14 KB + * 0b1101..15 KB + * 0b1110..16383 Bytes * 0b1111..Reserved */ #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK) @@ -1031,8 +1034,8 @@ typedef struct { #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK (0x2U) #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT (1U) /*! CT - Command Type - * 0b1..Read operation * 0b0..Write operation + * 0b1..Read operation */ #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK) @@ -1062,10 +1065,10 @@ typedef struct { #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT (21U) /*! EVLS - Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the * outer VLAN Tag in received packet. - * 0b11..Always strip * 0b00..Do not strip - * 0b10..Strip if VLAN filter fails * 0b01..Strip if VLAN filter passes + * 0b10..Strip if VLAN filter fails + * 0b11..Always strip */ #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK) @@ -1105,10 +1108,10 @@ typedef struct { #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT (28U) /*! EIVLS - Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation * on inner VLAN Tag in received packet. - * 0b11..Always strip * 0b00..Do not strip - * 0b10..Strip if VLAN filter fails * 0b01..Strip if VLAN filter passes + * 0b10..Strip if VLAN filter fails + * 0b11..Always strip */ #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK) @@ -1140,16 +1143,16 @@ typedef struct { #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK (0x20000U) #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT (17U) /*! ETV - 12bits or 16bits VLAN comparison - * 0b1..12 bit VLAN comparison * 0b0..16 bit VLAN comparison + * 0b1..12 bit VLAN comparison */ #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK) #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK (0x40000U) #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT (18U) /*! DOVLTC - Disable VLAN Type Comparison - * 0b1..VLAN type comparison is disabled * 0b0..VLAN type comparison is enabled + * 0b1..VLAN type comparison is disabled */ #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK) @@ -1205,9 +1208,9 @@ typedef struct { /*! VLC - VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion, insertion, or * replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag * (bytes 15 and 16) of all transmitted packets with VLAN tags. + * 0b00..No VLAN tag deletion, insertion, or replacement * 0b01..VLAN tag deletion * 0b10..VLAN tag insertion - * 0b00..No VLAN tag deletion, insertion, or replacement * 0b11..VLAN tag replacement */ #define ENET_QOS_MAC_VLAN_INCL_VLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLC_MASK) @@ -1261,8 +1264,8 @@ typedef struct { #define ENET_QOS_MAC_VLAN_INCL_BUSY_MASK (0x80000000U) #define ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT (31U) /*! BUSY - Busy - * 0b1..Busy status detected * 0b0..Busy status not detected + * 0b1..Busy status detected */ #define ENET_QOS_MAC_VLAN_INCL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_BUSY_MASK) /*! @} */ @@ -1278,9 +1281,9 @@ typedef struct { #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK (0x30000U) #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT (16U) /*! VLC - VLAN Tag Control in Transmit Packets + * 0b00..No VLAN tag deletion, insertion, or replacement * 0b01..VLAN tag deletion * 0b10..VLAN tag insertion - * 0b00..No VLAN tag deletion, insertion, or replacement * 0b11..VLAN tag replacement */ #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK) @@ -1333,11 +1336,11 @@ typedef struct { #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U) #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U) /*! PLT - Pause Low Threshold - * 0b011..Pause Time minus 144 Slot Times (PT -144 slot times) - * 0b100..Pause Time minus 256 Slot Times (PT -256 slot times) + * 0b000..Pause Time minus 4 Slot Times (PT -4 slot times) * 0b001..Pause Time minus 28 Slot Times (PT -28 slot times) * 0b010..Pause Time minus 36 Slot Times (PT -36 slot times) - * 0b000..Pause Time minus 4 Slot Times (PT -4 slot times) + * 0b011..Pause Time minus 144 Slot Times (PT -144 slot times) + * 0b100..Pause Time minus 256 Slot Times (PT -256 slot times) * 0b101..Pause Time minus 512 Slot Times (PT -512 slot times) * 0b110..Reserved */ @@ -1346,8 +1349,8 @@ typedef struct { #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U) #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U) /*! DZPQ - Disable Zero-Quanta Pause - * 0b1..Zero-Quanta Pause packet generation is disabled * 0b0..Zero-Quanta Pause packet generation is enabled + * 0b1..Zero-Quanta Pause packet generation is disabled */ #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK) @@ -1644,120 +1647,120 @@ typedef struct { #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK (0x1U) #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT (0U) /*! RGSMIIIS - RGMII or SMII Interrupt Status - * 0b1..RGMII or SMII Interrupt Status is active * 0b0..RGMII or SMII Interrupt Status is not active + * 0b1..RGMII or SMII Interrupt Status is active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK) #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK (0x8U) #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT (3U) /*! PHYIS - PHY Interrupt - * 0b1..PHY Interrupt detected * 0b0..PHY Interrupt not detected + * 0b1..PHY Interrupt detected */ #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK) #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK (0x10U) #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT (4U) /*! PMTIS - PMT Interrupt Status - * 0b1..PMT Interrupt status active * 0b0..PMT Interrupt status not active + * 0b1..PMT Interrupt status active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK) #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK (0x20U) #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT (5U) /*! LPIIS - LPI Interrupt Status - * 0b1..LPI Interrupt status active * 0b0..LPI Interrupt status not active + * 0b1..LPI Interrupt status active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK) #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK (0x100U) #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT (8U) /*! MMCIS - MMC Interrupt Status - * 0b1..MMC Interrupt status active * 0b0..MMC Interrupt status not active + * 0b1..MMC Interrupt status active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK) #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK (0x200U) #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT (9U) /*! MMCRXIS - MMC Receive Interrupt Status - * 0b1..MMC Receive Interrupt status active * 0b0..MMC Receive Interrupt status not active + * 0b1..MMC Receive Interrupt status active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK) #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK (0x400U) #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT (10U) /*! MMCTXIS - MMC Transmit Interrupt Status - * 0b1..MMC Transmit Interrupt status active * 0b0..MMC Transmit Interrupt status not active + * 0b1..MMC Transmit Interrupt status active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK) #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK (0x800U) #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT (11U) /*! MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status - * 0b1..MMC Receive Checksum Offload Interrupt status active * 0b0..MMC Receive Checksum Offload Interrupt status not active + * 0b1..MMC Receive Checksum Offload Interrupt status active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK) #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK (0x1000U) #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT (12U) /*! TSIS - Timestamp Interrupt Status - * 0b1..Timestamp Interrupt status active * 0b0..Timestamp Interrupt status not active + * 0b1..Timestamp Interrupt status active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK) #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK (0x2000U) #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT (13U) /*! TXSTSIS - Transmit Status Interrupt - * 0b1..Transmit Interrupt status active * 0b0..Transmit Interrupt status not active + * 0b1..Transmit Interrupt status active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK) #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK (0x4000U) #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT (14U) /*! RXSTSIS - Receive Status Interrupt - * 0b1..Receive Interrupt status active * 0b0..Receive Interrupt status not active + * 0b1..Receive Interrupt status active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK) #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK (0x20000U) #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT (17U) /*! FPEIS - Frame Preemption Interrupt Status - * 0b1..Frame Preemption Interrupt status active * 0b0..Frame Preemption Interrupt status not active + * 0b1..Frame Preemption Interrupt status active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK) #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK (0x40000U) #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT (18U) /*! MDIOIS - MDIO Interrupt Status - * 0b1..MDIO Interrupt status active * 0b0..MDIO Interrupt status not active + * 0b1..MDIO Interrupt status active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK) #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK (0x80000U) #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT (19U) /*! MFTIS - MMC FPE Transmit Interrupt Status - * 0b1..MMC FPE Transmit Interrupt status active * 0b0..MMC FPE Transmit Interrupt status not active + * 0b1..MMC FPE Transmit Interrupt status active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK) #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK (0x100000U) #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT (20U) /*! MFRIS - MMC FPE Receive Interrupt Status - * 0b1..MMC FPE Receive Interrupt status active * 0b0..MMC FPE Receive Interrupt status not active + * 0b1..MMC FPE Receive Interrupt status active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK) /*! @} */ @@ -1855,8 +1858,8 @@ typedef struct { /*! TJT - Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which * happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled) * and JD bit is reset in the MAC_CONFIGURATION register. - * 0b1..Transmit Jabber Timeout occurred * 0b0..No Transmit Jabber Timeout + * 0b1..Transmit Jabber Timeout occurred */ #define ENET_QOS_MAC_RX_TX_STATUS_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK) @@ -1864,8 +1867,8 @@ typedef struct { #define ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT (1U) /*! NCARR - No Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit * indicates that the carrier signal from the PHY is not present at the end of preamble transmission. - * 0b1..No carrier * 0b0..Carrier is present + * 0b1..No carrier */ #define ENET_QOS_MAC_RX_TX_STATUS_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK) @@ -1874,8 +1877,8 @@ typedef struct { /*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit * indicates that the loss of carrier occurred during packet transmission, that is, the phy_crs_i * signal was inactive for one or more transmission clock periods during packet transmission. - * 0b1..Loss of carrier * 0b0..Carrier is present + * 0b1..Loss of carrier */ #define ENET_QOS_MAC_RX_TX_STATUS_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK) @@ -1885,8 +1888,8 @@ typedef struct { * DC bit is set in the MAC_CONFIGURATION register, this bit indicates that the transmission * ended because of excessive deferral of over 24,288 bit times (155,680 in 1000/2500 Mbps mode or * when Jumbo packet is enabled). - * 0b1..Excessive deferral * 0b0..No Excessive deferral + * 0b1..Excessive deferral */ #define ENET_QOS_MAC_RX_TX_STATUS_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK) @@ -1895,8 +1898,8 @@ typedef struct { /*! LCOL - Late Collision When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit * indicates that the packet transmission aborted because a collision occurred after the collision * window (512 bytes including Preamble and Carrier Extension in GMII mode). - * 0b1..Late collision is sensed * 0b0..No collision + * 0b1..Late collision is sensed */ #define ENET_QOS_MAC_RX_TX_STATUS_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK) @@ -1905,8 +1908,8 @@ typedef struct { /*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this * bit indicates that the transmission aborted after 16 successive collisions while attempting * to transmit the current packet. - * 0b1..Excessive collision is sensed * 0b0..No collision + * 0b1..Excessive collision is sensed */ #define ENET_QOS_MAC_RX_TX_STATUS_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK) @@ -1915,8 +1918,8 @@ typedef struct { /*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048 * bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the * MAC_CONFIGURATION register. - * 0b1..Receive watchdog timed out * 0b0..No receive watchdog timeout + * 0b1..Receive watchdog timed out */ #define ENET_QOS_MAC_RX_TX_STATUS_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK) /*! @} */ @@ -1954,8 +1957,8 @@ typedef struct { #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT (5U) /*! MGKPRCVD - Magic Packet Received When this bit is set, it indicates that the power management * event is generated because of the reception of a magic packet. - * 0b1..Magic packet is received * 0b0..No Magic packet is received + * 0b1..Magic packet is received */ #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK) @@ -1963,8 +1966,8 @@ typedef struct { #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT (6U) /*! RWKPRCVD - Remote Wake-Up Packet Received When this bit is set, it indicates that the power * management event is generated because of the reception of a remote wake-up packet. - * 0b1..Remote wake-up packet is received * 0b0..Remote wake-up packet is received + * 0b1..Remote wake-up packet is received */ #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK) @@ -2020,8 +2023,8 @@ typedef struct { #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT (0U) /*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has * entered the LPI state because of the setting of the LPIEN bit. - * 0b1..Transmit LPI entry detected * 0b0..Transmit LPI entry not detected + * 0b1..Transmit LPI entry detected */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK) @@ -2029,8 +2032,8 @@ typedef struct { #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT (1U) /*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited * the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired. - * 0b1..Transmit LPI exit detected * 0b0..Transmit LPI exit not detected + * 0b1..Transmit LPI exit detected */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK) @@ -2038,8 +2041,8 @@ typedef struct { #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT (2U) /*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received * an LPI pattern and entered the LPI state. - * 0b1..Receive LPI entry detected * 0b0..Receive LPI entry not detected + * 0b1..Receive LPI entry detected */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK) @@ -2048,8 +2051,8 @@ typedef struct { /*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped * receiving the LPI pattern on the GMII interface, exited the LPI state, and resumed the normal * reception. - * 0b1..Receive LPI exit detected * 0b0..Receive LPI exit not detected + * 0b1..Receive LPI exit detected */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK) @@ -2057,16 +2060,16 @@ typedef struct { #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT (8U) /*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the * LPI pattern on the GMII interface. - * 0b1..Transmit LPI state detected * 0b0..Transmit LPI state not detected + * 0b1..Transmit LPI state detected */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK) #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK (0x200U) #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT (9U) /*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the GMII interface. - * 0b1..Receive LPI state detected * 0b0..Receive LPI state not detected + * 0b1..Receive LPI state detected */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK) @@ -2186,17 +2189,17 @@ typedef struct { #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK (0x10000U) #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT (16U) /*! LNKMOD - Link Mode This bit indicates the current mode of operation of the link. - * 0b1..Full-duplex mode * 0b0..Half-duplex mode + * 0b1..Full-duplex mode */ #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK) #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK (0x60000U) #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT (17U) /*! LNKSPEED - Link Speed This bit indicates the current speed of the link. - * 0b10..125 MHz * 0b00..2.5 MHz * 0b01..25 MHz + * 0b10..125 MHz * 0b11..Reserved */ #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK) @@ -2204,8 +2207,8 @@ typedef struct { #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK (0x80000U) #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT (19U) /*! LNKSTS - Link Status This bit indicates whether the link is up (1'b1) or down (1'b0). - * 0b1..Link up * 0b0..Link down + * 0b1..Link up */ #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK) /*! @} */ @@ -2231,8 +2234,8 @@ typedef struct { #define ENET_QOS_MAC_DEBUG_RPESTS_SHIFT (0U) /*! RPESTS - MAC GMII Receive Protocol Engine Status When this bit is set, it indicates that the MAC * GMII receive protocol engine is actively receiving data, and it is not in the Idle state. - * 0b1..MAC GMII Receive Protocol Engine Status detected * 0b0..MAC GMII Receive Protocol Engine Status not detected + * 0b1..MAC GMII Receive Protocol Engine Status detected */ #define ENET_QOS_MAC_DEBUG_RPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RPESTS_MASK) @@ -2249,18 +2252,18 @@ typedef struct { /*! TPESTS - MAC GMII or MII Transmit Protocol Engine Status When this bit is set, it indicates that * the MAC GMII or MII transmit protocol engine is actively transmitting data, and it is not in * the Idle state. - * 0b1..MAC GMII Transmit Protocol Engine Status detected * 0b0..MAC GMII Transmit Protocol Engine Status not detected + * 0b1..MAC GMII Transmit Protocol Engine Status detected */ #define ENET_QOS_MAC_DEBUG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TPESTS_MASK) #define ENET_QOS_MAC_DEBUG_TFCSTS_MASK (0x60000U) #define ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT (17U) /*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module. - * 0b10..Generating and transmitting a Pause control packet (in full-duplex mode) * 0b00..Idle state - * 0b11..Transferring input packet for transmission * 0b01..Waiting for one of the following: Status of the previous packet OR IPG or back off period to be over + * 0b10..Generating and transmitting a Pause control packet (in full-duplex mode) + * 0b11..Transferring input packet for transmission */ #define ENET_QOS_MAC_DEBUG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TFCSTS_MASK) /*! @} */ @@ -2271,20 +2274,20 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_MIISEL_MASK (0x1U) #define ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT (0U) /*! MIISEL - 10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation - * 0b1..10 or 100 Mbps support * 0b0..No 10 or 100 Mbps support + * 0b1..10 or 100 Mbps support */ #define ENET_QOS_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MIISEL_MASK) #define ENET_QOS_MAC_HW_FEAT_NRVF_MASK (0x7U) #define ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT (0U) /*! NRVF - Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected: + * 0b000..No Extended Rx VLAN Filters + * 0b001..4 Extended Rx VLAN Filters + * 0b010..8 Extended Rx VLAN Filters * 0b011..16 Extended Rx VLAN Filters * 0b100..24 Extended Rx VLAN Filters * 0b101..32 Extended Rx VLAN Filters - * 0b001..4 Extended Rx VLAN Filters - * 0b010..8 Extended Rx VLAN Filters - * 0b000..No Extended Rx VLAN Filters * 0b110..Reserved */ #define ENET_QOS_MAC_HW_FEAT_NRVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT)) & ENET_QOS_MAC_HW_FEAT_NRVF_MASK) @@ -2293,18 +2296,18 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U) /*! RXFIFOSIZE - MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in * bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7: - * 0b00011..1024 bytes * 0b00000..128 bytes - * 0b01010..128 KB - * 0b00111..16384 bytes - * 0b00100..2048 bytes * 0b00001..256 bytes - * 0b01011..256 KB - * 0b01000..32 KB - * 0b00101..4096 bytes * 0b00010..512 bytes - * 0b01001..64 KB + * 0b00011..1024 bytes + * 0b00100..2048 bytes + * 0b00101..4096 bytes * 0b00110..8192 bytes + * 0b00111..16384 bytes + * 0b01000..32 KB + * 0b01001..64 KB + * 0b01010..128 KB + * 0b01011..256 KB * 0b01100..Reserved */ #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK) @@ -2326,16 +2329,16 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK (0x2U) #define ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT (1U) /*! GMIISEL - 1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation - * 0b1..1000 Mbps support * 0b0..No 1000 Mbps support + * 0b1..1000 Mbps support */ #define ENET_QOS_MAC_HW_FEAT_GMIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK) #define ENET_QOS_MAC_HW_FEAT_HDSEL_MASK (0x4U) #define ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT (2U) /*! HDSEL - Half-duplex Support This bit is set to 1 when the half-duplex mode is selected - * 0b1..Half-duplex support * 0b0..No Half-duplex support + * 0b1..Half-duplex support */ #define ENET_QOS_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HDSEL_MASK) @@ -2343,8 +2346,8 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT (3U) /*! PCSSEL - PCS Registers (TBI, SGMII, or RTBI PHY interface) This bit is set to 1 when the TBI, * SGMII, or RTBI PHY interface option is selected - * 0b1..PCS Registers (TBI, SGMII, or RTBI PHY interface) * 0b0..No PCS Registers (TBI, SGMII, or RTBI PHY interface) + * 0b1..PCS Registers (TBI, SGMII, or RTBI PHY interface) */ #define ENET_QOS_MAC_HW_FEAT_PCSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK) @@ -2352,48 +2355,48 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT (4U) /*! CBTISEL - Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the * Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected. - * 0b1..Enable Queue/Channel based VLAN tag insertion on Tx feature is selected * 0b0..Enable Queue/Channel based VLAN tag insertion on Tx feature is not selected + * 0b1..Enable Queue/Channel based VLAN tag insertion on Tx feature is selected */ #define ENET_QOS_MAC_HW_FEAT_CBTISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK) #define ENET_QOS_MAC_HW_FEAT_VLHASH_MASK (0x10U) #define ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT (4U) /*! VLHASH - VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected - * 0b1..VLAN Hash Filter selected * 0b0..VLAN Hash Filter not selected + * 0b1..VLAN Hash Filter selected */ #define ENET_QOS_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_QOS_MAC_HW_FEAT_VLHASH_MASK) #define ENET_QOS_MAC_HW_FEAT_DVLAN_MASK (0x20U) #define ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT (5U) /*! DVLAN - Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected. - * 0b1..Double VLAN option is selected * 0b0..Double VLAN option is not selected + * 0b1..Double VLAN option is selected */ #define ENET_QOS_MAC_HW_FEAT_DVLAN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DVLAN_MASK) #define ENET_QOS_MAC_HW_FEAT_SMASEL_MASK (0x20U) #define ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT (5U) /*! SMASEL - SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected - * 0b1..SMA (MDIO) Interface selected * 0b0..SMA (MDIO) Interface not selected + * 0b1..SMA (MDIO) Interface selected */ #define ENET_QOS_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SMASEL_MASK) #define ENET_QOS_MAC_HW_FEAT_SPRAM_MASK (0x20U) #define ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT (5U) /*! SPRAM - Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected. - * 0b1..Single Port RAM feature is selected * 0b0..Single Port RAM feature is not selected + * 0b1..Single Port RAM feature is selected */ #define ENET_QOS_MAC_HW_FEAT_SPRAM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPRAM_MASK) #define ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK (0x40U) #define ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT (6U) /*! RWKSEL - PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected - * 0b1..PMT Remote Wake-up Packet Enable option is selected * 0b0..PMT Remote Wake-up Packet Enable option is not selected + * 0b1..PMT Remote Wake-up Packet Enable option is selected */ #define ENET_QOS_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK) @@ -2401,17 +2404,17 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U) /*! TXFIFOSIZE - MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in * bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7: - * 0b00011..1024 bytes * 0b00000..128 bytes - * 0b01010..128 KB - * 0b00111..16384 bytes - * 0b00100..2048 bytes * 0b00001..256 bytes - * 0b01000..32 KB - * 0b00101..4096 bytes * 0b00010..512 bytes - * 0b01001..64 KB + * 0b00011..1024 bytes + * 0b00100..2048 bytes + * 0b00101..4096 bytes * 0b00110..8192 bytes + * 0b00111..16384 bytes + * 0b01000..32 KB + * 0b01001..64 KB + * 0b01010..128 KB * 0b01011..Reserved */ #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK) @@ -2433,24 +2436,24 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK (0x80U) #define ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT (7U) /*! MGKSEL - PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected - * 0b1..PMT Magic Packet Enable option is selected * 0b0..PMT Magic Packet Enable option is not selected + * 0b1..PMT Magic Packet Enable option is selected */ #define ENET_QOS_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK) #define ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK (0x100U) #define ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT (8U) /*! MMCSEL - RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected - * 0b1..RMON Module Enable option is selected * 0b0..RMON Module Enable option is not selected + * 0b1..RMON Module Enable option is selected */ #define ENET_QOS_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK) #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U) #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U) /*! ARPOFFSEL - ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected - * 0b1..ARP Offload Enable option is selected * 0b0..ARP Offload Enable option is not selected + * 0b1..ARP Offload Enable option is selected */ #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK) @@ -2458,8 +2461,8 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT (9U) /*! PDUPSEL - Broadcast/Multicast Packet Duplication This bit is set to 1 when the * Broadcast/Multicast Packet Duplication feature is selected. - * 0b1..Broadcast/Multicast Packet Duplication feature is selected * 0b0..Broadcast/Multicast Packet Duplication feature is not selected + * 0b1..Broadcast/Multicast Packet Duplication feature is selected */ #define ENET_QOS_MAC_HW_FEAT_PDUPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK) @@ -2467,8 +2470,8 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT (10U) /*! FRPSEL - Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible * Programmable Receive Parser option is selected. - * 0b1..Flexible Receive Parser feature is selected * 0b0..Flexible Receive Parser feature is not selected + * 0b1..Flexible Receive Parser feature is selected */ #define ENET_QOS_MAC_HW_FEAT_FRPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK) @@ -2476,9 +2479,9 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT (11U) /*! FRPBS - Flexible Receive Parser Buffer size This field indicates the supported Max Number of * bytes of the packet data to be Parsed by Flexible Receive Parser. + * 0b00..64 Bytes * 0b01..128 Bytes * 0b10..256 Bytes - * 0b00..64 Bytes * 0b11..Reserved */ #define ENET_QOS_MAC_HW_FEAT_FRPBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPBS_MASK) @@ -2486,16 +2489,16 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_OSTEN_MASK (0x800U) #define ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT (11U) /*! OSTEN - One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected. - * 0b1..One-Step Timestamping feature is selected * 0b0..One-Step Timestamping feature is not selected + * 0b1..One-Step Timestamping feature is selected */ #define ENET_QOS_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_OSTEN_MASK) #define ENET_QOS_MAC_HW_FEAT_PTOEN_MASK (0x1000U) #define ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT (12U) /*! PTOEN - PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected. - * 0b1..PTP Offload feature is selected * 0b0..PTP Offload feature is not selected + * 0b1..PTP Offload feature is selected */ #define ENET_QOS_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PTOEN_MASK) @@ -2516,16 +2519,16 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_TSSEL_MASK (0x1000U) #define ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT (12U) /*! TSSEL - IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected - * 0b1..IEEE 1588-2008 Timestamp Enable option is selected * 0b0..IEEE 1588-2008 Timestamp Enable option is not selected + * 0b1..IEEE 1588-2008 Timestamp Enable option is selected */ #define ENET_QOS_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSEL_MASK) #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U) #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U) /*! ADVTHWORD - IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected - * 0b1..IEEE 1588 High Word Register option is selected * 0b0..IEEE 1588 High Word Register option is not selected + * 0b1..IEEE 1588 High Word Register option is selected */ #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK) @@ -2533,8 +2536,8 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT (13U) /*! EEESEL - Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient * Ethernet (EEE) option is selected - * 0b1..Energy Efficient Ethernet Enable option is selected * 0b0..Energy Efficient Ethernet Enable option is not selected + * 0b1..Energy Efficient Ethernet Enable option is selected */ #define ENET_QOS_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_EEESEL_MASK) @@ -2542,9 +2545,9 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT (13U) /*! FRPES - Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser * Entries supported by Flexible Receive Parser. + * 0b00..64 Entries * 0b01..128 Entries * 0b10..256 Entries - * 0b00..64 Entries * 0b11..Reserved */ #define ENET_QOS_MAC_HW_FEAT_FRPES(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPES_MASK) @@ -2563,16 +2566,16 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT (14U) /*! TXCOESEL - Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit * TCP/IP Checksum Insertion option is selected - * 0b1..Transmit Checksum Offload Enable option is selected * 0b0..Transmit Checksum Offload Enable option is not selected + * 0b1..Transmit Checksum Offload Enable option is selected */ #define ENET_QOS_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK) #define ENET_QOS_MAC_HW_FEAT_DCBEN_MASK (0x10000U) #define ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT (16U) /*! DCBEN - DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected - * 0b1..DCB Feature is selected * 0b0..DCB Feature is not selected + * 0b1..DCB Feature is selected */ #define ENET_QOS_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DCBEN_MASK) @@ -2580,28 +2583,28 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT (16U) /*! ESTSEL - Enhancements to Scheduling Traffic Enable This bit is set to 1 when the Enable * Enhancements to Scheduling Traffic feature is selected. - * 0b1..Enable Enhancements to Scheduling Traffic feature is selected * 0b0..Enable Enhancements to Scheduling Traffic feature is not selected + * 0b1..Enable Enhancements to Scheduling Traffic feature is selected */ #define ENET_QOS_MAC_HW_FEAT_ESTSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK) #define ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U) #define ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT (16U) /*! RXCOESEL - Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected - * 0b1..Receive Checksum Offload Enable option is selected * 0b0..Receive Checksum Offload Enable option is not selected + * 0b1..Receive Checksum Offload Enable option is selected */ #define ENET_QOS_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK) #define ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK (0xE0000U) #define ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT (17U) /*! ESTDEP - Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5 - * 0b101..1024 + * 0b000..No Depth configured + * 0b001..64 * 0b010..128 * 0b011..256 * 0b100..512 - * 0b001..64 - * 0b000..No Depth configured + * 0b101..1024 * 0b110..Reserved */ #define ENET_QOS_MAC_HW_FEAT_ESTDEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK) @@ -2609,8 +2612,8 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_SPHEN_MASK (0x20000U) #define ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT (17U) /*! SPHEN - Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected - * 0b1..Split Header Feature is selected * 0b0..Split Header Feature is not selected + * 0b1..Split Header Feature is selected */ #define ENET_QOS_MAC_HW_FEAT_SPHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPHEN_MASK) @@ -2625,8 +2628,8 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT (18U) /*! TSOEN - TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation * Offloading for TCP/IP Packets option is selected - * 0b1..TCP Segmentation Offload Feature is selected * 0b0..TCP Segmentation Offload Feature is not selected + * 0b1..TCP Segmentation Offload Feature is selected */ #define ENET_QOS_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSOEN_MASK) @@ -2647,16 +2650,16 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U) #define ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT (19U) /*! DBGMEMA - DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected - * 0b1..DMA Debug Registers option is selected * 0b0..DMA Debug Registers option is not selected + * 0b1..DMA Debug Registers option is selected */ #define ENET_QOS_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK) #define ENET_QOS_MAC_HW_FEAT_AVSEL_MASK (0x100000U) #define ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT (20U) /*! AVSEL - AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected. - * 0b1..AV Feature is selected * 0b0..AV Feature is not selected + * 0b1..AV Feature is selected */ #define ENET_QOS_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AVSEL_MASK) @@ -2675,8 +2678,8 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT (21U) /*! RAVSEL - Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video * Bridging option on Rx Side Only is selected. - * 0b1..Rx Side Only AV Feature is selected * 0b0..Rx Side Only AV Feature is not selected + * 0b1..Rx Side Only AV Feature is selected */ #define ENET_QOS_MAC_HW_FEAT_RAVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK) @@ -2684,8 +2687,8 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT (23U) /*! MACADR32SEL - MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 * MAC Address Registers (32-63) option is selected - * 0b1..MAC Addresses 32-63 Select option is selected * 0b0..MAC Addresses 32-63 Select option is not selected + * 0b1..MAC Addresses 32-63 Select option is selected */ #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK) @@ -2693,18 +2696,18 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT (23U) /*! POUOST - One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One * step timestamp for PTP over UDP/IP feature is selected. - * 0b1..One Step for PTP over UDP/IP Feature is selected * 0b0..One Step for PTP over UDP/IP Feature is not selected + * 0b1..One Step for PTP over UDP/IP Feature is selected */ #define ENET_QOS_MAC_HW_FEAT_POUOST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT)) & ENET_QOS_MAC_HW_FEAT_POUOST_MASK) #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U) #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U) /*! HASHTBLSZ - Hash Table Size This field indicates the size of the hash table: + * 0b00..No hash table + * 0b01..64 * 0b10..128 * 0b11..256 - * 0b01..64 - * 0b00..No hash table */ #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK) @@ -2712,19 +2715,19 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT (24U) /*! MACADR64SEL - MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 * MAC Address Registers (64-127) option is selected - * 0b1..MAC Addresses 64-127 Select option is selected * 0b0..MAC Addresses 64-127 Select option is not selected + * 0b1..MAC Addresses 64-127 Select option is selected */ #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK) #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U) #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U) /*! PPSOUTNUM - Number of PPS Outputs This field indicates the number of PPS outputs: + * 0b000..No PPS output * 0b001..1 PPS output * 0b010..2 PPS output * 0b011..3 PPS output * 0b100..4 PPS output - * 0b000..No PPS output * 0b101..Reserved */ #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK) @@ -2733,9 +2736,9 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U) /*! TSSTSSEL - Timestamp System Time Source This bit indicates the source of the Timestamp system * time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected - * 0b10..External - * 0b01..Internal * 0b00..Reserved + * 0b01..Internal + * 0b10..External * 0b11..Both */ #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK) @@ -2743,14 +2746,15 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_FPESEL_MASK (0x4000000U) #define ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT (26U) /*! FPESEL - Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected. - * 0b1..Frame Preemption Enable feature is selected * 0b0..Frame Preemption Enable feature is not selected + * 0b1..Frame Preemption Enable feature is selected */ #define ENET_QOS_MAC_HW_FEAT_FPESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FPESEL_MASK) #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK (0x78000000U) #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT (27U) /*! L3L4FNUM - Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters: + * 0b0000..No L3 or L4 Filter * 0b0001..1 L3 or L4 Filter * 0b0010..2 L3 or L4 Filters * 0b0011..3 L3 or L4 Filters @@ -2759,7 +2763,6 @@ typedef struct { * 0b0110..6 L3 or L4 Filters * 0b0111..7 L3 or L4 Filters * 0b1000..8 L3 or L4 Filters - * 0b0000..No L3 or L4 Filter */ #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK) @@ -2767,16 +2770,16 @@ typedef struct { #define ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT (27U) /*! SAVLANINS - Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and * VLAN Insertion on Tx option is selected - * 0b1..Source Address or VLAN Insertion Enable option is selected * 0b0..Source Address or VLAN Insertion Enable option is not selected + * 0b1..Source Address or VLAN Insertion Enable option is selected */ #define ENET_QOS_MAC_HW_FEAT_SAVLANINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK) #define ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK (0x8000000U) #define ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT (27U) /*! TBSSEL - Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected. - * 0b1..Time Based Scheduling Enable feature is selected * 0b0..Time Based Scheduling Enable feature is not selected + * 0b1..Time Based Scheduling Enable feature is selected */ #define ENET_QOS_MAC_HW_FEAT_TBSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK) @@ -2785,34 +2788,34 @@ typedef struct { /*! ACTPHYSEL - Active PHY Selected When you have multiple PHY interfaces in your configuration, * this field indicates the sampled value of phy_intf_sel_i during reset de-assertion. * 0b000..GMII - * 0b111..RevMII * 0b001..RGMII + * 0b010..SGMII + * 0b011..TBI * 0b100..RMII * 0b101..RTBI - * 0b010..SGMII * 0b110..SMII - * 0b011..TBI + * 0b111..RevMII */ #define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK) #define ENET_QOS_MAC_HW_FEAT_ASP_MASK (0x30000000U) #define ENET_QOS_MAC_HW_FEAT_ASP_SHIFT (28U) /*! ASP - Automotive Safety Package Following are the encoding for the different Safety features + * 0b00..No Safety features selected + * 0b01..Only "ECC protection for external memory" feature is selected * 0b10..All the Automotive Safety features are selected without the "Parity Port Enable for external interface" feature * 0b11..All the Automotive Safety features are selected with the "Parity Port Enable for external interface" feature - * 0b01..Only "ECC protection for external memory" feature is selected - * 0b00..No Safety features selected */ #define ENET_QOS_MAC_HW_FEAT_ASP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ASP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ASP_MASK) #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U) #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U) /*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs: + * 0b000..No auxiliary input * 0b001..1 auxiliary input * 0b010..2 auxiliary input * 0b011..3 auxiliary input * 0b100..4 auxiliary input - * 0b000..No auxiliary input * 0b101..Reserved */ #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK) @@ -2981,32 +2984,32 @@ typedef struct { #define ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK (0x10000U) #define ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT (16U) /*! RVER - Received Verify Frame Set when a Verify mPacket is received. - * 0b1..Received Verify Frame * 0b0..Not received Verify Frame + * 0b1..Received Verify Frame */ #define ENET_QOS_MAC_FPE_CTRL_STS_RVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK) #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK (0x20000U) #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT (17U) /*! RRSP - Received Respond Frame Set when a Respond mPacket is received. - * 0b1..Received Respond Frame * 0b0..Not received Respond Frame + * 0b1..Received Respond Frame */ #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK) #define ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK (0x40000U) #define ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT (18U) /*! TVER - Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field). - * 0b1..transmitted Verify Frame * 0b0..Not transmitted Verify Frame + * 0b1..transmitted Verify Frame */ #define ENET_QOS_MAC_FPE_CTRL_STS_TVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK) #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK (0x80000U) #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT (19U) /*! TRSP - Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field). - * 0b1..transmitted Respond Frame * 0b0..Not transmitted Respond Frame + * 0b1..transmitted Respond Frame */ #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK) /*! @} */ @@ -3153,8 +3156,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT (0U) /*! RXGBPKTIS - MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the * rxpacketcount_gb counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Receive Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK) @@ -3162,8 +3165,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT (1U) /*! RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the * rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive Good Bad Octet Counter Interrupt Status detected * 0b0..MMC Receive Good Bad Octet Counter Interrupt Status not detected + * 0b1..MMC Receive Good Bad Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK) @@ -3171,8 +3174,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT (2U) /*! RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status This bit is set when the * rxoctetcount_g counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive Good Octet Counter Interrupt Status detected * 0b0..MMC Receive Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive Good Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK) @@ -3180,8 +3183,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT (3U) /*! RXBCGPIS - MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the * rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive Broadcast Good Packet Counter Interrupt Status detected * 0b0..MMC Receive Broadcast Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Broadcast Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK) @@ -3189,8 +3192,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT (4U) /*! RXMCGPIS - MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the * rxmulticastpackets_g counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive Multicast Good Packet Counter Interrupt Status detected * 0b0..MMC Receive Multicast Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Multicast Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK) @@ -3198,8 +3201,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT (5U) /*! RXCRCERPIS - MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the * rxcrcerror counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive CRC Error Packet Counter Interrupt Status detected * 0b0..MMC Receive CRC Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive CRC Error Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK) @@ -3207,8 +3210,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT (6U) /*! RXALGNERPIS - MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when * the rxalignmenterror counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive Alignment Error Packet Counter Interrupt Status detected * 0b0..MMC Receive Alignment Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Alignment Error Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK) @@ -3216,8 +3219,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT (7U) /*! RXRUNTPIS - MMC Receive Runt Packet Counter Interrupt Status This bit is set when the * rxrunterror counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive Runt Packet Counter Interrupt Status detected * 0b0..MMC Receive Runt Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Runt Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK) @@ -3225,8 +3228,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT (8U) /*! RXJABERPIS - MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the * rxjabbererror counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive Jabber Error Packet Counter Interrupt Status detected * 0b0..MMC Receive Jabber Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Jabber Error Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK) @@ -3234,8 +3237,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT (9U) /*! RXUSIZEGPIS - MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when * the rxundersize_g counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive Undersize Good Packet Counter Interrupt Status detected * 0b0..MMC Receive Undersize Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Undersize Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK) @@ -3243,8 +3246,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT (10U) /*! RXOSIZEGPIS - MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the * rxoversize_g counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive Oversize Good Packet Counter Interrupt Status detected * 0b0..MMC Receive Oversize Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Oversize Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK) @@ -3252,8 +3255,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT (11U) /*! RX64OCTGBPIS - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set * when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK) @@ -3262,8 +3265,8 @@ typedef struct { /*! RX65T127OCTGBPIS - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit * is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum * value. - * 0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK) @@ -3272,8 +3275,8 @@ typedef struct { /*! RX128T255OCTGBPIS - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This * bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the * maximum value. - * 0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK) @@ -3282,8 +3285,8 @@ typedef struct { /*! RX256T511OCTGBPIS - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This * bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the * maximum value. - * 0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK) @@ -3292,8 +3295,8 @@ typedef struct { /*! RX512T1023OCTGBPIS - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This * bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the * maximum value. - * 0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK) @@ -3302,8 +3305,8 @@ typedef struct { /*! RX1024TMAXOCTGBPIS - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status * This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the * maximum value. - * 0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK) @@ -3311,8 +3314,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT (17U) /*! RXUCGPIS - MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the * rxunicastpackets_g counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive Unicast Good Packet Counter Interrupt Status detected * 0b0..MMC Receive Unicast Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Unicast Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK) @@ -3320,16 +3323,16 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT (18U) /*! RXLENERPIS - MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the * rxlengtherror counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive Length Error Packet Counter Interrupt Status detected * 0b0..MMC Receive Length Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Length Error Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK (0x80000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT (19U) /*! RXORANGEPIS - MMC Receive Out Of Range Error Packet Counter Interrupt Status. - * 0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Status detected * 0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK) @@ -3337,8 +3340,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT (20U) /*! RXPAUSPIS - MMC Receive Pause Packet Counter Interrupt Status This bit is set when the * rxpausepackets counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive Pause Packet Counter Interrupt Status detected * 0b0..MMC Receive Pause Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Pause Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK) @@ -3346,8 +3349,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT (21U) /*! RXFOVPIS - MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the * rxfifooverflow counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Status detected * 0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Status not detected + * 0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK) @@ -3355,8 +3358,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT (22U) /*! RXVLANGBPIS - MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the * rxvlanpackets_gb counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK) @@ -3364,8 +3367,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT (23U) /*! RXWDOGPIS - MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the * rxwatchdog error counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive Watchdog Error Packet Counter Interrupt Status detected * 0b0..MMC Receive Watchdog Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Watchdog Error Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK) @@ -3373,8 +3376,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT (24U) /*! RXRCVERRPIS - MMC Receive Error Packet Counter Interrupt Status This bit is set when the * rxrcverror counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive Error Packet Counter Interrupt Status detected * 0b0..MMC Receive Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Error Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK) @@ -3382,8 +3385,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT (25U) /*! RXCTRLPIS - MMC Receive Control Packet Counter Interrupt Status This bit is set when the * rxctrlpackets_g counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive Control Packet Counter Interrupt Status detected * 0b0..MMC Receive Control Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Control Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK) @@ -3391,8 +3394,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT (26U) /*! RXLPIUSCIS - MMC Receive LPI microsecond counter interrupt status This bit is set when the * Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive LPI microsecond Counter Interrupt Status detected * 0b0..MMC Receive LPI microsecond Counter Interrupt Status not detected + * 0b1..MMC Receive LPI microsecond Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK) @@ -3400,8 +3403,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT (27U) /*! RXLPITRCIS - MMC Receive LPI transition counter interrupt status This bit is set when the * Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive LPI transition Counter Interrupt Status detected * 0b0..MMC Receive LPI transition Counter Interrupt Status not detected + * 0b1..MMC Receive LPI transition Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK) /*! @} */ @@ -3413,8 +3416,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT (0U) /*! TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the * txoctetcount_gb counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Good Bad Octet Counter Interrupt Status detected * 0b0..MMC Transmit Good Bad Octet Counter Interrupt Status not detected + * 0b1..MMC Transmit Good Bad Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK) @@ -3422,8 +3425,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT (1U) /*! TXGBPKTIS - MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the * txpacketcount_gb counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Transmit Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK) @@ -3431,8 +3434,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT (2U) /*! TXBCGPIS - MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the * txbroadcastpackets_g counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Status detected * 0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK) @@ -3440,8 +3443,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT (3U) /*! TXMCGPIS - MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the * txmulticastpackets_g counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Multicast Good Packet Counter Interrupt Status detected * 0b0..MMC Transmit Multicast Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Multicast Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK) @@ -3449,8 +3452,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT (4U) /*! TX64OCTGBPIS - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set * when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK) @@ -3459,8 +3462,8 @@ typedef struct { /*! TX65T127OCTGBPIS - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This * bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it * reaches the maximum value. - * 0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK) @@ -3469,8 +3472,8 @@ typedef struct { /*! TX128T255OCTGBPIS - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This * bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the * maximum value. - * 0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK) @@ -3479,8 +3482,8 @@ typedef struct { /*! TX256T511OCTGBPIS - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This * bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the * maximum value. - * 0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK) @@ -3489,8 +3492,8 @@ typedef struct { /*! TX512T1023OCTGBPIS - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status * This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the * maximum value. - * 0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK) @@ -3499,8 +3502,8 @@ typedef struct { /*! TX1024TMAXOCTGBPIS - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status * This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or * the maximum value. - * 0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK) @@ -3508,8 +3511,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT (10U) /*! TXUCGBPIS - MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when * the txunicastpackets_gb counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK) @@ -3517,8 +3520,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT (11U) /*! TXMCGBPIS - MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when * the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK) @@ -3526,8 +3529,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT (12U) /*! TXBCGBPIS - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when * the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status detected * 0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK) @@ -3535,8 +3538,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT (13U) /*! TXUFLOWERPIS - MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when * the txunderflowerror counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Underflow Error Packet Counter Interrupt Status detected * 0b0..MMC Transmit Underflow Error Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Underflow Error Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK) @@ -3544,8 +3547,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT (14U) /*! TXSCOLGPIS - MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set * when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Status detected * 0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK) @@ -3553,8 +3556,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT (15U) /*! TXMCOLGPIS - MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is * set when the txmulticol_g counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status detected * 0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK) @@ -3562,8 +3565,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT (16U) /*! TXDEFPIS - MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the * txdeferred counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Deferred Packet Counter Interrupt Status detected * 0b0..MMC Transmit Deferred Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Deferred Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK) @@ -3571,8 +3574,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT (17U) /*! TXLATCOLPIS - MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when * the txlatecol counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Late Collision Packet Counter Interrupt Status detected * 0b0..MMC Transmit Late Collision Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Late Collision Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK) @@ -3580,8 +3583,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT (18U) /*! TXEXCOLPIS - MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set * when the txexesscol counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Status detected * 0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK) @@ -3589,8 +3592,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT (19U) /*! TXCARERPIS - MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the * txcarriererror counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Carrier Error Packet Counter Interrupt Status detected * 0b0..MMC Transmit Carrier Error Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Carrier Error Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK) @@ -3598,8 +3601,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT (20U) /*! TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status This bit is set when the * txoctetcount_g counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Good Octet Counter Interrupt Status detected * 0b0..MMC Transmit Good Octet Counter Interrupt Status not detected + * 0b1..MMC Transmit Good Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK) @@ -3607,8 +3610,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT (21U) /*! TXGPKTIS - MMC Transmit Good Packet Counter Interrupt Status This bit is set when the * txpacketcount_g counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Good Packet Counter Interrupt Status detected * 0b0..MMC Transmit Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK) @@ -3616,8 +3619,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT (22U) /*! TXEXDEFPIS - MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set * when the txexcessdef counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Status detected * 0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK) @@ -3625,8 +3628,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT (23U) /*! TXPAUSPIS - MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the * txpausepacketserror counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Pause Packet Counter Interrupt Status detected * 0b0..MMC Transmit Pause Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Pause Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK) @@ -3634,8 +3637,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT (24U) /*! TXVLANGPIS - MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the * txvlanpackets_g counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit VLAN Good Packet Counter Interrupt Status detected * 0b0..MMC Transmit VLAN Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit VLAN Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK) @@ -3643,8 +3646,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT (25U) /*! TXOSIZEGPIS - MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when * the txoversize_g counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit Oversize Good Packet Counter Interrupt Status detected * 0b0..MMC Transmit Oversize Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Oversize Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK) @@ -3652,8 +3655,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT (26U) /*! TXLPIUSCIS - MMC Transmit LPI microsecond counter interrupt status This bit is set when the * Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit LPI microsecond Counter Interrupt Status detected * 0b0..MMC Transmit LPI microsecond Counter Interrupt Status not detected + * 0b1..MMC Transmit LPI microsecond Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK) @@ -3661,8 +3664,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT (27U) /*! TXLPITRCIS - MMC Transmit LPI transition counter interrupt status This bit is set when the * Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Transmit LPI transition Counter Interrupt Status detected * 0b0..MMC Transmit LPI transition Counter Interrupt Status not detected + * 0b1..MMC Transmit LPI transition Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK) /*! @} */ @@ -5066,8 +5069,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT (0U) /*! RXIPV4GPIS - MMC Receive IPV4 Good Packet Counter Interrupt Status This bit is set when the * rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive IPV4 Good Packet Counter Interrupt Status detected * 0b0..MMC Receive IPV4 Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK) @@ -5075,8 +5078,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT (1U) /*! RXIPV4HERPIS - MMC Receive IPV4 Header Error Packet Counter Interrupt Status This bit is set * when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Status detected * 0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK) @@ -5084,8 +5087,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT (2U) /*! RXIPV4NOPAYPIS - MMC Receive IPV4 No Payload Packet Counter Interrupt Status This bit is set * when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Status detected * 0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK) @@ -5093,8 +5096,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT (3U) /*! RXIPV4FRAGPIS - MMC Receive IPV4 Fragmented Packet Counter Interrupt Status This bit is set when * the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status detected * 0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK) @@ -5103,8 +5106,8 @@ typedef struct { /*! RXIPV4UDSBLPIS - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status This bit * is set when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum * value. - * 0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status detected * 0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK) @@ -5112,8 +5115,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT (5U) /*! RXIPV6GPIS - MMC Receive IPV6 Good Packet Counter Interrupt Status This bit is set when the * rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive IPV6 Good Packet Counter Interrupt Status detected * 0b0..MMC Receive IPV6 Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK) @@ -5121,8 +5124,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT (6U) /*! RXIPV6HERPIS - MMC Receive IPV6 Header Error Packet Counter Interrupt Status This bit is set * when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Status detected * 0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK) @@ -5130,8 +5133,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT (7U) /*! RXIPV6NOPAYPIS - MMC Receive IPV6 No Payload Packet Counter Interrupt Status This bit is set * when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Status detected * 0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK) @@ -5139,8 +5142,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT (8U) /*! RXUDPGPIS - MC Receive UDP Good Packet Counter Interrupt Status This bit is set when the * rxudp_gd_pkts counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive UDP Good Packet Counter Interrupt Status detected * 0b0..MMC Receive UDP Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive UDP Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK) @@ -5148,8 +5151,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT (9U) /*! RXUDPERPIS - MMC Receive UDP Error Packet Counter Interrupt Status This bit is set when the * rxudp_err_pkts counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive UDP Error Packet Counter Interrupt Status detected * 0b0..MMC Receive UDP Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive UDP Error Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK) @@ -5157,8 +5160,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT (10U) /*! RXTCPGPIS - MMC Receive TCP Good Packet Counter Interrupt Status This bit is set when the * rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive TCP Good Packet Counter Interrupt Status detected * 0b0..MMC Receive TCP Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive TCP Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK) @@ -5166,8 +5169,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT (11U) /*! RXTCPERPIS - MMC Receive TCP Error Packet Counter Interrupt Status This bit is set when the * rxtcp_err_pkts counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive TCP Error Packet Counter Interrupt Status detected * 0b0..MMC Receive TCP Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive TCP Error Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK) @@ -5175,8 +5178,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT (12U) /*! RXICMPGPIS - MMC Receive ICMP Good Packet Counter Interrupt Status This bit is set when the * rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive ICMP Good Packet Counter Interrupt Status detected * 0b0..MMC Receive ICMP Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive ICMP Good Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK) @@ -5184,8 +5187,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT (13U) /*! RXICMPERPIS - MMC Receive ICMP Error Packet Counter Interrupt Status This bit is set when the * rxicmp_err_pkts counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive ICMP Error Packet Counter Interrupt Status detected * 0b0..MMC Receive ICMP Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive ICMP Error Packet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK) @@ -5193,8 +5196,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT (16U) /*! RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status This bit is set when the * rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive IPV4 Good Octet Counter Interrupt Status detected * 0b0..MMC Receive IPV4 Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Good Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK) @@ -5202,8 +5205,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT (17U) /*! RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status This bit is set when * the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Status detected * 0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK) @@ -5211,8 +5214,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT (18U) /*! RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status This bit is set when * the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Status detected * 0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK) @@ -5220,8 +5223,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT (19U) /*! RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status This bit is set when * the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status detected * 0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK) @@ -5230,8 +5233,8 @@ typedef struct { /*! RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status This bit * is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum * value. - * 0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status detected * 0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK) @@ -5239,8 +5242,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT (21U) /*! RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status This bit is set when the * rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive IPV6 Good Octet Counter Interrupt Status detected * 0b0..MMC Receive IPV6 Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 Good Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK) @@ -5248,8 +5251,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT (22U) /*! RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status This bit is set when * the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Status detected * 0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK) @@ -5257,8 +5260,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT (23U) /*! RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status This bit is set when * the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Status detected * 0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK) @@ -5266,8 +5269,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT (24U) /*! RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status This bit is set when the * rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive UDP Good Octet Counter Interrupt Status detected * 0b0..MMC Receive UDP Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive UDP Good Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK) @@ -5275,8 +5278,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT (25U) /*! RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status This bit is set when the * rxudp_err_octets counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive UDP Error Octet Counter Interrupt Status detected * 0b0..MMC Receive UDP Error Octet Counter Interrupt Status not detected + * 0b1..MMC Receive UDP Error Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK) @@ -5284,8 +5287,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT (26U) /*! RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status This bit is set when the * rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive TCP Good Octet Counter Interrupt Status detected * 0b0..MMC Receive TCP Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive TCP Good Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK) @@ -5293,8 +5296,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT (27U) /*! RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status This bit is set when the * rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive TCP Error Octet Counter Interrupt Status detected * 0b0..MMC Receive TCP Error Octet Counter Interrupt Status not detected + * 0b1..MMC Receive TCP Error Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK) @@ -5302,8 +5305,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT (28U) /*! RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status This bit is set when the * rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive ICMP Good Octet Counter Interrupt Status detected * 0b0..MMC Receive ICMP Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive ICMP Good Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK) @@ -5311,8 +5314,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT (29U) /*! RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status This bit is set when the * rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Receive ICMP Error Octet Counter Interrupt Status detected * 0b0..MMC Receive ICMP Error Octet Counter Interrupt Status not detected + * 0b1..MMC Receive ICMP Error Octet Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK) /*! @} */ @@ -5606,8 +5609,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT (0U) /*! FCIS - MMC Tx FPE Fragment Counter Interrupt status This bit is set when the * Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Tx FPE Fragment Counter Interrupt status detected * 0b0..MMC Tx FPE Fragment Counter Interrupt status not detected + * 0b1..MMC Tx FPE Fragment Counter Interrupt status detected */ #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK) @@ -5615,8 +5618,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT (1U) /*! HRCIS - MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr * counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Tx Hold Request Counter Interrupt Status detected * 0b0..MMC Tx Hold Request Counter Interrupt Status not detected + * 0b1..MMC Tx Hold Request Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK) /*! @} */ @@ -5671,8 +5674,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT (0U) /*! PAECIS - MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the * Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Rx Packet Assembly Error Counter Interrupt Status detected * 0b0..MMC Rx Packet Assembly Error Counter Interrupt Status not detected + * 0b1..MMC Rx Packet Assembly Error Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK) @@ -5680,8 +5683,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT (1U) /*! PSECIS - MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the * Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Rx Packet SMD Error Counter Interrupt Status detected * 0b0..MMC Rx Packet SMD Error Counter Interrupt Status not detected + * 0b1..MMC Rx Packet SMD Error Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK) @@ -5689,8 +5692,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT (2U) /*! PAOCIS - MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the * Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Rx Packet Assembly OK Counter Interrupt Status detected * 0b0..MMC Rx Packet Assembly OK Counter Interrupt Status not detected + * 0b1..MMC Rx Packet Assembly OK Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK) @@ -5698,8 +5701,8 @@ typedef struct { #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT (3U) /*! FCIS - MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the * Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. - * 0b1..MMC Rx FPE Fragment Counter Interrupt Status detected * 0b0..MMC Rx FPE Fragment Counter Interrupt Status not detected + * 0b1..MMC Rx FPE Fragment Counter Interrupt Status detected */ #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK) /*! @} */ @@ -7315,17 +7318,17 @@ typedef struct { #define ENET_QOS_MAC_INDIR_ACCESS_CTRL_COM_MASK (0x2U) #define ENET_QOS_MAC_INDIR_ACCESS_CTRL_COM_SHIFT (1U) /*! COM - Command type. Indicates the register access type. - * 0b1..Indicates a read operation * 0b0..Indicates a write operation + * 0b1..Indicates a read operation */ #define ENET_QOS_MAC_INDIR_ACCESS_CTRL_COM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INDIR_ACCESS_CTRL_COM_SHIFT)) & ENET_QOS_MAC_INDIR_ACCESS_CTRL_COM_MASK) #define ENET_QOS_MAC_INDIR_ACCESS_CTRL_AUTO_MASK (0x20U) #define ENET_QOS_MAC_INDIR_ACCESS_CTRL_AUTO_SHIFT (5U) /*! AUTO - Auto increment enable + * 0b0..AOFF is not incremented automatically. Software should program the correct Address Offset for each access. * 0b1..AOFF is incremented by 1. Software should ensure not to cause a wrap condition. Byte wise read/write is * not supported when auto increment is enabled. - * 0b0..AOFF is not incremented automatically. Software should program the correct Address Offset for each access. */ #define ENET_QOS_MAC_INDIR_ACCESS_CTRL_AUTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INDIR_ACCESS_CTRL_AUTO_SHIFT)) & ENET_QOS_MAC_INDIR_ACCESS_CTRL_AUTO_MASK) @@ -7626,8 +7629,8 @@ typedef struct { #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT (0U) /*! TSSOVF - Timestamp Seconds Overflow When this bit is set, it indicates that the seconds value of * the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF. - * 0b1..Timestamp Seconds Overflow status detected * 0b0..Timestamp Seconds Overflow status not detected + * 0b1..Timestamp Seconds Overflow status detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK) @@ -7636,16 +7639,16 @@ typedef struct { /*! TSTARGT0 - Timestamp Target Time Reached When set, this bit indicates that the value of system * time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and * MAC_PPS0_Target_Time_Nanoseconds registers. - * 0b1..Timestamp Target Time Reached status detected * 0b0..Timestamp Target Time Reached status not detected + * 0b1..Timestamp Target Time Reached status detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK) #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK (0x4U) #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT (2U) /*! AUXTSTRIG - Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO. - * 0b1..Auxiliary Timestamp Trigger Snapshot status detected * 0b0..Auxiliary Timestamp Trigger Snapshot status not detected + * 0b1..Auxiliary Timestamp Trigger Snapshot status detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK) @@ -7653,8 +7656,8 @@ typedef struct { #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT (3U) /*! TSTRGTERR0 - Timestamp Target Time Error This bit is set when the latest target time programmed * in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses. - * 0b1..Timestamp Target Time Error status detected * 0b0..Timestamp Target Time Error status not detected + * 0b1..Timestamp Target Time Error status detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK) @@ -7663,8 +7666,8 @@ typedef struct { /*! TSTARGT1 - Timestamp Target Time Reached for Target Time PPS1 When set, this bit indicates that * the value of system time is greater than or equal to the value specified in the * MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers. - * 0b1..Timestamp Target Time Reached for Target Time PPS1 status detected * 0b0..Timestamp Target Time Reached for Target Time PPS1 status not detected + * 0b1..Timestamp Target Time Reached for Target Time PPS1 status detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK) @@ -7672,8 +7675,8 @@ typedef struct { #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT (5U) /*! TSTRGTERR1 - Timestamp Target Time Error This bit is set when the latest target time programmed * in the MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers elapses. - * 0b1..Timestamp Target Time Error status detected * 0b0..Timestamp Target Time Error status not detected + * 0b1..Timestamp Target Time Error status detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK) @@ -7682,8 +7685,8 @@ typedef struct { /*! TSTARGT2 - Timestamp Target Time Reached for Target Time PPS2 When set, this bit indicates that * the value of system time is greater than or equal to the value specified in the * MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers. - * 0b1..Timestamp Target Time Reached for Target Time PPS2 status detected * 0b0..Timestamp Target Time Reached for Target Time PPS2 status not detected + * 0b1..Timestamp Target Time Reached for Target Time PPS2 status detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK) @@ -7691,8 +7694,8 @@ typedef struct { #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT (7U) /*! TSTRGTERR2 - Timestamp Target Time Error This bit is set when the latest target time programmed * in the MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers elapses. - * 0b1..Timestamp Target Time Error status detected * 0b0..Timestamp Target Time Error status not detected + * 0b1..Timestamp Target Time Error status detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK) @@ -7701,8 +7704,8 @@ typedef struct { /*! TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 When this bit is set, it indicates * that the value of system time is greater than or equal to the value specified in the * MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers. - * 0b1..Timestamp Target Time Reached for Target Time PPS3 status detected * 0b0..Timestamp Target Time Reached for Target Time PPS3 status not detected + * 0b1..Timestamp Target Time Reached for Target Time PPS3 status detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK) @@ -7710,8 +7713,8 @@ typedef struct { #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT (9U) /*! TSTRGTERR3 - Timestamp Target Time Error This bit is set when the latest target time programmed * in the MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers elapses. - * 0b1..Timestamp Target Time Error status detected * 0b0..Timestamp Target Time Error status not detected + * 0b1..Timestamp Target Time Error status detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK) @@ -7720,8 +7723,8 @@ typedef struct { /*! TXTSSIS - Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop * transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in * the MAC_TX_TIMESTAMP_STATUS_NANOSECONDS and MAC_TX_TIMESTAMP_STATUS_SECONDS registers. - * 0b1..Tx Timestamp Status Interrupt status detected * 0b0..Tx Timestamp Status Interrupt status not detected + * 0b1..Tx Timestamp Status Interrupt status detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK) @@ -7736,8 +7739,8 @@ typedef struct { #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT (24U) /*! ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary * timestamp snapshot FIFO is full and external trigger was set. - * 0b1..Auxiliary Timestamp Snapshot Trigger Missed status detected * 0b0..Auxiliary Timestamp Snapshot Trigger Missed status not detected + * 0b1..Auxiliary Timestamp Snapshot Trigger Missed status detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK) @@ -7760,8 +7763,8 @@ typedef struct { #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK (0x80000000U) #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT (31U) /*! TXTSSMIS - Transmit Timestamp Status Missed - * 0b1..Transmit Timestamp Status Missed status detected * 0b0..Transmit Timestamp Status Missed status not detected + * 0b1..Transmit Timestamp Status Missed status detected */ #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK) /*! @} */ @@ -7950,20 +7953,20 @@ typedef struct { /*! TRGTMODSEL0 - Target Time Register Mode for PPS0 Output This field indicates the Target Time * registers (MAC_PPS0_TARGET_TIME_SECONDS and MAC_PPS0_TARGET_TIME_NANOSECONDS) mode for PPS0 * output signal: - * 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation * 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function * must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding * ptp_pps_o output port - * 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted * 0b01..Reserved + * 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation + * 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted */ #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK) #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK (0x80U) #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT (7U) /*! MCGREN0 - MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode. - * 0b1..0th PPS instance is enabled to operate in MCGR mode * 0b0..0th PPS instance is enabled to operate in PPS mode + * 0b1..0th PPS instance is enabled to operate in MCGR mode */ #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK) @@ -7977,12 +7980,12 @@ typedef struct { /*! TRGTMODSEL1 - Target Time Register Mode for PPS1 Output This field indicates the Target Time * registers (MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS) mode for PPS1 * output signal. - * 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation * 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function * must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding * ptp_pps_o output port - * 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted * 0b01..Reserved + * 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation + * 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted */ #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK) @@ -8004,12 +8007,12 @@ typedef struct { /*! TRGTMODSEL2 - Target Time Register Mode for PPS2 Output This field indicates the Target Time * registers (MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS) mode for PPS2 * output signal. - * 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation * 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function * must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding * ptp_pps_o output port - * 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted * 0b01..Reserved + * 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation + * 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted */ #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK) @@ -8031,12 +8034,12 @@ typedef struct { /*! TRGTMODSEL3 - Target Time Register Mode for PPS3 Output This field indicates the Target Time * registers (MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS) mode for PPS3 * output signal. - * 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation * 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function * must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding * ptp_pps_o output port - * 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted * 0b01..Reserved + * 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation + * 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted */ #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK) @@ -8067,8 +8070,8 @@ typedef struct { #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT (31U) /*! TRGTBUSY0 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the * PPS_CONTROL register is programmed to 010 or 011. - * 0b1..PPS Target Time Register Busy is detected * 0b0..PPS Target Time Register Busy status is not detected + * 0b1..PPS Target Time Register Busy is detected */ #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK) /*! @} */ @@ -8114,8 +8117,8 @@ typedef struct { #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT (31U) /*! TRGTBUSY1 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the * PPS_CONTROL register is programmed to 010 or 011. - * 0b1..PPS Target Time Register Busy is detected * 0b0..PPS Target Time Register Busy status is not detected + * 0b1..PPS Target Time Register Busy is detected */ #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK) /*! @} */ @@ -8161,8 +8164,8 @@ typedef struct { #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT (31U) /*! TRGTBUSY2 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the * PPS_CONTROL register is programmed to 010 or 011. - * 0b1..PPS Target Time Register Busy is detected * 0b0..PPS Target Time Register Busy status is not detected + * 0b1..PPS Target Time Register Busy is detected */ #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK) /*! @} */ @@ -8208,8 +8211,8 @@ typedef struct { #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT (31U) /*! TRGTBUSY3 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the * PPS_CONTROL register is programmed to 010 or 011. - * 0b1..PPS Target Time Register Busy is detected * 0b0..PPS Target Time Register Busy status is not detected + * 0b1..PPS Target Time Register Busy is detected */ #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK) /*! @} */ @@ -8286,8 +8289,8 @@ typedef struct { /*! DRRDIS - Disable PTO Delay Request/Response response generation When this bit is set, the Delay * Request and Delay response is not generated for received SYNC and Delay request packet * respectively, as required by the programmed mode. - * 0b1..PTO Delay Request/Response response generation is disabled * 0b0..PTO Delay Request/Response response generation is enabled + * 0b1..PTO Delay Request/Response response generation is disabled */ #define ENET_QOS_MAC_PTO_CONTROL_DRRDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK) @@ -8296,8 +8299,8 @@ typedef struct { /*! PDRDIS - Disable Peer Delay Response response generation When this bit is set, the Peer Delay * Response (Pdelay_Resp) response is not be generated for received Peer Delay Request (Pdelay_Req) * request packet, as required by the programmed mode. - * 0b1..Peer Delay Response response generation is disabled * 0b0..Peer Delay Response response generation is enabled + * 0b1..Peer Delay Response response generation is disabled */ #define ENET_QOS_MAC_PTO_CONTROL_PDRDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK) @@ -8347,13 +8350,13 @@ typedef struct { #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK (0x700U) #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT (8U) /*! DRSYNCR - Delay_Req to SYNC Ratio In Slave mode, it is used for controlling frequency of Delay_Req messages transmitted. - * 0b110..Reserved * 0b000..DelayReq generated for every received SYNC - * 0b100..for every 16 SYNC messages * 0b001..DelayReq generated every alternate reception of SYNC - * 0b101..for every 32 SYNC messages * 0b010..for every 4 SYNC messages * 0b011..for every 8 SYNC messages + * 0b100..for every 16 SYNC messages + * 0b101..for every 32 SYNC messages + * 0b110..Reserved */ #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK) @@ -8385,10 +8388,10 @@ typedef struct { #define ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK (0x60U) #define ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT (5U) /*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: + * 0b00..WRR algorithm + * 0b01..WFQ algorithm when DCB feature is selected.Otherwise, Reserved * 0b10..DWRR algorithm when DCB feature is selected.Otherwise, Reserved * 0b11..Strict priority algorithm - * 0b01..WFQ algorithm when DCB feature is selected.Otherwise, Reserved - * 0b00..WRR algorithm */ #define ENET_QOS_MTL_OPERATION_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK) @@ -8440,20 +8443,20 @@ typedef struct { #define ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK (0xCU) #define ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT (2U) /*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Write operation. - * 0b11..All four bytes are valid - * 0b10..Byte 0, Byte 1, and Byte 2 are valid - * 0b01..Byte 0 and Byte 1 are valid * 0b00..Byte 0 valid + * 0b01..Byte 0 and Byte 1 are valid + * 0b10..Byte 0, Byte 1, and Byte 2 are valid + * 0b11..All four bytes are valid */ #define ENET_QOS_MTL_DBG_CTL_BYTEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK) #define ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK (0x60U) #define ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT (5U) /*! PKTSTATE - Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO. - * 0b01..Control Word/Normal Status - * 0b11..EOP Data/EOP * 0b00..Packet Data + * 0b01..Control Word/Normal Status * 0b10..SOP Data/Last Status + * 0b11..EOP Data/EOP */ #define ENET_QOS_MTL_DBG_CTL_PKTSTATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK) @@ -8494,10 +8497,10 @@ typedef struct { #define ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK (0x3000U) #define ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT (12U) /*! FIFOSEL - FIFO Selected for Access This field indicates the FIFO selected for debug access: - * 0b11..Rx FIFO - * 0b10..TSO FIFO (cannot be accessed when SLVMOD is set) * 0b00..Tx FIFO * 0b01..Tx Status FIFO (only read access when SLVMOD is set) + * 0b10..TSO FIFO (cannot be accessed when SLVMOD is set) + * 0b11..Rx FIFO */ #define ENET_QOS_MTL_DBG_CTL_FIFOSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK) @@ -8528,28 +8531,28 @@ typedef struct { /*! FIFOBUSY - FIFO Busy When set, this bit indicates that a FIFO operation is in progress in the * MAC and content of the following fields is not valid: - All other fields of this register - All * fields of the MTL_FIFO_DEBUG_DATA register - * 0b1..FIFO Busy detected * 0b0..FIFO Busy not detected + * 0b1..FIFO Busy detected */ #define ENET_QOS_MTL_DBG_STS_FIFOBUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT)) & ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK) #define ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK (0x6U) #define ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT (1U) /*! PKTSTATE - Encoded Packet State This field is used to get the control or status information of the selected FIFO. - * 0b01..Control Word/Normal Status - * 0b11..EOP Data/EOP * 0b00..Packet Data + * 0b01..Control Word/Normal Status * 0b10..SOP Data/Last Status + * 0b11..EOP Data/EOP */ #define ENET_QOS_MTL_DBG_STS_PKTSTATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK) #define ENET_QOS_MTL_DBG_STS_BYTEEN_MASK (0x18U) #define ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT (3U) /*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Read operation. - * 0b11..All four bytes are valid - * 0b10..Byte 0, Byte 1, and Byte 2 are valid - * 0b01..Byte 0 and Byte 1 are valid * 0b00..Byte 0 valid + * 0b01..Byte 0 and Byte 1 are valid + * 0b10..Byte 0, Byte 1, and Byte 2 are valid + * 0b11..All four bytes are valid */ #define ENET_QOS_MTL_DBG_STS_BYTEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_STS_BYTEEN_MASK) @@ -8557,8 +8560,8 @@ typedef struct { #define ENET_QOS_MTL_DBG_STS_PKTI_SHIFT (8U) /*! PKTI - Receive Packet Available Interrupt Status When set, this bit indicates that MAC layer has * written the EOP of received packet to the Rx FIFO. - * 0b1..Receive Packet Available Interrupt Status detected * 0b0..Receive Packet Available Interrupt Status not detected + * 0b1..Receive Packet Available Interrupt Status detected */ #define ENET_QOS_MTL_DBG_STS_PKTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTI_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTI_MASK) @@ -8566,8 +8569,8 @@ typedef struct { #define ENET_QOS_MTL_DBG_STS_STSI_SHIFT (9U) /*! STSI - Transmit Status Available Interrupt Status When set, this bit indicates that the Slave * mode Tx packet is transmitted, and the status is available in Tx Status FIFO. - * 0b1..Transmit Status Available Interrupt Status detected * 0b0..Transmit Status Available Interrupt Status not detected + * 0b1..Transmit Status Available Interrupt Status detected */ #define ENET_QOS_MTL_DBG_STS_STSI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_STSI_SHIFT)) & ENET_QOS_MTL_DBG_STS_STSI_MASK) @@ -8594,64 +8597,64 @@ typedef struct { #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK (0x1U) #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT (0U) /*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0. - * 0b1..Queue 0 Interrupt status detected * 0b0..Queue 0 Interrupt status not detected + * 0b1..Queue 0 Interrupt status detected */ #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK) #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK (0x2U) #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT (1U) /*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1. - * 0b1..Queue 1 Interrupt status detected * 0b0..Queue 1 Interrupt status not detected + * 0b1..Queue 1 Interrupt status detected */ #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK) #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK (0x4U) #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT (2U) /*! Q2IS - Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2. - * 0b1..Queue 2 Interrupt status detected * 0b0..Queue 2 Interrupt status not detected + * 0b1..Queue 2 Interrupt status detected */ #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK) #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK (0x8U) #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT (3U) /*! Q3IS - Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3. - * 0b1..Queue 3 Interrupt status detected * 0b0..Queue 3 Interrupt status not detected + * 0b1..Queue 3 Interrupt status detected */ #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK) #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK (0x10U) #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT (4U) /*! Q4IS - Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4. - * 0b1..Queue 4 Interrupt status detected * 0b0..Queue 4 Interrupt status not detected + * 0b1..Queue 4 Interrupt status detected */ #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK) #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK (0x20000U) #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT (17U) /*! DBGIS - Debug Interrupt status This bit indicates an interrupt event during the slave access. - * 0b1..Debug Interrupt status detected * 0b0..Debug Interrupt status not detected + * 0b1..Debug Interrupt status detected */ #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK) #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK (0x40000U) #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT (18U) /*! ESTIS - EST (TAS- 802. - * 0b1..EST (TAS- 802.1Qbv) Interrupt status detected * 0b0..EST (TAS- 802.1Qbv) Interrupt status not detected + * 0b1..EST (TAS- 802.1Qbv) Interrupt status detected */ #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK) #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK (0x800000U) #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT (23U) /*! MTLPIS - MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block. - * 0b1..MTL Rx Parser Interrupt status detected * 0b0..MTL Rx Parser Interrupt status not detected + * 0b1..MTL Rx Parser Interrupt status detected */ #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK) /*! @} */ @@ -8823,8 +8826,8 @@ typedef struct { #define ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT (4U) /*! DDBF - Do not Drop frames during Frame Size Error When set, frames are not be dropped during * Head-of-Line blocking due to Frame Size Error (HLBF field of MTL_EST_STATUS register). - * 0b1..Do not Drop frames during Frame Size Error * 0b0..Drop frames during Frame Size Error + * 0b1..Do not Drop frames during Frame Size Error */ #define ENET_QOS_MTL_EST_CONTROL_DDBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DDBF_MASK) @@ -8842,10 +8845,10 @@ typedef struct { #define ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT (6U) /*! LCSE - Loop Count to report Scheduling Error Programmable number of GCL list iterations before * reporting an HLBS error defined in EST_STATUS register. - * 0b10..16 iterations - * 0b11..32 iterations * 0b00..4 iterations * 0b01..8 iterations + * 0b10..16 iterations + * 0b11..32 iterations */ #define ENET_QOS_MTL_EST_CONTROL_LCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_LCSE_MASK) @@ -8886,8 +8889,8 @@ typedef struct { #define ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT (0U) /*! SWLC - Switch to S/W owned list Complete When "1" indicates the hardware has successfully * switched to the SWOL, and the SWOL bit has been updated to that effect. - * 0b1..Switch to S/W owned list Complete detected * 0b0..Switch to S/W owned list Complete not detected + * 0b1..Switch to S/W owned list Complete detected */ #define ENET_QOS_MTL_EST_STATUS_SWLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWLC_MASK) @@ -8895,8 +8898,8 @@ typedef struct { #define ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT (1U) /*! BTRE - BTR Error When "1" indicates a programming error in the BTR of SWOL where the programmed * value is less than current time. - * 0b1..BTR Error detected * 0b0..BTR Error not detected + * 0b1..BTR Error detected */ #define ENET_QOS_MTL_EST_STATUS_BTRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRE_MASK) @@ -8906,8 +8909,8 @@ typedef struct { * Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or * equal to the duration needed for frame size (or frame fragment size when preemption is * enabled) transmission. - * 0b1..Head-Of-Line Blocking due to Frame Size detected * 0b0..Head-Of-Line Blocking due to Frame Size not detected + * 0b1..Head-Of-Line Blocking due to Frame Size detected */ #define ENET_QOS_MTL_EST_STATUS_HLBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBF_MASK) @@ -8915,8 +8918,8 @@ typedef struct { #define ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT (3U) /*! HLBS - Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration * and get scheduled even after 4 iterations of the GCL. - * 0b1..Head-Of-Line Blocking due to Scheduling detected * 0b0..Head-Of-Line Blocking due to Scheduling not detected + * 0b1..Head-Of-Line Blocking due to Scheduling detected */ #define ENET_QOS_MTL_EST_STATUS_HLBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBS_MASK) @@ -8925,8 +8928,8 @@ typedef struct { /*! CGCE - Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the * programmed Time Interval (TI) value after the optional Left Shifting is less than or equal to the * Cycle Time (CTR). - * 0b1..Constant Gate Control Error detected * 0b0..Constant Gate Control Error not detected + * 0b1..Constant Gate Control Error detected */ #define ENET_QOS_MTL_EST_STATUS_CGCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGCE_MASK) @@ -8934,8 +8937,8 @@ typedef struct { #define ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT (7U) /*! SWOL - S/W owned list When '0' indicates Gate control list number "0" is owned by software and * when "1" indicates the Gate Control list "1" is owned by the software. - * 0b1..Gate control list number "1" is owned by software * 0b0..Gate control list number "0" is owned by software + * 0b1..Gate control list number "1" is owned by software */ #define ENET_QOS_MTL_EST_STATUS_SWOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWOL_MASK) @@ -9054,8 +9057,8 @@ typedef struct { #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK (0x2U) #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT (1U) /*! R1W0 - Read '1', Write '0': When set to '1': Read Operation When set to '0': Write Operation. - * 0b1..Read Operation * 0b0..Write Operation + * 0b1..Read Operation */ #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK) @@ -9115,9 +9118,9 @@ typedef struct { /*! ESTEIEC - ECC Inject Error Control for EST Memory When EIEE bit of this register is set, * following are the errors inserted based on the value encoded in this field. * 0b00..Insert 1 bit error - * 0b11..Insert 1 bit error in address field * 0b01..Insert 2 bit errors * 0b10..Insert 3 bit errors + * 0b11..Insert 1 bit error in address field */ #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK) /*! @} */ @@ -9151,8 +9154,8 @@ typedef struct { #define ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK (0x10000000U) #define ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT (28U) /*! HRS - Hold/Release Status - 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State. - * 0b1..Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State * 0b0..Indicates a Set-and-Release-MAC operation was last executed and the pMAC is in Release State + * 0b1..Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State */ #define ENET_QOS_MTL_FPE_CTRL_STS_HRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK) /*! @} */ @@ -9198,8 +9201,8 @@ typedef struct { #define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT (31U) /*! RXPI - RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State * and waiting for a new packet for processing. - * 0b1..RX Parser in Idle state * 0b0..RX Parser not in Idle state + * 0b1..RX Parser in Idle state */ #define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK) /*! @} */ @@ -9212,8 +9215,8 @@ typedef struct { /*! NVEOVIS - Number of Valid Entries Overflow Interrupt Status While parsing if the Instruction * address found to be more than NVE (Number of Valid Entries in MTL_RXP_CONTROL register), then * this bit is set to 1. - * 0b1..Number of Valid Entries Overflow Interrupt Status detected * 0b0..Number of Valid Entries Overflow Interrupt Status not detected + * 0b1..Number of Valid Entries Overflow Interrupt Status detected */ #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK) @@ -9222,8 +9225,8 @@ typedef struct { /*! NPEOVIS - Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the * number of parsed entries found to be more than NPE[] (Number of Parseable Entries in * MTL_RXP_CONTROL register),then this bit is set to 1. - * 0b1..Number of Parsable Entries Overflow Interrupt Status detected * 0b0..Number of Parsable Entries Overflow Interrupt Status not detected + * 0b1..Number of Parsable Entries Overflow Interrupt Status detected */ #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK) @@ -9231,8 +9234,8 @@ typedef struct { #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT (2U) /*! FOOVIS - Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's * 'Frame Offset' found to be more than EOF offset, then then this bit is set. - * 0b1..Frame Offset Overflow Interrupt Status detected * 0b0..Frame Offset Overflow Interrupt Status not detected + * 0b1..Frame Offset Overflow Interrupt Status detected */ #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK) @@ -9240,8 +9243,8 @@ typedef struct { #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT (3U) /*! PDRFIS - Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the * packet by setting RF=1 in the instruction memory, then this bit is set to 1. - * 0b1..Packet Dropped due to RF Interrupt Status detected * 0b0..Packet Dropped due to RF Interrupt Status not detected + * 0b1..Packet Dropped due to RF Interrupt Status detected */ #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK) @@ -9290,8 +9293,8 @@ typedef struct { #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT (31U) /*! RXPDCOVF - Rx Parser Drop Counter Overflow Bit When set, this bit indicates that the * MTL_RXP_DROP_CNT (RXPDC) Counter field crossed the maximum limit. - * 0b1..Rx Parser Drop count overflow occurred * 0b0..Rx Parser Drop count overflow not occurred + * 0b1..Rx Parser Drop count overflow occurred */ #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK) /*! @} */ @@ -9311,8 +9314,8 @@ typedef struct { #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT (31U) /*! RXPECOVF - Rx Parser Error Counter Overflow Bit When set, this bit indicates that the * MTL_RXP_ERROR_CNT (RXPEC) Counter field crossed the maximum limit. - * 0b1..Rx Parser Error count overflow occurred * 0b0..Rx Parser Error count overflow not occurred + * 0b1..Rx Parser Error count overflow occurred */ #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK) /*! @} */ @@ -9337,8 +9340,8 @@ typedef struct { #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT (31U) /*! STARTBUSY - FRP Instruction Table Access Busy When this bit is set to 1 by the software then it * indicates to start the Read/Write operation from/to the Rx Parser Memory. - * 0b1..hardware is busy (Read/Write operation from/to the Rx Parser Memory) * 0b0..hardware not busy + * 0b1..hardware is busy (Read/Write operation from/to the Rx Parser Memory) */ #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK) /*! @} */ @@ -9363,8 +9366,8 @@ typedef struct { #define ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBCOF_MASK (0x80000000U) #define ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBCOF_SHIFT (31U) /*! RXPBCOF - Rx Parser bypass Counter Overflow Bit. Access restriction applies. Clears on read. Self-set to 1 on internal event. - * 0b1..Indicates that MTL_RXP_BYPASS_CNT[RXPBC] counter field has crossed the maximum limit * 0b0..Indicates that MTL_RXP_BYPASS_CNT[RXPBC] counter field has not crossed the maximum limit + * 0b1..Indicates that MTL_RXP_BYPASS_CNT[RXPBC] counter field has crossed the maximum limit */ #define ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBCOF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBCOF_SHIFT)) & ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBCOF_MASK) /*! @} */ @@ -9392,8 +9395,8 @@ typedef struct { #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U) /*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0. * 0b00..Not enabled - * 0b10..Enabled * 0b01..Enable in AV mode (Reserved in non-AV) + * 0b10..Enabled * 0b11..Reserved */ #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK) @@ -9401,14 +9404,14 @@ typedef struct { #define ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK (0x70U) #define ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT (4U) /*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. + * 0b000..32 + * 0b001..64 + * 0b010..96 * 0b011..128 * 0b100..192 * 0b101..256 - * 0b000..32 * 0b110..384 * 0b111..512 - * 0b001..64 - * 0b010..96 */ #define ENET_QOS_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK) @@ -9435,8 +9438,8 @@ typedef struct { #define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U) /*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue * Underflow Packet Counter field overflows, that is, it has crossed the maximum count. - * 0b1..Overflow detected for Underflow Packet Counter * 0b0..Overflow not detected for Underflow Packet Counter + * 0b1..Overflow detected for Underflow Packet Counter */ #define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK) /*! @} */ @@ -9453,18 +9456,18 @@ typedef struct { * indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because * of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue * when PFC is enabled - Reception of 802. - * 0b1..Transmit Queue in Pause status is detected * 0b0..Transmit Queue in Pause status is not detected + * 0b1..Transmit Queue in Pause status is detected */ #define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK) #define ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK (0x6U) #define ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT (1U) /*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: - * 0b11..Flushing the Tx queue because of the Packet Abort request from the MAC * 0b00..Idle state * 0b01..Read state (transferring data to the MAC transmitter) * 0b10..Waiting for pending Tx Status from the MAC transmitter + * 0b11..Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ENET_QOS_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK) @@ -9472,8 +9475,8 @@ typedef struct { #define ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT (3U) /*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx * Queue Write Controller is active, and it is transferring the data to the Tx Queue. - * 0b1..MTL Tx Queue Write Controller status is detected * 0b0..MTL Tx Queue Write Controller status is not detected + * 0b1..MTL Tx Queue Write Controller status is detected */ #define ENET_QOS_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK) @@ -9481,16 +9484,16 @@ typedef struct { #define ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT (4U) /*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue * is not empty and some data is left for transmission. - * 0b1..MTL Tx Queue Not Empty status is detected * 0b0..MTL Tx Queue Not Empty status is not detected + * 0b1..MTL Tx Queue Not Empty status is detected */ #define ENET_QOS_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK) #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U) #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U) /*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full. - * 0b1..MTL Tx Status FIFO Full status is detected * 0b0..MTL Tx Status FIFO Full status is not detected + * 0b1..MTL Tx Status FIFO Full status is detected */ #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK) @@ -9536,11 +9539,11 @@ typedef struct { #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U) #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U) /*! SLC - Slot Count - * 0b100..16 slots * 0b000..1 slot * 0b001..2 slots * 0b010..4 slots * 0b011..8 slots + * 0b100..16 slots * 0b101..Reserved */ #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK) @@ -9625,16 +9628,16 @@ typedef struct { #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U) /*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue * had an underflow while transmitting the packet. - * 0b1..Transmit Queue Underflow Interrupt Status detected * 0b0..Transmit Queue Underflow Interrupt Status not detected + * 0b1..Transmit Queue Underflow Interrupt Status detected */ #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK) #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U) #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U) /*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value. - * 0b1..Average Bits Per Slot Interrupt Status detected * 0b0..Average Bits Per Slot Interrupt Status not detected + * 0b1..Average Bits Per Slot Interrupt Status detected */ #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK) @@ -9659,8 +9662,8 @@ typedef struct { #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U) /*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had * an overflow while receiving the packet. - * 0b1..Receive Queue Overflow Interrupt Status detected * 0b0..Receive Queue Overflow Interrupt Status not detected + * 0b1..Receive Queue Overflow Interrupt Status detected */ #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK) @@ -9684,10 +9687,10 @@ typedef struct { /*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue * (in bytes): The received packet is transferred to the application or DMA when the packet size * within the MTL Rx queue is larger than the threshold. - * 0b11..128 - * 0b01..32 * 0b00..64 + * 0b01..32 * 0b10..96 + * 0b11..128 */ #define ENET_QOS_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK) @@ -9725,8 +9728,8 @@ typedef struct { /*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC * does not drop the packets which only have the errors detected by the Receive Checksum Offload * engine. - * 0b1..Dropping of TCP/IP Checksum Error Packets is disabled * 0b0..Dropping of TCP/IP Checksum Error Packets is enabled + * 0b1..Dropping of TCP/IP Checksum Error Packets is disabled */ #define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK) @@ -9778,8 +9781,8 @@ typedef struct { #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U) /*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue * Overflow Packet Counter field crossed the maximum limit. - * 0b1..Overflow Counter overflow detected * 0b0..Overflow Counter overflow not detected + * 0b1..Overflow Counter overflow detected */ #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK) @@ -9794,8 +9797,8 @@ typedef struct { #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT (27U) /*! MISCNTOVF - Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue * Missed Packet Counter crossed the maximum limit. - * 0b1..Missed Packet Counter overflow detected * 0b0..Missed Packet Counter overflow not detected + * 0b1..Missed Packet Counter overflow detected */ #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK) /*! @} */ @@ -9810,27 +9813,27 @@ typedef struct { #define ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT (0U) /*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL * Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue. - * 0b1..MTL Rx Queue Write Controller Active Status detected * 0b0..MTL Rx Queue Write Controller Active Status not detected + * 0b1..MTL Rx Queue Write Controller Active Status detected */ #define ENET_QOS_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK) #define ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK (0x6U) #define ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT (1U) /*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: - * 0b11..Flushing the packet data and status * 0b00..Idle state * 0b01..Reading packet data * 0b10..Reading packet status (or timestamp) + * 0b11..Flushing the packet data and status */ #define ENET_QOS_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK) #define ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK (0x30U) #define ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT (4U) /*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: - * 0b10..Rx Queue fill-level above flow-control activate threshold - * 0b01..Rx Queue fill-level below flow-control deactivate threshold * 0b00..Rx Queue empty + * 0b01..Rx Queue fill-level below flow-control deactivate threshold + * 0b10..Rx Queue fill-level above flow-control activate threshold * 0b11..Rx Queue full */ #define ENET_QOS_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK) @@ -10003,56 +10006,56 @@ typedef struct { #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK (0x1U) #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT (0U) /*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0. - * 0b1..DMA Channel 0 Interrupt Status detected * 0b0..DMA Channel 0 Interrupt Status not detected + * 0b1..DMA Channel 0 Interrupt Status detected */ #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK) #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK (0x2U) #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT (1U) /*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1. - * 0b1..DMA Channel 1 Interrupt Status detected * 0b0..DMA Channel 1 Interrupt Status not detected + * 0b1..DMA Channel 1 Interrupt Status detected */ #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK) #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U) #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT (2U) /*! DC2IS - DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2. - * 0b1..DMA Channel 2 Interrupt Status detected * 0b0..DMA Channel 2 Interrupt Status not detected + * 0b1..DMA Channel 2 Interrupt Status detected */ #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK) #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK (0x8U) #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT (3U) /*! DC3IS - DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3. - * 0b1..DMA Channel 3 Interrupt Status detected * 0b0..DMA Channel 3 Interrupt Status not detected + * 0b1..DMA Channel 3 Interrupt Status detected */ #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK) #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK (0x10U) #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT (4U) /*! DC4IS - DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4. - * 0b1..DMA Channel 4 Interrupt Status detected * 0b0..DMA Channel 4 Interrupt Status not detected + * 0b1..DMA Channel 4 Interrupt Status detected */ #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK) #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK (0x10000U) #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT (16U) /*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL. - * 0b1..MTL Interrupt Status detected * 0b0..MTL Interrupt Status not detected + * 0b1..MTL Interrupt Status detected */ #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK) #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK (0x20000U) #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT (17U) /*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC. - * 0b1..MAC Interrupt Status detected * 0b0..MAC Interrupt Status not detected + * 0b1..MAC Interrupt Status detected */ #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK) /*! @} */ @@ -10064,8 +10067,8 @@ typedef struct { #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT (0U) /*! AXWHSTS - AXI Master Write Channel When high, this bit indicates that the write channel of the * AXI master is active, and it is transferring data. - * 0b1..AXI Master Write Channel or AHB Master Status detected * 0b0..AXI Master Write Channel or AHB Master Status not detected + * 0b1..AXI Master Write Channel or AHB Master Status detected */ #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK) @@ -10073,92 +10076,92 @@ typedef struct { #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT (1U) /*! AXRHSTS - AXI Master Read Channel Status When high, this bit indicates that the read channel of * the AXI master is active, and it is transferring the data. - * 0b1..AXI Master Read Channel Status detected * 0b0..AXI Master Read Channel Status not detected + * 0b1..AXI Master Read Channel Status detected */ #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK) #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK (0xF00U) #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT (8U) /*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0. - * 0b0010..Reserved for future use - * 0b0101..Running (Closing the Rx Descriptor) + * 0b0000..Stopped (Reset or Stop Receive Command issued) * 0b0001..Running (Fetching Rx Transfer Descriptor) - * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) + * 0b0010..Reserved for future use * 0b0011..Running (Waiting for Rx packet) - * 0b0000..Stopped (Reset or Stop Receive Command issued) * 0b0100..Suspended (Rx Descriptor Unavailable) + * 0b0101..Running (Closing the Rx Descriptor) * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) */ #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK) #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK (0xF000U) #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT (12U) /*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0. - * 0b0101..Reserved for future use - * 0b0111..Running (Closing Tx Descriptor) + * 0b0000..Stopped (Reset or Stop Transmit Command issued) * 0b0001..Running (Fetching Tx Transfer Descriptor) - * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) * 0b0010..Running (Waiting for status) - * 0b0000..Stopped (Reset or Stop Transmit Command issued) - * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0111..Running (Closing Tx Descriptor) */ #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK) #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK (0xF0000U) #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT (16U) /*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1. - * 0b0010..Reserved for future use - * 0b0101..Running (Closing the Rx Descriptor) + * 0b0000..Stopped (Reset or Stop Receive Command issued) * 0b0001..Running (Fetching Rx Transfer Descriptor) - * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) + * 0b0010..Reserved for future use * 0b0011..Running (Waiting for Rx packet) - * 0b0000..Stopped (Reset or Stop Receive Command issued) * 0b0100..Suspended (Rx Descriptor Unavailable) + * 0b0101..Running (Closing the Rx Descriptor) * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) */ #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK) #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK (0xF00000U) #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT (20U) /*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1. - * 0b0101..Reserved for future use - * 0b0111..Running (Closing Tx Descriptor) + * 0b0000..Stopped (Reset or Stop Transmit Command issued) * 0b0001..Running (Fetching Tx Transfer Descriptor) - * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) * 0b0010..Running (Waiting for status) - * 0b0000..Stopped (Reset or Stop Transmit Command issued) - * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0111..Running (Closing Tx Descriptor) */ #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK) #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK (0xF000000U) #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT (24U) /*! RPS2 - DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2. - * 0b0010..Reserved for future use - * 0b0101..Running (Closing the Rx Descriptor) + * 0b0000..Stopped (Reset or Stop Receive Command issued) * 0b0001..Running (Fetching Rx Transfer Descriptor) - * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) + * 0b0010..Reserved for future use * 0b0011..Running (Waiting for Rx packet) - * 0b0000..Stopped (Reset or Stop Receive Command issued) * 0b0100..Suspended (Rx Descriptor Unavailable) + * 0b0101..Running (Closing the Rx Descriptor) * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) */ #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK) #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK (0xF0000000U) #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT (28U) /*! TPS2 - DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2. - * 0b0101..Reserved for future use - * 0b0111..Running (Closing Tx Descriptor) + * 0b0000..Stopped (Reset or Stop Transmit Command issued) * 0b0001..Running (Fetching Tx Transfer Descriptor) - * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) * 0b0010..Running (Waiting for status) - * 0b0000..Stopped (Reset or Stop Transmit Command issued) - * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0111..Running (Closing Tx Descriptor) */ #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK) /*! @} */ @@ -10169,56 +10172,56 @@ typedef struct { #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK (0xFU) #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT (0U) /*! RPS3 - DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3. - * 0b0010..Reserved for future use - * 0b0101..Running (Closing the Rx Descriptor) + * 0b0000..Stopped (Reset or Stop Receive Command issued) * 0b0001..Running (Fetching Rx Transfer Descriptor) - * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) + * 0b0010..Reserved for future use * 0b0011..Running (Waiting for Rx packet) - * 0b0000..Stopped (Reset or Stop Receive Command issued) * 0b0100..Suspended (Rx Descriptor Unavailable) + * 0b0101..Running (Closing the Rx Descriptor) * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) */ #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK) #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK (0xF0U) #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT (4U) /*! TPS3 - DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3. - * 0b0101..Reserved for future use - * 0b0111..Running (Closing Tx Descriptor) + * 0b0000..Stopped (Reset or Stop Transmit Command issued) * 0b0001..Running (Fetching Tx Transfer Descriptor) - * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) * 0b0010..Running (Waiting for status) - * 0b0000..Stopped (Reset or Stop Transmit Command issued) - * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0111..Running (Closing Tx Descriptor) */ #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK) #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK (0xF00U) #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT (8U) /*! RPS4 - DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4. - * 0b0010..Reserved for future use - * 0b0101..Running (Closing the Rx Descriptor) + * 0b0000..Stopped (Reset or Stop Receive Command issued) * 0b0001..Running (Fetching Rx Transfer Descriptor) - * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) + * 0b0010..Reserved for future use * 0b0011..Running (Waiting for Rx packet) - * 0b0000..Stopped (Reset or Stop Receive Command issued) * 0b0100..Suspended (Rx Descriptor Unavailable) + * 0b0101..Running (Closing the Rx Descriptor) * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) */ #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK) #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK (0xF000U) #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT (12U) /*! TPS4 - DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4. - * 0b0101..Reserved for future use - * 0b0111..Running (Closing Tx Descriptor) + * 0b0000..Stopped (Reset or Stop Transmit Command issued) * 0b0001..Running (Fetching Tx Transfer Descriptor) - * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) * 0b0010..Running (Waiting for status) - * 0b0000..Stopped (Reset or Stop Transmit Command issued) - * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0111..Running (Closing Tx Descriptor) */ #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK) /*! @} */ @@ -10360,8 +10363,8 @@ typedef struct { #define ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK (0x1U) #define ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT (0U) /*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state. - * 0b1..Start Transmission Command * 0b0..Stop Transmission Command + * 0b1..Start Transmission Command */ #define ENET_QOS_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK) @@ -10410,8 +10413,8 @@ typedef struct { #define ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT (0U) /*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from * the Receive list and processes the incoming packets. - * 0b1..Start Receive * 0b0..Stop Receive + * 0b1..Start Receive */ #define ENET_QOS_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK) @@ -10749,16 +10752,16 @@ typedef struct { #define ENET_QOS_DMA_CHX_STAT_TI_MASK (0x1U) #define ENET_QOS_DMA_CHX_STAT_TI_SHIFT (0U) /*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete. - * 0b1..Transmit Interrupt status detected * 0b0..Transmit Interrupt status not detected + * 0b1..Transmit Interrupt status detected */ #define ENET_QOS_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TI_MASK) #define ENET_QOS_DMA_CHX_STAT_TPS_MASK (0x2U) #define ENET_QOS_DMA_CHX_STAT_TPS_SHIFT (1U) /*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped. - * 0b1..Transmit Process Stopped status detected * 0b0..Transmit Process Stopped status not detected + * 0b1..Transmit Process Stopped status detected */ #define ENET_QOS_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TPS_MASK) @@ -10766,16 +10769,16 @@ typedef struct { #define ENET_QOS_DMA_CHX_STAT_TBU_SHIFT (2U) /*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next * descriptor in the Transmit list, and the DMA cannot acquire it. - * 0b1..Transmit Buffer Unavailable status detected * 0b0..Transmit Buffer Unavailable status not detected + * 0b1..Transmit Buffer Unavailable status detected */ #define ENET_QOS_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TBU_MASK) #define ENET_QOS_DMA_CHX_STAT_RI_MASK (0x40U) #define ENET_QOS_DMA_CHX_STAT_RI_SHIFT (6U) /*! RI - Receive Interrupt This bit indicates that the packet reception is complete. - * 0b1..Receive Interrupt status detected * 0b0..Receive Interrupt status not detected + * 0b1..Receive Interrupt status detected */ #define ENET_QOS_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RI_MASK) @@ -10783,16 +10786,16 @@ typedef struct { #define ENET_QOS_DMA_CHX_STAT_RBU_SHIFT (7U) /*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next * descriptor in the Receive list, and the DMA cannot acquire it. - * 0b1..Receive Buffer Unavailable status detected * 0b0..Receive Buffer Unavailable status not detected + * 0b1..Receive Buffer Unavailable status detected */ #define ENET_QOS_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RBU_MASK) #define ENET_QOS_DMA_CHX_STAT_RPS_MASK (0x100U) #define ENET_QOS_DMA_CHX_STAT_RPS_SHIFT (8U) /*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. - * 0b1..Receive Process Stopped status detected * 0b0..Receive Process Stopped status not detected + * 0b1..Receive Process Stopped status detected */ #define ENET_QOS_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RPS_MASK) @@ -10800,8 +10803,8 @@ typedef struct { #define ENET_QOS_DMA_CHX_STAT_RWT_SHIFT (9U) /*! RWT - Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048 * bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. - * 0b1..Receive Watchdog Timeout status detected * 0b0..Receive Watchdog Timeout status not detected + * 0b1..Receive Watchdog Timeout status detected */ #define ENET_QOS_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RWT_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RWT_MASK) @@ -10809,8 +10812,8 @@ typedef struct { #define ENET_QOS_DMA_CHX_STAT_ETI_SHIFT (10U) /*! ETI - Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the * transfer of packet data to the MTL TXFIFO memory. - * 0b1..Early Transmit Interrupt status detected * 0b0..Early Transmit Interrupt status not detected + * 0b1..Early Transmit Interrupt status detected */ #define ENET_QOS_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ETI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ETI_MASK) @@ -10818,16 +10821,16 @@ typedef struct { #define ENET_QOS_DMA_CHX_STAT_ERI_SHIFT (11U) /*! ERI - Early Receive Interrupt This bit when set indicates that the RxDMA has completed the * transfer of packet data to the memory. - * 0b1..Early Receive Interrupt status detected * 0b0..Early Receive Interrupt status not detected + * 0b1..Early Receive Interrupt status detected */ #define ENET_QOS_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ERI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ERI_MASK) #define ENET_QOS_DMA_CHX_STAT_FBE_MASK (0x1000U) #define ENET_QOS_DMA_CHX_STAT_FBE_SHIFT (12U) /*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). - * 0b1..Fatal Bus Error status detected * 0b0..Fatal Bus Error status not detected + * 0b1..Fatal Bus Error status detected */ #define ENET_QOS_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_FBE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_FBE_MASK) @@ -10837,8 +10840,8 @@ typedef struct { * descriptor error, which indicates invalid context in the middle of packet flow ( intermediate * descriptor) or all one's descriptor in Tx case and on Rx side it indicates DMA has read a descriptor * with either of the buffer address as ones which is considered to be invalid. - * 0b1..Context Descriptor Error status detected * 0b0..Context Descriptor Error status not detected + * 0b1..Context Descriptor Error status detected */ #define ENET_QOS_DMA_CHX_STAT_CDE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_CDE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_CDE_MASK) @@ -10849,8 +10852,8 @@ typedef struct { * register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive * Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context * Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit. - * 0b1..Abnormal Interrupt Summary status detected * 0b0..Abnormal Interrupt Summary status not detected + * 0b1..Abnormal Interrupt Summary status detected */ #define ENET_QOS_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_AIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_AIS_MASK) @@ -10861,8 +10864,8 @@ typedef struct { * register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive * Interrupt - Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt * enable is set in DMA_CH3_INTERRUPT_ENABLE register) affect the Normal Interrupt Summary bit. - * 0b1..Normal Interrupt Summary status detected * 0b0..Normal Interrupt Summary status not detected + * 0b1..Normal Interrupt Summary status detected */ #define ENET_QOS_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_NIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_NIS_MASK) @@ -10894,8 +10897,8 @@ typedef struct { #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U) #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U) /*! MFCO - Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. - * 0b1..Miss Frame Counter overflow occurred * 0b0..Miss Frame Counter overflow not occurred + * 0b1..Miss Frame Counter overflow occurred */ #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK) /*! @} */ @@ -10915,8 +10918,8 @@ typedef struct { #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT (31U) /*! RXPACOF - Rx Parser Accept Counter Overflow Bit When set, this bit indicates that the RXPAC * Counter field crossed the maximum limit. - * 0b1..Rx Parser Accept Counter overflow occurred * 0b0..Rx Parser Accept Counter overflow not occurred + * 0b1..Rx Parser Accept Counter overflow occurred */ #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK) /*! @} */ @@ -10958,5 +10961,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ENET_QOS_H_ */ +#endif /* PERI_ENET_QOS_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_FLEXIO.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_FLEXIO.h index d5ce40723d..8c390b8e5b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_FLEXIO.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_FLEXIO.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXIO ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file FLEXIO.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_FLEXIO.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for FLEXIO * * CMSIS Peripheral Access Layer for FLEXIO */ -#if !defined(FLEXIO_H_) -#define FLEXIO_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_FLEXIO_H_) +#define PERI_FLEXIO_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -224,10 +227,10 @@ typedef struct { __IO uint32_t PINFEN; /**< Pin Falling Edge Enable, offset: 0x5C */ __IO uint32_t PINOUTD; /**< Pin Output Data, offset: 0x60 */ __IO uint32_t PINOUTE; /**< Pin Output Enable, offset: 0x64 */ - __O uint32_t PINOUTDIS; /**< Pin Output Disable, offset: 0x68 */ - __O uint32_t PINOUTCLR; /**< Pin Output Clear, offset: 0x6C */ - __O uint32_t PINOUTSET; /**< Pin Output Set, offset: 0x70 */ - __O uint32_t PINOUTTOG; /**< Pin Output Toggle, offset: 0x74 */ + __IO uint32_t PINOUTDIS; /**< Pin Output Disable, offset: 0x68 */ + __IO uint32_t PINOUTCLR; /**< Pin Output Clear, offset: 0x6C */ + __IO uint32_t PINOUTSET; /**< Pin Output Set, offset: 0x70 */ + __IO uint32_t PINOUTTOG; /**< Pin Output Toggle, offset: 0x74 */ uint8_t RESERVED_5[8]; __IO uint32_t SHIFTCTL[FLEXIO_SHIFTCTL_COUNT]; /**< Shifter Control N, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_6[96]; @@ -970,5 +973,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* FLEXIO_H_ */ +#endif /* PERI_FLEXIO_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_FLEXSPI.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_FLEXSPI.h index 1599739d08..a7c5a13832 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_FLEXSPI.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_FLEXSPI.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXSPI ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file FLEXSPI.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_FLEXSPI.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for FLEXSPI * * CMSIS Peripheral Access Layer for FLEXSPI */ -#if !defined(FLEXSPI_H_) -#define FLEXSPI_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_FLEXSPI_H_) +#define PERI_FLEXSPI_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -210,7 +213,7 @@ typedef struct { __IO uint32_t IPCR0; /**< IP Control 0, offset: 0xA0 */ __IO uint32_t IPCR1; /**< IP Control 1, offset: 0xA4 */ uint8_t RESERVED_3[8]; - __O uint32_t IPCMD; /**< IP Command, offset: 0xB0 */ + __IO uint32_t IPCMD; /**< IP Command, offset: 0xB0 */ __IO uint32_t DLPR; /**< Data Learning Pattern, offset: 0xB4 */ __IO uint32_t IPRXFCR; /**< IP Receive FIFO Control, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP Transmit FIFO Control, offset: 0xBC */ @@ -598,9 +601,9 @@ typedef struct { #define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) /*! IPCMDDONE - IP-Triggered Command Sequences Execution Finished * 0b0..Interrupt condition has not occurred - * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt condition has occurred */ #define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) @@ -608,9 +611,9 @@ typedef struct { #define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) /*! IPCMDGE - IP-Triggered Command Sequences Grant Timeout * 0b0..Interrupt condition has not occurred - * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt condition has occurred */ #define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) @@ -618,9 +621,9 @@ typedef struct { #define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) /*! AHBCMDGE - AHB-Triggered Command Sequences Grant Timeout * 0b0..Interrupt condition has not occurred - * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt condition has occurred */ #define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) @@ -628,9 +631,9 @@ typedef struct { #define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) /*! IPCMDERR - IP-Triggered Command Sequences Error * 0b0..Interrupt condition has not occurred - * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt condition has occurred */ #define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) @@ -638,9 +641,9 @@ typedef struct { #define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) /*! AHBCMDERR - AHB-Triggered Command Sequences Error * 0b0..Interrupt condition has not occurred - * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt condition has occurred */ #define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) @@ -648,9 +651,9 @@ typedef struct { #define FLEXSPI_INTR_IPRXWA_SHIFT (5U) /*! IPRXWA - IP Receive FIFO Watermark Available * 0b0..Interrupt condition has not occurred - * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt condition has occurred */ #define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) @@ -658,9 +661,9 @@ typedef struct { #define FLEXSPI_INTR_IPTXWE_SHIFT (6U) /*! IPTXWE - IP Transmit FIFO Watermark Empty * 0b0..Interrupt condition has not occurred - * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt condition has occurred */ #define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) @@ -668,9 +671,9 @@ typedef struct { #define FLEXSPI_INTR_DATALEARNFAIL_SHIFT (7U) /*! DATALEARNFAIL - Data Learning Failed * 0b0..Interrupt condition has not occurred - * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt condition has occurred */ #define FLEXSPI_INTR_DATALEARNFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK) @@ -678,9 +681,9 @@ typedef struct { #define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) /*! SCKSTOPBYRD - SCLK Stopped Due To Full Receive FIFO * 0b0..Interrupt condition has not occurred - * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt condition has occurred */ #define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) @@ -688,9 +691,9 @@ typedef struct { #define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) /*! SCKSTOPBYWR - SCLK Stopped Due To Empty Transmit FIFO * 0b0..Interrupt condition has not occurred - * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt condition has occurred */ #define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) @@ -698,9 +701,9 @@ typedef struct { #define FLEXSPI_INTR_AHBBUSERROR_SHIFT (10U) /*! AHBBUSERROR - AHB Bus Error * 0b0..Interrupt condition has not occurred - * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt condition has occurred */ #define FLEXSPI_INTR_AHBBUSERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK) @@ -708,9 +711,9 @@ typedef struct { #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) /*! SEQTIMEOUT - Sequence Execution Timeout * 0b0..Interrupt condition has not occurred - * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt condition has occurred */ #define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) @@ -723,9 +726,9 @@ typedef struct { #define FLEXSPI_INTR_KEYERROR_SHIFT (13U) /*! KEYERROR - OTFAD Key Blob Processing Error * 0b0..Interrupt condition has not occurred - * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag + * 0b1..Interrupt condition has occurred */ #define FLEXSPI_INTR_KEYERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK) /*! @} */ @@ -1427,5 +1430,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* FLEXSPI_H_ */ +#endif /* PERI_FLEXSPI_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_FSB.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_FSB.h index fba512337e..1beeaec0f2 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_FSB.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_FSB.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for FSB ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file FSB.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_FSB.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for FSB * * CMSIS Peripheral Access Layer for FSB */ -#if !defined(FSB_H_) -#define FSB_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_FSB_H_) +#define PERI_FSB_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -344,5 +347,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* FSB_H_ */ +#endif /* PERI_FSB_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_GPC_CPU_CTRL.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_GPC_CPU_CTRL.h index 7fa5671bf3..bf805bc99b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_GPC_CPU_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_GPC_CPU_CTRL.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPC_CPU_CTRL ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file GPC_CPU_CTRL.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_GPC_CPU_CTRL.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for GPC_CPU_CTRL * * CMSIS Peripheral Access Layer for GPC_CPU_CTRL */ -#if !defined(GPC_CPU_CTRL_H_) -#define GPC_CPU_CTRL_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_GPC_CPU_CTRL_H_) +#define PERI_GPC_CPU_CTRL_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -1303,5 +1306,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* GPC_CPU_CTRL_H_ */ +#endif /* PERI_GPC_CPU_CTRL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_GPC_GLOBAL.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_GPC_GLOBAL.h index 37c7176a6a..c82a76f165 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_GPC_GLOBAL.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_GPC_GLOBAL.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPC_GLOBAL ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file GPC_GLOBAL.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_GPC_GLOBAL.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for GPC_GLOBAL * * CMSIS Peripheral Access Layer for GPC_GLOBAL */ -#if !defined(GPC_GLOBAL_H_) -#define GPC_GLOBAL_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_GPC_GLOBAL_H_) +#define PERI_GPC_GLOBAL_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -461,5 +464,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* GPC_GLOBAL_H_ */ +#endif /* PERI_GPC_GLOBAL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_I2S.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_I2S.h index 9bb79db3bd..340bf2f9da 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_I2S.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_I2S.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for I2S ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file I2S.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_I2S.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for I2S * * CMSIS Peripheral Access Layer for I2S */ -#if !defined(I2S_H_) -#define I2S_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_I2S_H_) +#define PERI_I2S_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -195,7 +198,7 @@ typedef struct { __IO uint32_t TCR3; /**< Transmit Configuration 3, offset: 0x14 */ __IO uint32_t TCR4; /**< Transmit Configuration 4, offset: 0x18 */ __IO uint32_t TCR5; /**< Transmit Configuration 5, offset: 0x1C */ - __O uint32_t TDR[I2S_TDR_COUNT]; /**< Transmit Data, array offset: 0x20, array step: 0x4, irregular array, not all indices are valid */ + __IO uint32_t TDR[I2S_TDR_COUNT]; /**< Transmit Data, array offset: 0x20, array step: 0x4, irregular array, not all indices are valid */ uint8_t RESERVED_0[16]; __I uint32_t TFR[I2S_TFR_COUNT]; /**< Transmit FIFO, array offset: 0x40, array step: 0x4, irregular array, not all indices are valid */ uint8_t RESERVED_1[16]; @@ -1325,5 +1328,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* I2S_H_ */ +#endif /* PERI_I2S_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_I3C.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_I3C.h index fbdb273725..73cbde32de 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_I3C.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_I3C.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for I3C ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file I3C.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_I3C.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for I3C * * CMSIS Peripheral Access Layer for I3C */ -#if !defined(I3C_H_) -#define I3C_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_I3C_H_) +#define PERI_I3C_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -285,8 +288,8 @@ typedef struct { #define I3C_MCONFIG_DISTO_MASK (0x8U) #define I3C_MCONFIG_DISTO_SHIFT (3U) /*! DISTO - Disable Timeout - * 0b1..Timeout disabled, if timeout is configured * 0b0..Timeout enabled + * 0b1..Timeout disabled, if timeout is configured */ #define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) @@ -303,9 +306,9 @@ typedef struct { #define I3C_MCONFIG_ODSTOP_MASK (0x40U) #define I3C_MCONFIG_ODSTOP_SHIFT (6U) /*! ODSTOP - Open Drain Stop + * 0b0..Disable open-drain stop. ODSTOP must be disabled when sending an HDR exit pattern. * 0b1..Enable open-drain stop. STOP is emitted at open-drain speeds even for I3C messages. In legacy devices, * this feature can ensure that the legacy devices see the STOP. - * 0b0..Disable open-drain stop. ODSTOP must be disabled when sending an HDR exit pattern. */ #define I3C_MCONFIG_ODSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK) @@ -327,10 +330,10 @@ typedef struct { #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) #define I3C_MCONFIG_ODHPP_SHIFT (24U) /*! ODHPP - Open Drain High Push-Pull + * 0b0..ODHPP disabled. Open-Drain SCL High half-clock period is the same as the Open-Drain Low SCL half-period. * 0b1..ODHPP enabled. Open-Drain High SCL half-lock period is one PPBAUD count for I3C messages. This setting is * faster (and works for I3C devices). Any legacy I2C devices on the bus will not see the SCL High at all * (less than the spike filter period). - * 0b0..ODHPP disabled. Open-Drain SCL High half-clock period is the same as the Open-Drain Low SCL half-period. */ #define I3C_MCONFIG_ODHPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK) @@ -351,53 +354,53 @@ typedef struct { #define I3C_SCONFIG_SLVENA_MASK (0x1U) #define I3C_SCONFIG_SLVENA_SHIFT (0U) /*! SLVENA - Target Enable - * 0b1..Target can operate on the I2C or I3C bus * 0b0..Target ignores the I2C or I3C bus + * 0b1..Target can operate on the I2C or I3C bus */ #define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK) #define I3C_SCONFIG_NACK_MASK (0x2U) #define I3C_SCONFIG_NACK_SHIFT (1U) /*! NACK - Not Acknowledge + * 0b0..Always NACK disable * 0b1..Always NACK enable. The target rejects all requests to it, except for a Common Command Code (CCC) * broadcast. NACK = 1 should be used with caution, because the controller may decide that the target is missing, if * NACK is overused. - * 0b0..Always NACK disable */ #define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK) #define I3C_SCONFIG_MATCHSS_MASK (0x4U) #define I3C_SCONFIG_MATCHSS_SHIFT (2U) /*! MATCHSS - Match START or STOP + * 0b0..Match START or STOP disable * 0b1..Match START or STOP enable. START and STOP sticky SSTATUS bits only become 1 when SSTATUS[MATCHED] is 1. * This setting allows START and STOP to be used to detect the end of a message to/from this target. - * 0b0..Match START or STOP disable */ #define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK) #define I3C_SCONFIG_S0IGNORE_MASK (0x8U) #define I3C_SCONFIG_S0IGNORE_SHIFT (3U) /*! S0IGNORE - Ignore TE0/TE1 Errors + * 0b0..Do not ignore TE0/TE1 errors * 0b1..Ignore TE0/TE1 errors. Target does not detect TE0 or TE1 errors, so it does not lock up waiting on an * Exit Pattern. This setting should only be used when the bus does not use HDR mode. - * 0b0..Do not ignore TE0/TE1 errors */ #define I3C_SCONFIG_S0IGNORE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK) #define I3C_SCONFIG_HDROK_MASK (0x10U) #define I3C_SCONFIG_HDROK_SHIFT (4U) /*! HDROK - HDR OK + * 0b0..Disable HDR OK. * 0b1..Enable HDR OK. Allow HDR-DDR and/or HDR-BT messaging if available by setting the corresponding * SIDEXT[BCR] bit to say HDR is available, and the corresponding GETCAPS bit for DDR and/or BT bit permitting use. - * 0b0..Disable HDR OK. */ #define I3C_SCONFIG_HDROK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_HDROK_SHIFT)) & I3C_SCONFIG_HDROK_MASK) #define I3C_SCONFIG_OFFLINE_MASK (0x200U) #define I3C_SCONFIG_OFFLINE_SHIFT (9U) /*! OFFLINE - Offline - * 0b1..Enables wait to ensure the bus is not in HDR mode. * 0b0..Disable + * 0b1..Enables wait to ensure the bus is not in HDR mode. */ #define I3C_SCONFIG_OFFLINE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK) @@ -418,113 +421,113 @@ typedef struct { #define I3C_SSTATUS_STNOTSTOP_MASK (0x1U) #define I3C_SSTATUS_STNOTSTOP_SHIFT (0U) /*! STNOTSTOP - Status Not Stop - * 0b1..The bus is busy (has activity). * 0b0..I3C module is in a STOP condition. + * 0b1..The bus is busy (has activity). */ #define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK) #define I3C_SSTATUS_STMSG_MASK (0x2U) #define I3C_SSTATUS_STMSG_SHIFT (1U) /*! STMSG - Status message - * 0b1..This bus target is listening to the bus traffic or responding. * 0b0..Bus target not listening or responding. + * 0b1..This bus target is listening to the bus traffic or responding. */ #define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK) #define I3C_SSTATUS_STCCCH_MASK (0x4U) #define I3C_SSTATUS_STCCCH_SHIFT (2U) /*! STCCCH - Status Common Command Code Handler - * 0b1..A CCC message is being handled automatically. * 0b0..No CCC message is being handled. + * 0b1..A CCC message is being handled automatically. */ #define I3C_SSTATUS_STCCCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK) #define I3C_SSTATUS_STREQRD_MASK (0x8U) #define I3C_SSTATUS_STREQRD_SHIFT (3U) /*! STREQRD - Status Request Read - * 0b1..The REQ in process is an SDR read from this target, or an In-Band Interrupt (IBI) is being pushed out. * 0b0..REQ in process is not an SDR read from this target. + * 0b1..The REQ in process is an SDR read from this target, or an In-Band Interrupt (IBI) is being pushed out. */ #define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK) #define I3C_SSTATUS_STREQWR_MASK (0x10U) #define I3C_SSTATUS_STREQWR_SHIFT (4U) /*! STREQWR - Status Request Write - * 0b1..REQ in process is SDR write data from the controller to this bus target (or all I3C targets), but not in ENTDAA mode. * 0b0..REQ in process is not SDR write data from the controller. + * 0b1..REQ in process is SDR write data from the controller to this bus target (or all I3C targets), but not in ENTDAA mode. */ #define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK) #define I3C_SSTATUS_STDAA_MASK (0x20U) #define I3C_SSTATUS_STDAA_SHIFT (5U) /*! STDAA - Status Dynamic Address Assignment - * 0b1..I3C bus is in Enter Dynamic Address Assignment (ENTDAA) mode, regardless of whether this bus target has a Dynamic Address or not. * 0b0..Not in ENTDAA mode. + * 0b1..I3C bus is in Enter Dynamic Address Assignment (ENTDAA) mode, regardless of whether this bus target has a Dynamic Address or not. */ #define I3C_SSTATUS_STDAA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK) #define I3C_SSTATUS_STHDR_MASK (0x40U) #define I3C_SSTATUS_STHDR_SHIFT (6U) /*! STHDR - Status High Data Rate + * 0b0..I3C bus not in HDR-DDR mode * 0b1..The I3C bus is in HDR-DDR mode, regardless of whether HDR mode is supported by this module or not, and * regardless of whether the message is to this module or to some other module. - * 0b0..I3C bus not in HDR-DDR mode */ #define I3C_SSTATUS_STHDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK) #define I3C_SSTATUS_START_MASK (0x100U) #define I3C_SSTATUS_START_SHIFT (8U) /*! START - Start - * 0b1..A START or repeated START was seen after the START bit was last cleared. * 0b0..No START seen. + * 0b1..A START or repeated START was seen after the START bit was last cleared. */ #define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) #define I3C_SSTATUS_MATCHED_MASK (0x200U) #define I3C_SSTATUS_MATCHED_SHIFT (9U) /*! MATCHED - Matched - * 0b1..An incoming header matched the I3C Dynamic or I2C Static address of this device (if any) since the bus was last cleared. * 0b0..No header matched. + * 0b1..An incoming header matched the I3C Dynamic or I2C Static address of this device (if any) since the bus was last cleared. */ #define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) #define I3C_SSTATUS_STOP_MASK (0x400U) #define I3C_SSTATUS_STOP_SHIFT (10U) /*! STOP - Stop - * 0b1..Stopped state detected. A STOP state was present on the bus since the bus was last cleared. * 0b0..No STOP detected. + * 0b1..Stopped state detected. A STOP state was present on the bus since the bus was last cleared. */ #define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) #define I3C_SSTATUS_RX_PEND_MASK (0x800U) #define I3C_SSTATUS_RX_PEND_SHIFT (11U) /*! RX_PEND - Received Message Pending - * 0b1..Received message is pending. * 0b0..No received message is pending. + * 0b1..Received message is pending. */ #define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK) #define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U) #define I3C_SSTATUS_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - Transmit Buffer Is Not Full - * 0b1..Transmit buffer not full * 0b0..Transmit buffer full + * 0b1..Transmit buffer not full */ #define I3C_SSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK) #define I3C_SSTATUS_DACHG_MASK (0x2000U) #define I3C_SSTATUS_DACHG_SHIFT (13U) /*! DACHG - Dynamic Address Change - * 0b1..DA change detected. The target DA has been assigned, re-assigned, or reset (lost) and is now in the state of being valid or none. * 0b0..No DA change detected. + * 0b1..DA change detected. The target DA has been assigned, re-assigned, or reset (lost) and is now in the state of being valid or none. */ #define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK) #define I3C_SSTATUS_CCC_MASK (0x4000U) #define I3C_SSTATUS_CCC_SHIFT (14U) /*! CCC - Common Command Code - * 0b1..CCC received. * 0b0..No CCC received. + * 0b1..CCC received. */ #define I3C_SSTATUS_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK) @@ -536,24 +539,24 @@ typedef struct { #define I3C_SSTATUS_HDRMATCH_MASK (0x10000U) #define I3C_SSTATUS_HDRMATCH_SHIFT (16U) /*! HDRMATCH - High Data Rate Command Match - * 0b1..HDR command matched the I3C Dynamic Address of this device. * 0b0..HDR command did not match. + * 0b1..HDR command matched the I3C Dynamic Address of this device. */ #define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK) #define I3C_SSTATUS_CHANDLED_MASK (0x20000U) #define I3C_SSTATUS_CHANDLED_SHIFT (17U) /*! CHANDLED - Common Command Code Handled - * 0b1..CCC handling in progress. * 0b0..CCC handling not in progress. + * 0b1..CCC handling in progress. */ #define I3C_SSTATUS_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK) #define I3C_SSTATUS_EVENT_MASK (0x40000U) #define I3C_SSTATUS_EVENT_SHIFT (18U) /*! EVENT - Event - * 0b1..An IBI, CR, or HJ has occurred. * 0b0..No event has occurred. + * 0b1..An IBI, CR, or HJ has occurred. */ #define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK) @@ -575,24 +578,24 @@ typedef struct { #define I3C_SSTATUS_IBIDIS_MASK (0x1000000U) #define I3C_SSTATUS_IBIDIS_SHIFT (24U) /*! IBIDIS - In-Band Interrupts Are Disabled - * 0b1..In-Band Interrupts disabled * 0b0..In-Band Interrupts not disabled + * 0b1..In-Band Interrupts disabled */ #define I3C_SSTATUS_IBIDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK) #define I3C_SSTATUS_MRDIS_MASK (0x2000000U) #define I3C_SSTATUS_MRDIS_SHIFT (25U) /*! MRDIS - Controller Requests Are Disabled - * 0b1..Controller Requests disabled * 0b0..Controller Requests not disabled + * 0b1..Controller Requests disabled */ #define I3C_SSTATUS_MRDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK) #define I3C_SSTATUS_HJDIS_MASK (0x8000000U) #define I3C_SSTATUS_HJDIS_SHIFT (27U) /*! HJDIS - Hot-Join Disabled - * 0b1..Hot-Join disabled * 0b0..Hot-Join not disabled + * 0b1..Hot-Join disabled */ #define I3C_SSTATUS_HJDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK) @@ -633,8 +636,8 @@ typedef struct { #define I3C_SCTRL_EXTDATA_MASK (0x8U) #define I3C_SCTRL_EXTDATA_SHIFT (3U) /*! EXTDATA - Extended Data - * 0b1..Extended data enabled. After IBIDATA is emitted, extended data is taken from IBIEXT1 and IBIEXT2 if configured. * 0b0..Extended data disabled. + * 0b1..Extended data enabled. After IBIDATA is emitted, extended data is taken from IBIEXT1 and IBIEXT2 if configured. */ #define I3C_SCTRL_EXTDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK) @@ -670,96 +673,96 @@ typedef struct { #define I3C_SINTSET_START_MASK (0x100U) #define I3C_SINTSET_START_SHIFT (8U) /*! START - Start Interrupt Enable - * 0b1..Enable START interrupt * 0b0..Disable START interrupt + * 0b1..Enable START interrupt */ #define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK) #define I3C_SINTSET_MATCHED_MASK (0x200U) #define I3C_SINTSET_MATCHED_SHIFT (9U) /*! MATCHED - Match interrupt enable - * 0b1..Enable match interrupt * 0b0..Disable match interrupt + * 0b1..Enable match interrupt */ #define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK) #define I3C_SINTSET_STOP_MASK (0x400U) #define I3C_SINTSET_STOP_SHIFT (10U) /*! STOP - Stop Interrupt Enable - * 0b1..Enable STOP interrupt * 0b0..Disable STOP interrupt + * 0b1..Enable STOP interrupt */ #define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK) #define I3C_SINTSET_RXPEND_MASK (0x800U) #define I3C_SINTSET_RXPEND_SHIFT (11U) /*! RXPEND - Receive Interrupt Enable - * 0b1..Enable Receive interrupt * 0b0..Disable Receive interrupt + * 0b1..Enable Receive interrupt */ #define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK) #define I3C_SINTSET_TXSEND_MASK (0x1000U) #define I3C_SINTSET_TXSEND_SHIFT (12U) /*! TXSEND - Transmit Interrupt Enable - * 0b1..Enable Transmit interrupt * 0b0..Disable Transmit interrupt + * 0b1..Enable Transmit interrupt */ #define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK) #define I3C_SINTSET_DACHG_MASK (0x2000U) #define I3C_SINTSET_DACHG_SHIFT (13U) /*! DACHG - Dynamic Address Change Interrupt Enable - * 0b1..Enable DA Change interrupt * 0b0..Disable DA Change interrupt + * 0b1..Enable DA Change interrupt */ #define I3C_SINTSET_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK) #define I3C_SINTSET_CCC_MASK (0x4000U) #define I3C_SINTSET_CCC_SHIFT (14U) /*! CCC - CCC (that was not handled by I3C module) Interrupt Enable - * 0b1..Enable CCC interrupt * 0b0..Disable CCC interrupt + * 0b1..Enable CCC interrupt */ #define I3C_SINTSET_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK) #define I3C_SINTSET_ERRWARN_MASK (0x8000U) #define I3C_SINTSET_ERRWARN_SHIFT (15U) /*! ERRWARN - Error or Warning Interrupt Enable - * 0b1..Enable error or warning interrupt * 0b0..Disable error or warning interrupt + * 0b1..Enable error or warning interrupt */ #define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK) #define I3C_SINTSET_DDRMATCHED_MASK (0x10000U) #define I3C_SINTSET_DDRMATCHED_SHIFT (16U) /*! DDRMATCHED - Double Data Rate Interrupt Enable - * 0b1..Enable DDR interrupt * 0b0..Disable DDR interrupt + * 0b1..Enable DDR interrupt */ #define I3C_SINTSET_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK) #define I3C_SINTSET_CHANDLED_MASK (0x20000U) #define I3C_SINTSET_CHANDLED_SHIFT (17U) /*! CHANDLED - Common Command Code (CCC) Interrupt Enable - * 0b1..Enable CCC Handled interrupt * 0b0..Disable CCC Handled interrupt + * 0b1..Enable CCC Handled interrupt */ #define I3C_SINTSET_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK) #define I3C_SINTSET_EVENT_MASK (0x40000U) #define I3C_SINTSET_EVENT_SHIFT (18U) /*! EVENT - Event Interrupt Enable - * 0b1..Enable Event interrupt * 0b0..Disable Event interrupt + * 0b1..Enable Event interrupt */ #define I3C_SINTSET_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK) #define I3C_SINTSET_SLVRST_MASK (0x80000U) #define I3C_SINTSET_SLVRST_SHIFT (19U) /*! SLVRST - Target Reset - * 0b1..Enable Target Reset interrupt * 0b0..Disable Target Reset interrupt + * 0b1..Enable Target Reset interrupt */ #define I3C_SINTSET_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_SLVRST_SHIFT)) & I3C_SINTSET_SLVRST_MASK) /*! @} */ @@ -893,88 +896,88 @@ typedef struct { #define I3C_SERRWARN_ORUN_MASK (0x1U) #define I3C_SERRWARN_ORUN_SHIFT (0U) /*! ORUN - Overrun Error - * 0b1..Overrun error * 0b0..No overrun error + * 0b1..Overrun error */ #define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) #define I3C_SERRWARN_URUN_MASK (0x2U) #define I3C_SERRWARN_URUN_SHIFT (1U) /*! URUN - Underrun Error - * 0b1..Underrun error * 0b0..No underrun error + * 0b1..Underrun error */ #define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) #define I3C_SERRWARN_URUNNACK_MASK (0x4U) #define I3C_SERRWARN_URUNNACK_SHIFT (2U) /*! URUNNACK - Underrun and Not Acknowledged (NACKED) Error - * 0b1..Underrun and not acknowledged error * 0b0..No underrun and not acknowledged error + * 0b1..Underrun and not acknowledged error */ #define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) #define I3C_SERRWARN_TERM_MASK (0x8U) #define I3C_SERRWARN_TERM_SHIFT (3U) /*! TERM - Terminated Error - * 0b1..Terminated error * 0b0..No terminated error + * 0b1..Terminated error */ #define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) #define I3C_SERRWARN_INVSTART_MASK (0x10U) #define I3C_SERRWARN_INVSTART_SHIFT (4U) /*! INVSTART - Invalid Start Error - * 0b1..Invalid start error * 0b0..No invalid start error + * 0b1..Invalid start error */ #define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) #define I3C_SERRWARN_SPAR_MASK (0x100U) #define I3C_SERRWARN_SPAR_SHIFT (8U) /*! SPAR - SDR Parity Error - * 0b1..SDR Parity error * 0b0..No SDR Parity error + * 0b1..SDR Parity error */ #define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) #define I3C_SERRWARN_HPAR_MASK (0x200U) #define I3C_SERRWARN_HPAR_SHIFT (9U) /*! HPAR - HDR Parity Error - * 0b1..HDR Parity error * 0b0..No HDR Parity error + * 0b1..HDR Parity error */ #define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK) #define I3C_SERRWARN_HCRC_MASK (0x400U) #define I3C_SERRWARN_HCRC_SHIFT (10U) /*! HCRC - HDR-DDR CRC Error - * 0b1..HDR-DDR CRC error * 0b0..No HDR-DDR CRC error + * 0b1..HDR-DDR CRC error */ #define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK) #define I3C_SERRWARN_S0S1_MASK (0x800U) #define I3C_SERRWARN_S0S1_SHIFT (11U) /*! S0S1 - TE0 or TE1 Error - * 0b1..TE0 or TE1 error * 0b0..No TE0 or TE1 error + * 0b1..TE0 or TE1 error */ #define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK) #define I3C_SERRWARN_OREAD_MASK (0x10000U) #define I3C_SERRWARN_OREAD_SHIFT (16U) /*! OREAD - Over-read Error - * 0b1..Over-read error * 0b0..No Over-read error + * 0b1..Over-read error */ #define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) #define I3C_SERRWARN_OWRITE_MASK (0x20000U) #define I3C_SERRWARN_OWRITE_SHIFT (17U) /*! OWRITE - Over-write Error - * 0b1..Overwrite error * 0b0..No Overwrite error + * 0b1..Overwrite error */ #define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) /*! @} */ @@ -1066,16 +1069,16 @@ typedef struct { #define I3C_SDATACTRL_TXFULL_MASK (0x40000000U) #define I3C_SDATACTRL_TXFULL_SHIFT (30U) /*! TXFULL - Transmit Is Full - * 0b1..Full * 0b0..Not full + * 0b1..Full */ #define I3C_SDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK) #define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U) #define I3C_SDATACTRL_RXEMPTY_SHIFT (31U) /*! RXEMPTY - Receive Is Empty - * 0b1..Empty * 0b0..Not empty + * 0b1..Empty */ #define I3C_SDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK) /*! @} */ @@ -1091,16 +1094,16 @@ typedef struct { #define I3C_SWDATAB_END_MASK (0x100U) #define I3C_SWDATAB_END_SHIFT (8U) /*! END - End - * 0b1..End. This bit marks the last byte of the message. * 0b0..Not the end. There are more bytes in the message. + * 0b1..End. This bit marks the last byte of the message. */ #define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK) #define I3C_SWDATAB_END_ALSO_MASK (0x10000U) #define I3C_SWDATAB_END_ALSO_SHIFT (16U) /*! END_ALSO - End Also - * 0b1..End. This bit marks the last byte of the message. * 0b0..Not the end. There are more bytes in the message. + * 0b1..End. This bit marks the last byte of the message. */ #define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK) /*! @} */ @@ -1130,8 +1133,8 @@ typedef struct { #define I3C_SWDATAH_END_MASK (0x10000U) #define I3C_SWDATAH_END_SHIFT (16U) /*! END - End of message - * 0b1..End. This bit marks the last byte of the message. * 0b0..Not the end. There are more bytes in the message. + * 0b1..End. This bit marks the last byte of the message. */ #define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK) /*! @} */ @@ -1273,24 +1276,24 @@ typedef struct { #define I3C_SCAPABILITIES2_AASA_MASK (0x200000U) #define I3C_SCAPABILITIES2_AASA_SHIFT (21U) /*! AASA - Supports SETAASA - * 0b1..Supports SETAASA * 0b0..Does not support SETAASA + * 0b1..Supports SETAASA */ #define I3C_SCAPABILITIES2_AASA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK) #define I3C_SCAPABILITIES2_SSTSUB_MASK (0x400000U) #define I3C_SCAPABILITIES2_SSTSUB_SHIFT (22U) /*! SSTSUB - Target-Target(s)-Tunnel Subscriber Capable - * 0b1..Subscriber capable * 0b0..Not subscriber capable + * 0b1..Subscriber capable */ #define I3C_SCAPABILITIES2_SSTSUB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK) #define I3C_SCAPABILITIES2_SSTWR_MASK (0x800000U) #define I3C_SCAPABILITIES2_SSTWR_SHIFT (23U) /*! SSTWR - Target-Target(s)-Tunnel Write Capable - * 0b1..Write capable * 0b0..Not write capable + * 0b1..Write capable */ #define I3C_SCAPABILITIES2_SSTWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK) /*! @} */ @@ -1312,10 +1315,10 @@ typedef struct { #define I3C_SCAPABILITIES_IDREG_SHIFT (2U) /*! IDREG - ID Register * 0b0000..All ID register features below are disabled. - * 0bxxx1..ID Instance is a register, and is used if there is no PARTNO register. - * 0bxx1x..An ID Random field is available. - * 0bx1xx..A Device Characteristic Register (DCR) is available. * 0b1xxx..A Bus Characteristics Register (BCR) is available. + * 0bx1xx..A Device Characteristic Register (DCR) is available. + * 0bxx1x..An ID Random field is available. + * 0bxxx1..ID Instance is a register, and is used if there is no PARTNO register. */ #define I3C_SCAPABILITIES_IDREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK) @@ -1324,7 +1327,6 @@ typedef struct { /*! HDRSUPP - High Data Rate Support * 0b00..No HDR modes supported * 0b01..Double Data Rate mode supported - * *.. */ #define I3C_SCAPABILITIES_HDRSUPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK) @@ -1350,10 +1352,10 @@ typedef struct { #define I3C_SCAPABILITIES_CCCHANDLE_SHIFT (12U) /*! CCCHANDLE - Common Command Codes Handling * 0b0000..All handling features below are disabled. - * 0bxxx1..The block (I3C module) manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items. - * 0bxx1x..The block manages maximum read and write lengths, and max data speed. - * 0bx1xx..GETSTATUS CCC returns SCTRL[PENDINT] and SCTRL[ACTSTATE] values. * 0b1xxx..GETSTATUS CCC returns SCTRL[VENDINFO] value. + * 0bx1xx..GETSTATUS CCC returns SCTRL[PENDINT] and SCTRL[ACTSTATE] values. + * 0bxx1x..The block manages maximum read and write lengths, and max data speed. + * 0bxxx1..The block (I3C module) manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items. */ #define I3C_SCAPABILITIES_CCCHANDLE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK) @@ -1361,11 +1363,11 @@ typedef struct { #define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT (16U) /*! IBI_MR_HJ - In-Band Interrupts, Controller Requests, Hot-Join Events * 0b00000..Application cannot generate IBI, CR, or HJ. - * 0bxxxx1..Application can generate an IBI. - * 0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register. - * 0bxx1xx..Application can generate a Controller Request for a secondary controller. - * 0bx1xxx..Application can generate a Hot-Join event. * 0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing. + * 0bx1xxx..Application can generate a Hot-Join event. + * 0bxx1xx..Application can generate a Controller Request for a secondary controller. + * 0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register. + * 0bxxxx1..Application can generate an IBI. */ #define I3C_SCAPABILITIES_IBI_MR_HJ(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK) @@ -1383,7 +1385,6 @@ typedef struct { * 0b000..No external FIFO is available * 0b001..Standard available or free external FIFO * 0b010..Request track external FIFO - * *.. */ #define I3C_SCAPABILITIES_EXTFIFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK) @@ -1410,16 +1411,16 @@ typedef struct { #define I3C_SCAPABILITIES_INT_MASK (0x40000000U) #define I3C_SCAPABILITIES_INT_SHIFT (30U) /*! INT - Interrupts - * 0b1..Supported * 0b0..Not supported + * 0b1..Supported */ #define I3C_SCAPABILITIES_INT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK) #define I3C_SCAPABILITIES_DMA_MASK (0x80000000U) #define I3C_SCAPABILITIES_DMA_SHIFT (31U) /*! DMA - Direct Memory Access - * 0b1..Supported * 0b0..Not supported + * 0b1..Supported */ #define I3C_SCAPABILITIES_DMA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK) /*! @} */ @@ -1495,8 +1496,8 @@ typedef struct { #define I3C_SMSGMAPADDR_LASTSTATIC_MASK (0x10U) #define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT (4U) /*! LASTSTATIC - Last Static Address Matched - * 0b1..I2C static address * 0b0..I3C dynamic address + * 0b1..I2C static address */ #define I3C_SMSGMAPADDR_LASTSTATIC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK) @@ -1642,8 +1643,8 @@ typedef struct { #define I3C_MSTATUS_NACKED_MASK (0x20U) #define I3C_MSTATUS_NACKED_SHIFT (5U) /*! NACKED - Not Acknowledged - * 0b1..NACKed (not acknowledged) * 0b0..Not NACKed + * 0b1..NACKed (not acknowledged) */ #define I3C_MSTATUS_NACKED(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK) @@ -1660,64 +1661,64 @@ typedef struct { #define I3C_MSTATUS_SLVSTART_MASK (0x100U) #define I3C_MSTATUS_SLVSTART_SHIFT (8U) /*! SLVSTART - Target Start - * 0b1..Target requesting START * 0b0..Target not requesting START + * 0b1..Target requesting START */ #define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK) #define I3C_MSTATUS_MCTRLDONE_MASK (0x200U) #define I3C_MSTATUS_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - Controller Control Done - * 0b1..Done * 0b0..Not done + * 0b1..Done */ #define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) #define I3C_MSTATUS_COMPLETE_MASK (0x400U) #define I3C_MSTATUS_COMPLETE_SHIFT (10U) /*! COMPLETE - Complete - * 0b1..Complete * 0b0..Not complete + * 0b1..Complete */ #define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) #define I3C_MSTATUS_RXPEND_MASK (0x800U) #define I3C_MSTATUS_RXPEND_SHIFT (11U) /*! RXPEND - RXPEND - * 0b1..Receive message pending * 0b0..No receive message pending + * 0b1..Receive message pending */ #define I3C_MSTATUS_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK) #define I3C_MSTATUS_TXNOTFULL_MASK (0x1000U) #define I3C_MSTATUS_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - TX Buffer or FIFO Not Full - * 0b1..Receive buffer or FIFO not full * 0b0..Receive buffer or FIFO full + * 0b1..Receive buffer or FIFO not full */ #define I3C_MSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK) #define I3C_MSTATUS_IBIWON_MASK (0x2000U) #define I3C_MSTATUS_IBIWON_SHIFT (13U) /*! IBIWON - In-Band Interrupt (IBI) Won - * 0b1..IBI arbitration won * 0b0..No IBI arbitration won + * 0b1..IBI arbitration won */ #define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK) #define I3C_MSTATUS_ERRWARN_MASK (0x8000U) #define I3C_MSTATUS_ERRWARN_SHIFT (15U) /*! ERRWARN - Error Or Warning - * 0b1..Error or warning * 0b0..No error or warning + * 0b1..Error or warning */ #define I3C_MSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK) #define I3C_MSTATUS_NOWMASTER_MASK (0x80000U) #define I3C_MSTATUS_NOWMASTER_SHIFT (19U) /*! NOWMASTER - Module Is Now Controller - * 0b1..Module has become controller * 0b0..Module has not become controller + * 0b1..Module has become controller */ #define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK) @@ -1758,16 +1759,16 @@ typedef struct { #define I3C_MIBIRULES_MSB0_MASK (0x40000000U) #define I3C_MIBIRULES_MSB0_SHIFT (30U) /*! MSB0 - Most Significant Address Bit Is 0 - * 0b1..For all I3C dynamic addresses, MSB is 0. * 0b0..MSB is not 0. + * 0b1..For all I3C dynamic addresses, MSB is 0. */ #define I3C_MIBIRULES_MSB0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK) #define I3C_MIBIRULES_NOBYTE_MASK (0x80000000U) #define I3C_MIBIRULES_NOBYTE_SHIFT (31U) /*! NOBYTE - No IBI byte - * 0b1..Without mandatory IBI byte * 0b0..With mandatory IBI byte + * 0b1..Without mandatory IBI byte */ #define I3C_MIBIRULES_NOBYTE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK) /*! @} */ @@ -1778,24 +1779,24 @@ typedef struct { #define I3C_MINTSET_SLVSTART_MASK (0x100U) #define I3C_MINTSET_SLVSTART_SHIFT (8U) /*! SLVSTART - Target Start Interrupt Enable - * 0b1..Enable * 0b0..Disable + * 0b1..Enable */ #define I3C_MINTSET_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK) #define I3C_MINTSET_MCTRLDONE_MASK (0x200U) #define I3C_MINTSET_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - Controller Control Done Interrupt Enable - * 0b1..Enable * 0b0..Disable + * 0b1..Enable */ #define I3C_MINTSET_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK) #define I3C_MINTSET_COMPLETE_MASK (0x400U) #define I3C_MINTSET_COMPLETE_SHIFT (10U) /*! COMPLETE - Completed Message Interrupt Enable - * 0b1..Enable * 0b0..Disable + * 0b1..Enable */ #define I3C_MINTSET_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK) @@ -1807,32 +1808,32 @@ typedef struct { #define I3C_MINTSET_TXNOTFULL_MASK (0x1000U) #define I3C_MINTSET_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - TX buffer/FIFO is not full interrupt enable - * 0b1..Enable * 0b0..Disable + * 0b1..Enable */ #define I3C_MINTSET_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK) #define I3C_MINTSET_IBIWON_MASK (0x2000U) #define I3C_MINTSET_IBIWON_SHIFT (13U) /*! IBIWON - In-Band Interrupt (IBI) Won Interrupt Enable - * 0b1..Enable * 0b0..Disable + * 0b1..Enable */ #define I3C_MINTSET_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK) #define I3C_MINTSET_ERRWARN_MASK (0x8000U) #define I3C_MINTSET_ERRWARN_SHIFT (15U) /*! ERRWARN - Error or Warning (ERRWARN) Interrupt Enable - * 0b1..Enable * 0b0..Disable + * 0b1..Enable */ #define I3C_MINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK) #define I3C_MINTSET_NOWMASTER_MASK (0x80000U) #define I3C_MINTSET_NOWMASTER_SHIFT (19U) /*! NOWMASTER - Now Controller (now this I3C module is a controller) Interrupt Enable - * 0b1..Enable * 0b0..Disable + * 0b1..Enable */ #define I3C_MINTSET_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK) /*! @} */ @@ -1843,64 +1844,64 @@ typedef struct { #define I3C_MINTCLR_SLVSTART_MASK (0x100U) #define I3C_MINTCLR_SLVSTART_SHIFT (8U) /*! SLVSTART - SLVSTART Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 * 0b0..No effect + * 0b1..Corresponding interrupt enable becomes 0 */ #define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK) #define I3C_MINTCLR_MCTRLDONE_MASK (0x200U) #define I3C_MINTCLR_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 * 0b0..No effect + * 0b1..Corresponding interrupt enable becomes 0 */ #define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) #define I3C_MINTCLR_COMPLETE_MASK (0x400U) #define I3C_MINTCLR_COMPLETE_SHIFT (10U) /*! COMPLETE - COMPLETE Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 * 0b0..No effect + * 0b1..Corresponding interrupt enable becomes 0 */ #define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) #define I3C_MINTCLR_RXPEND_MASK (0x800U) #define I3C_MINTCLR_RXPEND_SHIFT (11U) /*! RXPEND - RXPEND Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 * 0b0..No effect + * 0b1..Corresponding interrupt enable becomes 0 */ #define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) #define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U) #define I3C_MINTCLR_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 * 0b0..No effect + * 0b1..Corresponding interrupt enable becomes 0 */ #define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) #define I3C_MINTCLR_IBIWON_MASK (0x2000U) #define I3C_MINTCLR_IBIWON_SHIFT (13U) /*! IBIWON - IBIWON Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 * 0b0..No effect + * 0b1..Corresponding interrupt enable becomes 0 */ #define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK) #define I3C_MINTCLR_ERRWARN_MASK (0x8000U) #define I3C_MINTCLR_ERRWARN_SHIFT (15U) /*! ERRWARN - ERRWARN Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 * 0b0..No effect + * 0b1..Corresponding interrupt enable becomes 0 */ #define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) #define I3C_MINTCLR_NOWMASTER_MASK (0x80000U) #define I3C_MINTCLR_NOWMASTER_SHIFT (19U) /*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 * 0b0..No effect + * 0b1..Corresponding interrupt enable becomes 0 */ #define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK) /*! @} */ @@ -1911,24 +1912,24 @@ typedef struct { #define I3C_MINTMASKED_SLVSTART_MASK (0x100U) #define I3C_MINTMASKED_SLVSTART_SHIFT (8U) /*! SLVSTART - SLVSTART Interrupt Mask - * 0b1..Interrupt enabled and active * 0b0..Interrupt not enabled and/or not active + * 0b1..Interrupt enabled and active */ #define I3C_MINTMASKED_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK) #define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U) #define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - MCTRLDONE Interrupt Mask - * 0b1..Interrupt enabled and active * 0b0..Interrupt not enabled and/or not active + * 0b1..Interrupt enabled and active */ #define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK) #define I3C_MINTMASKED_COMPLETE_MASK (0x400U) #define I3C_MINTMASKED_COMPLETE_SHIFT (10U) /*! COMPLETE - COMPLETE Interrupt Mask - * 0b1..Interrupt enabled and active * 0b0..Interrupt not enabled and/or not active + * 0b1..Interrupt enabled and active */ #define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK) @@ -1940,32 +1941,32 @@ typedef struct { #define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U) #define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - TXNOTFULL Interrupt Mask - * 0b1..Interrupt enabled and active * 0b0..Interrupt not enabled and/or not active + * 0b1..Interrupt enabled and active */ #define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK) #define I3C_MINTMASKED_IBIWON_MASK (0x2000U) #define I3C_MINTMASKED_IBIWON_SHIFT (13U) /*! IBIWON - IBIWON Interrupt Mask - * 0b1..Interrupt enabled and active * 0b0..Interrupt not enabled and/or not active + * 0b1..Interrupt enabled and active */ #define I3C_MINTMASKED_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK) #define I3C_MINTMASKED_ERRWARN_MASK (0x8000U) #define I3C_MINTMASKED_ERRWARN_SHIFT (15U) /*! ERRWARN - ERRWARN Interrupt Mask - * 0b1..Interrupt enabled and active * 0b0..Interrupt not enabled and/or not active + * 0b1..Interrupt enabled and active */ #define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK) #define I3C_MINTMASKED_NOWMASTER_MASK (0x80000U) #define I3C_MINTMASKED_NOWMASTER_SHIFT (19U) /*! NOWMASTER - NOWCONTROLLER Interrupt Mask - * 0b1..Interrupt enabled and active * 0b0..Interrupt not enabled and/or not active + * 0b1..Interrupt enabled and active */ #define I3C_MINTMASKED_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK) /*! @} */ @@ -1976,88 +1977,88 @@ typedef struct { #define I3C_MERRWARN_URUN_MASK (0x2U) #define I3C_MERRWARN_URUN_SHIFT (1U) /*! URUN - Underrun error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define I3C_MERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_URUN_SHIFT)) & I3C_MERRWARN_URUN_MASK) #define I3C_MERRWARN_NACK_MASK (0x4U) #define I3C_MERRWARN_NACK_SHIFT (2U) /*! NACK - Not Acknowledge Error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) #define I3C_MERRWARN_WRABT_MASK (0x8U) #define I3C_MERRWARN_WRABT_SHIFT (3U) /*! WRABT - Write Abort Error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) #define I3C_MERRWARN_TERM_MASK (0x10U) #define I3C_MERRWARN_TERM_SHIFT (4U) /*! TERM - Terminate Error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define I3C_MERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK) #define I3C_MERRWARN_HPAR_MASK (0x200U) #define I3C_MERRWARN_HPAR_SHIFT (9U) /*! HPAR - High Data Rate Parity - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK) #define I3C_MERRWARN_HCRC_MASK (0x400U) #define I3C_MERRWARN_HCRC_SHIFT (10U) /*! HCRC - High Data Rate CRC Error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK) #define I3C_MERRWARN_OREAD_MASK (0x10000U) #define I3C_MERRWARN_OREAD_SHIFT (16U) /*! OREAD - Over-read Error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) #define I3C_MERRWARN_OWRITE_MASK (0x20000U) #define I3C_MERRWARN_OWRITE_SHIFT (17U) /*! OWRITE - Over-write Error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) #define I3C_MERRWARN_MSGERR_MASK (0x40000U) #define I3C_MERRWARN_MSGERR_SHIFT (18U) /*! MSGERR - Message Error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) #define I3C_MERRWARN_INVREQ_MASK (0x80000U) #define I3C_MERRWARN_INVREQ_SHIFT (19U) /*! INVREQ - Invalid Request Error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK) #define I3C_MERRWARN_TIMEOUT_MASK (0x100000U) #define I3C_MERRWARN_TIMEOUT_SHIFT (20U) /*! TIMEOUT - Timeout Error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) /*! @} */ @@ -2101,16 +2102,16 @@ typedef struct { #define I3C_MDATACTRL_FLUSHTB_MASK (0x1U) #define I3C_MDATACTRL_FLUSHTB_SHIFT (0U) /*! FLUSHTB - Flush To-bus Buffer or FIFO - * 0b1..Flush the buffer * 0b0..No action + * 0b1..Flush the buffer */ #define I3C_MDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK) #define I3C_MDATACTRL_FLUSHFB_MASK (0x2U) #define I3C_MDATACTRL_FLUSHFB_SHIFT (1U) /*! FLUSHFB - Flush From-bus Buffer or FIFO - * 0b1..Flush the buffer * 0b0..No action + * 0b1..Flush the buffer */ #define I3C_MDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK) @@ -2333,8 +2334,8 @@ typedef struct { #define I3C_MWMSG_DDR_CONTROL2_END_MASK (0x4000U) #define I3C_MWMSG_DDR_CONTROL2_END_SHIFT (14U) /*! END - End of message - * 0b1..End. DDR message ends on HDR Exit. * 0b0..Not the end. DDR message ends waiting for a new DDR message (will issue a HDR Restart for the new message). + * 0b1..End. DDR message ends on HDR Exit. */ #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_END_MASK) /*! @} */ @@ -2363,8 +2364,8 @@ typedef struct { #define I3C_MDYNADDR_DAVALID_MASK (0x1U) #define I3C_MDYNADDR_DAVALID_SHIFT (0U) /*! DAVALID - Dynamic address valid - * 0b1..Valid DA assigned * 0b0..No valid DA assigned + * 0b1..Valid DA assigned */ #define I3C_MDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK) @@ -2459,72 +2460,72 @@ typedef struct { #define I3C_SERRWARNMASK_ORUN_MASK (0x1U) #define I3C_SERRWARNMASK_ORUN_SHIFT (0U) /*! ORUN - ORUN mask - * 0b1..Allow * 0b0..Deny + * 0b1..Allow */ #define I3C_SERRWARNMASK_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_ORUN_SHIFT)) & I3C_SERRWARNMASK_ORUN_MASK) #define I3C_SERRWARNMASK_URUN_MASK (0x2U) #define I3C_SERRWARNMASK_URUN_SHIFT (1U) /*! URUN - URUN mask - * 0b1..Allow * 0b0..Deny + * 0b1..Allow */ #define I3C_SERRWARNMASK_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_URUN_SHIFT)) & I3C_SERRWARNMASK_URUN_MASK) #define I3C_SERRWARNMASK_URUNNACK_MASK (0x4U) #define I3C_SERRWARNMASK_URUNNACK_SHIFT (2U) /*! URUNNACK - URUNNACK mask - * 0b1..Allow * 0b0..Deny + * 0b1..Allow */ #define I3C_SERRWARNMASK_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_URUNNACK_SHIFT)) & I3C_SERRWARNMASK_URUNNACK_MASK) #define I3C_SERRWARNMASK_TERM_MASK (0x8U) #define I3C_SERRWARNMASK_TERM_SHIFT (3U) /*! TERM - TERM mask - * 0b1..Allow * 0b0..Deny + * 0b1..Allow */ #define I3C_SERRWARNMASK_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_TERM_SHIFT)) & I3C_SERRWARNMASK_TERM_MASK) #define I3C_SERRWARNMASK_INVSTART_MASK (0x10U) #define I3C_SERRWARNMASK_INVSTART_SHIFT (4U) /*! INVSTART - INVSTART mask - * 0b1..Allow * 0b0..Deny + * 0b1..Allow */ #define I3C_SERRWARNMASK_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_INVSTART_SHIFT)) & I3C_SERRWARNMASK_INVSTART_MASK) #define I3C_SERRWARNMASK_SPAR_MASK (0x100U) #define I3C_SERRWARNMASK_SPAR_SHIFT (8U) /*! SPAR - SPAR mask - * 0b1..Allow * 0b0..Deny + * 0b1..Allow */ #define I3C_SERRWARNMASK_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_SPAR_SHIFT)) & I3C_SERRWARNMASK_SPAR_MASK) #define I3C_SERRWARNMASK_HPAR_MASK (0x200U) #define I3C_SERRWARNMASK_HPAR_SHIFT (9U) /*! HPAR - HPAR mask - * 0b1..Allow * 0b0..Deny + * 0b1..Allow */ #define I3C_SERRWARNMASK_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_HPAR_SHIFT)) & I3C_SERRWARNMASK_HPAR_MASK) #define I3C_SERRWARNMASK_HCRC_MASK (0x400U) #define I3C_SERRWARNMASK_HCRC_SHIFT (10U) /*! HCRC - HCRC mask - * 0b1..Allow * 0b0..Deny + * 0b1..Allow */ #define I3C_SERRWARNMASK_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_HCRC_SHIFT)) & I3C_SERRWARNMASK_HCRC_MASK) #define I3C_SERRWARNMASK_S0S1_MASK (0x800U) #define I3C_SERRWARNMASK_S0S1_SHIFT (11U) /*! S0S1 - S0S1 mask - * 0b1..Allow * 0b0..Deny + * 0b1..Allow */ #define I3C_SERRWARNMASK_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_S0S1_SHIFT)) & I3C_SERRWARNMASK_S0S1_MASK) /*! @} */ @@ -2554,7 +2555,6 @@ typedef struct { * 0b011..Cleared using RSTDAA * 0b100..Auto MAP change happened last. The change may have changed this DA as well (for example, ENTDAA, and * SETAASA), but at least one MAP entry automatically changed after. - * *.. */ #define I3C_SMAPCTRL0_CAUSE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK) /*! @} */ @@ -2714,5 +2714,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* I3C_H_ */ +#endif /* PERI_I3C_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_IOMUXC1.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_IOMUXC1.h index 2dea692ceb..3abf5ef313 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_IOMUXC1.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_IOMUXC1.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOMUXC1 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file IOMUXC1.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_IOMUXC1.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for IOMUXC1 * * CMSIS Peripheral Access Layer for IOMUXC1 */ -#if !defined(IOMUXC1_H_) -#define IOMUXC1_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_IOMUXC1_H_) +#define PERI_IOMUXC1_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -220,8 +223,8 @@ typedef struct { #define IOMUXC1_SW_MUX_CTL_PAD_SION_MASK (0x10U) #define IOMUXC1_SW_MUX_CTL_PAD_SION_SHIFT (4U) /*! SION - Software Input On Field. - * 0b1..Force input path of pad DAP_TDO_TRACESWO * 0b0..Input Path is determined by functionality + * 0b1..Force input path of pad DAP_TDO_TRACESWO */ #define IOMUXC1_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_SION_MASK) /*! @} */ @@ -338,5 +341,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* IOMUXC1_H_ */ +#endif /* PERI_IOMUXC1_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_IPC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_IPC.h index cd088fadfa..27b7c01223 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_IPC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_IPC.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for IPC ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file IPC.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_IPC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for IPC * * CMSIS Peripheral Access Layer for IPC */ -#if !defined(IPC_H_) -#define IPC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_IPC_H_) +#define PERI_IPC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -261,5 +264,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* IPC_H_ */ +#endif /* PERI_IPC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ISI.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ISI.h index d2d35d3858..df6a902f89 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ISI.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ISI.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for ISI ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ISI.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_ISI.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ISI * * CMSIS Peripheral Access Layer for ISI */ -#if !defined(ISI_H_) -#define ISI_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ISI_H_) +#define PERI_ISI_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -1220,5 +1223,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ISI_H_ */ +#endif /* PERI_ISI_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LCDIF.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LCDIF.h index be924533cf..59995b78bd 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LCDIF.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LCDIF.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for LCDIF ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file LCDIF.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_LCDIF.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for LCDIF * * CMSIS Peripheral Access Layer for LCDIF */ -#if !defined(LCDIF_H_) -#define LCDIF_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_LCDIF_H_) +#define PERI_LCDIF_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -786,5 +789,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* LCDIF_H_ */ +#endif /* PERI_LCDIF_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPI2C.h index ccbab374a1..bb721396ce 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPI2C.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPI2C.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPI2C ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file LPI2C.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_LPI2C.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for LPI2C * * CMSIS Peripheral Access Layer for LPI2C */ -#if !defined(LPI2C_H_) -#define LPI2C_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_LPI2C_H_) +#define PERI_LPI2C_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -354,9 +357,9 @@ typedef struct { #define LPI2C_MSR_EPF_SHIFT (8U) /*! EPF - End Packet Flag * 0b0..No Stop or repeated Start generated - * 0b1..Stop or repeated Start generated * 0b0..No effect * 0b1..Clear the flag + * 0b1..Stop or repeated Start generated */ #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) @@ -364,19 +367,19 @@ typedef struct { #define LPI2C_MSR_SDF_SHIFT (9U) /*! SDF - Stop Detect Flag * 0b0..No Stop condition generated - * 0b1..Stop condition generated * 0b0..No effect * 0b1..Clear the flag + * 0b1..Stop condition generated */ #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) #define LPI2C_MSR_NDF_MASK (0x400U) #define LPI2C_MSR_NDF_SHIFT (10U) /*! NDF - NACK Detect Flag - * 0b0..No unexpected NACK detected - * 0b1..Unexpected NACK detected * 0b0..No effect + * 0b0..No unexpected NACK detected * 0b1..Clear the flag + * 0b1..Unexpected NACK detected */ #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) @@ -384,9 +387,9 @@ typedef struct { #define LPI2C_MSR_ALF_SHIFT (11U) /*! ALF - Arbitration Lost Flag * 0b0..Controller did not lose arbitration - * 0b1..Controller lost arbitration * 0b0..No effect * 0b1..Clear the flag + * 0b1..Controller lost arbitration */ #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) @@ -394,19 +397,19 @@ typedef struct { #define LPI2C_MSR_FEF_SHIFT (12U) /*! FEF - FIFO Error Flag * 0b0..No FIFO error - * 0b1..FIFO error * 0b0..No effect * 0b1..Clear the flag + * 0b1..FIFO error */ #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) #define LPI2C_MSR_PLTF_MASK (0x2000U) #define LPI2C_MSR_PLTF_SHIFT (13U) /*! PLTF - Pin Low Timeout Flag - * 0b0..Pin low timeout did not occur - * 0b1..Pin low timeout occurred * 0b0..No effect + * 0b0..Pin low timeout did not occur * 0b1..Clear the flag + * 0b1..Pin low timeout occurred */ #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) @@ -414,19 +417,19 @@ typedef struct { #define LPI2C_MSR_DMF_SHIFT (14U) /*! DMF - Data Match Flag * 0b0..Matching data not received - * 0b1..Matching data received * 0b0..No effect * 0b1..Clear the flag + * 0b1..Matching data received */ #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) #define LPI2C_MSR_STF_MASK (0x8000U) #define LPI2C_MSR_STF_SHIFT (15U) /*! STF - Start Flag - * 0b0..Start condition not detected - * 0b1..Start condition detected * 0b0..No effect + * 0b0..Start condition not detected * 0b1..Clear the flag + * 0b1..Start condition detected */ #define LPI2C_MSR_STF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK) @@ -962,10 +965,10 @@ typedef struct { #define LPI2C_SSR_RSF_MASK (0x100U) #define LPI2C_SSR_RSF_SHIFT (8U) /*! RSF - Repeated Start Flag - * 0b0..No repeated Start detected - * 0b1..Repeated Start detected * 0b0..No effect + * 0b0..No repeated Start detected * 0b1..Clear the flag + * 0b1..Repeated Start detected */ #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) @@ -973,9 +976,9 @@ typedef struct { #define LPI2C_SSR_SDF_SHIFT (9U) /*! SDF - Stop Detect Flag * 0b0..No Stop detected - * 0b1..Stop detected * 0b0..No effect * 0b1..Clear the flag + * 0b1..Stop detected */ #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) @@ -983,8 +986,8 @@ typedef struct { #define LPI2C_SSR_BEF_SHIFT (10U) /*! BEF - Bit Error Flag * 0b0..No bit error occurred - * 0b1..Bit error occurred * 0b0..No effect + * 0b1..Bit error occurred * 0b1..Clear the flag */ #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) @@ -993,9 +996,9 @@ typedef struct { #define LPI2C_SSR_FEF_SHIFT (11U) /*! FEF - FIFO Error Flag * 0b0..No FIFO error - * 0b1..FIFO error * 0b0..No effect * 0b1..Clear the flag + * 0b1..FIFO error */ #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) @@ -1550,5 +1553,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* LPI2C_H_ */ +#endif /* PERI_LPI2C_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPIT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPIT.h index 6cb7349bd9..f7258a134a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPIT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPIT.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPIT ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file LPIT.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_LPIT.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for LPIT * * CMSIS Peripheral Access Layer for LPIT */ -#if !defined(LPIT_H_) -#define LPIT_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_LPIT_H_) +#define PERI_LPIT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -190,7 +193,7 @@ typedef struct { __IO uint32_t MSR; /**< Module Status, offset: 0xC */ __IO uint32_t MIER; /**< Module Interrupt Enable, offset: 0x10 */ __IO uint32_t SETTEN; /**< Set Timer Enable, offset: 0x14 */ - __O uint32_t CLRTEN; /**< Clear Timer Enable, offset: 0x18 */ + __IO uint32_t CLRTEN; /**< Clear Timer Enable, offset: 0x18 */ uint8_t RESERVED_0[4]; struct { /* offset: 0x20, array step: 0x10 */ __IO uint32_t TVAL; /**< Timer Value, array offset: 0x20, array step: 0x10 */ @@ -284,40 +287,40 @@ typedef struct { #define LPIT_MSR_TIF0_MASK (0x1U) #define LPIT_MSR_TIF0_SHIFT (0U) /*! TIF0 - Channel 0 Timer Interrupt Flag - * 0b0..Not timed out - * 0b1..Timed out * 0b0..No effect + * 0b0..Not timed out * 0b1..Clear the flag + * 0b1..Timed out */ #define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK) #define LPIT_MSR_TIF1_MASK (0x2U) #define LPIT_MSR_TIF1_SHIFT (1U) /*! TIF1 - Channel 1 Timer Interrupt Flag - * 0b0..Not timed out - * 0b1..Timed out * 0b0..No effect + * 0b0..Not timed out * 0b1..Clear the flag + * 0b1..Timed out */ #define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK) #define LPIT_MSR_TIF2_MASK (0x4U) #define LPIT_MSR_TIF2_SHIFT (2U) /*! TIF2 - Channel 2 Timer Interrupt Flag - * 0b0..Not timed out - * 0b1..Timed out * 0b0..No effect + * 0b0..Not timed out * 0b1..Clear the flag + * 0b1..Timed out */ #define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK) #define LPIT_MSR_TIF3_MASK (0x8U) #define LPIT_MSR_TIF3_SHIFT (3U) /*! TIF3 - Channel 3 Timer Interrupt Flag - * 0b0..Not timed out - * 0b1..Timed out * 0b0..No effect + * 0b0..Not timed out * 0b1..Clear the flag + * 0b1..Timed out */ #define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK) /*! @} */ @@ -564,5 +567,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* LPIT_H_ */ +#endif /* PERI_LPIT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPSPI.h index d9791f6983..7012021f8c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPSPI.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPSPI.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPSPI ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file LPSPI.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_LPSPI.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for LPSPI * * CMSIS Peripheral Access Layer for LPSPI */ -#if !defined(LPSPI_H_) -#define LPSPI_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_LPSPI_H_) +#define PERI_LPSPI_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -231,7 +234,6 @@ typedef struct { #define LPSPI_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Module Identification Number * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. - * *.. */ #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) @@ -888,5 +890,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* LPSPI_H_ */ +#endif /* PERI_LPSPI_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPTMR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPTMR.h index 5cd67e2673..9f60ec0c0c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPTMR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPTMR.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPTMR ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file LPTMR.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_LPTMR.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for LPTMR * * CMSIS Peripheral Access Layer for LPTMR */ -#if !defined(LPTMR_H_) -#define LPTMR_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_LPTMR_H_) +#define PERI_LPTMR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -362,5 +365,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* LPTMR_H_ */ +#endif /* PERI_LPTMR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPUART.h index a70b470863..f19579dd01 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPUART.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_LPUART.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPUART ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file LPUART.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_LPUART.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for LPUART * * CMSIS Peripheral Access Layer for LPUART */ -#if !defined(LPUART_H_) -#define LPUART_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_LPUART_H_) +#define PERI_LPUART_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -1482,5 +1485,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* LPUART_H_ */ +#endif /* PERI_LPUART_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MCM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MCM.h index e81c6ffcbf..208d9dd41f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MCM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MCM.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCM ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file MCM.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_MCM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MCM * * CMSIS Peripheral Access Layer for MCM */ -#if !defined(MCM_H_) -#define MCM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_MCM_H_) +#define PERI_MCM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -491,5 +494,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* MCM_H_ */ +#endif /* PERI_MCM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MEDIAMIX_BLK_CTRL.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MEDIAMIX_BLK_CTRL.h index 4d9a43751f..d1e8ea8806 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MEDIAMIX_BLK_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MEDIAMIX_BLK_CTRL.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MEDIAMIX_BLK_CTRL ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file MEDIAMIX_BLK_CTRL.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_MEDIAMIX_BLK_CTRL.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MEDIAMIX_BLK_CTRL * * CMSIS Peripheral Access Layer for MEDIAMIX_BLK_CTRL */ -#if !defined(MEDIAMIX_BLK_CTRL_H_) -#define MEDIAMIX_BLK_CTRL_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_MEDIAMIX_BLK_CTRL_H_) +#define PERI_MEDIAMIX_BLK_CTRL_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -449,8 +452,8 @@ typedef struct { #define MEDIAMIX_BLK_CTRL_LDB_CTRL_CH0_FIFO_RESET_MASK (0x800U) #define MEDIAMIX_BLK_CTRL_LDB_CTRL_CH0_FIFO_RESET_SHIFT (11U) /*! CH0_FIFO_RESET - LVDS channel 0 async FIFO software reset - * 0b1..Software reset * 0b0..No action + * 0b1..Software reset */ #define MEDIAMIX_BLK_CTRL_LDB_CTRL_CH0_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << MEDIAMIX_BLK_CTRL_LDB_CTRL_CH0_FIFO_RESET_SHIFT)) & MEDIAMIX_BLK_CTRL_LDB_CTRL_CH0_FIFO_RESET_MASK) @@ -798,6 +801,7 @@ typedef struct { #define MEDIAMIX_BLK_CTRL_CAMERA_MUX_DATA_TYPE_MASK (0x1F8U) #define MEDIAMIX_BLK_CTRL_CAMERA_MUX_DATA_TYPE_SHIFT (3U) /*! DATA_TYPE - Data type + * 0b011000..YUV420 8-bit * 0b011001..YUV420 10-bit * 0b011010..Legacy YUV420 (8-bit) * 0b011100..YUV420 8-bit (Chroma Shifted Pixel Sampling) @@ -814,7 +818,6 @@ typedef struct { * 0b101100..RAW12 * 0b101101..RAW14 * 0b110000..User define32. Align with MIPI CSI ipi_mode[8] configure to 1'b0. - * 0b011000..YUV420 8-bit * 0b110001..User define16. Align with MIPI CSI ipi_mode[8] configure to 1'b1. */ #define MEDIAMIX_BLK_CTRL_CAMERA_MUX_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MEDIAMIX_BLK_CTRL_CAMERA_MUX_DATA_TYPE_SHIFT)) & MEDIAMIX_BLK_CTRL_CAMERA_MUX_DATA_TYPE_MASK) @@ -900,18 +903,18 @@ typedef struct { #define MEDIAMIX_BLK_CTRL_DISPLAY_MUX_LCDIF_CROSS_LINE_PATTERN_MASK (0xFU) #define MEDIAMIX_BLK_CTRL_DISPLAY_MUX_LCDIF_CROSS_LINE_PATTERN_SHIFT (0U) /*! LCDIF_CROSS_LINE_PATTERN - LCDIF pixel component bit map configuration, aligned with the cross line pattern configuration on LCDIF. - * 0b1101..UYVY to YUYV from LCDIF[23:8] - * 0b1100..YUYV to YUYV from LCDIF[23:8] - * 0b1001..UYVY to YUYV from LCDIF[16:0] - * 0b1000..YUYV to YUYV from LCDIF[16:0] - * 0b0111..RGB565 to RGB565 - * 0b0110..RGB888 to RGB666 - * 0b0101..BGR888 to RGB888 - * 0b0100..BRG888 to RGB888 * 0b0000..RGB888 to RGB888 * 0b0001..RBG888 to RGB888 * 0b0010..GBR888 to RGB888 * 0b0011..GRB888 to RGB888 + * 0b0100..BRG888 to RGB888 + * 0b0101..BGR888 to RGB888 + * 0b0110..RGB888 to RGB666 + * 0b0111..RGB565 to RGB565 + * 0b1000..YUYV to YUYV from LCDIF[16:0] + * 0b1001..UYVY to YUYV from LCDIF[16:0] + * 0b1100..YUYV to YUYV from LCDIF[23:8] + * 0b1101..UYVY to YUYV from LCDIF[23:8] */ #define MEDIAMIX_BLK_CTRL_DISPLAY_MUX_LCDIF_CROSS_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << MEDIAMIX_BLK_CTRL_DISPLAY_MUX_LCDIF_CROSS_LINE_PATTERN_SHIFT)) & MEDIAMIX_BLK_CTRL_DISPLAY_MUX_LCDIF_CROSS_LINE_PATTERN_MASK) @@ -1149,11 +1152,6 @@ typedef struct { #define MEDIAMIX_BLK_CTRL_INTERFACE_CTRL_REG_DATA_TYPE_IN_MASK (0x7800000U) #define MEDIAMIX_BLK_CTRL_INTERFACE_CTRL_REG_DATA_TYPE_IN_SHIFT (23U) /*! DATA_TYPE_IN - CSI input data type - * 0b1100..Reserved - * 0b1000..Reserved - * 0b1001..Bayer 8-bit - * 0b1010..Bayer 10-bit - * 0b1011..Reserved * 0b0000..UYVY bt656 8-bit * 0b0001..UYVY bt656 10-bit * 0b0010..RGB 8-bit @@ -1162,16 +1160,21 @@ typedef struct { * 0b0101..YUV422 YVYU 8-bit * 0b0110..YUV444 YUV 8-bit * 0b0111..Reserved + * 0b1000..Reserved + * 0b1001..Bayer 8-bit + * 0b1010..Bayer 10-bit + * 0b1011..Reserved + * 0b1100..Reserved */ #define MEDIAMIX_BLK_CTRL_INTERFACE_CTRL_REG_DATA_TYPE_IN(x) (((uint32_t)(((uint32_t)(x)) << MEDIAMIX_BLK_CTRL_INTERFACE_CTRL_REG_DATA_TYPE_IN_SHIFT)) & MEDIAMIX_BLK_CTRL_INTERFACE_CTRL_REG_DATA_TYPE_IN_MASK) #define MEDIAMIX_BLK_CTRL_INTERFACE_CTRL_REG_MASK_VSYNC_CNTR_MASK (0x18000000U) #define MEDIAMIX_BLK_CTRL_INTERFACE_CTRL_REG_MASK_VSYNC_CNTR_SHIFT (27U) /*! MASK_VSYNC_CNTR - CSI mask VSYNC counter - * 0b11..Mask 3 frames * 0b00..No mask * 0b01..Mask 1 frame * 0b10..Mask 2 frames + * 0b11..Mask 3 frames */ #define MEDIAMIX_BLK_CTRL_INTERFACE_CTRL_REG_MASK_VSYNC_CNTR(x) (((uint32_t)(((uint32_t)(x)) << MEDIAMIX_BLK_CTRL_INTERFACE_CTRL_REG_MASK_VSYNC_CNTR_SHIFT)) & MEDIAMIX_BLK_CTRL_INTERFACE_CTRL_REG_MASK_VSYNC_CNTR_MASK) @@ -1256,10 +1259,10 @@ typedef struct { #define MEDIAMIX_BLK_CTRL_CSI_ERRCONTROL_1_MASK (0x200000U) #define MEDIAMIX_BLK_CTRL_CSI_ERRCONTROL_1_SHIFT (21U) /*! ERRCONTROL_1 - Control error lane 1 + * 0b0..No error detected. * 0b1..An incorrect line state sequence is detected. For example, if a turnaround request or Escape mode request * is immediately followed by a Stop state instead of the required Bridge state, this signal is asserted and * remains high until the line returns to Stop state. - * 0b0..No error detected. */ #define MEDIAMIX_BLK_CTRL_CSI_ERRCONTROL_1(x) (((uint32_t)(((uint32_t)(x)) << MEDIAMIX_BLK_CTRL_CSI_ERRCONTROL_1_SHIFT)) & MEDIAMIX_BLK_CTRL_CSI_ERRCONTROL_1_MASK) @@ -1298,10 +1301,10 @@ typedef struct { #define MEDIAMIX_BLK_CTRL_DSI_CLKSEL_MASK (0xC0U) #define MEDIAMIX_BLK_CTRL_DSI_CLKSEL_SHIFT (6U) /*! CLKSEL - Control of PLL clock output selection - * 0b10..buffered clkext - * 0b11..Forbidden * 0b00..Clocks stopped * 0b01..Clock generation + * 0b10..buffered clkext + * 0b11..Forbidden */ #define MEDIAMIX_BLK_CTRL_DSI_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIAMIX_BLK_CTRL_DSI_CLKSEL_SHIFT)) & MEDIAMIX_BLK_CTRL_DSI_CLKSEL_MASK) @@ -1400,8 +1403,8 @@ typedef struct { #define MEDIAMIX_BLK_CTRL_DSI_W1_FORCE_LOCK_MASK (0x400U) #define MEDIAMIX_BLK_CTRL_DSI_W1_FORCE_LOCK_SHIFT (10U) /*! FORCE_LOCK - PLL force lock control - * 0b1..Force PLL internal lock indication * 0b0..According to lock detector + * 0b1..Force PLL internal lock indication */ #define MEDIAMIX_BLK_CTRL_DSI_W1_FORCE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MEDIAMIX_BLK_CTRL_DSI_W1_FORCE_LOCK_SHIFT)) & MEDIAMIX_BLK_CTRL_DSI_W1_FORCE_LOCK_MASK) @@ -1464,8 +1467,8 @@ typedef struct { #define MEDIAMIX_BLK_CTRL_DSI_R1_LOCK_PLL_MASK (0x400U) #define MEDIAMIX_BLK_CTRL_DSI_R1_LOCK_PLL_SHIFT (10U) /*! LOCK_PLL - PLL lock state - * 0b1..PLL is locked * 0b0..PLL is not locked + * 0b1..PLL is locked */ #define MEDIAMIX_BLK_CTRL_DSI_R1_LOCK_PLL(x) (((uint32_t)(((uint32_t)(x)) << MEDIAMIX_BLK_CTRL_DSI_R1_LOCK_PLL_SHIFT)) & MEDIAMIX_BLK_CTRL_DSI_R1_LOCK_PLL_MASK) /*! @} */ @@ -1504,5 +1507,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* MEDIAMIX_BLK_CTRL_H_ */ +#endif /* PERI_MEDIAMIX_BLK_CTRL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MIPI_CSI.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MIPI_CSI.h index a664d028a9..b58152aba3 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MIPI_CSI.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MIPI_CSI.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIPI_CSI ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file MIPI_CSI.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_MIPI_CSI.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIPI_CSI * * CMSIS Peripheral Access Layer for MIPI_CSI */ -#if !defined(MIPI_CSI_H_) -#define MIPI_CSI_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_MIPI_CSI_H_) +#define PERI_MIPI_CSI_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -453,8 +456,8 @@ typedef struct { #define MIPI_CSI_PPI_PG_CONFIG_ppi_pg_pattern_MASK (0x1U) #define MIPI_CSI_PPI_PG_CONFIG_ppi_pg_pattern_SHIFT (0U) /*! ppi_pg_pattern - Configures the PPI Pattern Generator's pattern: - * 0b1..Horizontal Pattern * 0b0..Vertical Pattern + * 0b1..Horizontal Pattern */ #define MIPI_CSI_PPI_PG_CONFIG_ppi_pg_pattern(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_PPI_PG_CONFIG_ppi_pg_pattern_SHIFT)) & MIPI_CSI_PPI_PG_CONFIG_ppi_pg_pattern_MASK) @@ -484,8 +487,8 @@ typedef struct { #define MIPI_CSI_PPI_PG_STATUS_ppi_pg_status_MASK (0x1U) #define MIPI_CSI_PPI_PG_STATUS_ppi_pg_status_SHIFT (0U) /*! ppi_pg_status - PPI Pattern Generator status: - * 0b1..PPI PG is running * 0b0..PPIPG is inactive + * 0b1..PPI PG is running */ #define MIPI_CSI_PPI_PG_STATUS_ppi_pg_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_PPI_PG_STATUS_ppi_pg_status_SHIFT)) & MIPI_CSI_PPI_PG_STATUS_ppi_pg_status_MASK) /*! @} */ @@ -504,16 +507,16 @@ typedef struct { #define MIPI_CSI_IPI_MODE_ipi_color_com_MASK (0x100U) #define MIPI_CSI_IPI_MODE_ipi_color_com_SHIFT (8U) /*! ipi_color_com - Indicates how color mode components are delivered as follows: - * 0b1..16 bits interface * 0b0..48 bits interface + * 0b1..16 bits interface */ #define MIPI_CSI_IPI_MODE_ipi_color_com(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_IPI_MODE_ipi_color_com_SHIFT)) & MIPI_CSI_IPI_MODE_ipi_color_com_MASK) #define MIPI_CSI_IPI_MODE_ipi_cut_through_MASK (0x10000U) #define MIPI_CSI_IPI_MODE_ipi_cut_through_SHIFT (16U) /*! ipi_cut_through - Indicates cut-through mode state: - * 0b1..Cut-through mode active * 0b0..Cut-through mode inactive + * 0b1..Cut-through mode active */ #define MIPI_CSI_IPI_MODE_ipi_cut_through(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_IPI_MODE_ipi_cut_through_SHIFT)) & MIPI_CSI_IPI_MODE_ipi_cut_through_MASK) @@ -654,8 +657,8 @@ typedef struct { #define MIPI_CSI_IPI_ADV_FEATURES_ipi_sync_event_mode_MASK (0x1000000U) #define MIPI_CSI_IPI_ADV_FEATURES_ipi_sync_event_mode_SHIFT (24U) /*! ipi_sync_event_mode - For Camera Mode: - * 0b1..Legacy mode. Frame Start triggers a sync event. * 0b0..Frame Start does not trigger any sync event. + * 0b1..Legacy mode. Frame Start triggers a sync event. */ #define MIPI_CSI_IPI_ADV_FEATURES_ipi_sync_event_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_IPI_ADV_FEATURES_ipi_sync_event_mode_SHIFT)) & MIPI_CSI_IPI_ADV_FEATURES_ipi_sync_event_mode_MASK) /*! @} */ @@ -1032,5 +1035,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* MIPI_CSI_H_ */ +#endif /* PERI_MIPI_CSI_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MIPI_DSI.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MIPI_DSI.h index bd290d4c0e..1109d8f24e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MIPI_DSI.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MIPI_DSI.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIPI_DSI ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file MIPI_DSI.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_MIPI_DSI.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIPI_DSI * * CMSIS Peripheral Access Layer for MIPI_DSI */ -#if !defined(MIPI_DSI_H_) -#define MIPI_DSI_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_MIPI_DSI_H_) +#define PERI_MIPI_DSI_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -285,8 +288,8 @@ typedef struct { #define MIPI_DSI_PWR_UP_shutdownz_MASK (0x1U) #define MIPI_DSI_PWR_UP_shutdownz_SHIFT (0U) /*! shutdownz - Reset or Power up - * 0b1..Power up the controller * 0b0..Reset the controller + * 0b1..Power up the controller */ #define MIPI_DSI_PWR_UP_shutdownz(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PWR_UP_shutdownz_SHIFT)) & MIPI_DSI_PWR_UP_shutdownz_MASK) /*! @} */ @@ -481,8 +484,8 @@ typedef struct { #define MIPI_DSI_MODE_CFG_cmd_video_mode_MASK (0x1U) #define MIPI_DSI_MODE_CFG_cmd_video_mode_SHIFT (0U) /*! cmd_video_mode - Command/Video Mode - * 0b1..Command mode * 0b0..Video mode + * 0b1..Command mode */ #define MIPI_DSI_MODE_CFG_cmd_video_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_MODE_CFG_cmd_video_mode_SHIFT)) & MIPI_DSI_MODE_CFG_cmd_video_mode_MASK) /*! @} */ @@ -575,8 +578,8 @@ typedef struct { #define MIPI_DSI_VID_MODE_CFG_vpg_mode_MASK (0x100000U) #define MIPI_DSI_VID_MODE_CFG_vpg_mode_SHIFT (20U) /*! vpg_mode - VPG Mode - * 0b1..Vertical only * 0b0..Horizontal or vertical + * 0b1..Vertical only */ #define MIPI_DSI_VID_MODE_CFG_vpg_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_vpg_mode_SHIFT)) & MIPI_DSI_VID_MODE_CFG_vpg_mode_MASK) @@ -1010,8 +1013,8 @@ typedef struct { #define MIPI_DSI_SDF_3D_format_3d_MASK (0xCU) #define MIPI_DSI_SDF_3D_format_3d_SHIFT (2U) /*! format_3d - Format 3D - * 0b01..Alternating frames of left and right data * 0b00..Alternating lines of left and right data + * 0b01..Alternating frames of left and right data * 0b10..Alternating pixels of left and right data * 0b11.. */ @@ -1126,10 +1129,10 @@ typedef struct { #define MIPI_DSI_PHY_IF_CFG_n_lanes_MASK (0x3U) #define MIPI_DSI_PHY_IF_CFG_n_lanes_SHIFT (0U) /*! n_lanes - Number of Lanes - * 0b11..lanes 0, 1, 2, and 3 * 0b00..lane 0 - * 0b10..lanes 0, 1, and 2 * 0b01..lanes 0 and 1 + * 0b10..lanes 0, 1, and 2 + * 0b11..lanes 0, 1, 2, and 3 */ #define MIPI_DSI_PHY_IF_CFG_n_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_IF_CFG_n_lanes_SHIFT)) & MIPI_DSI_PHY_IF_CFG_n_lanes_MASK) @@ -1271,8 +1274,8 @@ typedef struct { #define MIPI_DSI_PHY_TST_CTRL1_phy_testen_MASK (0x10000U) #define MIPI_DSI_PHY_TST_CTRL1_phy_testen_SHIFT (16U) /*! phy_testen - PHY Test Enable - * 0b1..Address write operation is set on the falling edge of the testclk signal. * 0b0..Data write operation is set on the rising edge of the testclk signal. + * 0b1..Address write operation is set on the falling edge of the testclk signal. */ #define MIPI_DSI_PHY_TST_CTRL1_phy_testen(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TST_CTRL1_phy_testen_SHIFT)) & MIPI_DSI_PHY_TST_CTRL1_phy_testen_MASK) /*! @} */ @@ -2278,8 +2281,8 @@ typedef struct { #define MIPI_DSI_SDF_3D_ACT_format_3d_MASK (0xCU) #define MIPI_DSI_SDF_3D_ACT_format_3d_SHIFT (2U) /*! format_3d - Format 3D - * 0b01..Alternating frames of left and right data * 0b00..Alternating lines of left and right data + * 0b01..Alternating frames of left and right data * 0b10..Alternating pixels of left and right data * 0b11.. */ @@ -2341,5 +2344,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* MIPI_DSI_H_ */ +#endif /* PERI_MIPI_DSI_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MU.h index adf55f33e4..7319bfb6e7 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_MU.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for MU ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file MU.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_MU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MU * * CMSIS Peripheral Access Layer for MU */ -#if !defined(MU_H_) -#define MU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_MU_H_) +#define PERI_MU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -215,7 +218,7 @@ typedef struct { __IO uint32_t RCR; /**< Receive Control Register, offset: 0x128 */ __I uint32_t RSR; /**< Receive Status Register, offset: 0x12C */ uint8_t RESERVED_3[208]; - __O uint32_t TR[MU_TR_COUNT]; /**< Transmit Register, array offset: 0x200, array step: 0x4 */ + __IO uint32_t TR[MU_TR_COUNT]; /**< Transmit Register, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_4[112]; __I uint32_t RR[MU_RR_COUNT]; /**< Receive Register, array offset: 0x280, array step: 0x4 */ } MU_Type; @@ -798,5 +801,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* MU_H_ */ +#endif /* PERI_MU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_NPU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_NPU.h index 1af733145f..90c6acf7b1 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_NPU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_NPU.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for NPU ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NPU.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_NPU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NPU * * CMSIS Peripheral Access Layer for NPU */ -#if !defined(NPU_H_) -#define NPU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NPU_H_) +#define PERI_NPU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -1389,5 +1392,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NPU_H_ */ +#endif /* PERI_NPU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_OCRAM_MECC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_OCRAM_MECC.h index ef25b78a93..02c06821e5 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_OCRAM_MECC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_OCRAM_MECC.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for OCRAM_MECC ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file OCRAM_MECC.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_OCRAM_MECC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for OCRAM_MECC * * CMSIS Peripheral Access Layer for OCRAM_MECC */ -#if !defined(OCRAM_MECC_H_) -#define OCRAM_MECC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_OCRAM_MECC_H_) +#define PERI_OCRAM_MECC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -3641,5 +3644,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* OCRAM_MECC_H_ */ +#endif /* PERI_OCRAM_MECC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_OTFAD.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_OTFAD.h index 133e3c0c7e..a8bc76e0bd 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_OTFAD.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_OTFAD.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for OTFAD ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file OTFAD.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_OTFAD.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for OTFAD * * CMSIS Peripheral Access Layer for OTFAD */ -#if !defined(OTFAD_H_) -#define OTFAD_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_OTFAD_H_) +#define PERI_OTFAD_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -513,5 +516,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* OTFAD_H_ */ +#endif /* PERI_OTFAD_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_PDM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_PDM.h index 67775f1cf3..bc27793974 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_PDM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_PDM.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for PDM ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file PDM.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_PDM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for PDM * * CMSIS Peripheral Access Layer for PDM */ -#if !defined(PDM_H_) -#define PDM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_PDM_H_) +#define PERI_PDM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -365,12 +368,12 @@ typedef struct { #define PDM_CTRL_2_QSEL_MASK (0xE000000U) #define PDM_CTRL_2_QSEL_SHIFT (25U) /*! QSEL - Quality Mode - * 0b001..High-Quality mode * 0b000..Medium-Quality mode - * 0b111..Low-Quality mode - * 0b110..Very-Low-Quality 0 mode - * 0b101..Very-Low-Quality 1 mode + * 0b001..High-Quality mode * 0b100..Very-Low-Quality 2 mode + * 0b101..Very-Low-Quality 1 mode + * 0b110..Very-Low-Quality 0 mode + * 0b111..Low-Quality mode */ #define PDM_CTRL_2_QSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK) /*! @} */ @@ -461,8 +464,8 @@ typedef struct { #define PDM_STAT_BSY_FIL_MASK (0x80000000U) #define PDM_STAT_BSY_FIL_SHIFT (31U) /*! BSY_FIL - Busy Flag - * 0b1..MICFIL is running * 0b0..MICFIL is stopped + * 0b1..MICFIL is running */ #define PDM_STAT_BSY_FIL(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK) /*! @} */ @@ -626,80 +629,80 @@ typedef struct { #define PDM_DC_CTRL_DCCONFIG0_MASK (0x3U) #define PDM_DC_CTRL_DCCONFIG0_SHIFT (0U) /*! DCCONFIG0 - Channel 0 DC Remover Configuration - * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed */ #define PDM_DC_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK) #define PDM_DC_CTRL_DCCONFIG1_MASK (0xCU) #define PDM_DC_CTRL_DCCONFIG1_SHIFT (2U) /*! DCCONFIG1 - Channel 1 DC Remover Configuration - * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed */ #define PDM_DC_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK) #define PDM_DC_CTRL_DCCONFIG2_MASK (0x30U) #define PDM_DC_CTRL_DCCONFIG2_SHIFT (4U) /*! DCCONFIG2 - Channel 2 DC Remover Configuration - * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed */ #define PDM_DC_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK) #define PDM_DC_CTRL_DCCONFIG3_MASK (0xC0U) #define PDM_DC_CTRL_DCCONFIG3_SHIFT (6U) /*! DCCONFIG3 - Channel 3 DC Remover Configuration - * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed */ #define PDM_DC_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK) #define PDM_DC_CTRL_DCCONFIG4_MASK (0x300U) #define PDM_DC_CTRL_DCCONFIG4_SHIFT (8U) /*! DCCONFIG4 - Channel 4 DC Remover Configuration - * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed */ #define PDM_DC_CTRL_DCCONFIG4(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK) #define PDM_DC_CTRL_DCCONFIG5_MASK (0xC00U) #define PDM_DC_CTRL_DCCONFIG5_SHIFT (10U) /*! DCCONFIG5 - Channel 5 DC Remover Configuration - * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed */ #define PDM_DC_CTRL_DCCONFIG5(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK) #define PDM_DC_CTRL_DCCONFIG6_MASK (0x3000U) #define PDM_DC_CTRL_DCCONFIG6_SHIFT (12U) /*! DCCONFIG6 - Channel 6 DC Remover Configuration - * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed */ #define PDM_DC_CTRL_DCCONFIG6(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK) #define PDM_DC_CTRL_DCCONFIG7_MASK (0xC000U) #define PDM_DC_CTRL_DCCONFIG7_SHIFT (14U) /*! DCCONFIG7 - Channel 7 DC Remover Configuration - * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed */ #define PDM_DC_CTRL_DCCONFIG7(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK) /*! @} */ @@ -710,80 +713,80 @@ typedef struct { #define PDM_DC_OUT_CTRL_DCCONFIG0_MASK (0x3U) #define PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT (0U) /*! DCCONFIG0 - Channel 0 DC Remover Configuration - * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed */ #define PDM_DC_OUT_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG0_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG1_MASK (0xCU) #define PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT (2U) /*! DCCONFIG1 - Channel 1 DC Remover Configuration - * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed */ #define PDM_DC_OUT_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG1_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG2_MASK (0x30U) #define PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT (4U) /*! DCCONFIG2 - Channel 2 DC Remover Configuration - * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed */ #define PDM_DC_OUT_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG2_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG3_MASK (0xC0U) #define PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT (6U) /*! DCCONFIG3 - Channel 3 DC Remover Configuration - * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed */ #define PDM_DC_OUT_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG3_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG4_MASK (0x300U) #define PDM_DC_OUT_CTRL_DCCONFIG4_SHIFT (8U) /*! DCCONFIG4 - Channel 4 DC Remover Configuration - * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed */ #define PDM_DC_OUT_CTRL_DCCONFIG4(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG4_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG5_MASK (0xC00U) #define PDM_DC_OUT_CTRL_DCCONFIG5_SHIFT (10U) /*! DCCONFIG5 - Channel 5 DC Remover Configuration - * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed */ #define PDM_DC_OUT_CTRL_DCCONFIG5(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG5_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG6_MASK (0x3000U) #define PDM_DC_OUT_CTRL_DCCONFIG6_SHIFT (12U) /*! DCCONFIG6 - Channel 6 DC Remover Configuration - * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed */ #define PDM_DC_OUT_CTRL_DCCONFIG6(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG6_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG7_MASK (0xC000U) #define PDM_DC_OUT_CTRL_DCCONFIG7_SHIFT (14U) /*! DCCONFIG7 - Channel 7 DC Remover Configuration - * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed */ #define PDM_DC_OUT_CTRL_DCCONFIG7(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG7_MASK) /*! @} */ @@ -1204,8 +1207,8 @@ typedef struct { #define PDM_VAD0_CTRL_2_VADFRENDIS_MASK (0x80000000U) #define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT (31U) /*! VADFRENDIS - Voice Activity Detector Frame Energy Disable - * 0b1..Disables * 0b0..Enables + * 0b1..Disables */ #define PDM_VAD0_CTRL_2_VADFRENDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK) /*! @} */ @@ -1410,5 +1413,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* PDM_H_ */ +#endif /* PERI_PDM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_PLL.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_PLL.h index 1d2b5f480c..31254ef680 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_PLL.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_PLL.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for PLL ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file PLL.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_PLL.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for PLL * * CMSIS Peripheral Access Layer for PLL */ -#if !defined(PLL_H_) -#define PLL_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_PLL_H_) +#define PERI_PLL_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -495,5 +498,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* PLL_H_ */ +#endif /* PERI_PLL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_PXP.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_PXP.h index ac2314a7b7..5f6fcb2b81 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_PXP.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_PXP.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for PXP ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file PXP.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_PXP.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for PXP * * CMSIS Peripheral Access Layer for PXP */ -#if !defined(PXP_H_) -#define PXP_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_PXP_H_) +#define PERI_PXP_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -4186,5 +4189,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* PXP_H_ */ +#endif /* PERI_PXP_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_RGPIO.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_RGPIO.h index fac7e238c7..227b121c8a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_RGPIO.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_RGPIO.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for RGPIO ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file RGPIO.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_RGPIO.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for RGPIO * * CMSIS Peripheral Access Layer for RGPIO */ -#if !defined(RGPIO_H_) -#define RGPIO_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_RGPIO_H_) +#define PERI_RGPIO_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -196,17 +199,17 @@ typedef struct { __IO uint32_t ICNP; /**< Interrupt Control Non-Privilege, offset: 0x1C */ uint8_t RESERVED_1[32]; __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x40 */ - __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x44 */ - __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x48 */ - __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0x4C */ + __IO uint32_t PSOR; /**< Port Set Output Register, offset: 0x44 */ + __IO uint32_t PCOR; /**< Port Clear Output Register, offset: 0x48 */ + __IO uint32_t PTOR; /**< Port Toggle Output Register, offset: 0x4C */ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x50 */ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x54 */ __IO uint32_t PIDR; /**< Port Input Disable Register, offset: 0x58 */ uint8_t RESERVED_2[4]; __IO uint8_t PDR[RGPIO_PDR_COUNT]; /**< Pin Data Register a, array offset: 0x60, array step: 0x1 */ __IO uint32_t ICR[RGPIO_ICR_COUNT]; /**< Interrupt Control Register 0..Interrupt Control Register 31, array offset: 0x80, array step: 0x4 */ - __O uint32_t GICLR; /**< Global Interrupt Control Low Register, offset: 0x100 */ - __O uint32_t GICHR; /**< Global Interrupt Control High Register, offset: 0x104 */ + __IO uint32_t GICLR; /**< Global Interrupt Control Low Register, offset: 0x100 */ + __IO uint32_t GICHR; /**< Global Interrupt Control High Register, offset: 0x104 */ uint8_t RESERVED_3[24]; __IO uint32_t ISFR[RGPIO_ISFR_COUNT]; /**< Interrupt Status Flag Register, array offset: 0x120, array step: 0x4 */ } RGPIO_Type; @@ -3764,5 +3767,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* RGPIO_H_ */ +#endif /* PERI_RGPIO_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_S3MU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_S3MU.h index 3f06955b0e..9b3782f676 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_S3MU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_S3MU.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for S3MU ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file S3MU.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_S3MU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for S3MU * * CMSIS Peripheral Access Layer for S3MU */ -#if !defined(S3MU_H_) -#define S3MU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_S3MU_H_) +#define PERI_S3MU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -196,7 +199,7 @@ typedef struct { __I uint32_t RSR; /**< Receive Status Register, offset: 0x12C */ uint8_t RESERVED_1[204]; __IO uint32_t UNUSED1; /**< Unused Register 1, offset: 0x1FC */ - __O uint32_t TR[S3MU_TR_COUNT]; /**< Transmit Register, array offset: 0x200, array step: 0x4 */ + __IO uint32_t TR[S3MU_TR_COUNT]; /**< Transmit Register, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_2[96]; __I uint32_t RR[S3MU_RR_COUNT]; /**< Receive Register, array offset: 0x280, array step: 0x4 */ } S3MU_Type; @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* S3MU_H_ */ +#endif /* PERI_S3MU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SEMA42.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SEMA42.h index eeb621d01c..2843ceffbc 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SEMA42.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SEMA42.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for SEMA42 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SEMA42.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_SEMA42.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SEMA42 * * CMSIS Peripheral Access Layer for SEMA42 */ -#if !defined(SEMA42_H_) -#define SEMA42_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SEMA42_H_) +#define PERI_SEMA42_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -1998,5 +2001,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SEMA42_H_ */ +#endif /* PERI_SEMA42_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SPDIF.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SPDIF.h index 0da3a97727..abf777e5b0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SPDIF.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SPDIF.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for SPDIF ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SPDIF.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_SPDIF.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SPDIF * * CMSIS Peripheral Access Layer for SPDIF */ -#if !defined(SPDIF_H_) -#define SPDIF_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SPDIF_H_) +#define PERI_SPDIF_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -1043,5 +1046,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SPDIF_H_ */ +#endif /* PERI_SPDIF_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SRC_GENERAL_REG.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SRC_GENERAL_REG.h index 41cd7b339a..9c7b26a18f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SRC_GENERAL_REG.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SRC_GENERAL_REG.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for SRC_GENERAL_REG ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SRC_GENERAL_REG.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_SRC_GENERAL_REG.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SRC_GENERAL_REG * * CMSIS Peripheral Access Layer for SRC_GENERAL_REG */ -#if !defined(SRC_GENERAL_REG_H_) -#define SRC_GENERAL_REG_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SRC_GENERAL_REG_H_) +#define PERI_SRC_GENERAL_REG_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -1154,5 +1157,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SRC_GENERAL_REG_H_ */ +#endif /* PERI_SRC_GENERAL_REG_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SRC_MEM_SLICE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SRC_MEM_SLICE.h index 3fc26e2ab8..29a37fbcd9 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SRC_MEM_SLICE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SRC_MEM_SLICE.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for SRC_MEM_SLICE ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SRC_MEM_SLICE.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_SRC_MEM_SLICE.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SRC_MEM_SLICE * * CMSIS Peripheral Access Layer for SRC_MEM_SLICE */ -#if !defined(SRC_MEM_SLICE_H_) -#define SRC_MEM_SLICE_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SRC_MEM_SLICE_H_) +#define PERI_SRC_MEM_SLICE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -335,5 +338,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SRC_MEM_SLICE_H_ */ +#endif /* PERI_SRC_MEM_SLICE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SRC_MIX_SLICE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SRC_MIX_SLICE.h index 6fb8ac437d..1bce346eea 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SRC_MIX_SLICE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SRC_MIX_SLICE.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for SRC_MIX_SLICE ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SRC_MIX_SLICE.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_SRC_MIX_SLICE.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SRC_MIX_SLICE * * CMSIS Peripheral Access Layer for SRC_MIX_SLICE */ -#if !defined(SRC_MIX_SLICE_H_) -#define SRC_MIX_SLICE_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SRC_MIX_SLICE_H_) +#define PERI_SRC_MIX_SLICE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -581,32 +584,32 @@ typedef struct { #define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_2_MASK (0x10U) #define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_2_SHIFT (4U) /*! RST_CTRL_SOFT_2 - Locked by LPM_MODE field. - * 0b1..No effect or software reset deassert * 0b0..Software reset assert + * 0b1..No effect or software reset deassert */ #define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_2_SHIFT)) & SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_2_MASK) #define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_3_MASK (0x40U) #define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_3_SHIFT (6U) /*! RST_CTRL_SOFT_3 - Locked by LPM_MODE field. - * 0b1..No effect or software reset deassert * 0b0..Software reset assert + * 0b1..No effect or software reset deassert */ #define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_3_SHIFT)) & SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_3_MASK) #define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_4_MASK (0x100U) #define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_4_SHIFT (8U) /*! RST_CTRL_SOFT_4 - Locked by LPM_MODE field. - * 0b1..No effect or software reset deassert * 0b0..Software reset assert + * 0b1..No effect or software reset deassert */ #define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_4(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_4_SHIFT)) & SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_4_MASK) #define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_5_MASK (0x400U) #define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_5_SHIFT (10U) /*! RST_CTRL_SOFT_5 - Locked by LPM_MODE field. - * 0b1..No effect or software reset deassert * 0b0..software reset assert + * 0b1..No effect or software reset deassert */ #define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_5(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_5_SHIFT)) & SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_5_MASK) /*! @} */ @@ -1059,5 +1062,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SRC_MIX_SLICE_H_ */ +#endif /* PERI_SRC_MIX_SLICE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SYSPM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SYSPM.h index 6ea887a55a..8dc7608de2 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SYSPM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SYSPM.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSPM ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SYSPM.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_SYSPM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SYSPM * * CMSIS Peripheral Access Layer for SYSPM */ -#if !defined(SYSPM_H_) -#define SYSPM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SYSPM_H_) +#define PERI_SYSPM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -386,5 +389,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SYSPM_H_ */ +#endif /* PERI_SYSPM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SYS_CTR_COMPARE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SYS_CTR_COMPARE.h index 1504324556..4f7bd67d43 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SYS_CTR_COMPARE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SYS_CTR_COMPARE.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYS_CTR_COMPARE ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SYS_CTR_COMPARE.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_SYS_CTR_COMPARE.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SYS_CTR_COMPARE * * CMSIS Peripheral Access Layer for SYS_CTR_COMPARE */ -#if !defined(SYS_CTR_COMPARE_H_) -#define SYS_CTR_COMPARE_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SYS_CTR_COMPARE_H_) +#define PERI_SYS_CTR_COMPARE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -339,5 +342,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SYS_CTR_COMPARE_H_ */ +#endif /* PERI_SYS_CTR_COMPARE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SYS_CTR_CONTROL.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SYS_CTR_CONTROL.h index ea94a58008..bbe9b1859a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SYS_CTR_CONTROL.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SYS_CTR_CONTROL.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYS_CTR_CONTROL ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SYS_CTR_CONTROL.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_SYS_CTR_CONTROL.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SYS_CTR_CONTROL * * CMSIS Peripheral Access Layer for SYS_CTR_CONTROL */ -#if !defined(SYS_CTR_CONTROL_H_) -#define SYS_CTR_CONTROL_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SYS_CTR_CONTROL_H_) +#define PERI_SYS_CTR_CONTROL_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -368,5 +371,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SYS_CTR_CONTROL_H_ */ +#endif /* PERI_SYS_CTR_CONTROL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SYS_CTR_READ.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SYS_CTR_READ.h index afc39db10f..e2413e8dee 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SYS_CTR_READ.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_SYS_CTR_READ.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYS_CTR_READ ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SYS_CTR_READ.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_SYS_CTR_READ.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SYS_CTR_READ * * CMSIS Peripheral Access Layer for SYS_CTR_READ */ -#if !defined(SYS_CTR_READ_H_) -#define SYS_CTR_READ_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SYS_CTR_READ_H_) +#define PERI_SYS_CTR_READ_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -258,5 +261,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SYS_CTR_READ_H_ */ +#endif /* PERI_SYS_CTR_READ_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TCM_ECC_MCM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TCM_ECC_MCM.h index ac1bdbff87..8c0eeee746 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TCM_ECC_MCM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TCM_ECC_MCM.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for TCM_ECC_MCM ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TCM_ECC_MCM.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_TCM_ECC_MCM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TCM_ECC_MCM * * CMSIS Peripheral Access Layer for TCM_ECC_MCM */ -#if !defined(TCM_ECC_MCM_H_) -#define TCM_ECC_MCM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TCM_ECC_MCM_H_) +#define PERI_TCM_ECC_MCM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -219,16 +222,16 @@ typedef struct { #define TCM_ECC_MCM_TCMECCR_WECC_DIS_MASK (0x1U) #define TCM_ECC_MCM_TCMECCR_WECC_DIS_SHIFT (0U) /*! WECC_DIS - Disable TCM ECC Write Generation - * 0b1..Disable ECC generation on TCM write data * 0b0..Enable ECC generation on TCM write data + * 0b1..Disable ECC generation on TCM write data */ #define TCM_ECC_MCM_TCMECCR_WECC_DIS(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_TCMECCR_WECC_DIS_SHIFT)) & TCM_ECC_MCM_TCMECCR_WECC_DIS_MASK) #define TCM_ECC_MCM_TCMECCR_RECC_DIS_MASK (0x2U) #define TCM_ECC_MCM_TCMECCR_RECC_DIS_SHIFT (1U) /*! RECC_DIS - Disable TCM ECC Read Check - * 0b1..Disable ECC check on TCM read data * 0b0..Enable ECC check on TCM read data + * 0b1..Disable ECC check on TCM read data */ #define TCM_ECC_MCM_TCMECCR_RECC_DIS(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_TCMECCR_RECC_DIS_SHIFT)) & TCM_ECC_MCM_TCMECCR_RECC_DIS_MASK) /*! @} */ @@ -575,5 +578,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TCM_ECC_MCM_H_ */ +#endif /* PERI_TCM_ECC_MCM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TMU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TMU.h index 84fd760d29..654a8a701a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TMU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TMU.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for TMU ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TMU.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_TMU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TMU * * CMSIS Peripheral Access Layer for TMU */ -#if !defined(TMU_H_) -#define TMU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TMU_H_) +#define PERI_TMU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -241,28 +244,28 @@ typedef struct { #define TMU_TMR_ALPF_MASK (0x3000000U) #define TMU_TMR_ALPF_SHIFT (24U) /*! ALPF - Average Low Pass Filter Setting - * 0b11..0.125 - * 0b10..0.25 - * 0b01..0.5 * 0b00..1.0 + * 0b01..0.5 + * 0b10..0.25 + * 0b11..0.125 */ #define TMU_TMR_ALPF(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMR_ALPF_SHIFT)) & TMU_TMR_ALPF_MASK) #define TMU_TMR_CMD_MASK (0x20000000U) #define TMU_TMR_CMD_SHIFT (29U) /*! CMD - Central Module Disable - * 0b1..Disabled * 0b0..Enabled + * 0b1..Disabled */ #define TMU_TMR_CMD(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMR_CMD_SHIFT)) & TMU_TMR_CMD_MASK) #define TMU_TMR_MODE_MASK (0xC0000000U) #define TMU_TMR_MODE_SHIFT (30U) /*! MODE - Mode - * 0b11..Reserved - * 0b10..Monitoring of sites as defined by TMSR[SITE] - * 0b01..Reserved * 0b00..Idle; low-power mode + * 0b01..Reserved + * 0b10..Monitoring of sites as defined by TMSR[SITE] + * 0b11..Reserved */ #define TMU_TMR_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMR_MODE_SHIFT)) & TMU_TMR_MODE_MASK) /*! @} */ @@ -273,32 +276,32 @@ typedef struct { #define TMU_TSR_ORH_MASK (0x10000000U) #define TMU_TSR_ORH_SHIFT (28U) /*! ORH - Out-of-Range High Temperature Measurement - * 0b1..Out-of-range high temperature measurement detected * 0b0..No out-of-range high temperature measurement detected + * 0b1..Out-of-range high temperature measurement detected */ #define TMU_TSR_ORH(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_ORH_SHIFT)) & TMU_TSR_ORH_MASK) #define TMU_TSR_ORL_MASK (0x20000000U) #define TMU_TSR_ORL_SHIFT (29U) /*! ORL - Out-of-Range Low Temperature Measurement - * 0b1..Out-of-range low temperature measurement detected * 0b0..No out-of-range low temperature measurement detected + * 0b1..Out-of-range low temperature measurement detected */ #define TMU_TSR_ORL(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_ORL_SHIFT)) & TMU_TSR_ORL_MASK) #define TMU_TSR_MIE_MASK (0x40000000U) #define TMU_TSR_MIE_SHIFT (30U) /*! MIE - Monitoring Interval Exceeded - * 0b1..Monitoring interval exceeded * 0b0..Monitoring interval not exceeded + * 0b1..Monitoring interval exceeded */ #define TMU_TSR_MIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_MIE_SHIFT)) & TMU_TSR_MIE_MASK) #define TMU_TSR_TB_MASK (0x80000000U) #define TMU_TSR_TB_SHIFT (31U) /*! TB - TMU Busy - * 0b1..TMU is busy * 0b0..TMU is idle + * 0b1..TMU is busy */ #define TMU_TSR_TB(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_TB_SHIFT)) & TMU_TSR_TB_MASK) /*! @} */ @@ -327,64 +330,64 @@ typedef struct { #define TMU_TIER_FTRCTIE_MASK (0x1000000U) #define TMU_TIER_FTRCTIE_SHIFT (24U) /*! FTRCTIE - Falling Temperature Rate Critical Threshold Interrupt Enable - * 0b1..Interrupt enabled; generates an interrupt if TIDR[FTRCT] is 1 * 0b0..Disabled + * 0b1..Interrupt enabled; generates an interrupt if TIDR[FTRCT] is 1 */ #define TMU_TIER_FTRCTIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_FTRCTIE_SHIFT)) & TMU_TIER_FTRCTIE_MASK) #define TMU_TIER_RTRCTIE_MASK (0x2000000U) #define TMU_TIER_RTRCTIE_SHIFT (25U) /*! RTRCTIE - Rising Temperature Rate Critical Threshold Interrupt Enable - * 0b1..Interrupt enabled; generates an interrupt if TIDR[RTRCT] is 1 * 0b0..Disabled + * 0b1..Interrupt enabled; generates an interrupt if TIDR[RTRCT] is 1 */ #define TMU_TIER_RTRCTIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_RTRCTIE_SHIFT)) & TMU_TIER_RTRCTIE_MASK) #define TMU_TIER_ALTCTIE_MASK (0x4000000U) #define TMU_TIER_ALTCTIE_SHIFT (26U) /*! ALTCTIE - Average Low Temperature Critical Threshold Interrupt Enable - * 0b1..Interrupt enabled; generates an interrupt if TIDR[ALTCT] is 1 * 0b0..Disabled + * 0b1..Interrupt enabled; generates an interrupt if TIDR[ALTCT] is 1 */ #define TMU_TIER_ALTCTIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ALTCTIE_SHIFT)) & TMU_TIER_ALTCTIE_MASK) #define TMU_TIER_ALTTIE_MASK (0x8000000U) #define TMU_TIER_ALTTIE_SHIFT (27U) /*! ALTTIE - Average Low Temperature Threshold Interrupt Enable - * 0b1..Interrupt enabled; generates an interrupt if TIDR[ALTT] is 1 * 0b0..Disabled + * 0b1..Interrupt enabled; generates an interrupt if TIDR[ALTT] is 1 */ #define TMU_TIER_ALTTIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ALTTIE_SHIFT)) & TMU_TIER_ALTTIE_MASK) #define TMU_TIER_ILTTIE_MASK (0x10000000U) #define TMU_TIER_ILTTIE_SHIFT (28U) /*! ILTTIE - Immediate Low Temperature Threshold Interrupt Enable - * 0b1..Interrupt enabled; generates an interrupt if TIDR[ILTT] is 1 * 0b0..Disabled + * 0b1..Interrupt enabled; generates an interrupt if TIDR[ILTT] is 1 */ #define TMU_TIER_ILTTIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ILTTIE_SHIFT)) & TMU_TIER_ILTTIE_MASK) #define TMU_TIER_AHTCTIE_MASK (0x20000000U) #define TMU_TIER_AHTCTIE_SHIFT (29U) /*! AHTCTIE - Average High Temperature Critical Threshold Interrupt Enable - * 0b1..Interrupt enabled; generates an interrupt if TIDR[AHTCT] is 1 * 0b0..Disabled + * 0b1..Interrupt enabled; generates an interrupt if TIDR[AHTCT] is 1 */ #define TMU_TIER_AHTCTIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_AHTCTIE_SHIFT)) & TMU_TIER_AHTCTIE_MASK) #define TMU_TIER_AHTTIE_MASK (0x40000000U) #define TMU_TIER_AHTTIE_SHIFT (30U) /*! AHTTIE - Average High Temperature Threshold Interrupt Enable - * 0b1..Interrupt enabled; generates an interrupt if TIDR[AHTT] is 1 * 0b0..Disabled + * 0b1..Interrupt enabled; generates an interrupt if TIDR[AHTT] is 1 */ #define TMU_TIER_AHTTIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_AHTTIE_SHIFT)) & TMU_TIER_AHTTIE_MASK) #define TMU_TIER_IHTTIE_MASK (0x80000000U) #define TMU_TIER_IHTTIE_SHIFT (31U) /*! IHTTIE - Immediate High Temperature Threshold Interrupt Enable - * 0b1..Interrupt enabled; generates an interrupt if TIDR[IHTT] is 1 * 0b0..Disabled + * 0b1..Interrupt enabled; generates an interrupt if TIDR[IHTT] is 1 */ #define TMU_TIER_IHTTIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_IHTTIE_SHIFT)) & TMU_TIER_IHTTIE_MASK) /*! @} */ @@ -395,74 +398,74 @@ typedef struct { #define TMU_TIDR_FTRCT_MASK (0x1000000U) #define TMU_TIDR_FTRCT_SHIFT (24U) /*! FTRCT - Falling Temperature Rate Critical Threshold + * 0b0..No threshold exceeded * 0b1..One or more monitored sites exceed the falling temperature rate critical threshold, as defined by . * TICSCR[SITE] captures the sites that exceed the threshold. - * 0b0..No threshold exceeded */ #define TMU_TIDR_FTRCT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_FTRCT_SHIFT)) & TMU_TIDR_FTRCT_MASK) #define TMU_TIDR_RTRCT_MASK (0x2000000U) #define TMU_TIDR_RTRCT_SHIFT (25U) /*! RTRCT - Rising Temperature Rate Critical Threshold + * 0b0..No threshold exceeded * 0b1..One or more monitored sites pass the rising temperature rate critical threshold, as defined by . * TICSCR[SITE] captures the sites that exceed the threshold. - * 0b0..No threshold exceeded */ #define TMU_TIDR_RTRCT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_RTRCT_SHIFT)) & TMU_TIDR_RTRCT_MASK) #define TMU_TIDR_ALTCT_MASK (0x4000000U) #define TMU_TIDR_ALTCT_SHIFT (26U) /*! ALTCT - Average Low Temperature Critical Threshold + * 0b0..No threshold exceeded * 0b1..One or more monitored sites pass the average low temperature threshold, as defined by . TICSCR[SITE] * captures the sites that pass the threshold. - * 0b0..No threshold exceeded */ #define TMU_TIDR_ALTCT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ALTCT_SHIFT)) & TMU_TIDR_ALTCT_MASK) #define TMU_TIDR_ALTT_MASK (0x8000000U) #define TMU_TIDR_ALTT_SHIFT (27U) /*! ALTT - Average Low Temperature Threshold + * 0b0..No threshold exceeded * 0b1..One or more monitored sites pass the average low temperature threshold, as defined by . TIASCR[SITE] * captures the sites that pass the threshold. - * 0b0..No threshold exceeded */ #define TMU_TIDR_ALTT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ALTT_SHIFT)) & TMU_TIDR_ALTT_MASK) #define TMU_TIDR_ILTT_MASK (0x10000000U) #define TMU_TIDR_ILTT_SHIFT (28U) /*! ILTT - Immediate Low Temperature Threshold + * 0b0..No threshold exceeded * 0b1..One or more monitored sites has passed the immediate low temperature threshold, as defined by . This * includes an out-of-range measured temperature below the minimum calibrated temperature. TIISCR[SITE] captures * the sites that pass the threshold. - * 0b0..No threshold exceeded */ #define TMU_TIDR_ILTT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ILTT_SHIFT)) & TMU_TIDR_ILTT_MASK) #define TMU_TIDR_AHTCT_MASK (0x20000000U) #define TMU_TIDR_AHTCT_SHIFT (29U) /*! AHTCT - Average High Temperature Critical Threshold Exceeded + * 0b0..No threshold exceeded * 0b1..One or more monitored sites exceed the average high temperature critical threshold, as defined by . * TICSCR[SITE] captures the sites that exceed the threshold. - * 0b0..No threshold exceeded */ #define TMU_TIDR_AHTCT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_AHTCT_SHIFT)) & TMU_TIDR_AHTCT_MASK) #define TMU_TIDR_AHTT_MASK (0x40000000U) #define TMU_TIDR_AHTT_SHIFT (30U) /*! AHTT - Average High Temperature Threshold Exceeded + * 0b0..No threshold exceeded * 0b1..One or more monitored sites exceed the average high temperature threshold, as defined by . TIASCR[SITE] * captures the sites that exceed the threshold. - * 0b0..No threshold exceeded */ #define TMU_TIDR_AHTT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_AHTT_SHIFT)) & TMU_TIDR_AHTT_MASK) #define TMU_TIDR_IHTT_MASK (0x80000000U) #define TMU_TIDR_IHTT_SHIFT (31U) /*! IHTT - Immediate High Temperature Threshold Exceeded + * 0b0..No threshold exceeded * 0b1..One or more monitored sites has exceeded the immediate high temperature threshold, as defined by . This * includes an out-of-range measured temperature above the maximum calibrated temperature. TIISCR[SITE] * captures the sites that exceed the threshold. - * 0b0..No threshold exceeded */ #define TMU_TIDR_IHTT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_IHTT_SHIFT)) & TMU_TIDR_IHTT_MASK) /*! @} */ @@ -510,8 +513,8 @@ typedef struct { #define TMU_TMHTCR_V_MASK (0x80000000U) #define TMU_TMHTCR_V_SHIFT (31U) /*! V - Valid Reading - * 0b1..Temperature reading is valid * 0b0..Temperature reading is not valid due to no measured temperature within the calibrated sensor range for an enabled monitored site + * 0b1..Temperature reading is valid */ #define TMU_TMHTCR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTCR_V_SHIFT)) & TMU_TMHTCR_V_MASK) /*! @} */ @@ -532,8 +535,8 @@ typedef struct { #define TMU_TMLTCR_V_MASK (0x80000000U) #define TMU_TMLTCR_V_SHIFT (31U) /*! V - Valid Reading - * 0b1..Temperature reading is valid * 0b0..Temperature reading is not valid because of no measured temperature within the sensor calibration range for an enabled monitored site + * 0b1..Temperature reading is valid */ #define TMU_TMLTCR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMLTCR_V_SHIFT)) & TMU_TMLTCR_V_MASK) /*! @} */ @@ -549,9 +552,9 @@ typedef struct { #define TMU_TMRTRCR_V_MASK (0x80000000U) #define TMU_TMRTRCR_V_SHIFT (31U) /*! V - Valid Reading - * 0b1..Temperature reading is valid * 0b0..Temperature reading is not valid because of no two successive measured temperatures within the sensor * calibration range for an enabled monitored site + * 0b1..Temperature reading is valid */ #define TMU_TMRTRCR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMRTRCR_V_SHIFT)) & TMU_TMRTRCR_V_MASK) /*! @} */ @@ -567,9 +570,9 @@ typedef struct { #define TMU_TMFTRCR_V_MASK (0x80000000U) #define TMU_TMFTRCR_V_SHIFT (31U) /*! V - Valid Reading - * 0b1..Temperature reading is valid * 0b0..Temperature reading is not valid because of no two successive measured temperatures within the sensor * calibration range for an enabled monitored site + * 0b1..Temperature reading is valid */ #define TMU_TMFTRCR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMFTRCR_V_SHIFT)) & TMU_TMFTRCR_V_MASK) /*! @} */ @@ -585,8 +588,8 @@ typedef struct { #define TMU_TMHTITR_EN_MASK (0x80000000U) #define TMU_TMHTITR_EN_SHIFT (31U) /*! EN - Enable Threshold - * 0b1..Threshold enabled * 0b0..Disabled + * 0b1..Threshold enabled */ #define TMU_TMHTITR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_EN_SHIFT)) & TMU_TMHTITR_EN_MASK) /*! @} */ @@ -602,8 +605,8 @@ typedef struct { #define TMU_TMHTATR_EN_MASK (0x80000000U) #define TMU_TMHTATR_EN_SHIFT (31U) /*! EN - Enable Threshold - * 0b1..Threshold enabled * 0b0..Disabled + * 0b1..Threshold enabled */ #define TMU_TMHTATR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_EN_SHIFT)) & TMU_TMHTATR_EN_MASK) /*! @} */ @@ -619,8 +622,8 @@ typedef struct { #define TMU_TMHTACTR_EN_MASK (0x80000000U) #define TMU_TMHTACTR_EN_SHIFT (31U) /*! EN - Enable Threshold - * 0b1..Threshold enabled * 0b0..Disabled + * 0b1..Threshold enabled */ #define TMU_TMHTACTR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_EN_SHIFT)) & TMU_TMHTACTR_EN_MASK) /*! @} */ @@ -636,8 +639,8 @@ typedef struct { #define TMU_TMLTITR_EN_MASK (0x80000000U) #define TMU_TMLTITR_EN_SHIFT (31U) /*! EN - Enable Threshold - * 0b1..Threshold enabled * 0b0..Disabled + * 0b1..Threshold enabled */ #define TMU_TMLTITR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMLTITR_EN_SHIFT)) & TMU_TMLTITR_EN_MASK) /*! @} */ @@ -653,8 +656,8 @@ typedef struct { #define TMU_TMLTATR_EN_MASK (0x80000000U) #define TMU_TMLTATR_EN_SHIFT (31U) /*! EN - Enable Threshold - * 0b1..Threshold enabled * 0b0..Disabled + * 0b1..Threshold enabled */ #define TMU_TMLTATR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMLTATR_EN_SHIFT)) & TMU_TMLTATR_EN_MASK) /*! @} */ @@ -670,8 +673,8 @@ typedef struct { #define TMU_TMLTACTR_EN_MASK (0x80000000U) #define TMU_TMLTACTR_EN_SHIFT (31U) /*! EN - Enable Threshold - * 0b1..Threshold enabled * 0b0..Disabled + * 0b1..Threshold enabled */ #define TMU_TMLTACTR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMLTACTR_EN_SHIFT)) & TMU_TMLTACTR_EN_MASK) /*! @} */ @@ -687,8 +690,8 @@ typedef struct { #define TMU_TMRTRCTR_EN_MASK (0x80000000U) #define TMU_TMRTRCTR_EN_SHIFT (31U) /*! EN - Enable Threshold - * 0b1..Threshold enabled * 0b0..Disabled + * 0b1..Threshold enabled */ #define TMU_TMRTRCTR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMRTRCTR_EN_SHIFT)) & TMU_TMRTRCTR_EN_MASK) /*! @} */ @@ -704,8 +707,8 @@ typedef struct { #define TMU_TMFTRCTR_EN_MASK (0x80000000U) #define TMU_TMFTRCTR_EN_SHIFT (31U) /*! EN - Enable threshold - * 0b1..Threshold Enabled * 0b0..Disabled + * 0b1..Threshold Enabled */ #define TMU_TMFTRCTR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMFTRCTR_EN_SHIFT)) & TMU_TMFTRCTR_EN_MASK) /*! @} */ @@ -744,8 +747,8 @@ typedef struct { #define TMU_TRITSR_V_MASK (0x80000000U) #define TMU_TRITSR_V_SHIFT (31U) /*! V - Valid Measured Temperature - * 0b1..Valid * 0b0..Not valid; temperature is out of sensor calibration range or the first measurement is still pending + * 0b1..Valid */ #define TMU_TRITSR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_V_SHIFT)) & TMU_TRITSR_V_MASK) /*! @} */ @@ -764,8 +767,8 @@ typedef struct { #define TMU_TRATSR_V_MASK (0x80000000U) #define TMU_TRATSR_V_SHIFT (31U) /*! V - Valid Measured Temperature - * 0b1..Valid * 0b0..Not valid; temperature is out of sensor range or the first measurement is still pending + * 0b1..Valid */ #define TMU_TRATSR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_V_SHIFT)) & TMU_TRATSR_V_MASK) /*! @} */ @@ -799,8 +802,8 @@ typedef struct { #define TMU_TCMCFG_SAR_RDY_MASK (0x10000U) #define TMU_TCMCFG_SAR_RDY_SHIFT (16U) /*! SAR_RDY - SAR Ready - * 0b1..SAR ready to receive command * 0b0..SAR not ready to receive command + * 0b1..SAR ready to receive command */ #define TMU_TCMCFG_SAR_RDY(x) (((uint32_t)(((uint32_t)(x)) << TMU_TCMCFG_SAR_RDY_SHIFT)) & TMU_TCMCFG_SAR_RDY_MASK) @@ -841,8 +844,8 @@ typedef struct { #define TMU_TTRCR_V_MASK (0x80000000U) #define TMU_TTRCR_V_SHIFT (31U) /*! V - Calibration Point is Valid - * 0b1..Valid * 0b0..Not valid + * 0b1..Valid */ #define TMU_TTRCR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TTRCR_V_SHIFT)) & TMU_TTRCR_V_MASK) /*! @} */ @@ -884,5 +887,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TMU_H_ */ +#endif /* PERI_TMU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TPM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TPM.h index 31b0c51c3d..6098dad7e4 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TPM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TPM.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for TPM ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TPM.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_TPM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TPM * * CMSIS Peripheral Access Layer for TPM */ -#if !defined(TPM_H_) -#define TPM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TPM_H_) +#define PERI_TPM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -760,5 +763,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TPM_H_ */ +#endif /* PERI_TPM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TRDC_MBC0.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TRDC_MBC0.h index bc7d50212f..44e317c11b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TRDC_MBC0.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TRDC_MBC0.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRDC_MBC0 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TRDC_MBC0.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_TRDC_MBC0.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TRDC_MBC0 * * CMSIS Peripheral Access Layer for TRDC_MBC0 */ -#if !defined(TRDC_MBC0_H_) -#define TRDC_MBC0_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TRDC_MBC0_H_) +#define PERI_TRDC_MBC0_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -587,5 +590,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TRDC_MBC0_H_ */ +#endif /* PERI_TRDC_MBC0_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TRDC_MBC2.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TRDC_MBC2.h index aafe494f34..be301484be 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TRDC_MBC2.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TRDC_MBC2.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRDC_MBC2 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TRDC_MBC2.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_TRDC_MBC2.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TRDC_MBC2 * * CMSIS Peripheral Access Layer for TRDC_MBC2 */ -#if !defined(TRDC_MBC2_H_) -#define TRDC_MBC2_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TRDC_MBC2_H_) +#define PERI_TRDC_MBC2_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -378,14 +381,14 @@ typedef struct { __I uint32_t W0; /**< MBC Domain Error Word0 Register, array offset: 0x400, array step: 0x10 */ __I uint32_t W1; /**< MBC Domain Error Word1 Register, array offset: 0x404, array step: 0x10 */ uint8_t RESERVED_0[4]; - __O uint32_t W3; /**< MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10 */ + __IO uint32_t W3; /**< MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10 */ } MBC_DERR[TRDC_MBC2_MBC_DERR_COUNT]; uint8_t RESERVED_5[96]; struct { /* offset: 0x480, array step: 0x10 */ __I uint32_t W0; /**< MRC Domain Error Word0 Register, array offset: 0x480, array step: 0x10, irregular array, not all indices are valid */ __I uint32_t W1; /**< MRC Domain Error Word1 Register, array offset: 0x484, array step: 0x10, irregular array, not all indices are valid */ uint8_t RESERVED_0[4]; - __O uint32_t W3; /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10, irregular array, not all indices are valid */ + __IO uint32_t W3; /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10, irregular array, not all indices are valid */ } MRC_DERR[TRDC_MBC2_MRC_DERR_COUNT]; uint8_t RESERVED_6[612]; __IO uint32_t PID[TRDC_MBC2_PID_COUNT]; /**< Process Identifier, array offset: 0x704, array step: 0x4, available only on: TRDC_AONMIX/TRDC1 (missing on TRDC_WAKEUPMIX/TRDC2) */ @@ -405,9 +408,9 @@ typedef struct { struct { /* offset: 0x10000, array step: 0x2000 */ __I uint32_t MBC_MEM_GLBCFG[TRDC_MBC2_MBC_INDEX_MBC_MEM_GLBCFG_COUNT]; /**< MBC Global Configuration Register, array offset: 0x10000, array step: index*0x2000, index2*0x4 */ __IO uint32_t MBC_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, array offset: 0x10010, array step: 0x2000 */ - __O uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x10014, array step: 0x2000 */ - __O uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x10018, array step: 0x2000 */ - __O uint32_t MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1001C, array step: 0x2000 */ + __IO uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x10014, array step: 0x2000 */ + __IO uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x10018, array step: 0x2000 */ + __IO uint32_t MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1001C, array step: 0x2000 */ __IO uint32_t MBC_MEMN_GLBAC[TRDC_MBC2_MBC_INDEX_MBC_MEMN_GLBAC_COUNT]; /**< MBC Global Access Control, array offset: 0x10020, array step: index*0x2000, index2*0x4 */ __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[TRDC_MBC2_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_COUNT]; /**< MBC Memory Block Configuration Word, array offset: 0x10040, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ uint8_t RESERVED_0[192]; @@ -670,9 +673,9 @@ typedef struct { __I uint32_t MRC_GLBCFG; /**< MRC Global Configuration Register, array offset: 0x14000, array step: 0x1000, irregular array, not all indices are valid */ uint8_t RESERVED_0[12]; __IO uint32_t MRC_NSE_RGN_INDIRECT; /**< MRC NonSecure Enable Region Indirect, array offset: 0x14010, array step: 0x1000, irregular array, not all indices are valid */ - __O uint32_t MRC_NSE_RGN_SET; /**< MRC NonSecure Enable Region Set, array offset: 0x14014, array step: 0x1000, irregular array, not all indices are valid */ - __O uint32_t MRC_NSE_RGN_CLR; /**< MRC NonSecure Enable Region Clear, array offset: 0x14018, array step: 0x1000, irregular array, not all indices are valid */ - __O uint32_t MRC_NSE_RGN_CLR_ALL; /**< MRC NonSecure Enable Region Clear All, array offset: 0x1401C, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t MRC_NSE_RGN_SET; /**< MRC NonSecure Enable Region Set, array offset: 0x14014, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t MRC_NSE_RGN_CLR; /**< MRC NonSecure Enable Region Clear, array offset: 0x14018, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t MRC_NSE_RGN_CLR_ALL; /**< MRC NonSecure Enable Region Clear All, array offset: 0x1401C, array step: 0x1000, irregular array, not all indices are valid */ __IO uint32_t MRC_GLBAC[TRDC_MBC2_MRC_INDEX_MRC_GLBAC_COUNT]; /**< MRC Global Access Control, array offset: 0x14020, array step: index*0x1000, index2*0x4, irregular array, not all indices are valid */ __IO uint32_t MRC_DOM0_RGD_W[TRDC_MBC2_MRC_INDEX_MRC_INDEX_DOM0_RGD_COUNT][TRDC_MBC2_MRC_INDEX_MRC_INDEX_DOM0_RGD_MRC_INDEX_DOM0_RGD_W_COUNT]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14040, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */ uint8_t RESERVED_1[64]; @@ -38282,5 +38285,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TRDC_MBC2_H_ */ +#endif /* PERI_TRDC_MBC2_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TRDC_MBC4.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TRDC_MBC4.h index 84db46c797..0a9aa6b103 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TRDC_MBC4.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TRDC_MBC4.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRDC_MBC4 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TRDC_MBC4.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_TRDC_MBC4.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TRDC_MBC4 * * CMSIS Peripheral Access Layer for TRDC_MBC4 */ -#if !defined(TRDC_MBC4_H_) -#define TRDC_MBC4_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TRDC_MBC4_H_) +#define PERI_TRDC_MBC4_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -377,14 +380,14 @@ typedef struct { __I uint32_t W0; /**< MBC Domain Error Word0 Register, array offset: 0x400, array step: 0x10 */ __I uint32_t W1; /**< MBC Domain Error Word1 Register, array offset: 0x404, array step: 0x10 */ uint8_t RESERVED_0[4]; - __O uint32_t W3; /**< MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10 */ + __IO uint32_t W3; /**< MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10 */ } MBC_DERR[TRDC_MBC4_MBC_DERR_COUNT]; uint8_t RESERVED_5[64]; struct { /* offset: 0x480, array step: 0x10 */ __I uint32_t W0; /**< MRC Domain Error Word0 Register, array offset: 0x480, array step: 0x10 */ __I uint32_t W1; /**< MRC Domain Error Word1 Register, array offset: 0x484, array step: 0x10 */ uint8_t RESERVED_0[4]; - __O uint32_t W3; /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10 */ + __IO uint32_t W3; /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10 */ } MRC_DERR[TRDC_MBC4_MRC_DERR_COUNT]; uint8_t RESERVED_6[880]; struct { /* offset: 0x800, array step: 0x20 */ @@ -402,9 +405,9 @@ typedef struct { struct { /* offset: 0x10000, array step: 0x2000 */ __I uint32_t MBC_MEM_GLBCFG[TRDC_MBC4_MBC_INDEX_MBC_MEM_GLBCFG_COUNT]; /**< MBC Global Configuration Register, array offset: 0x10000, array step: index*0x2000, index2*0x4 */ __IO uint32_t MBC_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, array offset: 0x10010, array step: 0x2000 */ - __O uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x10014, array step: 0x2000 */ - __O uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x10018, array step: 0x2000 */ - __O uint32_t MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1001C, array step: 0x2000 */ + __IO uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x10014, array step: 0x2000 */ + __IO uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x10018, array step: 0x2000 */ + __IO uint32_t MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1001C, array step: 0x2000 */ __IO uint32_t MBC_MEMN_GLBAC[TRDC_MBC4_MBC_INDEX_MBC_MEMN_GLBAC_COUNT]; /**< MBC Global Access Control, array offset: 0x10020, array step: index*0x2000, index2*0x4 */ __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[TRDC_MBC4_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_COUNT]; /**< MBC Memory Block Configuration Word, array offset: 0x10040, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0-1], [3][0-4] */ uint8_t RESERVED_0[228]; @@ -635,9 +638,9 @@ typedef struct { __I uint32_t MRC_GLBCFG; /**< MRC Global Configuration Register, array offset: 0x18000, array step: 0xFC4 */ uint8_t RESERVED_0[12]; __IO uint32_t MRC_NSE_RGN_INDIRECT; /**< MRC NonSecure Enable Region Indirect, array offset: 0x18010, array step: 0xFC4 */ - __O uint32_t MRC_NSE_RGN_SET; /**< MRC NonSecure Enable Region Set, array offset: 0x18014, array step: 0xFC4 */ - __O uint32_t MRC_NSE_RGN_CLR; /**< MRC NonSecure Enable Region Clear, array offset: 0x18018, array step: 0xFC4 */ - __O uint32_t MRC_NSE_RGN_CLR_ALL; /**< MRC NonSecure Enable Region Clear All, array offset: 0x1801C, array step: 0xFC4 */ + __IO uint32_t MRC_NSE_RGN_SET; /**< MRC NonSecure Enable Region Set, array offset: 0x18014, array step: 0xFC4 */ + __IO uint32_t MRC_NSE_RGN_CLR; /**< MRC NonSecure Enable Region Clear, array offset: 0x18018, array step: 0xFC4 */ + __IO uint32_t MRC_NSE_RGN_CLR_ALL; /**< MRC NonSecure Enable Region Clear All, array offset: 0x1801C, array step: 0xFC4 */ __IO uint32_t MRC_GLBAC[TRDC_MBC4_MRC_INDEX_MRC_GLBAC_COUNT]; /**< MRC Global Access Control, array offset: 0x18020, array step: index*0xFC4, index2*0x4 */ __IO uint32_t MRC_DOM0_RGD_W[TRDC_MBC4_MRC_INDEX_MRC_INDEX_DOM0_RGD_COUNT][TRDC_MBC4_MRC_INDEX_MRC_INDEX_DOM0_RGD_MRC_INDEX_DOM0_RGD_W_COUNT]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18040, array step: index*0xFC4, index2*0x8, index3*0x4 */ __IO uint32_t MRC_DOM0_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x180C0, array step: 0xFC4 */ @@ -39219,5 +39222,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TRDC_MBC4_H_ */ +#endif /* PERI_TRDC_MBC4_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TRGMUX.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TRGMUX.h index c4d1f69fba..62f3590e8f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TRGMUX.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TRGMUX.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRGMUX ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TRGMUX.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_TRGMUX.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TRGMUX * * CMSIS Peripheral Access Layer for TRGMUX */ -#if !defined(TRGMUX_H_) -#define TRGMUX_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TRGMUX_H_) +#define PERI_TRGMUX_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -249,5 +252,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TRGMUX_H_ */ +#endif /* PERI_TRGMUX_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TSTMR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TSTMR.h index 917f45dd17..a0a430eaf1 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TSTMR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_TSTMR.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for TSTMR ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TSTMR.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_TSTMR.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TSTMR * * CMSIS Peripheral Access Layer for TSTMR */ -#if !defined(TSTMR_H_) -#define TSTMR_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TSTMR_H_) +#define PERI_TSTMR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -249,5 +252,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TSTMR_H_ */ +#endif /* PERI_TSTMR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_USB.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_USB.h index 83c08df8d2..e12b1f2410 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_USB.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_USB.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for USB ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file USB.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_USB.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for USB * * CMSIS Peripheral Access Layer for USB */ -#if !defined(USB_H_) -#define USB_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_USB_H_) +#define PERI_USB_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -317,8 +320,8 @@ typedef struct { #define USB_HWHOST_HC_MASK (0x1U) #define USB_HWHOST_HC_SHIFT (0U) /*! HC - HC - * 0b1..Supported * 0b0..Not supported + * 0b1..Supported */ #define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) @@ -334,8 +337,8 @@ typedef struct { #define USB_HWDEVICE_DC_MASK (0x1U) #define USB_HWDEVICE_DC_SHIFT (0U) /*! DC - DC - * 0b1..Supported * 0b0..Not supported + * 0b1..Supported */ #define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) @@ -997,8 +1000,8 @@ typedef struct { #define USB_PORTSC1_OCA_MASK (0x10U) #define USB_PORTSC1_OCA_SHIFT (4U) /*! OCA - OCA - * 0b1..This port currently has an over-current condition * 0b0..This port does not have an over-current condition. + * 0b1..This port currently has an over-current condition */ #define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) @@ -1031,8 +1034,8 @@ typedef struct { #define USB_PORTSC1_LS_SHIFT (10U) /*! LS - LS * 0b00..SE0 - * 0b10..J-state * 0b01..K-state + * 0b10..J-state * 0b11..Undefined */ #define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) @@ -1090,16 +1093,16 @@ typedef struct { #define USB_PORTSC1_PHCD_MASK (0x800000U) #define USB_PORTSC1_PHCD_SHIFT (23U) /*! PHCD - PHCD - * 0b1..Disable PHY clock * 0b0..Enable PHY clock + * 0b1..Disable PHY clock */ #define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) #define USB_PORTSC1_PFSC_MASK (0x1000000U) #define USB_PORTSC1_PFSC_SHIFT (24U) /*! PFSC - PFSC - * 0b1..Forced to full speed * 0b0..Normal operation + * 0b1..Forced to full speed */ #define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) @@ -1887,5 +1890,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* USB_H_ */ +#endif /* PERI_USB_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_USBNC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_USBNC.h index bb0b2fca08..d8783a19e3 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_USBNC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_USBNC.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBNC ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file USBNC.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_USBNC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for USBNC * * CMSIS Peripheral Access Layer for USBNC */ -#if !defined(USBNC_H_) -#define USBNC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_USBNC_H_) +#define PERI_USBNC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -202,80 +205,80 @@ typedef struct { #define USBNC_CTRL1_OVER_CUR_DIS_MASK (0x80U) #define USBNC_CTRL1_OVER_CUR_DIS_SHIFT (7U) /*! OVER_CUR_DIS - OVER_CUR_DIS - * 0b1..Disables overcurrent detection * 0b0..Enables overcurrent detection + * 0b1..Disables overcurrent detection */ #define USBNC_CTRL1_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK) #define USBNC_CTRL1_OVER_CUR_POL_MASK (0x100U) #define USBNC_CTRL1_OVER_CUR_POL_SHIFT (8U) /*! OVER_CUR_POL - OVER_CUR_POL - * 0b1..Low active (low on this signal represents an overcurrent condition) * 0b0..High active (high on this signal represents an overcurrent condition) + * 0b1..Low active (low on this signal represents an overcurrent condition) */ #define USBNC_CTRL1_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK) #define USBNC_CTRL1_PWR_POL_MASK (0x200U) #define USBNC_CTRL1_PWR_POL_SHIFT (9U) /*! PWR_POL - PWR_POL - * 0b1..PMIC Power Pin is High active. * 0b0..PMIC Power Pin is Low active. + * 0b1..PMIC Power Pin is High active. */ #define USBNC_CTRL1_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK) #define USBNC_CTRL1_WIE_MASK (0x400U) #define USBNC_CTRL1_WIE_SHIFT (10U) /*! WIE - WIE - * 0b1..Interrupt Enabled * 0b0..Interrupt Disabled + * 0b1..Interrupt Enabled */ #define USBNC_CTRL1_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK) #define USBNC_CTRL1_WKUP_SW_EN_MASK (0x4000U) #define USBNC_CTRL1_WKUP_SW_EN_SHIFT (14U) /*! WKUP_SW_EN - WKUP_SW_EN - * 0b1..Enable * 0b0..Disable + * 0b1..Enable */ #define USBNC_CTRL1_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK) #define USBNC_CTRL1_WKUP_SW_MASK (0x8000U) #define USBNC_CTRL1_WKUP_SW_SHIFT (15U) /*! WKUP_SW - WKUP_SW - * 0b1..Force wake-up * 0b0..Inactive + * 0b1..Force wake-up */ #define USBNC_CTRL1_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK) #define USBNC_CTRL1_WKUP_ID_EN_MASK (0x10000U) #define USBNC_CTRL1_WKUP_ID_EN_SHIFT (16U) /*! WKUP_ID_EN - WKUP_ID_EN - * 0b1..Enable * 0b0..Disable + * 0b1..Enable */ #define USBNC_CTRL1_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK) #define USBNC_CTRL1_WKUP_VBUS_EN_MASK (0x20000U) #define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT (17U) /*! WKUP_VBUS_EN - WKUP_VBUS_EN - * 0b1..Enable * 0b0..Disable + * 0b1..Enable */ #define USBNC_CTRL1_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK) #define USBNC_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U) #define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT (29U) /*! WKUP_DPDM_EN - Wake-up on DP/DM change enable - * 0b1..(Default) DP/DM changes wake-up to be enabled, it is for device only. * 0b0..DP/DM changes wake-up to be disabled only when VBUS is 0. + * 0b1..(Default) DP/DM changes wake-up to be enabled, it is for device only. */ #define USBNC_CTRL1_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK) #define USBNC_CTRL1_WIR_MASK (0x80000000U) #define USBNC_CTRL1_WIR_SHIFT (31U) /*! WIR - WIR - * 0b1..Wake-up Interrupt Request received * 0b0..No wake-up interrupt request received + * 0b1..Wake-up Interrupt Request received */ #define USBNC_CTRL1_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK) /*! @} */ @@ -491,5 +494,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* USBNC_H_ */ +#endif /* PERI_USBNC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_USDHC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_USDHC.h index ed897e1356..896b12b8e7 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_USDHC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_USDHC.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for USDHC ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file USDHC.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_USDHC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for USDHC * * CMSIS Peripheral Access Layer for USDHC */ -#if !defined(USDHC_H_) -#define USDHC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_USDHC_H_) +#define PERI_USDHC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -201,7 +204,7 @@ typedef struct { __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ uint8_t RESERVED_0[4]; - __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ + __IO uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status, offset: 0x54 */ __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ uint8_t RESERVED_1[4]; @@ -267,25 +270,25 @@ typedef struct { #define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) #define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) /*! BLKSIZE - Transfer block size - * 0b1000000000000..4096 bytes - * 0b0100000000000..2048 bytes - * 0b0001000000000..512 bytes - * 0b0000111111111..511 bytes - * 0b0000000000100..4 bytes - * 0b0000000000011..3 bytes - * 0b0000000000010..2 bytes - * 0b0000000000001..1 byte * 0b0000000000000..No data transfer + * 0b0000000000001..1 byte + * 0b0000000000010..2 bytes + * 0b0000000000011..3 bytes + * 0b0000000000100..4 bytes + * 0b0000111111111..511 bytes + * 0b0001000000000..512 bytes + * 0b0100000000000..2048 bytes + * 0b1000000000000..4096 bytes */ #define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) #define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) #define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) /*! BLKCNT - Blocks count for current transfer - * 0b1111111111111111..65535 blocks - * 0b0000000000000010..2 blocks - * 0b0000000000000001..1 block * 0b0000000000000000..Stop count + * 0b0000000000000001..1 block + * 0b0000000000000010..2 blocks + * 0b1111111111111111..65535 blocks */ #define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) /*! @} */ @@ -379,34 +382,34 @@ typedef struct { #define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) /*! CCCEN - Command CRC check enable - * 0b1..Enables command CRC check * 0b0..Disables command CRC check + * 0b1..Enables command CRC check */ #define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) #define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) #define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) /*! CICEN - Command index check enable - * 0b1..Enables command index check * 0b0..Disable command index check + * 0b1..Enables command index check */ #define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) #define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) /*! DPSEL - Data present select - * 0b1..Data present * 0b0..No data present + * 0b1..Data present */ #define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) #define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) /*! CMDTYP - Command type - * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR - * 0b10..Resume CMD52 for writing function select in CCCR - * 0b01..Suspend CMD52 for writing bus suspend in CCCR * 0b00..Normal other commands + * 0b01..Suspend CMD52 for writing bus suspend in CCCR + * 0b10..Resume CMD52 for writing function select in CCCR + * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR */ #define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) @@ -467,104 +470,104 @@ typedef struct { #define USDHC_PRES_STATE_CIHB_MASK (0x1U) #define USDHC_PRES_STATE_CIHB_SHIFT (0U) /*! CIHB - Command inhibit (CMD) - * 0b1..Cannot issue command * 0b0..Can issue command using only CMD line + * 0b1..Cannot issue command */ #define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) #define USDHC_PRES_STATE_CDIHB_MASK (0x2U) #define USDHC_PRES_STATE_CDIHB_SHIFT (1U) /*! CDIHB - Command Inhibit Data (DATA) - * 0b1..Cannot issue command that uses the DATA line * 0b0..Can issue command that uses the DATA line + * 0b1..Cannot issue command that uses the DATA line */ #define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) #define USDHC_PRES_STATE_DLA_MASK (0x4U) #define USDHC_PRES_STATE_DLA_SHIFT (2U) /*! DLA - Data line active - * 0b1..DATA line active * 0b0..DATA line inactive + * 0b1..DATA line active */ #define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) #define USDHC_PRES_STATE_SDSTB_MASK (0x8U) #define USDHC_PRES_STATE_SDSTB_SHIFT (3U) /*! SDSTB - SD clock stable - * 0b1..Clock is stable. * 0b0..Clock is changing frequency and not stable. + * 0b1..Clock is stable. */ #define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) #define USDHC_PRES_STATE_WTA_MASK (0x100U) #define USDHC_PRES_STATE_WTA_SHIFT (8U) /*! WTA - Write transfer active - * 0b1..Transferring data * 0b0..No valid data + * 0b1..Transferring data */ #define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) #define USDHC_PRES_STATE_RTA_MASK (0x200U) #define USDHC_PRES_STATE_RTA_SHIFT (9U) /*! RTA - Read transfer active - * 0b1..Transferring data * 0b0..No valid data + * 0b1..Transferring data */ #define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) #define USDHC_PRES_STATE_BWEN_MASK (0x400U) #define USDHC_PRES_STATE_BWEN_SHIFT (10U) /*! BWEN - Buffer write enable - * 0b1..Write enable * 0b0..Write disable + * 0b1..Write enable */ #define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) #define USDHC_PRES_STATE_BREN_MASK (0x800U) #define USDHC_PRES_STATE_BREN_SHIFT (11U) /*! BREN - Buffer read enable - * 0b1..Read enable * 0b0..Read disable + * 0b1..Read enable */ #define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) #define USDHC_PRES_STATE_RTR_MASK (0x1000U) #define USDHC_PRES_STATE_RTR_SHIFT (12U) /*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode, and eMMC HS200 mode) - * 0b1..Sampling clock needs re-tuning * 0b0..Fixed or well tuned sampling clock + * 0b1..Sampling clock needs re-tuning */ #define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) #define USDHC_PRES_STATE_TSCD_MASK (0x8000U) #define USDHC_PRES_STATE_TSCD_SHIFT (15U) /*! TSCD - Tap select change done - * 0b1..Delay cell select change is finished. * 0b0..Delay cell select change is not finished. + * 0b1..Delay cell select change is finished. */ #define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) #define USDHC_PRES_STATE_CINST_MASK (0x10000U) #define USDHC_PRES_STATE_CINST_SHIFT (16U) /*! CINST - Card inserted - * 0b1..Card inserted * 0b0..Power on reset or no card + * 0b1..Card inserted */ #define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) #define USDHC_PRES_STATE_CDPL_MASK (0x40000U) #define USDHC_PRES_STATE_CDPL_SHIFT (18U) /*! CDPL - Card detect pin level - * 0b1..Card present (CD_B = 0) * 0b0..No card present (CD_B = 1) + * 0b1..Card present (CD_B = 0) */ #define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) #define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) #define USDHC_PRES_STATE_WPSPL_SHIFT (19U) /*! WPSPL - Write protect switch pin level - * 0b1..Write enabled (WP = 0) * 0b0..Write protected (WP = 1) + * 0b1..Write enabled (WP = 0) */ #define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) @@ -576,14 +579,14 @@ typedef struct { #define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) #define USDHC_PRES_STATE_DLSL_SHIFT (24U) /*! DLSL - DATA[7:0] line signal level - * 0b00000111..Data 7 line signal level - * 0b00000110..Data 6 line signal level - * 0b00000101..Data 5 line signal level - * 0b00000100..Data 4 line signal level - * 0b00000011..Data 3 line signal level - * 0b00000010..Data 2 line signal level - * 0b00000001..Data 1 line signal level * 0b00000000..Data 0 line signal level + * 0b00000001..Data 1 line signal level + * 0b00000010..Data 2 line signal level + * 0b00000011..Data 3 line signal level + * 0b00000100..Data 4 line signal level + * 0b00000101..Data 5 line signal level + * 0b00000110..Data 6 line signal level + * 0b00000111..Data 7 line signal level */ #define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) /*! @} */ @@ -594,9 +597,9 @@ typedef struct { #define USDHC_PROT_CTRL_DTW_MASK (0x6U) #define USDHC_PROT_CTRL_DTW_SHIFT (1U) /*! DTW - Data transfer width - * 0b10..8-bit mode - * 0b01..4-bit mode * 0b00..1-bit mode + * 0b01..4-bit mode + * 0b10..8-bit mode * 0b11..Reserved */ #define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) @@ -604,8 +607,8 @@ typedef struct { #define USDHC_PROT_CTRL_D3CD_MASK (0x8U) #define USDHC_PROT_CTRL_D3CD_SHIFT (3U) /*! D3CD - DATA3 as card detection pin - * 0b1..DATA3 as card detection pin * 0b0..DATA3 does not monitor card insertion + * 0b1..DATA3 as card detection pin */ #define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) @@ -622,16 +625,16 @@ typedef struct { #define USDHC_PROT_CTRL_CDTL_MASK (0x40U) #define USDHC_PROT_CTRL_CDTL_SHIFT (6U) /*! CDTL - Card detect test level - * 0b1..Card detect test level is 1, card inserted * 0b0..Card detect test level is 0, no card inserted + * 0b1..Card detect test level is 1, card inserted */ #define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) #define USDHC_PROT_CTRL_CDSS_MASK (0x80U) #define USDHC_PROT_CTRL_CDSS_SHIFT (7U) /*! CDSS - Card detect signal selection - * 0b1..Card detection test level is selected (for test purpose). * 0b0..Card detection level is selected (for normal purpose). + * 0b1..Card detection test level is selected (for test purpose). */ #define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) @@ -648,32 +651,32 @@ typedef struct { #define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) #define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) /*! SABGREQ - Stop at block gap request - * 0b1..Stop * 0b0..Transfer + * 0b1..Stop */ #define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) #define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) #define USDHC_PROT_CTRL_CREQ_SHIFT (17U) /*! CREQ - Continue request - * 0b1..Restart * 0b0..No effect + * 0b1..Restart */ #define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) #define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) #define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) /*! RWCTL - Read wait control - * 0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set * 0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set + * 0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set */ #define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) #define USDHC_PROT_CTRL_IABG_MASK (0x80000U) #define USDHC_PROT_CTRL_IABG_SHIFT (19U) /*! IABG - Interrupt at block gap - * 0b1..Enables interrupt at block gap * 0b0..Disables interrupt at block gap + * 0b1..Enables interrupt at block gap */ #define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) @@ -685,32 +688,32 @@ typedef struct { #define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) #define USDHC_PROT_CTRL_WECINT_SHIFT (24U) /*! WECINT - Wakeup event enable on card interrupt - * 0b1..Enables wakeup event enable on card interrupt * 0b0..Disables wakeup event enable on card interrupt + * 0b1..Enables wakeup event enable on card interrupt */ #define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) #define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) #define USDHC_PROT_CTRL_WECINS_SHIFT (25U) /*! WECINS - Wakeup event enable on SD card insertion - * 0b1..Enable wakeup event enable on SD card insertion * 0b0..Disable wakeup event enable on SD card insertion + * 0b1..Enable wakeup event enable on SD card insertion */ #define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) #define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) #define USDHC_PROT_CTRL_WECRM_SHIFT (26U) /*! WECRM - Wakeup event enable on SD card removal - * 0b1..Enables wakeup event enable on SD card removal * 0b0..Disables wakeup event enable on SD card removal + * 0b1..Enables wakeup event enable on SD card removal */ #define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) /*! NON_EXACT_BLK_RD - Non-exact block read - * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. * 0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read. + * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. */ #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) /*! @} */ @@ -736,13 +739,13 @@ typedef struct { #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) /*! DTOCV - Data timeout counter value - * 0b1111..SDCLK x 2 31, recommend to use for HS400 mode - * 0b1110..SDCLK x 2 30, recommend to use for HS200 and SDR104 mode - * 0b1101..SDCLK x 2 29, recommend to use for supported speed modes except HS200, HS400, SDR104 mode - * 0b0011..SDCLK x 2 19 - * 0b0010..SDCLK x 2 18 - * 0b0001..SDCLK x 2 33 * 0b0000..SDCLK x 2 32 + * 0b0001..SDCLK x 2 33 + * 0b0010..SDCLK x 2 18 + * 0b0011..SDCLK x 2 19 + * 0b1101..SDCLK x 2 29, recommend to use for supported speed modes except HS200, HS400, SDR104 mode + * 0b1110..SDCLK x 2 30, recommend to use for HS200 and SDR104 mode + * 0b1111..SDCLK x 2 31, recommend to use for HS400 mode */ #define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) @@ -754,24 +757,24 @@ typedef struct { #define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) #define USDHC_SYS_CTRL_RSTA_SHIFT (24U) /*! RSTA - Software reset for all - * 0b1..Reset * 0b0..No reset + * 0b1..Reset */ #define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) #define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) #define USDHC_SYS_CTRL_RSTC_SHIFT (25U) /*! RSTC - Software reset for CMD line - * 0b1..Reset * 0b0..No reset + * 0b1..Reset */ #define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) #define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) #define USDHC_SYS_CTRL_RSTD_SHIFT (26U) /*! RSTD - Software reset for data line - * 0b1..Reset * 0b0..No reset + * 0b1..Reset */ #define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) @@ -792,80 +795,80 @@ typedef struct { #define USDHC_INT_STATUS_CC_MASK (0x1U) #define USDHC_INT_STATUS_CC_SHIFT (0U) /*! CC - Command complete - * 0b1..Command complete * 0b0..Command not complete + * 0b1..Command complete */ #define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) #define USDHC_INT_STATUS_TC_MASK (0x2U) #define USDHC_INT_STATUS_TC_SHIFT (1U) /*! TC - Transfer complete - * 0b1..Transfer complete * 0b0..Transfer does not complete + * 0b1..Transfer complete */ #define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) #define USDHC_INT_STATUS_BGE_MASK (0x4U) #define USDHC_INT_STATUS_BGE_SHIFT (2U) /*! BGE - Block gap event - * 0b1..Transaction stopped at block gap * 0b0..No block gap event + * 0b1..Transaction stopped at block gap */ #define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) #define USDHC_INT_STATUS_DINT_MASK (0x8U) #define USDHC_INT_STATUS_DINT_SHIFT (3U) /*! DINT - DMA interrupt - * 0b1..DMA interrupt is generated. * 0b0..No DMA interrupt + * 0b1..DMA interrupt is generated. */ #define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) #define USDHC_INT_STATUS_BWR_MASK (0x10U) #define USDHC_INT_STATUS_BWR_SHIFT (4U) /*! BWR - Buffer write ready - * 0b1..Ready to write buffer * 0b0..Not ready to write buffer + * 0b1..Ready to write buffer */ #define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) #define USDHC_INT_STATUS_BRR_MASK (0x20U) #define USDHC_INT_STATUS_BRR_SHIFT (5U) /*! BRR - Buffer read ready - * 0b1..Ready to read buffer * 0b0..Not ready to read buffer + * 0b1..Ready to read buffer */ #define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) #define USDHC_INT_STATUS_CINS_MASK (0x40U) #define USDHC_INT_STATUS_CINS_SHIFT (6U) /*! CINS - Card insertion - * 0b1..Card inserted * 0b0..Card state unstable or removed + * 0b1..Card inserted */ #define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) #define USDHC_INT_STATUS_CRM_MASK (0x80U) #define USDHC_INT_STATUS_CRM_SHIFT (7U) /*! CRM - Card removal - * 0b1..Card removed * 0b0..Card state unstable or inserted + * 0b1..Card removed */ #define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) #define USDHC_INT_STATUS_CINT_MASK (0x100U) #define USDHC_INT_STATUS_CINT_SHIFT (8U) /*! CINT - Card interrupt - * 0b1..Generate card interrupt * 0b0..No card interrupt + * 0b1..Generate card interrupt */ #define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) #define USDHC_INT_STATUS_RTE_MASK (0x1000U) #define USDHC_INT_STATUS_RTE_SHIFT (12U) /*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and eMMC HS200 mode) - * 0b1..Re-tuning should be performed. * 0b0..Re-tuning is not required. + * 0b1..Re-tuning should be performed. */ #define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) @@ -887,64 +890,64 @@ typedef struct { #define USDHC_INT_STATUS_CTOE_MASK (0x10000U) #define USDHC_INT_STATUS_CTOE_SHIFT (16U) /*! CTOE - Command timeout error - * 0b1..Time out * 0b0..No error + * 0b1..Time out */ #define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) #define USDHC_INT_STATUS_CCE_MASK (0x20000U) #define USDHC_INT_STATUS_CCE_SHIFT (17U) /*! CCE - Command CRC error - * 0b1..CRC error generated * 0b0..No error + * 0b1..CRC error generated */ #define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) #define USDHC_INT_STATUS_CEBE_MASK (0x40000U) #define USDHC_INT_STATUS_CEBE_SHIFT (18U) /*! CEBE - Command end bit error - * 0b1..End bit error generated * 0b0..No error + * 0b1..End bit error generated */ #define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) #define USDHC_INT_STATUS_CIE_MASK (0x80000U) #define USDHC_INT_STATUS_CIE_SHIFT (19U) /*! CIE - Command index error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) #define USDHC_INT_STATUS_DTOE_MASK (0x100000U) #define USDHC_INT_STATUS_DTOE_SHIFT (20U) /*! DTOE - Data timeout error - * 0b1..Time out * 0b0..No error + * 0b1..Time out */ #define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) #define USDHC_INT_STATUS_DCE_MASK (0x200000U) #define USDHC_INT_STATUS_DCE_SHIFT (21U) /*! DCE - Data CRC error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) #define USDHC_INT_STATUS_DEBE_MASK (0x400000U) #define USDHC_INT_STATUS_DEBE_SHIFT (22U) /*! DEBE - Data end bit error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) #define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) #define USDHC_INT_STATUS_AC12E_SHIFT (24U) /*! AC12E - Auto CMD12 error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) @@ -956,8 +959,8 @@ typedef struct { #define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) #define USDHC_INT_STATUS_DMAE_SHIFT (28U) /*! DMAE - DMA error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) /*! @} */ @@ -968,176 +971,176 @@ typedef struct { #define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) #define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) /*! CCSEN - Command complete status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) #define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) #define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) /*! TCSEN - Transfer complete status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) #define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) #define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) /*! BGESEN - Block gap event status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) #define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) /*! DINTSEN - DMA interrupt status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) #define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) /*! BWRSEN - Buffer write ready status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) #define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) /*! BRRSEN - Buffer read ready status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) #define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) /*! CINSSEN - Card insertion status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) #define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) /*! CRMSEN - Card removal status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) #define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) /*! CINTSEN - Card interrupt status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) #define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) #define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) /*! RTESEN - Re-tuning event status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) #define USDHC_INT_STATUS_EN_TPSEN_MASK (0x2000U) #define USDHC_INT_STATUS_EN_TPSEN_SHIFT (13U) /*! TPSEN - Tuning pass status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) #define USDHC_INT_STATUS_EN_CQISEN_MASK (0x4000U) #define USDHC_INT_STATUS_EN_CQISEN_SHIFT (14U) /*! CQISEN - Command queuing status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_CQISEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CQISEN_SHIFT)) & USDHC_INT_STATUS_EN_CQISEN_MASK) #define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) /*! CTOESEN - Command timeout error status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) #define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) #define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) /*! CCESEN - Command CRC error status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) #define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) /*! CEBESEN - Command end bit error status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) #define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) #define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) /*! CIESEN - Command index error status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) #define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) /*! DTOESEN - Data timeout error status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) #define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) #define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) /*! DCESEN - Data CRC error status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) #define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) /*! DEBESEN - Data end bit error status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) #define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) /*! AC12ESEN - Auto CMD12 error status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) #define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) #define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) /*! TNESEN - Tuning error status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) #define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) /*! DMAESEN - DMA error status enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) /*! @} */ @@ -1148,176 +1151,176 @@ typedef struct { #define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) /*! CCIEN - Command complete interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) #define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) /*! TCIEN - Transfer complete interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) /*! BGEIEN - Block gap event interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) /*! DINTIEN - DMA interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) /*! BWRIEN - Buffer write ready interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) /*! BRRIEN - Buffer read ready interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) /*! CINSIEN - Card insertion interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) /*! CRMIEN - Card removal interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) /*! CINTIEN - Card interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) /*! RTEIEN - Re-tuning event interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) #define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x2000U) #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (13U) /*! TPIEN - Tuning pass interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) #define USDHC_INT_SIGNAL_EN_CQIIEN_MASK (0x4000U) #define USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT (14U) /*! CQIIEN - Command queuing signal enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_CQIIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CQIIEN_MASK) #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) /*! CTOEIEN - Command timeout error interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) /*! CCEIEN - Command CRC error interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) /*! CEBEIEN - Command end bit error interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) /*! CIEIEN - Command index error interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) /*! DTOEIEN - Data timeout error interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) /*! DCEIEN - Data CRC error interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) /*! DEBEIEN - Data end bit error interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) /*! AC12EIEN - Auto CMD12 error interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) /*! TNEIEN - Tuning error interrupt enable - * 0b1..Enabled * 0b0..Masked + * 0b1..Enabled */ #define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) /*! DMAEIEN - DMA error interrupt enable - * 0b1..Enable * 0b0..Masked + * 0b1..Enable */ #define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) /*! @} */ @@ -1328,64 +1331,64 @@ typedef struct { #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) /*! AC12NE - Auto CMD12 not executed - * 0b1..Not executed * 0b0..Executed + * 0b1..Not executed */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) /*! AC12TOE - Auto CMD12 / 23 timeout error - * 0b1..Time out * 0b0..No error + * 0b1..Time out */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x4U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (2U) /*! AC12CE - Auto CMD12 / 23 CRC error - * 0b1..CRC error met in Auto CMD12/23 response * 0b0..No CRC error + * 0b1..CRC error met in Auto CMD12/23 response */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x8U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (3U) /*! AC12EBE - Auto CMD12 / 23 end bit error - * 0b1..End bit error generated * 0b0..No error + * 0b1..End bit error generated */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) /*! AC12IE - Auto CMD12 / 23 index error - * 0b1..Error, the CMD index in response is not CMD12/23 * 0b0..No error + * 0b1..Error, the CMD index in response is not CMD12/23 */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) /*! CNIBAC12E - Command not issued by Auto CMD12 error - * 0b1..Not issued * 0b0..No error + * 0b1..Not issued */ #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) /*! EXECUTE_TUNING - Execute tuning - * 0b1..Start tuning procedure * 0b0..Tuning procedure is aborted + * 0b1..Start tuning procedure */ #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) /*! SMP_CLK_SEL - Sample clock select - * 0b1..Tuned clock is used to sample data * 0b0..Fixed clock is used to sample data + * 0b1..Tuned clock is used to sample data */ #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) /*! @} */ @@ -1411,8 +1414,8 @@ typedef struct { #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) /*! USE_TUNING_SDR50 - Use Tuning for SDR50 - * 0b1..SDR50 supports tuning * 0b0..SDR50 does not support tuning + * 0b1..SDR50 supports tuning */ #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) @@ -1429,56 +1432,56 @@ typedef struct { #define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) /*! ADMAS - ADMA support - * 0b1..Advanced DMA supported * 0b0..Advanced DMA not supported + * 0b1..Advanced DMA supported */ #define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) #define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) #define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) /*! HSS - High speed support - * 0b1..High speed supported * 0b0..High speed not supported + * 0b1..High speed supported */ #define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) #define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) /*! DMAS - DMA support - * 0b1..DMA supported * 0b0..DMA not supported + * 0b1..DMA supported */ #define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) #define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) #define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) /*! SRS - Suspend / resume support - * 0b1..Supported * 0b0..Not supported + * 0b1..Supported */ #define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) #define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) #define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) /*! VS33 - Voltage support 3.3 V - * 0b1..3.3 V supported * 0b0..3.3 V not supported + * 0b1..3.3 V supported */ #define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) #define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) #define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) /*! VS30 - Voltage support 3.0 V - * 0b1..3.0 V supported * 0b0..3.0 V not supported + * 0b1..3.0 V supported */ #define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) #define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) #define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) /*! VS18 - Voltage support 1.8 V - * 0b1..1.8 V supported * 0b0..1.8 V not supported + * 0b1..1.8 V supported */ #define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) /*! @} */ @@ -1503,24 +1506,24 @@ typedef struct { #define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) #define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) /*! DMAEN - DMA enable - * 0b1..Enable * 0b0..Disable + * 0b1..Enable */ #define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) #define USDHC_MIX_CTRL_BCEN_MASK (0x2U) #define USDHC_MIX_CTRL_BCEN_SHIFT (1U) /*! BCEN - Block count enable - * 0b1..Enable * 0b0..Disable + * 0b1..Enable */ #define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) #define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) #define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) /*! AC12EN - Auto CMD12 enable - * 0b1..Enable * 0b0..Disable + * 0b1..Enable */ #define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) @@ -1532,16 +1535,16 @@ typedef struct { #define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) #define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) /*! DTDSEL - Data transfer direction select - * 0b1..Read (Card to host) * 0b0..Write (Host to card) + * 0b1..Read (Card to host) */ #define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) #define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) #define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) /*! MSBSEL - Multi / Single block select - * 0b1..Multiple blocks * 0b0..Single block + * 0b1..Multiple blocks */ #define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) @@ -1558,32 +1561,32 @@ typedef struct { #define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) /*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and eMMC HS200 mode) - * 0b1..Execute tuning * 0b0..Not tuned or tuning completed + * 0b1..Execute tuning */ #define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) /*! SMP_CLK_SEL - Clock selection - * 0b1..Tuned clock is used to sample data / cmd * 0b0..Fixed clock is used to sample data / cmd + * 0b1..Tuned clock is used to sample data / cmd */ #define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) /*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and eMMC HS200 mode) - * 0b1..Enable auto tuning * 0b0..Disable auto tuning + * 0b1..Enable auto tuning */ #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) #define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) /*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and eMMC HS200 mode) - * 0b1..Feedback clock comes from the ipp_card_clk_out * 0b0..Feedback clock comes from the loopback CLK + * 0b1..Feedback clock comes from the ipp_card_clk_out */ #define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) @@ -1698,16 +1701,16 @@ typedef struct { #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) /*! ADMALME - ADMA length mismatch error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) /*! ADMADCE - ADMA descriptor error - * 0b1..Error * 0b0..No error + * 0b1..Error */ #define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) /*! @} */ @@ -1922,8 +1925,8 @@ typedef struct { #define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) #define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) /*! VSELECT - Voltage selection - * 0b1..Change the voltage to low voltage range , around 1.8 V * 0b0..Change the voltage to high voltage range, around 3.0 V + * 0b1..Change the voltage to low voltage range , around 1.8 V */ #define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) @@ -2064,8 +2067,8 @@ typedef struct { #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) /*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 - * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled. * 0b0..Disable + * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled. */ #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) @@ -2512,5 +2515,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* USDHC_H_ */ +#endif /* PERI_USDHC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_WAKEUP_AHBRM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_WAKEUP_AHBRM.h index 885fd5fd48..ef69af9b0d 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_WAKEUP_AHBRM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_WAKEUP_AHBRM.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for WAKEUP_AHBRM ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file WAKEUP_AHBRM.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_WAKEUP_AHBRM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for WAKEUP_AHBRM * * CMSIS Peripheral Access Layer for WAKEUP_AHBRM */ -#if !defined(WAKEUP_AHBRM_H_) -#define WAKEUP_AHBRM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_WAKEUP_AHBRM_H_) +#define PERI_WAKEUP_AHBRM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -251,5 +254,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* WAKEUP_AHBRM_H_ */ +#endif /* PERI_WAKEUP_AHBRM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_WDOG.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_WDOG.h index 1f471dd8f1..c6a0bdef61 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_WDOG.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_WDOG.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for WDOG ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file WDOG.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_WDOG.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for WDOG * * CMSIS Peripheral Access Layer for WDOG */ -#if !defined(WDOG_H_) -#define WDOG_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_WDOG_H_) +#define PERI_WDOG_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -390,5 +393,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* WDOG_H_ */ +#endif /* PERI_WDOG_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_XCACHE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_XCACHE.h index 98b8330683..34826e9300 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_XCACHE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_XCACHE.h @@ -65,14 +65,14 @@ ** MIMX9352XVVXM_ca55 ** MIMX9352XVVXM_cm33 ** -** Version: rev. 1.0, 2021-11-16 -** Build: b240711 +** Version: rev. 2.0, 2024-10-29 +** Build: b250521 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCACHE ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -81,21 +81,24 @@ ** Revisions: ** - rev. 1.0 (2021-11-16) ** Initial version. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file XCACHE.h - * @version 1.0 - * @date 2021-11-16 + * @file PERI_XCACHE.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for XCACHE * * CMSIS Peripheral Access Layer for XCACHE */ -#if !defined(XCACHE_H_) -#define XCACHE_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_XCACHE_H_) +#define PERI_XCACHE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX9301CVVXD_ca55) || defined(CPU_MIMX9301DVVXD_ca55)) #include "MIMX9301_ca55_COMMON.h" @@ -398,5 +401,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* XCACHE_H_ */ +#endif /* PERI_XCACHE_H_ */ From 6b1cfed01d8dced3201a81bd954827223e984b8f Mon Sep 17 00:00:00 2001 From: Qiang Zhao Date: Fri, 4 Jul 2025 14:21:32 +0530 Subject: [PATCH 2/2] mcux-sdk-ng: sar_adc: update sar_adc driver Update sar_adc driver Signed-off-by: Qiang Zhao --- .../mcux-sdk-ng/drivers/sar_adc/fsl_sar_adc.c | 243 +++++++++++++++-- .../mcux-sdk-ng/drivers/sar_adc/fsl_sar_adc.h | 258 ++++++++++++++++-- 2 files changed, 457 insertions(+), 44 deletions(-) diff --git a/mcux/mcux-sdk-ng/drivers/sar_adc/fsl_sar_adc.c b/mcux/mcux-sdk-ng/drivers/sar_adc/fsl_sar_adc.c index 81e77885c1..9c9eb2c4cd 100644 --- a/mcux/mcux-sdk-ng/drivers/sar_adc/fsl_sar_adc.c +++ b/mcux/mcux-sdk-ng/drivers/sar_adc/fsl_sar_adc.c @@ -1,6 +1,5 @@ /* - * Copyright 2023-2024 NXP - * All rights reserved. + * Copyright 2023-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -30,6 +29,8 @@ static ADC_Type *s_adcBases[] = ADC_BASE_PTRS; static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS; #endif /* !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) */ +static adc_clock_frequency_t adcClockFreq; + /******************************************************************************* * Code ******************************************************************************/ @@ -73,17 +74,46 @@ void ADC_GetDefaultConfig(adc_config_t *config) /* Initializes the configure structure to zero. */ (void)memset(config, 0, sizeof(*config)); - config->enableAutoClockOff = false; - config->enableOverWrite = true; - config->enableConvertPresampleVal = false; - config->clockFrequency = kADC_FullBusFrequency; - config->convDataAlign = kADC_ConvDataRightAlign; - config->dmaRequestClearSrc = kADC_DMARequestClearByAck; + config->enableAutoClockOff = false; + config->enableOverWrite = true; + config->enableConvertPresampleVal = false; +#if defined(FSL_FEATURE_ADC_HAS_MCR_XSTARTEN) && (FSL_FEATURE_ADC_HAS_MCR_XSTARTEN==1U) + config->enableAuxiliaryTrig = false; +#endif /* FSL_FEATURE_ADC_HAS_MCR_XSTARTEN */ + +#if defined(FSL_FEATURE_ADC_HAS_AMSIO) && (FSL_FEATURE_ADC_HAS_AMSIO==1U) + config->speedMode = kADC_SpeedModeNormal; +#endif /* FSL_FEATURE_ADC_HAS_AMSIO */ +#if defined(FSL_FEATURE_ADC_HAS_DSDR) && (FSL_FEATURE_ADC_HAS_DSDR==1U) + config->convDelay = 0x00U; +#endif /* FSL_FEATURE_ADC_HAS_DSDR */ +#if defined(FSL_FEATURE_ADC_HAS_BCTUMODE) && (FSL_FEATURE_ADC_HAS_BCTUMODE==1U) + config->bctuMode = kADC_BctuModeDisable; +#endif /* FSL_FEATURE_ADC_HAS_BCTUMODE */ +#if (defined(FSL_FEATURE_ADC_HAS_CALBISTREG) && (FSL_FEATURE_ADC_HAS_CALBISTREG==1U)) + config->convRes = kADC_ConvRes14Bit; +#endif /* FSL_FEATURE_ADC_HAS_CALBISTREG */ +#if defined(FSL_FEATURE_ADC_HAS_MCR_AVGS) && (FSL_FEATURE_ADC_HAS_MCR_AVGS==1U) + config->convAvg = kADC_ConvAvgDisable; +#endif /* FSL_FEATURE_ADC_HAS_MCR_AVGS */ + config->extTrig = kADC_ExtTrigDisable; +#if !(defined(FSL_FEATURE_ADC_HAS_MCR_ADCLKSE) && (FSL_FEATURE_ADC_HAS_MCR_ADCLKSE==0U)) + config->clockFrequency = kADC_FullBusFrequency; +#endif /* FSL_FEATURE_ADC_HAS_MCR_ADCLKSE */ +#if (defined(FSL_FEATURE_ADC_HAS_MCR_ADCLKSEL) && (FSL_FEATURE_ADC_HAS_MCR_ADCLKSEL==1U)) + config->clockFrequency = kADC_ModuleClockFreq; +#endif /* FSL_FEATURE_ADC_HAS_MCR_ADCLKSEL */ + config->convDataAlign = kADC_ConvDataRightAlign; + config->dmaRequestClearSrc = kADC_DMARequestClearByAck; for (uint8_t index = 0U; index < (uint8_t)ADC_GROUP_COUNTS; ++index) { config->samplePhaseDuration[index] = 0x14U; +#if(ADC_GROUP_COUNTS==2U) config->presampleVoltageSrc[index] = kADC_PresampleVoltageSrcDVDD; +#else /* ADC_GROUP_COUNTS==3U */ + config->presampleVoltageSrc[index] = kADC_PresampleVoltageSrcVREL; +#endif /* ADC_GROUP_COUNTS */ } } @@ -102,26 +132,79 @@ void ADC_Init(ADC_Type *base, const adc_config_t *config) CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]); #endif /* !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) */ - /* 1. Set auto-clock-off, overwrite and conversion data align. */ - base->MCR = ((base->MCR & (~(ADC_MCR_ACKO_MASK | ADC_MCR_OWREN_MASK | ADC_MCR_WLSIDE_MASK))) | - (ADC_MCR_ACKO(config->enableAutoClockOff ? 1U : 0U) | - ADC_MCR_OWREN(config->enableOverWrite ? 1U : 0U) | ADC_MCR_WLSIDE(config->convDataAlign))); - - /* 2. Set the operating clock. */ + base->MCR = ((base->MCR & (~(ADC_MCR_ACKO_MASK | ADC_MCR_OWREN_MASK | ADC_MCR_WLSIDE_MASK +#if defined(FSL_FEATURE_ADC_HAS_EXTERNAL_TRIGGER) && (FSL_FEATURE_ADC_HAS_EXTERNAL_TRIGGER==1U) + | ADC_MCR_TRGEN_MASK | ADC_MCR_EDGE_MASK +#endif /* FSL_FEATURE_ADC_HAS_EXTERNAL_TRIGGER */ +#if defined(FSL_FEATURE_ADC_HAS_MCR_XSTARTEN) && (FSL_FEATURE_ADC_HAS_MCR_XSTARTEN==1U) + | ADC_MCR_XSTRTEN_MASK +#endif /* FSL_FEATURE_ADC_HAS_MCR_XSTARTEN */ +#if defined(FSL_FEATURE_ADC_HAS_BCTUMODE) && (FSL_FEATURE_ADC_HAS_BCTUMODE==1U) + | ADC_MCR_BCTUEN_MASK | ADC_MCR_BCTU_MODE_MASK +#endif /* FSL_FEATURE_ADC_HAS_BCTUMODE */ +#if defined(FSL_FEATURE_ADC_HAS_MCR_AVGS) && (FSL_FEATURE_ADC_HAS_MCR_AVGS==1U) + | ADC_MCR_AVGEN_MASK | ADC_MCR_AVGS_MASK +#endif /* FSL_FEATURE_ADC_HAS_MCR_AVGS */ + ))) + | (ADC_MCR_ACKO(config->enableAutoClockOff ? 1U : 0U) | ADC_MCR_OWREN(config->enableOverWrite ? 1U : 0U) + | ADC_MCR_WLSIDE(config->convDataAlign) +#if defined(FSL_FEATURE_ADC_HAS_EXTERNAL_TRIGGER) && (FSL_FEATURE_ADC_HAS_EXTERNAL_TRIGGER==1U) + | ADC_MCR_TRGEN(((uint32_t)config->extTrig & 0x2U) >> 1U) | ADC_MCR_EDGE((uint32_t)config->extTrig & 0x1U) +#endif /* FSL_FEATURE_ADC_HAS_EXTERNAL_TRIGGER */ +#if defined(FSL_FEATURE_ADC_HAS_MCR_XSTARTEN) && FSL_FEATURE_ADC_HAS_MCR_XSTARTEN==1U + | ADC_MCR_XSTRTEN(config->enableAuxiliaryTrig) +#endif /* FSL_FEATURE_ADC_HAS_MCR_XSTARTEN */ +#if defined(FSL_FEATURE_ADC_HAS_BCTUMODE) && (FSL_FEATURE_ADC_HAS_BCTUMODE==1U) + | ADC_MCR_BCTUEN((bool)((uint32_t)config->bctuMode & 0x2U)) | ADC_MCR_BCTU_MODE((bool)((uint32_t)config->bctuMode & 0x1U)) +#endif /* FSL_FEATURE_ADC_HAS_BCTUMODE */ +#if defined(FSL_FEATURE_ADC_HAS_MCR_AVGS) && (FSL_FEATURE_ADC_HAS_MCR_AVGS==1U) + | ADC_MCR_AVGEN(((uint32_t)config->convAvg & 0x4U) >> 2U) | ADC_MCR_AVGS((uint32_t)config->convAvg & 0x3U) +#endif /* FSL_FEATURE_ADC_HAS_MCR_AVGS */ + )); + +#if defined(FSL_FEATURE_ADC_HAS_AMSIO) && (FSL_FEATURE_ADC_HAS_AMSIO==1U) + ADC_SetAdcSpeedMode(base, config->speedMode); +#endif /* FSL_FEATURE_ADC_HAS_AMSIO */ + +#if (defined(FSL_FEATURE_ADC_HAS_CALBISTREG) && (FSL_FEATURE_ADC_HAS_CALBISTREG==1U)) + base->CALBISTREG = ((base->CALBISTREG & ~ADC_CALBISTREG_RESN_MASK) | ADC_CALBISTREG_RESN(config->convRes)); +#endif /* FSL_FEATURE_ADC_HAS_CALBISTREG */ + + /* Set the operating clock. */ + ADC_SetPowerDownMode(base, true); + while (ADC_GetAdcState(base) != kADC_AdcPowerdown); + ADC_SetOperatingClock(base, config->clockFrequency); + adcClockFreq = config->clockFrequency; + __ISB(); + + ADC_SetPowerDownMode(base, false); + while (ADC_GetAdcState(base) != kADC_AdcIdle); - /* 3. Set DMA transfer. */ + /* Set DMA transfer. */ base->DMAE = ((base->DMAE & (~ADC_DMAE_DCLR_MASK)) | ADC_DMAE_DCLR(config->dmaRequestClearSrc)); - /* 4. Set group 0 and group 1 sample phase duration. */ + /* Set GROUPn sample phase duration. */ base->CTR0 = ((base->CTR0 & (~ADC_CTR0_INPSAMP_MASK)) | ADC_CTR0_INPSAMP(config->samplePhaseDuration[0U])); base->CTR1 = ((base->CTR1 & (~ADC_CTR1_INPSAMP_MASK)) | ADC_CTR1_INPSAMP(config->samplePhaseDuration[1U])); +#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3) + if(1U == FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3(base)) + { + base->CTR2 = ((base->CTR2 & (~ADC_CTR2_INPSAMP_MASK)) | ADC_CTR2_INPSAMP(config->samplePhaseDuration[2U])); + } +#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3 */ - /* 5. Set Group 0 and Group 32 pre-sample voltage sources and decide whether to convert the pre-sample value. */ - base->PSCR = - ((base->PSCR & (~(ADC_PSCR_PREVAL0_MASK | ADC_PSCR_PREVAL1_MASK | ADC_PSCR_PRECONV_MASK))) | - (ADC_PSCR_PREVAL0(config->presampleVoltageSrc[0U]) | ADC_PSCR_PREVAL1(config->presampleVoltageSrc[1U]) | - ADC_PSCR_PRECONV(config->enableConvertPresampleVal ? 1U : 0U))); + /* Set GROUPn pre-sample voltage sources and decide whether to convert the pre-sample value. */ + base->PSCR = ((base->PSCR & (~(ADC_PSCR_PREVAL0_MASK | ADC_PSCR_PREVAL1_MASK | ADC_PSCR_PRECONV_MASK))) + | (ADC_PSCR_PREVAL0(config->presampleVoltageSrc[0U]) | ADC_PSCR_PREVAL1(config->presampleVoltageSrc[1U]) + | ADC_PSCR_PRECONV(config->enableConvertPresampleVal ? 1U : 0U))); + +#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3) + if(1U == FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3(base)) + { + base->PSCR = ((base->PSCR & (~ADC_PSCR_PREVAL2_MASK)) | ADC_PSCR_PREVAL1(config->presampleVoltageSrc[2U])); + } +#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3 */ } /*! @@ -173,8 +256,8 @@ void ADC_SetConvChainConfig(ADC_Type *base, const adc_chain_config_t *config) if (chanConf->enableWdg) { CWSELR_IO(base, - ((GET_REGINDEX(chanConf->channelIndex) * 4U) + (GET_BITINDEX(chanConf->channelIndex) >> 3U))) |= - WDG_SELECT(chanConf->wdgIndex, ((uint32_t)(chanConf->channelIndex) % 8U)); + ((GET_REGINDEX(chanConf->channelIndex) * 4U) + (GET_BITINDEX(chanConf->channelIndex) >> 3U))) |= + WDG_SELECT(chanConf->wdgIndex, ((uint32_t)(chanConf->channelIndex) % 8U)); } chanConf += 1U; @@ -182,6 +265,13 @@ void ADC_SetConvChainConfig(ADC_Type *base, const adc_chain_config_t *config) for (uint8_t index = 0U; index < (uint8_t)ADC_GROUP_COUNTS; ++index) { +#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3) + if(1U != FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3(base)) + { + break; + } +#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3 */ + /* 1. Set conversion channel's interrupt.*/ *(((volatile uint32_t *)(&(base->CIMR0))) + index) = convChannelIntMask[index]; /* 2. Set the conversion channel's pre-sample feature.*/ @@ -201,6 +291,12 @@ void ADC_SetConvChainConfig(ADC_Type *base, const adc_chain_config_t *config) { for (uint8_t index = 0U; index < (uint8_t)ADC_GROUP_COUNTS; ++index) { +#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3) + if(1U != FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3(base)) + { + break; + } +#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3 */ *(((volatile uint32_t *)(&(base->JCMR0))) + index) = convChannelMask[index]; } @@ -217,6 +313,12 @@ void ADC_SetConvChainConfig(ADC_Type *base, const adc_chain_config_t *config) { for (uint8_t index = 0U; index < (uint8_t)ADC_GROUP_COUNTS; ++index) { +#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3) + if(1U != FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3(base)) + { + break; + } +#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3 */ *(((volatile uint32_t *)(&(base->NCMR0))) + index) = convChannelMask[index]; } @@ -248,14 +350,18 @@ void ADC_SetAnalogWdgConfig(ADC_Type *base, const adc_wdg_config_t *config) { assert(config != NULL); +#if (defined(ADC_THRESHOLD_COUNTS) && (ADC_THRESHOLD_COUNTS==8U)) volatile uint32_t *THRHLR[ADC_THRESHOLD_COUNTS] = {&(base->THRHLR0), &(base->THRHLR1), &(base->THRHLR2), &(base->THRHLR3), &(base->THRHLR4), &(base->THRHLR5), &(base->THRHLR6), &(base->THRHLR7)}; +#else /* ADC_THRESHOLD_COUNTS=4U */ + volatile uint32_t *THRHLR[ADC_THRESHOLD_COUNTS] = {&(base->THRHLR[0]), &(base->THRHLR[1]), + &(base->THRHLR[2]), &(base->THRHLR[3])}; +#endif /* ADC_THRESHOLD_COUNTS */ /* Set low/high threshold values for selected channels. */ - *(THRHLR[config->wdgIndex]) = - (((*(THRHLR[config->wdgIndex])) & (~(ADC_THRHLR_THRL_MASK | ADC_THRHLR_THRH_MASK))) | - (ADC_THRHLR_THRL(config->lowThresholdVal) | ADC_THRHLR_THRH(config->highThresholdVal))); + *(THRHLR[config->wdgIndex]) = (((*(THRHLR[config->wdgIndex])) & (~(ADC_THRHLR_THRL_MASK | ADC_THRHLR_THRH_MASK))) | + (ADC_THRHLR_THRL(config->lowThresholdVal) | ADC_THRHLR_THRH(config->highThresholdVal))); /* Enable analog watchdog low/high threshold interrupts. */ ADC_EnableWdgThresholdInt(base, (uint32_t)(((uint32_t)config->wdgThresholdInt) << (2U * (config->wdgIndex)))); @@ -291,25 +397,79 @@ bool ADC_DoCalibration(ADC_Type *base, const adc_calibration_config_t *config) assert(config != NULL); bool calibrationStatus = true; + bool clockNeedRecovery = false; + +#if (defined(FSL_FEATURE_ADC_HAS_CALBISTREG) && (FSL_FEATURE_ADC_HAS_CALBISTREG==1U)) + /* Clear the bits and set to calibration values */ + base->CALBISTREG = ((base->CALBISTREG & (~(ADC_CALBISTREG_AVG_EN_MASK | + ADC_CALBISTREG_TSAMP_MASK | + ADC_CALBISTREG_NR_SMPL_MASK))) | + (ADC_CALBISTREG_TSAMP(config->sampleTime) | + ADC_CALBISTREG_NR_SMPL(config->averageSampleNumbers) | + ADC_CALBISTREG_AVG_EN(config->enableAverage ? 1U : 0U))); + +#if defined(FSL_FEATURE_ADC_HAS_AMSIO) && (FSL_FEATURE_ADC_HAS_AMSIO==1U) + ADC_SetAdcSpeedMode(base, kADC_SpeedModeNormal); +#endif /* FSL_FEATURE_ADC_HAS_AMSIO */ + +#if defined(FSL_FEATURE_ADC_HAS_CAL2) && (FSL_FEATURE_ADC_HAS_CAL2==1U) + base->CAL2 &= ~ADC_CAL2_ENX_MASK; +#endif /* FSL_FEATURE_ADC_HAS_CAL2 */ + + /* Slow down ADC functional clock frequency. */ + if(adcClockFreq != kADC_ModuleClockFreqDivide8) + { + ADC_SetPowerDownMode(base, true); + while (ADC_GetAdcState(base) != kADC_AdcPowerdown); + + ADC_SetOperatingClock(base, kADC_ModuleClockFreqDivide8); + __ISB(); + + ADC_SetPowerDownMode(base, false); + while (ADC_GetAdcState(base) != kADC_AdcIdle); + + clockNeedRecovery = true; + } + + /* Start calibration. */ + base->CALBISTREG |= ADC_CALBISTREG_TEST_EN_MASK; +#else /* Clear the bits and set to calibration values */ base->MCR = ((base->MCR & (~(ADC_MCR_AVGEN_MASK | ADC_MCR_TSAMP_MASK | ADC_MCR_NRSMPL_MASK))) | (ADC_MCR_AVGEN(config->enableAverage ? 1U : 0U) | ADC_MCR_TSAMP(config->sampleTime) | ADC_MCR_NRSMPL(config->averageSampleNumbers))); + /* Slow down ADC functional clock frequency. */ + if(adcClockFreq != kADC_HalfBusFrequency) + { + ADC_SetPowerDownMode(base, true); + while (ADC_GetAdcState(base) != kADC_AdcPowerdown); + + ADC_SetOperatingClock(base, kADC_HalfBusFrequency); + __ISB(); + + ADC_SetPowerDownMode(base, false); + while (ADC_GetAdcState(base) != kADC_AdcIdle); + + clockNeedRecovery = true; + } + /* Start calibration. */ base->MCR |= ADC_MCR_CALSTART_MASK; +#endif /* FSL_FEATURE_ADC_HAS_CALBISTREG */ /* Wait for calibration to finish. */ while (ADC_CheckCalibrationBusy(base)) { } + /* Check the status of calibration. If calibration failed, check the pass/fail status of each calibration step * in the CALSTAT register look for failures, if calibration passes, double-check the MSR[CALIBRTD] bitfield. */ if (ADC_CheckCalibrationFailed(base)) { - base->MSR = ADC_MSR_CALFAIL_MASK; + ADC_ClearCalibrationFailedFlag(base); calibrationStatus = false; } else @@ -324,9 +484,23 @@ bool ADC_DoCalibration(ADC_Type *base, const adc_calibration_config_t *config) } } + /* ADC functional clock recovery. */ + if(clockNeedRecovery) + { + ADC_SetPowerDownMode(base, true); + while (ADC_GetAdcState(base) != kADC_AdcPowerdown); + + ADC_SetOperatingClock(base, adcClockFreq); + __ISB(); + + ADC_SetPowerDownMode(base, false); + while (ADC_GetAdcState(base) != kADC_AdcIdle); + } + return calibrationStatus; } +#if !(defined(FSL_FEATURE_ADC_HAS_CALSTAT) && (FSL_FEATURE_ADC_HAS_CALSTAT==0U)) /*! * brief This function is used to get the test result for the last failed test. * @@ -347,6 +521,7 @@ void ADC_GetCalibrationLastFailedTestResult(ADC_Type *base, int16_t *result) *result = (int16_t)tempResult; } +#endif /* FSL_FEATURE_ADC_HAS_CALSTAT */ /*! * brief This function is used to configure the user gain and offset. @@ -358,9 +533,14 @@ void ADC_GetCalibrationLastFailedTestResult(ADC_Type *base, int16_t *result) void ADC_SetUserOffsetAndGainConfig(ADC_Type *base, const adc_user_offset_gain_config_t *config) { assert(config != NULL); - +#if !(defined(FSL_FEATURE_ADC_HAS_USROFSGN) && (FSL_FEATURE_ADC_HAS_USROFSGN==0U)) base->USROFSGN = ((base->USROFSGN & (~(ADC_USROFSGN_GAINUSER_MASK | ADC_USROFSGN_OFFSUSER_MASK))) | (ADC_USROFSGN_OFFSUSER(config->userOffset) | ADC_USROFSGN_GAINUSER(config->userGain))); +#endif /* FSL_FEATURE_ADC_HAS_USROFSGN */ +#if defined(FSL_FEATURE_ADC_HAS_OFSGNUSR) && (FSL_FEATURE_ADC_HAS_OFSGNUSR==1U) + base->OFSGNUSR = ((base->OFSGNUSR & (~(ADC_OFSGNUSR_GAIN_USER_MASK | ADC_OFSGNUSR_OFFSET_USER_MASK))) | + (ADC_OFSGNUSR_OFFSET_USER(config->userOffset) | ADC_OFSGNUSR_GAIN_USER(config->userGain))); +#endif /* FSL_FEATURE_ADC_HAS_OFSGNUSR */ } /*! @@ -427,8 +607,13 @@ void ADC_SetSelfTestWdgConfig(ADC_Type *base, const adc_self_test_wdg_config_t * { assert(config != NULL); +#if(ADC_SELF_TEST_THRESHOLD_COUNTS==6U) volatile uint32_t *STAWR[ADC_SELF_TEST_THRESHOLD_COUNTS] = {&(base->STAW0R), &(base->STAW1AR), &(base->STAW1BR), &(base->STAW2R), &(base->STAW4R), &(base->STAW5R)}; +#else /* ADC_SELF_TEST_THRESHOLD_COUNTS==5U */ + volatile uint32_t *STAWR[ADC_SELF_TEST_THRESHOLD_COUNTS] = {&(base->STAW0R), &(base->STAW1R), &(base->STAW2R), + &(base->STAW4R), &(base->STAW5R)}; +#endif /* ADC_SELF_TEST_THRESHOLD_COUNTS */ /* Set low/high threshold values for selected watchdog. */ if (config->wdgThresholdId == kADC_SelfTestWdgThresholdForAlgSStep2) @@ -513,6 +698,7 @@ bool ADC_GetSelfTestChannelConvData(ADC_Type *base, adc_self_test_conv_result_t return true; } +#if !(defined(FSL_FEATURE_ADC_HAS_STDR2) && (FSL_FEATURE_ADC_HAS_STDR2==0U)) /*! * brief This function is used to get the test channel converted data when algorithm S step 1 executes. * @@ -544,3 +730,4 @@ bool ADC_GetSelfTestChannelConvDataForAlgSStep1(ADC_Type *base, adc_self_test_co return true; } +#endif /* FSL_FEATURE_ADC_HAS_STDR2 */ diff --git a/mcux/mcux-sdk-ng/drivers/sar_adc/fsl_sar_adc.h b/mcux/mcux-sdk-ng/drivers/sar_adc/fsl_sar_adc.h index c996377459..9d74c513d9 100644 --- a/mcux/mcux-sdk-ng/drivers/sar_adc/fsl_sar_adc.h +++ b/mcux/mcux-sdk-ng/drivers/sar_adc/fsl_sar_adc.h @@ -1,6 +1,5 @@ /* - * Copyright 2023-2024 NXP - * All rights reserved. + * Copyright 2023-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,8 +19,8 @@ ******************************************************************************/ /*! @name Driver version */ /*! @{ */ -/*! @brief SAR ADC driver version 2.1.1. */ -#define FSL_SAR_ADC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*! @brief SAR ADC driver version 2.3.0. */ +#define FSL_SAR_ADC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*! @} */ #define ADC_GROUP_COUNTS FSL_FEATURE_ADC_CHANNEL_GROUPS_COUNT @@ -40,7 +39,13 @@ #define JCMR_IO(base, registerIndex) REGISTER_READWRITE(((base)->JCMR0), (registerIndex)) #define PSR_IO(base, registerIndex) REGISTER_READWRITE(((base)->PSR0), (registerIndex)) #define DMAR_IO(base, registerIndex) REGISTER_READWRITE(((base)->DMAR0), (registerIndex)) + +#if(ADC_GROUP_COUNTS==2U) #define CWSELR_IO(base, registerIndex) REGISTER_READWRITE(((base)->CWSELR0), (registerIndex)) +#else /* ADC_GROUP_COUNTS==3U */ +#define CWSELR_IO(base, registerIndex) REGISTER_READWRITE(((base)->CWSELRPI[0U]), (registerIndex)) +#endif /* ADC_GROUP_COUNTS */ + #define CWENR_IO(base, registerIndex) REGISTER_READWRITE(((base)->CWENR0), (registerIndex)) #define CIMR_IO(base, registerIndex) REGISTER_READWRITE(((base)->CIMR0), (registerIndex)) #define CEOCFR_IO(base, registerIndex) REGISTER_READWRITE(((base)->CEOCFR0), (registerIndex)) @@ -51,11 +56,19 @@ #define AWORR_I(base, registerIndex) REGISTER_READONLY((base->AWORR0), (registerIndex)) #define CDR_I(base, registerIndex) REGISTER_READONLY((base->PCDR[0U]), (registerIndex)) +#if(ADC_GROUP_COUNTS==2U) #define WDG_SELECT_MASK(shiftIndex) ((uint32_t)ADC_CWSELR0_WSEL_CH0_MASK << ((shiftIndex) * 4U)) #define WDG_SELECT_SHIFT(shiftIndex) (ADC_CWSELR0_WSEL_CH0_SHIFT + ((shiftIndex) * 4U)) #define WDG_SELECT(val, shiftIndex) \ (((uint32_t)(((uint32_t)(val)) << WDG_SELECT_SHIFT(shiftIndex))) & WDG_SELECT_MASK(shiftIndex)) +#else /* ADC_GROUP_COUNTS==3U */ +#define WDG_SELECT_MASK(shiftIndex) ((uint32_t)ADC_CWSELRPI_WSEL_SI0_0_MASK << ((shiftIndex) * 4U)) +#define WDG_SELECT_SHIFT(shiftIndex) (ADC_CWSELRPI_WSEL_SI0_0_SHIFT + ((shiftIndex) * 4U)) +#define WDG_SELECT(val, shiftIndex) \ + (((uint32_t)(((uint32_t)(val)) << WDG_SELECT_SHIFT(shiftIndex))) & WDG_SELECT_MASK(shiftIndex)) +#endif /* ADC_GROUP_COUNTS */ +#if(ADC_SELF_TEST_THRESHOLD_COUNTS==6U) #define ADC_THRHLR_THRL_MASK ADC_THRHLR0_THRL_MASK #define ADC_THRHLR_THRL_SHIFT ADC_THRHLR0_THRL_SHIFT #define ADC_THRHLR_THRL(val) ADC_THRHLR0_THRL(val) @@ -63,6 +76,7 @@ #define ADC_THRHLR_THRH_MASK ADC_THRHLR0_THRH_MASK #define ADC_THRHLR_THRH_SHIFT ADC_THRHLR0_THRH_SHIFT #define ADC_THRHLR_THRH(val) ADC_THRHLR0_THRH(val) +#endif #define ADC_CDR_VALID_MASK ADC_PCDR_VALID_MASK #define ADC_CDR_VALID_SHIFT ADC_PCDR_VALID_SHIFT @@ -92,8 +106,11 @@ enum _adc_conv_int_enable { kADC_NormalConvChainEndIntEnable = ADC_IMR_MSKECH_MASK, /*!< Enable end of normal chain conversion interrupt. */ kADC_NormalConvEndIntEnable = ADC_IMR_MSKEOC_MASK, /*!< Enable end of normal conversion interrupt. */ - kADC_InjectConvChainEndIntEnable = ADC_IMR_MSKJEOC_MASK, /*!< Enable end of inject chain conversion interrupt. */ + kADC_InjectConvChainEndIntEnable = ADC_IMR_MSKJECH_MASK, /*!< Enable end of inject chain conversion interrupt. */ kADC_InjectConvEndIntEnable = ADC_IMR_MSKJEOC_MASK, /*!< Enable end of inject conversion interrupt. */ +#if defined(FSL_FEATURE_ADC_HAS_BCTUMODE) && (FSL_FEATURE_ADC_HAS_BCTUMODE==1U) + kADC_BctuConvEndIntEnable = ADC_IMR_MSKEOBCTU_MASK, /*!< Enable end of BCTU conversion interrupt. */ +#endif /* FSL_FEATURE_ADC_HAS_BCTUMODE */ }; /*! @@ -148,6 +165,10 @@ enum _adc_conv_int_flag inject chain conversion interrupt has occurred. */ kADC_InjectConvEndIntFlag = ADC_ISR_JEOC_MASK, /*!< Indicates whether the end of inject conversion interrupt has occurred. */ +#if defined(FSL_FEATURE_ADC_HAS_BCTUMODE) && (FSL_FEATURE_ADC_HAS_BCTUMODE==1U) + kADC_BctuConvEndIntFlag = ADC_ISR_EOBCTU_MASK, /*!< Indicates whether the end of + BCTU conversion interrupt has occurred. */ +#endif /* FSL_FEATURE_ADC_HAS_BCTUMODE */ }; /*! @@ -216,6 +237,67 @@ enum _adc_self_test_int_flag watchdog sequence error interrupt has occurred. */ }; +#if defined(FSL_FEATURE_ADC_HAS_BCTUMODE) && (FSL_FEATURE_ADC_HAS_BCTUMODE==1U) +/*! + * @brief This enumeration provides the selection of the Body Cross Trigger Unit (BCTU) mode. + */ +typedef enum _adc_bctu_mode +{ + kADC_BctuModeDisable = 0x0U, /*!< BCTU disabled. */ + kADC_BctuTrig = 0x2U, /*!< BCTU enabled, only BCTU can trigger conversion. */ + kADC_AllTrig = 0x3U, /*!< BCTU enabled, all trigger sources can trigger conversion. */ +} adc_bctu_mode_t; +#endif /* FSL_FEATURE_ADC_HAS_BCTUMODE */ + +#if (defined(FSL_FEATURE_ADC_HAS_CALBISTREG) && (FSL_FEATURE_ADC_HAS_CALBISTREG==1U)) +/*! + * @brief This enumeration provides the selection of the ADC conversion resolution. + */ +typedef enum _adc_conv_res +{ + kADC_ConvRes14Bit = 0x0U, /*!< 14-bit resolution. */ + kADC_ConvRes12Bit = 0x1U, /*!< 12-bit resolution. */ + kADC_ConvRes10Bit = 0x2U, /*!< 10-bit resolution. */ + kADC_ConvRes8Bit = 0x2U, /*!< 8-bit resolution. */ +} adc_conv_res_t; +#endif /* FSL_FEATURE_ADC_HAS_CALBISTREG */ + +/*! + * @brief This enumeration provides the selection of the ADC external trigger type. + */ +typedef enum _adc_ext_trig +{ + kADC_ExtTrigDisable = 0x0U, /*!< Normal trigger input does not start a conversion. */ + kADC_ExtTrigFallingEdge = 0x2U, /*!< Normal trigger (falling edge) input starts a conversion. */ + kADC_ExtTrigRisingEdge = 0x3U, /*!< Normal trigger (rising edge) input starts a conversion. */ +} adc_ext_trig_t; + +#if defined(FSL_FEATURE_ADC_HAS_AMSIO) && (FSL_FEATURE_ADC_HAS_AMSIO==1U) +/*! + * @brief This enumeration provides the selection of the ADC conversion speed mode. + */ +typedef enum _adc_speed_mode +{ + kADC_SpeedModeNormal = 0x0U, /*!< Normal conversion speed. */ + kADC_SpeedModeHigh = 0x3U, /*!< High-speed conversion. */ +} adc_speed_mode_t; +#endif /* FSL_FEATURE_ADC_HAS_AMSIO */ + +#if defined(FSL_FEATURE_ADC_HAS_MCR_AVGS) && (FSL_FEATURE_ADC_HAS_MCR_AVGS==1U) +/*! + * @brief This enumeration provides the selection of the number of conversions ADC uses to calculate + * the conversion result. + */ +typedef enum _adc_conv_avg +{ + kADC_ConvAvgDisable = 0x0U, /*!< Conversions averaging disabled. */ + kADC_ConvAvg4 = 0x4U, /*!< 4 conversions averaging. */ + kADC_ConvAvg8 = 0x5U, /*!< 8 conversions averaging. */ + kADC_ConvAvg16 = 0x6U, /*!< 16 conversions averaging. */ + kADC_ConvAvg32 = 0x7U, /*!< 32 conversions averaging. */ +} adc_conv_avg_t; +#endif /* FSL_FEATURE_ADC_HAS_MCR_AVGS */ + /*! * @brief This enumeration provides the selection of the ADC state. */ @@ -246,8 +328,16 @@ typedef enum _adc_conv_mode */ typedef enum _adc_clock_frequency { +#if !(defined(FSL_FEATURE_ADC_HAS_MCR_ADCLKSE) && (FSL_FEATURE_ADC_HAS_MCR_ADCLKSE==0U)) kADC_HalfBusFrequency = 0x00U, /*!< Half of bus clock frequency. */ kADC_FullBusFrequency = 0x01U, /*!< Equal to bus clock frequency. */ +#endif /* FSL_FEATURE_ADC_HAS_MCR_ADCLKSE */ +#if (defined(FSL_FEATURE_ADC_HAS_MCR_ADCLKSEL) && (FSL_FEATURE_ADC_HAS_MCR_ADCLKSEL==1U)) + kADC_ModuleClockFreq = 0x00U, /*!< Module clock frequency. */ + kADC_ModuleClockFreqDivide2 = 0x01U, /*!< Module clock frequency / 2. */ + kADC_ModuleClockFreqDivide4 = 0x02U, /*!< Module clock frequency / 4. */ + kADC_ModuleClockFreqDivide8 = 0x03U, /*!< Module clock frequency / 8. */ +#endif /* FSL_FEATURE_ADC_HAS_MCR_ADCLKSEL */ } adc_clock_frequency_t; /*! @@ -266,10 +356,15 @@ typedef enum _adc_conv_data_align */ typedef enum _adc_presample_voltage_src { +#if(ADC_GROUP_COUNTS==2U) kADC_PresampleVoltageSrcDVDD = 0x00U, /*!< Use DVDD0P8/2 as pre-sample voltage source. */ kADC_PresampleVoltageSrcAVDD = 0x01U, /*!< Use AVDD1P8/4 as pre-sample voltage source. */ kADC_PresampleVoltageSrcVREFL = 0x02U, /*!< Use VREFL_1p8 as pre-sample voltage source. */ kADC_PresampleVoltageSrcVREFH = 0x03U, /*!< Use VREFH_1p8 as pre-sample voltage source. */ +#else /* ADC_GROUP_COUNTS==3U */ + kADC_PresampleVoltageSrcVREL = 0x00U, /*!< Use VREL as pre-sample voltage source. */ + kADC_PresampleVoltageSrcVREH = 0x01U, /*!< Use VREH as pre-sample voltage source. */ +#endif /* ADC_GROUP_COUNTS */ } adc_presample_voltage_src_t; /*! @@ -288,10 +383,17 @@ typedef enum _adc_dma_request_clear_src */ typedef enum _adc_average_sample_numbers { +#if (defined(FSL_FEATURE_ADC_HAS_CALBISTREG) && (FSL_FEATURE_ADC_HAS_CALBISTREG==1U)) + kADC_AverageSampleNumbers4 = 0x00U, /*!< Use 4 averaging samples during calibration. */ + kADC_AverageSampleNumbers8 = 0x01U, /*!< Use 8 averaging samples during calibration. */ + kADC_AverageSampleNumbers16 = 0x02U, /*!< Use 16 averaging samples during calibration. */ + kADC_AverageSampleNumbers32 = 0x03U, /*!< Use 32 averaging samples during calibration. */ +#else kADC_AverageSampleNumbers16 = 0x00U, /*!< Use 16 averaging samples during calibration. */ kADC_AverageSampleNumbers32 = 0x01U, /*!< Use 32 averaging samples during calibration. */ kADC_AverageSampleNumbers128 = 0x02U, /*!< Use 128 averaging samples during calibration. */ kADC_AverageSampleNumbers512 = 0x03U, /*!< Use 512 averaging samples during calibration. */ +#endif /* FSL_FEATURE_ADC_HAS_CALBISTREG */ } adc_average_sample_numbers_t; /*! @@ -341,10 +443,15 @@ typedef enum _adc_self_test_wdg_threshold { kADC_SelfTestWdgThresholdForAlgSStep0 = 0U, /*!< Self-test watchdog threshold for the algorithm S step 0. */ +#if(ADC_GROUP_COUNTS==2U) kADC_SelfTestWdgThresholdForAlgSStep1Integer = 1U, /*!< Self-test watchdog threshold for the algorithm S step 1 integer part. */ kADC_SelfTestWdgThresholdForAlgSStep1Fraction = 2U, /*!< Self-test watchdog threshold for the algorithm S step 1 fraction part. */ +#else /* ADC_GROUP_COUNTS==3U */ + kADC_SelfTestWdgThresholdForAlgSStep1 = 2U, /*!< Self-test watchdog threshold + for the algorithm S step 1 fraction part. */ +#endif /* ADC_GROUP_COUNTS */ kADC_SelfTestWdgThresholdForAlgSStep2 = 3U, /*!< Self-test watchdog threshold for the algorithm S step 2. */ kADC_SelfTestWdgThresholdForAlgCStep0 = 5U, /*!< Self-test watchdog threshold @@ -382,6 +489,29 @@ typedef struct _adc_config bool enableConvertPresampleVal; /*!< Decides whether to convert the pre-sampled value, if enabled, pre-sampling is followed by the conversion, sampling will be bypassed and conversion of the pre-sampled data will be done. */ +#if defined(FSL_FEATURE_ADC_HAS_MCR_XSTARTEN) && (FSL_FEATURE_ADC_HAS_MCR_XSTARTEN==1U) + bool enableAuxiliaryTrig; /*!< Decides whether to enable the auxiliary normal trigger source + to start a conversion. You can use this field to synchronize the + start of a conversion of two ADC instances. */ +#endif /* FSL_FEATURE_ADC_HAS_MCR_XSTARTEN */ +#if defined(FSL_FEATURE_ADC_HAS_AMSIO) && (FSL_FEATURE_ADC_HAS_AMSIO==1U) + adc_speed_mode_t speedMode; /*!< Selects ADC speed mode. */ +#endif /* FSL_FEATURE_ADC_HAS_AMSIO */ +#if defined(FSL_FEATURE_ADC_HAS_DSDR) && (FSL_FEATURE_ADC_HAS_DSDR==1U) + uint16_t convDelay; /*!< Specifies the delay in terms of the number of module clock cycles. In case + the channel to convert changed since the last conversion and this new channel + is an external channel, the conversion starts after a delay configured by convDelay. */ +#endif /* FSL_FEATURE_ADC_HAS_DSDR */ +#if defined(FSL_FEATURE_ADC_HAS_BCTUMODE) && (FSL_FEATURE_ADC_HAS_BCTUMODE==1U) + adc_bctu_mode_t bctuMode; /*!< Selects the BCTU mode. */ +#endif /* FSL_FEATURE_ADC_HAS_BCTUMODE */ +#if (defined(FSL_FEATURE_ADC_HAS_CALBISTREG) && (FSL_FEATURE_ADC_HAS_CALBISTREG==1U)) + adc_conv_res_t convRes; /*!< Specifies the number of significant bits per conversion data. */ +#endif /* FSL_FEATURE_ADC_HAS_CALBISTREG */ +#if defined(FSL_FEATURE_ADC_HAS_MCR_AVGS) && (FSL_FEATURE_ADC_HAS_MCR_AVGS==1U) + adc_conv_avg_t convAvg; /*!< Selects the number of conversions ADC uses to calculate the conversion result. */ +#endif /* FSL_FEATURE_ADC_HAS_MCR_AVGS */ + adc_ext_trig_t extTrig; /*!< Specifies whether the normal trigger (with trigger type) input starts a conversion. */ adc_conv_data_align_t convDataAlign; /*!< Selects the conversion data alignment. */ adc_clock_frequency_t clockFrequency; /*!< Selects the ADC clock frequency. */ adc_dma_request_clear_src_t dmaRequestClearSrc; /*!< Selects DMA request clear source. */ @@ -576,6 +706,7 @@ static inline void ADC_SetPowerDownMode(ADC_Type *base, bool enable) */ static inline void ADC_SetOperatingClock(ADC_Type *base, adc_clock_frequency_t clockSelect) { +#if !(defined(FSL_FEATURE_ADC_HAS_MCR_ADCLKSE) && (FSL_FEATURE_ADC_HAS_MCR_ADCLKSE==0U)) if (kADC_HalfBusFrequency == clockSelect) { base->MCR &= ~ADC_MCR_ADCLKSE_MASK; @@ -584,7 +715,26 @@ static inline void ADC_SetOperatingClock(ADC_Type *base, adc_clock_frequency_t c { base->MCR |= ADC_MCR_ADCLKSE_MASK; } +#endif /* FSL_FEATURE_ADC_HAS_MCR_ADCLKSE */ +#if (defined(FSL_FEATURE_ADC_HAS_MCR_ADCLKSEL) && (FSL_FEATURE_ADC_HAS_MCR_ADCLKSEL==1U)) + base->MCR = ((base->MCR & ~ADC_MCR_ADCLKSEL_MASK) | ADC_MCR_ADCLKSEL(clockSelect)); +#endif /* FSL_FEATURE_ADC_HAS_MCR_ADCLKSEL */ } + +#if defined(FSL_FEATURE_ADC_HAS_AMSIO) && (FSL_FEATURE_ADC_HAS_AMSIO==1U) +/*! + * @brief This function is used to set the ADC speed mode. + * + * + * @param base ADC peripheral base address. + * @param speedMode ADC speed mode selection, please refer to @ref adc_speed_mode_t for details. + */ +static inline void ADC_SetAdcSpeedMode(ADC_Type *base, adc_speed_mode_t speedMode) +{ + base->AMSIO = ((base->AMSIO & ~ADC_AMSIO_HSEN_MASK) | ADC_AMSIO_HSEN(speedMode)); +} +#endif /* FSL_FEATURE_ADC_HAS_AMSIO */ + /*! * @} */ @@ -645,6 +795,22 @@ static inline bool ADC_CheckSelfTestConvInProcess(ADC_Type *base) return (0UL != ((base->MSR & ADC_MSR_SELF_TEST_S_MASK) >> ADC_MSR_SELF_TEST_S_SHIFT)); } +#if defined(FSL_FEATURE_ADC_HAS_BCTUMODE) && (FSL_FEATURE_ADC_HAS_BCTUMODE==1U) +/*! + * @brief This function is used to check whether the BCTU conversion was started. + * + * @param base ADC peripheral base address. + * + * @return BCTU conversion status. + * - \b true Ongoing conversion was triggered by BCTU. + * - \b false Conversion was not triggered by BCTU. + */ +static inline bool ADC_CheckBctuConvStatus(ADC_Type *base) +{ + return (0UL != ((base->MSR & ADC_MSR_BCTUSTART_MASK) >> ADC_MSR_BCTUSTART_SHIFT)); +} +#endif /* FSL_FEATURE_ADC_HAS_BCTUMODE */ + /*! * @brief This function is used to check whether the inject conversion is in process or not. * @@ -687,6 +853,47 @@ static inline bool ADC_CheckNormalConvInProcess(ADC_Type *base) return (0UL != ((base->MSR & ADC_MSR_NSTART_MASK) >> ADC_MSR_NSTART_SHIFT)); } +#if (defined(FSL_FEATURE_ADC_HAS_CALBISTREG) && (FSL_FEATURE_ADC_HAS_CALBISTREG==1U)) +/*! + * @brief This function is used to check whether the ADC is executing calibration or ready for use. + * + * @param base ADC peripheral base address. + * + * @return Calibration process status. + * - \b true ADC is busy in a calibration process. + * - \b false ADC is ready for use. + */ +static inline bool ADC_CheckCalibrationBusy(ADC_Type *base) +{ + return (0UL != ((base->CALBISTREG & ADC_CALBISTREG_C_T_BUSY_MASK) >> ADC_CALBISTREG_C_T_BUSY_SHIFT)); +} + +/*! + * @brief This function is used to check whether the calibration has failed or passed. + * + * @note When the user clears the calibration failed status and then reads the status, it will display the calibration + * passed. At this time, the calibration may not be successful. The user must read the MSR[CALBUSY] bit by function @ref + * ADC_CheckCalibrationBusy to perform a double check. + * + * @return Normal conversion status. + * - \b true Calibration failed. + * - \b false Calibration passed (must be checked with CALBUSY = 0b). + */ +static inline bool ADC_CheckCalibrationFailed(ADC_Type *base) +{ + return (0UL != ((base->CALBISTREG & ADC_CALBISTREG_TEST_FAIL_MASK) >> ADC_CALBISTREG_TEST_FAIL_SHIFT)); +} + +/*! + * @brief This function is used to clear the flag of calibration. + * + * @param base ADC peripheral base address. + */ +static inline void ADC_ClearCalibrationFailedFlag(ADC_Type *base) +{ + base->CALBISTREG = ADC_CALBISTREG_TEST_FAIL_MASK; +} +#else /*! * @brief This function is used to check whether the ADC is executing calibration or ready for use. * @@ -726,6 +933,7 @@ static inline void ADC_ClearCalibrationFailedFlag(ADC_Type *base) { base->MSR = ADC_MSR_CALFAIL_MASK; } +#endif /* FSL_FEATURE_ADC_HAS_CALBISTREG */ /*! * @brief This function is used to check whether the calibration is successful or not. @@ -1224,15 +1432,6 @@ static inline void ADC_ClearWdgThresholdIntStatus(ADC_Type *base, uint32_t mask) */ bool ADC_DoCalibration(ADC_Type *base, const adc_calibration_config_t *config); -/*! - * @brief This function is used to get the test result for the last failed test. - * - * @param base ADC peripheral base address. - * @param result Points to a 16-bit signed variable, and it is used to store the test result for the last failing - * test. - */ -void ADC_GetCalibrationLastFailedTestResult(ADC_Type *base, int16_t *result); - /*! * @brief This function is used to configure the user gain and offset. * @@ -1268,6 +1467,16 @@ void ADC_SetSelfTestConfig(ADC_Type *base, const adc_self_test_config_t *config) */ void ADC_SetSelfTestWdgConfig(ADC_Type *base, const adc_self_test_wdg_config_t *config); +#if !(defined(FSL_FEATURE_ADC_HAS_CALSTAT) && (FSL_FEATURE_ADC_HAS_CALSTAT==0U)) +/*! + * @brief This function is used to get the test result for the last failed test. + * + * @param base ADC peripheral base address. + * @param result Points to a 16-bit signed variable, and it is used to store the test result for the last failing + * test. + */ +void ADC_GetCalibrationLastFailedTestResult(ADC_Type *base, int16_t *result); + /*! * @brief This function is used to get the status of the calibration steps. * @@ -1282,6 +1491,7 @@ static inline uint16_t ADC_GetCalibrationStepsStatus(ADC_Type *base) { return (uint16_t)(base->CALSTAT & 0xFFFFU); } +#endif /* FSL_FEATURE_ADC_HAS_CALSTAT */ /*! * @brief This function is used to enable the ADC self-test. @@ -1330,7 +1540,11 @@ static inline void ADC_DisableSelfTest(ADC_Type *base) */ static inline void ADC_EnableSelfTestWdgThreshold(ADC_Type *base, adc_self_test_wdg_threshold_t wdgID) { - if ((wdgID != kADC_SelfTestWdgThresholdForAlgSStep1Fraction) && (wdgID != kADC_SelfTestWdgThresholdForAlgCStepx)) + if ((wdgID != kADC_SelfTestWdgThresholdForAlgCStepx) + #if(ADC_GROUP_COUNTS==2U) + &&(wdgID != kADC_SelfTestWdgThresholdForAlgSStep1Fraction) + #endif /* ADC_GROUP_COUNTS */ + ) { STAWR_IO(base, wdgID) |= ADC_STAWR_AWDE_MASK; } @@ -1355,7 +1569,11 @@ static inline void ADC_EnableSelfTestWdgThreshold(ADC_Type *base, adc_self_test_ */ static inline void ADC_DisableSelfTestWdgThreshold(ADC_Type *base, adc_self_test_wdg_threshold_t wdgID) { - if ((wdgID != kADC_SelfTestWdgThresholdForAlgSStep1Fraction) && (wdgID != kADC_SelfTestWdgThresholdForAlgCStepx)) + if ((wdgID != kADC_SelfTestWdgThresholdForAlgCStepx) + #if(ADC_GROUP_COUNTS==2U) + &&(wdgID != kADC_SelfTestWdgThresholdForAlgSStep1Fraction) + #endif /* ADC_GROUP_COUNTS */ + ) { STAWR_IO(base, wdgID) &= ~ADC_STAWR_AWDE_MASK; } @@ -1455,12 +1673,18 @@ static inline uint16_t ADC_GetSelfTestChannelConvFailedData(ADC_Type *base, adc_ case kADC_SelfTestWdgThresholdForAlgSStep0: data = (uint16_t)((base->STSR3 & ADC_STSR3_DATA0_MASK) >> ADC_STSR3_DATA0_SHIFT); break; +#if(ADC_GROUP_COUNTS==2U) case kADC_SelfTestWdgThresholdForAlgSStep1Integer: data = (uint16_t)((base->STSR2 & ADC_STSR2_DATA0_MASK) >> ADC_STSR2_DATA0_SHIFT); break; case kADC_SelfTestWdgThresholdForAlgSStep1Fraction: data = (uint16_t)((base->STSR2 & ADC_STSR2_DATA1_MASK) >> ADC_STSR2_DATA1_SHIFT); break; +#else /* ADC_GROUP_COUNTS==3U */ + case kADC_SelfTestWdgThresholdForAlgSStep1: + data = (uint16_t)((base->STSR2 & ADC_STSR2_DATA0_MASK) >> ADC_STSR2_DATA0_SHIFT); + break; +#endif /* ADC_GROUP_COUNTS */ case kADC_SelfTestWdgThresholdForAlgSStep2: data = (uint16_t)((base->STSR3 & ADC_STSR3_DATA1_MASK) >> ADC_STSR3_DATA1_SHIFT); break; @@ -1566,6 +1790,7 @@ bool ADC_GetChannelConvResult(ADC_Type *base, adc_conv_result_t *result, uint8_t */ bool ADC_GetSelfTestChannelConvData(ADC_Type *base, adc_self_test_conv_result_t *result); +#if !(defined(FSL_FEATURE_ADC_HAS_STDR2) && (FSL_FEATURE_ADC_HAS_STDR2==0U)) /*! * @brief This function is used to get the test channel converted data when algorithm S step 1 executes. * @@ -1579,6 +1804,7 @@ bool ADC_GetSelfTestChannelConvData(ADC_Type *base, adc_self_test_conv_result_t * - \b false Obtaining the self-test channel conversion result failed. */ bool ADC_GetSelfTestChannelConvDataForAlgSStep1(ADC_Type *base, adc_self_test_conv_result_t *result); +#endif /* FSL_FEATURE_ADC_HAS_STDR2 */ /*! * @} */