diff --git a/dts/nxp/mcx/MCXA344VFM-pinctrl.h b/dts/nxp/mcx/MCXA344VFM-pinctrl.h
new file mode 100644
index 0000000000..1c9db15cba
--- /dev/null
+++ b/dts/nxp/mcx/MCXA344VFM-pinctrl.h
@@ -0,0 +1,242 @@
+/*
+ * NOTE: Autogenerated file by gen_soc_headers.py
+ * for MCXA344VFM/signal_configuration.xml
+ *
+ * 
+ */
+
+#ifndef _ZEPHYR_DTS_BINDING_MCXA344VFM_
+#define _ZEPHYR_DTS_BINDING_MCXA344VFM_
+
+#define A15X_MUX(port, pin, mux)		\
+	(((((port) - '0') & 0xF) << 28) |	\
+	(((pin) & 0x3F) << 22) |		\
+	(((mux) & 0xF) << 8))
+
+#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */
+#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */
+#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */
+#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */
+#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */
+#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */
+#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */
+#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */
+#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */
+#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */
+#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */
+#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */
+#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */
+#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */
+#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */
+#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */
+#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */
+#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */
+#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */
+#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */
+#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */
+#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */
+#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */
+#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */
+#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */
+#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */
+#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */
+#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */
+#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */
+#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */
+#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */
+#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */
+#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */
+#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */
+#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */
+#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */
+#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */
+#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */
+#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */
+#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */
+#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */
+#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */
+#define CMP2_IN3_P1_2 A15X_MUX('1',2,0) /* PT1_2 */
+#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */
+#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */
+#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */
+#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */
+#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */
+#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */
+#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */
+#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */
+#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */
+#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */
+#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */
+#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */
+#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */
+#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */
+#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */
+#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */
+#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */
+#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */
+#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */
+#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */
+#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */
+#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */
+#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */
+#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */
+#define SMARTDMA_PIO4_P1_8 A15X_MUX('1',8,7) /* PT1_8 */
+#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */
+#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */
+#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */
+#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */
+#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */
+#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */
+#define SMARTDMA_PIO5_P1_9 A15X_MUX('1',9,7) /* PT1_9 */
+#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */
+#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */
+#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */
+#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */
+#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */
+#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */
+#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */
+#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */
+#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */
+#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */
+#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */
+#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */
+#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */
+#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define CMP2_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define CMP1_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */
+#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */
+#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */
+#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */
+#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */
+#define SMARTDMA_PIO26_P2_2 A15X_MUX('2',2,7) /* PT2_2 */
+#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define ADC0_A3_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */
+#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */
+#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */
+#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */
+#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */
+#define SMARTDMA_PIO27_P2_3 A15X_MUX('2',3,7) /* PT2_3 */
+#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */
+#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */
+#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */
+#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */
+#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */
+#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */
+#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */
+#define SMARTDMA_PIO31_P2_7 A15X_MUX('2',7,7) /* PT2_7 */
+#define OPAMP0_INP_P2_12 A15X_MUX('2',12,0) /* PT2_12 */
+#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */
+#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */
+#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */
+#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */
+#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */
+#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */
+#define SMARTDMA_PIO16_P2_12 A15X_MUX('2',12,7) /* PT2_12 */
+#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */
+#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */
+#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */
+#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */
+#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */
+#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */
+#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */
+#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */
+#define SMARTDMA_PIO17_P2_13 A15X_MUX('2',13,7) /* PT2_13 */
+#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */
+#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define WUU0_IN21_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define CMP0_INP4_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */
+#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */
+#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */
+#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */
+#define SMARTDMA_PIO18_P2_15 A15X_MUX('2',15,7) /* PT2_15 */
+#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */
+#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */
+#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */
+#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */
+#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */
+#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */
+#define SMARTDMA_PIO20_P2_17 A15X_MUX('2',17,7) /* PT2_17 */
+#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */
+#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */
+#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */
+#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */
+#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */
+#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */
+#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */
+#define SMARTDMA_PIO0_P3_0 A15X_MUX('3',0,10) /* PT3_0 */
+#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */
+#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */
+#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */
+#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */
+#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */
+#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */
+#define SMARTDMA_PIO1_P3_1 A15X_MUX('3',1,10) /* PT3_1 */
+#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */
+#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */
+#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */
+#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */
+#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */
+#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */
+#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */
+#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */
+#define SMARTDMA_PIO8_P3_8 A15X_MUX('3',8,10) /* PT3_8 */
+#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */
+#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */
+#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */
+#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */
+#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */
+#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */
+#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */
+#define SMARTDMA_PIO9_P3_9 A15X_MUX('3',9,10) /* PT3_9 */
+#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */
+#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */
+#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */
+#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */
+#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */
+#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */
+#define SMARTDMA_PIO10_P3_10 A15X_MUX('3',10,10) /* PT3_10 */
+#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */
+#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */
+#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */
+#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */
+#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */
+#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */
+#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */
+#define SMARTDMA_PIO11_P3_11 A15X_MUX('3',11,10) /* PT3_11 */
+#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */
+#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */
+#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */
+#define LPI2C1_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */
+#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */
+#define PWM1_A3_P3_27 A15X_MUX('3',27,7) /* PT3_27 */
+#define SMARTDMA_PIO27_P3_27 A15X_MUX('3',27,10) /* PT3_27 */
+#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */
+#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */
+#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */
+#define LPI2C1_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */
+#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */
+#define PWM1_B3_P3_28 A15X_MUX('3',28,7) /* PT3_28 */
+#define SMARTDMA_PIO28_P3_28 A15X_MUX('3',28,10) /* PT3_28 */
+#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */
+#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */
+#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */
+#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */
+#define LPI2C1_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */
+#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */
+#define SMARTDMA_PIO29_P3_29 A15X_MUX('3',29,10) /* PT3_29 */
+#endif
diff --git a/dts/nxp/mcx/MCXA344VLF-pinctrl.h b/dts/nxp/mcx/MCXA344VLF-pinctrl.h
new file mode 100644
index 0000000000..441b63e8a1
--- /dev/null
+++ b/dts/nxp/mcx/MCXA344VLF-pinctrl.h
@@ -0,0 +1,333 @@
+/*
+ * NOTE: Autogenerated file by gen_soc_headers.py
+ * for MCXA344VLF/signal_configuration.xml
+ *
+ * 
+ */
+
+#ifndef _ZEPHYR_DTS_BINDING_MCXA344VLF_
+#define _ZEPHYR_DTS_BINDING_MCXA344VLF_
+
+#define A15X_MUX(port, pin, mux)		\
+	(((((port) - '0') & 0xF) << 28) |	\
+	(((pin) & 0x3F) << 22) |		\
+	(((mux) & 0xF) << 8))
+
+#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */
+#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */
+#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */
+#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */
+#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */
+#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */
+#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */
+#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */
+#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */
+#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */
+#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */
+#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */
+#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */
+#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */
+#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */
+#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */
+#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */
+#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */
+#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */
+#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */
+#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */
+#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */
+#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */
+#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */
+#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */
+#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */
+#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */
+#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */
+#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */
+#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */
+#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */
+#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */
+#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */
+#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */
+#define SMARTDMA_PIO2_P0_6 A15X_MUX('0',6,7) /* PT0_6 */
+#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */
+#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */
+#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */
+#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */
+#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */
+#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */
+#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */
+#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */
+#define SMARTDMA_PIO6_P0_16 A15X_MUX('0',16,7) /* PT0_16 */
+#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */
+#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */
+#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */
+#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */
+#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */
+#define SMARTDMA_PIO7_P0_17 A15X_MUX('0',17,7) /* PT0_17 */
+#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */
+#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */
+#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */
+#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */
+#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */
+#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */
+#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */
+#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */
+#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */
+#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */
+#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */
+#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */
+#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */
+#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */
+#define CMP2_IN3_P1_2 A15X_MUX('1',2,0) /* PT1_2 */
+#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */
+#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */
+#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */
+#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */
+#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */
+#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */
+#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */
+#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */
+#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */
+#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */
+#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */
+#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */
+#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */
+#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */
+#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */
+#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */
+#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */
+#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */
+#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */
+#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */
+#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */
+#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */
+#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */
+#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */
+#define SMARTDMA_PIO4_P1_8 A15X_MUX('1',8,7) /* PT1_8 */
+#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */
+#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */
+#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */
+#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */
+#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */
+#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */
+#define SMARTDMA_PIO5_P1_9 A15X_MUX('1',9,7) /* PT1_9 */
+#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */
+#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */
+#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */
+#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */
+#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */
+#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */
+#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */
+#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */
+#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */
+#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */
+#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */
+#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */
+#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */
+#define OPAMP2_INP_P2_0 A15X_MUX('2',0,0) /* PT2_0 */
+#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */
+#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */
+#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */
+#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */
+#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */
+#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */
+#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */
+#define SMARTDMA_PIO24_P2_0 A15X_MUX('2',0,7) /* PT2_0 */
+#define OPAMP2_INN_P2_1 A15X_MUX('2',1,0) /* PT2_1 */
+#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */
+#define ADC1_A0_P2_1 A15X_MUX('2',1,0) /* PT2_1 */
+#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */
+#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */
+#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */
+#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */
+#define SMARTDMA_PIO25_P2_1 A15X_MUX('2',1,7) /* PT2_1 */
+#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define CMP2_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define CMP1_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */
+#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */
+#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */
+#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */
+#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */
+#define SMARTDMA_PIO26_P2_2 A15X_MUX('2',2,7) /* PT2_2 */
+#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define ADC0_A3_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */
+#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */
+#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */
+#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */
+#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */
+#define SMARTDMA_PIO27_P2_3 A15X_MUX('2',3,7) /* PT2_3 */
+#define CMP2_INP4_P2_6 A15X_MUX('2',6,0) /* PT2_6 */
+#define OPAMP2_OUT_P2_6 A15X_MUX('2',6,0) /* PT2_6 */
+#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */
+#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */
+#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */
+#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */
+#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */
+#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */
+#define SMARTDMA_PIO30_P2_6 A15X_MUX('2',6,7) /* PT2_6 */
+#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */
+#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */
+#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */
+#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */
+#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */
+#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */
+#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */
+#define SMARTDMA_PIO31_P2_7 A15X_MUX('2',7,7) /* PT2_7 */
+#define OPAMP0_INP_P2_12 A15X_MUX('2',12,0) /* PT2_12 */
+#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */
+#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */
+#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */
+#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */
+#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */
+#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */
+#define SMARTDMA_PIO16_P2_12 A15X_MUX('2',12,7) /* PT2_12 */
+#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */
+#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */
+#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */
+#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */
+#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */
+#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */
+#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */
+#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */
+#define SMARTDMA_PIO17_P2_13 A15X_MUX('2',13,7) /* PT2_13 */
+#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */
+#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define WUU0_IN21_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define CMP0_INP4_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */
+#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */
+#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */
+#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */
+#define SMARTDMA_PIO18_P2_15 A15X_MUX('2',15,7) /* PT2_15 */
+#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */
+#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */
+#define OPAMP1_INP_P2_16 A15X_MUX('2',16,0) /* PT2_16 */
+#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */
+#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */
+#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */
+#define SMARTDMA_PIO19_P2_16 A15X_MUX('2',16,7) /* PT2_16 */
+#define OPAMP1_INN_P2_17 A15X_MUX('2',17,0) /* PT2_17 */
+#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */
+#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */
+#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */
+#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */
+#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */
+#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */
+#define SMARTDMA_PIO20_P2_17 A15X_MUX('2',17,7) /* PT2_17 */
+#define P2_19 A15X_MUX('2',19,0) /* PT2_19 */
+#define OPAMP1_OUT_P2_19 A15X_MUX('2',19,0) /* PT2_19 */
+#define ADC1_A2_P2_19 A15X_MUX('2',19,0) /* PT2_19 */
+#define CMP1_INP4_P2_19 A15X_MUX('2',19,0) /* PT2_19 */
+#define TRIG_OUT5_P2_19 A15X_MUX('2',19,1) /* PT2_19 */
+#define SMARTDMA_PIO21_P2_19 A15X_MUX('2',19,7) /* PT2_19 */
+#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */
+#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */
+#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */
+#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */
+#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */
+#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */
+#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */
+#define SMARTDMA_PIO0_P3_0 A15X_MUX('3',0,10) /* PT3_0 */
+#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */
+#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */
+#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */
+#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */
+#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */
+#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */
+#define SMARTDMA_PIO1_P3_1 A15X_MUX('3',1,10) /* PT3_1 */
+#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */
+#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */
+#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */
+#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */
+#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */
+#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */
+#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */
+#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */
+#define SMARTDMA_PIO8_P3_8 A15X_MUX('3',8,10) /* PT3_8 */
+#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */
+#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */
+#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */
+#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */
+#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */
+#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */
+#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */
+#define SMARTDMA_PIO9_P3_9 A15X_MUX('3',9,10) /* PT3_9 */
+#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */
+#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */
+#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */
+#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */
+#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */
+#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */
+#define SMARTDMA_PIO10_P3_10 A15X_MUX('3',10,10) /* PT3_10 */
+#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */
+#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */
+#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */
+#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */
+#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */
+#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */
+#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */
+#define SMARTDMA_PIO11_P3_11 A15X_MUX('3',11,10) /* PT3_11 */
+#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */
+#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */
+#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */
+#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */
+#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */
+#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */
+#define SMARTDMA_PIO12_P3_12 A15X_MUX('3',12,10) /* PT3_12 */
+#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */
+#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */
+#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */
+#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */
+#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */
+#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */
+#define SMARTDMA_PIO13_P3_13 A15X_MUX('3',13,10) /* PT3_13 */
+#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */
+#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */
+#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */
+#define LPI2C1_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */
+#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */
+#define PWM1_A3_P3_27 A15X_MUX('3',27,7) /* PT3_27 */
+#define SMARTDMA_PIO27_P3_27 A15X_MUX('3',27,10) /* PT3_27 */
+#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */
+#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */
+#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */
+#define LPI2C1_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */
+#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */
+#define PWM1_B3_P3_28 A15X_MUX('3',28,7) /* PT3_28 */
+#define SMARTDMA_PIO28_P3_28 A15X_MUX('3',28,10) /* PT3_28 */
+#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */
+#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */
+#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */
+#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */
+#define LPI2C1_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */
+#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */
+#define SMARTDMA_PIO29_P3_29 A15X_MUX('3',29,10) /* PT3_29 */
+#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */
+#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */
+#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */
+#define LPI2C1_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */
+#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */
+#define PWM1_A0_P3_30 A15X_MUX('3',30,7) /* PT3_30 */
+#define SMARTDMA_PIO30_P3_30 A15X_MUX('3',30,10) /* PT3_30 */
+#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */
+#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */
+#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */
+#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */
+#define LPI2C1_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */
+#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */
+#define PWM1_B0_P3_31 A15X_MUX('3',31,7) /* PT3_31 */
+#define SMARTDMA_PIO31_P3_31 A15X_MUX('3',31,10) /* PT3_31 */
+#endif
diff --git a/dts/nxp/mcx/MCXA344VLH-pinctrl.h b/dts/nxp/mcx/MCXA344VLH-pinctrl.h
new file mode 100644
index 0000000000..8ea94c63da
--- /dev/null
+++ b/dts/nxp/mcx/MCXA344VLH-pinctrl.h
@@ -0,0 +1,441 @@
+/*
+ * NOTE: Autogenerated file by gen_soc_headers.py
+ * for MCXA344VLH/signal_configuration.xml
+ *
+ * 
+ */
+
+#ifndef _ZEPHYR_DTS_BINDING_MCXA344VLH_
+#define _ZEPHYR_DTS_BINDING_MCXA344VLH_
+
+#define A15X_MUX(port, pin, mux)		\
+	(((((port) - '0') & 0xF) << 28) |	\
+	(((pin) & 0x3F) << 22) |		\
+	(((mux) & 0xF) << 8))
+
+#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */
+#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */
+#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */
+#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */
+#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */
+#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */
+#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */
+#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */
+#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */
+#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */
+#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */
+#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */
+#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */
+#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */
+#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */
+#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */
+#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */
+#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */
+#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */
+#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */
+#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */
+#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */
+#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */
+#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */
+#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */
+#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */
+#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */
+#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */
+#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */
+#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */
+#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */
+#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */
+#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */
+#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */
+#define SMARTDMA_PIO2_P0_6 A15X_MUX('0',6,7) /* PT0_6 */
+#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */
+#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */
+#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */
+#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */
+#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */
+#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */
+#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */
+#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */
+#define SMARTDMA_PIO6_P0_16 A15X_MUX('0',16,7) /* PT0_16 */
+#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */
+#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */
+#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */
+#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */
+#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */
+#define SMARTDMA_PIO7_P0_17 A15X_MUX('0',17,7) /* PT0_17 */
+#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */
+#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */
+#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */
+#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */
+#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */
+#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */
+#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */
+#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */
+#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */
+#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */
+#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */
+#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */
+#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */
+#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */
+#define CMP2_IN3_P1_2 A15X_MUX('1',2,0) /* PT1_2 */
+#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */
+#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */
+#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */
+#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */
+#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */
+#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */
+#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */
+#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */
+#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */
+#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */
+#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */
+#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */
+#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */
+#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */
+#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */
+#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */
+#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */
+#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */
+#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */
+#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */
+#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */
+#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */
+#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */
+#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */
+#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */
+#define SMARTDMA_PIO0_P1_4 A15X_MUX('1',4,7) /* PT1_4 */
+#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */
+#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */
+#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */
+#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */
+#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */
+#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */
+#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */
+#define SMARTDMA_PIO1_P1_5 A15X_MUX('1',5,7) /* PT1_5 */
+#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */
+#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */
+#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */
+#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */
+#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */
+#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */
+#define SMARTDMA_PIO2_P1_6 A15X_MUX('1',6,7) /* PT1_6 */
+#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */
+#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */
+#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */
+#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */
+#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */
+#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */
+#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */
+#define SMARTDMA_PIO3_P1_7 A15X_MUX('1',7,7) /* PT1_7 */
+#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */
+#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */
+#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */
+#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */
+#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */
+#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */
+#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */
+#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */
+#define SMARTDMA_PIO4_P1_8 A15X_MUX('1',8,7) /* PT1_8 */
+#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */
+#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */
+#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */
+#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */
+#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */
+#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */
+#define SMARTDMA_PIO5_P1_9 A15X_MUX('1',9,7) /* PT1_9 */
+#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */
+#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */
+#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */
+#define LPI2C0_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */
+#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */
+#define SMARTDMA_PIO6_P1_10 A15X_MUX('1',10,7) /* PT1_10 */
+#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */
+#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */
+#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */
+#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */
+#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */
+#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */
+#define LPI2C0_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */
+#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */
+#define SMARTDMA_PIO7_P1_11 A15X_MUX('1',11,7) /* PT1_11 */
+#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */
+#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */
+#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */
+#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */
+#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */
+#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */
+#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */
+#define SMARTDMA_PIO8_P1_12 A15X_MUX('1',12,7) /* PT1_12 */
+#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */
+#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */
+#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */
+#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */
+#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */
+#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */
+#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */
+#define SMARTDMA_PIO9_P1_13 A15X_MUX('1',13,7) /* PT1_13 */
+#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */
+#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */
+#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */
+#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */
+#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */
+#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */
+#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */
+#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */
+#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */
+#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */
+#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */
+#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */
+#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */
+#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */
+#define OPAMP2_INP_P2_0 A15X_MUX('2',0,0) /* PT2_0 */
+#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */
+#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */
+#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */
+#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */
+#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */
+#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */
+#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */
+#define SMARTDMA_PIO24_P2_0 A15X_MUX('2',0,7) /* PT2_0 */
+#define OPAMP2_INN_P2_1 A15X_MUX('2',1,0) /* PT2_1 */
+#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */
+#define ADC1_A0_P2_1 A15X_MUX('2',1,0) /* PT2_1 */
+#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */
+#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */
+#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */
+#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */
+#define SMARTDMA_PIO25_P2_1 A15X_MUX('2',1,7) /* PT2_1 */
+#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define CMP2_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define CMP1_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */
+#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */
+#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */
+#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */
+#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */
+#define SMARTDMA_PIO26_P2_2 A15X_MUX('2',2,7) /* PT2_2 */
+#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define ADC0_A3_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */
+#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */
+#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */
+#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */
+#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */
+#define SMARTDMA_PIO27_P2_3 A15X_MUX('2',3,7) /* PT2_3 */
+#define CMP2_IN0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */
+#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */
+#define ADC0_A1_P2_4 A15X_MUX('2',4,0) /* PT2_4 */
+#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */
+#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */
+#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */
+#define SMARTDMA_PIO28_P2_4 A15X_MUX('2',4,7) /* PT2_4 */
+#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */
+#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */
+#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */
+#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */
+#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */
+#define SMARTDMA_PIO29_P2_5 A15X_MUX('2',5,7) /* PT2_5 */
+#define CMP2_INP4_P2_6 A15X_MUX('2',6,0) /* PT2_6 */
+#define OPAMP2_OUT_P2_6 A15X_MUX('2',6,0) /* PT2_6 */
+#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */
+#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */
+#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */
+#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */
+#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */
+#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */
+#define SMARTDMA_PIO30_P2_6 A15X_MUX('2',6,7) /* PT2_6 */
+#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */
+#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */
+#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */
+#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */
+#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */
+#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */
+#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */
+#define SMARTDMA_PIO31_P2_7 A15X_MUX('2',7,7) /* PT2_7 */
+#define OPAMP0_INP_P2_12 A15X_MUX('2',12,0) /* PT2_12 */
+#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */
+#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */
+#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */
+#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */
+#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */
+#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */
+#define SMARTDMA_PIO16_P2_12 A15X_MUX('2',12,7) /* PT2_12 */
+#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */
+#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */
+#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */
+#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */
+#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */
+#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */
+#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */
+#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */
+#define SMARTDMA_PIO17_P2_13 A15X_MUX('2',13,7) /* PT2_13 */
+#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */
+#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define WUU0_IN21_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define CMP0_INP4_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */
+#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */
+#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */
+#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */
+#define SMARTDMA_PIO18_P2_15 A15X_MUX('2',15,7) /* PT2_15 */
+#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */
+#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */
+#define OPAMP1_INP_P2_16 A15X_MUX('2',16,0) /* PT2_16 */
+#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */
+#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */
+#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */
+#define SMARTDMA_PIO19_P2_16 A15X_MUX('2',16,7) /* PT2_16 */
+#define OPAMP1_INN_P2_17 A15X_MUX('2',17,0) /* PT2_17 */
+#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */
+#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */
+#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */
+#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */
+#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */
+#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */
+#define SMARTDMA_PIO20_P2_17 A15X_MUX('2',17,7) /* PT2_17 */
+#define P2_19 A15X_MUX('2',19,0) /* PT2_19 */
+#define OPAMP1_OUT_P2_19 A15X_MUX('2',19,0) /* PT2_19 */
+#define ADC1_A2_P2_19 A15X_MUX('2',19,0) /* PT2_19 */
+#define CMP1_INP4_P2_19 A15X_MUX('2',19,0) /* PT2_19 */
+#define TRIG_OUT5_P2_19 A15X_MUX('2',19,1) /* PT2_19 */
+#define SMARTDMA_PIO21_P2_19 A15X_MUX('2',19,7) /* PT2_19 */
+#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */
+#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */
+#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */
+#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */
+#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */
+#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */
+#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */
+#define SMARTDMA_PIO0_P3_0 A15X_MUX('3',0,10) /* PT3_0 */
+#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */
+#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */
+#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */
+#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */
+#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */
+#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */
+#define SMARTDMA_PIO1_P3_1 A15X_MUX('3',1,10) /* PT3_1 */
+#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */
+#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */
+#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */
+#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */
+#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */
+#define PWM0_A3_P3_6 A15X_MUX('3',6,5) /* PT3_6 */
+#define PWM1_A0_P3_6 A15X_MUX('3',6,7) /* PT3_6 */
+#define SMARTDMA_PIO6_P3_6 A15X_MUX('3',6,10) /* PT3_6 */
+#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */
+#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */
+#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */
+#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */
+#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */
+#define PWM0_B3_P3_7 A15X_MUX('3',7,5) /* PT3_7 */
+#define PWM1_B0_P3_7 A15X_MUX('3',7,7) /* PT3_7 */
+#define SMARTDMA_PIO7_P3_7 A15X_MUX('3',7,10) /* PT3_7 */
+#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */
+#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */
+#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */
+#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */
+#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */
+#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */
+#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */
+#define SMARTDMA_PIO8_P3_8 A15X_MUX('3',8,10) /* PT3_8 */
+#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */
+#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */
+#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */
+#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */
+#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */
+#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */
+#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */
+#define SMARTDMA_PIO9_P3_9 A15X_MUX('3',9,10) /* PT3_9 */
+#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */
+#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */
+#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */
+#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */
+#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */
+#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */
+#define SMARTDMA_PIO10_P3_10 A15X_MUX('3',10,10) /* PT3_10 */
+#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */
+#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */
+#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */
+#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */
+#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */
+#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */
+#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */
+#define SMARTDMA_PIO11_P3_11 A15X_MUX('3',11,10) /* PT3_11 */
+#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */
+#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */
+#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */
+#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */
+#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */
+#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */
+#define SMARTDMA_PIO12_P3_12 A15X_MUX('3',12,10) /* PT3_12 */
+#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */
+#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */
+#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */
+#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */
+#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */
+#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */
+#define SMARTDMA_PIO13_P3_13 A15X_MUX('3',13,10) /* PT3_13 */
+#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */
+#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */
+#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */
+#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */
+#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */
+#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */
+#define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */
+#define SMARTDMA_PIO14_P3_14 A15X_MUX('3',14,10) /* PT3_14 */
+#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */
+#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */
+#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */
+#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */
+#define PWM0_X3_P3_15 A15X_MUX('3',15,5) /* PT3_15 */
+#define PWM1_B1_P3_15 A15X_MUX('3',15,7) /* PT3_15 */
+#define SMARTDMA_PIO15_P3_15 A15X_MUX('3',15,10) /* PT3_15 */
+#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */
+#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */
+#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */
+#define LPI2C1_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */
+#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */
+#define PWM1_A3_P3_27 A15X_MUX('3',27,7) /* PT3_27 */
+#define SMARTDMA_PIO27_P3_27 A15X_MUX('3',27,10) /* PT3_27 */
+#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */
+#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */
+#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */
+#define LPI2C1_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */
+#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */
+#define PWM1_B3_P3_28 A15X_MUX('3',28,7) /* PT3_28 */
+#define SMARTDMA_PIO28_P3_28 A15X_MUX('3',28,10) /* PT3_28 */
+#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */
+#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */
+#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */
+#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */
+#define LPI2C1_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */
+#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */
+#define SMARTDMA_PIO29_P3_29 A15X_MUX('3',29,10) /* PT3_29 */
+#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */
+#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */
+#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */
+#define LPI2C1_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */
+#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */
+#define PWM1_A0_P3_30 A15X_MUX('3',30,7) /* PT3_30 */
+#define SMARTDMA_PIO30_P3_30 A15X_MUX('3',30,10) /* PT3_30 */
+#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */
+#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */
+#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */
+#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */
+#define LPI2C1_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */
+#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */
+#define PWM1_B0_P3_31 A15X_MUX('3',31,7) /* PT3_31 */
+#define SMARTDMA_PIO31_P3_31 A15X_MUX('3',31,10) /* PT3_31 */
+#endif
diff --git a/dts/nxp/mcx/MCXA344VLL-pinctrl.h b/dts/nxp/mcx/MCXA344VLL-pinctrl.h
new file mode 100644
index 0000000000..10f5311936
--- /dev/null
+++ b/dts/nxp/mcx/MCXA344VLL-pinctrl.h
@@ -0,0 +1,596 @@
+/*
+ * NOTE: Autogenerated file by gen_soc_headers.py
+ * for MCXA344VLL/signal_configuration.xml
+ *
+ * 
+ */
+
+#ifndef _ZEPHYR_DTS_BINDING_MCXA344VLL_
+#define _ZEPHYR_DTS_BINDING_MCXA344VLL_
+
+#define A15X_MUX(port, pin, mux)		\
+	(((((port) - '0') & 0xF) << 28) |	\
+	(((pin) & 0x3F) << 22) |		\
+	(((mux) & 0xF) << 8))
+
+#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */
+#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */
+#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */
+#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */
+#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */
+#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */
+#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */
+#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */
+#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */
+#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */
+#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */
+#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */
+#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */
+#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */
+#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */
+#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */
+#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */
+#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */
+#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */
+#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */
+#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */
+#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */
+#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */
+#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */
+#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */
+#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */
+#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */
+#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */
+#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */
+#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */
+#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */
+#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */
+#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */
+#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */
+#define SMARTDMA_PIO2_P0_6 A15X_MUX('0',6,7) /* PT0_6 */
+#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */
+#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */
+#define P0_14 A15X_MUX('0',14,0) /* PT0_14 */
+#define CT_INP2_P0_14 A15X_MUX('0',14,4) /* PT0_14 */
+#define UTICK_CAP0_P0_14 A15X_MUX('0',14,5) /* PT0_14 */
+#define SMARTDMA_PIO4_P0_14 A15X_MUX('0',14,7) /* PT0_14 */
+#define P0_15 A15X_MUX('0',15,0) /* PT0_15 */
+#define CT_INP3_P0_15 A15X_MUX('0',15,4) /* PT0_15 */
+#define UTICK_CAP1_P0_15 A15X_MUX('0',15,5) /* PT0_15 */
+#define SMARTDMA_PIO5_P0_15 A15X_MUX('0',15,7) /* PT0_15 */
+#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */
+#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */
+#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */
+#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */
+#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */
+#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */
+#define SMARTDMA_PIO6_P0_16 A15X_MUX('0',16,7) /* PT0_16 */
+#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */
+#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */
+#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */
+#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */
+#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */
+#define SMARTDMA_PIO7_P0_17 A15X_MUX('0',17,7) /* PT0_17 */
+#define ADC0_A8_P0_18 A15X_MUX('0',18,0) /* PT0_18 */
+#define P0_18 A15X_MUX('0',18,0) /* PT0_18 */
+#define LPI2C0_SCLS_P0_18 A15X_MUX('0',18,2) /* PT0_18 */
+#define CT0_MAT2_P0_18 A15X_MUX('0',18,4) /* PT0_18 */
+#define SMARTDMA_PIO8_P0_18 A15X_MUX('0',18,7) /* PT0_18 */
+#define CMP0_OUT_P0_18 A15X_MUX('0',18,8) /* PT0_18 */
+#define P0_19 A15X_MUX('0',19,0) /* PT0_19 */
+#define ADC0_A9_P0_19 A15X_MUX('0',19,0) /* PT0_19 */
+#define WUU0_IN3_P0_19 A15X_MUX('0',19,0) /* PT0_19 */
+#define LPI2C0_SDAS_P0_19 A15X_MUX('0',19,2) /* PT0_19 */
+#define CT0_MAT3_P0_19 A15X_MUX('0',19,4) /* PT0_19 */
+#define SMARTDMA_PIO9_P0_19 A15X_MUX('0',19,7) /* PT0_19 */
+#define CMP1_OUT_P0_19 A15X_MUX('0',19,8) /* PT0_19 */
+#define P0_20 A15X_MUX('0',20,0) /* PT0_20 */
+#define ADC0_A10_P0_20 A15X_MUX('0',20,0) /* PT0_20 */
+#define WUU0_IN4_P0_20 A15X_MUX('0',20,0) /* PT0_20 */
+#define LPUART0_RXD_P0_20 A15X_MUX('0',20,3) /* PT0_20 */
+#define CT_INP0_P0_20 A15X_MUX('0',20,4) /* PT0_20 */
+#define SMARTDMA_PIO10_P0_20 A15X_MUX('0',20,7) /* PT0_20 */
+#define CMP2_OUT_P0_20 A15X_MUX('0',20,8) /* PT0_20 */
+#define P0_21 A15X_MUX('0',21,0) /* PT0_21 */
+#define ADC0_A11_P0_21 A15X_MUX('0',21,0) /* PT0_21 */
+#define LPUART0_TXD_P0_21 A15X_MUX('0',21,3) /* PT0_21 */
+#define CT_INP1_P0_21 A15X_MUX('0',21,4) /* PT0_21 */
+#define SMARTDMA_PIO11_P0_21 A15X_MUX('0',21,7) /* PT0_21 */
+#define ADC0_A12_P0_22 A15X_MUX('0',22,0) /* PT0_22 */
+#define P0_22 A15X_MUX('0',22,0) /* PT0_22 */
+#define LPUART0_RTS_B_P0_22 A15X_MUX('0',22,3) /* PT0_22 */
+#define CT_INP2_P0_22 A15X_MUX('0',22,4) /* PT0_22 */
+#define CT0_MAT0_P0_22 A15X_MUX('0',22,5) /* PT0_22 */
+#define SMARTDMA_PIO12_P0_22 A15X_MUX('0',22,7) /* PT0_22 */
+#define P0_23 A15X_MUX('0',23,0) /* PT0_23 */
+#define ADC0_A13_P0_23 A15X_MUX('0',23,0) /* PT0_23 */
+#define CMP2_IN2_P0_23 A15X_MUX('0',23,0) /* PT0_23 */
+#define WUU0_IN5_P0_23 A15X_MUX('0',23,0) /* PT0_23 */
+#define LPUART0_CTS_B_P0_23 A15X_MUX('0',23,3) /* PT0_23 */
+#define CT_INP3_P0_23 A15X_MUX('0',23,4) /* PT0_23 */
+#define CT0_MAT1_P0_23 A15X_MUX('0',23,5) /* PT0_23 */
+#define SMARTDMA_PIO13_P0_23 A15X_MUX('0',23,7) /* PT0_23 */
+#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
+#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */
+#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */
+#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */
+#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */
+#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */
+#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */
+#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */
+#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */
+#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */
+#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */
+#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */
+#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */
+#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */
+#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */
+#define CMP2_IN3_P1_2 A15X_MUX('1',2,0) /* PT1_2 */
+#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */
+#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */
+#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */
+#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */
+#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */
+#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */
+#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */
+#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */
+#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */
+#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */
+#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */
+#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */
+#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */
+#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */
+#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */
+#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */
+#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */
+#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */
+#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */
+#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */
+#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */
+#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */
+#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */
+#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */
+#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */
+#define SMARTDMA_PIO0_P1_4 A15X_MUX('1',4,7) /* PT1_4 */
+#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */
+#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */
+#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */
+#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */
+#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */
+#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */
+#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */
+#define SMARTDMA_PIO1_P1_5 A15X_MUX('1',5,7) /* PT1_5 */
+#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */
+#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */
+#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */
+#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */
+#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */
+#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */
+#define SMARTDMA_PIO2_P1_6 A15X_MUX('1',6,7) /* PT1_6 */
+#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */
+#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */
+#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */
+#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */
+#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */
+#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */
+#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */
+#define SMARTDMA_PIO3_P1_7 A15X_MUX('1',7,7) /* PT1_7 */
+#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */
+#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */
+#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */
+#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */
+#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */
+#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */
+#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */
+#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */
+#define SMARTDMA_PIO4_P1_8 A15X_MUX('1',8,7) /* PT1_8 */
+#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */
+#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */
+#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */
+#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */
+#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */
+#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */
+#define SMARTDMA_PIO5_P1_9 A15X_MUX('1',9,7) /* PT1_9 */
+#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */
+#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */
+#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */
+#define LPI2C0_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */
+#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */
+#define SMARTDMA_PIO6_P1_10 A15X_MUX('1',10,7) /* PT1_10 */
+#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */
+#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */
+#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */
+#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */
+#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */
+#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */
+#define LPI2C0_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */
+#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */
+#define SMARTDMA_PIO7_P1_11 A15X_MUX('1',11,7) /* PT1_11 */
+#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */
+#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */
+#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */
+#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */
+#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */
+#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */
+#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */
+#define SMARTDMA_PIO8_P1_12 A15X_MUX('1',12,7) /* PT1_12 */
+#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */
+#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */
+#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */
+#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */
+#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */
+#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */
+#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */
+#define SMARTDMA_PIO9_P1_13 A15X_MUX('1',13,7) /* PT1_13 */
+#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */
+#define ADC1_A12_P1_14 A15X_MUX('1',14,0) /* PT1_14 */
+#define P1_14 A15X_MUX('1',14,0) /* PT1_14 */
+#define LPI2C1_SCLS_P1_14 A15X_MUX('1',14,2) /* PT1_14 */
+#define LPUART2_RTS_B_P1_14 A15X_MUX('1',14,3) /* PT1_14 */
+#define SMARTDMA_PIO10_P1_14 A15X_MUX('1',14,7) /* PT1_14 */
+#define WUU0_IN13_P1_15 A15X_MUX('1',15,0) /* PT1_15 */
+#define ADC1_A13_P1_15 A15X_MUX('1',15,0) /* PT1_15 */
+#define P1_15 A15X_MUX('1',15,0) /* PT1_15 */
+#define LPI2C1_SDAS_P1_15 A15X_MUX('1',15,2) /* PT1_15 */
+#define LPUART2_CTS_B_P1_15 A15X_MUX('1',15,3) /* PT1_15 */
+#define SMARTDMA_PIO11_P1_15 A15X_MUX('1',15,7) /* PT1_15 */
+#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */
+#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */
+#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */
+#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */
+#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */
+#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */
+#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */
+#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */
+#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */
+#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */
+#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */
+#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */
+#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */
+#define OPAMP2_INP_P2_0 A15X_MUX('2',0,0) /* PT2_0 */
+#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */
+#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */
+#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */
+#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */
+#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */
+#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */
+#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */
+#define SMARTDMA_PIO24_P2_0 A15X_MUX('2',0,7) /* PT2_0 */
+#define OPAMP2_INN_P2_1 A15X_MUX('2',1,0) /* PT2_1 */
+#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */
+#define ADC1_A0_P2_1 A15X_MUX('2',1,0) /* PT2_1 */
+#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */
+#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */
+#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */
+#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */
+#define SMARTDMA_PIO25_P2_1 A15X_MUX('2',1,7) /* PT2_1 */
+#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define CMP2_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define CMP1_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
+#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */
+#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */
+#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */
+#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */
+#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */
+#define SMARTDMA_PIO26_P2_2 A15X_MUX('2',2,7) /* PT2_2 */
+#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define ADC0_A3_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
+#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */
+#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */
+#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */
+#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */
+#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */
+#define SMARTDMA_PIO27_P2_3 A15X_MUX('2',3,7) /* PT2_3 */
+#define CMP2_IN0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */
+#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */
+#define ADC0_A1_P2_4 A15X_MUX('2',4,0) /* PT2_4 */
+#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */
+#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */
+#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */
+#define SMARTDMA_PIO28_P2_4 A15X_MUX('2',4,7) /* PT2_4 */
+#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */
+#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */
+#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */
+#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */
+#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */
+#define SMARTDMA_PIO29_P2_5 A15X_MUX('2',5,7) /* PT2_5 */
+#define CMP2_INP4_P2_6 A15X_MUX('2',6,0) /* PT2_6 */
+#define OPAMP2_OUT_P2_6 A15X_MUX('2',6,0) /* PT2_6 */
+#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */
+#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */
+#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */
+#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */
+#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */
+#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */
+#define SMARTDMA_PIO30_P2_6 A15X_MUX('2',6,7) /* PT2_6 */
+#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */
+#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */
+#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */
+#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */
+#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */
+#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */
+#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */
+#define SMARTDMA_PIO31_P2_7 A15X_MUX('2',7,7) /* PT2_7 */
+#define P2_10 A15X_MUX('2',10,0) /* PT2_10 */
+#define TRIG_OUT5_P2_10 A15X_MUX('2',10,1) /* PT2_10 */
+#define LPUART2_TXD_P2_10 A15X_MUX('2',10,3) /* PT2_10 */
+#define SMARTDMA_PIO14_P2_10 A15X_MUX('2',10,7) /* PT2_10 */
+#define P2_11 A15X_MUX('2',11,0) /* PT2_11 */
+#define TRIG_IN4_P2_11 A15X_MUX('2',11,1) /* PT2_11 */
+#define LPUART2_RXD_P2_11 A15X_MUX('2',11,3) /* PT2_11 */
+#define SMARTDMA_PIO15_P2_11 A15X_MUX('2',11,7) /* PT2_11 */
+#define OPAMP0_INP_P2_12 A15X_MUX('2',12,0) /* PT2_12 */
+#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */
+#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */
+#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */
+#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */
+#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */
+#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */
+#define SMARTDMA_PIO16_P2_12 A15X_MUX('2',12,7) /* PT2_12 */
+#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */
+#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */
+#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */
+#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */
+#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */
+#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */
+#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */
+#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */
+#define SMARTDMA_PIO17_P2_13 A15X_MUX('2',13,7) /* PT2_13 */
+#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */
+#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define WUU0_IN21_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define CMP0_INP4_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */
+#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */
+#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */
+#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */
+#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */
+#define SMARTDMA_PIO18_P2_15 A15X_MUX('2',15,7) /* PT2_15 */
+#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */
+#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */
+#define OPAMP1_INP_P2_16 A15X_MUX('2',16,0) /* PT2_16 */
+#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */
+#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */
+#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */
+#define SMARTDMA_PIO19_P2_16 A15X_MUX('2',16,7) /* PT2_16 */
+#define OPAMP1_INN_P2_17 A15X_MUX('2',17,0) /* PT2_17 */
+#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */
+#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */
+#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */
+#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */
+#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */
+#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */
+#define SMARTDMA_PIO20_P2_17 A15X_MUX('2',17,7) /* PT2_17 */
+#define P2_19 A15X_MUX('2',19,0) /* PT2_19 */
+#define OPAMP1_OUT_P2_19 A15X_MUX('2',19,0) /* PT2_19 */
+#define ADC1_A2_P2_19 A15X_MUX('2',19,0) /* PT2_19 */
+#define CMP1_INP4_P2_19 A15X_MUX('2',19,0) /* PT2_19 */
+#define TRIG_OUT5_P2_19 A15X_MUX('2',19,1) /* PT2_19 */
+#define SMARTDMA_PIO21_P2_19 A15X_MUX('2',19,7) /* PT2_19 */
+#define P2_20 A15X_MUX('2',20,0) /* PT2_20 */
+#define TRIG_IN8_P2_20 A15X_MUX('2',20,1) /* PT2_20 */
+#define LPSPI1_PCS2_P2_20 A15X_MUX('2',20,2) /* PT2_20 */
+#define CT2_MAT0_P2_20 A15X_MUX('2',20,4) /* PT2_20 */
+#define SMARTDMA_PIO22_P2_20 A15X_MUX('2',20,7) /* PT2_20 */
+#define P2_21 A15X_MUX('2',21,0) /* PT2_21 */
+#define TRIG_IN9_P2_21 A15X_MUX('2',21,1) /* PT2_21 */
+#define LPSPI1_PCS3_P2_21 A15X_MUX('2',21,2) /* PT2_21 */
+#define CT2_MAT1_P2_21 A15X_MUX('2',21,4) /* PT2_21 */
+#define SMARTDMA_PIO23_P2_21 A15X_MUX('2',21,7) /* PT2_21 */
+#define P2_23 A15X_MUX('2',23,0) /* PT2_23 */
+#define TRIG_OUT5_P2_23 A15X_MUX('2',23,1) /* PT2_23 */
+#define CT2_MAT3_P2_23 A15X_MUX('2',23,4) /* PT2_23 */
+#define P2_24 A15X_MUX('2',24,0) /* PT2_24 */
+#define TRIG_OUT6_P2_24 A15X_MUX('2',24,1) /* PT2_24 */
+#define CT_INP8_P2_24 A15X_MUX('2',24,4) /* PT2_24 */
+#define P2_25 A15X_MUX('2',25,0) /* PT2_25 */
+#define TRIG_OUT7_P2_25 A15X_MUX('2',25,1) /* PT2_25 */
+#define CT_INP9_P2_25 A15X_MUX('2',25,4) /* PT2_25 */
+#define P2_26 A15X_MUX('2',26,0) /* PT2_26 */
+#define TRIG_IN5_P2_26 A15X_MUX('2',26,1) /* PT2_26 */
+#define CT_INP10_P2_26 A15X_MUX('2',26,4) /* PT2_26 */
+#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */
+#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */
+#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */
+#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */
+#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */
+#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */
+#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */
+#define SMARTDMA_PIO0_P3_0 A15X_MUX('3',0,10) /* PT3_0 */
+#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */
+#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */
+#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */
+#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */
+#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */
+#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */
+#define SMARTDMA_PIO1_P3_1 A15X_MUX('3',1,10) /* PT3_1 */
+#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */
+#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */
+#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */
+#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */
+#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */
+#define PWM0_A3_P3_6 A15X_MUX('3',6,5) /* PT3_6 */
+#define PWM1_A0_P3_6 A15X_MUX('3',6,7) /* PT3_6 */
+#define SMARTDMA_PIO6_P3_6 A15X_MUX('3',6,10) /* PT3_6 */
+#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */
+#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */
+#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */
+#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */
+#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */
+#define PWM0_B3_P3_7 A15X_MUX('3',7,5) /* PT3_7 */
+#define PWM1_B0_P3_7 A15X_MUX('3',7,7) /* PT3_7 */
+#define SMARTDMA_PIO7_P3_7 A15X_MUX('3',7,10) /* PT3_7 */
+#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */
+#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */
+#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */
+#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */
+#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */
+#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */
+#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */
+#define SMARTDMA_PIO8_P3_8 A15X_MUX('3',8,10) /* PT3_8 */
+#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */
+#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */
+#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */
+#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */
+#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */
+#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */
+#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */
+#define SMARTDMA_PIO9_P3_9 A15X_MUX('3',9,10) /* PT3_9 */
+#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */
+#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */
+#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */
+#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */
+#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */
+#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */
+#define SMARTDMA_PIO10_P3_10 A15X_MUX('3',10,10) /* PT3_10 */
+#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */
+#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */
+#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */
+#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */
+#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */
+#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */
+#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */
+#define SMARTDMA_PIO11_P3_11 A15X_MUX('3',11,10) /* PT3_11 */
+#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */
+#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */
+#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */
+#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */
+#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */
+#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */
+#define SMARTDMA_PIO12_P3_12 A15X_MUX('3',12,10) /* PT3_12 */
+#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */
+#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */
+#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */
+#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */
+#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */
+#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */
+#define SMARTDMA_PIO13_P3_13 A15X_MUX('3',13,10) /* PT3_13 */
+#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */
+#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */
+#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */
+#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */
+#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */
+#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */
+#define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */
+#define SMARTDMA_PIO14_P3_14 A15X_MUX('3',14,10) /* PT3_14 */
+#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */
+#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */
+#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */
+#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */
+#define PWM0_X3_P3_15 A15X_MUX('3',15,5) /* PT3_15 */
+#define PWM1_B1_P3_15 A15X_MUX('3',15,7) /* PT3_15 */
+#define SMARTDMA_PIO15_P3_15 A15X_MUX('3',15,10) /* PT3_15 */
+#define P3_16 A15X_MUX('3',16,0) /* PT3_16 */
+#define CT_INP8_P3_16 A15X_MUX('3',16,4) /* PT3_16 */
+#define PWM1_A0_P3_16 A15X_MUX('3',16,7) /* PT3_16 */
+#define SMARTDMA_PIO16_P3_16 A15X_MUX('3',16,10) /* PT3_16 */
+#define P3_17 A15X_MUX('3',17,0) /* PT3_17 */
+#define CT_INP9_P3_17 A15X_MUX('3',17,4) /* PT3_17 */
+#define PWM1_B0_P3_17 A15X_MUX('3',17,7) /* PT3_17 */
+#define SMARTDMA_PIO17_P3_17 A15X_MUX('3',17,10) /* PT3_17 */
+#define P3_18 A15X_MUX('3',18,0) /* PT3_18 */
+#define CT2_MAT0_P3_18 A15X_MUX('3',18,4) /* PT3_18 */
+#define PWM0_X0_P3_18 A15X_MUX('3',18,5) /* PT3_18 */
+#define PWM1_X0_P3_18 A15X_MUX('3',18,7) /* PT3_18 */
+#define SMARTDMA_PIO18_P3_18 A15X_MUX('3',18,10) /* PT3_18 */
+#define P3_19 A15X_MUX('3',19,0) /* PT3_19 */
+#define CT2_MAT1_P3_19 A15X_MUX('3',19,4) /* PT3_19 */
+#define PWM0_X1_P3_19 A15X_MUX('3',19,5) /* PT3_19 */
+#define PWM1_X1_P3_19 A15X_MUX('3',19,7) /* PT3_19 */
+#define SMARTDMA_PIO19_P3_19 A15X_MUX('3',19,10) /* PT3_19 */
+#define P3_20 A15X_MUX('3',20,0) /* PT3_20 */
+#define TRIG_OUT0_P3_20 A15X_MUX('3',20,1) /* PT3_20 */
+#define LPUART1_RXD_P3_20 A15X_MUX('3',20,3) /* PT3_20 */
+#define CT2_MAT2_P3_20 A15X_MUX('3',20,4) /* PT3_20 */
+#define PWM0_X2_P3_20 A15X_MUX('3',20,5) /* PT3_20 */
+#define PWM1_A3_P3_20 A15X_MUX('3',20,7) /* PT3_20 */
+#define SMARTDMA_PIO20_P3_20 A15X_MUX('3',20,10) /* PT3_20 */
+#define P3_21 A15X_MUX('3',21,0) /* PT3_21 */
+#define TRIG_OUT1_P3_21 A15X_MUX('3',21,1) /* PT3_21 */
+#define LPUART1_TXD_P3_21 A15X_MUX('3',21,3) /* PT3_21 */
+#define CT2_MAT3_P3_21 A15X_MUX('3',21,4) /* PT3_21 */
+#define PWM0_X3_P3_21 A15X_MUX('3',21,5) /* PT3_21 */
+#define PWM1_B3_P3_21 A15X_MUX('3',21,7) /* PT3_21 */
+#define SMARTDMA_PIO21_P3_21 A15X_MUX('3',21,10) /* PT3_21 */
+#define P3_22 A15X_MUX('3',22,0) /* PT3_22 */
+#define LPUART1_RTS_B_P3_22 A15X_MUX('3',22,3) /* PT3_22 */
+#define CT_INP10_P3_22 A15X_MUX('3',22,4) /* PT3_22 */
+#define PWM1_X2_P3_22 A15X_MUX('3',22,7) /* PT3_22 */
+#define SMARTDMA_PIO22_P3_22 A15X_MUX('3',22,10) /* PT3_22 */
+#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */
+#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */
+#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */
+#define LPI2C1_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */
+#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */
+#define PWM1_A3_P3_27 A15X_MUX('3',27,7) /* PT3_27 */
+#define SMARTDMA_PIO27_P3_27 A15X_MUX('3',27,10) /* PT3_27 */
+#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */
+#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */
+#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */
+#define LPI2C1_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */
+#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */
+#define PWM1_B3_P3_28 A15X_MUX('3',28,7) /* PT3_28 */
+#define SMARTDMA_PIO28_P3_28 A15X_MUX('3',28,10) /* PT3_28 */
+#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */
+#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */
+#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */
+#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */
+#define LPI2C1_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */
+#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */
+#define SMARTDMA_PIO29_P3_29 A15X_MUX('3',29,10) /* PT3_29 */
+#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */
+#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */
+#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */
+#define LPI2C1_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */
+#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */
+#define PWM1_A0_P3_30 A15X_MUX('3',30,7) /* PT3_30 */
+#define SMARTDMA_PIO30_P3_30 A15X_MUX('3',30,10) /* PT3_30 */
+#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */
+#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */
+#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */
+#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */
+#define LPI2C1_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */
+#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */
+#define PWM1_B0_P3_31 A15X_MUX('3',31,7) /* PT3_31 */
+#define SMARTDMA_PIO31_P3_31 A15X_MUX('3',31,10) /* PT3_31 */
+#define P4_2 A15X_MUX('4',2,0) /* PT4_2 */
+#define WUU0_IN16_P4_2 A15X_MUX('4',2,0) /* PT4_2 */
+#define CLKOUT_P4_2 A15X_MUX('4',2,1) /* PT4_2 */
+#define LPUART3_RXD_P4_2 A15X_MUX('4',2,3) /* PT4_2 */
+#define PWM0_A2_P4_2 A15X_MUX('4',2,5) /* PT4_2 */
+#define SMARTDMA_PIO22_P4_2 A15X_MUX('4',2,7) /* PT4_2 */
+#define P4_3 A15X_MUX('4',3,0) /* PT4_3 */
+#define PWM0_B2_P4_3 A15X_MUX('4',3,5) /* PT4_3 */
+#define SMARTDMA_PIO23_P4_3 A15X_MUX('4',3,7) /* PT4_3 */
+#define WUU0_IN17_P4_4 A15X_MUX('4',4,0) /* PT4_4 */
+#define P4_4 A15X_MUX('4',4,0) /* PT4_4 */
+#define PWM0_A1_P4_4 A15X_MUX('4',4,5) /* PT4_4 */
+#define SMARTDMA_PIO24_P4_4 A15X_MUX('4',4,7) /* PT4_4 */
+#define P4_5 A15X_MUX('4',5,0) /* PT4_5 */
+#define TRIG_OUT3_P4_5 A15X_MUX('4',5,1) /* PT4_5 */
+#define LPUART3_TXD_P4_5 A15X_MUX('4',5,3) /* PT4_5 */
+#define PWM0_B1_P4_5 A15X_MUX('4',5,5) /* PT4_5 */
+#define SMARTDMA_PIO25_P4_5 A15X_MUX('4',5,7) /* PT4_5 */
+#define P4_6 A15X_MUX('4',6,0) /* PT4_6 */
+#define TRIG_IN4_P4_6 A15X_MUX('4',6,1) /* PT4_6 */
+#define LPUART3_CTS_B_P4_6 A15X_MUX('4',6,3) /* PT4_6 */
+#define CT_INP6_P4_6 A15X_MUX('4',6,4) /* PT4_6 */
+#define PWM0_A0_P4_6 A15X_MUX('4',6,5) /* PT4_6 */
+#define SMARTDMA_PIO26_P4_6 A15X_MUX('4',6,7) /* PT4_6 */
+#define P4_7 A15X_MUX('4',7,0) /* PT4_7 */
+#define TRIG_IN5_P4_7 A15X_MUX('4',7,1) /* PT4_7 */
+#define LPUART3_RTS_B_P4_7 A15X_MUX('4',7,3) /* PT4_7 */
+#define CT_INP7_P4_7 A15X_MUX('4',7,4) /* PT4_7 */
+#define PWM0_B0_P4_7 A15X_MUX('4',7,5) /* PT4_7 */
+#define SMARTDMA_PIO27_P4_7 A15X_MUX('4',7,7) /* PT4_7 */
+#endif
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/CMakeLists.txt
new file mode 100644
index 0000000000..086d5f9916
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+#### device spepcific drivers
+include(${SdkRootDirPath}/devices/arm/device_header_cstartup.cmake)
+mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA344/drivers)
+
+#### MCX shared drivers/components/middlewares, project segments
+include(${SdkRootDirPath}/devices/MCX/shared.cmake)
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343.h
new file mode 100644
index 0000000000..53641b659e
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343.h
@@ -0,0 +1,92 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**
+**     Compilers:
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    MCXAP144M180FS6_RM_Rev.1_DraftC
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MCXA343
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MCXA343.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for MCXA343
+ *
+ * CMSIS Peripheral Access Layer for MCXA343
+ */
+
+#if !defined(MCXA343_H_)  /* Check if memory map has not been already included */
+#define MCXA343_H_
+
+/* IP Header Files List */
+#include "PERI_ADC.h"
+#include "PERI_AOI.h"
+#include "PERI_CAN.h"
+#include "PERI_CDOG.h"
+#include "PERI_CMC.h"
+#include "PERI_CRC.h"
+#include "PERI_CTIMER.h"
+#include "PERI_DEBUGMAILBOX.h"
+#include "PERI_DMA.h"
+#include "PERI_EIM.h"
+#include "PERI_EQDC.h"
+#include "PERI_ERM.h"
+#include "PERI_FMC.h"
+#include "PERI_FMU.h"
+#include "PERI_FREQME.h"
+#include "PERI_GLIKEY.h"
+#include "PERI_GPIO.h"
+#include "PERI_INPUTMUX.h"
+#include "PERI_LPCMP.h"
+#include "PERI_LPI2C.h"
+#include "PERI_LPSPI.h"
+#include "PERI_LPTMR.h"
+#include "PERI_LPUART.h"
+#include "PERI_MAU.h"
+#include "PERI_MRCC.h"
+#include "PERI_OPAMP.h"
+#include "PERI_OSTIMER.h"
+#include "PERI_PORT.h"
+#include "PERI_PWM.h"
+#include "PERI_RTC.h"
+#include "PERI_SCG.h"
+#include "PERI_SMARTDMA.h"
+#include "PERI_SPC.h"
+#include "PERI_SYSCON.h"
+#include "PERI_TRDC.h"
+#include "PERI_UTICK.h"
+#include "PERI_VBAT.h"
+#include "PERI_WAKETIMER.h"
+#include "PERI_WUU.h"
+#include "PERI_WWDT.h"
+
+#endif  /* #if !defined(MCXA343_H_) */
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343_COMMON.h
new file mode 100644
index 0000000000..fba2dc3ef4
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343_COMMON.h
@@ -0,0 +1,849 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**
+**     Compilers:
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    MCXAP144M180FS6_RM_Rev.1_DraftC
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MCXA343
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MCXA343_COMMON.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for MCXA343
+ *
+ * CMSIS Peripheral Access Layer for MCXA343
+ */
+
+#if !defined(MCXA343_COMMON_H_)
+#define MCXA343_COMMON_H_                        /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 138                /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M33 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M33 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M33 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M33 Usage Fault Interrupt */
+  SecureFault_IRQn             = -9,               /**< Cortex-M33 Secure Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M33 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M33 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M33 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M33 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  Reserved16_IRQn              = 0,                /**< OR IRQ1 to IRQ53 */
+  CMC_IRQn                     = 1,                /**< Core Mode Controller interrupt */
+  DMA_CH0_IRQn                 = 2,                /**< DMA3_0_CH0 error or transfer complete */
+  DMA_CH1_IRQn                 = 3,                /**< DMA3_0_CH1 error or transfer complete */
+  DMA_CH2_IRQn                 = 4,                /**< DMA3_0_CH2 error or transfer complete */
+  DMA_CH3_IRQn                 = 5,                /**< DMA3_0_CH3 error or transfer complete */
+  DMA_CH4_IRQn                 = 6,                /**< DMA3_0_CH4 error or transfer complete */
+  DMA_CH5_IRQn                 = 7,                /**< DMA3_0_CH5 error or transfer complete */
+  DMA_CH6_IRQn                 = 8,                /**< DMA3_0_CH6 error or transfer complete */
+  DMA_CH7_IRQn                 = 9,                /**< DMA3_0_CH7 error or transfer complete */
+  ERM0_SINGLE_BIT_IRQn         = 10,               /**< ERM Single Bit error interrupt */
+  ERM0_MULTI_BIT_IRQn          = 11,               /**< ERM Multi Bit error interrupt */
+  FMU0_IRQn                    = 12,               /**< Flash Management Unit interrupt */
+  GLIKEY0_IRQn                 = 13,               /**< GLIKEY Interrupt  */
+  MBC0_IRQn                    = 14,               /**< MBC secure violation interrupt */
+  SCG0_IRQn                    = 15,               /**< System Clock Generator interrupt */
+  SPC0_IRQn                    = 16,               /**< System Power Controller interrupt */
+  Reserved33_IRQn              = 17,               /**< Reserved interrupt */
+  WUU0_IRQn                    = 18,               /**< Wake Up Unit interrupt */
+  CAN0_IRQn                    = 19,               /**< Controller Area Network 0 interrupt */
+  Reserved36_IRQn              = 20,               /**< Reserved interrupt */
+  Reserved37_IRQn              = 21,               /**< Reserved interrupt */
+  Reserved38_IRQn              = 22,               /**< Reserved interrupt */
+  Reserved39_IRQn              = 23,               /**< Reserved interrupt */
+  Reserved40_IRQn              = 24,               /**< Reserved interrupt */
+  Reserved41_IRQn              = 25,               /**< Reserved interrupt */
+  LPI2C0_IRQn                  = 26,               /**< Low-Power Inter Integrated Circuit 0 interrupt */
+  LPI2C1_IRQn                  = 27,               /**< Low-Power Inter Integrated Circuit 1 interrupt */
+  LPSPI0_IRQn                  = 28,               /**< Low-Power Serial Peripheral Interface 0 interrupt */
+  LPSPI1_IRQn                  = 29,               /**< Low-Power Serial Peripheral Interface 1 interrupt */
+  Reserved46_IRQn              = 30,               /**< Reserved interrupt */
+  LPUART0_IRQn                 = 31,               /**< Low-Power Universal Asynchronous Receive/Transmit 0 interrupt */
+  LPUART1_IRQn                 = 32,               /**< Low-Power Universal Asynchronous Receive/Transmit 1 interrupt */
+  LPUART2_IRQn                 = 33,               /**< Low-Power Universal Asynchronous Receive/Transmit 2 interrupt */
+  LPUART3_IRQn                 = 34,               /**< Low-Power Universal Asynchronous Receive/Transmit 3 interrupt */
+  Reserved51_IRQn              = 35,               /**< Reserved interrupt */
+  Reserved52_IRQn              = 36,               /**< Reserved interrupt */
+  Reserved53_IRQn              = 37,               /**< Reserved interrupt */
+  CDOG0_IRQn                   = 38,               /**< Code Watchdog Timer 0 interrupt */
+  CTIMER0_IRQn                 = 39,               /**< Standard counter/timer 0 interrupt */
+  CTIMER1_IRQn                 = 40,               /**< Standard counter/timer 1 interrupt */
+  CTIMER2_IRQn                 = 41,               /**< Standard counter/timer 2 interrupt */
+  Reserved58_IRQn              = 42,               /**< Reserved interrupt */
+  Reserved59_IRQn              = 43,               /**< Reserved interrupt */
+  FLEXPWM0_RELOAD_ERROR_IRQn   = 44,               /**< FlexPWM0_reload_error interrupt */
+  FLEXPWM0_FAULT_IRQn          = 45,               /**< FlexPWM0_fault interrupt */
+  FLEXPWM0_SUBMODULE0_IRQn     = 46,               /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */
+  FLEXPWM0_SUBMODULE1_IRQn     = 47,               /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */
+  FLEXPWM0_SUBMODULE2_IRQn     = 48,               /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */
+  FLEXPWM0_SUBMODULE3_IRQn     = 49,               /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */
+  EQDC0_COMPARE_IRQn           = 50,               /**< Compare */
+  EQDC0_HOME_IRQn              = 51,               /**< Home */
+  EQDC0_WATCHDOG_IRQn          = 52,               /**< Watchdog / Simultaneous A and B Change */
+  EQDC0_INDEX_IRQn             = 53,               /**< Index / Roll Over / Roll Under */
+  FREQME0_IRQn                 = 54,               /**< Frequency Measurement interrupt */
+  LPTMR0_IRQn                  = 55,               /**< Low Power Timer 0 interrupt */
+  Reserved72_IRQn              = 56,               /**< Reserved interrupt */
+  OS_EVENT_IRQn                = 57,               /**< OS event timer interrupt */
+  WAKETIMER0_IRQn              = 58,               /**< Wake Timer Interrupt */
+  UTICK0_IRQn                  = 59,               /**< Micro-Tick Timer interrupt */
+  WWDT0_IRQn                   = 60,               /**< Windowed Watchdog Timer 0 interrupt */
+  ADC0_IRQn                    = 62,               /**< Analog-to-Digital Converter 0 interrupt */
+  ADC1_IRQn                    = 63,               /**< Analog-to-Digital Converter 1 interrupt */
+  CMP0_IRQn                    = 64,               /**< Comparator 0 interrupt */
+  CMP1_IRQn                    = 65,               /**< Comparator 1 interrupt */
+  CMP2_IRQn                    = 66,               /**< Comparator 2 interrupt */
+  Reserved83_IRQn              = 67,               /**< Reserved interrupt */
+  Reserved84_IRQn              = 68,               /**< Reserved interrupt */
+  Reserved85_IRQn              = 69,               /**< Reserved interrupt */
+  Reserved86_IRQn              = 70,               /**< Reserved interrupt */
+  GPIO0_IRQn                   = 71,               /**< General Purpose Input/Output interrupt 0 */
+  GPIO1_IRQn                   = 72,               /**< General Purpose Input/Output interrupt 1 */
+  GPIO2_IRQn                   = 73,               /**< General Purpose Input/Output interrupt 2 */
+  GPIO3_IRQn                   = 74,               /**< General Purpose Input/Output interrupt 3 */
+  GPIO4_IRQn                   = 75,               /**< General Purpose Input/Output interrupt 4 */
+  Reserved92_IRQn              = 76,               /**< Reserved interrupt */
+  Reserved93_IRQn              = 77,               /**< Reserved interrupt */
+  Reserved94_IRQn              = 78,               /**< Reserved interrupt */
+  FLEXPWM1_RELOAD_ERROR_IRQn   = 79,               /**< FlexPWM1_reload_error interrupt */
+  FLEXPWM1_FAULT_IRQn          = 80,               /**< FlexPWM1_fault interrupt */
+  FLEXPWM1_SUBMODULE0_IRQn     = 81,               /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */
+  FLEXPWM1_SUBMODULE1_IRQn     = 82,               /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */
+  FLEXPWM1_SUBMODULE2_IRQn     = 83,               /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */
+  FLEXPWM1_SUBMODULE3_IRQn     = 84,               /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */
+  EQDC1_COMPARE_IRQn           = 85,               /**< Compare */
+  EQDC1_HOME_IRQn              = 86,               /**< Home */
+  EQDC1_WATCHDOG_IRQn          = 87,               /**< Watchdog / Simultaneous A and B Change */
+  EQDC1_INDEX_IRQn             = 88,               /**< Index / Roll Over / Roll Under */
+  Reserved105_IRQn             = 89,               /**< Reserved interrupt */
+  Reserved106_IRQn             = 90,               /**< Reserved interrupt */
+  Reserved107_IRQn             = 91,               /**< Reserved interrupt */
+  Reserved108_IRQn             = 92,               /**< Reserved interrupt */
+  Reserved109_IRQn             = 93,               /**< Reserved interrupt */
+  Reserved110_IRQn             = 94,               /**< Reserved interrupt */
+  Reserved111_IRQn             = 95,               /**< Reserved interrupt */
+  Reserved112_IRQn             = 96,               /**< Reserved interrupt */
+  Reserved113_IRQn             = 97,               /**< Reserved interrupt */
+  Reserved114_IRQn             = 98,               /**< Reserved interrupt */
+  Reserved115_IRQn             = 99,               /**< Reserved interrupt */
+  Reserved116_IRQn             = 100,              /**< Reserved interrupt */
+  Reserved117_IRQn             = 101,              /**< Reserved interrupt */
+  Reserved118_IRQn             = 102,              /**< Reserved interrupt */
+  Reserved119_IRQn             = 103,              /**< Reserved interrupt */
+  Reserved120_IRQn             = 104,              /**< Reserved interrupt */
+  Reserved121_IRQn             = 105,              /**< Reserved interrupt */
+  Reserved122_IRQn             = 106,              /**< Reserved interrupt */
+  MAU_IRQn                     = 107,              /**< MAU interrupt */
+  SMARTDMA_IRQn                = 108,              /**< SmartDMA interrupt */
+  Reserved125_IRQn             = 109,              /**< Reserved interrupt */
+  Reserved126_IRQn             = 110,              /**< Reserved interrupt */
+  Reserved127_IRQn             = 111,              /**< Reserved interrupt */
+  Reserved128_IRQn             = 112,              /**< Reserved interrupt */
+  Reserved129_IRQn             = 113,              /**< Reserved interrupt */
+  Reserved130_IRQn             = 114,              /**< Reserved interrupt */
+  Reserved131_IRQn             = 115,              /**< Reserved interrupt */
+  Reserved132_IRQn             = 116,              /**< Reserved interrupt */
+  Reserved133_IRQn             = 117,              /**< Reserved interrupt */
+  Reserved134_IRQn             = 118,              /**< Reserved interrupt */
+  RTC_IRQn                     = 119,              /**< RTC alarm interrupt */
+  RTC_1HZ_IRQn                 = 120,              /**< RTC 1Hz interrupt */
+  Reserved137_IRQn             = 121               /**< Reserved interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M33 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+#define __DSP_PRESENT                  1         /**< Defines if Armv8-M Mainline core supports DSP instructions */
+#define __SAUREGION_PRESENT            0         /**< Defines if an SAU is present or not */
+
+#include "core_cm33.h"                 /* Core Peripheral Access Layer */
+#include "system_MCXA343.h"            /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+#ifndef MCXA343_SERIES
+#define MCXA343_SERIES
+#endif
+/* CPU specific feature definitions */
+#include "MCXA343_features.h"
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x400AF000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE                                (0x400B0000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1                                     ((ADC_Type *)ADC1_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0, ADC1 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn, ADC1_IRQn }
+
+/* AOI - Peripheral instance base addresses */
+/** Peripheral AOI0 base address */
+#define AOI0_BASE                                (0x40089000u)
+/** Peripheral AOI0 base pointer */
+#define AOI0                                     ((AOI_Type *)AOI0_BASE)
+/** Peripheral AOI1 base address */
+#define AOI1_BASE                                (0x40097000u)
+/** Peripheral AOI1 base pointer */
+#define AOI1                                     ((AOI_Type *)AOI1_BASE)
+/** Array initializer of AOI peripheral base addresses */
+#define AOI_BASE_ADDRS                           { AOI0_BASE, AOI1_BASE }
+/** Array initializer of AOI peripheral base pointers */
+#define AOI_BASE_PTRS                            { AOI0, AOI1 }
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE                                (0x400CC000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0                                     ((CAN_Type *)CAN0_BASE)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS                           { CAN0_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS                            { CAN0 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_Rx_Warning_IRQS                      { CAN0_IRQn }
+#define CAN_Tx_Warning_IRQS                      { CAN0_IRQn }
+#define CAN_Wake_Up_IRQS                         { CAN0_IRQn }
+#define CAN_Error_IRQS                           { CAN0_IRQn }
+#define CAN_Bus_Off_IRQS                         { CAN0_IRQn }
+#define CAN_ORed_Message_buffer_IRQS             { CAN0_IRQn }
+
+/* CDOG - Peripheral instance base addresses */
+/** Peripheral CDOG0 base address */
+#define CDOG0_BASE                               (0x40100000u)
+/** Peripheral CDOG0 base pointer */
+#define CDOG0                                    ((CDOG_Type *)CDOG0_BASE)
+/** Array initializer of CDOG peripheral base addresses */
+#define CDOG_BASE_ADDRS                          { CDOG0_BASE }
+/** Array initializer of CDOG peripheral base pointers */
+#define CDOG_BASE_PTRS                           { CDOG0 }
+/** Interrupt vectors for the CDOG peripheral type */
+#define CDOG_IRQS                                { CDOG0_IRQn }
+
+/* CMC - Peripheral instance base addresses */
+/** Peripheral CMC base address */
+#define CMC_BASE                                 (0x4008B000u)
+/** Peripheral CMC base pointer */
+#define CMC                                      ((CMC_Type *)CMC_BASE)
+/** Array initializer of CMC peripheral base addresses */
+#define CMC_BASE_ADDRS                           { CMC_BASE }
+/** Array initializer of CMC peripheral base pointers */
+#define CMC_BASE_PTRS                            { CMC }
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC0 base address */
+#define CRC0_BASE                                (0x4008A000u)
+/** Peripheral CRC0 base pointer */
+#define CRC0                                     ((CRC_Type *)CRC0_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC0_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC0 }
+
+/* CTIMER - Peripheral instance base addresses */
+/** Peripheral CTIMER0 base address */
+#define CTIMER0_BASE                             (0x40004000u)
+/** Peripheral CTIMER0 base pointer */
+#define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
+/** Peripheral CTIMER1 base address */
+#define CTIMER1_BASE                             (0x40005000u)
+/** Peripheral CTIMER1 base pointer */
+#define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
+/** Peripheral CTIMER2 base address */
+#define CTIMER2_BASE                             (0x40006000u)
+/** Peripheral CTIMER2 base pointer */
+#define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
+/** Array initializer of CTIMER peripheral base addresses */
+#define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE }
+/** Array initializer of CTIMER peripheral base pointers */
+#define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2 }
+/** Interrupt vectors for the CTIMER peripheral type */
+#define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn }
+
+/* DEBUGMAILBOX - Peripheral instance base addresses */
+/** Peripheral DBGMAILBOX base address */
+#define DBGMAILBOX_BASE                          (0x40101000u)
+/** Peripheral DBGMAILBOX base pointer */
+#define DBGMAILBOX                               ((DEBUGMAILBOX_Type *)DBGMAILBOX_BASE)
+/** Array initializer of DEBUGMAILBOX peripheral base addresses */
+#define DEBUGMAILBOX_BASE_ADDRS                  { DBGMAILBOX_BASE }
+/** Array initializer of DEBUGMAILBOX peripheral base pointers */
+#define DEBUGMAILBOX_BASE_PTRS                   { DBGMAILBOX }
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA0 base address */
+#define DMA0_BASE                                (0x40080000u)
+/** Peripheral DMA0 base pointer */
+#define DMA0                                     ((DMA_Type *)DMA0_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA0_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+
+/* EIM - Peripheral instance base addresses */
+/** Peripheral EIM0 base address */
+#define EIM0_BASE                                (0x4008C000u)
+/** Peripheral EIM0 base pointer */
+#define EIM0                                     ((EIM_Type *)EIM0_BASE)
+/** Array initializer of EIM peripheral base addresses */
+#define EIM_BASE_ADDRS                           { EIM0_BASE }
+/** Array initializer of EIM peripheral base pointers */
+#define EIM_BASE_PTRS                            { EIM0 }
+
+/* EQDC - Peripheral instance base addresses */
+/** Peripheral EQDC0 base address */
+#define EQDC0_BASE                               (0x400A7000u)
+/** Peripheral EQDC0 base pointer */
+#define EQDC0                                    ((EQDC_Type *)EQDC0_BASE)
+/** Peripheral EQDC1 base address */
+#define EQDC1_BASE                               (0x400A8000u)
+/** Peripheral EQDC1 base pointer */
+#define EQDC1                                    ((EQDC_Type *)EQDC1_BASE)
+/** Array initializer of EQDC peripheral base addresses */
+#define EQDC_BASE_ADDRS                          { EQDC0_BASE, EQDC1_BASE }
+/** Array initializer of EQDC peripheral base pointers */
+#define EQDC_BASE_PTRS                           { EQDC0, EQDC1 }
+/** Interrupt vectors for the EQDC peripheral type */
+#define EQDC_COMPARE_IRQS                        { EQDC0_COMPARE_IRQn, EQDC1_COMPARE_IRQn }
+#define EQDC_HOME_IRQS                           { EQDC0_HOME_IRQn, EQDC1_HOME_IRQn }
+#define EQDC_WDOG_IRQS                           { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn }
+#define EQDC_INDEX_IRQS                          { EQDC0_INDEX_IRQn, EQDC1_INDEX_IRQn }
+#define EQDC_INPUT_SWITCH_IRQS                   { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn }
+
+/* ERM - Peripheral instance base addresses */
+/** Peripheral ERM0 base address */
+#define ERM0_BASE                                (0x4008D000u)
+/** Peripheral ERM0 base pointer */
+#define ERM0                                     ((ERM_Type *)ERM0_BASE)
+/** Array initializer of ERM peripheral base addresses */
+#define ERM_BASE_ADDRS                           { ERM0_BASE }
+/** Array initializer of ERM peripheral base pointers */
+#define ERM_BASE_PTRS                            { ERM0 }
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC0 base address */
+#define FMC0_BASE                                (0x40094000u)
+/** Peripheral FMC0 base pointer */
+#define FMC0                                     ((FMC_Type *)FMC0_BASE)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS                           { FMC0_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS                            { FMC0 }
+
+/* FMU - Peripheral instance base addresses */
+/** Peripheral FMU0 base address */
+#define FMU0_BASE                                (0x40095000u)
+/** Peripheral FMU0 base pointer */
+#define FMU0                                     ((FMU_Type *)FMU0_BASE)
+/** Array initializer of FMU peripheral base addresses */
+#define FMU_BASE_ADDRS                           { FMU0_BASE }
+/** Array initializer of FMU peripheral base pointers */
+#define FMU_BASE_PTRS                            { FMU0 }
+
+/* FREQME - Peripheral instance base addresses */
+/** Peripheral FREQME0 base address */
+#define FREQME0_BASE                             (0x40009000u)
+/** Peripheral FREQME0 base pointer */
+#define FREQME0                                  ((FREQME_Type *)FREQME0_BASE)
+/** Array initializer of FREQME peripheral base addresses */
+#define FREQME_BASE_ADDRS                        { FREQME0_BASE }
+/** Array initializer of FREQME peripheral base pointers */
+#define FREQME_BASE_PTRS                         { FREQME0 }
+/** Interrupt vectors for the FREQME peripheral type */
+#define FREQME_IRQS                              { FREQME0_IRQn }
+
+/* GLIKEY - Peripheral instance base addresses */
+/** Peripheral GLIKEY0 base address */
+#define GLIKEY0_BASE                             (0x40091D00u)
+/** Peripheral GLIKEY0 base pointer */
+#define GLIKEY0                                  ((GLIKEY_Type *)GLIKEY0_BASE)
+/** Array initializer of GLIKEY peripheral base addresses */
+#define GLIKEY_BASE_ADDRS                        { GLIKEY0_BASE }
+/** Array initializer of GLIKEY peripheral base pointers */
+#define GLIKEY_BASE_PTRS                         { GLIKEY0 }
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIO0 base address */
+#define GPIO0_BASE                               (0x40102000u)
+/** Peripheral GPIO0 base pointer */
+#define GPIO0                                    ((GPIO_Type *)GPIO0_BASE)
+/** Peripheral GPIO1 base address */
+#define GPIO1_BASE                               (0x40103000u)
+/** Peripheral GPIO1 base pointer */
+#define GPIO1                                    ((GPIO_Type *)GPIO1_BASE)
+/** Peripheral GPIO2 base address */
+#define GPIO2_BASE                               (0x40104000u)
+/** Peripheral GPIO2 base pointer */
+#define GPIO2                                    ((GPIO_Type *)GPIO2_BASE)
+/** Peripheral GPIO3 base address */
+#define GPIO3_BASE                               (0x40105000u)
+/** Peripheral GPIO3 base pointer */
+#define GPIO3                                    ((GPIO_Type *)GPIO3_BASE)
+/** Peripheral GPIO4 base address */
+#define GPIO4_BASE                               (0x40106000u)
+/** Peripheral GPIO4 base pointer */
+#define GPIO4                                    ((GPIO_Type *)GPIO4_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 }
+/** Interrupt vectors for the GPIO peripheral type */
+#define GPIO_IRQS                                { GPIO0_IRQn, GPIO1_IRQn, GPIO2_IRQn, GPIO3_IRQn, GPIO4_IRQn }
+
+/* INPUTMUX - Peripheral instance base addresses */
+/** Peripheral INPUTMUX0 base address */
+#define INPUTMUX0_BASE                           (0x40001000u)
+/** Peripheral INPUTMUX0 base pointer */
+#define INPUTMUX0                                ((INPUTMUX_Type *)INPUTMUX0_BASE)
+/** Array initializer of INPUTMUX peripheral base addresses */
+#define INPUTMUX_BASE_ADDRS                      { INPUTMUX0_BASE }
+/** Array initializer of INPUTMUX peripheral base pointers */
+#define INPUTMUX_BASE_PTRS                       { INPUTMUX0 }
+
+/* LPCMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE                                (0x400B1000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0                                     ((LPCMP_Type *)CMP0_BASE)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE                                (0x400B2000u)
+/** Peripheral CMP1 base pointer */
+#define CMP1                                     ((LPCMP_Type *)CMP1_BASE)
+/** Peripheral CMP2 base address */
+#define CMP2_BASE                                (0x400B3000u)
+/** Peripheral CMP2 base pointer */
+#define CMP2                                     ((LPCMP_Type *)CMP2_BASE)
+/** Array initializer of LPCMP peripheral base addresses */
+#define LPCMP_BASE_ADDRS                         { CMP0_BASE, CMP1_BASE, CMP2_BASE }
+/** Array initializer of LPCMP peripheral base pointers */
+#define LPCMP_BASE_PTRS                          { CMP0, CMP1, CMP2 }
+
+/* LPI2C - Peripheral instance base addresses */
+/** Peripheral LPI2C0 base address */
+#define LPI2C0_BASE                              (0x4009A000u)
+/** Peripheral LPI2C0 base pointer */
+#define LPI2C0                                   ((LPI2C_Type *)LPI2C0_BASE)
+/** Peripheral LPI2C1 base address */
+#define LPI2C1_BASE                              (0x4009B000u)
+/** Peripheral LPI2C1 base pointer */
+#define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
+/** Array initializer of LPI2C peripheral base addresses */
+#define LPI2C_BASE_ADDRS                         { LPI2C0_BASE, LPI2C1_BASE }
+/** Array initializer of LPI2C peripheral base pointers */
+#define LPI2C_BASE_PTRS                          { LPI2C0, LPI2C1 }
+/** Interrupt vectors for the LPI2C peripheral type */
+#define LPI2C_IRQS                               { LPI2C0_IRQn, LPI2C1_IRQn }
+
+/* LPSPI - Peripheral instance base addresses */
+/** Peripheral LPSPI0 base address */
+#define LPSPI0_BASE                              (0x4009C000u)
+/** Peripheral LPSPI0 base pointer */
+#define LPSPI0                                   ((LPSPI_Type *)LPSPI0_BASE)
+/** Peripheral LPSPI1 base address */
+#define LPSPI1_BASE                              (0x4009D000u)
+/** Peripheral LPSPI1 base pointer */
+#define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
+/** Array initializer of LPSPI peripheral base addresses */
+#define LPSPI_BASE_ADDRS                         { LPSPI0_BASE, LPSPI1_BASE }
+/** Array initializer of LPSPI peripheral base pointers */
+#define LPSPI_BASE_PTRS                          { LPSPI0, LPSPI1 }
+/** Interrupt vectors for the LPSPI peripheral type */
+#define LPSPI_IRQS                               { LPSPI0_IRQn, LPSPI1_IRQn }
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x400AB000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS                          { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn }
+
+/* LPUART - Peripheral instance base addresses */
+/** Peripheral LPUART0 base address */
+#define LPUART0_BASE                             (0x4009F000u)
+/** Peripheral LPUART0 base pointer */
+#define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
+/** Peripheral LPUART1 base address */
+#define LPUART1_BASE                             (0x400A0000u)
+/** Peripheral LPUART1 base pointer */
+#define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
+/** Peripheral LPUART2 base address */
+#define LPUART2_BASE                             (0x400A1000u)
+/** Peripheral LPUART2 base pointer */
+#define LPUART2                                  ((LPUART_Type *)LPUART2_BASE)
+/** Peripheral LPUART3 base address */
+#define LPUART3_BASE                             (0x400A2000u)
+/** Peripheral LPUART3 base pointer */
+#define LPUART3                                  ((LPUART_Type *)LPUART3_BASE)
+/** Array initializer of LPUART peripheral base addresses */
+#define LPUART_BASE_ADDRS                        { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE }
+/** Array initializer of LPUART peripheral base pointers */
+#define LPUART_BASE_PTRS                         { LPUART0, LPUART1, LPUART2, LPUART3 }
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS                        { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn }
+#define LPUART_ERR_IRQS                          { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn }
+
+/* MAU - Peripheral instance base addresses */
+/** Peripheral MAU0 base address */
+#define MAU0_BASE                                (0x40108000u)
+/** Peripheral MAU0 base pointer */
+#define MAU0                                     ((MAU_Type *)MAU0_BASE)
+/** Array initializer of MAU peripheral base addresses */
+#define MAU_BASE_ADDRS                           { MAU0_BASE }
+/** Array initializer of MAU peripheral base pointers */
+#define MAU_BASE_PTRS                            { MAU0 }
+/** Interrupt vectors for the MAU peripheral type */
+#define MAU_IRQS                                 { MAU_IRQn }
+
+/* MRCC - Peripheral instance base addresses */
+/** Peripheral MRCC0 base address */
+#define MRCC0_BASE                               (0x40091000u)
+/** Peripheral MRCC0 base pointer */
+#define MRCC0                                    ((MRCC_Type *)MRCC0_BASE)
+/** Array initializer of MRCC peripheral base addresses */
+#define MRCC_BASE_ADDRS                          { MRCC0_BASE }
+/** Array initializer of MRCC peripheral base pointers */
+#define MRCC_BASE_PTRS                           { MRCC0 }
+
+/* OPAMP - Peripheral instance base addresses */
+/** Peripheral OPAMP0 base address */
+#define OPAMP0_BASE                              (0x400B7000u)
+/** Peripheral OPAMP0 base pointer */
+#define OPAMP0                                   ((OPAMP_Type *)OPAMP0_BASE)
+/** Peripheral OPAMP1 base address */
+#define OPAMP1_BASE                              (0x400B8000u)
+/** Peripheral OPAMP1 base pointer */
+#define OPAMP1                                   ((OPAMP_Type *)OPAMP1_BASE)
+/** Peripheral OPAMP2 base address */
+#define OPAMP2_BASE                              (0x400B9000u)
+/** Peripheral OPAMP2 base pointer */
+#define OPAMP2                                   ((OPAMP_Type *)OPAMP2_BASE)
+/** Array initializer of OPAMP peripheral base addresses */
+#define OPAMP_BASE_ADDRS                         { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE }
+/** Array initializer of OPAMP peripheral base pointers */
+#define OPAMP_BASE_PTRS                          { OPAMP0, OPAMP1, OPAMP2 }
+
+/* OSTIMER - Peripheral instance base addresses */
+/** Peripheral OSTIMER0 base address */
+#define OSTIMER0_BASE                            (0x400AD000u)
+/** Peripheral OSTIMER0 base pointer */
+#define OSTIMER0                                 ((OSTIMER_Type *)OSTIMER0_BASE)
+/** Array initializer of OSTIMER peripheral base addresses */
+#define OSTIMER_BASE_ADDRS                       { OSTIMER0_BASE }
+/** Array initializer of OSTIMER peripheral base pointers */
+#define OSTIMER_BASE_PTRS                        { OSTIMER0 }
+/** Interrupt vectors for the OSTIMER peripheral type */
+#define OSTIMER_IRQS                             { OS_EVENT_IRQn }
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORT0 base address */
+#define PORT0_BASE                               (0x400BC000u)
+/** Peripheral PORT0 base pointer */
+#define PORT0                                    ((PORT_Type *)PORT0_BASE)
+/** Peripheral PORT1 base address */
+#define PORT1_BASE                               (0x400BD000u)
+/** Peripheral PORT1 base pointer */
+#define PORT1                                    ((PORT_Type *)PORT1_BASE)
+/** Peripheral PORT2 base address */
+#define PORT2_BASE                               (0x400BE000u)
+/** Peripheral PORT2 base pointer */
+#define PORT2                                    ((PORT_Type *)PORT2_BASE)
+/** Peripheral PORT3 base address */
+#define PORT3_BASE                               (0x400BF000u)
+/** Peripheral PORT3 base pointer */
+#define PORT3                                    ((PORT_Type *)PORT3_BASE)
+/** Peripheral PORT4 base address */
+#define PORT4_BASE                               (0x400C0000u)
+/** Peripheral PORT4 base pointer */
+#define PORT4                                    ((PORT_Type *)PORT4_BASE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS                          { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS                           { PORT0, PORT1, PORT2, PORT3, PORT4 }
+
+/* PWM - Peripheral instance base addresses */
+/** Peripheral FLEXPWM0 base address */
+#define FLEXPWM0_BASE                            (0x400A9000u)
+/** Peripheral FLEXPWM0 base pointer */
+#define FLEXPWM0                                 ((PWM_Type *)FLEXPWM0_BASE)
+/** Peripheral FLEXPWM1 base address */
+#define FLEXPWM1_BASE                            (0x400AA000u)
+/** Peripheral FLEXPWM1 base pointer */
+#define FLEXPWM1                                 ((PWM_Type *)FLEXPWM1_BASE)
+/** Array initializer of PWM peripheral base addresses */
+#define PWM_BASE_ADDRS                           { FLEXPWM0_BASE, FLEXPWM1_BASE }
+/** Array initializer of PWM peripheral base pointers */
+#define PWM_BASE_PTRS                            { FLEXPWM0, FLEXPWM1 }
+/** Interrupt vectors for the PWM peripheral type */
+#define PWM_CMP_IRQS                             { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } }
+#define PWM_RELOAD_IRQS                          { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } }
+#define PWM_CAPTURE_IRQS                         { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } }
+#define PWM_FAULT_IRQS                           { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn }
+#define PWM_RELOAD_ERROR_IRQS                    { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn }
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC0 base address */
+#define RTC0_BASE                                (0x400EE000u)
+/** Peripheral RTC0 base pointer */
+#define RTC0                                     ((RTC_Type *)RTC0_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC0_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC0 }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+
+/* SCG - Peripheral instance base addresses */
+/** Peripheral SCG0 base address */
+#define SCG0_BASE                                (0x4008F000u)
+/** Peripheral SCG0 base pointer */
+#define SCG0                                     ((SCG_Type *)SCG0_BASE)
+/** Array initializer of SCG peripheral base addresses */
+#define SCG_BASE_ADDRS                           { SCG0_BASE }
+/** Array initializer of SCG peripheral base pointers */
+#define SCG_BASE_PTRS                            { SCG0 }
+
+/* SMARTDMA - Peripheral instance base addresses */
+/** Peripheral SMARTDMA0 base address */
+#define SMARTDMA0_BASE                           (0x4000E000u)
+/** Peripheral SMARTDMA0 base pointer */
+#define SMARTDMA0                                ((SMARTDMA_Type *)SMARTDMA0_BASE)
+/** Array initializer of SMARTDMA peripheral base addresses */
+#define SMARTDMA_BASE_ADDRS                      { SMARTDMA0_BASE }
+/** Array initializer of SMARTDMA peripheral base pointers */
+#define SMARTDMA_BASE_PTRS                       { SMARTDMA0 }
+
+/* SPC - Peripheral instance base addresses */
+/** Peripheral SPC0 base address */
+#define SPC0_BASE                                (0x40090000u)
+/** Peripheral SPC0 base pointer */
+#define SPC0                                     ((SPC_Type *)SPC0_BASE)
+/** Array initializer of SPC peripheral base addresses */
+#define SPC_BASE_ADDRS                           { SPC0_BASE }
+/** Array initializer of SPC peripheral base pointers */
+#define SPC_BASE_PTRS                            { SPC0 }
+
+/* SYSCON - Peripheral instance base addresses */
+/** Peripheral SYSCON base address */
+#define SYSCON_BASE                              (0x40091000u)
+/** Peripheral SYSCON base pointer */
+#define SYSCON                                   ((SYSCON_Type *)SYSCON_BASE)
+/** Array initializer of SYSCON peripheral base addresses */
+#define SYSCON_BASE_ADDRS                        { SYSCON_BASE }
+/** Array initializer of SYSCON peripheral base pointers */
+#define SYSCON_BASE_PTRS                         { SYSCON }
+
+/* TRDC - Peripheral instance base addresses */
+/** Peripheral MBC0 base address */
+#define MBC0_BASE                                (0x4008E000u)
+/** Peripheral MBC0 base pointer */
+#define MBC0                                     ((TRDC_Type *)MBC0_BASE)
+/** Array initializer of TRDC peripheral base addresses */
+#define TRDC_BASE_ADDRS                          { MBC0_BASE }
+/** Array initializer of TRDC peripheral base pointers */
+#define TRDC_BASE_PTRS                           { MBC0 }
+#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1}
+#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1}
+#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1}
+#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0}
+#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT}
+#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1}
+#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1}
+#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1}
+#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0}
+#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT}
+
+
+/* UTICK - Peripheral instance base addresses */
+/** Peripheral UTICK0 base address */
+#define UTICK0_BASE                              (0x4000B000u)
+/** Peripheral UTICK0 base pointer */
+#define UTICK0                                   ((UTICK_Type *)UTICK0_BASE)
+/** Array initializer of UTICK peripheral base addresses */
+#define UTICK_BASE_ADDRS                         { UTICK0_BASE }
+/** Array initializer of UTICK peripheral base pointers */
+#define UTICK_BASE_PTRS                          { UTICK0 }
+/** Interrupt vectors for the UTICK peripheral type */
+#define UTICK_IRQS                               { UTICK0_IRQn }
+
+/* VBAT - Peripheral instance base addresses */
+/** Peripheral VBAT0 base address */
+#define VBAT0_BASE                               (0x40093000u)
+/** Peripheral VBAT0 base pointer */
+#define VBAT0                                    ((VBAT_Type *)VBAT0_BASE)
+/** Array initializer of VBAT peripheral base addresses */
+#define VBAT_BASE_ADDRS                          { VBAT0_BASE }
+/** Array initializer of VBAT peripheral base pointers */
+#define VBAT_BASE_PTRS                           { VBAT0 }
+
+/* WAKETIMER - Peripheral instance base addresses */
+/** Peripheral WAKETIMER0 base address */
+#define WAKETIMER0_BASE                          (0x400AE000u)
+/** Peripheral WAKETIMER0 base pointer */
+#define WAKETIMER0                               ((WAKETIMER_Type *)WAKETIMER0_BASE)
+/** Array initializer of WAKETIMER peripheral base addresses */
+#define WAKETIMER_BASE_ADDRS                     { WAKETIMER0_BASE }
+/** Array initializer of WAKETIMER peripheral base pointers */
+#define WAKETIMER_BASE_PTRS                      { WAKETIMER0 }
+/** Interrupt vectors for the WAKETIMER peripheral type */
+#define WAKETIMER_IRQS                           { WAKETIMER0_IRQn }
+
+/* WUU - Peripheral instance base addresses */
+/** Peripheral WUU0 base address */
+#define WUU0_BASE                                (0x40092000u)
+/** Peripheral WUU0 base pointer */
+#define WUU0                                     ((WUU_Type *)WUU0_BASE)
+/** Array initializer of WUU peripheral base addresses */
+#define WUU_BASE_ADDRS                           { WUU0_BASE }
+/** Array initializer of WUU peripheral base pointers */
+#define WUU_BASE_PTRS                            { WUU0 }
+
+/* WWDT - Peripheral instance base addresses */
+/** Peripheral WWDT0 base address */
+#define WWDT0_BASE                               (0x4000C000u)
+/** Peripheral WWDT0 base pointer */
+#define WWDT0                                    ((WWDT_Type *)WWDT0_BASE)
+/** Array initializer of WWDT peripheral base addresses */
+#define WWDT_BASE_ADDRS                          { WWDT0_BASE }
+/** Array initializer of WWDT peripheral base pointers */
+#define WWDT_BASE_PTRS                           { WWDT0 }
+
+/* ----------------------------------------------------------------------------
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDK Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif  /* MCXA343_COMMON_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343_features.h
new file mode 100644
index 0000000000..f6ece55889
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343_features.h
@@ -0,0 +1,898 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2024-03-26
+**     Build:               b250814
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**
+** ###################################################################
+*/
+
+#ifndef _MCXA343_FEATURES_H_
+#define _MCXA343_FEATURES_H_
+
+/* SOC module features */
+
+#if defined(CPU_MCXA343VFM)
+    /* @brief AOI availability on the SoC. */
+    #define FSL_FEATURE_SOC_AOI_COUNT (2)
+    /* @brief CDOG availability on the SoC. */
+    #define FSL_FEATURE_SOC_CDOG_COUNT (1)
+    /* @brief CMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMC_COUNT (1)
+    /* @brief CRC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CRC_COUNT (1)
+    /* @brief CTIMER availability on the SoC. */
+    #define FSL_FEATURE_SOC_CTIMER_COUNT (3)
+    /* @brief EDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_EDMA_COUNT (1)
+    /* @brief EIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EIM_COUNT (1)
+    /* @brief EQDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_EQDC_COUNT (2)
+    /* @brief FLEXCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
+    /* @brief FMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_FMC_COUNT (1)
+    /* @brief FREQME availability on the SoC. */
+    #define FSL_FEATURE_SOC_FREQME_COUNT (1)
+    /* @brief GPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_GPIO_COUNT (5)
+    /* @brief SPC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SPC_COUNT (1)
+    /* @brief INPUTMUX availability on the SoC. */
+    #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+    /* @brief LPADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPADC_COUNT (2)
+    /* @brief LPCMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPCMP_COUNT (3)
+    /* @brief LPI2C availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPI2C_COUNT (2)
+    /* @brief LPSPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPSPI_COUNT (2)
+    /* @brief LPTMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+    /* @brief LPUART availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPUART_COUNT (4)
+    /* @brief OPAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_OPAMP_COUNT (1)
+    /* @brief OSTIMER availability on the SoC. */
+    #define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
+    /* @brief PORT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PORT_COUNT (5)
+    /* @brief PWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWM_COUNT (2)
+    /* @brief RTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_RTC_COUNT (1)
+    /* @brief SCG availability on the SoC. */
+    #define FSL_FEATURE_SOC_SCG_COUNT (1)
+    /* @brief SMARTDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1)
+    /* @brief SYSCON availability on the SoC. */
+    #define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+    /* @brief UTICK availability on the SoC. */
+    #define FSL_FEATURE_SOC_UTICK_COUNT (1)
+    /* @brief WAKETIMER availability on the SoC. */
+    #define FSL_FEATURE_SOC_WAKETIMER_COUNT (1)
+    /* @brief WWDT availability on the SoC. */
+    #define FSL_FEATURE_SOC_WWDT_COUNT (1)
+    /* @brief WUU availability on the SoC. */
+    #define FSL_FEATURE_SOC_WUU_COUNT (1)
+#elif defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)
+    /* @brief AOI availability on the SoC. */
+    #define FSL_FEATURE_SOC_AOI_COUNT (2)
+    /* @brief CDOG availability on the SoC. */
+    #define FSL_FEATURE_SOC_CDOG_COUNT (1)
+    /* @brief CMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMC_COUNT (1)
+    /* @brief CRC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CRC_COUNT (1)
+    /* @brief CTIMER availability on the SoC. */
+    #define FSL_FEATURE_SOC_CTIMER_COUNT (3)
+    /* @brief EDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_EDMA_COUNT (1)
+    /* @brief EIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EIM_COUNT (1)
+    /* @brief EQDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_EQDC_COUNT (2)
+    /* @brief FLEXCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
+    /* @brief FMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_FMC_COUNT (1)
+    /* @brief FREQME availability on the SoC. */
+    #define FSL_FEATURE_SOC_FREQME_COUNT (1)
+    /* @brief GPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_GPIO_COUNT (5)
+    /* @brief SPC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SPC_COUNT (1)
+    /* @brief INPUTMUX availability on the SoC. */
+    #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+    /* @brief LPADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPADC_COUNT (2)
+    /* @brief LPCMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPCMP_COUNT (3)
+    /* @brief LPI2C availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPI2C_COUNT (2)
+    /* @brief LPSPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPSPI_COUNT (2)
+    /* @brief LPTMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+    /* @brief LPUART availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPUART_COUNT (4)
+    /* @brief OPAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_OPAMP_COUNT (3)
+    /* @brief OSTIMER availability on the SoC. */
+    #define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
+    /* @brief PORT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PORT_COUNT (5)
+    /* @brief PWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWM_COUNT (2)
+    /* @brief RTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_RTC_COUNT (1)
+    /* @brief SCG availability on the SoC. */
+    #define FSL_FEATURE_SOC_SCG_COUNT (1)
+    /* @brief SMARTDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1)
+    /* @brief SYSCON availability on the SoC. */
+    #define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+    /* @brief UTICK availability on the SoC. */
+    #define FSL_FEATURE_SOC_UTICK_COUNT (1)
+    /* @brief WAKETIMER availability on the SoC. */
+    #define FSL_FEATURE_SOC_WAKETIMER_COUNT (1)
+    /* @brief WWDT availability on the SoC. */
+    #define FSL_FEATURE_SOC_WWDT_COUNT (1)
+    /* @brief WUU availability on the SoC. */
+    #define FSL_FEATURE_SOC_WUU_COUNT (1)
+#endif
+
+/* LPADC module features */
+
+/* @brief FIFO availability on the SoC. */
+#define FSL_FEATURE_LPADC_FIFO_COUNT (1)
+/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */
+#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1)
+/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)
+/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
+/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
+/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)
+/* @brief Has conversion resolution select  (bitfield CMDLn[MODE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)
+/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
+#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
+/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)
+/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)
+/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)
+/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
+/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
+/* @brief Has calibration (bitfield CFG[CALOFS]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
+/* @brief Has offset trim (register OFSTRIM). */
+#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
+/* @brief Has power select (bitfield CFG[PWRSEL]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1)
+/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0)
+/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0)
+/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0)
+/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
+/* @brief Conversion averaged bitfiled width. */
+#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4)
+/* @brief Enable hardware trigger command selection */
+#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0)
+/* @brief OFSTRIM availability on the SoC. */
+#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1)
+/* @brief Has Trigger status register. */
+#define FSL_FEATURE_LPADC_HAS_TSTAT (1)
+/* @brief Has B side channels. */
+#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0)
+/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */
+#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1)
+/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */
+#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1)
+/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */
+#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1)
+/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */
+#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1)
+/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */
+#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1)
+/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */
+#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1)
+/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1)
+/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1)
+/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1)
+/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */
+#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2)
+/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
+#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
+/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1)
+/* @brief Has internal temperature sensor. */
+#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1)
+/* @brief Temperature sensor parameter A (slope). */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (738.0f)
+/* @brief Temperature sensor parameter B (offset). */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (287.5f)
+/* @brief Temperature sensor parameter Alpha. */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (10.06f)
+/* @brief The buffer size of temperature sensor. */
+#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U)
+
+/* AOI module features */
+
+/* @brief Maximum value of input mux. */
+#define FSL_FEATURE_AOI_MODULE_INPUTS (4)
+/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */
+#define FSL_FEATURE_AOI_EVENT_COUNT (4)
+
+/* FLEXCAN module features */
+
+/* @brief Message buffer size */
+#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32)
+/* @brief Has doze mode support (register bit field MCR[DOZE]). */
+#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1)
+/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1)
+/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
+#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
+/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
+#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
+/* @brief Instance has extended bit timing register (register CBT). */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1)
+/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
+#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1)
+/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1)
+/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
+#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1)
+/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1)
+/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
+/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0)
+/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0)
+/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0)
+/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
+#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1)
+/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1)
+/* @brief Has memory error control (register MECR). */
+#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0)
+/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */
+#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1)
+/* @brief Has Pretended Networking mode support. */
+#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1)
+/* @brief Has Enhanced Rx FIFO. */
+#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1)
+/* @brief Has Enhanced Rx FIFO. */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1)
+/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */
+#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12)
+/* @brief The number of enhanced Rx FIFO filter element registers. */
+#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32)
+/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */
+#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0)
+/* @brief Has more than 64 MBs. */
+#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0)
+/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */
+#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0)
+/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */
+#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0)
+/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0)
+/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */
+#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0)
+/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1)
+/* @brief FlexCAN maximum data rate. */
+#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000)
+/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */
+#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (1)
+/* @brief Enter Freeze mode before entering Disable and Stop mode. */
+#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0)
+/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0)
+/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0)
+/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */
+#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0)
+
+/* CDOG module features */
+
+/* @brief SOC has no reset driver. */
+#define FSL_FEATURE_CDOG_HAS_NO_RESET (1)
+/* @brief CDOG Load default configurations during init function */
+#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0)
+
+/* CMC module features */
+
+/* @brief Has SRAM_DIS register */
+#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (0)
+/* @brief Has BSR register */
+#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (0)
+/* @brief Has RSTCNT register */
+#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (0)
+/* @brief Has BLR register */
+#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0)
+
+/* LPCMP module features */
+
+/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1)
+/* @brief Has IER RRF_IE bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1)
+/* @brief Has CSR RRF bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1)
+/* @brief Has Round Robin mode (related to existence of registers RRCR0). */
+#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1)
+/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */
+#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1)
+/* @brief Has CCR0 CMP_STOP_EN bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1)
+/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */
+#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1)
+
+/* CTIMER module features */
+
+/* @brief CTIMER has no capture channel. */
+#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0)
+/* @brief CTIMER has no capture 2 interrupt. */
+#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0)
+/* @brief CTIMER capture 3 interrupt. */
+#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
+/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */
+#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0)
+/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */
+#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
+/* @brief CTIMER Has register MSR */
+#define FSL_FEATURE_CTIMER_HAS_MSR (1)
+
+/* EDMA module features */
+
+/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8)
+/* @brief If 8 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
+/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
+/* @brief If 16 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1)
+/* @brief Has DMA_Error interrupt vector. */
+#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
+/* @brief If 64 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1)
+/* @brief whether has prot register */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0)
+/* @brief If 128 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1)
+/* @brief whether has MP channel mux */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0)
+/* @brief If 128 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1)
+/* @brief If channel clock controlled independently */
+#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1)
+/* @brief Has register CH_CSR. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1)
+/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */
+#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (8)
+/* @brief Has channel mux */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1)
+/* @brief Has no register bit fields MP_CSR[EBW]. */
+#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1)
+/* @brief Instance has channel mux */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1)
+/* @brief If dma has common clock gate */
+#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0)
+/* @brief Has register CH_SBR. */
+#define FSL_FEATURE_EDMA_HAS_SBR (1)
+/* @brief If dma channel IRQ support parameter */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0)
+/* @brief Has no register bit fields CH_SBR[ATTR]. */
+#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1)
+/* @brief NBYTES must be multiple of 8 when using scatter gather. */
+#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0)
+/* @brief Has register bit field CH_CSR[SWAP]. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0)
+/* @brief NBYTES must be multiple of 8 when using scatter gather. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0)
+/* @brief Instance has register bit field CH_CSR[SWAP]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0)
+/* @brief Has register bit fields MP_CSR[GMRC]. */
+#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1)
+/* @brief Has register bit field CH_SBR[INSTR]. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0)
+/* @brief Instance has register bit field CH_SBR[INSTR]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0)
+/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE  (0)
+/* @brief Instance has register CH_MATTR. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0)
+/* @brief Has register bit field CH_CSR[SIGNEXT]. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0)
+/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0)
+/* @brief Has register bit field TCD_CSR[BWC]. */
+#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1)
+/* @brief Instance has register bit field TCD_CSR[BWC]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1)
+/* @brief Has register bit fields TCD_CSR[TMC]. */
+#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0)
+/* @brief Instance has register bit fields TCD_CSR[TMC]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0)
+/* @brief Has no register bit fields CH_SBR[SEC]. */
+#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1)
+/* @brief edma5 has different tcd type. */
+#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0)
+
+/* EQDC module features */
+
+/* @brief If EQDC CTRL2 register has EMIP bit field. */
+#define FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD (1)
+
+/* PWM module features */
+
+/* @brief If (e)FlexPWM has module A channels (outputs). */
+#define FSL_FEATURE_PWM_HAS_CHANNELA (1)
+/* @brief If (e)FlexPWM has module B channels (outputs). */
+#define FSL_FEATURE_PWM_HAS_CHANNELB (1)
+/* @brief If (e)FlexPWM has module X channels (outputs). */
+#define FSL_FEATURE_PWM_HAS_CHANNELX (1)
+/* @brief If (e)FlexPWM has fractional feature. */
+#define FSL_FEATURE_PWM_HAS_FRACTIONAL (0)
+/* @brief If (e)FlexPWM has mux trigger source select bit field. */
+#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1)
+/* @brief Number of submodules in each (e)FlexPWM module. */
+#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4)
+/* @brief Number of fault channel in each (e)FlexPWM module. */
+#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1)
+/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */
+#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1)
+/* @brief If (e)FlexPWM has phase delay feature. */
+#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1)
+/* @brief If (e)FlexPWM has input filter capture feature. */
+#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1)
+/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */
+#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (0)
+/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */
+#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0)
+/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */
+#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1)
+/* @brief Is affected by errata with ID 51989. */
+#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0)
+
+/* FMU module features */
+
+/* @brief Is the flash module msf1? */
+#define FSL_FEATURE_FSL_FEATURE_FLASH_IS_MSF1 (1)
+/* @brief P-Flash block count. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
+/* @brief P-Flash block0 start address. */
+#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U)
+/* @brief P-Flash block0 size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U)
+/* @brief P-Flash sector size. */
+#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U)
+/* @brief P-Flash page size. */
+#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128)
+/* @brief P-Flash phrase size. */
+#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16)
+/* @brief Has IFR memory. */
+#define FSL_FEATURE_FLASH_HAS_IFR (1)
+/* @brief flash BLOCK0 IFR0 start address. */
+#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u)
+/* @brief flash BLOCK0 IFR1 start address. */
+#define FSL_FEATURE_FLASH_IFR1_START_ADDRESS (0x01100000U)
+/* @brief flash block IFR0 size. */
+#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U)
+/* @brief flash block IFR1 size. */
+#define FSL_FEATURE_FLASH_IFR1_SIZE (0x2000U)
+/* @brief IFR sector size. */
+#define FSL_FEATURE_FLASH_IFR_SECTOR_SIZE (0x2000U)
+/* @brief IFR page size. */
+#define FSL_FEATURE_FLASH_IFR_PAGE_SIZE (128)
+
+/* GLIKEY module features */
+
+/* @brief GLIKEY has 8 step FSM configuration */
+#define FSL_FEATURE_GLIKEY_HAS_EIGHT_STEPS (0)
+
+/* GPIO module features */
+
+/* @brief Has GPIO attribute checker register (GACR). */
+#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0)
+/* @brief Has GPIO version ID register (VERID). */
+#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1)
+/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */
+#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0)
+/* @brief Has GPIO port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1)
+/* @brief Has GPIO interrupt/DMA request/trigger output selection. */
+#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0)
+
+/* LPI2C module features */
+
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
+/* @brief Has dedicated interrupt for master and slave. */
+#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0)
+
+/* LPSPI module features */
+
+/* @brief Capacity (number of entries) of the transmit/receive FIFO. */
+#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Has CCR1 (related to existence of registers CCR1). */
+#define FSL_FEATURE_LPSPI_HAS_CCR1 (1)
+/* @brief Has no PCSCFG bit in CFGR1 register. */
+#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0)
+/* @brief Has no WIDTH bits in TCR register. */
+#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0)
+
+/* LPTMR module features */
+
+/* @brief Has shared interrupt handler with another LPTMR module. */
+#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+/* @brief Whether LPTMR counter is 32 bits width. */
+#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1)
+/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
+#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1)
+/* @brief Do not has prescaler clock source 0. */
+#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1)
+/* @brief Do not has prescaler clock source 1. */
+#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0)
+/* @brief Do not has prescaler clock source 2. */
+#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1)
+/* @brief Do not has prescaler clock source 3. */
+#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0)
+
+/* LPUART module features */
+
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_HAS_FIFO (1)
+/* @brief Has 32-bit register MODIR */
+#define FSL_FEATURE_LPUART_HAS_MODIR (1)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief If 10-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
+/* @brief If 7-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_LPUART_IS_SCI (1)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
+/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
+#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0)
+/* @brief Has separate RX and TX interrupts. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
+/* @brief Has LPAURT_PARAM. */
+#define FSL_FEATURE_LPUART_HAS_PARAM (1)
+/* @brief Has LPUART_VERID. */
+#define FSL_FEATURE_LPUART_HAS_VERID (1)
+/* @brief Has LPUART_GLOBAL. */
+#define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
+/* @brief Has LPUART_PINCFG. */
+#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
+/* @brief Belong to LPFLEXCOMM */
+#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0)
+/* @brief Has register MODEM Control. */
+#define FSL_FEATURE_LPUART_HAS_MCR (0)
+/* @brief Has register Half Duplex Control. */
+#define FSL_FEATURE_LPUART_HAS_HDCR (0)
+/* @brief Has register Timeout. */
+#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0)
+/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */
+#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4)
+/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */
+#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1)
+
+/* MAU module features */
+
+/* @brief Indirect operation is in low address. */
+#define FSL_FEATURE_MAU_INDIRECT_IS_LOW_ADDR  (1)
+
+/* TRDC module features */
+
+/* @brief Process master count. */
+#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2)
+/* @brief TRDC instance has PID configuration or not. */
+#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0)
+/* @brief TRDC instance has MBC. */
+#define FSL_FEATURE_TRDC_HAS_MBC (1)
+/* @brief TRDC instance has MRC. */
+#define FSL_FEATURE_TRDC_HAS_MRC (0)
+/* @brief TRDC instance has TRDC_CR. */
+#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0)
+/* @brief TRDC instance has MDA_Wx_y_DFMT. */
+#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0)
+/* @brief TRDC instance has TRDC_FDID. */
+#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0)
+/* @brief TRDC instance has TRDC_FLW_CTL. */
+#define FSL_FEATURE_TRDC_HAS_FLW (0)
+
+/* OPAMP module features */
+
+/* @brief Opamp has OPAMP_CTR OUTSW bit */
+#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (0)
+/* @brief Opamp has OPAMP_CTR ADCSW1 bit */
+#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (0)
+/* @brief Opamp has OPAMP_CTR ADCSW2 bit */
+#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (0)
+/* @brief Opamp has OPAMP_CTR BUFEN bit */
+#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (0)
+/* @brief Opamp has OPAMP_CTR INPSEL bit */
+#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (0)
+/* @brief Opamp has OPAMP_CTR TRIGMD bit */
+#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (0)
+/* @brief OPAMP support reference buffer */
+#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
+/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Do not has interrupt control (register ISFR). */
+#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1)
+/* @brief Has pull value (register bit field PCR[PV]). */
+#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1)
+/* @brief Has drive strength1 control (register bit PCR[DSE1]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1)
+/* @brief Has version ID register (register VERID). */
+#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1)
+/* @brief Has voltage range control (register bit CONFIG[RANGE]). */
+#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1)
+/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */
+#define FSL_FEATURE_PORT_SUPPORT_EFT (0)
+/* @brief Function 0 is GPIO. */
+#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
+/* @brief Defines width of PCR[MUX] field. */
+#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
+/* @brief Has independent interrupt control(register ICR). */
+#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0)
+/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
+#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
+/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */
+#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1)
+/* @brief Has Invert Input (register bit field PCR[INV]). */
+#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1)
+/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
+
+/* RTC module features */
+
+/* @brief Has wakeup pin. */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0)
+/* @brief Has wakeup pin selection (bit field CR[WPS]). */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0)
+/* @brief Has low power features (registers MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+/* @brief Has read/write access control (registers WAR and RAR). */
+#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
+/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_SECURITY (0)
+/* @brief Has RTC_CLKIN available. */
+#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
+/* @brief Has prescaler adjust for LPO. */
+#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1)
+/* @brief Has Clock Pin Enable field. */
+#define FSL_FEATURE_RTC_HAS_CPE (0)
+/* @brief Has Timer Seconds Interrupt Configuration field. */
+#define FSL_FEATURE_RTC_HAS_TSIC (1)
+/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
+#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0)
+/* @brief Has Tamper Interrupt Register (register TIR). */
+#define FSL_FEATURE_RTC_HAS_TIR (0)
+/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
+#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0)
+/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
+#define FSL_FEATURE_RTC_HAS_TIR_SIE (0)
+/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
+#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0)
+/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
+#define FSL_FEATURE_RTC_HAS_SR_TIDF (0)
+/* @brief Has Tamper Detect Register (register TDR). */
+#define FSL_FEATURE_RTC_HAS_TDR (0)
+/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
+#define FSL_FEATURE_RTC_HAS_TDR_TPF (0)
+/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
+#define FSL_FEATURE_RTC_HAS_TDR_STF (0)
+/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
+#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0)
+/* @brief Has Tamper Time Seconds Register (register TTSR). */
+#define FSL_FEATURE_RTC_HAS_TTSR (0)
+/* @brief Has Pin Configuration Register (register PCR). */
+#define FSL_FEATURE_RTC_HAS_PCR (0)
+/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */
+#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1)
+/* @brief Has no supervisor access bit (CR[SUP]). */
+#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1)
+/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */
+#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0)
+/* @brief Has clock output bit (CR[CLKO]). */
+#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0)
+
+/* SPC module features */
+
+/* @brief Has DCDC */
+#define FSL_FEATURE_MCX_SPC_HAS_DCDC (0)
+/* @brief Has SYS LDO */
+#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (0)
+/* @brief Has IOVDD_LVDF */
+#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (0)
+/* @brief Has COREVDD_HVDF */
+#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (0)
+/* @brief Has CORELDO_VDD_DS */
+#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1)
+/* @brief Has LPBUFF_EN */
+#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (0)
+/* @brief Has COREVDD_IVS_EN */
+#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (0)
+/* @brief Has SWITCH_STATE */
+#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0)
+/* @brief Has SRAMRETLDO */
+#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (1)
+/* @brief Has CFG register */
+#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0)
+/* @brief Has SRAMLDO_DPD_ON */
+#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (1)
+/* @brief Has CNTRL register */
+#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1)
+/* @brief Has DPDOWN_PULLDOWN_DISABLE */
+#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0)
+/* @brief Not have glitch detect */
+#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (0)
+/* @brief Has BLEED_EN */
+#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (0)
+/* @brief Has Power Request Status Flag */
+#define FSL_FEATURE_MCX_SPC_HAS_PD_STATUS_PWR_REQ_STATUS_BIT (0)
+
+/* SYSCON module features */
+
+/* @brief Flash page size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128)
+/* @brief Flash sector size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192)
+/* @brief Flash size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (122880)
+/* @brief Support ROMAPI */
+#define FSL_FEATURE_SYSCON_ROMAPI (1)
+/* @brief ROMAPI tree address */
+#define FSL_FEATURE_ROMAPI_BASE (0x03005FE0U)
+/* @brief ROMAPI support IFR function */
+#define FSL_FEATURE_ROMAPI_IFR (0)
+/* @brief Powerlib API is different with other series devices */
+#define FSL_FEATURE_POWERLIB_EXTEND (1)
+/* @brief No OSTIMER register in PMC */
+#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1)
+/* @brief Starter register discontinuous. */
+#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
+/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */
+#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (0)
+/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */
+#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (0)
+
+/* UTICK module features */
+
+/* @brief UTICK does not support power down configure. */
+#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
+
+/* VBAT module features */
+
+/* @brief Has STATUS register */
+#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (0)
+/* @brief Has TAMPER register */
+#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (0)
+/* @brief Has BANDGAP register */
+#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (0)
+/* @brief Has LDOCTL register */
+#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (0)
+/* @brief Has OSCCTL register */
+#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (0)
+/* @brief Has SWICTL register */
+#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (0)
+/* @brief Has CLKMON register */
+#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0)
+
+/* WWDT module features */
+
+/* @brief WWDT does not support oscillator lock. */
+#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0)
+/* @brief soc has reset. */
+#define FSL_FEATURE_WWDT_HAS_NO_RESET (1)
+/* @brief Has LPOSC as clock source. */
+#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0)
+/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */
+#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0)
+
+#endif /* _MCXA343_FEATURES_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/fsl_device_registers.h
new file mode 100644
index 0000000000..696bf96564
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/fsl_device_registers.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2025 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/startup_MCXA343.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/startup_MCXA343.c
new file mode 100644
index 0000000000..ea271db1a3
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/startup_MCXA343.c
@@ -0,0 +1,1464 @@
+//*****************************************************************************
+// MCXA343 startup code
+//
+// Version : 060825
+//*****************************************************************************
+//
+// Copyright 2016-2025 NXP
+//
+// SPDX-License-Identifier: BSD-3-Clause
+//*****************************************************************************
+#include <stdint.h>
+
+#if defined(DEBUG)
+#if defined(__GNUC__)
+#pragma GCC push_options
+#pragma GCC optimize("Og")
+#endif //(__GNUC__)
+#endif //(DEBUG)
+
+#if defined(__cplusplus)
+#if defined(__MCUXPRESSO)
+#if defined(__REDLIB__)
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+extern void __libc_init_array(void);
+}
+#endif //(__REDLIB__)
+#endif //(__MCUXPRESSO)
+#endif //(__cplusplus)
+
+#define WEAK __attribute__((weak))
+#if defined(__MCUXPRESSO)
+#define WEAK_AV __attribute__((weak, section(".after_vectors")))
+#else
+#define WEAK_AV __attribute__((weak))
+#endif //(__MCUXPRESSO)
+#define ALIAS(f) __attribute__((weak, alias(#f)))
+
+//*****************************************************************************
+#if defined(__cplusplus)
+extern "C" {
+#endif //(__cplusplus)
+
+//*****************************************************************************
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+//*****************************************************************************
+//*****************************************************************************
+// Declaration of external SystemInit function
+//*****************************************************************************
+extern void SystemInit(void);
+
+//*****************************************************************************
+// Forward declaration of the core exception handlers.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions.
+// If your application is a C++ one, then any interrupt handlers defined
+// in C++ files within in your main application will need to have C linkage
+// rather than C++ linkage. To do this, make sure that you are using extern "C"
+// { .... } around the interrupt handler within your main application code.
+//*****************************************************************************
+#if defined(__MCUXPRESSO)
+void ResetISR(void);
+#else
+void Reset_Handler(void);
+#endif //(__MCUXPRESSO)
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SecureFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void DefaultISR(void);
+
+//*****************************************************************************
+// Forward declaration of the application IRQ handlers. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over weak definitions below
+//*****************************************************************************
+WEAK void Reserved16_IRQHandler(void);
+WEAK void CMC_IRQHandler(void);
+WEAK void DMA_CH0_IRQHandler(void);
+WEAK void DMA_CH1_IRQHandler(void);
+WEAK void DMA_CH2_IRQHandler(void);
+WEAK void DMA_CH3_IRQHandler(void);
+WEAK void DMA_CH4_IRQHandler(void);
+WEAK void DMA_CH5_IRQHandler(void);
+WEAK void DMA_CH6_IRQHandler(void);
+WEAK void DMA_CH7_IRQHandler(void);
+WEAK void ERM0_SINGLE_BIT_IRQHandler(void);
+WEAK void ERM0_MULTI_BIT_IRQHandler(void);
+WEAK void FMU0_IRQHandler(void);
+WEAK void GLIKEY0_IRQHandler(void);
+WEAK void MBC0_IRQHandler(void);
+WEAK void SCG0_IRQHandler(void);
+WEAK void SPC0_IRQHandler(void);
+WEAK void Reserved33_IRQHandler(void);
+WEAK void WUU0_IRQHandler(void);
+WEAK void CAN0_IRQHandler(void);
+WEAK void Reserved36_IRQHandler(void);
+WEAK void Reserved37_IRQHandler(void);
+WEAK void Reserved38_IRQHandler(void);
+WEAK void Reserved39_IRQHandler(void);
+WEAK void Reserved40_IRQHandler(void);
+WEAK void Reserved41_IRQHandler(void);
+WEAK void LPI2C0_IRQHandler(void);
+WEAK void LPI2C1_IRQHandler(void);
+WEAK void LPSPI0_IRQHandler(void);
+WEAK void LPSPI1_IRQHandler(void);
+WEAK void Reserved46_IRQHandler(void);
+WEAK void LPUART0_IRQHandler(void);
+WEAK void LPUART1_IRQHandler(void);
+WEAK void LPUART2_IRQHandler(void);
+WEAK void LPUART3_IRQHandler(void);
+WEAK void Reserved51_IRQHandler(void);
+WEAK void Reserved52_IRQHandler(void);
+WEAK void Reserved53_IRQHandler(void);
+WEAK void CDOG0_IRQHandler(void);
+WEAK void CTIMER0_IRQHandler(void);
+WEAK void CTIMER1_IRQHandler(void);
+WEAK void CTIMER2_IRQHandler(void);
+WEAK void Reserved58_IRQHandler(void);
+WEAK void Reserved59_IRQHandler(void);
+WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void);
+WEAK void FLEXPWM0_FAULT_IRQHandler(void);
+WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void);
+WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void);
+WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void);
+WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void);
+WEAK void EQDC0_COMPARE_IRQHandler(void);
+WEAK void EQDC0_HOME_IRQHandler(void);
+WEAK void EQDC0_WATCHDOG_IRQHandler(void);
+WEAK void EQDC0_INDEX_IRQHandler(void);
+WEAK void FREQME0_IRQHandler(void);
+WEAK void LPTMR0_IRQHandler(void);
+WEAK void Reserved72_IRQHandler(void);
+WEAK void OS_EVENT_IRQHandler(void);
+WEAK void WAKETIMER0_IRQHandler(void);
+WEAK void UTICK0_IRQHandler(void);
+WEAK void WWDT0_IRQHandler(void);
+WEAK void Reserved77_IRQHandler(void);
+WEAK void ADC0_IRQHandler(void);
+WEAK void ADC1_IRQHandler(void);
+WEAK void CMP0_IRQHandler(void);
+WEAK void CMP1_IRQHandler(void);
+WEAK void CMP2_IRQHandler(void);
+WEAK void Reserved83_IRQHandler(void);
+WEAK void Reserved84_IRQHandler(void);
+WEAK void Reserved85_IRQHandler(void);
+WEAK void Reserved86_IRQHandler(void);
+WEAK void GPIO0_IRQHandler(void);
+WEAK void GPIO1_IRQHandler(void);
+WEAK void GPIO2_IRQHandler(void);
+WEAK void GPIO3_IRQHandler(void);
+WEAK void GPIO4_IRQHandler(void);
+WEAK void Reserved92_IRQHandler(void);
+WEAK void Reserved93_IRQHandler(void);
+WEAK void Reserved94_IRQHandler(void);
+WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void);
+WEAK void FLEXPWM1_FAULT_IRQHandler(void);
+WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void);
+WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void);
+WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void);
+WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void);
+WEAK void EQDC1_COMPARE_IRQHandler(void);
+WEAK void EQDC1_HOME_IRQHandler(void);
+WEAK void EQDC1_WATCHDOG_IRQHandler(void);
+WEAK void EQDC1_INDEX_IRQHandler(void);
+WEAK void Reserved105_IRQHandler(void);
+WEAK void Reserved106_IRQHandler(void);
+WEAK void Reserved107_IRQHandler(void);
+WEAK void Reserved108_IRQHandler(void);
+WEAK void Reserved109_IRQHandler(void);
+WEAK void Reserved110_IRQHandler(void);
+WEAK void Reserved111_IRQHandler(void);
+WEAK void Reserved112_IRQHandler(void);
+WEAK void Reserved113_IRQHandler(void);
+WEAK void Reserved114_IRQHandler(void);
+WEAK void Reserved115_IRQHandler(void);
+WEAK void Reserved116_IRQHandler(void);
+WEAK void Reserved117_IRQHandler(void);
+WEAK void Reserved118_IRQHandler(void);
+WEAK void Reserved119_IRQHandler(void);
+WEAK void Reserved120_IRQHandler(void);
+WEAK void Reserved121_IRQHandler(void);
+WEAK void Reserved122_IRQHandler(void);
+WEAK void MAU_IRQHandler(void);
+WEAK void SMARTDMA_IRQHandler(void);
+WEAK void Reserved125_IRQHandler(void);
+WEAK void Reserved126_IRQHandler(void);
+WEAK void Reserved127_IRQHandler(void);
+WEAK void Reserved128_IRQHandler(void);
+WEAK void Reserved129_IRQHandler(void);
+WEAK void Reserved130_IRQHandler(void);
+WEAK void Reserved131_IRQHandler(void);
+WEAK void Reserved132_IRQHandler(void);
+WEAK void Reserved133_IRQHandler(void);
+WEAK void Reserved134_IRQHandler(void);
+WEAK void RTC_IRQHandler(void);
+WEAK void RTC_1HZ_IRQHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the driver IRQ handlers. These are aliased
+// to the DefaultISR, which is a 'forever' loop. When the driver
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//*****************************************************************************
+void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CMC_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR);
+void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved33_DriverIRQHandler(void) ALIAS(DefaultISR);
+void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved39_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved40_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved51_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved52_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved58_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR);
+void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR);
+void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CMP2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved83_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved93_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved94_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved111_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR);
+void MAU_DriverIRQHandler(void) ALIAS(DefaultISR);
+void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved125_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR);
+void RTC_DriverIRQHandler(void) ALIAS(DefaultISR);
+void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR);
+
+//*****************************************************************************
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//*****************************************************************************
+#if defined(__MCUXPRESSO)
+#if defined(__REDLIB__)
+extern void __main(void);
+#else
+extern int main(void);
+#endif //(__REDLIB__)
+#elif defined(__ICCARM__)
+extern void __iar_program_start(void);
+#elif defined(__GNUC__)
+#if defined(__REDLIB__)
+extern void __main(void);
+#else
+extern void _start(void);
+#endif //(__REDLIB__)
+#else
+#error Unsupported toolchain!
+#endif //(__MCUXPRESSO)
+
+//*****************************************************************************
+// External declaration for the pointer from the Linker Script
+//*****************************************************************************
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[];
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+#define _vStackTop  Image$$ARM_LIB_STACK$$ZI$$Limit
+#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base
+#elif defined(__MCUXPRESSO)
+extern void _vStackTop(void);
+extern void _vStackBase(void);
+#define Reset_Handler ResetISR // To be compatible with other compilers
+#elif defined(__ICCARM__)
+#pragma segment = "CSTACK"
+#define _vStackTop  __section_end("CSTACK")
+#define _vStackBase __section_begin("CSTACK")
+#elif defined(__GNUC__)
+extern uint32_t __StackTop[];
+extern uint32_t __StackLimit[];
+
+#define _vStackTop  __StackTop
+#define _vStackBase __StackLimit
+
+extern uint32_t __etext[];
+extern uint32_t __data_start__[];
+extern uint32_t __data_end__[];
+
+extern uint32_t __bss_start__[];
+extern uint32_t __bss_end__[];
+#else
+#error Unsupported toolchain!
+#endif //(__CC_ARM) || (__ARMCC_VERSION)
+
+//*****************************************************************************
+#if defined(__cplusplus)
+} // extern "C"
+#endif //(__cplusplus)
+//*****************************************************************************
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//*****************************************************************************
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+extern void (*const __Vectors[])(void);
+#define __vector_table __Vectors
+__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = {
+#elif defined(__MCUXPRESSO)
+extern void (*const g_pfnVectors[])(void);
+extern void *__Vectors __attribute__((alias("g_pfnVectors")));
+#define __vector_table g_pfnVectors
+__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = {
+#elif defined(__ICCARM__)
+extern void (*const __vector_table[])(void);
+/* The vector table is not needed for initialization. */
+extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table")));
+__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = {
+#elif defined(__GNUC__)
+extern void (*const __isr_vector[])(void);
+#define __vector_table __isr_vector
+__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = {
+#else
+#error Unsupported toolchain!
+#endif //(__CC_ARM) || (__ARMCC_VERSION)
+    // Core Level - CM33
+    (void (*)())((uint32_t)_vStackTop), // The initial stack pointer
+    Reset_Handler,                      // The reset handler
+
+    NMI_Handler,                        // NMI Handler
+    HardFault_Handler,                  // Hard Fault Handler
+    MemManage_Handler,                  // MPU Fault Handler
+    BusFault_Handler,                   // Bus Fault Handler
+    UsageFault_Handler,                 // Usage Fault Handler
+    SecureFault_Handler,                // Secure Fault Handler
+    0,                                  // Reserved
+    0,                                  // Reserved
+    0,                                  // Reserved
+    SVC_Handler,                        // SVCall Handler
+    DebugMon_Handler,                   // Debug Monitor Handler
+    0,                                  // Reserved
+    PendSV_Handler,                     // PendSV Handler
+    SysTick_Handler,                    // SysTick Handler
+
+    // Chip Level - MCXA343
+    Reserved16_IRQHandler,            // 16 : Reserved interrupt
+    CMC_IRQHandler,                   // 17 : Core Mode Controller interrupt
+    DMA_CH0_IRQHandler,               // 18 : DMA3_0_CH0 error or transfer complete
+    DMA_CH1_IRQHandler,               // 19 : DMA3_0_CH1 error or transfer complete
+    DMA_CH2_IRQHandler,               // 20 : DMA3_0_CH2 error or transfer complete
+    DMA_CH3_IRQHandler,               // 21 : DMA3_0_CH3 error or transfer complete
+    DMA_CH4_IRQHandler,               // 22 : DMA3_0_CH4 error or transfer complete
+    DMA_CH5_IRQHandler,               // 23 : DMA3_0_CH5 error or transfer complete
+    DMA_CH6_IRQHandler,               // 24 : DMA3_0_CH6 error or transfer complete
+    DMA_CH7_IRQHandler,               // 25 : DMA3_0_CH7 error or transfer complete
+    ERM0_SINGLE_BIT_IRQHandler,       // 26 : ERM Single Bit error interrupt
+    ERM0_MULTI_BIT_IRQHandler,        // 27 : ERM Multi Bit error interrupt
+    FMU0_IRQHandler,                  // 28 : Flash Management Unit interrupt
+    GLIKEY0_IRQHandler,               // 29 : GLIKEY Interrupt
+    MBC0_IRQHandler,                  // 30 : MBC secure violation interrupt
+    SCG0_IRQHandler,                  // 31 : System Clock Generator interrupt
+    SPC0_IRQHandler,                  // 32 : System Power Controller interrupt
+    Reserved33_IRQHandler,            // 33 : Reserved interrupt
+    WUU0_IRQHandler,                  // 34 : Wake Up Unit interrupt
+    CAN0_IRQHandler,                  // 35 : Controller Area Network 0 interrupt
+    Reserved36_IRQHandler,            // 36 : Reserved interrupt
+    Reserved37_IRQHandler,            // 37 : Reserved interrupt
+    Reserved38_IRQHandler,            // 38 : Reserved interrupt
+    Reserved39_IRQHandler,            // 39 : Reserved interrupt
+    Reserved40_IRQHandler,            // 40 : Reserved interrupt
+    Reserved41_IRQHandler,            // 41 : Reserved interrupt
+    LPI2C0_IRQHandler,                // 42 : Low-Power Inter Integrated Circuit 0 interrupt
+    LPI2C1_IRQHandler,                // 43 : Low-Power Inter Integrated Circuit 1 interrupt
+    LPSPI0_IRQHandler,                // 44 : Low-Power Serial Peripheral Interface 0 interrupt
+    LPSPI1_IRQHandler,                // 45 : Low-Power Serial Peripheral Interface 1 interrupt
+    Reserved46_IRQHandler,            // 46 : Reserved interrupt
+    LPUART0_IRQHandler,               // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt
+    LPUART1_IRQHandler,               // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt
+    LPUART2_IRQHandler,               // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt
+    LPUART3_IRQHandler,               // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt
+    Reserved51_IRQHandler,            // 51 : Reserved interrupt
+    Reserved52_IRQHandler,            // 52 : Reserved interrupt
+    Reserved53_IRQHandler,            // 53 : Reserved interrupt
+    CDOG0_IRQHandler,                 // 54 : Code Watchdog Timer 0 interrupt
+    CTIMER0_IRQHandler,               // 55 : Standard counter/timer 0 interrupt
+    CTIMER1_IRQHandler,               // 56 : Standard counter/timer 1 interrupt
+    CTIMER2_IRQHandler,               // 57 : Standard counter/timer 2 interrupt
+    Reserved58_IRQHandler,            // 58 : Reserved interrupt
+    Reserved59_IRQHandler,            // 59 : Reserved interrupt
+    FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt
+    FLEXPWM0_FAULT_IRQHandler,        // 61 : FlexPWM0_fault interrupt
+    FLEXPWM0_SUBMODULE0_IRQHandler,   // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt
+    FLEXPWM0_SUBMODULE1_IRQHandler,   // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt
+    FLEXPWM0_SUBMODULE2_IRQHandler,   // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt
+    FLEXPWM0_SUBMODULE3_IRQHandler,   // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt
+    EQDC0_COMPARE_IRQHandler,         // 66 : Compare
+    EQDC0_HOME_IRQHandler,            // 67 : Home
+    EQDC0_WATCHDOG_IRQHandler,        // 68 : Watchdog / Simultaneous A and B Change
+    EQDC0_INDEX_IRQHandler,           // 69 : Index / Roll Over / Roll Under
+    FREQME0_IRQHandler,               // 70 : Frequency Measurement interrupt
+    LPTMR0_IRQHandler,                // 71 : Low Power Timer 0 interrupt
+    Reserved72_IRQHandler,            // 72 : Reserved interrupt
+    OS_EVENT_IRQHandler,              // 73 : OS event timer interrupt
+    WAKETIMER0_IRQHandler,            // 74 : Wake Timer Interrupt
+    UTICK0_IRQHandler,                // 75 : Micro-Tick Timer interrupt
+    WWDT0_IRQHandler,                 // 76 : Windowed Watchdog Timer 0 interrupt
+    Reserved77_IRQHandler,            // 77 : Reserved interrupt
+    ADC0_IRQHandler,                  // 78 : Analog-to-Digital Converter 0 interrupt
+    ADC1_IRQHandler,                  // 79 : Analog-to-Digital Converter 1 interrupt
+    CMP0_IRQHandler,                  // 80 : Comparator 0 interrupt
+    CMP1_IRQHandler,                  // 81 : Comparator 1 interrupt
+    CMP2_IRQHandler,                  // 82 : Comparator 2 interrupt
+    Reserved83_IRQHandler,            // 83 : Reserved interrupt
+    Reserved84_IRQHandler,            // 84 : Reserved interrupt
+    Reserved85_IRQHandler,            // 85 : Reserved interrupt
+    Reserved86_IRQHandler,            // 86 : Reserved interrupt
+    GPIO0_IRQHandler,                 // 87 : General Purpose Input/Output interrupt 0
+    GPIO1_IRQHandler,                 // 88 : General Purpose Input/Output interrupt 1
+    GPIO2_IRQHandler,                 // 89 : General Purpose Input/Output interrupt 2
+    GPIO3_IRQHandler,                 // 90 : General Purpose Input/Output interrupt 3
+    GPIO4_IRQHandler,                 // 91 : General Purpose Input/Output interrupt 4
+    Reserved92_IRQHandler,            // 92 : Reserved interrupt
+    Reserved93_IRQHandler,            // 93 : Reserved interrupt
+    Reserved94_IRQHandler,            // 94 : Reserved interrupt
+    FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt
+    FLEXPWM1_FAULT_IRQHandler,        // 96 : FlexPWM1_fault interrupt
+    FLEXPWM1_SUBMODULE0_IRQHandler,   // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt
+    FLEXPWM1_SUBMODULE1_IRQHandler,   // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt
+    FLEXPWM1_SUBMODULE2_IRQHandler,   // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt
+    FLEXPWM1_SUBMODULE3_IRQHandler,   // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt
+    EQDC1_COMPARE_IRQHandler,         // 101: Compare
+    EQDC1_HOME_IRQHandler,            // 102: Home
+    EQDC1_WATCHDOG_IRQHandler,        // 103: Watchdog / Simultaneous A and B Change
+    EQDC1_INDEX_IRQHandler,           // 104: Index / Roll Over / Roll Under
+    Reserved105_IRQHandler,           // 105: Reserved interrupt
+    Reserved106_IRQHandler,           // 106: Reserved interrupt
+    Reserved107_IRQHandler,           // 107: Reserved interrupt
+    Reserved108_IRQHandler,           // 108: Reserved interrupt
+    Reserved109_IRQHandler,           // 109: Reserved interrupt
+    Reserved110_IRQHandler,           // 110: Reserved interrupt
+    Reserved111_IRQHandler,           // 111: Reserved interrupt
+    Reserved112_IRQHandler,           // 112: Reserved interrupt
+    Reserved113_IRQHandler,           // 113: Reserved interrupt
+    Reserved114_IRQHandler,           // 114: Reserved interrupt
+    Reserved115_IRQHandler,           // 115: Reserved interrupt
+    Reserved116_IRQHandler,           // 116: Reserved interrupt
+    Reserved117_IRQHandler,           // 117: Reserved interrupt
+    Reserved118_IRQHandler,           // 118: Reserved interrupt
+    Reserved119_IRQHandler,           // 119: Reserved interrupt
+    Reserved120_IRQHandler,           // 120: Reserved interrupt
+    Reserved121_IRQHandler,           // 121: Reserved interrupt
+    Reserved122_IRQHandler,           // 122: Reserved interrupt
+    MAU_IRQHandler,                   // 123: MAU interrupt
+    SMARTDMA_IRQHandler,              // 124: SmartDMA interrupt
+    Reserved125_IRQHandler,           // 125: Reserved interrupt
+    Reserved126_IRQHandler,           // 126: Reserved interrupt
+    Reserved127_IRQHandler,           // 127: Reserved interrupt
+    Reserved128_IRQHandler,           // 128: Reserved interrupt
+    Reserved129_IRQHandler,           // 129: Reserved interrupt
+    Reserved130_IRQHandler,           // 130: Reserved interrupt
+    Reserved131_IRQHandler,           // 131: Reserved interrupt
+    Reserved132_IRQHandler,           // 132: Reserved interrupt
+    Reserved133_IRQHandler,           // 133: Reserved interrupt
+    Reserved134_IRQHandler,           // 134: Reserved interrupt
+    RTC_IRQHandler,                   // 135: RTC alarm interrupt
+    RTC_1HZ_IRQHandler,               // 136: RTC 1Hz interrupt
+};                                     /* End of __vector_table */
+
+#if defined(__MCUXPRESSO)
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors")));
+void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128)));
+unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors);
+#endif //(ENABLE_RAM_VECTOR_TABLE)
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart,
+                                                                    unsigned int start,
+                                                                    unsigned int len)
+{
+    unsigned int *pulDest = (unsigned int *)start;
+    unsigned int *pulSrc  = (unsigned int *)romstart;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = *pulSrc++;
+}
+
+__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len)
+{
+    unsigned int *pulDest = (unsigned int *)start;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+#endif //(__MCUXPRESSO)
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+__attribute__ ((used, section("InRoot$$Sections")))
+__attribute__ ((naked))
+#elif defined(__MCUXPRESSO)
+__attribute__ ((naked, section(".after_vectors.reset")))
+#elif defined(__ICCARM__)
+__stackless
+#elif defined(__GNUC__)
+__attribute__ ((naked))
+#endif //(__CC_ARM) || (__ARMCC_VERSION)
+void Reset_Handler(void)
+{
+    // Disable interrupts
+    __asm volatile("cpsid i");
+    // Config VTOR & MSP register
+    __asm volatile(
+        "LDR R0, =0xE000ED08  \n"
+        "STR %0, [R0]         \n"
+        "LDR R1, [%0]         \n"
+        "MSR MSP, R1          \n"
+        "MSR MSPLIM, %1       \n"
+        :
+        : "r"(__vector_table), "r"(_vStackBase)
+        : "r0", "r1");
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+    __asm volatile(
+        "LDR R0, =SystemInit \n"
+        "BLX R0              \n"
+        "cpsie i             \n"
+        "LDR R0, =__main     \n"
+        "BX  R0              \n");
+#elif defined(__MCUXPRESSO)
+    SystemInit();
+
+    //
+    // Copy the data sections from flash to SRAM.
+    //
+    unsigned int LoadAddr, ExeAddr, SectionLen;
+    unsigned int *SectionTableAddr;
+
+    // Load base address of Global Section Table
+    SectionTableAddr = &__data_section_table;
+
+    // Copy the data sections from flash to SRAM.
+    while (SectionTableAddr < &__data_section_table_end)
+    {
+        LoadAddr   = *SectionTableAddr++;
+        ExeAddr    = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        data_init(LoadAddr, ExeAddr, SectionLen);
+    }
+
+    // At this point, SectionTableAddr = &__bss_section_table;
+    // Zero fill the bss segment
+    while (SectionTableAddr < &__bss_section_table_end)
+    {
+        ExeAddr    = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        bss_init(ExeAddr, SectionLen);
+    }
+
+#if defined(__cplusplus)
+    //
+    // Call C++ library initialisation
+    //
+    __libc_init_array();
+#endif //(__cplusplus)
+
+    // Reenable interrupts
+    __asm volatile("cpsie i");
+
+#if defined(__REDLIB__)
+    // Call the Redlib library, which in turn calls main()
+    __main();
+#else
+    main();
+#endif //(__REDLIB__)
+#elif defined(__ICCARM__)
+    SystemInit();
+    // Reenable interrupts
+    __asm volatile("cpsie i");
+
+    __iar_program_start();
+#elif defined(__GNUC__)
+#if !defined(__NO_SYSTEM_INIT)
+    SystemInit();
+#endif //(__NO_SYSTEM_INIT)
+    /*     Loop to copy data from read only memory to RAM. The ranges
+     *      of copy from/to are specified by following symbols evaluated in
+     *      linker script.
+     *      1. __etext/_data_start__/__data_end__
+     *      Note: All must be aligned to 4 bytes boundary.
+     */
+    uint32_t *pDataSrc, *pDataDest;
+
+    pDataSrc  = (uint32_t *)__etext;
+    pDataDest = (uint32_t *)__data_start__;
+    while (pDataDest < __data_end__)
+    {
+        *pDataDest++ = *pDataSrc++;
+    }
+#if defined(__STARTUP_CLEAR_BSS)
+    /*     This part of work usually is done in C library startup code. Otherwise,
+     *     define this macro to enable it in this startup.
+     *
+     *     Loop to zero out BSS section, which uses following symbols
+     *     in linker script:
+     *      __bss_start__: start of BSS section. Must align to 4
+     *      __bss_end__: end of BSS section. Must align to 4
+     */
+    pDataDest = (uint32_t *)__bss_start__;
+    while (pDataDest < __bss_end__)
+    {
+        *pDataDest++ = 0U;
+    }
+#endif //(__STARTUP_CLEAR_BSS)
+
+    __asm volatile("cpsie i");
+
+#if !defined(__START)
+#if defined(__REDLIB__)
+#define __START __main
+#else
+#define __START _start
+#endif //(__REDLIB__)
+#endif //(__START)
+
+    __START();
+
+#endif //(__GNUC__)
+
+    //
+    // main() shouldn't return, but if it does, we'll just enter an infinite loop
+    //
+#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM)
+    while (1)
+    {
+        ;
+    }
+#endif //!(__ARMCC_VERSION) && !(__CC_ARM)
+}
+
+//*****************************************************************************
+// Default core exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+WEAK_AV void NMI_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void HardFault_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void MemManage_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void BusFault_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void UsageFault_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void SecureFault_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void SVC_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void DebugMon_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void PendSV_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void SysTick_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+//*****************************************************************************
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//*****************************************************************************
+WEAK_AV void DefaultISR(void)
+{
+    while (1)
+    {
+    }
+}
+
+//*****************************************************************************
+// Default application exception handlers. Override the ones here by defining
+// your own handler routines in your application code. These routines call
+// driver exception handlers or DefaultISR() if no driver exception
+// handler is included.
+//*****************************************************************************
+WEAK void Reserved16_IRQHandler(void)
+{
+    Reserved16_DriverIRQHandler();
+}
+
+WEAK void CMC_IRQHandler(void)
+{
+    CMC_DriverIRQHandler();
+}
+
+WEAK void DMA_CH0_IRQHandler(void)
+{
+    DMA_CH0_DriverIRQHandler();
+}
+
+WEAK void DMA_CH1_IRQHandler(void)
+{
+    DMA_CH1_DriverIRQHandler();
+}
+
+WEAK void DMA_CH2_IRQHandler(void)
+{
+    DMA_CH2_DriverIRQHandler();
+}
+
+WEAK void DMA_CH3_IRQHandler(void)
+{
+    DMA_CH3_DriverIRQHandler();
+}
+
+WEAK void DMA_CH4_IRQHandler(void)
+{
+    DMA_CH4_DriverIRQHandler();
+}
+
+WEAK void DMA_CH5_IRQHandler(void)
+{
+    DMA_CH5_DriverIRQHandler();
+}
+
+WEAK void DMA_CH6_IRQHandler(void)
+{
+    DMA_CH6_DriverIRQHandler();
+}
+
+WEAK void DMA_CH7_IRQHandler(void)
+{
+    DMA_CH7_DriverIRQHandler();
+}
+
+WEAK void ERM0_SINGLE_BIT_IRQHandler(void)
+{
+    ERM0_SINGLE_BIT_DriverIRQHandler();
+}
+
+WEAK void ERM0_MULTI_BIT_IRQHandler(void)
+{
+    ERM0_MULTI_BIT_DriverIRQHandler();
+}
+
+WEAK void FMU0_IRQHandler(void)
+{
+    FMU0_DriverIRQHandler();
+}
+
+WEAK void GLIKEY0_IRQHandler(void)
+{
+    GLIKEY0_DriverIRQHandler();
+}
+
+WEAK void MBC0_IRQHandler(void)
+{
+    MBC0_DriverIRQHandler();
+}
+
+WEAK void SCG0_IRQHandler(void)
+{
+    SCG0_DriverIRQHandler();
+}
+
+WEAK void SPC0_IRQHandler(void)
+{
+    SPC0_DriverIRQHandler();
+}
+
+WEAK void Reserved33_IRQHandler(void)
+{
+    Reserved33_DriverIRQHandler();
+}
+
+WEAK void WUU0_IRQHandler(void)
+{
+    WUU0_DriverIRQHandler();
+}
+
+WEAK void CAN0_IRQHandler(void)
+{
+    CAN0_DriverIRQHandler();
+}
+
+WEAK void Reserved36_IRQHandler(void)
+{
+    Reserved36_DriverIRQHandler();
+}
+
+WEAK void Reserved37_IRQHandler(void)
+{
+    Reserved37_DriverIRQHandler();
+}
+
+WEAK void Reserved38_IRQHandler(void)
+{
+    Reserved38_DriverIRQHandler();
+}
+
+WEAK void Reserved39_IRQHandler(void)
+{
+    Reserved39_DriverIRQHandler();
+}
+
+WEAK void Reserved40_IRQHandler(void)
+{
+    Reserved40_DriverIRQHandler();
+}
+
+WEAK void Reserved41_IRQHandler(void)
+{
+    Reserved41_DriverIRQHandler();
+}
+
+WEAK void LPI2C0_IRQHandler(void)
+{
+    LPI2C0_DriverIRQHandler();
+}
+
+WEAK void LPI2C1_IRQHandler(void)
+{
+    LPI2C1_DriverIRQHandler();
+}
+
+WEAK void LPSPI0_IRQHandler(void)
+{
+    LPSPI0_DriverIRQHandler();
+}
+
+WEAK void LPSPI1_IRQHandler(void)
+{
+    LPSPI1_DriverIRQHandler();
+}
+
+WEAK void Reserved46_IRQHandler(void)
+{
+    Reserved46_DriverIRQHandler();
+}
+
+WEAK void LPUART0_IRQHandler(void)
+{
+    LPUART0_DriverIRQHandler();
+}
+
+WEAK void LPUART1_IRQHandler(void)
+{
+    LPUART1_DriverIRQHandler();
+}
+
+WEAK void LPUART2_IRQHandler(void)
+{
+    LPUART2_DriverIRQHandler();
+}
+
+WEAK void LPUART3_IRQHandler(void)
+{
+    LPUART3_DriverIRQHandler();
+}
+
+WEAK void Reserved51_IRQHandler(void)
+{
+    Reserved51_DriverIRQHandler();
+}
+
+WEAK void Reserved52_IRQHandler(void)
+{
+    Reserved52_DriverIRQHandler();
+}
+
+WEAK void Reserved53_IRQHandler(void)
+{
+    Reserved53_DriverIRQHandler();
+}
+
+WEAK void CDOG0_IRQHandler(void)
+{
+    CDOG0_DriverIRQHandler();
+}
+
+WEAK void CTIMER0_IRQHandler(void)
+{
+    CTIMER0_DriverIRQHandler();
+}
+
+WEAK void CTIMER1_IRQHandler(void)
+{
+    CTIMER1_DriverIRQHandler();
+}
+
+WEAK void CTIMER2_IRQHandler(void)
+{
+    CTIMER2_DriverIRQHandler();
+}
+
+WEAK void Reserved58_IRQHandler(void)
+{
+    Reserved58_DriverIRQHandler();
+}
+
+WEAK void Reserved59_IRQHandler(void)
+{
+    Reserved59_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void)
+{
+    FLEXPWM0_RELOAD_ERROR_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_FAULT_IRQHandler(void)
+{
+    FLEXPWM0_FAULT_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void)
+{
+    FLEXPWM0_SUBMODULE0_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void)
+{
+    FLEXPWM0_SUBMODULE1_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void)
+{
+    FLEXPWM0_SUBMODULE2_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void)
+{
+    FLEXPWM0_SUBMODULE3_DriverIRQHandler();
+}
+
+WEAK void EQDC0_COMPARE_IRQHandler(void)
+{
+    EQDC0_COMPARE_DriverIRQHandler();
+}
+
+WEAK void EQDC0_HOME_IRQHandler(void)
+{
+    EQDC0_HOME_DriverIRQHandler();
+}
+
+WEAK void EQDC0_WATCHDOG_IRQHandler(void)
+{
+    EQDC0_WATCHDOG_DriverIRQHandler();
+}
+
+WEAK void EQDC0_INDEX_IRQHandler(void)
+{
+    EQDC0_INDEX_DriverIRQHandler();
+}
+
+WEAK void FREQME0_IRQHandler(void)
+{
+    FREQME0_DriverIRQHandler();
+}
+
+WEAK void LPTMR0_IRQHandler(void)
+{
+    LPTMR0_DriverIRQHandler();
+}
+
+WEAK void Reserved72_IRQHandler(void)
+{
+    Reserved72_DriverIRQHandler();
+}
+
+WEAK void OS_EVENT_IRQHandler(void)
+{
+    OS_EVENT_DriverIRQHandler();
+}
+
+WEAK void WAKETIMER0_IRQHandler(void)
+{
+    WAKETIMER0_DriverIRQHandler();
+}
+
+WEAK void UTICK0_IRQHandler(void)
+{
+    UTICK0_DriverIRQHandler();
+}
+
+WEAK void WWDT0_IRQHandler(void)
+{
+    WWDT0_DriverIRQHandler();
+}
+
+WEAK void Reserved77_IRQHandler(void)
+{
+    Reserved77_DriverIRQHandler();
+}
+
+WEAK void ADC0_IRQHandler(void)
+{
+    ADC0_DriverIRQHandler();
+}
+
+WEAK void ADC1_IRQHandler(void)
+{
+    ADC1_DriverIRQHandler();
+}
+
+WEAK void CMP0_IRQHandler(void)
+{
+    CMP0_DriverIRQHandler();
+}
+
+WEAK void CMP1_IRQHandler(void)
+{
+    CMP1_DriverIRQHandler();
+}
+
+WEAK void CMP2_IRQHandler(void)
+{
+    CMP2_DriverIRQHandler();
+}
+
+WEAK void Reserved83_IRQHandler(void)
+{
+    Reserved83_DriverIRQHandler();
+}
+
+WEAK void Reserved84_IRQHandler(void)
+{
+    Reserved84_DriverIRQHandler();
+}
+
+WEAK void Reserved85_IRQHandler(void)
+{
+    Reserved85_DriverIRQHandler();
+}
+
+WEAK void Reserved86_IRQHandler(void)
+{
+    Reserved86_DriverIRQHandler();
+}
+
+WEAK void GPIO0_IRQHandler(void)
+{
+    GPIO0_DriverIRQHandler();
+}
+
+WEAK void GPIO1_IRQHandler(void)
+{
+    GPIO1_DriverIRQHandler();
+}
+
+WEAK void GPIO2_IRQHandler(void)
+{
+    GPIO2_DriverIRQHandler();
+}
+
+WEAK void GPIO3_IRQHandler(void)
+{
+    GPIO3_DriverIRQHandler();
+}
+
+WEAK void GPIO4_IRQHandler(void)
+{
+    GPIO4_DriverIRQHandler();
+}
+
+WEAK void Reserved92_IRQHandler(void)
+{
+    Reserved92_DriverIRQHandler();
+}
+
+WEAK void Reserved93_IRQHandler(void)
+{
+    Reserved93_DriverIRQHandler();
+}
+
+WEAK void Reserved94_IRQHandler(void)
+{
+    Reserved94_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void)
+{
+    FLEXPWM1_RELOAD_ERROR_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_FAULT_IRQHandler(void)
+{
+    FLEXPWM1_FAULT_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void)
+{
+    FLEXPWM1_SUBMODULE0_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void)
+{
+    FLEXPWM1_SUBMODULE1_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void)
+{
+    FLEXPWM1_SUBMODULE2_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void)
+{
+    FLEXPWM1_SUBMODULE3_DriverIRQHandler();
+}
+
+WEAK void EQDC1_COMPARE_IRQHandler(void)
+{
+    EQDC1_COMPARE_DriverIRQHandler();
+}
+
+WEAK void EQDC1_HOME_IRQHandler(void)
+{
+    EQDC1_HOME_DriverIRQHandler();
+}
+
+WEAK void EQDC1_WATCHDOG_IRQHandler(void)
+{
+    EQDC1_WATCHDOG_DriverIRQHandler();
+}
+
+WEAK void EQDC1_INDEX_IRQHandler(void)
+{
+    EQDC1_INDEX_DriverIRQHandler();
+}
+
+WEAK void Reserved105_IRQHandler(void)
+{
+    Reserved105_DriverIRQHandler();
+}
+
+WEAK void Reserved106_IRQHandler(void)
+{
+    Reserved106_DriverIRQHandler();
+}
+
+WEAK void Reserved107_IRQHandler(void)
+{
+    Reserved107_DriverIRQHandler();
+}
+
+WEAK void Reserved108_IRQHandler(void)
+{
+    Reserved108_DriverIRQHandler();
+}
+
+WEAK void Reserved109_IRQHandler(void)
+{
+    Reserved109_DriverIRQHandler();
+}
+
+WEAK void Reserved110_IRQHandler(void)
+{
+    Reserved110_DriverIRQHandler();
+}
+
+WEAK void Reserved111_IRQHandler(void)
+{
+    Reserved111_DriverIRQHandler();
+}
+
+WEAK void Reserved112_IRQHandler(void)
+{
+    Reserved112_DriverIRQHandler();
+}
+
+WEAK void Reserved113_IRQHandler(void)
+{
+    Reserved113_DriverIRQHandler();
+}
+
+WEAK void Reserved114_IRQHandler(void)
+{
+    Reserved114_DriverIRQHandler();
+}
+
+WEAK void Reserved115_IRQHandler(void)
+{
+    Reserved115_DriverIRQHandler();
+}
+
+WEAK void Reserved116_IRQHandler(void)
+{
+    Reserved116_DriverIRQHandler();
+}
+
+WEAK void Reserved117_IRQHandler(void)
+{
+    Reserved117_DriverIRQHandler();
+}
+
+WEAK void Reserved118_IRQHandler(void)
+{
+    Reserved118_DriverIRQHandler();
+}
+
+WEAK void Reserved119_IRQHandler(void)
+{
+    Reserved119_DriverIRQHandler();
+}
+
+WEAK void Reserved120_IRQHandler(void)
+{
+    Reserved120_DriverIRQHandler();
+}
+
+WEAK void Reserved121_IRQHandler(void)
+{
+    Reserved121_DriverIRQHandler();
+}
+
+WEAK void Reserved122_IRQHandler(void)
+{
+    Reserved122_DriverIRQHandler();
+}
+
+WEAK void MAU_IRQHandler(void)
+{
+    MAU_DriverIRQHandler();
+}
+
+WEAK void SMARTDMA_IRQHandler(void)
+{
+    SMARTDMA_DriverIRQHandler();
+}
+
+WEAK void Reserved125_IRQHandler(void)
+{
+    Reserved125_DriverIRQHandler();
+}
+
+WEAK void Reserved126_IRQHandler(void)
+{
+    Reserved126_DriverIRQHandler();
+}
+
+WEAK void Reserved127_IRQHandler(void)
+{
+    Reserved127_DriverIRQHandler();
+}
+
+WEAK void Reserved128_IRQHandler(void)
+{
+    Reserved128_DriverIRQHandler();
+}
+
+WEAK void Reserved129_IRQHandler(void)
+{
+    Reserved129_DriverIRQHandler();
+}
+
+WEAK void Reserved130_IRQHandler(void)
+{
+    Reserved130_DriverIRQHandler();
+}
+
+WEAK void Reserved131_IRQHandler(void)
+{
+    Reserved131_DriverIRQHandler();
+}
+
+WEAK void Reserved132_IRQHandler(void)
+{
+    Reserved132_DriverIRQHandler();
+}
+
+WEAK void Reserved133_IRQHandler(void)
+{
+    Reserved133_DriverIRQHandler();
+}
+
+WEAK void Reserved134_IRQHandler(void)
+{
+    Reserved134_DriverIRQHandler();
+}
+
+WEAK void RTC_IRQHandler(void)
+{
+    RTC_DriverIRQHandler();
+}
+
+WEAK void RTC_1HZ_IRQHandler(void)
+{
+    RTC_1HZ_DriverIRQHandler();
+}
+
+//*****************************************************************************
+
+#if defined(DEBUG)
+#if defined(__GNUC__)
+#pragma GCC pop_options
+#endif //(__GNUC__)
+#endif //(DEBUG)
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/startup_MCXA343.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/startup_MCXA343.cpp
new file mode 100644
index 0000000000..ea271db1a3
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/startup_MCXA343.cpp
@@ -0,0 +1,1464 @@
+//*****************************************************************************
+// MCXA343 startup code
+//
+// Version : 060825
+//*****************************************************************************
+//
+// Copyright 2016-2025 NXP
+//
+// SPDX-License-Identifier: BSD-3-Clause
+//*****************************************************************************
+#include <stdint.h>
+
+#if defined(DEBUG)
+#if defined(__GNUC__)
+#pragma GCC push_options
+#pragma GCC optimize("Og")
+#endif //(__GNUC__)
+#endif //(DEBUG)
+
+#if defined(__cplusplus)
+#if defined(__MCUXPRESSO)
+#if defined(__REDLIB__)
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+extern void __libc_init_array(void);
+}
+#endif //(__REDLIB__)
+#endif //(__MCUXPRESSO)
+#endif //(__cplusplus)
+
+#define WEAK __attribute__((weak))
+#if defined(__MCUXPRESSO)
+#define WEAK_AV __attribute__((weak, section(".after_vectors")))
+#else
+#define WEAK_AV __attribute__((weak))
+#endif //(__MCUXPRESSO)
+#define ALIAS(f) __attribute__((weak, alias(#f)))
+
+//*****************************************************************************
+#if defined(__cplusplus)
+extern "C" {
+#endif //(__cplusplus)
+
+//*****************************************************************************
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+//*****************************************************************************
+//*****************************************************************************
+// Declaration of external SystemInit function
+//*****************************************************************************
+extern void SystemInit(void);
+
+//*****************************************************************************
+// Forward declaration of the core exception handlers.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions.
+// If your application is a C++ one, then any interrupt handlers defined
+// in C++ files within in your main application will need to have C linkage
+// rather than C++ linkage. To do this, make sure that you are using extern "C"
+// { .... } around the interrupt handler within your main application code.
+//*****************************************************************************
+#if defined(__MCUXPRESSO)
+void ResetISR(void);
+#else
+void Reset_Handler(void);
+#endif //(__MCUXPRESSO)
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SecureFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void DefaultISR(void);
+
+//*****************************************************************************
+// Forward declaration of the application IRQ handlers. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over weak definitions below
+//*****************************************************************************
+WEAK void Reserved16_IRQHandler(void);
+WEAK void CMC_IRQHandler(void);
+WEAK void DMA_CH0_IRQHandler(void);
+WEAK void DMA_CH1_IRQHandler(void);
+WEAK void DMA_CH2_IRQHandler(void);
+WEAK void DMA_CH3_IRQHandler(void);
+WEAK void DMA_CH4_IRQHandler(void);
+WEAK void DMA_CH5_IRQHandler(void);
+WEAK void DMA_CH6_IRQHandler(void);
+WEAK void DMA_CH7_IRQHandler(void);
+WEAK void ERM0_SINGLE_BIT_IRQHandler(void);
+WEAK void ERM0_MULTI_BIT_IRQHandler(void);
+WEAK void FMU0_IRQHandler(void);
+WEAK void GLIKEY0_IRQHandler(void);
+WEAK void MBC0_IRQHandler(void);
+WEAK void SCG0_IRQHandler(void);
+WEAK void SPC0_IRQHandler(void);
+WEAK void Reserved33_IRQHandler(void);
+WEAK void WUU0_IRQHandler(void);
+WEAK void CAN0_IRQHandler(void);
+WEAK void Reserved36_IRQHandler(void);
+WEAK void Reserved37_IRQHandler(void);
+WEAK void Reserved38_IRQHandler(void);
+WEAK void Reserved39_IRQHandler(void);
+WEAK void Reserved40_IRQHandler(void);
+WEAK void Reserved41_IRQHandler(void);
+WEAK void LPI2C0_IRQHandler(void);
+WEAK void LPI2C1_IRQHandler(void);
+WEAK void LPSPI0_IRQHandler(void);
+WEAK void LPSPI1_IRQHandler(void);
+WEAK void Reserved46_IRQHandler(void);
+WEAK void LPUART0_IRQHandler(void);
+WEAK void LPUART1_IRQHandler(void);
+WEAK void LPUART2_IRQHandler(void);
+WEAK void LPUART3_IRQHandler(void);
+WEAK void Reserved51_IRQHandler(void);
+WEAK void Reserved52_IRQHandler(void);
+WEAK void Reserved53_IRQHandler(void);
+WEAK void CDOG0_IRQHandler(void);
+WEAK void CTIMER0_IRQHandler(void);
+WEAK void CTIMER1_IRQHandler(void);
+WEAK void CTIMER2_IRQHandler(void);
+WEAK void Reserved58_IRQHandler(void);
+WEAK void Reserved59_IRQHandler(void);
+WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void);
+WEAK void FLEXPWM0_FAULT_IRQHandler(void);
+WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void);
+WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void);
+WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void);
+WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void);
+WEAK void EQDC0_COMPARE_IRQHandler(void);
+WEAK void EQDC0_HOME_IRQHandler(void);
+WEAK void EQDC0_WATCHDOG_IRQHandler(void);
+WEAK void EQDC0_INDEX_IRQHandler(void);
+WEAK void FREQME0_IRQHandler(void);
+WEAK void LPTMR0_IRQHandler(void);
+WEAK void Reserved72_IRQHandler(void);
+WEAK void OS_EVENT_IRQHandler(void);
+WEAK void WAKETIMER0_IRQHandler(void);
+WEAK void UTICK0_IRQHandler(void);
+WEAK void WWDT0_IRQHandler(void);
+WEAK void Reserved77_IRQHandler(void);
+WEAK void ADC0_IRQHandler(void);
+WEAK void ADC1_IRQHandler(void);
+WEAK void CMP0_IRQHandler(void);
+WEAK void CMP1_IRQHandler(void);
+WEAK void CMP2_IRQHandler(void);
+WEAK void Reserved83_IRQHandler(void);
+WEAK void Reserved84_IRQHandler(void);
+WEAK void Reserved85_IRQHandler(void);
+WEAK void Reserved86_IRQHandler(void);
+WEAK void GPIO0_IRQHandler(void);
+WEAK void GPIO1_IRQHandler(void);
+WEAK void GPIO2_IRQHandler(void);
+WEAK void GPIO3_IRQHandler(void);
+WEAK void GPIO4_IRQHandler(void);
+WEAK void Reserved92_IRQHandler(void);
+WEAK void Reserved93_IRQHandler(void);
+WEAK void Reserved94_IRQHandler(void);
+WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void);
+WEAK void FLEXPWM1_FAULT_IRQHandler(void);
+WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void);
+WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void);
+WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void);
+WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void);
+WEAK void EQDC1_COMPARE_IRQHandler(void);
+WEAK void EQDC1_HOME_IRQHandler(void);
+WEAK void EQDC1_WATCHDOG_IRQHandler(void);
+WEAK void EQDC1_INDEX_IRQHandler(void);
+WEAK void Reserved105_IRQHandler(void);
+WEAK void Reserved106_IRQHandler(void);
+WEAK void Reserved107_IRQHandler(void);
+WEAK void Reserved108_IRQHandler(void);
+WEAK void Reserved109_IRQHandler(void);
+WEAK void Reserved110_IRQHandler(void);
+WEAK void Reserved111_IRQHandler(void);
+WEAK void Reserved112_IRQHandler(void);
+WEAK void Reserved113_IRQHandler(void);
+WEAK void Reserved114_IRQHandler(void);
+WEAK void Reserved115_IRQHandler(void);
+WEAK void Reserved116_IRQHandler(void);
+WEAK void Reserved117_IRQHandler(void);
+WEAK void Reserved118_IRQHandler(void);
+WEAK void Reserved119_IRQHandler(void);
+WEAK void Reserved120_IRQHandler(void);
+WEAK void Reserved121_IRQHandler(void);
+WEAK void Reserved122_IRQHandler(void);
+WEAK void MAU_IRQHandler(void);
+WEAK void SMARTDMA_IRQHandler(void);
+WEAK void Reserved125_IRQHandler(void);
+WEAK void Reserved126_IRQHandler(void);
+WEAK void Reserved127_IRQHandler(void);
+WEAK void Reserved128_IRQHandler(void);
+WEAK void Reserved129_IRQHandler(void);
+WEAK void Reserved130_IRQHandler(void);
+WEAK void Reserved131_IRQHandler(void);
+WEAK void Reserved132_IRQHandler(void);
+WEAK void Reserved133_IRQHandler(void);
+WEAK void Reserved134_IRQHandler(void);
+WEAK void RTC_IRQHandler(void);
+WEAK void RTC_1HZ_IRQHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the driver IRQ handlers. These are aliased
+// to the DefaultISR, which is a 'forever' loop. When the driver
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//*****************************************************************************
+void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CMC_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR);
+void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved33_DriverIRQHandler(void) ALIAS(DefaultISR);
+void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved39_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved40_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved51_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved52_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved58_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR);
+void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR);
+void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CMP2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved83_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved93_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved94_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved111_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR);
+void MAU_DriverIRQHandler(void) ALIAS(DefaultISR);
+void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved125_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR);
+void RTC_DriverIRQHandler(void) ALIAS(DefaultISR);
+void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR);
+
+//*****************************************************************************
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//*****************************************************************************
+#if defined(__MCUXPRESSO)
+#if defined(__REDLIB__)
+extern void __main(void);
+#else
+extern int main(void);
+#endif //(__REDLIB__)
+#elif defined(__ICCARM__)
+extern void __iar_program_start(void);
+#elif defined(__GNUC__)
+#if defined(__REDLIB__)
+extern void __main(void);
+#else
+extern void _start(void);
+#endif //(__REDLIB__)
+#else
+#error Unsupported toolchain!
+#endif //(__MCUXPRESSO)
+
+//*****************************************************************************
+// External declaration for the pointer from the Linker Script
+//*****************************************************************************
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[];
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+#define _vStackTop  Image$$ARM_LIB_STACK$$ZI$$Limit
+#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base
+#elif defined(__MCUXPRESSO)
+extern void _vStackTop(void);
+extern void _vStackBase(void);
+#define Reset_Handler ResetISR // To be compatible with other compilers
+#elif defined(__ICCARM__)
+#pragma segment = "CSTACK"
+#define _vStackTop  __section_end("CSTACK")
+#define _vStackBase __section_begin("CSTACK")
+#elif defined(__GNUC__)
+extern uint32_t __StackTop[];
+extern uint32_t __StackLimit[];
+
+#define _vStackTop  __StackTop
+#define _vStackBase __StackLimit
+
+extern uint32_t __etext[];
+extern uint32_t __data_start__[];
+extern uint32_t __data_end__[];
+
+extern uint32_t __bss_start__[];
+extern uint32_t __bss_end__[];
+#else
+#error Unsupported toolchain!
+#endif //(__CC_ARM) || (__ARMCC_VERSION)
+
+//*****************************************************************************
+#if defined(__cplusplus)
+} // extern "C"
+#endif //(__cplusplus)
+//*****************************************************************************
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//*****************************************************************************
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+extern void (*const __Vectors[])(void);
+#define __vector_table __Vectors
+__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = {
+#elif defined(__MCUXPRESSO)
+extern void (*const g_pfnVectors[])(void);
+extern void *__Vectors __attribute__((alias("g_pfnVectors")));
+#define __vector_table g_pfnVectors
+__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = {
+#elif defined(__ICCARM__)
+extern void (*const __vector_table[])(void);
+/* The vector table is not needed for initialization. */
+extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table")));
+__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = {
+#elif defined(__GNUC__)
+extern void (*const __isr_vector[])(void);
+#define __vector_table __isr_vector
+__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = {
+#else
+#error Unsupported toolchain!
+#endif //(__CC_ARM) || (__ARMCC_VERSION)
+    // Core Level - CM33
+    (void (*)())((uint32_t)_vStackTop), // The initial stack pointer
+    Reset_Handler,                      // The reset handler
+
+    NMI_Handler,                        // NMI Handler
+    HardFault_Handler,                  // Hard Fault Handler
+    MemManage_Handler,                  // MPU Fault Handler
+    BusFault_Handler,                   // Bus Fault Handler
+    UsageFault_Handler,                 // Usage Fault Handler
+    SecureFault_Handler,                // Secure Fault Handler
+    0,                                  // Reserved
+    0,                                  // Reserved
+    0,                                  // Reserved
+    SVC_Handler,                        // SVCall Handler
+    DebugMon_Handler,                   // Debug Monitor Handler
+    0,                                  // Reserved
+    PendSV_Handler,                     // PendSV Handler
+    SysTick_Handler,                    // SysTick Handler
+
+    // Chip Level - MCXA343
+    Reserved16_IRQHandler,            // 16 : Reserved interrupt
+    CMC_IRQHandler,                   // 17 : Core Mode Controller interrupt
+    DMA_CH0_IRQHandler,               // 18 : DMA3_0_CH0 error or transfer complete
+    DMA_CH1_IRQHandler,               // 19 : DMA3_0_CH1 error or transfer complete
+    DMA_CH2_IRQHandler,               // 20 : DMA3_0_CH2 error or transfer complete
+    DMA_CH3_IRQHandler,               // 21 : DMA3_0_CH3 error or transfer complete
+    DMA_CH4_IRQHandler,               // 22 : DMA3_0_CH4 error or transfer complete
+    DMA_CH5_IRQHandler,               // 23 : DMA3_0_CH5 error or transfer complete
+    DMA_CH6_IRQHandler,               // 24 : DMA3_0_CH6 error or transfer complete
+    DMA_CH7_IRQHandler,               // 25 : DMA3_0_CH7 error or transfer complete
+    ERM0_SINGLE_BIT_IRQHandler,       // 26 : ERM Single Bit error interrupt
+    ERM0_MULTI_BIT_IRQHandler,        // 27 : ERM Multi Bit error interrupt
+    FMU0_IRQHandler,                  // 28 : Flash Management Unit interrupt
+    GLIKEY0_IRQHandler,               // 29 : GLIKEY Interrupt
+    MBC0_IRQHandler,                  // 30 : MBC secure violation interrupt
+    SCG0_IRQHandler,                  // 31 : System Clock Generator interrupt
+    SPC0_IRQHandler,                  // 32 : System Power Controller interrupt
+    Reserved33_IRQHandler,            // 33 : Reserved interrupt
+    WUU0_IRQHandler,                  // 34 : Wake Up Unit interrupt
+    CAN0_IRQHandler,                  // 35 : Controller Area Network 0 interrupt
+    Reserved36_IRQHandler,            // 36 : Reserved interrupt
+    Reserved37_IRQHandler,            // 37 : Reserved interrupt
+    Reserved38_IRQHandler,            // 38 : Reserved interrupt
+    Reserved39_IRQHandler,            // 39 : Reserved interrupt
+    Reserved40_IRQHandler,            // 40 : Reserved interrupt
+    Reserved41_IRQHandler,            // 41 : Reserved interrupt
+    LPI2C0_IRQHandler,                // 42 : Low-Power Inter Integrated Circuit 0 interrupt
+    LPI2C1_IRQHandler,                // 43 : Low-Power Inter Integrated Circuit 1 interrupt
+    LPSPI0_IRQHandler,                // 44 : Low-Power Serial Peripheral Interface 0 interrupt
+    LPSPI1_IRQHandler,                // 45 : Low-Power Serial Peripheral Interface 1 interrupt
+    Reserved46_IRQHandler,            // 46 : Reserved interrupt
+    LPUART0_IRQHandler,               // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt
+    LPUART1_IRQHandler,               // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt
+    LPUART2_IRQHandler,               // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt
+    LPUART3_IRQHandler,               // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt
+    Reserved51_IRQHandler,            // 51 : Reserved interrupt
+    Reserved52_IRQHandler,            // 52 : Reserved interrupt
+    Reserved53_IRQHandler,            // 53 : Reserved interrupt
+    CDOG0_IRQHandler,                 // 54 : Code Watchdog Timer 0 interrupt
+    CTIMER0_IRQHandler,               // 55 : Standard counter/timer 0 interrupt
+    CTIMER1_IRQHandler,               // 56 : Standard counter/timer 1 interrupt
+    CTIMER2_IRQHandler,               // 57 : Standard counter/timer 2 interrupt
+    Reserved58_IRQHandler,            // 58 : Reserved interrupt
+    Reserved59_IRQHandler,            // 59 : Reserved interrupt
+    FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt
+    FLEXPWM0_FAULT_IRQHandler,        // 61 : FlexPWM0_fault interrupt
+    FLEXPWM0_SUBMODULE0_IRQHandler,   // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt
+    FLEXPWM0_SUBMODULE1_IRQHandler,   // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt
+    FLEXPWM0_SUBMODULE2_IRQHandler,   // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt
+    FLEXPWM0_SUBMODULE3_IRQHandler,   // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt
+    EQDC0_COMPARE_IRQHandler,         // 66 : Compare
+    EQDC0_HOME_IRQHandler,            // 67 : Home
+    EQDC0_WATCHDOG_IRQHandler,        // 68 : Watchdog / Simultaneous A and B Change
+    EQDC0_INDEX_IRQHandler,           // 69 : Index / Roll Over / Roll Under
+    FREQME0_IRQHandler,               // 70 : Frequency Measurement interrupt
+    LPTMR0_IRQHandler,                // 71 : Low Power Timer 0 interrupt
+    Reserved72_IRQHandler,            // 72 : Reserved interrupt
+    OS_EVENT_IRQHandler,              // 73 : OS event timer interrupt
+    WAKETIMER0_IRQHandler,            // 74 : Wake Timer Interrupt
+    UTICK0_IRQHandler,                // 75 : Micro-Tick Timer interrupt
+    WWDT0_IRQHandler,                 // 76 : Windowed Watchdog Timer 0 interrupt
+    Reserved77_IRQHandler,            // 77 : Reserved interrupt
+    ADC0_IRQHandler,                  // 78 : Analog-to-Digital Converter 0 interrupt
+    ADC1_IRQHandler,                  // 79 : Analog-to-Digital Converter 1 interrupt
+    CMP0_IRQHandler,                  // 80 : Comparator 0 interrupt
+    CMP1_IRQHandler,                  // 81 : Comparator 1 interrupt
+    CMP2_IRQHandler,                  // 82 : Comparator 2 interrupt
+    Reserved83_IRQHandler,            // 83 : Reserved interrupt
+    Reserved84_IRQHandler,            // 84 : Reserved interrupt
+    Reserved85_IRQHandler,            // 85 : Reserved interrupt
+    Reserved86_IRQHandler,            // 86 : Reserved interrupt
+    GPIO0_IRQHandler,                 // 87 : General Purpose Input/Output interrupt 0
+    GPIO1_IRQHandler,                 // 88 : General Purpose Input/Output interrupt 1
+    GPIO2_IRQHandler,                 // 89 : General Purpose Input/Output interrupt 2
+    GPIO3_IRQHandler,                 // 90 : General Purpose Input/Output interrupt 3
+    GPIO4_IRQHandler,                 // 91 : General Purpose Input/Output interrupt 4
+    Reserved92_IRQHandler,            // 92 : Reserved interrupt
+    Reserved93_IRQHandler,            // 93 : Reserved interrupt
+    Reserved94_IRQHandler,            // 94 : Reserved interrupt
+    FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt
+    FLEXPWM1_FAULT_IRQHandler,        // 96 : FlexPWM1_fault interrupt
+    FLEXPWM1_SUBMODULE0_IRQHandler,   // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt
+    FLEXPWM1_SUBMODULE1_IRQHandler,   // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt
+    FLEXPWM1_SUBMODULE2_IRQHandler,   // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt
+    FLEXPWM1_SUBMODULE3_IRQHandler,   // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt
+    EQDC1_COMPARE_IRQHandler,         // 101: Compare
+    EQDC1_HOME_IRQHandler,            // 102: Home
+    EQDC1_WATCHDOG_IRQHandler,        // 103: Watchdog / Simultaneous A and B Change
+    EQDC1_INDEX_IRQHandler,           // 104: Index / Roll Over / Roll Under
+    Reserved105_IRQHandler,           // 105: Reserved interrupt
+    Reserved106_IRQHandler,           // 106: Reserved interrupt
+    Reserved107_IRQHandler,           // 107: Reserved interrupt
+    Reserved108_IRQHandler,           // 108: Reserved interrupt
+    Reserved109_IRQHandler,           // 109: Reserved interrupt
+    Reserved110_IRQHandler,           // 110: Reserved interrupt
+    Reserved111_IRQHandler,           // 111: Reserved interrupt
+    Reserved112_IRQHandler,           // 112: Reserved interrupt
+    Reserved113_IRQHandler,           // 113: Reserved interrupt
+    Reserved114_IRQHandler,           // 114: Reserved interrupt
+    Reserved115_IRQHandler,           // 115: Reserved interrupt
+    Reserved116_IRQHandler,           // 116: Reserved interrupt
+    Reserved117_IRQHandler,           // 117: Reserved interrupt
+    Reserved118_IRQHandler,           // 118: Reserved interrupt
+    Reserved119_IRQHandler,           // 119: Reserved interrupt
+    Reserved120_IRQHandler,           // 120: Reserved interrupt
+    Reserved121_IRQHandler,           // 121: Reserved interrupt
+    Reserved122_IRQHandler,           // 122: Reserved interrupt
+    MAU_IRQHandler,                   // 123: MAU interrupt
+    SMARTDMA_IRQHandler,              // 124: SmartDMA interrupt
+    Reserved125_IRQHandler,           // 125: Reserved interrupt
+    Reserved126_IRQHandler,           // 126: Reserved interrupt
+    Reserved127_IRQHandler,           // 127: Reserved interrupt
+    Reserved128_IRQHandler,           // 128: Reserved interrupt
+    Reserved129_IRQHandler,           // 129: Reserved interrupt
+    Reserved130_IRQHandler,           // 130: Reserved interrupt
+    Reserved131_IRQHandler,           // 131: Reserved interrupt
+    Reserved132_IRQHandler,           // 132: Reserved interrupt
+    Reserved133_IRQHandler,           // 133: Reserved interrupt
+    Reserved134_IRQHandler,           // 134: Reserved interrupt
+    RTC_IRQHandler,                   // 135: RTC alarm interrupt
+    RTC_1HZ_IRQHandler,               // 136: RTC 1Hz interrupt
+};                                     /* End of __vector_table */
+
+#if defined(__MCUXPRESSO)
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors")));
+void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128)));
+unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors);
+#endif //(ENABLE_RAM_VECTOR_TABLE)
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart,
+                                                                    unsigned int start,
+                                                                    unsigned int len)
+{
+    unsigned int *pulDest = (unsigned int *)start;
+    unsigned int *pulSrc  = (unsigned int *)romstart;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = *pulSrc++;
+}
+
+__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len)
+{
+    unsigned int *pulDest = (unsigned int *)start;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+#endif //(__MCUXPRESSO)
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+__attribute__ ((used, section("InRoot$$Sections")))
+__attribute__ ((naked))
+#elif defined(__MCUXPRESSO)
+__attribute__ ((naked, section(".after_vectors.reset")))
+#elif defined(__ICCARM__)
+__stackless
+#elif defined(__GNUC__)
+__attribute__ ((naked))
+#endif //(__CC_ARM) || (__ARMCC_VERSION)
+void Reset_Handler(void)
+{
+    // Disable interrupts
+    __asm volatile("cpsid i");
+    // Config VTOR & MSP register
+    __asm volatile(
+        "LDR R0, =0xE000ED08  \n"
+        "STR %0, [R0]         \n"
+        "LDR R1, [%0]         \n"
+        "MSR MSP, R1          \n"
+        "MSR MSPLIM, %1       \n"
+        :
+        : "r"(__vector_table), "r"(_vStackBase)
+        : "r0", "r1");
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+    __asm volatile(
+        "LDR R0, =SystemInit \n"
+        "BLX R0              \n"
+        "cpsie i             \n"
+        "LDR R0, =__main     \n"
+        "BX  R0              \n");
+#elif defined(__MCUXPRESSO)
+    SystemInit();
+
+    //
+    // Copy the data sections from flash to SRAM.
+    //
+    unsigned int LoadAddr, ExeAddr, SectionLen;
+    unsigned int *SectionTableAddr;
+
+    // Load base address of Global Section Table
+    SectionTableAddr = &__data_section_table;
+
+    // Copy the data sections from flash to SRAM.
+    while (SectionTableAddr < &__data_section_table_end)
+    {
+        LoadAddr   = *SectionTableAddr++;
+        ExeAddr    = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        data_init(LoadAddr, ExeAddr, SectionLen);
+    }
+
+    // At this point, SectionTableAddr = &__bss_section_table;
+    // Zero fill the bss segment
+    while (SectionTableAddr < &__bss_section_table_end)
+    {
+        ExeAddr    = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        bss_init(ExeAddr, SectionLen);
+    }
+
+#if defined(__cplusplus)
+    //
+    // Call C++ library initialisation
+    //
+    __libc_init_array();
+#endif //(__cplusplus)
+
+    // Reenable interrupts
+    __asm volatile("cpsie i");
+
+#if defined(__REDLIB__)
+    // Call the Redlib library, which in turn calls main()
+    __main();
+#else
+    main();
+#endif //(__REDLIB__)
+#elif defined(__ICCARM__)
+    SystemInit();
+    // Reenable interrupts
+    __asm volatile("cpsie i");
+
+    __iar_program_start();
+#elif defined(__GNUC__)
+#if !defined(__NO_SYSTEM_INIT)
+    SystemInit();
+#endif //(__NO_SYSTEM_INIT)
+    /*     Loop to copy data from read only memory to RAM. The ranges
+     *      of copy from/to are specified by following symbols evaluated in
+     *      linker script.
+     *      1. __etext/_data_start__/__data_end__
+     *      Note: All must be aligned to 4 bytes boundary.
+     */
+    uint32_t *pDataSrc, *pDataDest;
+
+    pDataSrc  = (uint32_t *)__etext;
+    pDataDest = (uint32_t *)__data_start__;
+    while (pDataDest < __data_end__)
+    {
+        *pDataDest++ = *pDataSrc++;
+    }
+#if defined(__STARTUP_CLEAR_BSS)
+    /*     This part of work usually is done in C library startup code. Otherwise,
+     *     define this macro to enable it in this startup.
+     *
+     *     Loop to zero out BSS section, which uses following symbols
+     *     in linker script:
+     *      __bss_start__: start of BSS section. Must align to 4
+     *      __bss_end__: end of BSS section. Must align to 4
+     */
+    pDataDest = (uint32_t *)__bss_start__;
+    while (pDataDest < __bss_end__)
+    {
+        *pDataDest++ = 0U;
+    }
+#endif //(__STARTUP_CLEAR_BSS)
+
+    __asm volatile("cpsie i");
+
+#if !defined(__START)
+#if defined(__REDLIB__)
+#define __START __main
+#else
+#define __START _start
+#endif //(__REDLIB__)
+#endif //(__START)
+
+    __START();
+
+#endif //(__GNUC__)
+
+    //
+    // main() shouldn't return, but if it does, we'll just enter an infinite loop
+    //
+#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM)
+    while (1)
+    {
+        ;
+    }
+#endif //!(__ARMCC_VERSION) && !(__CC_ARM)
+}
+
+//*****************************************************************************
+// Default core exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+WEAK_AV void NMI_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void HardFault_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void MemManage_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void BusFault_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void UsageFault_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void SecureFault_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void SVC_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void DebugMon_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void PendSV_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void SysTick_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+//*****************************************************************************
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//*****************************************************************************
+WEAK_AV void DefaultISR(void)
+{
+    while (1)
+    {
+    }
+}
+
+//*****************************************************************************
+// Default application exception handlers. Override the ones here by defining
+// your own handler routines in your application code. These routines call
+// driver exception handlers or DefaultISR() if no driver exception
+// handler is included.
+//*****************************************************************************
+WEAK void Reserved16_IRQHandler(void)
+{
+    Reserved16_DriverIRQHandler();
+}
+
+WEAK void CMC_IRQHandler(void)
+{
+    CMC_DriverIRQHandler();
+}
+
+WEAK void DMA_CH0_IRQHandler(void)
+{
+    DMA_CH0_DriverIRQHandler();
+}
+
+WEAK void DMA_CH1_IRQHandler(void)
+{
+    DMA_CH1_DriverIRQHandler();
+}
+
+WEAK void DMA_CH2_IRQHandler(void)
+{
+    DMA_CH2_DriverIRQHandler();
+}
+
+WEAK void DMA_CH3_IRQHandler(void)
+{
+    DMA_CH3_DriverIRQHandler();
+}
+
+WEAK void DMA_CH4_IRQHandler(void)
+{
+    DMA_CH4_DriverIRQHandler();
+}
+
+WEAK void DMA_CH5_IRQHandler(void)
+{
+    DMA_CH5_DriverIRQHandler();
+}
+
+WEAK void DMA_CH6_IRQHandler(void)
+{
+    DMA_CH6_DriverIRQHandler();
+}
+
+WEAK void DMA_CH7_IRQHandler(void)
+{
+    DMA_CH7_DriverIRQHandler();
+}
+
+WEAK void ERM0_SINGLE_BIT_IRQHandler(void)
+{
+    ERM0_SINGLE_BIT_DriverIRQHandler();
+}
+
+WEAK void ERM0_MULTI_BIT_IRQHandler(void)
+{
+    ERM0_MULTI_BIT_DriverIRQHandler();
+}
+
+WEAK void FMU0_IRQHandler(void)
+{
+    FMU0_DriverIRQHandler();
+}
+
+WEAK void GLIKEY0_IRQHandler(void)
+{
+    GLIKEY0_DriverIRQHandler();
+}
+
+WEAK void MBC0_IRQHandler(void)
+{
+    MBC0_DriverIRQHandler();
+}
+
+WEAK void SCG0_IRQHandler(void)
+{
+    SCG0_DriverIRQHandler();
+}
+
+WEAK void SPC0_IRQHandler(void)
+{
+    SPC0_DriverIRQHandler();
+}
+
+WEAK void Reserved33_IRQHandler(void)
+{
+    Reserved33_DriverIRQHandler();
+}
+
+WEAK void WUU0_IRQHandler(void)
+{
+    WUU0_DriverIRQHandler();
+}
+
+WEAK void CAN0_IRQHandler(void)
+{
+    CAN0_DriverIRQHandler();
+}
+
+WEAK void Reserved36_IRQHandler(void)
+{
+    Reserved36_DriverIRQHandler();
+}
+
+WEAK void Reserved37_IRQHandler(void)
+{
+    Reserved37_DriverIRQHandler();
+}
+
+WEAK void Reserved38_IRQHandler(void)
+{
+    Reserved38_DriverIRQHandler();
+}
+
+WEAK void Reserved39_IRQHandler(void)
+{
+    Reserved39_DriverIRQHandler();
+}
+
+WEAK void Reserved40_IRQHandler(void)
+{
+    Reserved40_DriverIRQHandler();
+}
+
+WEAK void Reserved41_IRQHandler(void)
+{
+    Reserved41_DriverIRQHandler();
+}
+
+WEAK void LPI2C0_IRQHandler(void)
+{
+    LPI2C0_DriverIRQHandler();
+}
+
+WEAK void LPI2C1_IRQHandler(void)
+{
+    LPI2C1_DriverIRQHandler();
+}
+
+WEAK void LPSPI0_IRQHandler(void)
+{
+    LPSPI0_DriverIRQHandler();
+}
+
+WEAK void LPSPI1_IRQHandler(void)
+{
+    LPSPI1_DriverIRQHandler();
+}
+
+WEAK void Reserved46_IRQHandler(void)
+{
+    Reserved46_DriverIRQHandler();
+}
+
+WEAK void LPUART0_IRQHandler(void)
+{
+    LPUART0_DriverIRQHandler();
+}
+
+WEAK void LPUART1_IRQHandler(void)
+{
+    LPUART1_DriverIRQHandler();
+}
+
+WEAK void LPUART2_IRQHandler(void)
+{
+    LPUART2_DriverIRQHandler();
+}
+
+WEAK void LPUART3_IRQHandler(void)
+{
+    LPUART3_DriverIRQHandler();
+}
+
+WEAK void Reserved51_IRQHandler(void)
+{
+    Reserved51_DriverIRQHandler();
+}
+
+WEAK void Reserved52_IRQHandler(void)
+{
+    Reserved52_DriverIRQHandler();
+}
+
+WEAK void Reserved53_IRQHandler(void)
+{
+    Reserved53_DriverIRQHandler();
+}
+
+WEAK void CDOG0_IRQHandler(void)
+{
+    CDOG0_DriverIRQHandler();
+}
+
+WEAK void CTIMER0_IRQHandler(void)
+{
+    CTIMER0_DriverIRQHandler();
+}
+
+WEAK void CTIMER1_IRQHandler(void)
+{
+    CTIMER1_DriverIRQHandler();
+}
+
+WEAK void CTIMER2_IRQHandler(void)
+{
+    CTIMER2_DriverIRQHandler();
+}
+
+WEAK void Reserved58_IRQHandler(void)
+{
+    Reserved58_DriverIRQHandler();
+}
+
+WEAK void Reserved59_IRQHandler(void)
+{
+    Reserved59_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void)
+{
+    FLEXPWM0_RELOAD_ERROR_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_FAULT_IRQHandler(void)
+{
+    FLEXPWM0_FAULT_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void)
+{
+    FLEXPWM0_SUBMODULE0_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void)
+{
+    FLEXPWM0_SUBMODULE1_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void)
+{
+    FLEXPWM0_SUBMODULE2_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void)
+{
+    FLEXPWM0_SUBMODULE3_DriverIRQHandler();
+}
+
+WEAK void EQDC0_COMPARE_IRQHandler(void)
+{
+    EQDC0_COMPARE_DriverIRQHandler();
+}
+
+WEAK void EQDC0_HOME_IRQHandler(void)
+{
+    EQDC0_HOME_DriverIRQHandler();
+}
+
+WEAK void EQDC0_WATCHDOG_IRQHandler(void)
+{
+    EQDC0_WATCHDOG_DriverIRQHandler();
+}
+
+WEAK void EQDC0_INDEX_IRQHandler(void)
+{
+    EQDC0_INDEX_DriverIRQHandler();
+}
+
+WEAK void FREQME0_IRQHandler(void)
+{
+    FREQME0_DriverIRQHandler();
+}
+
+WEAK void LPTMR0_IRQHandler(void)
+{
+    LPTMR0_DriverIRQHandler();
+}
+
+WEAK void Reserved72_IRQHandler(void)
+{
+    Reserved72_DriverIRQHandler();
+}
+
+WEAK void OS_EVENT_IRQHandler(void)
+{
+    OS_EVENT_DriverIRQHandler();
+}
+
+WEAK void WAKETIMER0_IRQHandler(void)
+{
+    WAKETIMER0_DriverIRQHandler();
+}
+
+WEAK void UTICK0_IRQHandler(void)
+{
+    UTICK0_DriverIRQHandler();
+}
+
+WEAK void WWDT0_IRQHandler(void)
+{
+    WWDT0_DriverIRQHandler();
+}
+
+WEAK void Reserved77_IRQHandler(void)
+{
+    Reserved77_DriverIRQHandler();
+}
+
+WEAK void ADC0_IRQHandler(void)
+{
+    ADC0_DriverIRQHandler();
+}
+
+WEAK void ADC1_IRQHandler(void)
+{
+    ADC1_DriverIRQHandler();
+}
+
+WEAK void CMP0_IRQHandler(void)
+{
+    CMP0_DriverIRQHandler();
+}
+
+WEAK void CMP1_IRQHandler(void)
+{
+    CMP1_DriverIRQHandler();
+}
+
+WEAK void CMP2_IRQHandler(void)
+{
+    CMP2_DriverIRQHandler();
+}
+
+WEAK void Reserved83_IRQHandler(void)
+{
+    Reserved83_DriverIRQHandler();
+}
+
+WEAK void Reserved84_IRQHandler(void)
+{
+    Reserved84_DriverIRQHandler();
+}
+
+WEAK void Reserved85_IRQHandler(void)
+{
+    Reserved85_DriverIRQHandler();
+}
+
+WEAK void Reserved86_IRQHandler(void)
+{
+    Reserved86_DriverIRQHandler();
+}
+
+WEAK void GPIO0_IRQHandler(void)
+{
+    GPIO0_DriverIRQHandler();
+}
+
+WEAK void GPIO1_IRQHandler(void)
+{
+    GPIO1_DriverIRQHandler();
+}
+
+WEAK void GPIO2_IRQHandler(void)
+{
+    GPIO2_DriverIRQHandler();
+}
+
+WEAK void GPIO3_IRQHandler(void)
+{
+    GPIO3_DriverIRQHandler();
+}
+
+WEAK void GPIO4_IRQHandler(void)
+{
+    GPIO4_DriverIRQHandler();
+}
+
+WEAK void Reserved92_IRQHandler(void)
+{
+    Reserved92_DriverIRQHandler();
+}
+
+WEAK void Reserved93_IRQHandler(void)
+{
+    Reserved93_DriverIRQHandler();
+}
+
+WEAK void Reserved94_IRQHandler(void)
+{
+    Reserved94_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void)
+{
+    FLEXPWM1_RELOAD_ERROR_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_FAULT_IRQHandler(void)
+{
+    FLEXPWM1_FAULT_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void)
+{
+    FLEXPWM1_SUBMODULE0_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void)
+{
+    FLEXPWM1_SUBMODULE1_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void)
+{
+    FLEXPWM1_SUBMODULE2_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void)
+{
+    FLEXPWM1_SUBMODULE3_DriverIRQHandler();
+}
+
+WEAK void EQDC1_COMPARE_IRQHandler(void)
+{
+    EQDC1_COMPARE_DriverIRQHandler();
+}
+
+WEAK void EQDC1_HOME_IRQHandler(void)
+{
+    EQDC1_HOME_DriverIRQHandler();
+}
+
+WEAK void EQDC1_WATCHDOG_IRQHandler(void)
+{
+    EQDC1_WATCHDOG_DriverIRQHandler();
+}
+
+WEAK void EQDC1_INDEX_IRQHandler(void)
+{
+    EQDC1_INDEX_DriverIRQHandler();
+}
+
+WEAK void Reserved105_IRQHandler(void)
+{
+    Reserved105_DriverIRQHandler();
+}
+
+WEAK void Reserved106_IRQHandler(void)
+{
+    Reserved106_DriverIRQHandler();
+}
+
+WEAK void Reserved107_IRQHandler(void)
+{
+    Reserved107_DriverIRQHandler();
+}
+
+WEAK void Reserved108_IRQHandler(void)
+{
+    Reserved108_DriverIRQHandler();
+}
+
+WEAK void Reserved109_IRQHandler(void)
+{
+    Reserved109_DriverIRQHandler();
+}
+
+WEAK void Reserved110_IRQHandler(void)
+{
+    Reserved110_DriverIRQHandler();
+}
+
+WEAK void Reserved111_IRQHandler(void)
+{
+    Reserved111_DriverIRQHandler();
+}
+
+WEAK void Reserved112_IRQHandler(void)
+{
+    Reserved112_DriverIRQHandler();
+}
+
+WEAK void Reserved113_IRQHandler(void)
+{
+    Reserved113_DriverIRQHandler();
+}
+
+WEAK void Reserved114_IRQHandler(void)
+{
+    Reserved114_DriverIRQHandler();
+}
+
+WEAK void Reserved115_IRQHandler(void)
+{
+    Reserved115_DriverIRQHandler();
+}
+
+WEAK void Reserved116_IRQHandler(void)
+{
+    Reserved116_DriverIRQHandler();
+}
+
+WEAK void Reserved117_IRQHandler(void)
+{
+    Reserved117_DriverIRQHandler();
+}
+
+WEAK void Reserved118_IRQHandler(void)
+{
+    Reserved118_DriverIRQHandler();
+}
+
+WEAK void Reserved119_IRQHandler(void)
+{
+    Reserved119_DriverIRQHandler();
+}
+
+WEAK void Reserved120_IRQHandler(void)
+{
+    Reserved120_DriverIRQHandler();
+}
+
+WEAK void Reserved121_IRQHandler(void)
+{
+    Reserved121_DriverIRQHandler();
+}
+
+WEAK void Reserved122_IRQHandler(void)
+{
+    Reserved122_DriverIRQHandler();
+}
+
+WEAK void MAU_IRQHandler(void)
+{
+    MAU_DriverIRQHandler();
+}
+
+WEAK void SMARTDMA_IRQHandler(void)
+{
+    SMARTDMA_DriverIRQHandler();
+}
+
+WEAK void Reserved125_IRQHandler(void)
+{
+    Reserved125_DriverIRQHandler();
+}
+
+WEAK void Reserved126_IRQHandler(void)
+{
+    Reserved126_DriverIRQHandler();
+}
+
+WEAK void Reserved127_IRQHandler(void)
+{
+    Reserved127_DriverIRQHandler();
+}
+
+WEAK void Reserved128_IRQHandler(void)
+{
+    Reserved128_DriverIRQHandler();
+}
+
+WEAK void Reserved129_IRQHandler(void)
+{
+    Reserved129_DriverIRQHandler();
+}
+
+WEAK void Reserved130_IRQHandler(void)
+{
+    Reserved130_DriverIRQHandler();
+}
+
+WEAK void Reserved131_IRQHandler(void)
+{
+    Reserved131_DriverIRQHandler();
+}
+
+WEAK void Reserved132_IRQHandler(void)
+{
+    Reserved132_DriverIRQHandler();
+}
+
+WEAK void Reserved133_IRQHandler(void)
+{
+    Reserved133_DriverIRQHandler();
+}
+
+WEAK void Reserved134_IRQHandler(void)
+{
+    Reserved134_DriverIRQHandler();
+}
+
+WEAK void RTC_IRQHandler(void)
+{
+    RTC_DriverIRQHandler();
+}
+
+WEAK void RTC_1HZ_IRQHandler(void)
+{
+    RTC_1HZ_DriverIRQHandler();
+}
+
+//*****************************************************************************
+
+#if defined(DEBUG)
+#if defined(__GNUC__)
+#pragma GCC pop_options
+#endif //(__GNUC__)
+#endif //(DEBUG)
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/system_MCXA343.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/system_MCXA343.c
new file mode 100644
index 0000000000..7f9a2612b2
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/system_MCXA343.c
@@ -0,0 +1,115 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**
+**     Compilers:
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    MCXAP144M180FS6_RM_Rev.1_DraftC
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MCXA343
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief Device specific configuration file for MCXA343 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+#if __has_include("fsl_clock.h")
+#include "fsl_clock.h"
+#endif
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Secure mode */
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Non-secure mode */
+  #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+    SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2));    /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2));    /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */
+#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+    SCB->NSACR |= ((3UL << 0) | (3UL << 10));   /* enable CP0, CP1, CP10, CP11 Non-secure Access */
+
+    /* Enable the LPCAC */
+    SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK;
+    SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK;
+
+    /* Route the PMC bandgap buffer signal to the ADC */
+    SPC0->CORELDO_CFG |= (1U << 24U);
+
+    /* Enables flash speculation */
+    SYSCON->NVM_CTRL &= ~(SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK | SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK);
+    SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK;
+
+  SystemInitHook();
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+#if __has_include("fsl_clock.h")
+    /* Get frequency of Core System */
+    SystemCoreClock = CLOCK_GetCoreSysClkFreq();
+#endif
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInitHook()
+   ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInitHook (void) {
+  /* Void implementation of the weak function. */
+}
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/system_MCXA343.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/system_MCXA343.h
new file mode 100644
index 0000000000..d67b6167d9
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/system_MCXA343.h
@@ -0,0 +1,116 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**
+**     Compilers:
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    MCXAP144M180FS6_RM_Rev.1_DraftC
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MCXA343
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief Device specific configuration file for MCXA343 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_MCXA343_H_
+#define _SYSTEM_MCXA343_H_                       /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define DEFAULT_SYSTEM_CLOCK           12000000u           /* Default System clock value */
+#define CLK_RTC_32K_CLK                   32768u           /* RTC oscillator 32 kHz output (32k_clk */
+#define CLK_FRO_12MHZ                  12000000u           /* FRO 12 MHz (fro_12m) */
+#define CLK_FRO_32MHZ                  32000000u           /* FRO 32 MHz (fro_32m) */
+#define CLK_FRO_48MHZ                  48000000u           /* FRO 48 MHz (fro_48m) */
+
+#ifndef CLK_CLK_IN
+#define CLK_CLK_IN                     16000000u           /* Default CLK_IN pin clock */
+#endif /* CLK_CLK_IN */
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SYSTEM_MCXA343_H_ */
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/variable.cmake
new file mode 100644
index 0000000000..92559a4022
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/variable.cmake
@@ -0,0 +1,14 @@
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+#### chip related
+include(${SdkRootDirPath}/devices/MCX/variable.cmake)
+mcux_set_variable(device MCXA343)
+mcux_set_variable(device_root devices)
+mcux_set_variable(soc_series MCXA)
+mcux_set_variable(soc_periph periph3)
+mcux_set_variable(core_id_suffix_name "")
+mcux_set_variable(multicore_foldername .)
+
+#### Source record
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/CMakeLists.txt
new file mode 100644
index 0000000000..086d5f9916
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+#### device spepcific drivers
+include(${SdkRootDirPath}/devices/arm/device_header_cstartup.cmake)
+mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA344/drivers)
+
+#### MCX shared drivers/components/middlewares, project segments
+include(${SdkRootDirPath}/devices/MCX/shared.cmake)
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344.h
new file mode 100644
index 0000000000..f17f4589ae
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344.h
@@ -0,0 +1,92 @@
+/*
+** ###################################################################
+**     Processors:          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Compilers:
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    MCXAP144M180FS6_RM_Rev.1_DraftC
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MCXA344
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MCXA344.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for MCXA344
+ *
+ * CMSIS Peripheral Access Layer for MCXA344
+ */
+
+#if !defined(MCXA344_H_)  /* Check if memory map has not been already included */
+#define MCXA344_H_
+
+/* IP Header Files List */
+#include "PERI_ADC.h"
+#include "PERI_AOI.h"
+#include "PERI_CAN.h"
+#include "PERI_CDOG.h"
+#include "PERI_CMC.h"
+#include "PERI_CRC.h"
+#include "PERI_CTIMER.h"
+#include "PERI_DEBUGMAILBOX.h"
+#include "PERI_DMA.h"
+#include "PERI_EIM.h"
+#include "PERI_EQDC.h"
+#include "PERI_ERM.h"
+#include "PERI_FMC.h"
+#include "PERI_FMU.h"
+#include "PERI_FREQME.h"
+#include "PERI_GLIKEY.h"
+#include "PERI_GPIO.h"
+#include "PERI_INPUTMUX.h"
+#include "PERI_LPCMP.h"
+#include "PERI_LPI2C.h"
+#include "PERI_LPSPI.h"
+#include "PERI_LPTMR.h"
+#include "PERI_LPUART.h"
+#include "PERI_MAU.h"
+#include "PERI_MRCC.h"
+#include "PERI_OPAMP.h"
+#include "PERI_OSTIMER.h"
+#include "PERI_PORT.h"
+#include "PERI_PWM.h"
+#include "PERI_RTC.h"
+#include "PERI_SCG.h"
+#include "PERI_SMARTDMA.h"
+#include "PERI_SPC.h"
+#include "PERI_SYSCON.h"
+#include "PERI_TRDC.h"
+#include "PERI_UTICK.h"
+#include "PERI_VBAT.h"
+#include "PERI_WAKETIMER.h"
+#include "PERI_WUU.h"
+#include "PERI_WWDT.h"
+
+#endif  /* #if !defined(MCXA344_H_) */
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344_COMMON.h
new file mode 100644
index 0000000000..6d81a9e200
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344_COMMON.h
@@ -0,0 +1,849 @@
+/*
+** ###################################################################
+**     Processors:          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Compilers:
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    MCXAP144M180FS6_RM_Rev.1_DraftC
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MCXA344
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MCXA344_COMMON.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for MCXA344
+ *
+ * CMSIS Peripheral Access Layer for MCXA344
+ */
+
+#if !defined(MCXA344_COMMON_H_)
+#define MCXA344_COMMON_H_                        /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 138                /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M33 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M33 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M33 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M33 Usage Fault Interrupt */
+  SecureFault_IRQn             = -9,               /**< Cortex-M33 Secure Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M33 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M33 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M33 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M33 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  Reserved16_IRQn              = 0,                /**< OR IRQ1 to IRQ53 */
+  CMC_IRQn                     = 1,                /**< Core Mode Controller interrupt */
+  DMA_CH0_IRQn                 = 2,                /**< DMA3_0_CH0 error or transfer complete */
+  DMA_CH1_IRQn                 = 3,                /**< DMA3_0_CH1 error or transfer complete */
+  DMA_CH2_IRQn                 = 4,                /**< DMA3_0_CH2 error or transfer complete */
+  DMA_CH3_IRQn                 = 5,                /**< DMA3_0_CH3 error or transfer complete */
+  DMA_CH4_IRQn                 = 6,                /**< DMA3_0_CH4 error or transfer complete */
+  DMA_CH5_IRQn                 = 7,                /**< DMA3_0_CH5 error or transfer complete */
+  DMA_CH6_IRQn                 = 8,                /**< DMA3_0_CH6 error or transfer complete */
+  DMA_CH7_IRQn                 = 9,                /**< DMA3_0_CH7 error or transfer complete */
+  ERM0_SINGLE_BIT_IRQn         = 10,               /**< ERM Single Bit error interrupt */
+  ERM0_MULTI_BIT_IRQn          = 11,               /**< ERM Multi Bit error interrupt */
+  FMU0_IRQn                    = 12,               /**< Flash Management Unit interrupt */
+  GLIKEY0_IRQn                 = 13,               /**< GLIKEY Interrupt  */
+  MBC0_IRQn                    = 14,               /**< MBC secure violation interrupt */
+  SCG0_IRQn                    = 15,               /**< System Clock Generator interrupt */
+  SPC0_IRQn                    = 16,               /**< System Power Controller interrupt */
+  Reserved33_IRQn              = 17,               /**< Reserved interrupt */
+  WUU0_IRQn                    = 18,               /**< Wake Up Unit interrupt */
+  CAN0_IRQn                    = 19,               /**< Controller Area Network 0 interrupt */
+  Reserved36_IRQn              = 20,               /**< Reserved interrupt */
+  Reserved37_IRQn              = 21,               /**< Reserved interrupt */
+  Reserved38_IRQn              = 22,               /**< Reserved interrupt */
+  Reserved39_IRQn              = 23,               /**< Reserved interrupt */
+  Reserved40_IRQn              = 24,               /**< Reserved interrupt */
+  Reserved41_IRQn              = 25,               /**< Reserved interrupt */
+  LPI2C0_IRQn                  = 26,               /**< Low-Power Inter Integrated Circuit 0 interrupt */
+  LPI2C1_IRQn                  = 27,               /**< Low-Power Inter Integrated Circuit 1 interrupt */
+  LPSPI0_IRQn                  = 28,               /**< Low-Power Serial Peripheral Interface 0 interrupt */
+  LPSPI1_IRQn                  = 29,               /**< Low-Power Serial Peripheral Interface 1 interrupt */
+  Reserved46_IRQn              = 30,               /**< Reserved interrupt */
+  LPUART0_IRQn                 = 31,               /**< Low-Power Universal Asynchronous Receive/Transmit 0 interrupt */
+  LPUART1_IRQn                 = 32,               /**< Low-Power Universal Asynchronous Receive/Transmit 1 interrupt */
+  LPUART2_IRQn                 = 33,               /**< Low-Power Universal Asynchronous Receive/Transmit 2 interrupt */
+  LPUART3_IRQn                 = 34,               /**< Low-Power Universal Asynchronous Receive/Transmit 3 interrupt */
+  Reserved51_IRQn              = 35,               /**< Reserved interrupt */
+  Reserved52_IRQn              = 36,               /**< Reserved interrupt */
+  Reserved53_IRQn              = 37,               /**< Reserved interrupt */
+  CDOG0_IRQn                   = 38,               /**< Code Watchdog Timer 0 interrupt */
+  CTIMER0_IRQn                 = 39,               /**< Standard counter/timer 0 interrupt */
+  CTIMER1_IRQn                 = 40,               /**< Standard counter/timer 1 interrupt */
+  CTIMER2_IRQn                 = 41,               /**< Standard counter/timer 2 interrupt */
+  Reserved58_IRQn              = 42,               /**< Reserved interrupt */
+  Reserved59_IRQn              = 43,               /**< Reserved interrupt */
+  FLEXPWM0_RELOAD_ERROR_IRQn   = 44,               /**< FlexPWM0_reload_error interrupt */
+  FLEXPWM0_FAULT_IRQn          = 45,               /**< FlexPWM0_fault interrupt */
+  FLEXPWM0_SUBMODULE0_IRQn     = 46,               /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */
+  FLEXPWM0_SUBMODULE1_IRQn     = 47,               /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */
+  FLEXPWM0_SUBMODULE2_IRQn     = 48,               /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */
+  FLEXPWM0_SUBMODULE3_IRQn     = 49,               /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */
+  EQDC0_COMPARE_IRQn           = 50,               /**< Compare */
+  EQDC0_HOME_IRQn              = 51,               /**< Home */
+  EQDC0_WATCHDOG_IRQn          = 52,               /**< Watchdog / Simultaneous A and B Change */
+  EQDC0_INDEX_IRQn             = 53,               /**< Index / Roll Over / Roll Under */
+  FREQME0_IRQn                 = 54,               /**< Frequency Measurement interrupt */
+  LPTMR0_IRQn                  = 55,               /**< Low Power Timer 0 interrupt */
+  Reserved72_IRQn              = 56,               /**< Reserved interrupt */
+  OS_EVENT_IRQn                = 57,               /**< OS event timer interrupt */
+  WAKETIMER0_IRQn              = 58,               /**< Wake Timer Interrupt */
+  UTICK0_IRQn                  = 59,               /**< Micro-Tick Timer interrupt */
+  WWDT0_IRQn                   = 60,               /**< Windowed Watchdog Timer 0 interrupt */
+  ADC0_IRQn                    = 62,               /**< Analog-to-Digital Converter 0 interrupt */
+  ADC1_IRQn                    = 63,               /**< Analog-to-Digital Converter 1 interrupt */
+  CMP0_IRQn                    = 64,               /**< Comparator 0 interrupt */
+  CMP1_IRQn                    = 65,               /**< Comparator 1 interrupt */
+  CMP2_IRQn                    = 66,               /**< Comparator 2 interrupt */
+  Reserved83_IRQn              = 67,               /**< Reserved interrupt */
+  Reserved84_IRQn              = 68,               /**< Reserved interrupt */
+  Reserved85_IRQn              = 69,               /**< Reserved interrupt */
+  Reserved86_IRQn              = 70,               /**< Reserved interrupt */
+  GPIO0_IRQn                   = 71,               /**< General Purpose Input/Output interrupt 0 */
+  GPIO1_IRQn                   = 72,               /**< General Purpose Input/Output interrupt 1 */
+  GPIO2_IRQn                   = 73,               /**< General Purpose Input/Output interrupt 2 */
+  GPIO3_IRQn                   = 74,               /**< General Purpose Input/Output interrupt 3 */
+  GPIO4_IRQn                   = 75,               /**< General Purpose Input/Output interrupt 4 */
+  Reserved92_IRQn              = 76,               /**< Reserved interrupt */
+  Reserved93_IRQn              = 77,               /**< Reserved interrupt */
+  Reserved94_IRQn              = 78,               /**< Reserved interrupt */
+  FLEXPWM1_RELOAD_ERROR_IRQn   = 79,               /**< FlexPWM1_reload_error interrupt */
+  FLEXPWM1_FAULT_IRQn          = 80,               /**< FlexPWM1_fault interrupt */
+  FLEXPWM1_SUBMODULE0_IRQn     = 81,               /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */
+  FLEXPWM1_SUBMODULE1_IRQn     = 82,               /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */
+  FLEXPWM1_SUBMODULE2_IRQn     = 83,               /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */
+  FLEXPWM1_SUBMODULE3_IRQn     = 84,               /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */
+  EQDC1_COMPARE_IRQn           = 85,               /**< Compare */
+  EQDC1_HOME_IRQn              = 86,               /**< Home */
+  EQDC1_WATCHDOG_IRQn          = 87,               /**< Watchdog / Simultaneous A and B Change */
+  EQDC1_INDEX_IRQn             = 88,               /**< Index / Roll Over / Roll Under */
+  Reserved105_IRQn             = 89,               /**< Reserved interrupt */
+  Reserved106_IRQn             = 90,               /**< Reserved interrupt */
+  Reserved107_IRQn             = 91,               /**< Reserved interrupt */
+  Reserved108_IRQn             = 92,               /**< Reserved interrupt */
+  Reserved109_IRQn             = 93,               /**< Reserved interrupt */
+  Reserved110_IRQn             = 94,               /**< Reserved interrupt */
+  Reserved111_IRQn             = 95,               /**< Reserved interrupt */
+  Reserved112_IRQn             = 96,               /**< Reserved interrupt */
+  Reserved113_IRQn             = 97,               /**< Reserved interrupt */
+  Reserved114_IRQn             = 98,               /**< Reserved interrupt */
+  Reserved115_IRQn             = 99,               /**< Reserved interrupt */
+  Reserved116_IRQn             = 100,              /**< Reserved interrupt */
+  Reserved117_IRQn             = 101,              /**< Reserved interrupt */
+  Reserved118_IRQn             = 102,              /**< Reserved interrupt */
+  Reserved119_IRQn             = 103,              /**< Reserved interrupt */
+  Reserved120_IRQn             = 104,              /**< Reserved interrupt */
+  Reserved121_IRQn             = 105,              /**< Reserved interrupt */
+  Reserved122_IRQn             = 106,              /**< Reserved interrupt */
+  MAU_IRQn                     = 107,              /**< MAU interrupt */
+  SMARTDMA_IRQn                = 108,              /**< SmartDMA interrupt */
+  Reserved125_IRQn             = 109,              /**< Reserved interrupt */
+  Reserved126_IRQn             = 110,              /**< Reserved interrupt */
+  Reserved127_IRQn             = 111,              /**< Reserved interrupt */
+  Reserved128_IRQn             = 112,              /**< Reserved interrupt */
+  Reserved129_IRQn             = 113,              /**< Reserved interrupt */
+  Reserved130_IRQn             = 114,              /**< Reserved interrupt */
+  Reserved131_IRQn             = 115,              /**< Reserved interrupt */
+  Reserved132_IRQn             = 116,              /**< Reserved interrupt */
+  Reserved133_IRQn             = 117,              /**< Reserved interrupt */
+  Reserved134_IRQn             = 118,              /**< Reserved interrupt */
+  RTC_IRQn                     = 119,              /**< RTC alarm interrupt */
+  RTC_1HZ_IRQn                 = 120,              /**< RTC 1Hz interrupt */
+  Reserved137_IRQn             = 121               /**< Reserved interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M33 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+#define __DSP_PRESENT                  1         /**< Defines if Armv8-M Mainline core supports DSP instructions */
+#define __SAUREGION_PRESENT            0         /**< Defines if an SAU is present or not */
+
+#include "core_cm33.h"                 /* Core Peripheral Access Layer */
+#include "system_MCXA344.h"            /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+#ifndef MCXA344_SERIES
+#define MCXA344_SERIES
+#endif
+/* CPU specific feature definitions */
+#include "MCXA344_features.h"
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x400AF000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE                                (0x400B0000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1                                     ((ADC_Type *)ADC1_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0, ADC1 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn, ADC1_IRQn }
+
+/* AOI - Peripheral instance base addresses */
+/** Peripheral AOI0 base address */
+#define AOI0_BASE                                (0x40089000u)
+/** Peripheral AOI0 base pointer */
+#define AOI0                                     ((AOI_Type *)AOI0_BASE)
+/** Peripheral AOI1 base address */
+#define AOI1_BASE                                (0x40097000u)
+/** Peripheral AOI1 base pointer */
+#define AOI1                                     ((AOI_Type *)AOI1_BASE)
+/** Array initializer of AOI peripheral base addresses */
+#define AOI_BASE_ADDRS                           { AOI0_BASE, AOI1_BASE }
+/** Array initializer of AOI peripheral base pointers */
+#define AOI_BASE_PTRS                            { AOI0, AOI1 }
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE                                (0x400CC000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0                                     ((CAN_Type *)CAN0_BASE)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS                           { CAN0_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS                            { CAN0 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_Rx_Warning_IRQS                      { CAN0_IRQn }
+#define CAN_Tx_Warning_IRQS                      { CAN0_IRQn }
+#define CAN_Wake_Up_IRQS                         { CAN0_IRQn }
+#define CAN_Error_IRQS                           { CAN0_IRQn }
+#define CAN_Bus_Off_IRQS                         { CAN0_IRQn }
+#define CAN_ORed_Message_buffer_IRQS             { CAN0_IRQn }
+
+/* CDOG - Peripheral instance base addresses */
+/** Peripheral CDOG0 base address */
+#define CDOG0_BASE                               (0x40100000u)
+/** Peripheral CDOG0 base pointer */
+#define CDOG0                                    ((CDOG_Type *)CDOG0_BASE)
+/** Array initializer of CDOG peripheral base addresses */
+#define CDOG_BASE_ADDRS                          { CDOG0_BASE }
+/** Array initializer of CDOG peripheral base pointers */
+#define CDOG_BASE_PTRS                           { CDOG0 }
+/** Interrupt vectors for the CDOG peripheral type */
+#define CDOG_IRQS                                { CDOG0_IRQn }
+
+/* CMC - Peripheral instance base addresses */
+/** Peripheral CMC base address */
+#define CMC_BASE                                 (0x4008B000u)
+/** Peripheral CMC base pointer */
+#define CMC                                      ((CMC_Type *)CMC_BASE)
+/** Array initializer of CMC peripheral base addresses */
+#define CMC_BASE_ADDRS                           { CMC_BASE }
+/** Array initializer of CMC peripheral base pointers */
+#define CMC_BASE_PTRS                            { CMC }
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC0 base address */
+#define CRC0_BASE                                (0x4008A000u)
+/** Peripheral CRC0 base pointer */
+#define CRC0                                     ((CRC_Type *)CRC0_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC0_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC0 }
+
+/* CTIMER - Peripheral instance base addresses */
+/** Peripheral CTIMER0 base address */
+#define CTIMER0_BASE                             (0x40004000u)
+/** Peripheral CTIMER0 base pointer */
+#define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
+/** Peripheral CTIMER1 base address */
+#define CTIMER1_BASE                             (0x40005000u)
+/** Peripheral CTIMER1 base pointer */
+#define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
+/** Peripheral CTIMER2 base address */
+#define CTIMER2_BASE                             (0x40006000u)
+/** Peripheral CTIMER2 base pointer */
+#define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
+/** Array initializer of CTIMER peripheral base addresses */
+#define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE }
+/** Array initializer of CTIMER peripheral base pointers */
+#define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2 }
+/** Interrupt vectors for the CTIMER peripheral type */
+#define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn }
+
+/* DEBUGMAILBOX - Peripheral instance base addresses */
+/** Peripheral DBGMAILBOX base address */
+#define DBGMAILBOX_BASE                          (0x40101000u)
+/** Peripheral DBGMAILBOX base pointer */
+#define DBGMAILBOX                               ((DEBUGMAILBOX_Type *)DBGMAILBOX_BASE)
+/** Array initializer of DEBUGMAILBOX peripheral base addresses */
+#define DEBUGMAILBOX_BASE_ADDRS                  { DBGMAILBOX_BASE }
+/** Array initializer of DEBUGMAILBOX peripheral base pointers */
+#define DEBUGMAILBOX_BASE_PTRS                   { DBGMAILBOX }
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA0 base address */
+#define DMA0_BASE                                (0x40080000u)
+/** Peripheral DMA0 base pointer */
+#define DMA0                                     ((DMA_Type *)DMA0_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA0_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+
+/* EIM - Peripheral instance base addresses */
+/** Peripheral EIM0 base address */
+#define EIM0_BASE                                (0x4008C000u)
+/** Peripheral EIM0 base pointer */
+#define EIM0                                     ((EIM_Type *)EIM0_BASE)
+/** Array initializer of EIM peripheral base addresses */
+#define EIM_BASE_ADDRS                           { EIM0_BASE }
+/** Array initializer of EIM peripheral base pointers */
+#define EIM_BASE_PTRS                            { EIM0 }
+
+/* EQDC - Peripheral instance base addresses */
+/** Peripheral EQDC0 base address */
+#define EQDC0_BASE                               (0x400A7000u)
+/** Peripheral EQDC0 base pointer */
+#define EQDC0                                    ((EQDC_Type *)EQDC0_BASE)
+/** Peripheral EQDC1 base address */
+#define EQDC1_BASE                               (0x400A8000u)
+/** Peripheral EQDC1 base pointer */
+#define EQDC1                                    ((EQDC_Type *)EQDC1_BASE)
+/** Array initializer of EQDC peripheral base addresses */
+#define EQDC_BASE_ADDRS                          { EQDC0_BASE, EQDC1_BASE }
+/** Array initializer of EQDC peripheral base pointers */
+#define EQDC_BASE_PTRS                           { EQDC0, EQDC1 }
+/** Interrupt vectors for the EQDC peripheral type */
+#define EQDC_COMPARE_IRQS                        { EQDC0_COMPARE_IRQn, EQDC1_COMPARE_IRQn }
+#define EQDC_HOME_IRQS                           { EQDC0_HOME_IRQn, EQDC1_HOME_IRQn }
+#define EQDC_WDOG_IRQS                           { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn }
+#define EQDC_INDEX_IRQS                          { EQDC0_INDEX_IRQn, EQDC1_INDEX_IRQn }
+#define EQDC_INPUT_SWITCH_IRQS                   { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn }
+
+/* ERM - Peripheral instance base addresses */
+/** Peripheral ERM0 base address */
+#define ERM0_BASE                                (0x4008D000u)
+/** Peripheral ERM0 base pointer */
+#define ERM0                                     ((ERM_Type *)ERM0_BASE)
+/** Array initializer of ERM peripheral base addresses */
+#define ERM_BASE_ADDRS                           { ERM0_BASE }
+/** Array initializer of ERM peripheral base pointers */
+#define ERM_BASE_PTRS                            { ERM0 }
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC0 base address */
+#define FMC0_BASE                                (0x40094000u)
+/** Peripheral FMC0 base pointer */
+#define FMC0                                     ((FMC_Type *)FMC0_BASE)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS                           { FMC0_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS                            { FMC0 }
+
+/* FMU - Peripheral instance base addresses */
+/** Peripheral FMU0 base address */
+#define FMU0_BASE                                (0x40095000u)
+/** Peripheral FMU0 base pointer */
+#define FMU0                                     ((FMU_Type *)FMU0_BASE)
+/** Array initializer of FMU peripheral base addresses */
+#define FMU_BASE_ADDRS                           { FMU0_BASE }
+/** Array initializer of FMU peripheral base pointers */
+#define FMU_BASE_PTRS                            { FMU0 }
+
+/* FREQME - Peripheral instance base addresses */
+/** Peripheral FREQME0 base address */
+#define FREQME0_BASE                             (0x40009000u)
+/** Peripheral FREQME0 base pointer */
+#define FREQME0                                  ((FREQME_Type *)FREQME0_BASE)
+/** Array initializer of FREQME peripheral base addresses */
+#define FREQME_BASE_ADDRS                        { FREQME0_BASE }
+/** Array initializer of FREQME peripheral base pointers */
+#define FREQME_BASE_PTRS                         { FREQME0 }
+/** Interrupt vectors for the FREQME peripheral type */
+#define FREQME_IRQS                              { FREQME0_IRQn }
+
+/* GLIKEY - Peripheral instance base addresses */
+/** Peripheral GLIKEY0 base address */
+#define GLIKEY0_BASE                             (0x40091D00u)
+/** Peripheral GLIKEY0 base pointer */
+#define GLIKEY0                                  ((GLIKEY_Type *)GLIKEY0_BASE)
+/** Array initializer of GLIKEY peripheral base addresses */
+#define GLIKEY_BASE_ADDRS                        { GLIKEY0_BASE }
+/** Array initializer of GLIKEY peripheral base pointers */
+#define GLIKEY_BASE_PTRS                         { GLIKEY0 }
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIO0 base address */
+#define GPIO0_BASE                               (0x40102000u)
+/** Peripheral GPIO0 base pointer */
+#define GPIO0                                    ((GPIO_Type *)GPIO0_BASE)
+/** Peripheral GPIO1 base address */
+#define GPIO1_BASE                               (0x40103000u)
+/** Peripheral GPIO1 base pointer */
+#define GPIO1                                    ((GPIO_Type *)GPIO1_BASE)
+/** Peripheral GPIO2 base address */
+#define GPIO2_BASE                               (0x40104000u)
+/** Peripheral GPIO2 base pointer */
+#define GPIO2                                    ((GPIO_Type *)GPIO2_BASE)
+/** Peripheral GPIO3 base address */
+#define GPIO3_BASE                               (0x40105000u)
+/** Peripheral GPIO3 base pointer */
+#define GPIO3                                    ((GPIO_Type *)GPIO3_BASE)
+/** Peripheral GPIO4 base address */
+#define GPIO4_BASE                               (0x40106000u)
+/** Peripheral GPIO4 base pointer */
+#define GPIO4                                    ((GPIO_Type *)GPIO4_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 }
+/** Interrupt vectors for the GPIO peripheral type */
+#define GPIO_IRQS                                { GPIO0_IRQn, GPIO1_IRQn, GPIO2_IRQn, GPIO3_IRQn, GPIO4_IRQn }
+
+/* INPUTMUX - Peripheral instance base addresses */
+/** Peripheral INPUTMUX0 base address */
+#define INPUTMUX0_BASE                           (0x40001000u)
+/** Peripheral INPUTMUX0 base pointer */
+#define INPUTMUX0                                ((INPUTMUX_Type *)INPUTMUX0_BASE)
+/** Array initializer of INPUTMUX peripheral base addresses */
+#define INPUTMUX_BASE_ADDRS                      { INPUTMUX0_BASE }
+/** Array initializer of INPUTMUX peripheral base pointers */
+#define INPUTMUX_BASE_PTRS                       { INPUTMUX0 }
+
+/* LPCMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE                                (0x400B1000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0                                     ((LPCMP_Type *)CMP0_BASE)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE                                (0x400B2000u)
+/** Peripheral CMP1 base pointer */
+#define CMP1                                     ((LPCMP_Type *)CMP1_BASE)
+/** Peripheral CMP2 base address */
+#define CMP2_BASE                                (0x400B3000u)
+/** Peripheral CMP2 base pointer */
+#define CMP2                                     ((LPCMP_Type *)CMP2_BASE)
+/** Array initializer of LPCMP peripheral base addresses */
+#define LPCMP_BASE_ADDRS                         { CMP0_BASE, CMP1_BASE, CMP2_BASE }
+/** Array initializer of LPCMP peripheral base pointers */
+#define LPCMP_BASE_PTRS                          { CMP0, CMP1, CMP2 }
+
+/* LPI2C - Peripheral instance base addresses */
+/** Peripheral LPI2C0 base address */
+#define LPI2C0_BASE                              (0x4009A000u)
+/** Peripheral LPI2C0 base pointer */
+#define LPI2C0                                   ((LPI2C_Type *)LPI2C0_BASE)
+/** Peripheral LPI2C1 base address */
+#define LPI2C1_BASE                              (0x4009B000u)
+/** Peripheral LPI2C1 base pointer */
+#define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
+/** Array initializer of LPI2C peripheral base addresses */
+#define LPI2C_BASE_ADDRS                         { LPI2C0_BASE, LPI2C1_BASE }
+/** Array initializer of LPI2C peripheral base pointers */
+#define LPI2C_BASE_PTRS                          { LPI2C0, LPI2C1 }
+/** Interrupt vectors for the LPI2C peripheral type */
+#define LPI2C_IRQS                               { LPI2C0_IRQn, LPI2C1_IRQn }
+
+/* LPSPI - Peripheral instance base addresses */
+/** Peripheral LPSPI0 base address */
+#define LPSPI0_BASE                              (0x4009C000u)
+/** Peripheral LPSPI0 base pointer */
+#define LPSPI0                                   ((LPSPI_Type *)LPSPI0_BASE)
+/** Peripheral LPSPI1 base address */
+#define LPSPI1_BASE                              (0x4009D000u)
+/** Peripheral LPSPI1 base pointer */
+#define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
+/** Array initializer of LPSPI peripheral base addresses */
+#define LPSPI_BASE_ADDRS                         { LPSPI0_BASE, LPSPI1_BASE }
+/** Array initializer of LPSPI peripheral base pointers */
+#define LPSPI_BASE_PTRS                          { LPSPI0, LPSPI1 }
+/** Interrupt vectors for the LPSPI peripheral type */
+#define LPSPI_IRQS                               { LPSPI0_IRQn, LPSPI1_IRQn }
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x400AB000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS                          { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn }
+
+/* LPUART - Peripheral instance base addresses */
+/** Peripheral LPUART0 base address */
+#define LPUART0_BASE                             (0x4009F000u)
+/** Peripheral LPUART0 base pointer */
+#define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
+/** Peripheral LPUART1 base address */
+#define LPUART1_BASE                             (0x400A0000u)
+/** Peripheral LPUART1 base pointer */
+#define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
+/** Peripheral LPUART2 base address */
+#define LPUART2_BASE                             (0x400A1000u)
+/** Peripheral LPUART2 base pointer */
+#define LPUART2                                  ((LPUART_Type *)LPUART2_BASE)
+/** Peripheral LPUART3 base address */
+#define LPUART3_BASE                             (0x400A2000u)
+/** Peripheral LPUART3 base pointer */
+#define LPUART3                                  ((LPUART_Type *)LPUART3_BASE)
+/** Array initializer of LPUART peripheral base addresses */
+#define LPUART_BASE_ADDRS                        { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE }
+/** Array initializer of LPUART peripheral base pointers */
+#define LPUART_BASE_PTRS                         { LPUART0, LPUART1, LPUART2, LPUART3 }
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS                        { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn }
+#define LPUART_ERR_IRQS                          { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn }
+
+/* MAU - Peripheral instance base addresses */
+/** Peripheral MAU0 base address */
+#define MAU0_BASE                                (0x40108000u)
+/** Peripheral MAU0 base pointer */
+#define MAU0                                     ((MAU_Type *)MAU0_BASE)
+/** Array initializer of MAU peripheral base addresses */
+#define MAU_BASE_ADDRS                           { MAU0_BASE }
+/** Array initializer of MAU peripheral base pointers */
+#define MAU_BASE_PTRS                            { MAU0 }
+/** Interrupt vectors for the MAU peripheral type */
+#define MAU_IRQS                                 { MAU_IRQn }
+
+/* MRCC - Peripheral instance base addresses */
+/** Peripheral MRCC0 base address */
+#define MRCC0_BASE                               (0x40091000u)
+/** Peripheral MRCC0 base pointer */
+#define MRCC0                                    ((MRCC_Type *)MRCC0_BASE)
+/** Array initializer of MRCC peripheral base addresses */
+#define MRCC_BASE_ADDRS                          { MRCC0_BASE }
+/** Array initializer of MRCC peripheral base pointers */
+#define MRCC_BASE_PTRS                           { MRCC0 }
+
+/* OPAMP - Peripheral instance base addresses */
+/** Peripheral OPAMP0 base address */
+#define OPAMP0_BASE                              (0x400B7000u)
+/** Peripheral OPAMP0 base pointer */
+#define OPAMP0                                   ((OPAMP_Type *)OPAMP0_BASE)
+/** Peripheral OPAMP1 base address */
+#define OPAMP1_BASE                              (0x400B8000u)
+/** Peripheral OPAMP1 base pointer */
+#define OPAMP1                                   ((OPAMP_Type *)OPAMP1_BASE)
+/** Peripheral OPAMP2 base address */
+#define OPAMP2_BASE                              (0x400B9000u)
+/** Peripheral OPAMP2 base pointer */
+#define OPAMP2                                   ((OPAMP_Type *)OPAMP2_BASE)
+/** Array initializer of OPAMP peripheral base addresses */
+#define OPAMP_BASE_ADDRS                         { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE }
+/** Array initializer of OPAMP peripheral base pointers */
+#define OPAMP_BASE_PTRS                          { OPAMP0, OPAMP1, OPAMP2 }
+
+/* OSTIMER - Peripheral instance base addresses */
+/** Peripheral OSTIMER0 base address */
+#define OSTIMER0_BASE                            (0x400AD000u)
+/** Peripheral OSTIMER0 base pointer */
+#define OSTIMER0                                 ((OSTIMER_Type *)OSTIMER0_BASE)
+/** Array initializer of OSTIMER peripheral base addresses */
+#define OSTIMER_BASE_ADDRS                       { OSTIMER0_BASE }
+/** Array initializer of OSTIMER peripheral base pointers */
+#define OSTIMER_BASE_PTRS                        { OSTIMER0 }
+/** Interrupt vectors for the OSTIMER peripheral type */
+#define OSTIMER_IRQS                             { OS_EVENT_IRQn }
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORT0 base address */
+#define PORT0_BASE                               (0x400BC000u)
+/** Peripheral PORT0 base pointer */
+#define PORT0                                    ((PORT_Type *)PORT0_BASE)
+/** Peripheral PORT1 base address */
+#define PORT1_BASE                               (0x400BD000u)
+/** Peripheral PORT1 base pointer */
+#define PORT1                                    ((PORT_Type *)PORT1_BASE)
+/** Peripheral PORT2 base address */
+#define PORT2_BASE                               (0x400BE000u)
+/** Peripheral PORT2 base pointer */
+#define PORT2                                    ((PORT_Type *)PORT2_BASE)
+/** Peripheral PORT3 base address */
+#define PORT3_BASE                               (0x400BF000u)
+/** Peripheral PORT3 base pointer */
+#define PORT3                                    ((PORT_Type *)PORT3_BASE)
+/** Peripheral PORT4 base address */
+#define PORT4_BASE                               (0x400C0000u)
+/** Peripheral PORT4 base pointer */
+#define PORT4                                    ((PORT_Type *)PORT4_BASE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS                          { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS                           { PORT0, PORT1, PORT2, PORT3, PORT4 }
+
+/* PWM - Peripheral instance base addresses */
+/** Peripheral FLEXPWM0 base address */
+#define FLEXPWM0_BASE                            (0x400A9000u)
+/** Peripheral FLEXPWM0 base pointer */
+#define FLEXPWM0                                 ((PWM_Type *)FLEXPWM0_BASE)
+/** Peripheral FLEXPWM1 base address */
+#define FLEXPWM1_BASE                            (0x400AA000u)
+/** Peripheral FLEXPWM1 base pointer */
+#define FLEXPWM1                                 ((PWM_Type *)FLEXPWM1_BASE)
+/** Array initializer of PWM peripheral base addresses */
+#define PWM_BASE_ADDRS                           { FLEXPWM0_BASE, FLEXPWM1_BASE }
+/** Array initializer of PWM peripheral base pointers */
+#define PWM_BASE_PTRS                            { FLEXPWM0, FLEXPWM1 }
+/** Interrupt vectors for the PWM peripheral type */
+#define PWM_CMP_IRQS                             { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } }
+#define PWM_RELOAD_IRQS                          { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } }
+#define PWM_CAPTURE_IRQS                         { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } }
+#define PWM_FAULT_IRQS                           { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn }
+#define PWM_RELOAD_ERROR_IRQS                    { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn }
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC0 base address */
+#define RTC0_BASE                                (0x400EE000u)
+/** Peripheral RTC0 base pointer */
+#define RTC0                                     ((RTC_Type *)RTC0_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC0_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC0 }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+
+/* SCG - Peripheral instance base addresses */
+/** Peripheral SCG0 base address */
+#define SCG0_BASE                                (0x4008F000u)
+/** Peripheral SCG0 base pointer */
+#define SCG0                                     ((SCG_Type *)SCG0_BASE)
+/** Array initializer of SCG peripheral base addresses */
+#define SCG_BASE_ADDRS                           { SCG0_BASE }
+/** Array initializer of SCG peripheral base pointers */
+#define SCG_BASE_PTRS                            { SCG0 }
+
+/* SMARTDMA - Peripheral instance base addresses */
+/** Peripheral SMARTDMA0 base address */
+#define SMARTDMA0_BASE                           (0x4000E000u)
+/** Peripheral SMARTDMA0 base pointer */
+#define SMARTDMA0                                ((SMARTDMA_Type *)SMARTDMA0_BASE)
+/** Array initializer of SMARTDMA peripheral base addresses */
+#define SMARTDMA_BASE_ADDRS                      { SMARTDMA0_BASE }
+/** Array initializer of SMARTDMA peripheral base pointers */
+#define SMARTDMA_BASE_PTRS                       { SMARTDMA0 }
+
+/* SPC - Peripheral instance base addresses */
+/** Peripheral SPC0 base address */
+#define SPC0_BASE                                (0x40090000u)
+/** Peripheral SPC0 base pointer */
+#define SPC0                                     ((SPC_Type *)SPC0_BASE)
+/** Array initializer of SPC peripheral base addresses */
+#define SPC_BASE_ADDRS                           { SPC0_BASE }
+/** Array initializer of SPC peripheral base pointers */
+#define SPC_BASE_PTRS                            { SPC0 }
+
+/* SYSCON - Peripheral instance base addresses */
+/** Peripheral SYSCON base address */
+#define SYSCON_BASE                              (0x40091000u)
+/** Peripheral SYSCON base pointer */
+#define SYSCON                                   ((SYSCON_Type *)SYSCON_BASE)
+/** Array initializer of SYSCON peripheral base addresses */
+#define SYSCON_BASE_ADDRS                        { SYSCON_BASE }
+/** Array initializer of SYSCON peripheral base pointers */
+#define SYSCON_BASE_PTRS                         { SYSCON }
+
+/* TRDC - Peripheral instance base addresses */
+/** Peripheral MBC0 base address */
+#define MBC0_BASE                                (0x4008E000u)
+/** Peripheral MBC0 base pointer */
+#define MBC0                                     ((TRDC_Type *)MBC0_BASE)
+/** Array initializer of TRDC peripheral base addresses */
+#define TRDC_BASE_ADDRS                          { MBC0_BASE }
+/** Array initializer of TRDC peripheral base pointers */
+#define TRDC_BASE_PTRS                           { MBC0 }
+#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1}
+#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1}
+#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1}
+#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0}
+#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT}
+#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1}
+#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1}
+#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1}
+#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0}
+#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT}
+
+
+/* UTICK - Peripheral instance base addresses */
+/** Peripheral UTICK0 base address */
+#define UTICK0_BASE                              (0x4000B000u)
+/** Peripheral UTICK0 base pointer */
+#define UTICK0                                   ((UTICK_Type *)UTICK0_BASE)
+/** Array initializer of UTICK peripheral base addresses */
+#define UTICK_BASE_ADDRS                         { UTICK0_BASE }
+/** Array initializer of UTICK peripheral base pointers */
+#define UTICK_BASE_PTRS                          { UTICK0 }
+/** Interrupt vectors for the UTICK peripheral type */
+#define UTICK_IRQS                               { UTICK0_IRQn }
+
+/* VBAT - Peripheral instance base addresses */
+/** Peripheral VBAT0 base address */
+#define VBAT0_BASE                               (0x40093000u)
+/** Peripheral VBAT0 base pointer */
+#define VBAT0                                    ((VBAT_Type *)VBAT0_BASE)
+/** Array initializer of VBAT peripheral base addresses */
+#define VBAT_BASE_ADDRS                          { VBAT0_BASE }
+/** Array initializer of VBAT peripheral base pointers */
+#define VBAT_BASE_PTRS                           { VBAT0 }
+
+/* WAKETIMER - Peripheral instance base addresses */
+/** Peripheral WAKETIMER0 base address */
+#define WAKETIMER0_BASE                          (0x400AE000u)
+/** Peripheral WAKETIMER0 base pointer */
+#define WAKETIMER0                               ((WAKETIMER_Type *)WAKETIMER0_BASE)
+/** Array initializer of WAKETIMER peripheral base addresses */
+#define WAKETIMER_BASE_ADDRS                     { WAKETIMER0_BASE }
+/** Array initializer of WAKETIMER peripheral base pointers */
+#define WAKETIMER_BASE_PTRS                      { WAKETIMER0 }
+/** Interrupt vectors for the WAKETIMER peripheral type */
+#define WAKETIMER_IRQS                           { WAKETIMER0_IRQn }
+
+/* WUU - Peripheral instance base addresses */
+/** Peripheral WUU0 base address */
+#define WUU0_BASE                                (0x40092000u)
+/** Peripheral WUU0 base pointer */
+#define WUU0                                     ((WUU_Type *)WUU0_BASE)
+/** Array initializer of WUU peripheral base addresses */
+#define WUU_BASE_ADDRS                           { WUU0_BASE }
+/** Array initializer of WUU peripheral base pointers */
+#define WUU_BASE_PTRS                            { WUU0 }
+
+/* WWDT - Peripheral instance base addresses */
+/** Peripheral WWDT0 base address */
+#define WWDT0_BASE                               (0x4000C000u)
+/** Peripheral WWDT0 base pointer */
+#define WWDT0                                    ((WWDT_Type *)WWDT0_BASE)
+/** Array initializer of WWDT peripheral base addresses */
+#define WWDT_BASE_ADDRS                          { WWDT0_BASE }
+/** Array initializer of WWDT peripheral base pointers */
+#define WWDT_BASE_PTRS                           { WWDT0 }
+
+/* ----------------------------------------------------------------------------
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDK Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif  /* MCXA344_COMMON_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344_features.h
new file mode 100644
index 0000000000..224dbf782e
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344_features.h
@@ -0,0 +1,898 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2024-03-26
+**     Build:               b250814
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**
+** ###################################################################
+*/
+
+#ifndef _MCXA344_FEATURES_H_
+#define _MCXA344_FEATURES_H_
+
+/* SOC module features */
+
+#if defined(CPU_MCXA344VFM)
+    /* @brief AOI availability on the SoC. */
+    #define FSL_FEATURE_SOC_AOI_COUNT (2)
+    /* @brief CDOG availability on the SoC. */
+    #define FSL_FEATURE_SOC_CDOG_COUNT (1)
+    /* @brief CMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMC_COUNT (1)
+    /* @brief CRC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CRC_COUNT (1)
+    /* @brief CTIMER availability on the SoC. */
+    #define FSL_FEATURE_SOC_CTIMER_COUNT (3)
+    /* @brief EDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_EDMA_COUNT (1)
+    /* @brief EIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EIM_COUNT (1)
+    /* @brief EQDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_EQDC_COUNT (2)
+    /* @brief FLEXCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
+    /* @brief FMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_FMC_COUNT (1)
+    /* @brief FREQME availability on the SoC. */
+    #define FSL_FEATURE_SOC_FREQME_COUNT (1)
+    /* @brief GPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_GPIO_COUNT (5)
+    /* @brief SPC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SPC_COUNT (1)
+    /* @brief INPUTMUX availability on the SoC. */
+    #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+    /* @brief LPADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPADC_COUNT (2)
+    /* @brief LPCMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPCMP_COUNT (3)
+    /* @brief LPI2C availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPI2C_COUNT (2)
+    /* @brief LPSPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPSPI_COUNT (2)
+    /* @brief LPTMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+    /* @brief LPUART availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPUART_COUNT (4)
+    /* @brief OPAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_OPAMP_COUNT (1)
+    /* @brief OSTIMER availability on the SoC. */
+    #define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
+    /* @brief PORT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PORT_COUNT (5)
+    /* @brief PWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWM_COUNT (2)
+    /* @brief RTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_RTC_COUNT (1)
+    /* @brief SCG availability on the SoC. */
+    #define FSL_FEATURE_SOC_SCG_COUNT (1)
+    /* @brief SMARTDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1)
+    /* @brief SYSCON availability on the SoC. */
+    #define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+    /* @brief UTICK availability on the SoC. */
+    #define FSL_FEATURE_SOC_UTICK_COUNT (1)
+    /* @brief WAKETIMER availability on the SoC. */
+    #define FSL_FEATURE_SOC_WAKETIMER_COUNT (1)
+    /* @brief WWDT availability on the SoC. */
+    #define FSL_FEATURE_SOC_WWDT_COUNT (1)
+    /* @brief WUU availability on the SoC. */
+    #define FSL_FEATURE_SOC_WUU_COUNT (1)
+#elif defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)
+    /* @brief AOI availability on the SoC. */
+    #define FSL_FEATURE_SOC_AOI_COUNT (2)
+    /* @brief CDOG availability on the SoC. */
+    #define FSL_FEATURE_SOC_CDOG_COUNT (1)
+    /* @brief CMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMC_COUNT (1)
+    /* @brief CRC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CRC_COUNT (1)
+    /* @brief CTIMER availability on the SoC. */
+    #define FSL_FEATURE_SOC_CTIMER_COUNT (3)
+    /* @brief EDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_EDMA_COUNT (1)
+    /* @brief EIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EIM_COUNT (1)
+    /* @brief EQDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_EQDC_COUNT (2)
+    /* @brief FLEXCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
+    /* @brief FMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_FMC_COUNT (1)
+    /* @brief FREQME availability on the SoC. */
+    #define FSL_FEATURE_SOC_FREQME_COUNT (1)
+    /* @brief GPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_GPIO_COUNT (5)
+    /* @brief SPC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SPC_COUNT (1)
+    /* @brief INPUTMUX availability on the SoC. */
+    #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+    /* @brief LPADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPADC_COUNT (2)
+    /* @brief LPCMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPCMP_COUNT (3)
+    /* @brief LPI2C availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPI2C_COUNT (2)
+    /* @brief LPSPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPSPI_COUNT (2)
+    /* @brief LPTMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+    /* @brief LPUART availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPUART_COUNT (4)
+    /* @brief OPAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_OPAMP_COUNT (3)
+    /* @brief OSTIMER availability on the SoC. */
+    #define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
+    /* @brief PORT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PORT_COUNT (5)
+    /* @brief PWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWM_COUNT (2)
+    /* @brief RTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_RTC_COUNT (1)
+    /* @brief SCG availability on the SoC. */
+    #define FSL_FEATURE_SOC_SCG_COUNT (1)
+    /* @brief SMARTDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1)
+    /* @brief SYSCON availability on the SoC. */
+    #define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+    /* @brief UTICK availability on the SoC. */
+    #define FSL_FEATURE_SOC_UTICK_COUNT (1)
+    /* @brief WAKETIMER availability on the SoC. */
+    #define FSL_FEATURE_SOC_WAKETIMER_COUNT (1)
+    /* @brief WWDT availability on the SoC. */
+    #define FSL_FEATURE_SOC_WWDT_COUNT (1)
+    /* @brief WUU availability on the SoC. */
+    #define FSL_FEATURE_SOC_WUU_COUNT (1)
+#endif
+
+/* LPADC module features */
+
+/* @brief FIFO availability on the SoC. */
+#define FSL_FEATURE_LPADC_FIFO_COUNT (1)
+/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */
+#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1)
+/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)
+/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
+/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
+/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)
+/* @brief Has conversion resolution select  (bitfield CMDLn[MODE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)
+/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
+#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
+/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)
+/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)
+/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)
+/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
+/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
+/* @brief Has calibration (bitfield CFG[CALOFS]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
+/* @brief Has offset trim (register OFSTRIM). */
+#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
+/* @brief Has power select (bitfield CFG[PWRSEL]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1)
+/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0)
+/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0)
+/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0)
+/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
+/* @brief Conversion averaged bitfiled width. */
+#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4)
+/* @brief Enable hardware trigger command selection */
+#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0)
+/* @brief OFSTRIM availability on the SoC. */
+#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1)
+/* @brief Has Trigger status register. */
+#define FSL_FEATURE_LPADC_HAS_TSTAT (1)
+/* @brief Has B side channels. */
+#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0)
+/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */
+#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1)
+/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */
+#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1)
+/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */
+#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1)
+/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */
+#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1)
+/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */
+#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1)
+/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */
+#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1)
+/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1)
+/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1)
+/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1)
+/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */
+#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2)
+/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
+#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
+/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1)
+/* @brief Has internal temperature sensor. */
+#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1)
+/* @brief Temperature sensor parameter A (slope). */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (738.0f)
+/* @brief Temperature sensor parameter B (offset). */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (287.5f)
+/* @brief Temperature sensor parameter Alpha. */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (10.06f)
+/* @brief The buffer size of temperature sensor. */
+#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U)
+
+/* AOI module features */
+
+/* @brief Maximum value of input mux. */
+#define FSL_FEATURE_AOI_MODULE_INPUTS (4)
+/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */
+#define FSL_FEATURE_AOI_EVENT_COUNT (4)
+
+/* FLEXCAN module features */
+
+/* @brief Message buffer size */
+#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32)
+/* @brief Has doze mode support (register bit field MCR[DOZE]). */
+#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1)
+/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1)
+/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
+#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
+/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
+#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
+/* @brief Instance has extended bit timing register (register CBT). */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1)
+/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
+#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1)
+/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1)
+/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
+#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1)
+/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1)
+/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
+/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0)
+/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0)
+/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0)
+/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
+#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1)
+/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1)
+/* @brief Has memory error control (register MECR). */
+#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0)
+/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */
+#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1)
+/* @brief Has Pretended Networking mode support. */
+#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1)
+/* @brief Has Enhanced Rx FIFO. */
+#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1)
+/* @brief Has Enhanced Rx FIFO. */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1)
+/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */
+#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12)
+/* @brief The number of enhanced Rx FIFO filter element registers. */
+#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32)
+/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */
+#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0)
+/* @brief Has more than 64 MBs. */
+#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0)
+/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */
+#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0)
+/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */
+#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0)
+/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0)
+/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */
+#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0)
+/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1)
+/* @brief FlexCAN maximum data rate. */
+#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000)
+/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */
+#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (1)
+/* @brief Enter Freeze mode before entering Disable and Stop mode. */
+#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0)
+/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0)
+/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0)
+/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */
+#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0)
+
+/* CDOG module features */
+
+/* @brief SOC has no reset driver. */
+#define FSL_FEATURE_CDOG_HAS_NO_RESET (1)
+/* @brief CDOG Load default configurations during init function */
+#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0)
+
+/* CMC module features */
+
+/* @brief Has SRAM_DIS register */
+#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (0)
+/* @brief Has BSR register */
+#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (0)
+/* @brief Has RSTCNT register */
+#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (0)
+/* @brief Has BLR register */
+#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0)
+
+/* LPCMP module features */
+
+/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1)
+/* @brief Has IER RRF_IE bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1)
+/* @brief Has CSR RRF bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1)
+/* @brief Has Round Robin mode (related to existence of registers RRCR0). */
+#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1)
+/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */
+#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1)
+/* @brief Has CCR0 CMP_STOP_EN bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1)
+/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */
+#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1)
+
+/* CTIMER module features */
+
+/* @brief CTIMER has no capture channel. */
+#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0)
+/* @brief CTIMER has no capture 2 interrupt. */
+#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0)
+/* @brief CTIMER capture 3 interrupt. */
+#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
+/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */
+#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0)
+/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */
+#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
+/* @brief CTIMER Has register MSR */
+#define FSL_FEATURE_CTIMER_HAS_MSR (1)
+
+/* EDMA module features */
+
+/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8)
+/* @brief If 8 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
+/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
+/* @brief If 16 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1)
+/* @brief Has DMA_Error interrupt vector. */
+#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
+/* @brief If 64 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1)
+/* @brief whether has prot register */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0)
+/* @brief If 128 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1)
+/* @brief whether has MP channel mux */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0)
+/* @brief If 128 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1)
+/* @brief If channel clock controlled independently */
+#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1)
+/* @brief Has register CH_CSR. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1)
+/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */
+#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (8)
+/* @brief Has channel mux */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1)
+/* @brief Has no register bit fields MP_CSR[EBW]. */
+#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1)
+/* @brief Instance has channel mux */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1)
+/* @brief If dma has common clock gate */
+#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0)
+/* @brief Has register CH_SBR. */
+#define FSL_FEATURE_EDMA_HAS_SBR (1)
+/* @brief If dma channel IRQ support parameter */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0)
+/* @brief Has no register bit fields CH_SBR[ATTR]. */
+#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1)
+/* @brief NBYTES must be multiple of 8 when using scatter gather. */
+#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0)
+/* @brief Has register bit field CH_CSR[SWAP]. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0)
+/* @brief NBYTES must be multiple of 8 when using scatter gather. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0)
+/* @brief Instance has register bit field CH_CSR[SWAP]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0)
+/* @brief Has register bit fields MP_CSR[GMRC]. */
+#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1)
+/* @brief Has register bit field CH_SBR[INSTR]. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0)
+/* @brief Instance has register bit field CH_SBR[INSTR]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0)
+/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE  (0)
+/* @brief Instance has register CH_MATTR. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0)
+/* @brief Has register bit field CH_CSR[SIGNEXT]. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0)
+/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0)
+/* @brief Has register bit field TCD_CSR[BWC]. */
+#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1)
+/* @brief Instance has register bit field TCD_CSR[BWC]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1)
+/* @brief Has register bit fields TCD_CSR[TMC]. */
+#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0)
+/* @brief Instance has register bit fields TCD_CSR[TMC]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0)
+/* @brief Has no register bit fields CH_SBR[SEC]. */
+#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1)
+/* @brief edma5 has different tcd type. */
+#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0)
+
+/* EQDC module features */
+
+/* @brief If EQDC CTRL2 register has EMIP bit field. */
+#define FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD (1)
+
+/* PWM module features */
+
+/* @brief If (e)FlexPWM has module A channels (outputs). */
+#define FSL_FEATURE_PWM_HAS_CHANNELA (1)
+/* @brief If (e)FlexPWM has module B channels (outputs). */
+#define FSL_FEATURE_PWM_HAS_CHANNELB (1)
+/* @brief If (e)FlexPWM has module X channels (outputs). */
+#define FSL_FEATURE_PWM_HAS_CHANNELX (1)
+/* @brief If (e)FlexPWM has fractional feature. */
+#define FSL_FEATURE_PWM_HAS_FRACTIONAL (0)
+/* @brief If (e)FlexPWM has mux trigger source select bit field. */
+#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1)
+/* @brief Number of submodules in each (e)FlexPWM module. */
+#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4)
+/* @brief Number of fault channel in each (e)FlexPWM module. */
+#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1)
+/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */
+#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1)
+/* @brief If (e)FlexPWM has phase delay feature. */
+#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1)
+/* @brief If (e)FlexPWM has input filter capture feature. */
+#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1)
+/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */
+#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (0)
+/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */
+#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0)
+/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */
+#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1)
+/* @brief Is affected by errata with ID 51989. */
+#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0)
+
+/* FMU module features */
+
+/* @brief Is the flash module msf1? */
+#define FSL_FEATURE_FSL_FEATURE_FLASH_IS_MSF1 (1)
+/* @brief P-Flash block count. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
+/* @brief P-Flash block0 start address. */
+#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U)
+/* @brief P-Flash block0 size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U)
+/* @brief P-Flash sector size. */
+#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U)
+/* @brief P-Flash page size. */
+#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128)
+/* @brief P-Flash phrase size. */
+#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16)
+/* @brief Has IFR memory. */
+#define FSL_FEATURE_FLASH_HAS_IFR (1)
+/* @brief flash BLOCK0 IFR0 start address. */
+#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u)
+/* @brief flash BLOCK0 IFR1 start address. */
+#define FSL_FEATURE_FLASH_IFR1_START_ADDRESS (0x01100000U)
+/* @brief flash block IFR0 size. */
+#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U)
+/* @brief flash block IFR1 size. */
+#define FSL_FEATURE_FLASH_IFR1_SIZE (0x2000U)
+/* @brief IFR sector size. */
+#define FSL_FEATURE_FLASH_IFR_SECTOR_SIZE (0x2000U)
+/* @brief IFR page size. */
+#define FSL_FEATURE_FLASH_IFR_PAGE_SIZE (128)
+
+/* GLIKEY module features */
+
+/* @brief GLIKEY has 8 step FSM configuration */
+#define FSL_FEATURE_GLIKEY_HAS_EIGHT_STEPS (0)
+
+/* GPIO module features */
+
+/* @brief Has GPIO attribute checker register (GACR). */
+#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0)
+/* @brief Has GPIO version ID register (VERID). */
+#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1)
+/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */
+#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0)
+/* @brief Has GPIO port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1)
+/* @brief Has GPIO interrupt/DMA request/trigger output selection. */
+#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0)
+
+/* LPI2C module features */
+
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
+/* @brief Has dedicated interrupt for master and slave. */
+#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0)
+
+/* LPSPI module features */
+
+/* @brief Capacity (number of entries) of the transmit/receive FIFO. */
+#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Has CCR1 (related to existence of registers CCR1). */
+#define FSL_FEATURE_LPSPI_HAS_CCR1 (1)
+/* @brief Has no PCSCFG bit in CFGR1 register. */
+#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0)
+/* @brief Has no WIDTH bits in TCR register. */
+#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0)
+
+/* LPTMR module features */
+
+/* @brief Has shared interrupt handler with another LPTMR module. */
+#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+/* @brief Whether LPTMR counter is 32 bits width. */
+#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1)
+/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
+#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1)
+/* @brief Do not has prescaler clock source 0. */
+#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1)
+/* @brief Do not has prescaler clock source 1. */
+#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0)
+/* @brief Do not has prescaler clock source 2. */
+#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1)
+/* @brief Do not has prescaler clock source 3. */
+#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0)
+
+/* LPUART module features */
+
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_HAS_FIFO (1)
+/* @brief Has 32-bit register MODIR */
+#define FSL_FEATURE_LPUART_HAS_MODIR (1)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief If 10-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
+/* @brief If 7-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_LPUART_IS_SCI (1)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
+/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
+#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0)
+/* @brief Has separate RX and TX interrupts. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
+/* @brief Has LPAURT_PARAM. */
+#define FSL_FEATURE_LPUART_HAS_PARAM (1)
+/* @brief Has LPUART_VERID. */
+#define FSL_FEATURE_LPUART_HAS_VERID (1)
+/* @brief Has LPUART_GLOBAL. */
+#define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
+/* @brief Has LPUART_PINCFG. */
+#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
+/* @brief Belong to LPFLEXCOMM */
+#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0)
+/* @brief Has register MODEM Control. */
+#define FSL_FEATURE_LPUART_HAS_MCR (0)
+/* @brief Has register Half Duplex Control. */
+#define FSL_FEATURE_LPUART_HAS_HDCR (0)
+/* @brief Has register Timeout. */
+#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0)
+/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */
+#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4)
+/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */
+#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1)
+
+/* MAU module features */
+
+/* @brief Indirect operation is in low address. */
+#define FSL_FEATURE_MAU_INDIRECT_IS_LOW_ADDR  (1)
+
+/* TRDC module features */
+
+/* @brief Process master count. */
+#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2)
+/* @brief TRDC instance has PID configuration or not. */
+#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0)
+/* @brief TRDC instance has MBC. */
+#define FSL_FEATURE_TRDC_HAS_MBC (1)
+/* @brief TRDC instance has MRC. */
+#define FSL_FEATURE_TRDC_HAS_MRC (0)
+/* @brief TRDC instance has TRDC_CR. */
+#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0)
+/* @brief TRDC instance has MDA_Wx_y_DFMT. */
+#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0)
+/* @brief TRDC instance has TRDC_FDID. */
+#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0)
+/* @brief TRDC instance has TRDC_FLW_CTL. */
+#define FSL_FEATURE_TRDC_HAS_FLW (0)
+
+/* OPAMP module features */
+
+/* @brief Opamp has OPAMP_CTR OUTSW bit */
+#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (0)
+/* @brief Opamp has OPAMP_CTR ADCSW1 bit */
+#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (0)
+/* @brief Opamp has OPAMP_CTR ADCSW2 bit */
+#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (0)
+/* @brief Opamp has OPAMP_CTR BUFEN bit */
+#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (0)
+/* @brief Opamp has OPAMP_CTR INPSEL bit */
+#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (0)
+/* @brief Opamp has OPAMP_CTR TRIGMD bit */
+#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (0)
+/* @brief OPAMP support reference buffer */
+#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
+/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Do not has interrupt control (register ISFR). */
+#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1)
+/* @brief Has pull value (register bit field PCR[PV]). */
+#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1)
+/* @brief Has drive strength1 control (register bit PCR[DSE1]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1)
+/* @brief Has version ID register (register VERID). */
+#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1)
+/* @brief Has voltage range control (register bit CONFIG[RANGE]). */
+#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1)
+/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */
+#define FSL_FEATURE_PORT_SUPPORT_EFT (0)
+/* @brief Function 0 is GPIO. */
+#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
+/* @brief Defines width of PCR[MUX] field. */
+#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
+/* @brief Has independent interrupt control(register ICR). */
+#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0)
+/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
+#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
+/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */
+#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1)
+/* @brief Has Invert Input (register bit field PCR[INV]). */
+#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1)
+/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
+
+/* RTC module features */
+
+/* @brief Has wakeup pin. */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0)
+/* @brief Has wakeup pin selection (bit field CR[WPS]). */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0)
+/* @brief Has low power features (registers MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+/* @brief Has read/write access control (registers WAR and RAR). */
+#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
+/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_SECURITY (0)
+/* @brief Has RTC_CLKIN available. */
+#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
+/* @brief Has prescaler adjust for LPO. */
+#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1)
+/* @brief Has Clock Pin Enable field. */
+#define FSL_FEATURE_RTC_HAS_CPE (0)
+/* @brief Has Timer Seconds Interrupt Configuration field. */
+#define FSL_FEATURE_RTC_HAS_TSIC (1)
+/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
+#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0)
+/* @brief Has Tamper Interrupt Register (register TIR). */
+#define FSL_FEATURE_RTC_HAS_TIR (0)
+/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
+#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0)
+/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
+#define FSL_FEATURE_RTC_HAS_TIR_SIE (0)
+/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
+#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0)
+/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
+#define FSL_FEATURE_RTC_HAS_SR_TIDF (0)
+/* @brief Has Tamper Detect Register (register TDR). */
+#define FSL_FEATURE_RTC_HAS_TDR (0)
+/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
+#define FSL_FEATURE_RTC_HAS_TDR_TPF (0)
+/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
+#define FSL_FEATURE_RTC_HAS_TDR_STF (0)
+/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
+#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0)
+/* @brief Has Tamper Time Seconds Register (register TTSR). */
+#define FSL_FEATURE_RTC_HAS_TTSR (0)
+/* @brief Has Pin Configuration Register (register PCR). */
+#define FSL_FEATURE_RTC_HAS_PCR (0)
+/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */
+#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1)
+/* @brief Has no supervisor access bit (CR[SUP]). */
+#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1)
+/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */
+#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0)
+/* @brief Has clock output bit (CR[CLKO]). */
+#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0)
+
+/* SPC module features */
+
+/* @brief Has DCDC */
+#define FSL_FEATURE_MCX_SPC_HAS_DCDC (0)
+/* @brief Has SYS LDO */
+#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (0)
+/* @brief Has IOVDD_LVDF */
+#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (0)
+/* @brief Has COREVDD_HVDF */
+#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (0)
+/* @brief Has CORELDO_VDD_DS */
+#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1)
+/* @brief Has LPBUFF_EN */
+#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (0)
+/* @brief Has COREVDD_IVS_EN */
+#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (0)
+/* @brief Has SWITCH_STATE */
+#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0)
+/* @brief Has SRAMRETLDO */
+#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (1)
+/* @brief Has CFG register */
+#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0)
+/* @brief Has SRAMLDO_DPD_ON */
+#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (1)
+/* @brief Has CNTRL register */
+#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1)
+/* @brief Has DPDOWN_PULLDOWN_DISABLE */
+#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0)
+/* @brief Not have glitch detect */
+#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (0)
+/* @brief Has BLEED_EN */
+#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (0)
+/* @brief Has Power Request Status Flag */
+#define FSL_FEATURE_MCX_SPC_HAS_PD_STATUS_PWR_REQ_STATUS_BIT (0)
+
+/* SYSCON module features */
+
+/* @brief Flash page size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128)
+/* @brief Flash sector size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192)
+/* @brief Flash size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (253952)
+/* @brief Support ROMAPI */
+#define FSL_FEATURE_SYSCON_ROMAPI (1)
+/* @brief ROMAPI tree address */
+#define FSL_FEATURE_ROMAPI_BASE (0x03005FE0U)
+/* @brief ROMAPI support IFR function */
+#define FSL_FEATURE_ROMAPI_IFR (0)
+/* @brief Powerlib API is different with other series devices */
+#define FSL_FEATURE_POWERLIB_EXTEND (1)
+/* @brief No OSTIMER register in PMC */
+#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1)
+/* @brief Starter register discontinuous. */
+#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
+/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */
+#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (0)
+/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */
+#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (0)
+
+/* UTICK module features */
+
+/* @brief UTICK does not support power down configure. */
+#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
+
+/* VBAT module features */
+
+/* @brief Has STATUS register */
+#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (0)
+/* @brief Has TAMPER register */
+#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (0)
+/* @brief Has BANDGAP register */
+#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (0)
+/* @brief Has LDOCTL register */
+#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (0)
+/* @brief Has OSCCTL register */
+#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (0)
+/* @brief Has SWICTL register */
+#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (0)
+/* @brief Has CLKMON register */
+#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0)
+
+/* WWDT module features */
+
+/* @brief WWDT does not support oscillator lock. */
+#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0)
+/* @brief soc has reset. */
+#define FSL_FEATURE_WWDT_HAS_NO_RESET (1)
+/* @brief Has LPOSC as clock source. */
+#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0)
+/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */
+#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0)
+
+#endif /* _MCXA344_FEATURES_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/CMakeLists.txt
new file mode 100644
index 0000000000..bca941a9d2
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/CMakeLists.txt
@@ -0,0 +1,35 @@
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+mcux_add_cmakelists(${SdkRootDirPath}/devices/MCX/MCXA/MCXA153/drivers/romapi)
+
+if (CONFIG_MCUX_COMPONENT_driver.clock)
+    mcux_component_version(2.0.0)
+    mcux_add_source( SOURCES fsl_clock.c fsl_clock.h )
+    mcux_add_include( INCLUDES . )
+endif()
+
+if (CONFIG_MCUX_COMPONENT_driver.edma_soc)
+    mcux_component_version(2.0.0)
+    mcux_add_source( SOURCES fsl_edma_soc.c fsl_edma_soc.h )
+    mcux_add_include( INCLUDES . )
+endif()
+
+if (CONFIG_MCUX_COMPONENT_driver.inputmux_connections)
+    mcux_component_version(2.0.0)
+    mcux_add_source( SOURCES fsl_inputmux_connections.h )
+    mcux_add_include( INCLUDES . )
+endif()
+
+if (CONFIG_MCUX_COMPONENT_driver.reset)
+    mcux_component_version(2.4.0)
+    mcux_add_source( SOURCES fsl_reset.c fsl_reset.h )
+    mcux_add_include( INCLUDES . )
+endif()
+
+if (CONFIG_MCUX_COMPONENT_driver.trdc_soc)
+    mcux_component_version(2.0.0)
+    mcux_add_source( SOURCES fsl_trdc_soc.h )
+    mcux_add_include( INCLUDES . )
+endif()
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_clock.c
new file mode 100644
index 0000000000..bae45612ba
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_clock.c
@@ -0,0 +1,1285 @@
+/*
+ * Copyright 2023, NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.clock"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/** External clock rate on the CLKIN pin in Hz. If not used,
+    set this to 0. Otherwise, set it to the exact rate in Hz this pin is
+    being driven at. */
+volatile static uint32_t s_Ext_Clk_Freq = 16000000U;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/* Get FRO 12M Clk */
+static uint32_t CLOCK_GetFro12MFreq(void);
+/* Get LF FRO_DIV Clk */
+static uint32_t CLOCK_GetFroLfDivFreq(void);
+/* Get CLK 1M Clk */
+static uint32_t CLOCK_GetClk1MFreq(void);
+/* Get HF FRO Clk */
+static uint32_t CLOCK_GetFroHfFreq(void);
+/* Get HF FRO_DIV Clk */
+static uint32_t CLOCK_GetFroHfDivFreq(void);
+/* Get CLK 45M Clk */
+static uint32_t CLOCK_GetClk45MFreq(void);
+/* Get CLK 16K Clk */
+static uint32_t CLOCK_GetClk16KFreq(uint8_t id);
+/* Get EXT OSC Clk */
+static uint32_t CLOCK_GetExtClkFreq(void);
+/* Get Main_Clk */
+uint32_t CLOCK_GetMainClk(void);
+/* Get FRO_16K */
+static uint32_t CLOCK_GetFRO16KFreq(void);
+
+/* Check if DIV is halt */
+static inline bool CLOCK_IsDivHalt(uint32_t div_value)
+{
+    if (0U != (div_value & (1UL << 30U)))
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Clock Selection for IP */
+/**
+ * brief   Configure the clock selection muxes.
+ * param   connection  : Clock to be configured.
+ * return  Nothing
+ */
+void CLOCK_AttachClk(clock_attach_id_t connection)
+{
+    const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection);
+    const uint32_t clk_sel    = CLK_ATTACH_CLK_SEL(connection);
+
+    if (kNONE_to_NONE != connection)
+    {
+        CLOCK_SetClockSelect((clock_select_name_t)reg_offset, clk_sel);
+    }
+}
+
+/* Return the actual clock attach id */
+/**
+ * brief   Get the actual clock attach id.
+ * This fuction uses the offset in input attach id, then it reads the actual
+ * source value in the register and combine the offset to obtain an actual
+ * attach id.
+ * value.
+ */
+clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t connection)
+{
+    const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection);
+    uint32_t actual_sel       = 0U;
+    uint32_t clock_attach_id  = 0U;
+
+    if (kNONE_to_NONE == connection)
+    {
+        return kNONE_to_NONE;
+    }
+
+    actual_sel      = CLOCK_GetClockSelect((clock_select_name_t)reg_offset);
+    clock_attach_id = CLK_ATTACH_MUX(reg_offset, actual_sel);
+
+    return (clock_attach_id_t)clock_attach_id;
+}
+
+/* Set the clock selection value */
+void CLOCK_SetClockSelect(clock_select_name_t sel_name, uint32_t value)
+{
+    volatile uint32_t *pClkCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)sel_name);
+    assert(sel_name <= kCLOCK_SelMax);
+
+    if (sel_name == kCLOCK_SelSCGSCS)
+    {
+        SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value);
+        while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(value))
+        {
+        }
+    }
+    else
+    {
+        /* Unlock clock configuration */
+        SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK;
+
+        *pClkCtrl = value;
+
+        /* Freeze clock configuration */
+        SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK;
+    }
+}
+
+/* Get the clock selection value */
+uint32_t CLOCK_GetClockSelect(clock_select_name_t sel_name)
+{
+    volatile uint32_t *pClkCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)sel_name);
+    uint32_t actual_sel         = 0U;
+    assert(sel_name <= kCLOCK_SelMax);
+
+    if (sel_name == kCLOCK_SelSCGSCS)
+    {
+        actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT);
+    }
+    else
+    {
+        actual_sel = *pClkCtrl;
+    }
+
+    return actual_sel;
+}
+
+/* Set the clock divider value */
+void CLOCK_SetClockDiv(clock_div_name_t div_name, uint32_t value)
+{
+    volatile uint32_t *pDivCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)div_name);
+    assert(div_name <= kCLOCK_DivMax);
+
+    /* Unlock clock configuration */
+    SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK;
+
+    /* halt and reset clock dividers */
+    *pDivCtrl = 0x3UL << 29U;
+
+    if (value == 0U) /*!<  halt */
+    {
+        *pDivCtrl |= (1UL << 30U);
+    }
+    else
+    {
+        *pDivCtrl = (value - 1U);
+    }
+
+    /* Freeze clock configuration */
+    SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK;
+}
+
+/* Get the clock divider value */
+uint32_t CLOCK_GetClockDiv(clock_div_name_t div_name)
+{
+    volatile uint32_t *pDivCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)div_name);
+    assert(div_name <= kCLOCK_DivMax);
+
+    if (((*pDivCtrl) & (1UL << 30U)) != 0U)
+    {
+        return 0;
+    }
+    else
+    {
+        return ((*pDivCtrl & 0xFFU) + 1U);
+    }
+}
+
+/* Halt the clock divider value */
+void CLOCK_HaltClockDiv(clock_div_name_t div_name)
+{
+    volatile uint32_t *pDivCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)div_name);
+    assert(div_name <= kCLOCK_DivMax);
+
+    /* Unlock clock configuration */
+    SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK;
+
+    *pDivCtrl |= (1UL << 30U);
+
+    /* Freeze clock configuration */
+    SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK;
+}
+
+/* Initialize the FROHF to given frequency (45,60,90,180) */
+status_t CLOCK_SetupFROHFClocking(uint32_t iFreq)
+{
+    uint8_t freq_select = 0x0U;
+    switch (iFreq)
+    {
+        case 45000000U:
+            freq_select = 1U;
+            break;
+        case 60000000U:
+            freq_select = 3U;
+            break;
+        case 90000000U:
+            freq_select = 5U;
+            break;
+        case 180000000U:
+            freq_select = 7U;
+            break;
+        default:
+            freq_select = 0xFU;
+            break;
+    }
+
+    if (0xFU == freq_select)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Set FIRC frequency */
+    SCG0->FIRCCFG = SCG_FIRCCFG_FREQ_SEL(freq_select);
+
+    /* Unlock FIRCCSR */
+    SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK;
+
+    /* Enable CLK 45 MHz clock for peripheral use */
+    SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK;
+    /* Enable FIRC HF clock for peripheral use */
+    SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK;
+    /* Enable FIRC */
+    SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK;
+
+    /* Lock FIRCCSR */
+    SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK;
+
+    /* Wait for FIRC clock to be valid. */
+    while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U)
+    {
+    }
+
+    return kStatus_Success;
+}
+
+/* Initialize the FRO12M. */
+status_t CLOCK_SetupFRO12MClocking(void)
+{
+    /* Unlock SIRCCSR */
+    SCG0->SIRCCSR &= ~SCG_SIRCCSR_LK_MASK;
+
+    /* Enable FRO12M clock for peripheral use */
+    SCG0->SIRCCSR |= SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK;
+
+    /* Lock SIRCCSR */
+    SCG0->SIRCCSR |= SCG_SIRCCSR_LK_MASK;
+
+    /* Wait for SIRC clock to be valid. */
+    while ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) == 0U)
+    {
+    }
+
+    /* Release FROLFDIV */
+    SYSCON->FROLFDIV &= ~SYSCON_FROLFDIV_HALT_MASK;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief   Initialize the FRO16K.
+ * This function turns on FRO16K.
+ * return  returns success or fail status.
+ */
+status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask)
+{
+    /* Enable clk_16k */
+    VBAT0->FROCTLA |= VBAT_FROCTLA_FRO_EN_MASK;
+    VBAT0->FROLCKA |= VBAT_FROLCKA_LOCK_MASK;
+
+    /* Enable clk_16k output clock to corresponding modules according to the
+     * enable_mask. */
+    VBAT0->FROCLKE |= VBAT_FROCLKE_CLKE(((uint32_t)clk_16k_enable_mask));
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief   Initialize the external osc clock to given frequency.
+ * param   iFreq   : Desired frequency (must be equal to exact rate in Hz)
+ * return  returns success or fail status.
+ */
+status_t CLOCK_SetupExtClocking(uint32_t iFreq)
+{
+    uint8_t range = 0U;
+
+    if ((iFreq >= 8000000U) && (iFreq < 16000000U))
+    {
+        range = 0U;
+    }
+    else if ((iFreq >= 16000000U) && (iFreq < 25000000U))
+    {
+        range = 1U;
+    }
+    else if ((iFreq >= 25000000U) && (iFreq < 40000000U))
+    {
+        range = 2U;
+    }
+    else if ((iFreq >= 40000000U) && (iFreq <= 50000000U))
+    {
+        range = 3U;
+    }
+    else
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* If configure register is locked, return error. */
+    if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U)
+    {
+        return kStatus_ReadOnly;
+    }
+
+    /* De-initializes the SCG SOSC */
+    SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;
+
+    /* Enable LDO */
+    SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
+
+    /* Select SOSC source(internal crystal oscillator) and Configure SOSC range */
+    SCG0->SOSCCFG = SCG_SOSCCFG_EREFS_MASK | SCG_SOSCCFG_RANGE(range);
+
+    /* Unlock SOSCCSR */
+    SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK;
+
+    /* Enable SOSC clock monitor and Enable SOSC */
+    SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK);
+
+    /* Wait for SOSC clock to be valid. */
+    while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U)
+    {
+    }
+
+    s_Ext_Clk_Freq = iFreq;
+
+    return kStatus_Success;
+}
+
+/*!
+ * @brief   Initialize the external reference clock to given frequency.
+ * param   iFreq   : Desired frequency (must be equal to exact rate in Hz)
+ * return  returns success or fail status.
+ */
+status_t CLOCK_SetupExtRefClocking(uint32_t iFreq)
+{
+    if (iFreq > 50000000U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* If configure register is locked, return error. */
+    if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U)
+    {
+        return kStatus_ReadOnly;
+    }
+
+    /* De-initializes the SCG SOSC */
+    SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;
+
+    /* Enable LDO */
+    SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
+
+    /* Select SOSC source (external reference clock)*/
+    SCG0->SOSCCFG &= ~SCG_SOSCCFG_EREFS_MASK;
+
+    /* Unlock SOSCCSR */
+    SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK;
+
+    /* Enable SOSC clock monitor and Enable SOSC */
+    SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK);
+
+    /* Wait for SOSC clock to be valid. */
+    while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U)
+    {
+    }
+
+    s_Ext_Clk_Freq = iFreq;
+
+    return kStatus_Success;
+}
+
+/* Get IP Clk */
+/*! brief  Return Frequency of selected clock
+ *  return Frequency of selected clock
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName)
+{
+    uint32_t freq = 0U;
+
+    switch (clockName)
+    {
+        case kCLOCK_MainClk: /* MAIN_CLK */
+            freq = CLOCK_GetMainClk();
+            break;
+        case kCLOCK_CoreSysClk: /* Core/system clock(CPU_CLK) */
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+        case kCLOCK_SYSTEM_CLK: /* AHB clock */
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+        case kCLOCK_BusClk: /* Bus clock */
+            freq = (CLOCK_GetCoreSysClkFreq() >> 1);
+            break;
+        case kCLOCK_ExtClk: /* External Clock */
+            freq = CLOCK_GetExtClkFreq();
+            break;
+        case kCLOCK_FroHf: /* FROHF */
+            freq = CLOCK_GetFroHfFreq();
+            break;
+        case kCLOCK_FroHfDiv: /* Divided by FROHF */
+            freq = CLOCK_GetFroHfDivFreq();
+            break;
+        case kCLOCK_Clk45M: /* CLK_45M */
+            freq = CLOCK_GetClk45MFreq();
+            break;
+        case kCLOCK_Fro12M: /* FRO12M */
+            freq = CLOCK_GetFro12MFreq();
+            break;
+        case kCLOCK_Fro12MDiv: /* FRO_LF_DIV */
+            freq = CLOCK_GetFro12MFreq() / ((SYSCON->FROLFDIV & 0xfU) + 1U);
+            break;
+        case kCLOCK_Clk1M: /* CLK1M */
+            freq = CLOCK_GetClk1MFreq();
+            break;
+        case kCLOCK_Fro16K: /* FRO16K */
+            freq = CLOCK_GetFRO16KFreq();
+            break;
+        case kCLOCK_Clk16K0: /* CLK16K[0] */
+            freq = CLOCK_GetClk16KFreq(0);
+            break;
+        case kCLOCK_Clk16K1: /* CLK16K[1] */
+            freq = CLOCK_GetClk16KFreq(1);
+            break;
+        case kCLOCK_SLOW_CLK: /* SYSTEM_CLK divided by 6 */
+            freq = (CLOCK_GetCoreSysClkFreq() / 6);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/* Get FRO 12M Clk */
+/*! brief  Return Frequency of FRO 12MHz
+ *  return Frequency of FRO 12MHz
+ */
+static uint32_t CLOCK_GetFro12MFreq(void)
+{
+    return ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK) != 0U) ? 12000000U : 0U;
+}
+
+/* Get CLK 1M Clk */
+/*! brief  Return Frequency of CLK 1MHz
+ *  return Frequency of CLK 1MHz
+ */
+static uint32_t CLOCK_GetClk1MFreq(void)
+{
+    return 1000000U;
+}
+
+/* Get HF FRO Clk */
+/*! brief  Return Frequency of High-Freq output of FRO
+ *  return Frequency of High-Freq output of FRO
+ */
+static uint32_t CLOCK_GetFroHfFreq(void)
+{
+    uint32_t freq;
+
+    if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) ||
+        ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT) == 0U))
+    {
+        freq = 0U;
+    }
+
+    switch ((SCG0->FIRCCFG & SCG_FIRCCFG_FREQ_SEL_MASK) >> SCG_FIRCCFG_FREQ_SEL_SHIFT)
+    {
+        case 1U:
+            freq = 45000000U;
+            break;
+        case 3U:
+            freq = 60000000U;
+            break;
+        case 5U:
+            freq = 90000000U;
+            break;
+        case 7U:
+            freq = 180000000U;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/* Get HF FRO DIV Clk */
+/*! brief  Return Frequency of High-Freq output of FRO
+ *  return Frequency of High-Freq output of FRO
+ */
+static uint32_t CLOCK_GetFroHfDivFreq(void)
+{
+    return CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & SYSCON_FROHFDIV_DIV_MASK) + 1U);
+}
+
+/* Get LF FRO DIV Clk */
+/*! brief  Return Frequency of High-Freq output of FRO
+ *  return Frequency of High-Freq output of FRO
+ */
+static uint32_t CLOCK_GetFroLfDivFreq(void)
+{
+    return CLOCK_GetFro12MFreq() / ((SYSCON->FROLFDIV & SYSCON_FROLFDIV_DIV_MASK) + 1U);
+}
+
+/* Get CLK_45M frequency */
+/*! brief  Return Frequency of CLK 45MHz
+ *  return Frequency of CLK 45MHz
+ */
+static uint32_t CLOCK_GetClk45MFreq(void)
+{
+    if ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) == 0U)
+    {
+        return 0U;
+    }
+    else
+    {
+        return 45000000U;
+    }
+}
+
+/*! brief  Return Frequency of FRO16K
+ *  return Frequency of FRO_16K
+ */
+static uint32_t CLOCK_GetFRO16KFreq(void)
+{
+    return ((VBAT0->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) != 0U) ? 16000U : 0U;
+}
+/* Get CLK 16K Clk */
+/*! brief  Return Frequency of CLK 16KHz
+ *  return Frequency of CLK 16KHz
+ */
+static uint32_t CLOCK_GetClk16KFreq(uint8_t id)
+{
+    return (((VBAT0->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) != 0U) &&
+            ((VBAT0->FROCLKE & VBAT_FROCLKE_CLKE((((uint32_t)id) << 1U))) != 0U)) ?
+               16000U :
+               0U;
+}
+
+/* Get EXT OSC Clk */
+/*! brief  Return Frequency of External Clock
+ *  return Frequency of External Clock. If no external clock is used returns 0.
+ */
+static uint32_t CLOCK_GetExtClkFreq(void)
+{
+    return ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) != 0U) ? s_Ext_Clk_Freq : 0U;
+}
+
+/* Get MAIN Clk */
+/*! brief  Return Frequency of Core System
+ *  return Frequency of Core System
+ */
+uint32_t CLOCK_GetMainClk(void)
+{
+    uint32_t freq = 0U;
+
+    switch ((SCG0->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT)
+    {
+        case 1U:
+            freq = CLOCK_GetExtClkFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetFro12MFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+        case 4U:
+            freq = CLOCK_GetClk16KFreq(1);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*! brief  Return Frequency of core
+ *  return Frequency of the core
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void)
+{
+    return CLOCK_GetMainClk() / ((SYSCON->AHBCLKDIV & SYSCON_AHBCLKDIV_DIV_MASK) + 1U);
+}
+
+/* Get CTimer Clk */
+/*! brief  Return Frequency of CTimer functional Clock
+ *  return Frequency of CTimer functional Clock
+ */
+uint32_t CLOCK_GetCTimerClkFreq(uint32_t id)
+{
+    uint32_t freq   = 0U;
+    uint32_t clksel = 0U;
+    uint32_t clkdiv = 0U;
+
+    switch (id)
+    {
+        case 0U:
+            clksel = MRCC0->MRCC_CTIMER0_CLKSEL;
+            clkdiv = MRCC0->MRCC_CTIMER0_CLKDIV;
+            break;
+        case 1U:
+            clksel = MRCC0->MRCC_CTIMER1_CLKSEL;
+            clkdiv = MRCC0->MRCC_CTIMER1_CLKDIV;
+            break;
+        case 2U:
+            clksel = MRCC0->MRCC_CTIMER2_CLKSEL;
+            clkdiv = MRCC0->MRCC_CTIMER2_CLKDIV;
+            break;
+        default:
+            clksel = MRCC0->MRCC_CTIMER0_CLKSEL;
+            clkdiv = MRCC0->MRCC_CTIMER0_CLKDIV;
+            break;
+    }
+
+    if (true == CLOCK_IsDivHalt(clkdiv))
+    {
+        return 0;
+    }
+
+    switch (clksel)
+    {
+        case 0U:
+            freq = CLOCK_GetFroLfDivFreq();
+            break;
+        case 1U:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetExtClkFreq();
+            break;
+        case 4U:
+            freq = CLOCK_GetClk16KFreq(1);
+            break;
+        case 5U:
+            freq = CLOCK_GetClk1MFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((clkdiv & 0xFFU) + 1U);
+}
+
+/* Get LPI2C Clk */
+/*! brief  Return Frequency of LPI2C functional Clock
+ *  return Frequency of LPI2C functional Clock
+ */
+uint32_t CLOCK_GetLpi2cClkFreq(uint32_t id)
+{
+    uint32_t freq = 0U;
+
+    uint32_t clksel = 0U;
+    uint32_t clkdiv = 0U;
+
+    switch (id)
+    {
+        case 0U:
+            clksel = MRCC0->MRCC_LPI2C0_CLKSEL;
+            clkdiv = MRCC0->MRCC_LPI2C0_CLKDIV;
+            break;
+        case 1U:
+            clksel = MRCC0->MRCC_LPI2C1_CLKSEL;
+            clkdiv = MRCC0->MRCC_LPI2C1_CLKDIV;
+            break;
+        default:
+            clksel = MRCC0->MRCC_LPI2C0_CLKSEL;
+            clkdiv = MRCC0->MRCC_LPI2C0_CLKDIV;
+            break;
+    }
+
+    if (true == CLOCK_IsDivHalt(clkdiv))
+    {
+        return 0;
+    }
+
+    switch (clksel)
+    {
+        case 0U:
+            freq = CLOCK_GetFroLfDivFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetFroHfDivFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetExtClkFreq();
+            break;
+        case 5U:
+            freq = CLOCK_GetClk1MFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((clkdiv & 0xFFU) + 1U);
+}
+
+/*! brief  Return Frequency of LPSPI Clock
+ *  return Frequency of LPSPI Clock
+ */
+uint32_t CLOCK_GetLpspiClkFreq(uint32_t id)
+{
+    uint32_t freq   = 0U;
+    uint32_t clksel = (0U == id) ? (MRCC0->MRCC_LPSPI0_CLKSEL) : (MRCC0->MRCC_LPSPI1_CLKSEL);
+    uint32_t clkdiv = (0U == id) ? (MRCC0->MRCC_LPSPI0_CLKDIV) : (MRCC0->MRCC_LPSPI1_CLKDIV);
+
+    if (true == CLOCK_IsDivHalt(clkdiv))
+    {
+        return 0;
+    }
+
+    switch (clksel)
+    {
+        case 0U:
+            freq = CLOCK_GetFroLfDivFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetFroHfDivFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetExtClkFreq();
+            break;
+        case 5U:
+            freq = CLOCK_GetClk1MFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((clkdiv & 0xFFU) + 1U);
+}
+
+/*! brief  Return Frequency of LPUART Clock
+ *  return Frequency of LPUART Clock
+ */
+uint32_t CLOCK_GetLpuartClkFreq(uint32_t id)
+{
+    uint32_t freq   = 0U;
+    uint32_t clksel = 0U;
+    uint32_t clkdiv = 0U;
+
+    switch (id)
+    {
+        case 0U:
+            clksel = MRCC0->MRCC_LPUART0_CLKSEL;
+            clkdiv = MRCC0->MRCC_LPUART0_CLKDIV;
+            break;
+        case 1U:
+            clksel = MRCC0->MRCC_LPUART1_CLKSEL;
+            clkdiv = MRCC0->MRCC_LPUART1_CLKDIV;
+            break;
+        case 2U:
+            clksel = MRCC0->MRCC_LPUART2_CLKSEL;
+            clkdiv = MRCC0->MRCC_LPUART2_CLKDIV;
+            break;
+        case 3U:
+            clksel = MRCC0->MRCC_LPUART3_CLKSEL;
+            clkdiv = MRCC0->MRCC_LPUART3_CLKDIV;
+            break;
+        default:
+            clksel = MRCC0->MRCC_LPUART0_CLKSEL;
+            clkdiv = MRCC0->MRCC_LPUART0_CLKDIV;
+            break;
+    }
+
+    if (true == CLOCK_IsDivHalt(clkdiv))
+    {
+        return 0;
+    }
+
+    switch (clksel)
+    {
+        case 0U:
+            freq = CLOCK_GetFroLfDivFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetFroHfDivFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetExtClkFreq();
+            break;
+        case 4U:
+            freq = CLOCK_GetClk16KFreq(1);
+            break;
+        case 5U:
+            freq = CLOCK_GetClk1MFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((clkdiv & 0xFFU) + 1U);
+}
+
+/*! brief  Return Frequency of LPTMR Clock
+ *  return Frequency of LPTMR Clock
+ */
+uint32_t CLOCK_GetLptmrClkFreq(void)
+{
+    uint32_t freq   = 0U;
+    uint32_t clksel = (MRCC0->MRCC_LPTMR0_CLKSEL);
+    uint32_t clkdiv = (MRCC0->MRCC_LPTMR0_CLKDIV);
+
+    if (true == CLOCK_IsDivHalt(clkdiv))
+    {
+        return 0;
+    }
+
+    switch (clksel)
+    {
+        case 0U:
+            freq = CLOCK_GetFroLfDivFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetFroHfDivFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetExtClkFreq();
+            break;
+        case 5U:
+            freq = CLOCK_GetClk1MFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((clkdiv & 0xFFU) + 1U);
+}
+
+/*! brief  Return Frequency of OSTIMER
+ *  return Frequency of OSTIMER Clock
+ */
+uint32_t CLOCK_GetOstimerClkFreq(void)
+{
+    uint32_t freq   = 0U;
+    uint32_t clksel = (MRCC0->MRCC_OSTIMER0_CLKSEL);
+
+    switch (clksel)
+    {
+        case 0U:
+            freq = CLOCK_GetClk16KFreq(1);
+            break;
+        case 2U:
+            freq = CLOCK_GetClk1MFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*! brief  Return Frequency of Adc Clock
+ *  return Frequency of Adc.
+ */
+uint32_t CLOCK_GetAdcClkFreq(uint32_t id)
+{
+    uint32_t freq = 0U;
+
+    uint32_t clksel = MRCC0->MRCC_ADC_CLKSEL;
+    uint32_t clkdiv = MRCC0->MRCC_ADC_CLKDIV;
+
+    if (true == CLOCK_IsDivHalt(clkdiv))
+    {
+        return 0;
+    }
+
+    switch (clksel)
+    {
+        case 0U:
+            freq = CLOCK_GetFroLfDivFreq();
+            break;
+        case 1U:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetExtClkFreq();
+            break;
+        case 5U:
+            freq = CLOCK_GetClk1MFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((clkdiv & 0xFFU) + 1U);
+}
+
+/*! brief  Return Frequency of CMP Function Clock
+ *  return Frequency of CMP Function.
+ */
+uint32_t CLOCK_GetCmpFClkFreq(uint32_t id)
+{
+    uint32_t freq   = 0U;
+    uint32_t clksel = 0U;
+    uint32_t clkdiv = 0U;
+
+    switch (id)
+    {
+        case 0U:
+            clksel = MRCC0->MRCC_CMP0_RR_CLKSEL;
+            clkdiv = MRCC0->MRCC_CMP0_FUNC_CLKDIV;
+            break;
+        case 1U:
+            clksel = MRCC0->MRCC_CMP1_RR_CLKSEL;
+            clkdiv = MRCC0->MRCC_CMP1_FUNC_CLKDIV;
+            break;
+        case 2U:
+            clksel = MRCC0->MRCC_CMP2_RR_CLKSEL;
+            clkdiv = MRCC0->MRCC_CMP2_FUNC_CLKDIV;
+            break;
+        default:
+            clksel = MRCC0->MRCC_CMP0_RR_CLKSEL;
+            clkdiv = MRCC0->MRCC_CMP0_FUNC_CLKDIV;
+            break;
+    }
+
+    if (true == CLOCK_IsDivHalt(clkdiv))
+    {
+        return 0;
+    }
+
+    switch (clksel)
+    {
+        case 0U:
+            freq = CLOCK_GetFroLfDivFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetFroHfDivFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetExtClkFreq();
+            break;
+        case 5U:
+            freq = CLOCK_GetClk1MFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((clkdiv & 0xFFU) + 1U);
+}
+
+/*! brief  Return Frequency of CMP Round Robin Clock
+ *  return Frequency of CMP Round Robin.
+ */
+uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id)
+{
+    uint32_t freq   = 0U;
+    uint32_t clksel = 0U;
+    uint32_t clkdiv = 0U;
+
+    switch (id)
+    {
+        case 0U:
+            clksel = MRCC0->MRCC_CMP0_RR_CLKSEL;
+            clkdiv = MRCC0->MRCC_CMP0_RR_CLKDIV;
+            break;
+        case 1U:
+            clksel = MRCC0->MRCC_CMP1_RR_CLKSEL;
+            clkdiv = MRCC0->MRCC_CMP1_RR_CLKDIV;
+            break;
+        case 2U:
+            clksel = MRCC0->MRCC_CMP2_RR_CLKSEL;
+            clkdiv = MRCC0->MRCC_CMP2_RR_CLKDIV;
+            break;
+        default:
+            clksel = MRCC0->MRCC_CMP0_RR_CLKSEL;
+            clkdiv = MRCC0->MRCC_CMP0_RR_CLKDIV;
+            break;
+    }
+
+    if (true == CLOCK_IsDivHalt(clkdiv))
+    {
+        return 0;
+    }
+
+    switch (clksel)
+    {
+        case 0U:
+            freq = CLOCK_GetFroLfDivFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetFroHfDivFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetExtClkFreq();
+            break;
+        case 5U:
+            freq = CLOCK_GetClk1MFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((clkdiv & 0xFFU) + 1U);
+}
+
+/*! brief  Return Frequency of Trace Clock
+ *  return Frequency of Trace.
+ */
+uint32_t CLOCK_GetTraceClkFreq(void)
+{
+    uint32_t freq   = 0U;
+    uint32_t clksel = (MRCC0->MRCC_DBG_TRACE_CLKSEL);
+    uint32_t clkdiv = (MRCC0->MRCC_DBG_TRACE_CLKDIV);
+
+    if (true == CLOCK_IsDivHalt(clkdiv))
+    {
+        return 0;
+    }
+
+    switch (clksel)
+    {
+        case 0U:
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+        case 1U:
+            freq = CLOCK_GetClk1MFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetClk16KFreq(1);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((clkdiv & 0xFFU) + 1U);
+}
+
+/*! brief  Return Frequency of CLKOUT Clock
+ *  return Frequency of CLKOUT.
+ */
+uint32_t CLOCK_GetClkoutClkFreq(void)
+{
+    uint32_t freq   = 0U;
+    uint32_t clksel = (MRCC0->MRCC_CLKOUT_CLKSEL);
+    uint32_t clkdiv = (MRCC0->MRCC_CLKOUT_CLKDIV);
+
+    if (true == CLOCK_IsDivHalt(clkdiv))
+    {
+        return 0;
+    }
+
+    switch (clksel)
+    {
+        case 0U:
+            freq = CLOCK_GetFro12MFreq();
+            break;
+        case 1U:
+            freq = CLOCK_GetFroHfDivFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetExtClkFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetClk16KFreq(1);
+            break;
+        case 6U:
+            freq = CLOCK_GetFreq(kCLOCK_SLOW_CLK);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((clkdiv & 0xFFU) + 1U);
+}
+
+/*! brief  Return Frequency of WWDT Clock
+ *  return Frequency of WWDT.
+ */
+uint32_t CLOCK_GetWwdtClkFreq(void)
+{
+    uint32_t freq   = 0U;
+    uint32_t clkdiv = (MRCC0->MRCC_WWDT0_CLKDIV);
+
+    if (true == CLOCK_IsDivHalt(clkdiv))
+    {
+        return 0;
+    }
+
+    freq = CLOCK_GetClk1MFreq();
+
+    return freq / ((clkdiv & 0xFFU) + 1U);
+}
+
+/*! brief  Return Frequency of FlexCAN FCLK
+ *  return Frequency of FlexCAN FCLK.
+ */
+uint32_t CLOCK_GetFlexcanClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    uint32_t clksel = MRCC0->MRCC_FLEXCAN0_CLKSEL;
+    uint32_t clkdiv = MRCC0->MRCC_FLEXCAN0_CLKDIV;
+
+    if (true == CLOCK_IsDivHalt(clkdiv))
+    {
+        return 0;
+    }
+
+    switch (clksel)
+    {
+        case 1U:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+        case 2U:
+            freq = CLOCK_GetFroHfDivFreq();
+            break;
+        case 3U:
+            freq = CLOCK_GetExtClkFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq / ((clkdiv & 0xFFU) + 1U);
+}
+
+/**
+ * @brief   Setup FRO 12M trim.
+ * @param   config   : FRO 12M trim value
+ * @return  returns success or fail status.
+ */
+status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config)
+{
+    SCG0->SIRCTCFG = SCG_SIRCTCFG_TRIMDIV(config.trimDiv) | SCG_SIRCTCFG_TRIMSRC(config.trimSrc);
+
+    if (kSCG_SircTrimNonUpdate == config.trimMode)
+    {
+        SCG0->SIRCSTAT = SCG_SIRCSTAT_CCOTRIM(config.cltrim);
+        SCG0->SIRCSTAT = SCG_SIRCSTAT_CCOTRIM(config.ccotrim);
+    }
+
+    /* Set trim mode. */
+    SCG0->SIRCCSR =
+        (SCG0->SIRCCSR & ~(SCG_SIRCCSR_SIRCTREN_MASK | SCG_SIRCCSR_SIRCTRUP_MASK)) | (uint32_t)config.trimMode;
+
+    if ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) == 0U)
+    {
+        return (status_t)kStatus_Fail;
+    }
+
+    if ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCERR_MASK) == SCG_SIRCCSR_SIRCERR_MASK)
+    {
+        return (status_t)kStatus_Fail;
+    }
+
+    if ((SCG0->SIRCCSR & SCG_SIRCCSR_TRIM_LOCK_MASK) == 0U)
+    {
+        return (status_t)kStatus_Fail;
+    }
+
+    return (status_t)kStatus_Success;
+}
+
+/*!
+ * @brief Sets the system OSC monitor mode.
+ *
+ * This function sets the system OSC monitor mode. The mode can be disabled,
+ * it can generate an interrupt when the error is disabled, or reset when the
+ * error is detected.
+ *
+ * @param mode Monitor mode to set.
+ */
+void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode)
+{
+    uint32_t reg = SCG0->SOSCCSR;
+
+    reg &= ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK);
+
+    reg |= (uint32_t)mode;
+
+    SCG0->SOSCCSR = reg;
+}
+
+/*!
+ * @brief   Set the additional number of wait-states added to account for the
+ * ratio of system clock period to flash access time during full speed power
+ * mode.
+ * @param   system_freq_hz  : Input frequency
+ * @param   mode            : Active run mode (voltage level).
+ * @return  success or fail status
+ */
+status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode)
+{
+    uint32_t num_wait_states_added = 3UL; /* Default 3 additional wait states */
+    switch ((uint32_t)mode)
+    {
+        case (uint32_t)kMD_Mode:
+        {
+            if (system_freq_hz > 45000000U)
+            {
+                return kStatus_Fail;
+            }
+            else if (system_freq_hz > 22500000U)
+            {
+                num_wait_states_added = 1U;
+            }
+            else
+            {
+                num_wait_states_added = 0U;
+            }
+            break;
+        }
+        case (uint32_t)kOD_Mode:
+        {
+            if (system_freq_hz > 180000000U)
+            {
+                return kStatus_Fail;
+            }
+            else if (system_freq_hz > 90000000U)
+            {
+                num_wait_states_added = 4U;
+            }
+            else if (system_freq_hz > 60000000U)
+            {
+                num_wait_states_added = 2U;
+            }
+            else if (system_freq_hz > 36000000U)
+            {
+                num_wait_states_added = 1U;
+            }
+            else
+            {
+                num_wait_states_added = 0U;
+            }
+            break;
+        }
+        default:
+            num_wait_states_added = 0U;
+            break;
+    }
+
+    /* additional wait-states are added */
+    FMU0->FCTRL = (FMU0->FCTRL & ~FMU_FCTRL_RWSC_MASK) | FMU_FCTRL_RWSC(num_wait_states_added);
+
+    return kStatus_Success;
+}
\ No newline at end of file
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_clock.h
new file mode 100644
index 0000000000..a472032e58
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_clock.h
@@ -0,0 +1,790 @@
+/*
+ * Copyright 2023, NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_CLOCK_H_
+#define _FSL_CLOCK_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup clock */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CLOCK driver version 2.0.0. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief Configure whether driver controls clock
+ *
+ * When set to 0, peripheral drivers will enable clock in initialize function
+ * and disable clock in de-initialize function. When set to 1, peripheral
+ * driver will not control the clock, application could control the clock out of
+ * the driver.
+ *
+ * @note All drivers share this feature switcher. If it is set to 1, application
+ * should handle clock enable and disable for all drivers.
+ */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
+#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0U
+#endif
+
+/* Definition for delay API in clock driver, users can redefine it to the real
+ * application. */
+#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
+#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (180000000U)
+#endif
+
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+/*------------------------------------------------------------------------------
+ clock_ip_name_t definition:
+------------------------------------------------------------------------------*/
+#define CLK_GATE_REG_OFFSET(value) (((uint32_t)(value)) >> 16U)
+#define CLK_GATE_BIT_SHIFT(value)  (((uint32_t)(value)) & 0x0000FFFFU)
+
+#define REG_PWM0SUBCTL (250U)
+#define REG_PWM1SUBCTL (240U)
+
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+typedef enum _clock_ip_name
+{
+    kCLOCK_InputMux      = ((0x00U << 16U) | (0U)),          /*!< Clock gate name: INPUTMUX0 */
+    kCLOCK_GateINPUTMUX0 = ((0x00U << 16U) | (0U)),          /*!< Clock gate name: INPUTMUX0 */
+    kCLOCK_GateCTIMER0   = ((0x00U << 16U) | (2U)),          /*!< Clock gate name: CTIMER0 */
+    kCLOCK_GateCTIMER1   = ((0x00U << 16U) | (3U)),          /*!< Clock gate name: CTIMER1 */
+    kCLOCK_GateCTIMER2   = ((0x00U << 16U) | (4U)),          /*!< Clock gate name: CTIMER2 */
+    kCLOCK_GateFREQME    = ((0x00U << 16U) | (7U)),          /*!< Clock gate name: FREQME  */
+    kCLOCK_GateUTICK0    = ((0x00U << 16U) | (8U)),          /*!< Clock gate name: UTICK0  */
+    kCLOCK_GateWWDT0     = ((0x00U << 16U) | (9U)),          /*!< Clock gate name: WWDT0     */
+    kCLOCK_Smartdma      = ((0x00U << 16U) | (10U)),         /*!< Clock gate name: SMARTDMA0 */
+    kCLOCK_GateDMA0      = ((0x00U << 16U) | (11U)),         /*!< Clock gate name: DMA0      */
+    kCLOCK_GateAOI0      = ((0x00U << 16U) | (12U)),         /*!< Clock gate name: AOI0      */
+    kCLOCK_GateCRC0      = ((0x00U << 16U) | (13U)),         /*!< Clock gate name: CRC0      */
+    kCLOCK_Crc0          = ((0x00U << 16U) | (13U)),         /*!< Clock gate name: CRC0      */
+    kCLOCK_GateEIM0      = ((0x00U << 16U) | (14U)),         /*!< Clock gate name: EIM0      */
+    kCLOCK_GateERM0      = ((0x00U << 16U) | (15U)),         /*!< Clock gate name: ERM0      */
+    kCLOCK_GateFMC       = ((0x00U << 16U) | (16U)),         /*!< Clock gate name: FMC       */
+    kCLOCK_GateAOI1      = ((0x00U << 16U) | (17U)),         /*!< Clock gate name: AOI1      */
+    kCLOCK_GateLPI2C0    = ((0x00U << 16U) | (19U)),         /*!< Clock gate name: LPI2C0 */
+    kCLOCK_GateLPI2C1    = ((0x00U << 16U) | (20U)),         /*!< Clock gate name: LPI2C1 */
+    kCLOCK_GateLPSPI0    = ((0x00U << 16U) | (21U)),         /*!< Clock gate name: LPSPI0 */
+    kCLOCK_GateLPSPI1    = ((0x00U << 16U) | (22U)),         /*!< Clock gate name: LPSPI1 */
+    kCLOCK_GateLPUART0   = ((0x00U << 16U) | (23U)),         /*!< Clock gate name: LPUART0   */
+    kCLOCK_GateLPUART1   = ((0x00U << 16U) | (24U)),         /*!< Clock gate name: LPUART1   */
+    kCLOCK_GateLPUART2   = ((0x00U << 16U) | (25U)),         /*!< Clock gate name: LPUART2   */
+    kCLOCK_GateLPUART3   = ((0x00U << 16U) | (26U)),         /*!< Clock gate name: LPUART3   */
+    kCLOCK_GateQDC0      = ((0x00U << 16U) | (29U)),         /*!< Clock gate name: QDC0      */
+    kCLOCK_GateQDC1      = ((0x00U << 16U) | (30U)),         /*!< Clock gate name: QDC1      */
+    kCLOCK_GateFLEXPWM0  = ((0x00U << 16U) | (31U)),         /*!< Clock gate name: FLEXPWM0  */
+    kCLOCK_GateFLEXPWM1  = ((0x10U << 16U) | (0U)),          /*!< Clock gate name: FLEXPWM1  */
+    kCLOCK_GateOSTIMER0  = ((0x10U << 16U) | (1U)),          /*!< Clock gate name: OSTIMER0  */
+    kCLOCK_GateADC0      = ((0x10U << 16U) | (2U)),          /*!< Clock gate name: ADC0      */
+    kCLOCK_GateADC1      = ((0x10U << 16U) | (3U)),          /*!< Clock gate name: ADC1      */
+    kCLOCK_GateCMP0      = ((0x10U << 16U) | (4U)),          /*!< Clock gate name: CMP0      */
+    kCLOCK_GateCMP1      = ((0x10U << 16U) | (5U)),          /*!< Clock gate name: CMP1      */
+    kCLOCK_GateCMP2      = ((0x10U << 16U) | (6U)),          /*!< Clock gate name: CMP2      */
+    kCLOCK_GateOPAMP0    = ((0x10U << 16U) | (8U)),          /*!< Clock gate name: OPAMP0  */
+    kCLOCK_GateOPAMP1    = ((0x10U << 16U) | (9U)),          /*!< Clock gate name: OPAMP1  */
+    kCLOCK_GateOPAMP2    = ((0x10U << 16U) | (10U)),         /*!< Clock gate name: OPAMP2 */
+    kCLOCK_GatePORT0     = ((0x10U << 16U) | (12U)),         /*!< Clock gate name: PORT0  */
+    kCLOCK_GatePORT1     = ((0x10U << 16U) | (13U)),         /*!< Clock gate name: PORT1  */
+    kCLOCK_GatePORT2     = ((0x10U << 16U) | (14U)),         /*!< Clock gate name: PORT2  */
+    kCLOCK_GatePORT3     = ((0x10U << 16U) | (15U)),         /*!< Clock gate name: PORT3  */
+    kCLOCK_GatePORT4     = ((0x10U << 16U) | (16U)),         /*!< Clock gate name: PORT4  */
+    kCLOCK_GateFLEXCAN0  = ((0x10U << 16U) | (18U)),         /*!< Clock gate name: FLEXCAN0  */
+    kCLOCK_GateRAMA      = ((0x20U << 16U) | (1U)),          /*!< Clock gate name: RAMA      */
+    kCLOCK_GateRAMB      = ((0x20U << 16U) | (2U)),          /*!< Clock gate name: RAMB      */
+    kCLOCK_GateRAMC      = ((0x20U << 16U) | (3U)),          /*!< Clock gate name: RAMC      */
+    kCLOCK_GateGPIO0     = ((0x20U << 16U) | (4U)),          /*!< Clock gate name: GPIO0     */
+    kCLOCK_GateGPIO1     = ((0x20U << 16U) | (5U)),          /*!< Clock gate name: GPIO1     */
+    kCLOCK_GateGPIO2     = ((0x20U << 16U) | (6U)),          /*!< Clock gate name: GPIO2     */
+    kCLOCK_GateGPIO3     = ((0x20U << 16U) | (7U)),          /*!< Clock gate name: GPIO3     */
+    kCLOCK_GateGPIO4     = ((0x20U << 16U) | (8U)),          /*!< Clock gate name: GPIO4     */
+    kCLOCK_GateMAU0      = ((0x20U << 16U) | (9U)),          /*!< Clock gate name: MAU0      */
+    kCLOCK_GateROMC      = ((0x20U << 16U) | (10U)),         /*!< Clock gate name: ROMC      */
+    kCLOCK_GatePWM0SM0   = ((REG_PWM0SUBCTL << 16U) | (0U)), /*!< Clock gate name: PWM0 SM0  */
+    kCLOCK_GatePWM0SM1   = ((REG_PWM0SUBCTL << 16U) | (1U)), /*!< Clock gate name: PWM0 SM1  */
+    kCLOCK_GatePWM0SM2   = ((REG_PWM0SUBCTL << 16U) | (2U)), /*!< Clock gate name: PWM0 SM2  */
+    kCLOCK_GatePWM0SM3   = ((REG_PWM0SUBCTL << 16U) | (3U)), /*!< Clock gate name: PWM0 SM3  */
+    kCLOCK_GatePWM1SM0   = ((REG_PWM1SUBCTL << 16U) | (0U)), /*!< Clock gate name: PWM1 SM0  */
+    kCLOCK_GatePWM1SM1   = ((REG_PWM1SUBCTL << 16U) | (1U)), /*!< Clock gate name: PWM1 SM1  */
+    kCLOCK_GatePWM1SM2   = ((REG_PWM1SUBCTL << 16U) | (2U)), /*!< Clock gate name: PWM1 SM2  */
+    kCLOCK_GatePWM1SM3   = ((REG_PWM1SUBCTL << 16U) | (3U)), /*!< Clock gate name: PWM1 SM3  */
+    kCLOCK_GateNotAvail  = (0xFFFFFFFFU),                    /*!< Clock gate name: None      */
+} clock_ip_name_t;
+
+/*! @brief Clock ip name array for AOI. */
+#define AOI_CLOCKS {kCLOCK_GateAOI0, kCLOCK_GateAOI1}
+/*! @brief Clock ip name array for CRC. */
+#define CRC_CLOCKS {kCLOCK_GateCRC0}
+/*! @brief Clock ip name array for CTIMER. */
+#define CTIMER_CLOCKS {kCLOCK_GateCTIMER0, kCLOCK_GateCTIMER1, kCLOCK_GateCTIMER2}
+/*! @brief Clock ip name array for DMA. */
+#define DMA_CLOCKS {kCLOCK_GateDMA0}
+/*! @brief Clock gate name array for EDMA. */
+#define EDMA_CLOCKS {kCLOCK_GateDMA0}
+/*! @brief Clock ip name array for ERM. */
+#define ERM_CLOCKS {kCLOCK_GateERM0}
+/*! @brief Clock ip name array for EIM. */
+#define EIM_CLOCKS {kCLOCK_GateEIM0}
+/*! @brief Clock ip name array for FLEXCAN. */
+#define FLEXCAN_CLOCKS {kCLOCK_GateFLEXCAN0}
+/*! @brief Clock ip name array for FREQME. */
+#define FREQME_CLOCKS {kCLOCK_GateFREQME}
+/*! @brief Clock ip name array for GPIO. */
+#define GPIO_CLOCKS {kCLOCK_GateGPIO0, kCLOCK_GateGPIO1, kCLOCK_GateGPIO2, kCLOCK_GateGPIO3, kCLOCK_GateGPIO4}
+/*! @brief Clock ip name array for INPUTMUX. */
+#define INPUTMUX_CLOCKS {kCLOCK_GateINPUTMUX0}
+/*! @brief Clock ip name array for GPIO. */
+#define LPCMP_CLOCKS {kCLOCK_GateCMP0, kCLOCK_GateCMP1, kCLOCK_GateCMP2}
+/*! @brief Clock ip name array for LPADC. */
+#define LPADC_CLOCKS {kCLOCK_GateADC0, kCLOCK_GateADC1}
+/*! @brief Clock ip name array for LPUART. */
+#define LPUART_CLOCKS {kCLOCK_GateLPUART0, kCLOCK_GateLPUART1, kCLOCK_GateLPUART2, kCLOCK_GateLPUART3}
+/*! @brief Clock ip name array for LPI2C. */
+#define LPI2C_CLOCKS {kCLOCK_GateLPI2C0, kCLOCK_GateLPI2C1}
+/*! @brief Clock ip name array for LSPI. */
+#define LPSPI_CLOCKS {kCLOCK_GateLPSPI0, kCLOCK_GateLPSPI1}
+/*! @brief Clock ip name array for MAU. */
+#define MAU_CLOCKS {kCLOCK_GateMAU0}
+/*! @brief Clock ip name array for OSTIMER. */
+#define OSTIMER_CLOCKS {kCLOCK_GateOSTIMER0}
+/*! @brief Clock ip name array for OPAMP. */
+#define OPAMP_CLOCKS {kCLOCK_GateOPAMP0, kCLOCK_GateOPAMP1, kCLOCK_GateOPAMP2}
+/*! @brief Clock ip name array for PWM. */
+#define PWM_CLOCKS                                                                         \
+    {                                                                                      \
+        {kCLOCK_GatePWM0SM0, kCLOCK_GatePWM0SM1, kCLOCK_GatePWM0SM2, kCLOCK_GatePWM0SM3},  \
+        {                                                                                  \
+            kCLOCK_GatePWM1SM0, kCLOCK_GatePWM1SM1, kCLOCK_GatePWM1SM2, kCLOCK_GatePWM1SM3 \
+        }                                                                                  \
+    }
+/*! @brief Clock ip name array for PORT. */
+#define PORT_CLOCKS {kCLOCK_GatePORT0, kCLOCK_GatePORT1, kCLOCK_GatePORT2, kCLOCK_GatePORT3, kCLOCK_GatePORT4 \ }
+/*! @brief Clock ip name array for QDC. */
+#define QDC_CLOCKS {kCLOCK_GateQDC0, kCLOCK_GateQDC1}
+/*! @brief Clock ip name array for SMARTDMA. */
+#define SMARTDMA_CLOCKS {kCLOCK_Smartdma}
+/*! @brief Clock ip name array for UTICK. */
+#define UTICK_CLOCKS {kCLOCK_GateUTICK0}
+/*! @brief Clock ip name array for WWDT. */
+#define WWDT_CLOCKS {kCLOCK_GateWWDT0}
+
+/*! @brief Clock name used to get clock frequency. */
+typedef enum _clock_name
+{
+    kCLOCK_MainClk,    /*!< MAIN_CLK                   */
+    kCLOCK_CoreSysClk, /*!< Core/system clock(CPU_CLK) */
+    kCLOCK_SYSTEM_CLK, /*!< SYSTEM clock/AHB_BUS       */
+    kCLOCK_BusClk,     /*!< SYSTEM clock divided by 2  */
+    kCLOCK_ExtClk,     /*!< External Clock             */
+    kCLOCK_FroHf,      /*!< FRO192                     */
+    kCLOCK_FroHfDiv,   /*!< Divided by FRO192          */
+    kCLOCK_Clk45M,     /*!< CLK45M                     */
+    kCLOCK_Fro12M,     /*!< FRO12M                     */
+    kCLOCK_Fro12MDiv,  /*!< FRO12MDiv                  */
+    kCLOCK_Clk1M,      /*!< CLK1M                      */
+    kCLOCK_Fro16K,     /*!< FRO16K                     */
+    kCLOCK_Clk16K0,    /*!< CLK16K[0]                  */
+    kCLOCK_Clk16K1,    /*!< CLK16K[1]                  */
+    kCLOCK_SLOW_CLK,   /*!< SYSTEM_CLK divided by 6    */
+} clock_name_t;
+
+/*! @brief Peripherals clock source definition. */
+#define BUS_CLK kCLOCK_BusClk
+
+/*! @brief Clock Mux Switches
+ *  The encoding is as follows each connection identified is 32bits wide while
+ * 24bits are valuable starting from LSB upwards
+ *
+ *  [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
+ *
+ */
+
+#define CLK_ATTACH_REG_OFFSET(value) (((uint32_t)(value)) >> 16U)
+#define CLK_ATTACH_CLK_SEL(value)    (((uint32_t)(value)) & 0x0000FFFFU)
+#define CLK_ATTACH_MUX(reg, sel)     ((((uint32_t)(reg)) << 16U) | (sel))
+
+/*! @brief Clock name used to get clock frequency. */
+typedef enum _clock_select_name
+{
+    kCLOCK_SelCTIMER0  = (0x0A0U), /*!< CTIMER0   clock selection */
+    kCLOCK_SelCTIMER1  = (0x0A8U), /*!< CTIMER1   clock selection */
+    kCLOCK_SelCTIMER2  = (0x0B0U), /*!< CTIMER2   clock selection */
+    kCLOCK_SelLPI2C0   = (0x0C0U), /*!< LPI2C0    clock selection */
+    kCLOCK_SelLPI2C1   = (0x0C8U), /*!< LPI2C1    clock selection */
+    kCLOCK_SelLPSPI0   = (0x0D0U), /*!< LPSPI0    clock selection */
+    kCLOCK_SelLPSPI1   = (0x0D8U), /*!< LPSPI1    clock selection */
+    kCLOCK_SelLPUART0  = (0x0E0U), /*!< LPUART0   clock selection */
+    kCLOCK_SelLPUART1  = (0x0E8U), /*!< LPUART1   clock selection */
+    kCLOCK_SelLPUART2  = (0x0F0U), /*!< LPUART2   clock selection */
+    kCLOCK_SelLPUART3  = (0x0F8U), /*!< LPUART3   clock selection */
+    kCLOCK_SelLPTMR0   = (0x100U), /*!< LPTMR0    clock selection */
+    kCLOCK_SelOSTIMER0 = (0x108U), /*!< OSTIMER0  clock selection */
+    kCLOCK_SelADC      = (0x110U), /*!< ADC       clock selection */
+    kCLOCK_SelCMP0_RR  = (0x120U), /*!< CMP0_RR   clock selection */
+    kCLOCK_SelCMP1_RR  = (0x130U), /*!< CMP1_RR   clock selection */
+    kCLOCK_SelCMP2_RR  = (0x140U), /*!< CMP2_RR   clock selection */
+    kCLOCK_SelFLEXCAN0 = (0x148U), /*!< FLEXCAN0  clock selection */
+    kCLOCK_SelTRACE    = (0x150U), /*!< TRACE     clock selection */
+    kCLOCK_SelCLKOUT   = (0x158U), /*!< CLKOUT    clock selection */
+    kCLOCK_SelSCGSCS   = (0x200U), /*!< SCG SCS   clock selection */
+    kCLOCK_SelMax      = (0x200U), /*!< MAX       clock selection */
+} clock_select_name_t;
+
+/*!
+ * @brief The enumerator of clock attach Id.
+ */
+typedef enum _clock_attach_id
+{
+    kCLK_IN_to_MAIN_CLK  = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 1U),      /*!< Attach clk_in to MAIN_CLK. */
+    kFRO12M_to_MAIN_CLK  = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 2U),      /*!< Attach FRO_12M to MAIN_CLK. */
+    kFRO_HF_to_MAIN_CLK  = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 3U),      /*!< Attach FRO_HF to MAIN_CLK. */
+    kCLK_16K_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 4U),      /*!< Attach CLK_16K[1] to MAIN_CLK. */
+    kNONE_to_MAIN_CLK    = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 7U),      /*!< Attach NONE to MAIN_CLK. */
+
+    kFRO_LF_DIV_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 0U),   /*!< Attach FRO_LF_DIV to CTIMER0.  */
+    kFRO_HF_to_CTIMER0     = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 1U),   /*!< Attach FRO_HF to CTIMER0.  */
+    kCLK_IN_to_CTIMER0     = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 3U),   /*!< Attach CLK_IN to CTIMER0.  */
+    kCLK_16K_to_CTIMER0    = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 4U),   /*!< Attach CLK_16K to CTIMER0. */
+    kCLK_1M_to_CTIMER0     = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 5U),   /*!< Attach CLK_1M to CTIMER0.  */
+    kNONE_to_CTIMER0       = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 7U),   /*!< Attach NONE to CTIMER0.    */
+
+    kFRO_LF_DIV_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 0U),   /*!< Attach FRO_LF_DIV to CTIMER1.  */
+    kFRO_HF_to_CTIMER1     = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 1U),   /*!< Attach FRO_HF to CTIMER1.  */
+    kCLK_IN_to_CTIMER1     = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 3U),   /*!< Attach CLK_IN to CTIMER1.  */
+    kCLK_16K_to_CTIMER1    = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 4U),   /*!< Attach CLK_16K to CTIMER1. */
+    kCLK_1M_to_CTIMER1     = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 5U),   /*!< Attach CLK_1M to CTIMER1.  */
+    kNONE_to_CTIMER1       = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 7U),   /*!< Attach NONE to CTIMER1.    */
+
+    kFRO_LF_DIV_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 0U),   /*!< Attach FRO_LF_DIV to CTIMER2.  */
+    kFRO_HF_to_CTIMER2     = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 1U),   /*!< Attach FRO_HF to CTIMER2.  */
+    kCLK_IN_to_CTIMER2     = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 3U),   /*!< Attach CLK_IN to CTIMER2.  */
+    kCLK_16K_to_CTIMER2    = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 4U),   /*!< Attach CLK_16K to CTIMER2. */
+    kCLK_1M_to_CTIMER2     = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 5U),   /*!< Attach CLK_1M to CTIMER2.  */
+    kNONE_to_CTIMER2       = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 7U),   /*!< Attach NONE to CTIMER2.    */
+
+    kFRO_HF_to_FLEXCAN0     = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN0, 1U), /*!< Attach FRO_HF to FLEXCAN0.*/
+    kFRO_HF_DIV_to_FLEXCAN0 = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN0, 2U), /*!< Attach FRO_HF_DIV to FLEXCAN0.*/
+    kCLK_IN_to_FLEXCAN0     = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN0, 3U), /*!< Attach CLK_IN to FLEXCAN0. */
+    kNONE_to_FLEXCAN0       = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN0, 7U), /*!< Attach NONE to FLEXCAN0. */
+
+    kFRO_LF_DIV_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 0U),     /*!< Attach FRO_LF_DIV to LPI2C0. */
+    kFRO_HF_DIV_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 2U),     /*!< Attach FRO_HF_DIV to LPI2C0. */
+    kCLK_IN_to_LPI2C0     = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 3U),     /*!< Attach CLK_IN to LPI2C0.     */
+    kCLK_1M_to_LPI2C0     = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 5U),     /*!< Attach CLK_1M to LPI2C0.     */
+    kNONE_to_LPI2C0       = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 7U),     /*!< Attach NONE to LPI2C0.       */
+
+    kFRO_LF_DIV_to_LPI2C1 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C1, 0U),     /*!< Attach FRO_LF_DIV to LPI2C1. */
+    kFRO_HF_DIV_to_LPI2C1 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C1, 2U),     /*!< Attach FRO_HF_DIV to LPI2C1. */
+    kCLK_IN_to_LPI2C1     = CLK_ATTACH_MUX(kCLOCK_SelLPI2C1, 3U),     /*!< Attach CLK_IN to LPI2C1.     */
+    kCLK_1M_to_LPI2C1     = CLK_ATTACH_MUX(kCLOCK_SelLPI2C1, 5U),     /*!< Attach CLK_1M to LPI2C1.     */
+    kNONE_to_LPI2C1       = CLK_ATTACH_MUX(kCLOCK_SelLPI2C1, 7U),     /*!< Attach NONE to LPI2C1.       */
+
+    kFRO_LF_DIV_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 0U),     /*!< Attach FRO_LF_DIV to LPSPI0. */
+    kFRO_HF_DIV_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 2U),     /*!< Attach FRO_HF_DIV to LPSPI0. */
+    kCLK_IN_to_LPSPI0     = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 3U),     /*!< Attach CLK_IN to LPSPI0.     */
+    kCLK_1M_to_LPSPI0     = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 5U),     /*!< Attach CLK_1M to LPSPI0.     */
+    kNONE_to_LPSPI0       = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 7U),     /*!< Attach NONE to LPSPI0.       */
+
+    kFRO_LF_DIV_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 0U),     /*!< Attach FRO_LF_DIV to LPSPI1. */
+    kFRO_HF_DIV_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 2U),     /*!< Attach FRO_HF_DIV to LPSPI1. */
+    kCLK_IN_to_LPSPI1     = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 3U),     /*!< Attach CLK_IN to LPSPI1.     */
+    kCLK_1M_to_LPSPI1     = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 5U),     /*!< Attach CLK_1M to LPSPI1.     */
+    kNONE_to_LPSPI1       = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 7U),     /*!< Attach NONE to LPSPI1.       */
+
+    kFRO_LF_DIV_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 0U),   /*!< Attach FRO_LF_DIV to LPUART0.     */
+    kFRO_HF_DIV_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 2U),   /*!< Attach FRO_HF_DIV to LPUART0. */
+    kCLK_IN_to_LPUART0     = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 3U),   /*!< Attach CLK_IN to LPUART0. */
+    kCLK_16K_to_LPUART0    = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 4U),   /*!< Attach CLK_16K to LPUART0. */
+    kCLK_1M_to_LPUART0     = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 5U),   /*!< Attach CLK_1M to LPUART0. */
+    kNONE_to_LPUART0       = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 7U),   /*!< Attach NONE to LPUART0. */
+
+    kFRO_LF_DIV_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 0U),   /*!< Attach FRO_LF_DIV to LPUART1.     */
+    kFRO_HF_DIV_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 2U),   /*!< Attach FRO_HF_DIV to LPUART1. */
+    kCLK_IN_to_LPUART1     = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 3U),   /*!< Attach CLK_IN to LPUART1. */
+    kCLK_16K_to_LPUART1    = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 4U),   /*!< Attach CLK_16K to LPUART1. */
+    kCLK_1M_to_LPUART1     = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 5U),   /*!< Attach CLK_1M to LPUART1. */
+    kNONE_to_LPUART1       = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 7U),   /*!< Attach NONE to LPUART1. */
+
+    kFRO_LF_DIV_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 0U),   /*!< Attach FRO_LF_DIV to LPUART2.     */
+    kFRO_HF_DIV_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 2U),   /*!< Attach FRO_HF_DIV to LPUART2. */
+    kCLK_IN_to_LPUART2     = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 3U),   /*!< Attach CLK_IN to LPUART2. */
+    kCLK_16K_to_LPUART2    = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 4U),   /*!< Attach CLK_16K to LPUART2. */
+    kCLK_1M_to_LPUART2     = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 5U),   /*!< Attach CLK_1M to LPUART2. */
+    kNONE_to_LPUART2       = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 7U),   /*!< Attach NONE to LPUART2. */
+
+    kFRO_LF_DIV_to_LPUART3 = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 0U),   /*!< Attach FRO_LF_DIV to LPUART2.     */
+    kFRO_HF_DIV_to_LPUART3 = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 2U),   /*!< Attach FRO_HF_DIV to LPUART2. */
+    kCLK_IN_to_LPUART3     = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 3U),   /*!< Attach CLK_IN to LPUART2. */
+    kCLK_16K_to_LPUART3    = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 4U),   /*!< Attach CLK_16K to LPUART2. */
+    kCLK_1M_to_LPUART3     = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 5U),   /*!< Attach CLK_1M to LPUART2. */
+    kNONE_to_LPUART3       = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 7U),   /*!< Attach NONE to LPUART2. */
+
+    kFRO_LF_DIV_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 0U),     /*!< Attach FRO_LF_DIV to LPTMR0. */
+    kFRO_HF_DIV_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 2U),     /*!< Attach FRO_HF_DIV to LPTMR0. */
+    kCLK_IN_to_LPTMR0     = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 3U),     /*!< Attach CLK_IN to LPTMR0.     */
+    kCLK_1M_to_LPTMR0     = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 5U),     /*!< Attach CLK_1M to LPTMR0.     */
+    kNONE_to_LPTMR0       = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 7U),     /*!< Attach NONE to LPTMR0.       */
+
+    kCLK_16K_to_OSTIMER = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 0U),     /*!< Attach FRO16K to OSTIMER0. */
+    kCLK_1M_to_OSTIMER  = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 2U),     /*!< Attach CLK_1M to OSTIMER0. */
+    kNONE_to_OSTIMER    = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 3U),     /*!< Attach NONE to OSTIMER0.   */
+
+    kFRO_LF_DIV_to_ADC = CLK_ATTACH_MUX(kCLOCK_SelADC, 0U),           /*!< Attach FRO_LF_DIV to ADC. */
+    kFRO_HF_to_ADC     = CLK_ATTACH_MUX(kCLOCK_SelADC, 1U),           /*!< Attach FRO_HF to ADC. */
+    kCLK_IN_to_ADC     = CLK_ATTACH_MUX(kCLOCK_SelADC, 3U),           /*!< Attach CLK_IN to ADC. */
+    kCLK_1M_to_ADC     = CLK_ATTACH_MUX(kCLOCK_SelADC, 5U),           /*!< Attach CLK_1M to ADC. */
+    kNONE_to_ADC       = CLK_ATTACH_MUX(kCLOCK_SelADC, 7U),           /*!< Attach NONE to ADC. */
+
+    kFRO_LF_DIV_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 0U),      /*!< Attach FRO_LF_DIV to CMP0. */
+    kFRO_HF_DIV_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 2U),      /*!< Attach FRO_HF_DIV to CMP0. */
+    kCLK_IN_to_CMP0     = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 3U),      /*!< Attach CLK_IN to CMP0.     */
+    kCLK_1M_to_CMP0     = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 5U),      /*!< Attach CLK_1M to CMP0.     */
+    kNONE_to_CMP0       = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 7U),      /*!< Attach NONE to CMP0.       */
+
+    kFRO_LF_DIV_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 0U),      /*!< Attach FRO_LF_DIV to CMP1. */
+    kFRO_HF_DIV_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 2U),      /*!< Attach FRO_HF_DIV to CMP1. */
+    kCLK_IN_to_CMP1     = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 3U),      /*!< Attach CLK_IN to CMP1.     */
+    kCLK_1M_to_CMP1     = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 5U),      /*!< Attach CLK_1M to CMP1.     */
+    kNONE_to_CMP1       = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 7U),      /*!< Attach NONE to CMP1.       */
+
+    kFRO_LF_DIV_to_CMP2 = CLK_ATTACH_MUX(kCLOCK_SelCMP2_RR, 0U),      /*!< Attach FRO_LF_DIV to CMP2. */
+    kFRO_HF_DIV_to_CMP2 = CLK_ATTACH_MUX(kCLOCK_SelCMP2_RR, 2U),      /*!< Attach FRO_HF_DIV to CMP2. */
+    kCLK_IN_to_CMP2     = CLK_ATTACH_MUX(kCLOCK_SelCMP2_RR, 3U),      /*!< Attach CLK_IN to CMP2.     */
+    kCLK_1M_to_CMP2     = CLK_ATTACH_MUX(kCLOCK_SelCMP2_RR, 5U),      /*!< Attach CLK_1M to CMP2.     */
+    kNONE_to_CMP2       = CLK_ATTACH_MUX(kCLOCK_SelCMP2_RR, 7U),      /*!< Attach NONE to CMP2.       */
+
+    kCPU_CLK_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 0U),          /*!< Attach CPU_CLK to TRACE. */
+    kCLK_1M_to_TRACE  = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 1U),          /*!< Attach CLK_1M to TRACE.  */
+    kCLK_16K_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 2U),          /*!< Attach CLK_16K to TRACE. */
+    kNONE_to_TRACE    = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 3U),          /*!< Attach NONE to TRACE.    */
+
+    kFRO12M_to_CLKOUT     = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 0U),     /*!< Attach FRO12M to CLKOUT.     */
+    kFRO_HF_DIV_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 1U),     /*!< Attach FRO_HF_DIV to CLKOUT. */
+    kCLK_IN_to_CLKOUT     = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 2U),     /*!< Attach CLK_IN to CLKOUT.     */
+    kCLK_16K_to_CLKOUT    = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 3U),     /*!< Attach CLK_16K to CLKOUT.    */
+    kSLOW_CLK_to_CLKOUT   = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 6U),     /*!< Attach SLOW_CLK to CLKOUT.   */
+    kNONE_to_CLKOUT       = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 7U),     /*!< Attach NONE to CLKOUT.       */
+
+    kNONE_to_NONE = (0xFFFFFFFFU),                                    /*!< Attach NONE to NONE. */
+
+} clock_attach_id_t;
+
+/*! @brief Clock dividers */
+typedef enum _clock_div_name
+{
+    kCLOCK_DivCTIMER0   = (0x0A4U), /*!< CTIMER0   clock divider */
+    kCLOCK_DivCTIMER1   = (0x0ACU), /*!< CTIMER1   clock divider */
+    kCLOCK_DivCTIMER2   = (0x0B4U), /*!< CTIMER2   clock divider */
+    kCLOCK_DivWWDT0     = (0x0BCU), /*!< WWDT0     clock divider */
+    kCLOCK_DivLPI2C0    = (0x0C4U), /*!< LPI2C0    clock divider */
+    kCLOCK_DivLPI2C1    = (0x0CCU), /*!< LPI2C1    clock divider */
+    kCLOCK_DivLPSPI0    = (0x0D4U), /*!< LPSPI0    clock divider */
+    kCLOCK_DivLPSPI1    = (0x0DCU), /*!< LPSPI1    clock divider */
+    kCLOCK_DivLPUART0   = (0x0E4U), /*!< LPUART0   clock divider */
+    kCLOCK_DivLPUART1   = (0x0ECU), /*!< LPUART1   clock divider */
+    kCLOCK_DivLPUART2   = (0x0F4U), /*!< LPUART2   clock divider */
+    kCLOCK_DivLPUART3   = (0x0FCU), /*!< LPUART3   clock divider */
+    kCLOCK_DivLPTMR0    = (0x104U), /*!< LPTMR0    clock divider */
+    kCLOCK_DivADC       = (0x114U), /*!< ADC       clock divider */
+    kCLOCK_DivCMP0_FUNC = (0x11CU), /*!< CMP0_FUNC clock divider */
+    kCLOCK_DivCMP0_RR   = (0x124U), /*!< CMP0_RR   clock divider */
+    kCLOCK_DivCMP1_FUNC = (0x12CU), /*!< CMP1_FUNC clock divider */
+    kCLOCK_DivCMP1_RR   = (0x134U), /*!< CMP1_RR   clock divider */
+    kCLOCK_DivCMP2_FUNC = (0x13CU), /*!< CMP2_FUNC clock divider */
+    kCLOCK_DivCMP2_RR   = (0x144U), /*!< CMP2_RR   clock divider */
+    kCLOCK_DivFLEXCAN0  = (0x14CU), /*!< FLEXCAN0  clock divider */
+    kCLOCK_DivTRACE     = (0x154U), /*!< DBG_TRACE clock divider */
+    kCLOCK_DivCLKOUT    = (0x15CU), /*!< CLKOUT    clock divider */
+    kCLOCK_DivSLOWCLK   = (0x378U), /*!< SLOWCLK   clock divider */
+    kCLOCK_DivBUSCLK    = (0x37CU), /*!< BUSCLK    clock divider */
+    kCLOCK_DivAHBCLK    = (0x380U), /*!< AHBCLK    clock divider */
+    kCLOCK_DivFRO_HF    = (0x388U), /*!< FROHF     clock divider */
+    kCLOCK_DivFRO_LF    = (0x38CU), /*!< FROLF     clock divider */
+    kCLOCK_DivMax       = (0x38CU)  /*!< Max       clock divider */
+} clock_div_name_t;
+
+/*!
+ * @brief firc trim source.
+ */
+typedef enum _clke_16k
+{
+    kCLKE_16K_SYSTEM   = VBAT_FROCLKE_CLKE(1U), /*!< To VSYS domain.     */
+    kCLKE_16K_COREMAIN = VBAT_FROCLKE_CLKE(2U)  /*!< To VDD_CORE domain. */
+} clke_16k_t;
+
+/*!
+ * @brief SCG status return codes.
+ */
+enum _scg_status
+{
+    kStatus_SCG_Busy       = MAKE_STATUS(kStatusGroup_SCG, 1), /*!< Clock is busy.  */
+    kStatus_SCG_InvalidSrc = MAKE_STATUS(kStatusGroup_SCG, 2)  /*!< Invalid source. */
+};
+
+/*!
+ * @brief sirc trim mode.
+ */
+typedef enum _sirc_trim_mode
+{
+    kSCG_SircTrimNonUpdate = SCG_SIRCCSR_SIRCTREN_MASK,
+    /*!< Trim enable but not enable trim value update. In this mode, the
+     trim value is fixed to the initialized value which is defined by
+     trimCoar and trimFine in configure structure \ref sirc_trim_mode_t.*/
+
+    kSCG_SircTrimUpdate = SCG_SIRCCSR_SIRCTREN_MASK | SCG_SIRCCSR_SIRCTRUP_MASK
+    /*!< Trim enable and trim value update enable. In this mode, the trim
+     value is auto update. */
+
+} sirc_trim_mode_t;
+
+/*!
+ * @brief sirc trim source.
+ */
+typedef enum _sirc_trim_src
+{
+    kNoTrimSrc             = 0, /*!< No external tirm source.    */
+    kSCG_SircTrimSrcSysOsc = 2U /*!< System OSC.                 */
+} sirc_trim_src_t;
+
+/*!
+ * @brief sirc trim configuration.
+ */
+typedef struct _sirc_trim_config
+{
+    sirc_trim_mode_t trimMode; /*!< Trim mode.       */
+    sirc_trim_src_t trimSrc;   /*!< Trim source.     */
+    uint16_t trimDiv;          /*!< Divider of SOSC. */
+    uint8_t cltrim;            /*!< Trim coarse value; Irrelevant if trimMode is
+                                  kSCG_TrimUpdate. */
+    uint8_t ccotrim;           /*!< Trim fine value; Irrelevant if trimMode is
+                                  kSCG_TrimUpdate. */
+} sirc_trim_config_t;
+
+/*!
+ * @brief SCG system OSC monitor mode.
+ */
+typedef enum _scg_sosc_monitor_mode
+{
+    kSCG_SysOscMonitorDisable = 0U,                         /*!< Monitor disabled. */
+    kSCG_SysOscMonitorInt     = SCG_SOSCCSR_SOSCCM_MASK,    /*!< Interrupt when the SOSC
+                                                               error is detected. */
+    kSCG_SysOscMonitorReset =
+        SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK /*!< Reset when the SOSC error is detected. */
+} scg_sosc_monitor_mode_t;
+
+/*!
+ * @brief The active run mode (voltage level).
+ */
+typedef enum _run_mode
+{
+    kMD_Mode, /*!< Mid voltage (1.0 V).       */
+    kOD_Mode, /*!< Overdrive voltage (1.2 V). */
+} run_mode_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief Enable the clock for specific IP.
+ * @param clk : Clock to be enabled.
+ * @return  Nothing
+ */
+static inline void CLOCK_EnableClock(clock_ip_name_t clk)
+{
+    uint32_t reg_offset         = CLK_GATE_REG_OFFSET(clk);
+    uint32_t bit_shift          = CLK_GATE_BIT_SHIFT(clk);
+    volatile uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_SET)) + reg_offset);
+
+    if (clk == kCLOCK_GateNotAvail)
+    {
+        return;
+    }
+
+    /* Unlock clock configuration */
+    SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK;
+
+    if (reg_offset == REG_PWM0SUBCTL)
+    {
+        SYSCON->PWM0SUBCTL |= (1UL << bit_shift);
+        MRCC0->MRCC_GLB_CC0_SET = MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK;
+    }
+    else if (reg_offset == REG_PWM1SUBCTL)
+    {
+        SYSCON->PWM1SUBCTL |= (1UL << bit_shift);
+        MRCC0->MRCC_GLB_CC1_SET = MRCC_MRCC_GLB_CC1_FLEXPWM1_MASK;
+    }
+    else
+    {
+        *pClkCtrl = (1UL << bit_shift);
+    }
+
+    /* Freeze clock configuration */
+    SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK;
+}
+
+/**
+ * @brief Disable the clock for specific IP.
+ * @param clk : Clock to be Disabled.
+ * @return  Nothing
+ */
+static inline void CLOCK_DisableClock(clock_ip_name_t clk)
+{
+    uint32_t reg_offset         = CLK_GATE_REG_OFFSET(clk);
+    uint32_t bit_shift          = CLK_GATE_BIT_SHIFT(clk);
+    volatile uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_CLR)) + reg_offset);
+
+    if (clk == kCLOCK_GateNotAvail)
+    {
+        return;
+    }
+
+    /* Unlock clock configuration */
+    SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK;
+
+    if (reg_offset == REG_PWM0SUBCTL)
+    {
+        SYSCON->PWM0SUBCTL &= ~(1UL << bit_shift);
+
+        if (0U == (SYSCON->PWM0SUBCTL & 0xFU))
+        {
+            MRCC0->MRCC_GLB_CC0_CLR = MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK;
+        }
+    }
+    else if (reg_offset == REG_PWM1SUBCTL)
+    {
+        SYSCON->PWM1SUBCTL &= ~(1UL << bit_shift);
+
+        if (0U == (SYSCON->PWM1SUBCTL & 0xFU))
+        {
+            MRCC0->MRCC_GLB_CC1_CLR = MRCC_MRCC_GLB_CC1_FLEXPWM1_MASK;
+        }
+    }
+    else
+    {
+        *pClkCtrl = (1UL << bit_shift);
+    }
+
+    /* Freeze clock configuration */
+    SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK;
+}
+
+/**
+ * @brief   Configure the clock selection muxes.
+ * @param   connection  : Clock to be configured.
+ */
+void CLOCK_AttachClk(clock_attach_id_t connection);
+
+/**
+ * @brief   Get the actual clock attach id.
+ * This fuction uses the offset in input attach id, then it reads the actual
+ * source value in the register and combine the offset to obtain an actual
+ * attach id.
+ * @param   connection  : Clock attach id to get.
+ * @return  Clock source value.
+ */
+clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t connection);
+
+/**
+ * @brief   Set the clock select value.
+ * This fuction set the peripheral clock select value.
+ * @param   sel_name : Clock select.
+ * @param   value    : value to be set.
+ */
+void CLOCK_SetClockSelect(clock_select_name_t sel_name, uint32_t value);
+
+/**
+ * @brief   Get the clock select value.
+ * This fuction get the peripheral clock select value.
+ * @param   sel_name  : Clock select.
+ * @return  Clock source value.
+ */
+uint32_t CLOCK_GetClockSelect(clock_select_name_t sel_name);
+
+/**
+ * @brief   Setup peripheral clock dividers.
+ * @param   div_name : Clock divider name
+ * @param   value    : Value to be divided
+ */
+void CLOCK_SetClockDiv(clock_div_name_t div_name, uint32_t value);
+
+/**
+ * @brief   Get peripheral clock dividers.
+ * @param   div_name    : Clock divider name
+ * @return  peripheral clock dividers
+ */
+uint32_t CLOCK_GetClockDiv(clock_div_name_t div_name);
+
+/**
+ * @brief   Halt peripheral clock dividers.
+ * @param   div_name    : Clock divider name
+ */
+void CLOCK_HaltClockDiv(clock_div_name_t div_name);
+
+/**
+ * @brief   Initialize the FROHF to given frequency (48,64,96,192).
+ * This function turns on FIRC and select the given frequency as the source of
+ * fro_hf
+ * @param   iFreq   : Desired frequency.
+ * @return  returns success or fail status.
+ */
+status_t CLOCK_SetupFROHFClocking(uint32_t iFreq);
+
+/**
+ * @brief   Initialize the FRO12M.
+ * This function turns on FRO12M.
+ * @return  returns success or fail status.
+ */
+status_t CLOCK_SetupFRO12MClocking(void);
+
+/**
+ * @brief   Initialize the FRO16K.
+ * This function turns on FRO16K.
+ * @param   clk_16k_enable_mask: 0-3
+ *             0b00: disable both clk_16k0 and clk_16k1
+ *             0b01: only enable clk_16k0
+ *             0b10: only enable clk_16k1
+ *             0b11: enable both clk_16k0 and clk_16k1
+ * @return  returns success or fail status.
+ */
+status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask);
+
+/**
+ * @brief   Initialize the external osc clock to given frequency.
+ * @param   iFreq   : Desired frequency (must be equal to exact rate in Hz)
+ * @return  returns success or fail status.
+ */
+status_t CLOCK_SetupExtClocking(uint32_t iFreq);
+
+/**
+ * @brief   Initialize the external reference clock to given frequency.
+ * @param   iFreq   : Desired frequency (must be equal to exact rate in Hz)
+ * @return  returns success or fail status.
+ */
+status_t CLOCK_SetupExtRefClocking(uint32_t iFreq);
+
+/*! @brief  Return Frequency of selected clock
+ *  @return Frequency of selected clock
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName);
+
+/*! @brief  Return Frequency of core
+ *  @return Frequency of the core
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void);
+
+/*! @brief  Return Frequency of CTimer functional Clock
+ *  @return Frequency of CTimer functional Clock
+ */
+uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
+
+/*! @brief  Return Frequency of LPI2C0 functional Clock
+ *  @return Frequency of LPI2C0 functional Clock
+ */
+uint32_t CLOCK_GetLpi2cClkFreq(uint32_t id);
+
+/*! @brief  Return Frequency of LPSPI functional Clock
+ *  @return Frequency of LPSPI functional Clock
+ */
+uint32_t CLOCK_GetLpspiClkFreq(uint32_t id);
+
+/*! @brief  Return Frequency of LPUART functional Clock
+ *  @return Frequency of LPUART functional Clock
+ */
+uint32_t CLOCK_GetLpuartClkFreq(uint32_t id);
+
+/*! @brief  Return Frequency of LPTMR functional Clock
+ *  @return Frequency of LPTMR functional Clock
+ */
+uint32_t CLOCK_GetLptmrClkFreq(void);
+
+/*! @brief  Return Frequency of OSTIMER
+ *  @return Frequency of OSTIMER Clock
+ */
+uint32_t CLOCK_GetOstimerClkFreq(void);
+
+/*! @brief  Return Frequency of Adc Clock
+ *  @return Frequency of Adc.
+ */
+uint32_t CLOCK_GetAdcClkFreq(uint32_t id);
+
+/*! @brief  Return Frequency of CMP Function Clock
+ *  @return Frequency of CMP Function.
+ */
+uint32_t CLOCK_GetCmpFClkFreq(uint32_t id);
+
+/*! @brief  Return Frequency of CMP Round Robin Clock
+ *  @return Frequency of CMP Round Robin.
+ */
+uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id);
+
+/*! @brief  Return Frequency of Trace Clock
+ *  @return Frequency of Trace.
+ */
+uint32_t CLOCK_GetTraceClkFreq(void);
+
+/*! @brief  Return Frequency of CLKOUT Clock
+ *  @return Frequency of CLKOUT.
+ */
+uint32_t CLOCK_GetClkoutClkFreq(void);
+
+/*! brief  Return Frequency of WWDT Clock
+ *  return Frequency of WWDT.
+ */
+uint32_t CLOCK_GetWwdtClkFreq(void);
+
+/*! @brief  Return Frequency of FlexCAN FCLK
+ *  @return Frequency of FlexCAN FCLK.
+ */
+uint32_t CLOCK_GetFlexcanClkFreq(void);
+
+/**
+ * @brief   Setup FRO 12M trim.
+ * @param   config   : FRO 12M trim value
+ * @return  returns success or fail status.
+ */
+status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config);
+
+/*!
+ * @brief Sets the system OSC monitor mode.
+ *
+ * This function sets the system OSC monitor mode. The mode can be disabled,
+ * it can generate an interrupt when the error is disabled, or reset when the
+ * error is detected.
+ *
+ * @param mode Monitor mode to set.
+ */
+void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode);
+
+/*!
+ * @brief   Set the additional number of wait-states added to account for the
+ * ratio of system clock period to flash access time during full speed power
+ * mode.
+ * @param   system_freq_hz  : Input frequency
+ * @param   mode            : Active run mode (voltage level).
+ * @return  success or fail status
+ */
+status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_CLOCK_H_ */
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_edma_soc.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_edma_soc.c
new file mode 100644
index 0000000000..79b9eb8a02
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_edma_soc.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2022 NXP
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_edma_soc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.edma_soc"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+extern void DMA_CH0_DriverIRQHandler(void);
+extern void DMA_CH1_DriverIRQHandler(void);
+extern void DMA_CH2_DriverIRQHandler(void);
+extern void DMA_CH3_DriverIRQHandler(void);
+extern void DMA_CH4_DriverIRQHandler(void);
+extern void DMA_CH5_DriverIRQHandler(void);
+extern void DMA_CH6_DriverIRQHandler(void);
+extern void DMA_CH7_DriverIRQHandler(void);
+extern void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * brief DMA instance 0, channel 0 IRQ handler.
+ *
+ */
+void DMA_CH0_DriverIRQHandler(void)
+{
+    /* Instance 0 channel 0 */
+    EDMA_DriverIRQHandler(0U, 0U);
+}
+
+/*!
+ * brief DMA instance 0, channel 1 IRQ handler.
+ *
+ */
+void DMA_CH1_DriverIRQHandler(void)
+{
+    /* Instance 0 channel 1 */
+    EDMA_DriverIRQHandler(0U, 1U);
+}
+
+/*!
+ * brief DMA instance 0, channel 2 IRQ handler.
+ *
+ */
+void DMA_CH2_DriverIRQHandler(void)
+{
+    /* Instance 0 channel 2 */
+    EDMA_DriverIRQHandler(0U, 2U);
+}
+
+/*!
+ * brief DMA instance 0, channel 3 IRQ handler.
+ *
+ */
+void DMA_CH3_DriverIRQHandler(void)
+{
+    /* Instance 0 channel 3 */
+    EDMA_DriverIRQHandler(0U, 3U);
+}
+
+/*!
+ * brief DMA instance 0, channel 4 IRQ handler.
+ *
+ */
+void DMA_CH4_DriverIRQHandler(void)
+{
+    /* Instance 0 channel 4 */
+    EDMA_DriverIRQHandler(0U, 4U);
+}
+/*!
+ * brief DMA instance 0, channel 5 IRQ handler.
+ *
+ */
+void DMA_CH5_DriverIRQHandler(void)
+{
+    /* Instance 0 channel 5 */
+    EDMA_DriverIRQHandler(0U, 5U);
+}
+
+/*!
+ * brief DMA instance 0, channel 6 IRQ handler.
+ *
+ */
+void DMA_CH6_DriverIRQHandler(void)
+{
+    /* Instance 0 channel 6 */
+    EDMA_DriverIRQHandler(0U, 6U);
+}
+
+/*!
+ * brief DMA instance 0, channel 7 IRQ handler.
+ *
+ */
+void DMA_CH7_DriverIRQHandler(void)
+{
+    /* Instance 0 channel 7 */
+    EDMA_DriverIRQHandler(0U, 7U);
+}
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_edma_soc.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_edma_soc.h
new file mode 100644
index 0000000000..de424c3594
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_edma_soc.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_EDMA_SOC_H_
+#define _FSL_EDMA_SOC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup edma_soc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @name Driver version */
+/*@{*/
+/*! @brief Driver version 2.0.0. */
+#define FSL_EDMA_SOC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*!@brief DMA IP version */
+#define FSL_EDMA_SOC_IP_DMA3 (1)
+#define FSL_EDMA_SOC_IP_DMA4 (0)
+
+/*!@brief DMA base table */
+#define EDMA_BASE_PTRS {DMA0}
+
+#define EDMA_CHN_IRQS                                                                                         \
+    {                                                                                                         \
+        {                                                                                                     \
+            DMA_CH0_IRQn, DMA_CH1_IRQn, DMA_CH2_IRQn, DMA_CH3_IRQn, DMA_CH4_IRQn, DMA_CH5_IRQn, DMA_CH6_IRQn, \
+                DMA_CH7_IRQn                                                                                  \
+        }                                                                                                     \
+    }
+
+/*!@brief EDMA base address convert macro */
+#define EDMA_CHANNEL_OFFSET           0x1000U
+#define EDMA_CHANNEL_ARRAY_STEP(base) (0x1000U)
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _FSL_EDMA_SOC_H_ */
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_inputmux_connections.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_inputmux_connections.h
new file mode 100644
index 0000000000..86907a0e30
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_inputmux_connections.h
@@ -0,0 +1,4647 @@
+/*
+ * Copyright 2023 , NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_INPUTMUX_CONNECTIONS_
+#define _FSL_INPUTMUX_CONNECTIONS_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief INPUTMUX_CONNECTION driver version 2.0.0. */
+#define FSL_INPUTMUX_CONNECTION_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#define INPUTMUX_GpioPortPinToPintsel(port, pin) ((pin) + (PINTSEL_PMUX_ID << PMUX_SHIFT))
+
+/*!
+ * @addtogroup inputmux_driver
+ * @{
+ */
+
+/*!
+ * @name Input multiplexing connections
+ * @{
+ */
+
+/*! @brief Periphinmux IDs */
+#define TIMER0CAPTSEL0            (0x020U)
+#define TIMER0TRIGIN              (0x030U)
+#define TIMER1CAPTSEL0            (0x040U)
+#define TIMER1TRIGIN              (0x050U)
+#define TIMER2CAPTSEL0            (0x060U)
+#define TIMER2TRIGIN              (0x070U)
+#define SMARTDMA0_TRIG0_REG       (0x0A0U)
+#define FREQMEAS_REF_REG          (0x180U)
+#define FREQMEAS_TAR_REG          (0x184U)
+#define TIMER3CAPTSEL0            (0x1A0U)
+#define TIMER3TRIGIN              (0x1B0U)
+#define TIMER4CAPTSEL0            (0x1C0U)
+#define TIMER4TRIGIN              (0x1D0U)
+#define AOI1_MUX_REG              (0x200U)
+#define CMP0_TRIG_REG             (0x260U)
+#define ADC0_TRIG0_REG            (0x280U)
+#define ADC2_TRIG0_REG            (0x2A0U)
+#define ADC1_TRIG0_REG            (0x2C0U)
+#define ADC3_TRIG0_REG            (0x2E0U)
+#define DAC0_TRIG0_REG            (0x300U)
+#define QDC0_TRIG_REG             (0x360U)
+#define QDC0_HOME_REG             (0x364U)
+#define QDC0_INDEX_REG            (0x368U)
+#define QDC0_PHASEB_REG           (0x36CU)
+#define QDC0_PHASEA_REG           (0x370U)
+#define QDC0_ICAP0_REG            (0x370U)
+#define QDC1_TRIG_REG             (0x380U)
+#define QDC1_HOME_REG             (0x384U)
+#define QDC1_INDEX_REG            (0x388U)
+#define QDC1_PHASEB_REG           (0x38CU)
+#define QDC1_PHASEA_REG           (0x390U)
+#define QDC1_ICAP0_REG            (0x390U)
+#define FlexPWM0_SM0_EXTA0_REG    (0x3A0U)
+#define FlexPWM0_SM0_EXTSYNC0_REG (0x3A4U)
+#define FlexPWM0_SM1_EXTA1_REG    (0x3A8U)
+#define FlexPWM0_SM1_EXTSYNC1_REG (0x3ACU)
+#define FlexPWM0_SM2_EXTA2_REG    (0x3B0U)
+#define FlexPWM0_SM2_EXTSYNC2_REG (0x3B4U)
+#define FlexPWM0_SM3_EXTA3_REG    (0x3B8U)
+#define FlexPWM0_SM3_EXTSYNC3_REG (0x3BCU)
+#define FlexPWM0_FAULT_REG        (0x3C0U)
+#define FlexPWM0_FORCE_REG        (0x3D0U)
+#define FlexPWM1_SM0_EXTA0_REG    (0x3E0U)
+#define FlexPWM1_SM0_EXTSYNC0_REG (0x3E4U)
+#define FlexPWM1_SM1_EXTA1_REG    (0x3E8U)
+#define FlexPWM1_SM1_EXTSYNC1_REG (0x3ECU)
+#define FlexPWM1_SM2_EXTA2_REG    (0x3F0U)
+#define FlexPWM1_SM2_EXTSYNC2_REG (0x3F4U)
+#define FlexPWM1_SM3_EXTA3_REG    (0x3F8U)
+#define FlexPWM1_SM3_EXTSYNC3_REG (0x3FCU)
+#define FlexPWM1_FAULT_REG        (0x400U)
+#define FlexPWM1_FORCE_REG        (0x410U)
+#define PWM0_EXT_CLK_REG          (0x420U)
+#define PWM1_EXT_CLK_REG          (0x424U)
+#define AOI0_MUX_REG              (0x440U)
+#define USBFS_TRIG_REG            (0x480U)
+#define EXT_TRIG0_REG             (0x4C0U)
+#define CMP1_TRIG_REG             (0x4E0U)
+#define CMP2_TRIG_REG             (0x500U)
+#define LPI2C2_TRIG_REG           (0x540U)
+#define LPI2C3_TRIG_REG           (0x560U)
+#define LPI2C0_TRIG_REG           (0x5A0U)
+#define LPI2C1_TRIG_REG           (0x5C0U)
+#define LPSPI0_TRIG_REG           (0x5E0U)
+#define LPSPI1_TRIG_REG           (0x600U)
+#define LPUART0_TRIG_REG          (0x620U)
+#define LPUART1_TRIG_REG          (0x640U)
+#define LPUART2_TRIG_REG          (0x660U)
+#define LPUART3_TRIG_REG          (0x680U)
+#define LPUART4_TRIG_REG          (0x6A0U)
+#define LPUART5_TRIG_REG          (0x6C0U)
+#define FLEXIO_TRIG0_REG          (0x6E0U)
+#define PMUX_SHIFT                (20U)
+
+typedef enum _inputmux_index_t
+{
+    kINPUTMUX_INDEX_CTIMER0CAPTSEL0    = 0U,
+    kINPUTMUX_INDEX_CTIMER0CAPTSEL1    = 1U,
+    kINPUTMUX_INDEX_CTIMER0CAPTSEL2    = 2U,
+    kINPUTMUX_INDEX_CTIMER0CAPTSEL3    = 3U,
+    kINPUTMUX_INDEX_CTIMER1CAPTSEL0    = 0U,
+    kINPUTMUX_INDEX_CTIMER1CAPTSEL1    = 1U,
+    kINPUTMUX_INDEX_CTIMER1CAPTSEL2    = 2U,
+    kINPUTMUX_INDEX_CTIMER1CAPTSEL3    = 3U,
+    kINPUTMUX_INDEX_CTIMER2CAPTSEL0    = 0U,
+    kINPUTMUX_INDEX_CTIMER2CAPTSEL1    = 1U,
+    kINPUTMUX_INDEX_CTIMER2CAPTSEL2    = 2U,
+    kINPUTMUX_INDEX_CTIMER2CAPTSEL3    = 3U,
+    kINPUTMUX_INDEX_CTIMER3CAPTSEL0    = 0U,
+    kINPUTMUX_INDEX_CTIMER3CAPTSEL1    = 1U,
+    kINPUTMUX_INDEX_CTIMER3CAPTSEL2    = 2U,
+    kINPUTMUX_INDEX_CTIMER3CAPTSEL3    = 3U,
+    kINPUTMUX_INDEX_CTIMER4CAPTSEL0    = 0U,
+    kINPUTMUX_INDEX_CTIMER4CAPTSEL1    = 1U,
+    kINPUTMUX_INDEX_CTIMER4CAPTSEL2    = 2U,
+    kINPUTMUX_INDEX_CTIMER4CAPTSEL3    = 3U,
+    kINPUTMUX_INDEX_SMARTDMA_TRIGSEL0  = 0U,
+    kINPUTMUX_INDEX_SMARTDMA_TRIGSEL1  = 1U,
+    kINPUTMUX_INDEX_SMARTDMA_TRIGSEL2  = 2U,
+    kINPUTMUX_INDEX_SMARTDMA_TRIGSEL3  = 3U,
+    kINPUTMUX_INDEX_SMARTDMA_TRIGSEL4  = 4U,
+    kINPUTMUX_INDEX_SMARTDMA_TRIGSEL5  = 5U,
+    kINPUTMUX_INDEX_SMARTDMA_TRIGSEL6  = 6U,
+    kINPUTMUX_INDEX_SMARTDMA_TRIGSEL7  = 7U,
+    kINPUTMUX_INDEX_ADC0_TRIGSEL0      = 0U,
+    kINPUTMUX_INDEX_ADC0_TRIGSEL1      = 1U,
+    kINPUTMUX_INDEX_ADC0_TRIGSEL2      = 2U,
+    kINPUTMUX_INDEX_ADC0_TRIGSEL3      = 3U,
+    kINPUTMUX_INDEX_ADC1_TRIGSEL0      = 0U,
+    kINPUTMUX_INDEX_ADC1_TRIGSEL1      = 1U,
+    kINPUTMUX_INDEX_ADC1_TRIGSEL2      = 2U,
+    kINPUTMUX_INDEX_ADC1_TRIGSEL3      = 3U,
+    kINPUTMUX_INDEX_ADC2_TRIGSEL0      = 0U,
+    kINPUTMUX_INDEX_ADC2_TRIGSEL1      = 1U,
+    kINPUTMUX_INDEX_ADC2_TRIGSEL2      = 2U,
+    kINPUTMUX_INDEX_ADC2_TRIGSEL3      = 3U,
+    kINPUTMUX_INDEX_ADC3_TRIGSEL0      = 0U,
+    kINPUTMUX_INDEX_ADC3_TRIGSEL1      = 1U,
+    kINPUTMUX_INDEX_ADC3_TRIGSEL2      = 2U,
+    kINPUTMUX_INDEX_ADC3_TRIGSEL3      = 3U,
+    kINPUTMUX_INDEX_QDC0_ICAPSEL1      = 1U,
+    kINPUTMUX_INDEX_QDC0_ICAPSEL2      = 2U,
+    kINPUTMUX_INDEX_QDC0_ICAPSEL3      = 3U,
+    kINPUTMUX_INDEX_QDC1_ICAPSEL1      = 1U,
+    kINPUTMUX_INDEX_QDC1_ICAPSEL2      = 2U,
+    kINPUTMUX_INDEX_QDC1_ICAPSEL3      = 3U,
+    kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL0 = 0U,
+    kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL1 = 1U,
+    kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL2 = 2U,
+    kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL3 = 3U,
+    kINPUTMUX_INDEX_FLEXPWM1_FAULTSEL0 = 0U,
+    kINPUTMUX_INDEX_FLEXPWM1_FAULTSEL1 = 1U,
+    kINPUTMUX_INDEX_FLEXPWM1_FAULTSEL2 = 2U,
+    kINPUTMUX_INDEX_FLEXPWM1_FAULTSEL3 = 3U,
+    kINPUTMUX_INDEX_AOI0_TRIGSEL0      = 0U,
+    kINPUTMUX_INDEX_AOI0_TRIGSEL1      = 1U,
+    kINPUTMUX_INDEX_AOI0_TRIGSEL2      = 2U,
+    kINPUTMUX_INDEX_AOI0_TRIGSEL3      = 3U,
+    kINPUTMUX_INDEX_AOI0_TRIGSEL4      = 4U,
+    kINPUTMUX_INDEX_AOI0_TRIGSEL5      = 5U,
+    kINPUTMUX_INDEX_AOI0_TRIGSEL6      = 6U,
+    kINPUTMUX_INDEX_AOI0_TRIGSEL7      = 7U,
+    kINPUTMUX_INDEX_AOI0_TRIGSEL8      = 8U,
+    kINPUTMUX_INDEX_AOI0_TRIGSEL9      = 9U,
+    kINPUTMUX_INDEX_AOI0_TRIGSEL10     = 10U,
+    kINPUTMUX_INDEX_AOI0_TRIGSEL11     = 11U,
+    kINPUTMUX_INDEX_AOI0_TRIGSEL12     = 12U,
+    kINPUTMUX_INDEX_AOI0_TRIGSEL13     = 13U,
+    kINPUTMUX_INDEX_AOI0_TRIGSEL14     = 14U,
+    kINPUTMUX_INDEX_AOI0_TRIGSEL15     = 15U,
+    kINPUTMUX_INDEX_AOI1_TRIGSEL0      = 0U,
+    kINPUTMUX_INDEX_AOI1_TRIGSEL1      = 1U,
+    kINPUTMUX_INDEX_AOI1_TRIGSEL2      = 2U,
+    kINPUTMUX_INDEX_AOI1_TRIGSEL3      = 3U,
+    kINPUTMUX_INDEX_AOI1_TRIGSEL4      = 4U,
+    kINPUTMUX_INDEX_AOI1_TRIGSEL5      = 5U,
+    kINPUTMUX_INDEX_AOI1_TRIGSEL6      = 6U,
+    kINPUTMUX_INDEX_AOI1_TRIGSEL7      = 7U,
+    kINPUTMUX_INDEX_AOI1_TRIGSEL8      = 8U,
+    kINPUTMUX_INDEX_AOI1_TRIGSEL9      = 9U,
+    kINPUTMUX_INDEX_AOI1_TRIGSEL10     = 10U,
+    kINPUTMUX_INDEX_AOI1_TRIGSEL11     = 11U,
+    kINPUTMUX_INDEX_AOI1_TRIGSEL12     = 12U,
+    kINPUTMUX_INDEX_AOI1_TRIGSEL13     = 13U,
+    kINPUTMUX_INDEX_AOI1_TRIGSEL14     = 14U,
+    kINPUTMUX_INDEX_AOI1_TRIGSEL15     = 15U,
+    kINPUTMUX_INDEX_EXT_TRIGSEL0       = 0U,
+    kINPUTMUX_INDEX_EXT_TRIGSEL1       = 1U,
+    kINPUTMUX_INDEX_EXT_TRIGSEL2       = 2U,
+    kINPUTMUX_INDEX_EXT_TRIGSEL3       = 3U,
+    kINPUTMUX_INDEX_EXT_TRIGSEL4       = 4U,
+    kINPUTMUX_INDEX_EXT_TRIGSEL6       = 6U,
+    kINPUTMUX_INDEX_EXT_TRIGSEL7       = 7U,
+    kINPUTMUX_INDEX_FLEXIO_TRIGSEL0    = 0U,
+    kINPUTMUX_INDEX_FLEXIO_TRIGSEL1    = 1U,
+    kINPUTMUX_INDEX_FLEXIO_TRIGSEL2    = 2U,
+    kINPUTMUX_INDEX_FLEXIO_TRIGSEL3    = 3U
+} inputmux_index_t;
+
+/*! @brief INPUTMUX connections type */
+typedef enum _inputmux_connection_t
+{
+    /*!< TIMER0 CAPTSEL. */
+    kINPUTMUX_CtimerInp0ToTimer0Captsel                 = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp1ToTimer0Captsel                 = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp2ToTimer0Captsel                 = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp3ToTimer0Captsel                 = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp4ToTimer0Captsel                 = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp5ToTimer0Captsel                 = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp6ToTimer0Captsel                 = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp7ToTimer0Captsel                 = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp8ToTimer0Captsel                 = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp9ToTimer0Captsel                 = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp10ToTimer0Captsel                = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp11ToTimer0Captsel                = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp12ToTimer0Captsel                = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp13ToTimer0Captsel                = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp14ToTimer0Captsel                = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp15ToTimer0Captsel                = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp16ToTimer0Captsel                = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp17ToTimer0Captsel                = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp18ToTimer0Captsel                = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp19ToTimer0Captsel                = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Usb0StartOfFrameToTimer0Captsel           = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToTimer0Captsel                   = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToTimer0Captsel                   = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToTimer0Captsel                   = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToTimer0Captsel                   = 25U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp0ToTimer0Captsel                 = 26U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToTimer0Captsel                 = 27U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp2ToTimer0Captsel                 = 28U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp3ToTimer0Captsel                 = 29U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToTimer0Captsel                    = 30U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToTimer0Captsel                    = 31U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToTimer0Captsel                    = 32U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToTimer0Captsel                  = 33U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToTimer0Captsel                  = 34U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToTimer0Captsel                  = 35U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToTimer0Captsel                  = 36U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToTimer0Captsel                  = 37U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToTimer0Captsel                  = 38U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToTimer0Captsel               = 39U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToTimer0Captsel               = 40U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToTimer0Captsel               = 41U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToTimer0Captsel               = 42U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToTimer0Captsel              = 43U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToTimer0Captsel            = 44U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToTimer0Captsel            = 45U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToTimer0Captsel            = 46U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToTimer0Captsel            = 47U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer0Captsel    = 48U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer0Captsel     = 49U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer0Captsel    = 50U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer0Captsel     = 51U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0EndOfFrameToTimer0Captsel           = 52U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0ReceivedDataWordToTimer0Captsel     = 53U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1EndOfFrameToTimer0Captsel           = 54U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1ReceivedDataWordToTimer0Captsel     = 55U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceivedDataWordToTimer0Captsel    = 56U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0TransmittedDataWordToTimer0Captsel = 57U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceiveLineIdleToTimer0Captsel     = 58U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceivedDataWordToTimer0Captsel    = 59U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1TransmittedDataWordToTimer0Captsel = 60U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceiveLineIdleToTimer0Captsel     = 61U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceivedDataWordToTimer0Captsel    = 62U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2TransmittedDataWordToTimer0Captsel = 63U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceiveLineIdleToTimer0Captsel     = 64U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceivedDataWordToTimer0Captsel    = 65U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3TransmittedDataWordToTimer0Captsel = 66U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceiveLineIdleToTimer0Captsel     = 67U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceivedDataWordToTimer0Captsel    = 68U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4TransmittedDataWordToTimer0Captsel = 69U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceiveLineIdleToTimer0Captsel     = 70U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToTimer0Captsel                   = 71U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToTimer0Captsel                   = 72U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToTimer0Captsel                   = 73U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToTimer0Captsel                   = 74U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp0ToTimer0Captsel                 = 75U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp1ToTimer0Captsel                 = 76U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp2ToTimer0Captsel                 = 77U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp3ToTimer0Captsel                 = 78U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToTimer0Captsel                  = 79U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToTimer0Captsel                  = 80U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToTimer0Captsel                  = 81U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToTimer0Captsel                  = 82U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToTimer0Captsel                  = 83U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToTimer0Captsel                  = 84U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToTimer0Captsel               = 85U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToTimer0Captsel               = 86U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToTimer0Captsel               = 87U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToTimer0Captsel               = 88U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToTimer0Captsel              = 89U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToTimer0Captsel            = 90U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToTimer0Captsel            = 91U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToTimer0Captsel            = 92U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToTimer0Captsel            = 93U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer0Captsel    = 94U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer0Captsel     = 95U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer0Captsel    = 96U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer0Captsel     = 97U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceivedDataWordToTimer0Captsel    = 98U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5TransmittedDataWordToTimer0Captsel = 99U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceiveLineIdleToTimer0Captsel     = 100U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp0ToTimer0Captsel                 = 105U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp1ToTimer0Captsel                 = 106U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp2ToTimer0Captsel                 = 107U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp3ToTimer0Captsel                 = 108U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp0ToTimer0Captsel                 = 109U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp1ToTimer0Captsel                 = 110U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp2ToTimer0Captsel                 = 111U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp3ToTimer0Captsel                 = 112U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+
+    /*!< TIMER1 CAPTSEL. */
+    kINPUTMUX_CtimerInp0ToTimer1Captsel                 = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp1ToTimer1Captsel                 = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp2ToTimer1Captsel                 = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp3ToTimer1Captsel                 = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp4ToTimer1Captsel                 = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp5ToTimer1Captsel                 = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp6ToTimer1Captsel                 = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp7ToTimer1Captsel                 = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp8ToTimer1Captsel                 = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp9ToTimer1Captsel                 = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp10ToTimer1Captsel                = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp11ToTimer1Captsel                = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp12ToTimer1Captsel                = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp13ToTimer1Captsel                = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp14ToTimer1Captsel                = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp15ToTimer1Captsel                = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp16ToTimer1Captsel                = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp17ToTimer1Captsel                = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp18ToTimer1Captsel                = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp19ToTimer1Captsel                = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Usb0StartOfFrameToTimer1Captsel           = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToTimer1Captsel                   = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToTimer1Captsel                   = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToTimer1Captsel                   = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToTimer1Captsel                   = 25U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp0ToTimer1Captsel                 = 26U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToTimer1Captsel                 = 27U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp2ToTimer1Captsel                 = 28U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp3ToTimer1Captsel                 = 29U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToTimer1Captsel                    = 30U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToTimer1Captsel                    = 31U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToTimer1Captsel                    = 32U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToTimer1Captsel                  = 33U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToTimer1Captsel                  = 34U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToTimer1Captsel                  = 35U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToTimer1Captsel                  = 36U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToTimer1Captsel                  = 37U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToTimer1Captsel                  = 38U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToTimer1Captsel               = 39U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToTimer1Captsel               = 40U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToTimer1Captsel               = 41U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToTimer1Captsel               = 42U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToTimer1Captsel              = 43U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToTimer1Captsel            = 44U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToTimer1Captsel            = 45U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToTimer1Captsel            = 46U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToTimer1Captsel            = 47U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer1Captsel    = 48U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer1Captsel     = 49U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer1Captsel    = 50U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer1Captsel     = 51U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0EndOfFrameToTimer1Captsel           = 52U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0ReceivedDataWordToTimer1Captsel     = 53U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1EndOfFrameToTimer1Captsel           = 54U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1ReceivedDataWordToTimer1Captsel     = 55U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceivedDataWordToTimer1Captsel    = 56U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0TransmittedDataWordToTimer1Captsel = 57U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceiveLineIdleToTimer1Captsel     = 58U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceivedDataWordToTimer1Captsel    = 59U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1TransmittedDataWordToTimer1Captsel = 60U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceiveLineIdleToTimer1Captsel     = 61U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceivedDataWordToTimer1Captsel    = 62U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2TransmittedDataWordToTimer1Captsel = 63U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceiveLineIdleToTimer1Captsel     = 64U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceivedDataWordToTimer1Captsel    = 65U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3TransmittedDataWordToTimer1Captsel = 66U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceiveLineIdleToTimer1Captsel     = 67U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceivedDataWordToTimer1Captsel    = 68U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4TransmittedDataWordToTimer1Captsel = 69U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceiveLineIdleToTimer1Captsel     = 70U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToTimer1Captsel                   = 71U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToTimer1Captsel                   = 72U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToTimer1Captsel                   = 73U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToTimer1Captsel                   = 74U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp0ToTimer1Captsel                 = 75U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp1ToTimer1Captsel                 = 76U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp2ToTimer1Captsel                 = 77U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp3ToTimer1Captsel                 = 78U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToTimer1Captsel                  = 79U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToTimer1Captsel                  = 80U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToTimer1Captsel                  = 81U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToTimer1Captsel                  = 82U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToTimer1Captsel                  = 83U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToTimer1Captsel                  = 84U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToTimer1Captsel               = 85U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToTimer1Captsel               = 86U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToTimer1Captsel               = 87U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToTimer1Captsel               = 88U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToTimer1Captsel              = 89U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToTimer1Captsel            = 90U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToTimer1Captsel            = 91U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToTimer1Captsel            = 92U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToTimer1Captsel            = 93U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer1Captsel    = 94U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer1Captsel     = 95U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer1Captsel    = 96U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer1Captsel     = 97U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceivedDataWordToTimer1Captsel    = 98U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5TransmittedDataWordToTimer1Captsel = 99U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceiveLineIdleToTimer1Captsel     = 100U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp0ToTimer1Captsel                 = 105U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp1ToTimer1Captsel                 = 106U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp2ToTimer1Captsel                 = 107U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp3ToTimer1Captsel                 = 108U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp0ToTimer1Captsel                 = 109U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp1ToTimer1Captsel                 = 110U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp2ToTimer1Captsel                 = 111U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp3ToTimer1Captsel                 = 112U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+
+    /*!< TIMER2 CAPTSEL. */
+    kINPUTMUX_CtimerInp0ToTimer2Captsel                 = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp1ToTimer2Captsel                 = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp2ToTimer2Captsel                 = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp3ToTimer2Captsel                 = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp4ToTimer2Captsel                 = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp5ToTimer2Captsel                 = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp6ToTimer2Captsel                 = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp7ToTimer2Captsel                 = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp8ToTimer2Captsel                 = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp9ToTimer2Captsel                 = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp10ToTimer2Captsel                = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp11ToTimer2Captsel                = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp12ToTimer2Captsel                = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp13ToTimer2Captsel                = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp14ToTimer2Captsel                = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp15ToTimer2Captsel                = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp16ToTimer2Captsel                = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp17ToTimer2Captsel                = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp18ToTimer2Captsel                = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp19ToTimer2Captsel                = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Usb0StartOfFrameToTimer2Captsel           = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToTimer2Captsel                   = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToTimer2Captsel                   = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToTimer2Captsel                   = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToTimer2Captsel                   = 25U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp0ToTimer2Captsel                 = 26U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToTimer2Captsel                 = 27U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp2ToTimer2Captsel                 = 28U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp3ToTimer2Captsel                 = 29U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToTimer2Captsel                    = 30U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToTimer2Captsel                    = 31U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToTimer2Captsel                    = 32U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToTimer2Captsel                  = 33U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToTimer2Captsel                  = 34U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToTimer2Captsel                  = 35U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToTimer2Captsel                  = 36U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToTimer2Captsel                  = 37U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToTimer2Captsel                  = 38U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToTimer2Captsel               = 39U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToTimer2Captsel               = 40U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToTimer2Captsel               = 41U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToTimer2Captsel               = 42U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToTimer2Captsel              = 43U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToTimer2Captsel            = 44U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToTimer2Captsel            = 45U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToTimer2Captsel            = 46U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToTimer2Captsel            = 47U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer2Captsel    = 48U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer2Captsel     = 49U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer2Captsel    = 50U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer2Captsel     = 51U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0EndOfFrameToTimer2Captsel           = 52U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0ReceivedDataWordToTimer2Captsel     = 53U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1EndOfFrameToTimer2Captsel           = 54U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1ReceivedDataWordToTimer2Captsel     = 55U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceivedDataWordToTimer2Captsel    = 56U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0TransmittedDataWordToTimer2Captsel = 57U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceiveLineIdleToTimer2Captsel     = 58U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceivedDataWordToTimer2Captsel    = 59U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1TransmittedDataWordToTimer2Captsel = 60U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceiveLineIdleToTimer2Captsel     = 61U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceivedDataWordToTimer2Captsel    = 62U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2TransmittedDataWordToTimer2Captsel = 63U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceiveLineIdleToTimer2Captsel     = 64U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceivedDataWordToTimer2Captsel    = 65U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3TransmittedDataWordToTimer2Captsel = 66U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceiveLineIdleToTimer2Captsel     = 67U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceivedDataWordToTimer2Captsel    = 68U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4TransmittedDataWordToTimer2Captsel = 69U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceiveLineIdleToTimer2Captsel     = 70U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToTimer2Captsel                   = 71U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToTimer2Captsel                   = 72U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToTimer2Captsel                   = 73U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToTimer2Captsel                   = 74U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp0ToTimer2Captsel                 = 75U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp1ToTimer2Captsel                 = 76U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp2ToTimer2Captsel                 = 77U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp3ToTimer2Captsel                 = 78U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToTimer2Captsel                  = 79U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToTimer2Captsel                  = 80U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToTimer2Captsel                  = 81U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToTimer2Captsel                  = 82U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToTimer2Captsel                  = 83U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToTimer2Captsel                  = 84U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToTimer2Captsel               = 85U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToTimer2Captsel               = 86U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToTimer2Captsel               = 87U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToTimer2Captsel               = 88U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToTimer2Captsel              = 89U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToTimer2Captsel            = 90U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToTimer2Captsel            = 91U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToTimer2Captsel            = 92U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToTimer2Captsel            = 93U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer2Captsel    = 94U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer2Captsel     = 95U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer2Captsel    = 96U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer2Captsel     = 97U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceivedDataWordToTimer2Captsel    = 98U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5TransmittedDataWordToTimer2Captsel = 99U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceiveLineIdleToTimer2Captsel     = 100U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp0ToTimer2Captsel                 = 105U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp1ToTimer2Captsel                 = 106U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp2ToTimer2Captsel                 = 107U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp3ToTimer2Captsel                 = 108U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp0ToTimer2Captsel                 = 109U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp1ToTimer2Captsel                 = 110U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp2ToTimer2Captsel                 = 111U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp3ToTimer2Captsel                 = 112U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+
+    /*!< TIMER3 CAPTSEL. */
+    kINPUTMUX_CtimerInp0ToTimer3Captsel                 = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp1ToTimer3Captsel                 = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp2ToTimer3Captsel                 = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp3ToTimer3Captsel                 = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp4ToTimer3Captsel                 = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp5ToTimer3Captsel                 = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp6ToTimer3Captsel                 = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp7ToTimer3Captsel                 = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp8ToTimer3Captsel                 = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp9ToTimer3Captsel                 = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp10ToTimer3Captsel                = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp11ToTimer3Captsel                = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp12ToTimer3Captsel                = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp13ToTimer3Captsel                = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp14ToTimer3Captsel                = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp15ToTimer3Captsel                = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp16ToTimer3Captsel                = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp17ToTimer3Captsel                = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp18ToTimer3Captsel                = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp19ToTimer3Captsel                = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Usb0StartOfFrameToTimer3Captsel           = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToTimer3Captsel                   = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToTimer3Captsel                   = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToTimer3Captsel                   = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToTimer3Captsel                   = 25U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp0ToTimer3Captsel                 = 26U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToTimer3Captsel                 = 27U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp2ToTimer3Captsel                 = 28U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp3ToTimer3Captsel                 = 29U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToTimer3Captsel                    = 30U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToTimer3Captsel                    = 31U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToTimer3Captsel                    = 32U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToTimer3Captsel                  = 33U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToTimer3Captsel                  = 34U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToTimer3Captsel                  = 35U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToTimer3Captsel                  = 36U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToTimer3Captsel                  = 37U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToTimer3Captsel                  = 38U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToTimer3Captsel               = 39U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToTimer3Captsel               = 40U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToTimer3Captsel               = 41U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToTimer3Captsel               = 42U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToTimer3Captsel              = 43U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToTimer3Captsel            = 44U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToTimer3Captsel            = 45U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToTimer3Captsel            = 46U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToTimer3Captsel            = 47U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer3Captsel    = 48U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer3Captsel     = 49U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer3Captsel    = 50U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer3Captsel     = 51U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0EndOfFrameToTimer3Captsel           = 52U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0ReceivedDataWordToTimer3Captsel     = 53U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1EndOfFrameToTimer3Captsel           = 54U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1ReceivedDataWordToTimer3Captsel     = 55U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceivedDataWordToTimer3Captsel    = 56U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0TransmittedDataWordToTimer3Captsel = 57U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceiveLineIdleToTimer3Captsel     = 58U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceivedDataWordToTimer3Captsel    = 59U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1TransmittedDataWordToTimer3Captsel = 60U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceiveLineIdleToTimer3Captsel     = 61U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceivedDataWordToTimer3Captsel    = 62U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2TransmittedDataWordToTimer3Captsel = 63U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceiveLineIdleToTimer3Captsel     = 64U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceivedDataWordToTimer3Captsel    = 65U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3TransmittedDataWordToTimer3Captsel = 66U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceiveLineIdleToTimer3Captsel     = 67U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceivedDataWordToTimer3Captsel    = 68U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4TransmittedDataWordToTimer3Captsel = 69U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceiveLineIdleToTimer3Captsel     = 70U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToTimer3Captsel                   = 71U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToTimer3Captsel                   = 72U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToTimer3Captsel                   = 73U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToTimer3Captsel                   = 74U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp0ToTimer3Captsel                 = 75U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp1ToTimer3Captsel                 = 76U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp2ToTimer3Captsel                 = 77U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp3ToTimer3Captsel                 = 78U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToTimer3Captsel                  = 79U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToTimer3Captsel                  = 80U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToTimer3Captsel                  = 81U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToTimer3Captsel                  = 82U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToTimer3Captsel                  = 83U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToTimer3Captsel                  = 84U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToTimer3Captsel               = 85U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToTimer3Captsel               = 86U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToTimer3Captsel               = 87U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToTimer3Captsel               = 88U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToTimer3Captsel              = 89U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToTimer3Captsel            = 90U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToTimer3Captsel            = 91U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToTimer3Captsel            = 92U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToTimer3Captsel            = 93U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer3Captsel    = 94U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer3Captsel     = 95U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer3Captsel    = 96U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer3Captsel     = 97U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceivedDataWordToTimer3Captsel    = 98U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5TransmittedDataWordToTimer3Captsel = 99U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceiveLineIdleToTimer3Captsel     = 100U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp0ToTimer3Captsel                 = 105U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp1ToTimer3Captsel                 = 106U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp2ToTimer3Captsel                 = 107U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp3ToTimer3Captsel                 = 108U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp0ToTimer3Captsel                 = 109U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp1ToTimer3Captsel                 = 110U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp2ToTimer3Captsel                 = 111U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp3ToTimer3Captsel                 = 112U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToTimer3Captsel                    = 113U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToTimer3Captsel                    = 114U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToTimer3Captsel                    = 115U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToTimer3Captsel                    = 116U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToTimer3Captsel                    = 117U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToTimer3Captsel                    = 118U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToTimer3Captsel                    = 119U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToTimer3Captsel                    = 120U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToTimer3Captsel                    = 121U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToTimer3Captsel                    = 122U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToTimer3Captsel                   = 123U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToTimer3Captsel                   = 124U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+
+    /*!< TIMER4 CAPTSEL. */
+    kINPUTMUX_CtimerInp0ToTimer4Captsel                 = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp1ToTimer4Captsel                 = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp2ToTimer4Captsel                 = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp3ToTimer4Captsel                 = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp4ToTimer4Captsel                 = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp5ToTimer4Captsel                 = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp6ToTimer4Captsel                 = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp7ToTimer4Captsel                 = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp8ToTimer4Captsel                 = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp9ToTimer4Captsel                 = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp10ToTimer4Captsel                = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp11ToTimer4Captsel                = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp12ToTimer4Captsel                = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp13ToTimer4Captsel                = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp14ToTimer4Captsel                = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp15ToTimer4Captsel                = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp16ToTimer4Captsel                = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp17ToTimer4Captsel                = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp18ToTimer4Captsel                = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp19ToTimer4Captsel                = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Usb0StartOfFrameToTimer4Captsel           = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToTimer4Captsel                   = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToTimer4Captsel                   = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToTimer4Captsel                   = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToTimer4Captsel                   = 25U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp0ToTimer4Captsel                 = 26U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToTimer4Captsel                 = 27U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp2ToTimer4Captsel                 = 28U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp3ToTimer4Captsel                 = 29U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToTimer4Captsel                    = 30U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToTimer4Captsel                    = 31U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToTimer4Captsel                    = 32U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToTimer4Captsel                  = 33U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToTimer4Captsel                  = 34U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToTimer4Captsel                  = 35U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToTimer4Captsel                  = 36U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToTimer4Captsel                  = 37U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToTimer4Captsel                  = 38U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToTimer4Captsel               = 39U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToTimer4Captsel               = 40U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToTimer4Captsel               = 41U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToTimer4Captsel               = 42U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToTimer4Captsel              = 43U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToTimer4Captsel            = 44U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToTimer4Captsel            = 45U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToTimer4Captsel            = 46U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToTimer4Captsel            = 47U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer4Captsel    = 48U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer4Captsel     = 49U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer4Captsel    = 50U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer4Captsel     = 51U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0EndOfFrameToTimer4Captsel           = 52U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0ReceivedDataWordToTimer4Captsel     = 53U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1EndOfFrameToTimer4Captsel           = 54U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1ReceivedDataWordToTimer4Captsel     = 55U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceivedDataWordToTimer4Captsel    = 56U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0TransmittedDataWordToTimer4Captsel = 57U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceiveLineIdleToTimer4Captsel     = 58U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceivedDataWordToTimer4Captsel    = 59U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1TransmittedDataWordToTimer4Captsel = 60U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceiveLineIdleToTimer4Captsel     = 61U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceivedDataWordToTimer4Captsel    = 62U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2TransmittedDataWordToTimer4Captsel = 63U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceiveLineIdleToTimer4Captsel     = 64U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceivedDataWordToTimer4Captsel    = 65U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3TransmittedDataWordToTimer4Captsel = 66U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceiveLineIdleToTimer4Captsel     = 67U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceivedDataWordToTimer4Captsel    = 68U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4TransmittedDataWordToTimer4Captsel = 69U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceiveLineIdleToTimer4Captsel     = 70U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToTimer4Captsel                   = 71U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToTimer4Captsel                   = 72U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToTimer4Captsel                   = 73U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToTimer4Captsel                   = 74U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp0ToTimer4Captsel                 = 75U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp1ToTimer4Captsel                 = 76U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp2ToTimer4Captsel                 = 77U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp3ToTimer4Captsel                 = 78U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToTimer4Captsel                  = 79U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToTimer4Captsel                  = 80U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToTimer4Captsel                  = 81U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToTimer4Captsel                  = 82U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToTimer4Captsel                  = 83U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToTimer4Captsel                  = 84U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToTimer4Captsel               = 85U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToTimer4Captsel               = 86U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToTimer4Captsel               = 87U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToTimer4Captsel               = 88U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToTimer4Captsel              = 89U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToTimer4Captsel            = 90U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToTimer4Captsel            = 91U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToTimer4Captsel            = 92U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToTimer4Captsel            = 93U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer4Captsel    = 94U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer4Captsel     = 95U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer4Captsel    = 96U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer4Captsel     = 97U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceivedDataWordToTimer4Captsel    = 98U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5TransmittedDataWordToTimer4Captsel = 99U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceiveLineIdleToTimer4Captsel     = 100U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp0ToTimer4Captsel                 = 105U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp1ToTimer4Captsel                 = 106U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp2ToTimer4Captsel                 = 107U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp3ToTimer4Captsel                 = 108U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp0ToTimer4Captsel                 = 109U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp1ToTimer4Captsel                 = 110U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp2ToTimer4Captsel                 = 111U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp3ToTimer4Captsel                 = 112U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToTimer4Captsel                    = 113U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToTimer4Captsel                    = 114U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToTimer4Captsel                    = 115U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToTimer4Captsel                    = 116U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToTimer4Captsel                    = 117U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToTimer4Captsel                    = 118U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToTimer4Captsel                    = 119U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToTimer4Captsel                    = 120U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToTimer4Captsel                    = 121U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToTimer4Captsel                    = 122U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToTimer4Captsel                   = 123U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToTimer4Captsel                   = 124U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+
+    /*!< TIMER0 Trigger. */
+    kINPUTMUX_CtimerInp0ToTimer0Trigger                 = 1U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp1ToTimer0Trigger                 = 2U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp2ToTimer0Trigger                 = 3U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp3ToTimer0Trigger                 = 4U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp4ToTimer0Trigger                 = 5U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp5ToTimer0Trigger                 = 6U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp6ToTimer0Trigger                 = 7U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp7ToTimer0Trigger                 = 8U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp8ToTimer0Trigger                 = 9U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp9ToTimer0Trigger                 = 10U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp10ToTimer0Trigger                = 11U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp11ToTimer0Trigger                = 12U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp12ToTimer0Trigger                = 13U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp13ToTimer0Trigger                = 14U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp14ToTimer0Trigger                = 15U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp15ToTimer0Trigger                = 16U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp16ToTimer0Trigger                = 17U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp17ToTimer0Trigger                = 18U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp18ToTimer0Trigger                = 19U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp19ToTimer0Trigger                = 20U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Usb0StartOfFrameToTimer0Trigger           = 21U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToTimer0Trigger                   = 22U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToTimer0Trigger                   = 23U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToTimer0Trigger                   = 24U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToTimer0Trigger                   = 25U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp0ToTimer0Trigger                 = 26U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToTimer0Trigger                 = 27U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp2ToTimer0Trigger                 = 28U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp3ToTimer0Trigger                 = 29U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToTimer0Trigger                    = 30U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToTimer0Trigger                    = 31U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToTimer0Trigger                    = 32U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToTimer0Trigger                  = 33U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToTimer0Trigger                  = 34U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToTimer0Trigger                  = 35U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToTimer0Trigger                  = 36U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToTimer0Trigger                  = 37U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToTimer0Trigger                  = 38U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToTimer0Trigger               = 39U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToTimer0Trigger               = 40U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToTimer0Trigger               = 41U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToTimer0Trigger               = 42U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToTimer0Trigger              = 43U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToTimer0Trigger            = 44U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToTimer0Trigger            = 45U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToTimer0Trigger            = 46U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToTimer0Trigger            = 47U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer0Trigger    = 48U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer0Trigger     = 49U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer0Trigger    = 50U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer0Trigger     = 51U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0EndOfFrameToTimer0Trigger           = 52U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0ReceivedDataWordToTimer0Trigger     = 53U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1EndOfFrameToTimer0Trigger           = 54U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1ReceivedDataWordToTimer0Trigger     = 55U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceivedDataWordToTimer0Trigger    = 56U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0TransmittedDataWordToTimer0Trigger = 57U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceiveLineIdleToTimer0Trigger     = 58U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceivedDataWordToTimer0Trigger    = 59U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1TransmittedDataWordToTimer0Trigger = 60U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceiveLineIdleToTimer0Trigger     = 61U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceivedDataWordToTimer0Trigger    = 62U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2TransmittedDataWordToTimer0Trigger = 63U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceiveLineIdleToTimer0Trigger     = 64U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceivedDataWordToTimer0Trigger    = 65U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3TransmittedDataWordToTimer0Trigger = 66U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceiveLineIdleToTimer0Trigger     = 67U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceivedDataWordToTimer0Trigger    = 68U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4TransmittedDataWordToTimer0Trigger = 69U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceiveLineIdleToTimer0Trigger     = 70U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToTimer0Trigger                   = 71U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToTimer0Trigger                   = 72U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToTimer0Trigger                   = 73U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToTimer0Trigger                   = 74U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp0ToTimer0Trigger                 = 75U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp1ToTimer0Trigger                 = 76U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp2ToTimer0Trigger                 = 77U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp3ToTimer0Trigger                 = 78U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToTimer0Trigger                  = 79U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToTimer0Trigger                  = 80U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToTimer0Trigger                  = 81U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToTimer0Trigger                  = 82U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToTimer0Trigger                  = 83U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToTimer0Trigger                  = 84U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToTimer0Trigger               = 85U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToTimer0Trigger               = 86U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToTimer0Trigger               = 87U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToTimer0Trigger               = 88U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToTimer0Trigger              = 89U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToTimer0Trigger            = 90U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToTimer0Trigger            = 91U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToTimer0Trigger            = 92U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToTimer0Trigger            = 93U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer0Trigger    = 94U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer0Trigger     = 95U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer0Trigger    = 96U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer0Trigger     = 97U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceivedDataWordToTimer0Trigger    = 98U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5TransmittedDataWordToTimer0Trigger = 99U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceiveLineIdleToTimer0Trigger     = 100U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp0ToTimer0Trigger                 = 105U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp1ToTimer0Trigger                 = 106U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp2ToTimer0Trigger                 = 107U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp3ToTimer0Trigger                 = 108U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp0ToTimer0Trigger                 = 109U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp1ToTimer0Trigger                 = 110U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp2ToTimer0Trigger                 = 111U + (TIMER0TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp3ToTimer0Trigger                 = 112U + (TIMER0TRIGIN << PMUX_SHIFT),
+
+    /*!< TIMER1 Trigger. */
+    kINPUTMUX_CtimerInp0ToTimer1Trigger                 = 1U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp1ToTimer1Trigger                 = 2U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp2ToTimer1Trigger                 = 3U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp3ToTimer1Trigger                 = 4U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp4ToTimer1Trigger                 = 5U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp5ToTimer1Trigger                 = 6U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp6ToTimer1Trigger                 = 7U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp7ToTimer1Trigger                 = 8U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp8ToTimer1Trigger                 = 9U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp9ToTimer1Trigger                 = 10U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp10ToTimer1Trigger                = 11U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp11ToTimer1Trigger                = 12U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp12ToTimer1Trigger                = 13U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp13ToTimer1Trigger                = 14U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp14ToTimer1Trigger                = 15U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp15ToTimer1Trigger                = 16U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp16ToTimer1Trigger                = 17U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp17ToTimer1Trigger                = 18U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp18ToTimer1Trigger                = 19U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp19ToTimer1Trigger                = 20U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Usb0StartOfFrameToTimer1Trigger           = 21U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToTimer1Trigger                   = 22U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToTimer1Trigger                   = 23U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToTimer1Trigger                   = 24U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToTimer1Trigger                   = 25U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp0ToTimer1Trigger                 = 26U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToTimer1Trigger                 = 27U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp2ToTimer1Trigger                 = 28U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp3ToTimer1Trigger                 = 29U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToTimer1Trigger                    = 30U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToTimer1Trigger                    = 31U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToTimer1Trigger                    = 32U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToTimer1Trigger                  = 33U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToTimer1Trigger                  = 34U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToTimer1Trigger                  = 35U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToTimer1Trigger                  = 36U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToTimer1Trigger                  = 37U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToTimer1Trigger                  = 38U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToTimer1Trigger               = 39U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToTimer1Trigger               = 40U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToTimer1Trigger               = 41U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToTimer1Trigger               = 42U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToTimer1Trigger              = 43U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToTimer1Trigger            = 44U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToTimer1Trigger            = 45U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToTimer1Trigger            = 46U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToTimer1Trigger            = 47U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer1Trigger    = 48U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer1Trigger     = 49U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer1Trigger    = 50U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer1Trigger     = 51U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0EndOfFrameToTimer1Trigger           = 52U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0ReceivedDataWordToTimer1Trigger     = 53U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1EndOfFrameToTimer1Trigger           = 54U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1ReceivedDataWordToTimer1Trigger     = 55U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceivedDataWordToTimer1Trigger    = 56U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0TransmittedDataWordToTimer1Trigger = 57U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceiveLineIdleToTimer1Trigger     = 58U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceivedDataWordToTimer1Trigger    = 59U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1TransmittedDataWordToTimer1Trigger = 60U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceiveLineIdleToTimer1Trigger     = 61U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceivedDataWordToTimer1Trigger    = 62U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2TransmittedDataWordToTimer1Trigger = 63U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceiveLineIdleToTimer1Trigger     = 64U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceivedDataWordToTimer1Trigger    = 65U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3TransmittedDataWordToTimer1Trigger = 66U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceiveLineIdleToTimer1Trigger     = 67U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceivedDataWordToTimer1Trigger    = 68U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4TransmittedDataWordToTimer1Trigger = 69U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceiveLineIdleToTimer1Trigger     = 70U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToTimer1Trigger                   = 71U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToTimer1Trigger                   = 72U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToTimer1Trigger                   = 73U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToTimer1Trigger                   = 74U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp0ToTimer1Trigger                 = 75U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp1ToTimer1Trigger                 = 76U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp2ToTimer1Trigger                 = 77U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp3ToTimer1Trigger                 = 78U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToTimer1Trigger                  = 79U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToTimer1Trigger                  = 80U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToTimer1Trigger                  = 81U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToTimer1Trigger                  = 82U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToTimer1Trigger                  = 83U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToTimer1Trigger                  = 84U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToTimer1Trigger               = 85U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToTimer1Trigger               = 86U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToTimer1Trigger               = 87U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToTimer1Trigger               = 88U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToTimer1Trigger              = 89U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToTimer1Trigger            = 90U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToTimer1Trigger            = 91U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToTimer1Trigger            = 92U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToTimer1Trigger            = 93U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer1Trigger    = 94U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer1Trigger     = 95U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer1Trigger    = 96U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer1Trigger     = 97U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceivedDataWordToTimer1Trigger    = 98U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5TransmittedDataWordToTimer1Trigger = 99U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceiveLineIdleToTimer1Trigger     = 100U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp0ToTimer1Trigger                 = 105U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp1ToTimer1Trigger                 = 106U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp2ToTimer1Trigger                 = 107U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp3ToTimer1Trigger                 = 108U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp0ToTimer1Trigger                 = 109U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp1ToTimer1Trigger                 = 110U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp2ToTimer1Trigger                 = 111U + (TIMER1TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp3ToTimer1Trigger                 = 112U + (TIMER1TRIGIN << PMUX_SHIFT),
+
+    /*!< TIMER2 Trigger. */
+    kINPUTMUX_CtimerInp0ToTimer2Trigger                 = 1U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp1ToTimer2Trigger                 = 2U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp2ToTimer2Trigger                 = 3U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp3ToTimer2Trigger                 = 4U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp4ToTimer2Trigger                 = 5U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp5ToTimer2Trigger                 = 6U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp6ToTimer2Trigger                 = 7U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp7ToTimer2Trigger                 = 8U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp8ToTimer2Trigger                 = 9U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp9ToTimer2Trigger                 = 10U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp10ToTimer2Trigger                = 11U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp11ToTimer2Trigger                = 12U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp12ToTimer2Trigger                = 13U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp13ToTimer2Trigger                = 14U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp14ToTimer2Trigger                = 15U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp15ToTimer2Trigger                = 16U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp16ToTimer2Trigger                = 17U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp17ToTimer2Trigger                = 18U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp18ToTimer2Trigger                = 19U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp19ToTimer2Trigger                = 20U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Usb0StartOfFrameToTimer2Trigger           = 21U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToTimer2Trigger                   = 22U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToTimer2Trigger                   = 23U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToTimer2Trigger                   = 24U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToTimer2Trigger                   = 25U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp0ToTimer2Trigger                 = 26U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToTimer2Trigger                 = 27U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp2ToTimer2Trigger                 = 28U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp3ToTimer2Trigger                 = 29U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToTimer2Trigger                    = 30U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToTimer2Trigger                    = 31U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToTimer2Trigger                    = 32U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToTimer2Trigger                  = 33U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToTimer2Trigger                  = 34U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToTimer2Trigger                  = 35U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToTimer2Trigger                  = 36U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToTimer2Trigger                  = 37U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToTimer2Trigger                  = 38U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToTimer2Trigger               = 39U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToTimer2Trigger               = 40U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToTimer2Trigger               = 41U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToTimer2Trigger               = 42U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToTimer2Trigger              = 43U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToTimer2Trigger            = 44U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToTimer2Trigger            = 45U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToTimer2Trigger            = 46U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToTimer2Trigger            = 47U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer2Trigger    = 48U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer2Trigger     = 49U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer2Trigger    = 50U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer2Trigger     = 51U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0EndOfFrameToTimer2Trigger           = 52U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0ReceivedDataWordToTimer2Trigger     = 53U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1EndOfFrameToTimer2Trigger           = 54U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1ReceivedDataWordToTimer2Trigger     = 55U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceivedDataWordToTimer2Trigger    = 56U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0TransmittedDataWordToTimer2Trigger = 57U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceiveLineIdleToTimer2Trigger     = 58U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceivedDataWordToTimer2Trigger    = 59U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1TransmittedDataWordToTimer2Trigger = 60U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceiveLineIdleToTimer2Trigger     = 61U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceivedDataWordToTimer2Trigger    = 62U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2TransmittedDataWordToTimer2Trigger = 63U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceiveLineIdleToTimer2Trigger     = 64U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceivedDataWordToTimer2Trigger    = 65U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3TransmittedDataWordToTimer2Trigger = 66U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceiveLineIdleToTimer2Trigger     = 67U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceivedDataWordToTimer2Trigger    = 68U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4TransmittedDataWordToTimer2Trigger = 69U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceiveLineIdleToTimer2Trigger     = 70U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToTimer2Trigger                   = 71U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToTimer2Trigger                   = 72U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToTimer2Trigger                   = 73U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToTimer2Trigger                   = 74U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp0ToTimer2Trigger                 = 75U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp1ToTimer2Trigger                 = 76U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp2ToTimer2Trigger                 = 77U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp3ToTimer2Trigger                 = 78U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToTimer2Trigger                  = 79U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToTimer2Trigger                  = 80U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToTimer2Trigger                  = 81U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToTimer2Trigger                  = 82U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToTimer2Trigger                  = 83U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToTimer2Trigger                  = 84U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToTimer2Trigger               = 85U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToTimer2Trigger               = 86U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToTimer2Trigger               = 87U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToTimer2Trigger               = 88U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToTimer2Trigger              = 89U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToTimer2Trigger            = 90U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToTimer2Trigger            = 91U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToTimer2Trigger            = 92U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToTimer2Trigger            = 93U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer2Trigger    = 94U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer2Trigger     = 95U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer2Trigger    = 96U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer2Trigger     = 97U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceivedDataWordToTimer2Trigger    = 98U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5TransmittedDataWordToTimer2Trigger = 99U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceiveLineIdleToTimer2Trigger     = 100U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp0ToTimer2Trigger                 = 105U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp1ToTimer2Trigger                 = 106U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp2ToTimer2Trigger                 = 107U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp3ToTimer2Trigger                 = 108U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp0ToTimer2Trigger                 = 109U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp1ToTimer2Trigger                 = 110U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp2ToTimer2Trigger                 = 111U + (TIMER2TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp3ToTimer2Trigger                 = 112U + (TIMER2TRIGIN << PMUX_SHIFT),
+
+    /*!< TIMER3 Trigger. */
+    kINPUTMUX_CtimerInp0ToTimer3Trigger                 = 1U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp1ToTimer3Trigger                 = 2U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp2ToTimer3Trigger                 = 3U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp3ToTimer3Trigger                 = 4U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp4ToTimer3Trigger                 = 5U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp5ToTimer3Trigger                 = 6U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp6ToTimer3Trigger                 = 7U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp7ToTimer3Trigger                 = 8U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp8ToTimer3Trigger                 = 9U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp9ToTimer3Trigger                 = 10U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp10ToTimer3Trigger                = 11U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp11ToTimer3Trigger                = 12U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp12ToTimer3Trigger                = 13U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp13ToTimer3Trigger                = 14U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp14ToTimer3Trigger                = 15U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp15ToTimer3Trigger                = 16U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp16ToTimer3Trigger                = 17U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp17ToTimer3Trigger                = 18U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp18ToTimer3Trigger                = 19U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp19ToTimer3Trigger                = 20U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Usb0StartOfFrameToTimer3Trigger           = 21U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToTimer3Trigger                   = 22U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToTimer3Trigger                   = 23U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToTimer3Trigger                   = 24U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToTimer3Trigger                   = 25U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp0ToTimer3Trigger                 = 26U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToTimer3Trigger                 = 27U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp2ToTimer3Trigger                 = 28U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp3ToTimer3Trigger                 = 29U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToTimer3Trigger                    = 30U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToTimer3Trigger                    = 31U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToTimer3Trigger                    = 32U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToTimer3Trigger                  = 33U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToTimer3Trigger                  = 34U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToTimer3Trigger                  = 35U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToTimer3Trigger                  = 36U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToTimer3Trigger                  = 37U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToTimer3Trigger                  = 38U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToTimer3Trigger               = 39U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToTimer3Trigger               = 40U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToTimer3Trigger               = 41U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToTimer3Trigger               = 42U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToTimer3Trigger              = 43U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToTimer3Trigger            = 44U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToTimer3Trigger            = 45U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToTimer3Trigger            = 46U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToTimer3Trigger            = 47U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer3Trigger    = 48U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer3Trigger     = 49U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer3Trigger    = 50U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer3Trigger     = 51U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0EndOfFrameToTimer3Trigger           = 52U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0ReceivedDataWordToTimer3Trigger     = 53U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1EndOfFrameToTimer3Trigger           = 54U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1ReceivedDataWordToTimer3Trigger     = 55U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceivedDataWordToTimer3Trigger    = 56U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0TransmittedDataWordToTimer3Trigger = 57U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceiveLineIdleToTimer3Trigger     = 58U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceivedDataWordToTimer3Trigger    = 59U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1TransmittedDataWordToTimer3Trigger = 60U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceiveLineIdleToTimer3Trigger     = 61U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceivedDataWordToTimer3Trigger    = 62U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2TransmittedDataWordToTimer3Trigger = 63U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceiveLineIdleToTimer3Trigger     = 64U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceivedDataWordToTimer3Trigger    = 65U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3TransmittedDataWordToTimer3Trigger = 66U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceiveLineIdleToTimer3Trigger     = 67U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceivedDataWordToTimer3Trigger    = 68U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4TransmittedDataWordToTimer3Trigger = 69U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceiveLineIdleToTimer3Trigger     = 70U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToTimer3Trigger                   = 71U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToTimer3Trigger                   = 72U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToTimer3Trigger                   = 73U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToTimer3Trigger                   = 74U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp0ToTimer3Trigger                 = 75U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp1ToTimer3Trigger                 = 76U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp2ToTimer3Trigger                 = 77U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp3ToTimer3Trigger                 = 78U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToTimer3Trigger                  = 79U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToTimer3Trigger                  = 80U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToTimer3Trigger                  = 81U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToTimer3Trigger                  = 82U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToTimer3Trigger                  = 83U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToTimer3Trigger                  = 84U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToTimer3Trigger               = 85U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToTimer3Trigger               = 86U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToTimer3Trigger               = 87U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToTimer3Trigger               = 88U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToTimer3Trigger              = 89U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToTimer3Trigger            = 90U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToTimer3Trigger            = 91U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToTimer3Trigger            = 92U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToTimer3Trigger            = 93U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer3Trigger    = 94U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer3Trigger     = 95U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer3Trigger    = 96U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer3Trigger     = 97U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceivedDataWordToTimer3Trigger    = 98U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5TransmittedDataWordToTimer3Trigger = 99U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceiveLineIdleToTimer3Trigger     = 100U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp0ToTimer3Trigger                 = 105U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp1ToTimer3Trigger                 = 106U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp2ToTimer3Trigger                 = 107U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp3ToTimer3Trigger                 = 108U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp0ToTimer3Trigger                 = 109U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp1ToTimer3Trigger                 = 110U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp2ToTimer3Trigger                 = 111U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp3ToTimer3Trigger                 = 112U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToTimer3Trigger                    = 113U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToTimer3Trigger                    = 114U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToTimer3Trigger                    = 115U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToTimer3Trigger                    = 116U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToTimer3Trigger                    = 117U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToTimer3Trigger                    = 118U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToTimer3Trigger                    = 119U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToTimer3Trigger                    = 120U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToTimer3Trigger                    = 121U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToTimer3Trigger                    = 122U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToTimer3Trigger                   = 123U + (TIMER3TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToTimer3Trigger                   = 124U + (TIMER3TRIGIN << PMUX_SHIFT),
+
+    /*!< TIMER4 Trigger. */
+    kINPUTMUX_CtimerInp0ToTimer4Trigger                 = 1U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp1ToTimer4Trigger                 = 2U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp2ToTimer4Trigger                 = 3U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp3ToTimer4Trigger                 = 4U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp4ToTimer4Trigger                 = 5U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp5ToTimer4Trigger                 = 6U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp6ToTimer4Trigger                 = 7U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp7ToTimer4Trigger                 = 8U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp8ToTimer4Trigger                 = 9U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp9ToTimer4Trigger                 = 10U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp10ToTimer4Trigger                = 11U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp11ToTimer4Trigger                = 12U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp12ToTimer4Trigger                = 13U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp13ToTimer4Trigger                = 14U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp14ToTimer4Trigger                = 15U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp15ToTimer4Trigger                = 16U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp16ToTimer4Trigger                = 17U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp17ToTimer4Trigger                = 18U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp18ToTimer4Trigger                = 19U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp19ToTimer4Trigger                = 20U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Usb0StartOfFrameToTimer4Trigger           = 21U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToTimer4Trigger                   = 22U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToTimer4Trigger                   = 23U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToTimer4Trigger                   = 24U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToTimer4Trigger                   = 25U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp0ToTimer4Trigger                 = 26U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToTimer4Trigger                 = 27U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp2ToTimer4Trigger                 = 28U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp3ToTimer4Trigger                 = 29U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToTimer4Trigger                    = 30U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToTimer4Trigger                    = 31U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToTimer4Trigger                    = 32U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToTimer4Trigger                  = 33U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToTimer4Trigger                  = 34U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToTimer4Trigger                  = 35U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToTimer4Trigger                  = 36U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToTimer4Trigger                  = 37U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToTimer4Trigger                  = 38U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToTimer4Trigger               = 39U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToTimer4Trigger               = 40U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToTimer4Trigger               = 41U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToTimer4Trigger               = 42U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToTimer4Trigger              = 43U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToTimer4Trigger            = 44U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToTimer4Trigger            = 45U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToTimer4Trigger            = 46U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToTimer4Trigger            = 47U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer4Trigger    = 48U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer4Trigger     = 49U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer4Trigger    = 50U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer4Trigger     = 51U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0EndOfFrameToTimer4Trigger           = 52U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0ReceivedDataWordToTimer4Trigger     = 53U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1EndOfFrameToTimer4Trigger           = 54U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1ReceivedDataWordToTimer4Trigger     = 55U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceivedDataWordToTimer4Trigger    = 56U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0TransmittedDataWordToTimer4Trigger = 57U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceiveLineIdleToTimer4Trigger     = 58U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceivedDataWordToTimer4Trigger    = 59U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1TransmittedDataWordToTimer4Trigger = 60U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceiveLineIdleToTimer4Trigger     = 61U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceivedDataWordToTimer4Trigger    = 62U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2TransmittedDataWordToTimer4Trigger = 63U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceiveLineIdleToTimer4Trigger     = 64U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceivedDataWordToTimer4Trigger    = 65U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3TransmittedDataWordToTimer4Trigger = 66U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceiveLineIdleToTimer4Trigger     = 67U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceivedDataWordToTimer4Trigger    = 68U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4TransmittedDataWordToTimer4Trigger = 69U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceiveLineIdleToTimer4Trigger     = 70U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToTimer4Trigger                   = 71U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToTimer4Trigger                   = 72U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToTimer4Trigger                   = 73U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToTimer4Trigger                   = 74U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp0ToTimer4Trigger                 = 75U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp1ToTimer4Trigger                 = 76U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp2ToTimer4Trigger                 = 77U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp3ToTimer4Trigger                 = 78U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToTimer4Trigger                  = 79U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToTimer4Trigger                  = 80U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToTimer4Trigger                  = 81U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToTimer4Trigger                  = 82U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToTimer4Trigger                  = 83U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToTimer4Trigger                  = 84U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToTimer4Trigger               = 85U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToTimer4Trigger               = 86U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToTimer4Trigger               = 87U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToTimer4Trigger               = 88U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToTimer4Trigger              = 89U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToTimer4Trigger            = 90U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToTimer4Trigger            = 91U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToTimer4Trigger            = 92U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToTimer4Trigger            = 93U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer4Trigger    = 94U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer4Trigger     = 95U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer4Trigger    = 96U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer4Trigger     = 97U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceivedDataWordToTimer4Trigger    = 98U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5TransmittedDataWordToTimer4Trigger = 99U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ReceiveLineIdleToTimer4Trigger     = 100U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp0ToTimer4Trigger                 = 105U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp1ToTimer4Trigger                 = 106U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp2ToTimer4Trigger                 = 107U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp3ToTimer4Trigger                 = 108U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp0ToTimer4Trigger                 = 109U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp1ToTimer4Trigger                 = 110U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp2ToTimer4Trigger                 = 111U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp3ToTimer4Trigger                 = 112U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToTimer4Trigger                    = 113U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToTimer4Trigger                    = 114U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToTimer4Trigger                    = 115U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToTimer4Trigger                    = 116U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToTimer4Trigger                    = 117U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToTimer4Trigger                    = 118U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToTimer4Trigger                    = 119U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToTimer4Trigger                    = 120U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToTimer4Trigger                    = 121U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToTimer4Trigger                    = 122U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToTimer4Trigger                   = 123U + (TIMER4TRIGIN << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToTimer4Trigger                   = 124U + (TIMER4TRIGIN << PMUX_SHIFT),
+
+    /*!< Selection for frequency measurement reference clock. */
+    kINPUTMUX_ClkInToFreqmeasRef           = 1U + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_FroOsc12MToFreqmeasRef       = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_FroHfDivToFreqmeasRef        = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Clk16K1ToFreqmeasRef         = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_SlowClkToFreqmeasRef         = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_FreqmeClkIn0ToFreqmeasRef    = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_FreqmeClkIn1ToFreqmeasRef    = 8u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFreqmeasRef        = 9u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFreqmeasRef        = 10u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToFreqmeasRef = 11u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToFreqmeasRef = 12u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToFreqmeasRef = 13u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToFreqmeasRef = 14u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToFreqmeasRef = 15u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToFreqmeasRef = 16u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToFreqmeasRef = 17u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToFreqmeasRef = 18u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFreqmeasRef        = 32u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFreqmeasRef        = 33u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToFreqmeasRef = 34u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToFreqmeasRef = 35u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToFreqmeasRef = 36u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToFreqmeasRef = 37u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToFreqmeasRef = 38u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToFreqmeasRef = 39u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToFreqmeasRef = 40u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToFreqmeasRef = 41u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+
+    /*!< Selection for frequency measurement target clock. */
+    kINPUTMUX_ClkInToFreqmeasTar           = 1U + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_FroOsc12MToFreqmeasTar       = 2u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_FroHfDivToFreqmeasTar        = 3u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Clk16K1ToFreqmeasTar         = 5u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_SlowClkToFreqmeasTar         = 6u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_FreqmeClkIn0ToFreqmeasTar    = 7u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_FreqmeClkIn1ToFreqmeasTar    = 8u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFreqmeasTar        = 9u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFreqmeasTar        = 10u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToFreqmeasTar = 11u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToFreqmeasTar = 12u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToFreqmeasTar = 13u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToFreqmeasTar = 14u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToFreqmeasTar = 15u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToFreqmeasTar = 16u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToFreqmeasTar = 17u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToFreqmeasTar = 18u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFreqmeasTar        = 32u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFreqmeasTar        = 33u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToFreqmeasTar = 34u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToFreqmeasTar = 35u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToFreqmeasTar = 36u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToFreqmeasTar = 37u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToFreqmeasTar = 38u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToFreqmeasTar = 39u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToFreqmeasTar = 40u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToFreqmeasTar = 41u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
+
+    /*!< Cmp0 Trigger. */
+    kINPUTMUX_Aoi0Out0ToCmp0Trigger           = 2U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToCmp0Trigger           = 3U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToCmp0Trigger           = 4U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToCmp0Trigger           = 5U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToCmp0Trigger            = 6U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToCmp0Trigger            = 7U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToCmp0Trigger          = 8U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToCmp0Trigger          = 9U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToCmp0Trigger          = 10U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToCmp0Trigger          = 11U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToCmp0Trigger          = 12U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToCmp0Trigger          = 13U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToCmp0Trigger             = 14U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToCmp0Trigger      = 16U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToCmp0Trigger    = 17U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToCmp0Trigger    = 18U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToCmp0Trigger    = 19U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToCmp0Trigger    = 20U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToCmp0Trigger    = 21U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToCmp0Trigger    = 22U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToCmp0Trigger    = 23U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToCmp0Trigger    = 24U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToCmp0Trigger = 25U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToCmp0Trigger = 26U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToCmp0Trigger = 27U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToCmp0Trigger = 28U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToCmp0Trigger = 29U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToCmp0Trigger                = 30U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToCmp0Trigger           = 31U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToCmp0Trigger           = 32U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToCmp0Trigger           = 33U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToCmp0Trigger           = 34U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M0ToCmp0Trigger          = 39U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToCmp0Trigger          = 40U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToCmp0Trigger          = 41U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToCmp0Trigger          = 42U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToCmp0Trigger      = 47U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToCmp0Trigger    = 48U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToCmp0Trigger    = 49U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToCmp0Trigger    = 50U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToCmp0Trigger    = 51U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToCmp0Trigger    = 52U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToCmp0Trigger    = 53U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToCmp0Trigger    = 54U + (CMP0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToCmp0Trigger    = 55U + (CMP0_TRIG_REG << PMUX_SHIFT),
+
+    /*!< Cmp1 Trigger. */
+    kINPUTMUX_Aoi0Out0ToCmp1Trigger           = 2U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToCmp1Trigger           = 3U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToCmp1Trigger           = 4U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToCmp1Trigger           = 5U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToCmp1Trigger            = 6U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToCmp1Trigger            = 7U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToCmp1Trigger          = 8U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToCmp1Trigger          = 9U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToCmp1Trigger          = 10U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToCmp1Trigger          = 11U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToCmp1Trigger          = 12U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToCmp1Trigger          = 13U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToCmp1Trigger             = 14U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToCmp1Trigger      = 16U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToCmp1Trigger    = 17U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToCmp1Trigger    = 18U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToCmp1Trigger    = 19U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToCmp1Trigger    = 20U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToCmp1Trigger    = 21U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToCmp1Trigger    = 22U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToCmp1Trigger    = 23U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToCmp1Trigger    = 24U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToCmp1Trigger = 25U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToCmp1Trigger = 26U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToCmp1Trigger = 27U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToCmp1Trigger = 28U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToCmp1Trigger = 29U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToCmp1Trigger                = 30U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToCmp1Trigger           = 31U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToCmp1Trigger           = 32U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToCmp1Trigger           = 33U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToCmp1Trigger           = 34U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M0ToCmp1Trigger          = 39U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToCmp1Trigger          = 40U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToCmp1Trigger          = 41U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToCmp1Trigger          = 42U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToCmp1Trigger      = 47U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToCmp1Trigger    = 48U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToCmp1Trigger    = 49U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToCmp1Trigger    = 50U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToCmp1Trigger    = 51U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToCmp1Trigger    = 52U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToCmp1Trigger    = 53U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToCmp1Trigger    = 54U + (CMP1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToCmp1Trigger    = 55U + (CMP1_TRIG_REG << PMUX_SHIFT),
+
+    /*!< Cmp2 Trigger. */
+    kINPUTMUX_Aoi0Out0ToCmp2Trigger           = 2U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToCmp2Trigger           = 3U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToCmp2Trigger           = 4U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToCmp2Trigger           = 5U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToCmp2Trigger            = 6U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToCmp2Trigger            = 7U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToCmp2Trigger          = 8U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToCmp2Trigger          = 9U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToCmp2Trigger          = 10U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToCmp2Trigger          = 11U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToCmp2Trigger          = 12U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToCmp2Trigger          = 13U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToCmp2Trigger             = 14U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToCmp2Trigger      = 16U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToCmp2Trigger    = 17U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToCmp2Trigger    = 18U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToCmp2Trigger    = 19U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToCmp2Trigger    = 20U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToCmp2Trigger    = 21U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToCmp2Trigger    = 22U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToCmp2Trigger    = 23U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToCmp2Trigger    = 24U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToCmp2Trigger = 25U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToCmp2Trigger = 26U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToCmp2Trigger = 27U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToCmp2Trigger = 28U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToCmp2Trigger = 29U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToCmp2Trigger                = 30U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToCmp2Trigger           = 31U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToCmp2Trigger           = 32U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToCmp2Trigger           = 33U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToCmp2Trigger           = 34U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M0ToCmp2Trigger          = 39U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToCmp2Trigger          = 40U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToCmp2Trigger          = 41U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToCmp2Trigger          = 42U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToCmp2Trigger      = 47U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToCmp2Trigger    = 48U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToCmp2Trigger    = 49U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToCmp2Trigger    = 50U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToCmp2Trigger    = 51U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToCmp2Trigger    = 52U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToCmp2Trigger    = 53U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToCmp2Trigger    = 54U + (CMP2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToCmp2Trigger    = 55U + (CMP2_TRIG_REG << PMUX_SHIFT),
+
+    /*!< Adc0 Trigger. */
+    kINPUTMUX_ArmTxevToAdc0Trigger            = 1U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToAdc0Trigger           = 2U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToAdc0Trigger           = 3U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToAdc0Trigger           = 4U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToAdc0Trigger           = 5U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToAdc0Trigger            = 6U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToAdc0Trigger            = 7U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToAdc0Trigger            = 7U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToAdc0Trigger          = 9U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToAdc0Trigger          = 10U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToAdc0Trigger          = 11U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToAdc0Trigger          = 12U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToAdc0Trigger          = 13U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToAdc0Trigger          = 14U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToAdc0Trigger             = 15U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToAdc0Trigger      = 17U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToAdc0Trigger    = 18U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToAdc0Trigger    = 19U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToAdc0Trigger    = 20U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToAdc0Trigger    = 21U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToAdc0Trigger    = 22U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToAdc0Trigger    = 23U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToAdc0Trigger    = 24U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToAdc0Trigger    = 25U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToAdc0Trigger = 26U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToAdc0Trigger = 27U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToAdc0Trigger = 28U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToAdc0Trigger = 29U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToAdc0Trigger = 30U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToAdc0Trigger                = 31U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToAdc0Trigger           = 33U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToAdc0Trigger           = 34U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToAdc0Trigger           = 35U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToAdc0Trigger           = 36U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp0ToAdc0Trigger         = 37U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp1ToAdc0Trigger         = 38U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp2ToAdc0Trigger         = 39U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp3ToAdc0Trigger         = 40U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M0ToAdc0Trigger          = 41U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToAdc0Trigger          = 42U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToAdc0Trigger          = 43U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToAdc0Trigger          = 44U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToAdc0Trigger          = 45U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToAdc0Trigger          = 46U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToAdc0Trigger          = 47U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToAdc0Trigger          = 48U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToAdc0Trigger      = 49U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToAdc0Trigger    = 50U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToAdc0Trigger    = 51U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToAdc0Trigger    = 52U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToAdc0Trigger    = 53U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToAdc0Trigger    = 54U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToAdc0Trigger    = 55U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToAdc0Trigger    = 56U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToAdc0Trigger    = 57U + (ADC0_TRIG0_REG << PMUX_SHIFT),
+
+    /*!< Adc1 Trigger. */
+    kINPUTMUX_ArmTxevToAdc1Trigger            = 1U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToAdc1Trigger           = 2U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToAdc1Trigger           = 3U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToAdc1Trigger           = 4U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToAdc1Trigger           = 5U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToAdc1Trigger            = 6U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToAdc1Trigger            = 7U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToAdc1Trigger            = 7U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToAdc1Trigger          = 9U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToAdc1Trigger          = 10U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToAdc1Trigger          = 11U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToAdc1Trigger          = 12U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToAdc1Trigger          = 13U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToAdc1Trigger          = 14U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToAdc1Trigger             = 15U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToAdc1Trigger      = 17U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToAdc1Trigger    = 18U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToAdc1Trigger    = 19U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToAdc1Trigger    = 20U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToAdc1Trigger    = 21U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToAdc1Trigger    = 22U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToAdc1Trigger    = 23U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToAdc1Trigger    = 24U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToAdc1Trigger    = 25U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToAdc1Trigger = 26U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToAdc1Trigger = 27U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToAdc1Trigger = 28U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToAdc1Trigger = 29U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToAdc1Trigger = 30U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToAdc1Trigger                = 31U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToAdc1Trigger           = 33U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToAdc1Trigger           = 34U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToAdc1Trigger           = 35U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToAdc1Trigger           = 36U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp0ToAdc1Trigger         = 37U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToAdc1Trigger         = 38U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp2ToAdc1Trigger         = 39U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp3ToAdc1Trigger         = 40U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M0ToAdc1Trigger          = 41U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToAdc1Trigger          = 42U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToAdc1Trigger          = 43U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToAdc1Trigger          = 44U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToAdc1Trigger          = 45U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToAdc1Trigger          = 46U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToAdc1Trigger          = 47U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToAdc1Trigger          = 48U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToAdc1Trigger      = 49U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToAdc1Trigger    = 50U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToAdc1Trigger    = 51U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToAdc1Trigger    = 52U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToAdc1Trigger    = 53U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToAdc1Trigger    = 54U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToAdc1Trigger    = 55U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToAdc1Trigger    = 56U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToAdc1Trigger    = 57U + (ADC1_TRIG0_REG << PMUX_SHIFT),
+
+    /*!< Adc2 Trigger. */
+    kINPUTMUX_ArmTxevToAdc2Trigger            = 1U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToAdc2Trigger           = 2U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToAdc2Trigger           = 3U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToAdc2Trigger           = 4U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToAdc2Trigger           = 5U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToAdc2Trigger            = 6U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToAdc2Trigger            = 7U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToAdc2Trigger            = 7U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToAdc2Trigger          = 9U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToAdc2Trigger          = 10U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToAdc2Trigger          = 11U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToAdc2Trigger          = 12U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToAdc2Trigger          = 13U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToAdc2Trigger          = 14U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToAdc2Trigger             = 15U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToAdc2Trigger      = 17U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToAdc2Trigger    = 18U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToAdc2Trigger    = 19U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToAdc2Trigger    = 20U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToAdc2Trigger    = 21U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToAdc2Trigger    = 22U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToAdc2Trigger    = 23U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToAdc2Trigger    = 24U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToAdc2Trigger    = 25U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToAdc2Trigger = 26U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToAdc2Trigger = 27U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToAdc2Trigger = 28U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToAdc2Trigger = 29U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToAdc2Trigger = 30U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToAdc2Trigger                = 31U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToAdc2Trigger           = 33U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToAdc2Trigger           = 34U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToAdc2Trigger           = 35U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToAdc2Trigger           = 36U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp0ToAdc2Trigger         = 37U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToAdc2Trigger         = 38U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp2ToAdc2Trigger         = 39U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp3ToAdc2Trigger         = 40U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M0ToAdc2Trigger          = 41U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToAdc2Trigger          = 42U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToAdc2Trigger          = 43U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToAdc2Trigger          = 44U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToAdc2Trigger          = 45U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToAdc2Trigger          = 46U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToAdc2Trigger          = 47U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToAdc2Trigger          = 48U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToAdc2Trigger      = 49U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToAdc2Trigger    = 50U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToAdc2Trigger    = 51U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToAdc2Trigger    = 52U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToAdc2Trigger    = 53U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToAdc2Trigger    = 54U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToAdc2Trigger    = 55U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToAdc2Trigger    = 56U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToAdc2Trigger    = 57U + (ADC2_TRIG0_REG << PMUX_SHIFT),
+
+    /*!< Adc3 Trigger. */
+    kINPUTMUX_ArmTxevToAdc3Trigger            = 1U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToAdc3Trigger           = 2U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToAdc3Trigger           = 3U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToAdc3Trigger           = 4U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToAdc3Trigger           = 5U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToAdc3Trigger            = 6U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToAdc3Trigger            = 7U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToAdc3Trigger            = 7U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToAdc3Trigger          = 9U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToAdc3Trigger          = 10U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToAdc3Trigger          = 11U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToAdc3Trigger          = 12U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToAdc3Trigger          = 13U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToAdc3Trigger          = 14U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToAdc3Trigger             = 15U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToAdc3Trigger      = 17U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToAdc3Trigger    = 18U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToAdc3Trigger    = 19U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToAdc3Trigger    = 20U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToAdc3Trigger    = 21U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToAdc3Trigger    = 22U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToAdc3Trigger    = 23U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToAdc3Trigger    = 24U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToAdc3Trigger    = 25U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToAdc3Trigger = 26U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToAdc3Trigger = 27U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToAdc3Trigger = 28U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToAdc3Trigger = 29U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToAdc3Trigger = 30U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToAdc3Trigger                = 31U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToAdc3Trigger           = 33U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToAdc3Trigger           = 34U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToAdc3Trigger           = 35U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToAdc3Trigger           = 36U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp0ToAdc3Trigger         = 37U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToAdc3Trigger         = 38U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp2ToAdc3Trigger         = 39U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp3ToAdc3Trigger         = 40U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M0ToAdc3Trigger          = 41U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToAdc3Trigger          = 42U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToAdc3Trigger          = 43U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToAdc3Trigger          = 44U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToAdc3Trigger          = 45U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToAdc3Trigger          = 46U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToAdc3Trigger          = 47U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToAdc3Trigger          = 48U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToAdc3Trigger      = 49U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToAdc3Trigger    = 50U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToAdc3Trigger    = 51U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToAdc3Trigger    = 52U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToAdc3Trigger    = 53U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToAdc3Trigger    = 54U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToAdc3Trigger    = 55U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToAdc3Trigger    = 56U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToAdc3Trigger    = 57U + (ADC3_TRIG0_REG << PMUX_SHIFT),
+
+    /*!< Dac0 Trigger. */
+    kINPUTMUX_ArmTxevToDac0Trigger            = 1U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToDac0Trigger           = 2U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToDac0Trigger           = 3U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToDac0Trigger           = 4U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToDac0Trigger           = 5U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToDac0Trigger            = 6U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToDac0Trigger            = 7U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToDac0Trigger            = 8U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToDac0Trigger          = 9U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToDac0Trigger          = 10U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToDac0Trigger          = 11U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToDac0Trigger          = 12U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToDac0Trigger          = 13U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToDac0Trigger          = 14U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToDac0Trigger             = 15U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToDac0Trigger    = 18U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToDac0Trigger    = 19U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToDac0Trigger    = 20U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToDac0Trigger    = 21U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToDac0Trigger = 26U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToDac0Trigger = 27U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToDac0Trigger = 28U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToDac0Trigger = 29U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToDac0Trigger = 30U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToDac0Trigger                = 31U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToDac0Trigger           = 33U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToDac0Trigger           = 34U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToDac0Trigger           = 35U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToDac0Trigger           = 36U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp0ToDac0Trigger         = 37U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToDac0Trigger         = 38U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp0ToDac0Trigger         = 39U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp1ToDac0Trigger         = 40U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M0ToDac0Trigger          = 41U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToDac0Trigger          = 42U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToDac0Trigger          = 43U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToDac0Trigger          = 44U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToDac0Trigger    = 50U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToDac0Trigger    = 51U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToDac0Trigger    = 52U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToDac0Trigger    = 55U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp0ToDac0Trigger         = 57U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp1ToDac0Trigger         = 58U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp0ToDac0Trigger         = 59U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp1ToDac0Trigger         = 60U + (DAC0_TRIG0_REG << PMUX_SHIFT),
+
+    /*!< Qdc0 Trigger. */
+    kINPUTMUX_ArmTxevToQdc0Trigger            = 1U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToQdc0Trigger           = 2U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToQdc0Trigger           = 3U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToQdc0Trigger           = 4U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToQdc0Trigger           = 5U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToQdc0Trigger            = 6U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToQdc0Trigger            = 7U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToQdc0Trigger            = 8U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToQdc0Trigger          = 9U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToQdc0Trigger          = 10U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToQdc0Trigger          = 11U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToQdc0Trigger          = 12U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToQdc0Trigger          = 13U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToQdc0Trigger          = 14U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Trigger    = 16U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Trigger    = 17U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Trigger    = 18U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Trigger    = 19U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Trigger    = 20U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Trigger    = 21U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Trigger    = 22U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Trigger    = 23U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToQdc0Trigger            = 24U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToQdc0Trigger            = 25U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToQdc0Trigger            = 26U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToQdc0Trigger            = 27U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToQdc0Trigger            = 28U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToQdc0Trigger            = 29U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToQdc0Trigger            = 30U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToQdc0Trigger            = 31U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToQdc0Trigger            = 32U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToQdc0Trigger            = 33U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToQdc0Trigger           = 34U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToQdc0Trigger           = 35U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToQdc0Trigger = 36U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToQdc0Trigger = 37U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToQdc0Trigger = 38U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToQdc0Trigger = 39U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToQdc0Trigger = 40U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToQdc0Trigger           = 41U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToQdc0Trigger           = 42U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToQdc0Trigger           = 43U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToQdc0Trigger           = 44U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToQdc0Trigger          = 49U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToQdc0Trigger          = 50U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToQdc0Trigger          = 51U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToQdc0Trigger          = 52U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Trigger    = 62U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Trigger    = 63U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Trigger    = 64U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Trigger    = 65U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Trigger    = 66U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Trigger    = 67U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Trigger    = 68U + (QDC0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Trigger    = 69U + (QDC0_TRIG_REG << PMUX_SHIFT),
+
+    /*!< Qdc0 Home. */
+    kINPUTMUX_ArmTxevToQdc0Home            = 1U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToQdc0Home           = 2U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToQdc0Home           = 3U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToQdc0Home           = 4U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToQdc0Home           = 5U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToQdc0Home            = 6U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToQdc0Home            = 7U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToQdc0Home            = 8U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToQdc0Home          = 9U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToQdc0Home          = 10U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToQdc0Home          = 11U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToQdc0Home          = 12U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToQdc0Home          = 13U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToQdc0Home          = 14U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Home    = 16U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Home    = 17U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Home    = 18U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Home    = 19U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Home    = 20U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Home    = 21U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Home    = 22U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Home    = 23U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToQdc0Home            = 24U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToQdc0Home            = 25U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToQdc0Home            = 26U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToQdc0Home            = 27U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToQdc0Home            = 28U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToQdc0Home            = 29U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToQdc0Home            = 30U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToQdc0Home            = 31U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToQdc0Home            = 32U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToQdc0Home            = 33U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToQdc0Home           = 34U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToQdc0Home           = 35U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToQdc0Home = 36U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToQdc0Home = 37U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToQdc0Home = 38U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToQdc0Home = 39U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToQdc0Home = 40U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToQdc0Home           = 41U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToQdc0Home           = 42U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToQdc0Home           = 43U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToQdc0Home           = 44U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToQdc0Home          = 49U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToQdc0Home          = 50U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToQdc0Home          = 51U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToQdc0Home          = 52U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Home    = 62U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Home    = 63U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Home    = 64U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Home    = 65U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Home    = 66U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Home    = 67U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Home    = 68U + (QDC0_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Home    = 69U + (QDC0_HOME_REG << PMUX_SHIFT),
+
+    /*!< Qdc0 Index. */
+    kINPUTMUX_ArmTxevToQdc0Index            = 1U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToQdc0Index           = 2U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToQdc0Index           = 3U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToQdc0Index           = 4U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToQdc0Index           = 5U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToQdc0Index            = 6U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToQdc0Index            = 7U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToQdc0Index            = 8U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToQdc0Index          = 9U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToQdc0Index          = 10U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToQdc0Index          = 11U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToQdc0Index          = 12U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToQdc0Index          = 13U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToQdc0Index          = 14U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Index    = 16U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Index    = 17U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Index    = 18U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Index    = 19U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Index    = 20U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Index    = 21U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Index    = 22U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Index    = 23U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToQdc0Index            = 24U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToQdc0Index            = 25U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToQdc0Index            = 26U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToQdc0Index            = 27U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToQdc0Index            = 28U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToQdc0Index            = 29U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToQdc0Index            = 30U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToQdc0Index            = 31U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToQdc0Index            = 32U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToQdc0Index            = 33U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToQdc0Index           = 34U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToQdc0Index           = 35U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToQdc0Index = 36U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToQdc0Index = 37U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToQdc0Index = 38U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToQdc0Index = 39U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToQdc0Index = 40U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToQdc0Index           = 41U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToQdc0Index           = 42U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToQdc0Index           = 43U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToQdc0Index           = 44U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToQdc0Index          = 49U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToQdc0Index          = 50U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToQdc0Index          = 51U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToQdc0Index          = 52U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Index    = 62U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Index    = 63U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Index    = 64U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Index    = 65U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Index    = 66U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Index    = 67U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Index    = 68U + (QDC0_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Index    = 69U + (QDC0_INDEX_REG << PMUX_SHIFT),
+
+    /*!< Qdc0 Phaseb. */
+    kINPUTMUX_ArmTxevToQdc0Phaseb            = 1U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToQdc0Phaseb           = 2U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToQdc0Phaseb           = 3U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToQdc0Phaseb           = 4U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToQdc0Phaseb           = 5U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToQdc0Phaseb            = 6U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToQdc0Phaseb            = 7U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToQdc0Phaseb            = 8U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToQdc0Phaseb          = 9U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToQdc0Phaseb          = 10U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToQdc0Phaseb          = 11U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToQdc0Phaseb          = 12U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToQdc0Phaseb          = 13U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToQdc0Phaseb          = 14U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Phaseb    = 16U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Phaseb    = 17U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Phaseb    = 18U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Phaseb    = 19U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Phaseb    = 20U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Phaseb    = 21U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Phaseb    = 22U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Phaseb    = 23U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToQdc0Phaseb            = 24U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToQdc0Phaseb            = 25U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToQdc0Phaseb            = 26U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToQdc0Phaseb            = 27U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToQdc0Phaseb            = 28U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToQdc0Phaseb            = 29U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToQdc0Phaseb            = 30U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToQdc0Phaseb            = 31U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToQdc0Phaseb            = 32U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToQdc0Phaseb            = 33U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToQdc0Phaseb           = 34U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToQdc0Phaseb           = 35U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToQdc0Phaseb = 36U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToQdc0Phaseb = 37U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToQdc0Phaseb = 38U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToQdc0Phaseb = 39U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToQdc0Phaseb = 40U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToQdc0Phaseb           = 41U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToQdc0Phaseb           = 42U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToQdc0Phaseb           = 43U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToQdc0Phaseb           = 44U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToQdc0Phaseb          = 49U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToQdc0Phaseb          = 50U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToQdc0Phaseb          = 51U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToQdc0Phaseb          = 52U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Phaseb    = 62U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Phaseb    = 63U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Phaseb    = 64U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Phaseb    = 65U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Phaseb    = 66U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Phaseb    = 67U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Phaseb    = 68U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Phaseb    = 69U + (QDC0_PHASEB_REG << PMUX_SHIFT),
+
+    /*!< Qdc0 Phasea. */
+    kINPUTMUX_ArmTxevToQdc0Phasea            = 1U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToQdc0Phasea           = 2U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToQdc0Phasea           = 3U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToQdc0Phasea           = 4U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToQdc0Phasea           = 5U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToQdc0Phasea            = 6U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToQdc0Phasea            = 7U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToQdc0Phasea            = 8U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToQdc0Phasea          = 9U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToQdc0Phasea          = 10U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToQdc0Phasea          = 11U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToQdc0Phasea          = 12U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToQdc0Phasea          = 13U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToQdc0Phasea          = 14U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Phasea    = 16U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Phasea    = 17U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Phasea    = 18U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Phasea    = 19U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Phasea    = 20U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Phasea    = 21U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Phasea    = 22U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Phasea    = 23U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToQdc0Phasea            = 24U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToQdc0Phasea            = 25U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToQdc0Phasea            = 26U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToQdc0Phasea            = 27U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToQdc0Phasea            = 28U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToQdc0Phasea            = 29U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToQdc0Phasea            = 30U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToQdc0Phasea            = 31U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToQdc0Phasea            = 32U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToQdc0Phasea            = 33U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToQdc0Phasea           = 34U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToQdc0Phasea           = 35U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToQdc0Phasea = 36U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToQdc0Phasea = 37U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToQdc0Phasea = 38U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToQdc0Phasea = 39U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToQdc0Phasea = 40U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToQdc0Phasea           = 41U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToQdc0Phasea           = 42U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToQdc0Phasea           = 43U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToQdc0Phasea           = 44U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToQdc0Phasea          = 49U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToQdc0Phasea          = 50U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToQdc0Phasea          = 51U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToQdc0Phasea          = 52U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Phasea    = 62U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Phasea    = 63U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Phasea    = 64U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Phasea    = 65U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Phasea    = 66U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Phasea    = 67U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Phasea    = 68U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Phasea    = 69U + (QDC0_PHASEA_REG << PMUX_SHIFT),
+
+    /*!< Qdc0 Icap1-3. */
+    kINPUTMUX_ArmTxevToQdc0Icap1            = 1U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToQdc0Icap1           = 2U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToQdc0Icap1           = 3U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToQdc0Icap1           = 4U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToQdc0Icap1           = 5U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToQdc0Icap1            = 6U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToQdc0Icap1            = 7U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToQdc0Icap1            = 8U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToQdc0Icap1          = 9U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToQdc0Icap1          = 10U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToQdc0Icap1          = 11U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToQdc0Icap1          = 12U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToQdc0Icap1          = 13U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToQdc0Icap1          = 14U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Icap1    = 16U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Icap1    = 17U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Icap1    = 18U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Icap1    = 19U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Icap1    = 20U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Icap1    = 21U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Icap1    = 22U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Icap1    = 23U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToQdc0Icap1            = 24U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToQdc0Icap1            = 25U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToQdc0Icap1            = 26U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToQdc0Icap1            = 27U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToQdc0Icap1            = 28U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToQdc0Icap1            = 29U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToQdc0Icap1            = 30U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToQdc0Icap1            = 31U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToQdc0Icap1            = 32U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToQdc0Icap1            = 33U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToQdc0Icap1           = 34U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToQdc0Icap1           = 35U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToQdc0Icap1 = 36U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToQdc0Icap1 = 37U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToQdc0Icap1 = 38U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToQdc0Icap1 = 39U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToQdc0Icap1 = 40U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToQdc0Icap1           = 41U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToQdc0Icap1           = 42U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToQdc0Icap1           = 43U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToQdc0Icap1           = 44U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToQdc0Icap1          = 49U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToQdc0Icap1          = 50U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToQdc0Icap1          = 51U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToQdc0Icap1          = 52U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Icap1    = 62U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Icap1    = 63U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Icap1    = 64U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Icap1    = 65U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Icap1    = 66U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Icap1    = 67U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Icap1    = 68U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Icap1    = 69U + (QDC0_ICAP0_REG << PMUX_SHIFT),
+
+    /*!< Qdc1 Trigger. */
+    kINPUTMUX_ArmTxevToQdc1Trigger            = 1U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToQdc1Trigger           = 2U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToQdc1Trigger           = 3U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToQdc1Trigger           = 4U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToQdc1Trigger           = 5U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToQdc1Trigger            = 6U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToQdc1Trigger            = 7U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToQdc1Trigger            = 8U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToQdc1Trigger          = 9U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToQdc1Trigger          = 10U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToQdc1Trigger          = 11U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToQdc1Trigger          = 12U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToQdc1Trigger          = 13U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToQdc1Trigger          = 14U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Trigger    = 16U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Trigger    = 17U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Trigger    = 18U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Trigger    = 19U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Trigger    = 20U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Trigger    = 21U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Trigger    = 22U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Trigger    = 23U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToQdc1Trigger            = 24U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToQdc1Trigger            = 25U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToQdc1Trigger            = 26U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToQdc1Trigger            = 27U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToQdc1Trigger            = 28U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToQdc1Trigger            = 29U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToQdc1Trigger            = 30U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToQdc1Trigger            = 31U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToQdc1Trigger            = 32U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToQdc1Trigger            = 33U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToQdc1Trigger           = 34U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToQdc1Trigger           = 35U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToQdc1Trigger = 36U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToQdc1Trigger = 37U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToQdc1Trigger = 38U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToQdc1Trigger = 39U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToQdc1Trigger = 40U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToQdc1Trigger           = 41U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToQdc1Trigger           = 42U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToQdc1Trigger           = 43U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToQdc1Trigger           = 44U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToQdc1Trigger          = 49U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToQdc1Trigger          = 50U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToQdc1Trigger          = 51U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToQdc1Trigger          = 52U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Trigger    = 62U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Trigger    = 63U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Trigger    = 64U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Trigger    = 65U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Trigger    = 66U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Trigger    = 67U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Trigger    = 68U + (QDC1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Trigger    = 69U + (QDC1_TRIG_REG << PMUX_SHIFT),
+
+    /*!< Qdc1 Home. */
+    kINPUTMUX_ArmTxevToQdc1Home            = 1U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToQdc1Home           = 2U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToQdc1Home           = 3U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToQdc1Home           = 4U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToQdc1Home           = 5U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToQdc1Home            = 6U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToQdc1Home            = 7U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToQdc1Home            = 8U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToQdc1Home          = 9U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToQdc1Home          = 10U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToQdc1Home          = 11U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToQdc1Home          = 12U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToQdc1Home          = 13U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToQdc1Home          = 14U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Home    = 16U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Home    = 17U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Home    = 18U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Home    = 19U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Home    = 20U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Home    = 21U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Home    = 22U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Home    = 23U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToQdc1Home            = 24U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToQdc1Home            = 25U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToQdc1Home            = 26U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToQdc1Home            = 27U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToQdc1Home            = 28U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToQdc1Home            = 29U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToQdc1Home            = 30U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToQdc1Home            = 31U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToQdc1Home            = 32U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToQdc1Home            = 33U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToQdc1Home           = 34U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToQdc1Home           = 35U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToQdc1Home = 36U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToQdc1Home = 37U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToQdc1Home = 38U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToQdc1Home = 39U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToQdc1Home = 40U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToQdc1Home           = 41U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToQdc1Home           = 42U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToQdc1Home           = 43U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToQdc1Home           = 44U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToQdc1Home          = 49U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToQdc1Home          = 50U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToQdc1Home          = 51U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToQdc1Home          = 52U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Home    = 62U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Home    = 63U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Home    = 64U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Home    = 65U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Home    = 66U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Home    = 67U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Home    = 68U + (QDC1_HOME_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Home    = 69U + (QDC1_HOME_REG << PMUX_SHIFT),
+
+    /*!< Qdc1 Index. */
+    kINPUTMUX_ArmTxevToQdc1Index            = 1U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToQdc1Index           = 2U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToQdc1Index           = 3U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToQdc1Index           = 4U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToQdc1Index           = 5U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToQdc1Index            = 6U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToQdc1Index            = 7U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToQdc1Index            = 8U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToQdc1Index          = 9U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToQdc1Index          = 10U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToQdc1Index          = 11U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToQdc1Index          = 12U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToQdc1Index          = 13U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToQdc1Index          = 14U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Index    = 16U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Index    = 17U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Index    = 18U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Index    = 19U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Index    = 20U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Index    = 21U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Index    = 22U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Index    = 23U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToQdc1Index            = 24U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToQdc1Index            = 25U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToQdc1Index            = 26U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToQdc1Index            = 27U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToQdc1Index            = 28U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToQdc1Index            = 29U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToQdc1Index            = 30U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToQdc1Index            = 31U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToQdc1Index            = 32U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToQdc1Index            = 33U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToQdc1Index           = 34U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToQdc1Index           = 35U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToQdc1Index = 36U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToQdc1Index = 37U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToQdc1Index = 38U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToQdc1Index = 39U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToQdc1Index = 40U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToQdc1Index           = 41U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToQdc1Index           = 42U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToQdc1Index           = 43U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToQdc1Index           = 44U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToQdc1Index          = 49U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToQdc1Index          = 50U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToQdc1Index          = 51U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToQdc1Index          = 52U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Index    = 62U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Index    = 63U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Index    = 64U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Index    = 65U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Index    = 66U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Index    = 67U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Index    = 68U + (QDC1_INDEX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Index    = 69U + (QDC1_INDEX_REG << PMUX_SHIFT),
+
+    /*!< Qdc1 Phaseb. */
+    kINPUTMUX_ArmTxevToQdc1Phaseb            = 1U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToQdc1Phaseb           = 2U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToQdc1Phaseb           = 3U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToQdc1Phaseb           = 4U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToQdc1Phaseb           = 5U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToQdc1Phaseb            = 6U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToQdc1Phaseb            = 7U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToQdc1Phaseb            = 8U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToQdc1Phaseb          = 9U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToQdc1Phaseb          = 10U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToQdc1Phaseb          = 11U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToQdc1Phaseb          = 12U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToQdc1Phaseb          = 13U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToQdc1Phaseb          = 14U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Phaseb    = 16U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Phaseb    = 17U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Phaseb    = 18U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Phaseb    = 19U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Phaseb    = 20U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Phaseb    = 21U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Phaseb    = 22U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Phaseb    = 23U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToQdc1Phaseb            = 24U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToQdc1Phaseb            = 25U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToQdc1Phaseb            = 26U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToQdc1Phaseb            = 27U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToQdc1Phaseb            = 28U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToQdc1Phaseb            = 29U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToQdc1Phaseb            = 30U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToQdc1Phaseb            = 31U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToQdc1Phaseb            = 32U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToQdc1Phaseb            = 33U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToQdc1Phaseb           = 34U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToQdc1Phaseb           = 35U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToQdc1Phaseb = 36U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToQdc1Phaseb = 37U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToQdc1Phaseb = 38U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToQdc1Phaseb = 39U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToQdc1Phaseb = 40U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToQdc1Phaseb           = 41U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToQdc1Phaseb           = 42U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToQdc1Phaseb           = 43U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToQdc1Phaseb           = 44U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToQdc1Phaseb          = 49U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToQdc1Phaseb          = 50U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToQdc1Phaseb          = 51U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToQdc1Phaseb          = 52U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Phaseb    = 62U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Phaseb    = 63U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Phaseb    = 64U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Phaseb    = 65U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Phaseb    = 66U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Phaseb    = 67U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Phaseb    = 68U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Phaseb    = 69U + (QDC1_PHASEB_REG << PMUX_SHIFT),
+
+    /*!< Qdc1 Phasea. */
+    kINPUTMUX_ArmTxevToQdc1Phasea            = 1U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToQdc1Phasea           = 2U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToQdc1Phasea           = 3U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToQdc1Phasea           = 4U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToQdc1Phasea           = 5U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToQdc1Phasea            = 6U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToQdc1Phasea            = 7U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToQdc1Phasea            = 8U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToQdc1Phasea          = 9U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToQdc1Phasea          = 10U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToQdc1Phasea          = 11U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToQdc1Phasea          = 12U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToQdc1Phasea          = 13U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToQdc1Phasea          = 14U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Phasea    = 16U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Phasea    = 17U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Phasea    = 18U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Phasea    = 19U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Phasea    = 20U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Phasea    = 21U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Phasea    = 22U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Phasea    = 23U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToQdc1Phasea            = 24U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToQdc1Phasea            = 25U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToQdc1Phasea            = 26U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToQdc1Phasea            = 27U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToQdc1Phasea            = 28U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToQdc1Phasea            = 29U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToQdc1Phasea            = 30U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToQdc1Phasea            = 31U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToQdc1Phasea            = 32U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToQdc1Phasea            = 33U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToQdc1Phasea           = 34U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToQdc1Phasea           = 35U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToQdc1Phasea = 36U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToQdc1Phasea = 37U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToQdc1Phasea = 38U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToQdc1Phasea = 39U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToQdc1Phasea = 40U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToQdc1Phasea           = 41U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToQdc1Phasea           = 42U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToQdc1Phasea           = 43U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToQdc1Phasea           = 44U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToQdc1Phasea          = 49U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToQdc1Phasea          = 50U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToQdc1Phasea          = 51U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToQdc1Phasea          = 52U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Phasea    = 62U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Phasea    = 63U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Phasea    = 64U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Phasea    = 65U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Phasea    = 66U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Phasea    = 67U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Phasea    = 68U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Phasea    = 69U + (QDC1_PHASEA_REG << PMUX_SHIFT),
+
+    /*!< Qdc1 Icap1-3. */
+    kINPUTMUX_ArmTxevToQdc1Icap1            = 1U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToQdc1Icap1           = 2U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToQdc1Icap1           = 3U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToQdc1Icap1           = 4U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToQdc1Icap1           = 5U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToQdc1Icap1            = 6U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToQdc1Icap1            = 7U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToQdc1Icap1            = 8U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToQdc1Icap1          = 9U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToQdc1Icap1          = 10U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToQdc1Icap1          = 11U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToQdc1Icap1          = 12U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToQdc1Icap1          = 13U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToQdc1Icap1          = 14U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Icap1    = 16U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Icap1    = 17U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Icap1    = 18U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Icap1    = 19U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Icap1    = 20U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Icap1    = 21U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Icap1    = 22U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Icap1    = 23U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToQdc1Icap1            = 24U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToQdc1Icap1            = 25U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToQdc1Icap1            = 26U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToQdc1Icap1            = 27U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToQdc1Icap1            = 28U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToQdc1Icap1            = 29U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToQdc1Icap1            = 30U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToQdc1Icap1            = 31U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToQdc1Icap1            = 32U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToQdc1Icap1            = 33U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToQdc1Icap1           = 34U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToQdc1Icap1           = 35U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToQdc1Icap1 = 36U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToQdc1Icap1 = 37U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToQdc1Icap1 = 38U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToQdc1Icap1 = 39U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToQdc1Icap1 = 40U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToQdc1Icap1           = 41U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToQdc1Icap1           = 42U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToQdc1Icap1           = 43U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToQdc1Icap1           = 44U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToQdc1Icap1          = 49U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToQdc1Icap1          = 50U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToQdc1Icap1          = 51U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToQdc1Icap1          = 52U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Icap1    = 62U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Icap1    = 63U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Icap1    = 64U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Icap1    = 65U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Icap1    = 66U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Icap1    = 67U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Icap1    = 68U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Icap1    = 69U + (QDC1_ICAP0_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM0_SM0_EXTA0 input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm0Sm0Exta0            = 1U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm0Sm0Exta0           = 2U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm0Sm0Exta0           = 3U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm0Sm0Exta0           = 4U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm0Sm0Exta0           = 5U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm0Sm0Exta0            = 6U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm0Sm0Exta0            = 7U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm0Sm0Exta0            = 8U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm0Sm0Exta0          = 9U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0Exta0          = 10U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm0Sm0Exta0          = 11U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0Exta0          = 12U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm0Sm0Exta0          = 13U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0Exta0          = 14U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm0Exta0       = 15U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm0Exta0       = 16U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm0Exta0       = 17U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm0Exta0       = 18U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm0Exta0      = 19U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm0Sm0Exta0            = 20U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm0Sm0Exta0            = 21U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm0Sm0Exta0            = 22U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm0Sm0Exta0            = 23U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm0Sm0Exta0            = 24U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm0Sm0Exta0            = 25U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm0Sm0Exta0            = 26U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm0Sm0Exta0            = 27U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm0Sm0Exta0            = 28U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm0Sm0Exta0            = 29U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm0Sm0Exta0           = 30U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm0Sm0Exta0           = 31U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm0Exta0 = 32U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm0Exta0 = 33U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0Exta0 = 34U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0Exta0 = 35U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm0Exta0 = 36U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm0Sm0Exta0           = 37U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm0Sm0Exta0           = 38U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm0Sm0Exta0           = 39U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm0Sm0Exta0           = 40U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm0Sm0Exta0          = 45U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm0Sm0Exta0          = 46U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm0Sm0Exta0          = 47U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm0Sm0Exta0          = 48U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm0Exta0       = 49U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm0Exta0       = 50U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm0Exta0       = 51U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm0Exta0       = 52U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm0Exta0      = 53U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm0Exta0    = 54U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm0Exta0    = 55U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm0Exta0    = 56U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm0Exta0    = 57U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm0Exta0    = 58U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm0Exta0    = 59U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm0Exta0    = 60U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm0Exta0    = 61U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM0_SM1_EXTA1 input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm0Sm1Exta1            = 1U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm0Sm1Exta1           = 2U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm0Sm1Exta1           = 3U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm0Sm1Exta1           = 4U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm0Sm1Exta1           = 5U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm0Sm1Exta1            = 6U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm0Sm1Exta1            = 7U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm0Sm1Exta1            = 8U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm0Sm1Exta1          = 9U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1Exta1          = 10U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm0Sm1Exta1          = 11U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1Exta1          = 12U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm0Sm1Exta1          = 13U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1Exta1          = 14U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm1Exta1       = 15U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm1Exta1       = 16U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm1Exta1       = 17U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm1Exta1       = 18U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm1Exta1      = 19U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm0Sm1Exta1            = 20U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm0Sm1Exta1            = 21U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm0Sm1Exta1            = 22U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm0Sm1Exta1            = 23U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm0Sm1Exta1            = 24U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm0Sm1Exta1            = 25U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm0Sm1Exta1            = 26U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm0Sm1Exta1            = 27U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm0Sm1Exta1            = 28U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm0Sm1Exta1            = 29U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm0Sm1Exta1           = 30U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm0Sm1Exta1           = 31U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm1Exta1 = 32U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm1Exta1 = 33U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1Exta1 = 34U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1Exta1 = 35U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm1Exta1 = 36U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm0Sm1Exta1           = 37U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm0Sm1Exta1           = 38U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm0Sm1Exta1           = 39U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm0Sm1Exta1           = 40U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm0Sm1Exta1          = 45U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm0Sm1Exta1          = 46U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm0Sm1Exta1          = 47U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm0Sm1Exta1          = 48U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm1Exta1       = 49U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm1Exta1       = 50U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm1Exta1       = 51U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm1Exta1       = 52U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm1Exta1      = 53U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm1Exta1    = 54U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm1Exta1    = 55U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm1Exta1    = 56U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm1Exta1    = 57U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm1Exta1    = 58U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm1Exta1    = 59U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm1Exta1    = 60U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm1Exta1    = 61U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM0_SM2_EXTA2 input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm0Sm2Exta2            = 1U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm0Sm2Exta2           = 2U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm0Sm2Exta2           = 3U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm0Sm2Exta2           = 4U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm0Sm2Exta2           = 5U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm0Sm2Exta2            = 6U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm0Sm2Exta2            = 7U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm0Sm2Exta2            = 8U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm0Sm2Exta2          = 9U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2Exta2          = 10U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm0Sm2Exta2          = 11U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2Exta2          = 12U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm0Sm2Exta2          = 13U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2Exta2          = 14U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm2Exta2       = 15U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm2Exta2       = 16U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm2Exta2       = 17U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm2Exta2       = 18U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm2Exta2      = 19U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm0Sm2Exta2            = 20U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm0Sm2Exta2            = 21U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm0Sm2Exta2            = 22U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm0Sm2Exta2            = 23U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm0Sm2Exta2            = 24U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm0Sm2Exta2            = 25U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm0Sm2Exta2            = 26U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm0Sm2Exta2            = 27U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm0Sm2Exta2            = 28U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm0Sm2Exta2            = 29U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm0Sm2Exta2           = 30U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm0Sm2Exta2           = 31U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm2Exta2 = 32U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm2Exta2 = 33U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2Exta2 = 34U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2Exta2 = 35U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm2Exta2 = 36U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm0Sm2Exta2           = 37U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm0Sm2Exta2           = 38U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm0Sm2Exta2           = 39U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm0Sm2Exta2           = 40U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm0Sm2Exta2          = 45U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm0Sm2Exta2          = 46U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm0Sm2Exta2          = 47U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm0Sm2Exta2          = 48U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm2Exta2       = 49U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm2Exta2       = 50U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm2Exta2       = 51U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm2Exta2       = 52U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm2Exta2      = 53U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm2Exta2    = 54U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm2Exta2    = 55U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm2Exta2    = 56U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm2Exta2    = 57U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm2Exta2    = 58U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm2Exta2    = 59U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm2Exta2    = 60U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm2Exta2    = 61U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM0_SM3_EXTA3 input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm0Sm3Exta3            = 1U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm0Sm3Exta3           = 2U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm0Sm3Exta3           = 3U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm0Sm3Exta3           = 4U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm0Sm3Exta3           = 5U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm0Sm3Exta3            = 6U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm0Sm3Exta3            = 7U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm0Sm3Exta3            = 8U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm0Sm3Exta3          = 9U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm0Sm3Exta3          = 10U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm0Sm3Exta3          = 11U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm0Sm3Exta3          = 12U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm0Sm3Exta3          = 13U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm0Sm3Exta3          = 14U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm3Exta3       = 15U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm3Exta3       = 16U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm3Exta3       = 17U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm3Exta3       = 18U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm3Exta3      = 19U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm0Sm3Exta3            = 20U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm0Sm3Exta3            = 21U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm0Sm3Exta3            = 22U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm0Sm3Exta3            = 23U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm0Sm3Exta3            = 24U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm0Sm3Exta3            = 25U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm0Sm3Exta3            = 26U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm0Sm3Exta3            = 27U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm0Sm3Exta3            = 28U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm0Sm3Exta3            = 29U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm0Sm3Exta3           = 30U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm0Sm3Exta3           = 31U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm3Exta3 = 32U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm3Exta3 = 33U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm3Exta3 = 34U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm3Exta3 = 35U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm3Exta3 = 36U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm0Sm3Exta3           = 37U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm0Sm3Exta3           = 38U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm0Sm3Exta3           = 39U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm0Sm3Exta3           = 40U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm0Sm3Exta3          = 45U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm0Sm3Exta3          = 46U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm0Sm3Exta3          = 47U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm0Sm3Exta3          = 48U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm3Exta3       = 49U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm3Exta3       = 50U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm3Exta3       = 51U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm3Exta3       = 52U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm3Exta3      = 53U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm3Exta3    = 54U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm3Exta3    = 55U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm3Exta3    = 56U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm3Exta3    = 57U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm3Exta3    = 58U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm3Exta3    = 59U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm3Exta3    = 60U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm3Exta3    = 61U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM0_SM0_EXTSYNC0 input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm0Sm0Extsync0            = 1U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm0Sm0Extsync0           = 2U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm0Sm0Extsync0           = 3U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm0Sm0Extsync0           = 4U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm0Sm0Extsync0           = 5U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm0Sm0Extsync0            = 6U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm0Sm0Extsync0            = 7U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm0Sm0Extsync0            = 8U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm0Sm0Extsync0          = 9U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0Extsync0          = 10U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm0Sm0Extsync0          = 11U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0Extsync0          = 12U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm0Sm0Extsync0          = 13U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0Extsync0          = 14U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm0Extsync0       = 15U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm0Extsync0       = 16U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm0Extsync0       = 17U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm0Extsync0       = 18U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm0Extsync0      = 19U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm0Sm0Extsync0            = 20U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm0Sm0Extsync0            = 21U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm0Sm0Extsync0            = 22U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm0Sm0Extsync0            = 23U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm0Sm0Extsync0            = 24U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm0Sm0Extsync0            = 25U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm0Sm0Extsync0            = 26U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm0Sm0Extsync0            = 27U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm0Sm0Extsync0            = 28U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm0Sm0Extsync0            = 29U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm0Sm0Extsync0           = 30U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm0Sm0Extsync0           = 31U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm0Extsync0 = 32U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm0Extsync0 = 33U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0Extsync0 = 34U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0Extsync0 = 35U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm0Extsync0 = 36U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm0Sm0Extsync0           = 37U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm0Sm0Extsync0           = 38U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm0Sm0Extsync0           = 39U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm0Sm0Extsync0           = 40U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm0Sm0Extsync0          = 45U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm0Sm0Extsync0          = 46U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm0Sm0Extsync0          = 47U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm0Sm0Extsync0          = 48U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm0Extsync0       = 49U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm0Extsync0       = 50U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm0Extsync0       = 51U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm0Extsync0       = 52U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm0Extsync0      = 53U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm0Extsync0    = 54U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm0Extsync0    = 55U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm0Extsync0    = 56U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm0Extsync0    = 57U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm0Extsync0    = 58U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm0Extsync0    = 59U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm0Extsync0    = 60U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm0Extsync0    = 61U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM0_SM1_EXTSYNC1 input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm0Sm1Extsync1            = 1U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm0Sm1Extsync1           = 2U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm0Sm1Extsync1           = 3U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm0Sm1Extsync1           = 4U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm0Sm1Extsync1           = 5U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm0Sm1Extsync1            = 6U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm0Sm1Extsync1            = 7U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm0Sm1Extsync1            = 8U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm0Sm1Extsync1          = 9U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1Extsync1          = 10U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm0Sm1Extsync1          = 11U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1Extsync1          = 12U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm0Sm1Extsync1          = 13U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1Extsync1          = 14U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm1Extsync1       = 15U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm1Extsync1       = 16U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm1Extsync1       = 17U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm1Extsync1       = 18U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm1Extsync1      = 19U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm0Sm1Extsync1            = 20U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm0Sm1Extsync1            = 21U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm0Sm1Extsync1            = 22U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm0Sm1Extsync1            = 23U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm0Sm1Extsync1            = 24U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm0Sm1Extsync1            = 25U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm0Sm1Extsync1            = 26U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm0Sm1Extsync1            = 27U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm0Sm1Extsync1            = 28U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm0Sm1Extsync1            = 29U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm0Sm1Extsync1           = 30U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm0Sm1Extsync1           = 31U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm1Extsync1 = 32U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm1Extsync1 = 33U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1Extsync1 = 34U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1Extsync1 = 35U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm1Extsync1 = 36U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm0Sm1Extsync1           = 37U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm0Sm1Extsync1           = 38U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm0Sm1Extsync1           = 39U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm0Sm1Extsync1           = 40U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm0Sm1Extsync1          = 45U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm0Sm1Extsync1          = 46U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm0Sm1Extsync1          = 47U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm0Sm1Extsync1          = 48U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm1Extsync1       = 49U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm1Extsync1       = 50U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm1Extsync1       = 51U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm1Extsync1       = 52U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm1Extsync1      = 53U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm1Extsync1    = 54U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm1Extsync1    = 55U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm1Extsync1    = 56U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm1Extsync1    = 57U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm1Extsync1    = 58U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm1Extsync1    = 59U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm1Extsync1    = 60U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm1Extsync1    = 61U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM0_SM2_EXTSYNC2 input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm0Sm2Extsync2            = 1U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm0Sm2Extsync2           = 2U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm0Sm2Extsync2           = 3U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm0Sm2Extsync2           = 4U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm0Sm2Extsync2           = 5U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm0Sm2Extsync2            = 6U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm0Sm2Extsync2            = 7U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm0Sm2Extsync2            = 8U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm0Sm2Extsync2          = 9U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2Extsync2          = 10U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm0Sm2Extsync2          = 11U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2Extsync2          = 12U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm0Sm2Extsync2          = 13U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2Extsync2          = 14U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm2Extsync2       = 15U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm2Extsync2       = 16U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm2Extsync2       = 17U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm2Extsync2       = 18U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm2Extsync2      = 19U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm0Sm2Extsync2            = 20U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm0Sm2Extsync2            = 21U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm0Sm2Extsync2            = 22U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm0Sm2Extsync2            = 23U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm0Sm2Extsync2            = 24U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm0Sm2Extsync2            = 25U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm0Sm2Extsync2            = 26U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm0Sm2Extsync2            = 27U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm0Sm2Extsync2            = 28U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm0Sm2Extsync2            = 29U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm0Sm2Extsync2           = 30U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm0Sm2Extsync2           = 31U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm2Extsync2 = 32U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm2Extsync2 = 33U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2Extsync2 = 34U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2Extsync2 = 35U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm2Extsync2 = 36U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm0Sm2Extsync2           = 37U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm0Sm2Extsync2           = 38U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm0Sm2Extsync2           = 39U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm0Sm2Extsync2           = 40U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm0Sm2Extsync2          = 45U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm0Sm2Extsync2          = 46U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm0Sm2Extsync2          = 47U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm0Sm2Extsync2          = 48U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm2Extsync2       = 49U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm2Extsync2       = 50U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm2Extsync2       = 51U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm2Extsync2       = 52U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm2Extsync2      = 53U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm2Extsync2    = 54U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm2Extsync2    = 55U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm2Extsync2    = 56U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm2Extsync2    = 57U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm2Extsync2    = 58U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm2Extsync2    = 59U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm2Extsync2    = 60U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm2Extsync2    = 61U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM0_SM3_EXTSYNC3 input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm0Sm3Extsync3            = 1U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm0Sm3Extsync3           = 2U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm0Sm3Extsync3           = 3U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm0Sm3Extsync3           = 4U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm0Sm3Extsync3           = 5U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm0Sm3Extsync3            = 6U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm0Sm3Extsync3            = 7U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm0Sm3Extsync3            = 8U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm0Sm3Extsync3          = 9U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm0Sm3Extsync3          = 10U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm0Sm3Extsync3          = 11U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm0Sm3Extsync3          = 12U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm0Sm3Extsync3          = 13U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm0Sm3Extsync3          = 14U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm3Extsync3       = 15U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm3Extsync3       = 16U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm3Extsync3       = 17U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm3Extsync3       = 18U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm3Extsync3      = 19U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm0Sm3Extsync3            = 20U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm0Sm3Extsync3            = 21U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm0Sm3Extsync3            = 22U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm0Sm3Extsync3            = 23U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm0Sm3Extsync3            = 24U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm0Sm3Extsync3            = 25U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm0Sm3Extsync3            = 26U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm0Sm3Extsync3            = 27U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm0Sm3Extsync3            = 28U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm0Sm3Extsync3            = 29U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm0Sm3Extsync3           = 30U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm0Sm3Extsync3           = 31U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm3Extsync3 = 32U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm3Extsync3 = 33U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm3Extsync3 = 34U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm3Extsync3 = 35U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm3Extsync3 = 36U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm0Sm3Extsync3           = 37U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm0Sm3Extsync3           = 38U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm0Sm3Extsync3           = 39U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm0Sm3Extsync3           = 40U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm0Sm3Extsync3          = 45U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm0Sm3Extsync3          = 46U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm0Sm3Extsync3          = 47U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm0Sm3Extsync3          = 48U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm3Extsync3       = 49U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm3Extsync3       = 50U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm3Extsync3       = 51U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm3Extsync3       = 52U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm3Extsync3      = 53U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm3Extsync3    = 54U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm3Extsync3    = 55U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm3Extsync3    = 56U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm3Extsync3    = 57U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm3Extsync3    = 58U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm3Extsync3    = 59U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm3Extsync3    = 60U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm3Extsync3    = 61U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM0_FAULT input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm0Fault            = 1U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm0Fault           = 2U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm0Fault           = 3U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm0Fault           = 4U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm0Fault           = 5U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm0Fault            = 6U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm0Fault            = 7U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm0Fault            = 8U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm0Fault          = 9U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm0Fault          = 10U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm0Fault          = 11U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm0Fault          = 12U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm0Fault          = 13U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm0Fault          = 14U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Fault       = 15U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Fault       = 16U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Fault       = 17U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Fault       = 18U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Fault      = 19U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm0Fault            = 20U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm0Fault            = 21U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm0Fault            = 22U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm0Fault            = 23U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm0Fault            = 24U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm0Fault            = 25U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm0Fault            = 26U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm0Fault            = 27U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm0Fault            = 28U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm0Fault            = 29U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm0Fault           = 30U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm0Fault           = 31U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Fault = 32U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Fault = 33U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault = 34U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault = 35U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Fault = 36U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm0Fault           = 37U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm0Fault           = 38U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm0Fault           = 39U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm0Fault           = 40U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm0Fault          = 45U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm0Fault          = 46U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm0Fault          = 47U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm0Fault          = 48U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Fault       = 49U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Fault       = 50U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Fault       = 51U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Fault       = 52U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Fault      = 53U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Fault    = 54U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Fault    = 55U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Fault    = 56U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Fault    = 57U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Fault    = 58U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Fault    = 59U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Fault    = 60U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Fault    = 61U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM0_FORCE input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm0Force            = 1U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm0Force           = 2U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm0Force           = 3U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm0Force           = 4U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm0Force           = 5U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm0Force            = 6U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm0Force            = 7U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm0Force            = 8U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm0Force          = 9U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm0Force          = 10U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm0Force          = 11U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm0Force          = 12U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm0Force          = 13U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm0Force          = 14U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Force       = 15U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Force       = 16U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Force       = 17U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Force       = 18U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Force      = 19U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm0Force            = 20U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm0Force            = 21U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm0Force            = 22U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm0Force            = 23U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm0Force            = 24U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm0Force            = 25U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm0Force            = 26U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm0Force            = 27U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm0Force            = 28U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm0Force            = 29U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm0Force           = 30U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm0Force           = 31U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Force = 32U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Force = 33U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Force = 34U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Force = 35U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Force = 36U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm0Force           = 37U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm0Force           = 38U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm0Force           = 39U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm0Force           = 40U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm0Force          = 45U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm0Force          = 46U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm0Force          = 47U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm0Force          = 48U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Force       = 49U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Force       = 50U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Force       = 51U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Force       = 52U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Force      = 53U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Force    = 54U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Force    = 55U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Force    = 56U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Force    = 57U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Force    = 58U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Force    = 59U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Force    = 60U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Force    = 61U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM1_SM0_EXTA0 input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm1Sm0Exta0            = 1U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm1Sm0Exta0           = 2U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm1Sm0Exta0           = 3U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm1Sm0Exta0           = 4U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm1Sm0Exta0           = 5U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm1Sm0Exta0            = 6U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm1Sm0Exta0            = 7U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm1Sm0Exta0            = 8U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm1Sm0Exta0          = 9U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0Exta0          = 10U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm1Sm0Exta0          = 11U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0Exta0          = 12U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm1Sm0Exta0          = 13U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0Exta0          = 14U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm0Exta0       = 15U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm0Exta0       = 16U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm0Exta0       = 17U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm0Exta0       = 18U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm0Exta0      = 19U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm1Sm0Exta0            = 20U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm1Sm0Exta0            = 21U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm1Sm0Exta0            = 22U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm1Sm0Exta0            = 23U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm1Sm0Exta0            = 24U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm1Sm0Exta0            = 25U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm1Sm0Exta0            = 26U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm1Sm0Exta0            = 27U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm1Sm0Exta0            = 28U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm1Sm0Exta0            = 29U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm1Sm0Exta0           = 30U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm1Sm0Exta0           = 31U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm0Exta0 = 32U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm0Exta0 = 33U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm0Exta0 = 34U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm0Exta0 = 35U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm0Exta0 = 36U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm1Sm0Exta0           = 37U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm1Sm0Exta0           = 38U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm1Sm0Exta0           = 39U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm1Sm0Exta0           = 40U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm1Sm0Exta0          = 45U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm1Sm0Exta0          = 46U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm1Sm0Exta0          = 47U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm1Sm0Exta0          = 48U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm0Exta0       = 49U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm0Exta0       = 50U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm0Exta0       = 51U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm0Exta0       = 52U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm0Exta0      = 53U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm0Exta0    = 54U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm0Exta0    = 55U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm0Exta0    = 56U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm0Exta0    = 57U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm0Exta0    = 58U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm0Exta0    = 59U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm0Exta0    = 60U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm0Exta0    = 61U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM1_SM1_EXTA1 input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm1Sm1Exta1            = 1U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm1Sm1Exta1           = 2U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm1Sm1Exta1           = 3U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm1Sm1Exta1           = 4U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm1Sm1Exta1           = 5U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm1Sm1Exta1            = 6U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm1Sm1Exta1            = 7U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm1Sm1Exta1            = 8U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm1Sm1Exta1          = 9U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1Exta1          = 10U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm1Sm1Exta1          = 11U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1Exta1          = 12U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm1Sm1Exta1          = 13U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1Exta1          = 14U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm1Exta1       = 15U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm1Exta1       = 16U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm1Exta1       = 17U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm1Exta1       = 18U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm1Exta1      = 19U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm1Sm1Exta1            = 20U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm1Sm1Exta1            = 21U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm1Sm1Exta1            = 22U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm1Sm1Exta1            = 23U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm1Sm1Exta1            = 24U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm1Sm1Exta1            = 25U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm1Sm1Exta1            = 26U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm1Sm1Exta1            = 27U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm1Sm1Exta1            = 28U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm1Sm1Exta1            = 29U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm1Sm1Exta1           = 30U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm1Sm1Exta1           = 31U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm1Exta1 = 32U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm1Exta1 = 33U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm1Exta1 = 34U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm1Exta1 = 35U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm1Exta1 = 36U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm1Sm1Exta1           = 37U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm1Sm1Exta1           = 38U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm1Sm1Exta1           = 39U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm1Sm1Exta1           = 40U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm1Sm1Exta1          = 45U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm1Sm1Exta1          = 46U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm1Sm1Exta1          = 47U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm1Sm1Exta1          = 48U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm1Exta1       = 49U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm1Exta1       = 50U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm1Exta1       = 51U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm1Exta1       = 52U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm1Exta1      = 53U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm1Exta1    = 54U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm1Exta1    = 55U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm1Exta1    = 56U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm1Exta1    = 57U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm1Exta1    = 58U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm1Exta1    = 59U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm1Exta1    = 60U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm1Exta1    = 61U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM1_SM2_EXTA2 input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm1Sm2Exta2            = 1U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm1Sm2Exta2           = 2U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm1Sm2Exta2           = 3U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm1Sm2Exta2           = 4U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm1Sm2Exta2           = 5U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm1Sm2Exta2            = 6U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm1Sm2Exta2            = 7U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm1Sm2Exta2            = 8U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm1Sm2Exta2          = 9U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm1Sm2Exta2          = 10U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm1Sm2Exta2          = 11U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm1Sm2Exta2          = 12U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm1Sm2Exta2          = 13U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm1Sm2Exta2          = 14U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm2Exta2       = 15U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm2Exta2       = 16U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm2Exta2       = 17U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm2Exta2       = 18U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm2Exta2      = 19U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm1Sm2Exta2            = 20U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm1Sm2Exta2            = 21U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm1Sm2Exta2            = 22U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm1Sm2Exta2            = 23U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm1Sm2Exta2            = 24U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm1Sm2Exta2            = 25U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm1Sm2Exta2            = 26U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm1Sm2Exta2            = 27U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm1Sm2Exta2            = 28U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm1Sm2Exta2            = 29U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm1Sm2Exta2           = 30U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm1Sm2Exta2           = 31U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm2Exta2 = 32U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm2Exta2 = 33U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm2Exta2 = 34U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm2Exta2 = 35U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm2Exta2 = 36U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm1Sm2Exta2           = 37U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm1Sm2Exta2           = 38U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm1Sm2Exta2           = 39U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm1Sm2Exta2           = 40U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm1Sm2Exta2          = 45U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm1Sm2Exta2          = 46U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm1Sm2Exta2          = 47U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm1Sm2Exta2          = 48U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm2Exta2       = 49U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm2Exta2       = 50U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm2Exta2       = 51U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm2Exta2       = 52U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm2Exta2      = 53U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm2Exta2    = 54U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm2Exta2    = 55U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm2Exta2    = 56U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm2Exta2    = 57U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm2Exta2    = 58U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm2Exta2    = 59U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm2Exta2    = 60U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm2Exta2    = 61U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM1_SM3_EXTA3 input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm1Sm3Exta3            = 1U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm1Sm3Exta3           = 2U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm1Sm3Exta3           = 3U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm1Sm3Exta3           = 4U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm1Sm3Exta3           = 5U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm1Sm3Exta3            = 6U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm1Sm3Exta3            = 7U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm1Sm3Exta3            = 8U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm1Sm3Exta3          = 9U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm1Sm3Exta3          = 10U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm1Sm3Exta3          = 11U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm1Sm3Exta3          = 12U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm1Sm3Exta3          = 13U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm1Sm3Exta3          = 14U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm3Exta3       = 15U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm3Exta3       = 16U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm3Exta3       = 17U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm3Exta3       = 18U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm3Exta3      = 19U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm1Sm3Exta3            = 20U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm1Sm3Exta3            = 21U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm1Sm3Exta3            = 22U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm1Sm3Exta3            = 23U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm1Sm3Exta3            = 24U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm1Sm3Exta3            = 25U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm1Sm3Exta3            = 26U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm1Sm3Exta3            = 27U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm1Sm3Exta3            = 28U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm1Sm3Exta3            = 29U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm1Sm3Exta3           = 30U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm1Sm3Exta3           = 31U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm3Exta3 = 32U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm3Exta3 = 33U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm3Exta3 = 34U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm3Exta3 = 35U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm3Exta3 = 36U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm1Sm3Exta3           = 37U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm1Sm3Exta3           = 38U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm1Sm3Exta3           = 39U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm1Sm3Exta3           = 40U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm1Sm3Exta3          = 45U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm1Sm3Exta3          = 46U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm1Sm3Exta3          = 47U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm1Sm3Exta3          = 48U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm3Exta3       = 49U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm3Exta3       = 50U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm3Exta3       = 51U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm3Exta3       = 52U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm3Exta3      = 53U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm3Exta3    = 54U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm3Exta3    = 55U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm3Exta3    = 56U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm3Exta3    = 57U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm3Exta3    = 58U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm3Exta3    = 59U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm3Exta3    = 60U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm3Exta3    = 61U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM1_SM0_EXTSYNC0 input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm1Sm0Extsync0            = 1U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm1Sm0Extsync0           = 2U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm1Sm0Extsync0           = 3U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm1Sm0Extsync0           = 4U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm1Sm0Extsync0           = 5U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm1Sm0Extsync0            = 6U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm1Sm0Extsync0            = 7U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm1Sm0Extsync0            = 8U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm1Sm0Extsync0          = 9U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0Extsync0          = 10U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm1Sm0Extsync0          = 11U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0Extsync0          = 12U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm1Sm0Extsync0          = 13U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0Extsync0          = 14U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm0Extsync0       = 15U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm0Extsync0       = 16U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm0Extsync0       = 17U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm0Extsync0       = 18U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm0Extsync0      = 19U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm1Sm0Extsync0            = 20U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm1Sm0Extsync0            = 21U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm1Sm0Extsync0            = 22U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm1Sm0Extsync0            = 23U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm1Sm0Extsync0            = 24U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm1Sm0Extsync0            = 25U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm1Sm0Extsync0            = 26U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm1Sm0Extsync0            = 27U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm1Sm0Extsync0            = 28U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm1Sm0Extsync0            = 29U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm1Sm0Extsync0           = 30U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm1Sm0Extsync0           = 31U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm0Extsync0 = 32U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm0Extsync0 = 33U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm0Extsync0 = 34U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm0Extsync0 = 35U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm0Extsync0 = 36U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm1Sm0Extsync0           = 37U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm1Sm0Extsync0           = 38U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm1Sm0Extsync0           = 39U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm1Sm0Extsync0           = 40U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm1Sm0Extsync0          = 45U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm1Sm0Extsync0          = 46U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm1Sm0Extsync0          = 47U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm1Sm0Extsync0          = 48U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm0Extsync0       = 49U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm0Extsync0       = 50U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm0Extsync0       = 51U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm0Extsync0       = 52U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm0Extsync0      = 53U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm0Extsync0    = 54U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm0Extsync0    = 55U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm0Extsync0    = 56U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm0Extsync0    = 57U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm0Extsync0    = 58U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm0Extsync0    = 59U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm0Extsync0    = 60U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm0Extsync0    = 61U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM1_SM1_EXTSYNC1 input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm1Sm1Extsync1            = 1U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm1Sm1Extsync1           = 2U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm1Sm1Extsync1           = 3U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm1Sm1Extsync1           = 4U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm1Sm1Extsync1           = 5U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm1Sm1Extsync1            = 6U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm1Sm1Extsync1            = 7U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm1Sm1Extsync1            = 8U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm1Sm1Extsync1          = 9U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1Extsync1          = 10U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm1Sm1Extsync1          = 11U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1Extsync1          = 12U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm1Sm1Extsync1          = 13U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1Extsync1          = 14U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm1Extsync1       = 15U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm1Extsync1       = 16U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm1Extsync1       = 17U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm1Extsync1       = 18U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm1Extsync1      = 19U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm1Sm1Extsync1            = 20U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm1Sm1Extsync1            = 21U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm1Sm1Extsync1            = 22U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm1Sm1Extsync1            = 23U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm1Sm1Extsync1            = 24U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm1Sm1Extsync1            = 25U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm1Sm1Extsync1            = 26U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm1Sm1Extsync1            = 27U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm1Sm1Extsync1            = 28U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm1Sm1Extsync1            = 29U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm1Sm1Extsync1           = 30U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm1Sm1Extsync1           = 31U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm1Extsync1 = 32U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm1Extsync1 = 33U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm1Extsync1 = 34U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm1Extsync1 = 35U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm1Extsync1 = 36U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm1Sm1Extsync1           = 37U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm1Sm1Extsync1           = 38U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm1Sm1Extsync1           = 39U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm1Sm1Extsync1           = 40U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm1Sm1Extsync1          = 45U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm1Sm1Extsync1          = 46U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm1Sm1Extsync1          = 47U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm1Sm1Extsync1          = 48U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm1Extsync1       = 49U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm1Extsync1       = 50U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm1Extsync1       = 51U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm1Extsync1       = 52U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm1Extsync1      = 53U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm1Extsync1    = 54U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm1Extsync1    = 55U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm1Extsync1    = 56U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm1Extsync1    = 57U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm1Extsync1    = 58U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm1Extsync1    = 59U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm1Extsync1    = 60U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm1Extsync1    = 61U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM1_SM2_EXTSYNC2 input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm1Sm2Extsync2            = 1U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm1Sm2Extsync2           = 2U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm1Sm2Extsync2           = 3U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm1Sm2Extsync2           = 4U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm1Sm2Extsync2           = 5U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm1Sm2Extsync2            = 6U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm1Sm2Extsync2            = 7U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm1Sm2Extsync2            = 8U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm1Sm2Extsync2          = 9U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm1Sm2Extsync2          = 10U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm1Sm2Extsync2          = 11U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm1Sm2Extsync2          = 12U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm1Sm2Extsync2          = 13U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm1Sm2Extsync2          = 14U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm2Extsync2       = 15U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm2Extsync2       = 16U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm2Extsync2       = 17U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm2Extsync2       = 18U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm2Extsync2      = 19U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm1Sm2Extsync2            = 20U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm1Sm2Extsync2            = 21U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm1Sm2Extsync2            = 22U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm1Sm2Extsync2            = 23U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm1Sm2Extsync2            = 24U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm1Sm2Extsync2            = 25U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm1Sm2Extsync2            = 26U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm1Sm2Extsync2            = 27U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm1Sm2Extsync2            = 28U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm1Sm2Extsync2            = 29U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm1Sm2Extsync2           = 30U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm1Sm2Extsync2           = 31U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm2Extsync2 = 32U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm2Extsync2 = 33U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm2Extsync2 = 34U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm2Extsync2 = 35U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm2Extsync2 = 36U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm1Sm2Extsync2           = 37U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm1Sm2Extsync2           = 38U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm1Sm2Extsync2           = 39U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm1Sm2Extsync2           = 40U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm1Sm2Extsync2          = 45U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm1Sm2Extsync2          = 46U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm1Sm2Extsync2          = 47U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm1Sm2Extsync2          = 48U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm2Extsync2       = 49U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm2Extsync2       = 50U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm2Extsync2       = 51U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm2Extsync2       = 52U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm2Extsync2      = 53U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm2Extsync2    = 54U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm2Extsync2    = 55U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm2Extsync2    = 56U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm2Extsync2    = 57U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm2Extsync2    = 58U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm2Extsync2    = 59U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm2Extsync2    = 60U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm2Extsync2    = 61U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM1_SM3_EXTSYNC3 input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm1Sm3Extsync3            = 1U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm1Sm3Extsync3           = 2U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm1Sm3Extsync3           = 3U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm1Sm3Extsync3           = 4U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm1Sm3Extsync3           = 5U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm1Sm3Extsync3            = 6U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm1Sm3Extsync3            = 7U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm1Sm3Extsync3            = 8U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm1Sm3Extsync3          = 9U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm1Sm3Extsync3          = 10U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm1Sm3Extsync3          = 11U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm1Sm3Extsync3          = 12U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm1Sm3Extsync3          = 13U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm1Sm3Extsync3          = 14U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm3Extsync3       = 15U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm3Extsync3       = 16U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm3Extsync3       = 17U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm3Extsync3       = 18U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm3Extsync3      = 19U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm1Sm3Extsync3            = 20U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm1Sm3Extsync3            = 21U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm1Sm3Extsync3            = 22U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm1Sm3Extsync3            = 23U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm1Sm3Extsync3            = 24U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm1Sm3Extsync3            = 25U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm1Sm3Extsync3            = 26U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm1Sm3Extsync3            = 27U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm1Sm3Extsync3            = 28U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm1Sm3Extsync3            = 29U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm1Sm3Extsync3           = 30U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm1Sm3Extsync3           = 31U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm3Extsync3 = 32U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm3Extsync3 = 33U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm3Extsync3 = 34U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm3Extsync3 = 35U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm3Extsync3 = 36U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm1Sm3Extsync3           = 37U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm1Sm3Extsync3           = 38U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm1Sm3Extsync3           = 39U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm1Sm3Extsync3           = 40U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm1Sm3Extsync3          = 45U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm1Sm3Extsync3          = 46U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm1Sm3Extsync3          = 47U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm1Sm3Extsync3          = 48U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm3Extsync3       = 49U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm3Extsync3       = 50U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm3Extsync3       = 51U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm3Extsync3       = 52U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm3Extsync3      = 53U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm3Extsync3    = 54U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm3Extsync3    = 55U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm3Extsync3    = 56U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm3Extsync3    = 57U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm3Extsync3    = 58U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm3Extsync3    = 59U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm3Extsync3    = 60U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm3Extsync3    = 61U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM1_FAULT input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm1Fault            = 1U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm1Fault           = 2U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm1Fault           = 3U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm1Fault           = 4U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm1Fault           = 5U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm1Fault            = 6U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm1Fault            = 7U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm1Fault            = 8U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm1Fault          = 9U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm1Fault          = 10U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm1Fault          = 11U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm1Fault          = 12U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm1Fault          = 13U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm1Fault          = 14U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Fault       = 15U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Fault       = 16U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Fault       = 17U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Fault       = 18U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Fault      = 19U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm1Fault            = 20U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm1Fault            = 21U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm1Fault            = 22U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm1Fault            = 23U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm1Fault            = 24U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm1Fault            = 25U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm1Fault            = 26U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm1Fault            = 27U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm1Fault            = 28U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm1Fault            = 29U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm1Fault           = 30U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm1Fault           = 31U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Fault = 32U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Fault = 33U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Fault = 34U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Fault = 35U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Fault = 36U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm1Fault           = 37U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm1Fault           = 38U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm1Fault           = 39U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm1Fault           = 40U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm1Fault          = 45U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm1Fault          = 46U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm1Fault          = 47U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm1Fault          = 48U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Fault       = 49U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Fault       = 50U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Fault       = 51U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Fault       = 52U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Fault      = 53U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Fault    = 54U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Fault    = 55U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Fault    = 56U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Fault    = 57U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Fault    = 58U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Fault    = 59U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Fault    = 60U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Fault    = 61U + (FlexPWM1_FAULT_REG << PMUX_SHIFT),
+
+    /*!< FlexPWM1_FORCE input trigger connections. */
+    kINPUTMUX_ArmTxevToFlexPwm1Force            = 1U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToFlexPwm1Force           = 2U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexPwm1Force           = 3U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexPwm1Force           = 4U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexPwm1Force           = 5U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexPwm1Force            = 6U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexPwm1Force            = 7U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexPwm1Force            = 8U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexPwm1Force          = 9U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToFlexPwm1Force          = 10U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexPwm1Force          = 11U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToFlexPwm1Force          = 12U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexPwm1Force          = 13U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToFlexPwm1Force          = 14U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Force       = 15U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Force       = 16U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Force       = 17U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Force       = 18U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Force      = 19U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexPwm1Force            = 20U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexPwm1Force            = 21U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexPwm1Force            = 22U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexPwm1Force            = 23U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexPwm1Force            = 24U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexPwm1Force            = 25U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexPwm1Force            = 26U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexPwm1Force            = 27U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToFlexPwm1Force            = 28U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToFlexPwm1Force            = 29U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToFlexPwm1Force           = 30U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToFlexPwm1Force           = 31U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Force = 32U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Force = 33U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Force = 34U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Force = 35U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Force = 36U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexPwm1Force           = 37U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexPwm1Force           = 38U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexPwm1Force           = 39U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexPwm1Force           = 40U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexPwm1Force          = 45U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexPwm1Force          = 46U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexPwm1Force          = 47U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexPwm1Force          = 48U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Force       = 49U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Force       = 50U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Force       = 51U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Force       = 52U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Force      = 53U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Force    = 54U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Force    = 55U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Force    = 56U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Force    = 57U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Force    = 58U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Force    = 59U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Force    = 60U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Force    = 61U + (FlexPWM1_FORCE_REG << PMUX_SHIFT),
+
+    /*!< PWM0 external clock trigger. */
+    kINPUTMUX_Clk16K1ToPwm0ExtClk    = 1U + (PWM0_EXT_CLK_REG << PMUX_SHIFT),
+    kINPUTMUX_ClkInToPwm0ExtClk      = 2U + (PWM0_EXT_CLK_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToPwm0ExtClk   = 3U + (PWM0_EXT_CLK_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToPwm0ExtClk   = 4U + (PWM0_EXT_CLK_REG << PMUX_SHIFT),
+    kINPUTMUX_ExttrigIn0ToPwm0ExtClk = 5U + (PWM0_EXT_CLK_REG << PMUX_SHIFT),
+    kINPUTMUX_ExttrigIn7ToPwm0ExtClk = 6U + (PWM0_EXT_CLK_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToPwm0ExtClk   = 7U + (PWM0_EXT_CLK_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToPwm0ExtClk   = 8U + (PWM0_EXT_CLK_REG << PMUX_SHIFT),
+
+    /*!< PWM1 external clock trigger. */
+    kINPUTMUX_Clk16K1ToPwm1ExtClk    = 1U + (PWM1_EXT_CLK_REG << PMUX_SHIFT),
+    kINPUTMUX_ClkInToPwm1ExtClk      = 2U + (PWM1_EXT_CLK_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToPwm1ExtClk   = 3U + (PWM1_EXT_CLK_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToPwm1ExtClk   = 4U + (PWM1_EXT_CLK_REG << PMUX_SHIFT),
+    kINPUTMUX_ExttrigIn0ToPwm1ExtClk = 5U + (PWM1_EXT_CLK_REG << PMUX_SHIFT),
+    kINPUTMUX_ExttrigIn7ToPwm1ExtClk = 6U + (PWM1_EXT_CLK_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToPwm1ExtClk   = 7U + (PWM1_EXT_CLK_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToPwm1ExtClk   = 8U + (PWM1_EXT_CLK_REG << PMUX_SHIFT),
+
+    /*!< AOI0 trigger input connections. */
+    kINPUTMUX_Adc0Tcomp0ToAoi0Mux         = 1U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToAoi0Mux         = 2U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp2ToAoi0Mux         = 3U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp3ToAoi0Mux         = 4U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToAoi0Mux            = 5U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToAoi0Mux            = 6U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToAoi0Mux            = 7U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToAoi0Mux          = 8U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToAoi0Mux          = 9U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToAoi0Mux          = 10U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToAoi0Mux          = 11U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToAoi0Mux          = 12U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToAoi0Mux          = 13U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToAoi0Mux          = 14U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToAoi0Mux          = 15U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToAoi0Mux          = 16U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToAoi0Mux          = 17U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToAoi0Mux          = 18U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToAoi0Mux          = 19U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToAoi0Mux             = 20U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToAoi0Mux       = 22U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToAoi0Mux       = 23U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToAoi0Mux       = 24U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToAoi0Mux       = 25U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatchToAoi0Mux       = 26U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToAoi0Mux    = 27U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToAoi0Mux    = 28U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToAoi0Mux    = 29U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToAoi0Mux    = 30U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToAoi0Mux    = 31U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToAoi0Mux    = 32U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToAoi0Mux    = 33U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToAoi0Mux    = 34U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToAoi0Mux            = 35U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToAoi0Mux            = 36U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToAoi0Mux            = 37U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToAoi0Mux            = 38U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToAoi0Mux            = 39U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToAoi0Mux            = 40U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToAoi0Mux            = 41U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToAoi0Mux            = 42U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToAoi0Mux            = 43U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToAoi0Mux            = 44U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToAoi0Mux           = 45U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToAoi0Mux           = 46U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToAoi0Mux = 47U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToAoi0Mux = 48U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToAoi0Mux = 49U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToAoi0Mux = 50U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToAoi0Mux = 51U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp0ToAoi0Mux         = 52U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp1ToAoi0Mux         = 53U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp2ToAoi0Mux         = 54U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp3ToAoi0Mux         = 55U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M0ToAoi0Mux          = 56U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToAoi0Mux          = 57U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToAoi0Mux          = 58U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToAoi0Mux          = 59U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToAoi0Mux          = 60U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToAoi0Mux          = 61U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToAoi0Mux          = 62U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToAoi0Mux          = 63U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToAoi0Mux          = 64U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToAoi0Mux          = 65U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToAoi0Mux          = 66U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToAoi0Mux          = 67U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToAoi0Mux       = 68U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToAoi0Mux       = 69U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToAoi0Mux       = 70U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToAoi0Mux       = 71U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatchToAoi0Mux       = 72U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToAoi0Mux    = 73U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToAoi0Mux    = 74U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToAoi0Mux    = 75U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToAoi0Mux    = 76U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToAoi0Mux    = 77U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToAoi0Mux    = 78U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToAoi0Mux    = 79U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToAoi0Mux    = 80U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0AOutToAoi0Mux        = 81U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0BOutToAoi0Mux        = 82U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1AOutToAoi0Mux        = 83U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1BOutToAoi0Mux        = 84U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2AOutToAoi0Mux        = 85U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2BOutToAoi0Mux        = 86U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3AOutToAoi0Mux        = 87U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3BOutToAoi0Mux        = 88U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp0ToAoi0Mux         = 89U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp1ToAoi0Mux         = 90U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp2ToAoi0Mux         = 91U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp3ToAoi0Mux         = 92U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp0ToAoi0Mux         = 93U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp1ToAoi0Mux         = 94U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp2ToAoi0Mux         = 95U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp3ToAoi0Mux         = 96U + (AOI0_MUX_REG << PMUX_SHIFT),
+
+    /*!< AOI1 trigger input connections. */
+    kINPUTMUX_Adc0Tcomp0ToAoi1Mux         = 1U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToAoi1Mux         = 2U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp2ToAoi1Mux         = 3U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp3ToAoi1Mux         = 4U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToAoi1Mux            = 5U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToAoi1Mux            = 6U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToAoi1Mux            = 6U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToAoi1Mux          = 8U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToAoi1Mux          = 9U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToAoi1Mux          = 10U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToAoi1Mux          = 11U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToAoi1Mux          = 12U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToAoi1Mux          = 13U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToAoi1Mux          = 14U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToAoi1Mux          = 15U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToAoi1Mux          = 16U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToAoi1Mux          = 17U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToAoi1Mux          = 18U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToAoi1Mux          = 19U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToAoi1Mux             = 20U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag0ToAoi1Mux       = 22U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag1ToAoi1Mux       = 23U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag2ToAoi1Mux       = 24U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0CmpFlag3ToAoi1Mux       = 25U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0PosMatchToAoi1Mux       = 26U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToAoi1Mux    = 27U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig1ToAoi1Mux    = 28U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToAoi1Mux    = 29U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig1ToAoi1Mux    = 30U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToAoi1Mux    = 31U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig1ToAoi1Mux    = 32U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToAoi1Mux    = 33U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig1ToAoi1Mux    = 34U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToAoi1Mux            = 35U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToAoi1Mux            = 36U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToAoi1Mux            = 37U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToAoi1Mux            = 38U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToAoi1Mux            = 39U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToAoi1Mux            = 40U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToAoi1Mux            = 41U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToAoi1Mux            = 42U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToAoi1Mux            = 43U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToAoi1Mux            = 44U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToAoi1Mux           = 45U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToAoi1Mux           = 46U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToAoi1Mux = 47U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToAoi1Mux = 48U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToAoi1Mux = 49U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToAoi1Mux = 50U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToAoi1Mux = 51U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp0ToAoi1Mux         = 52U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp1ToAoi1Mux         = 53U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp2ToAoi1Mux         = 54U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp3ToAoi1Mux         = 55U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M0ToAoi1Mux          = 56U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToAoi1Mux          = 57U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToAoi1Mux          = 58U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToAoi1Mux          = 59U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToAoi1Mux          = 60U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToAoi1Mux          = 61U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToAoi1Mux          = 62U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToAoi1Mux          = 63U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToAoi1Mux          = 64U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToAoi1Mux          = 65U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToAoi1Mux          = 66U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToAoi1Mux          = 67U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag0ToAoi1Mux       = 68U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag1ToAoi1Mux       = 69U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag2ToAoi1Mux       = 70U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1CmpFlag3ToAoi1Mux       = 71U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1PosMatchToAoi1Mux       = 72U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToAoi1Mux    = 73U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig1ToAoi1Mux    = 74U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToAoi1Mux    = 75U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig1ToAoi1Mux    = 76U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToAoi1Mux    = 77U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig1ToAoi1Mux    = 78U + (AOI1_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToAoi1Mux    = 79U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig1ToAoi1Mux    = 80U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0AOutToAoi1Mux        = 81U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0BOutToAoi1Mux        = 82U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1AOutToAoi1Mux        = 83U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1BOutToAoi1Mux        = 84U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2AOutToAoi1Mux        = 85U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2BOutToAoi1Mux        = 86U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3AOutToAoi1Mux        = 87U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3BOutToAoi1Mux        = 88U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp0ToAoi1Mux         = 89U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp1ToAoi1Mux         = 90U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp2ToAoi1Mux         = 91U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc2Tcomp3ToAoi1Mux         = 92U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp0ToAoi1Mux         = 93U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp1ToAoi1Mux         = 94U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp2ToAoi1Mux         = 95U + (AOI0_MUX_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc3Tcomp3ToAoi1Mux         = 96U + (AOI0_MUX_REG << PMUX_SHIFT),
+
+    /*!< USB-FS trigger input connections. */
+    kINPUTMUX_Lpuart0TrgTxdataToUsbfsTrigger = 1U + (USBFS_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1TrgTxdataToUsbfsTrigger = 2U + (USBFS_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2TrgTxdataToUsbfsTrigger = 3U + (USBFS_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3TrgTxdataToUsbfsTrigger = 4U + (USBFS_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4TrgTxdataToUsbfsTrigger = 5U + (USBFS_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5TrgTxdataToUsbfsTrigger = 6U + (USBFS_TRIG_REG << PMUX_SHIFT),
+
+    /*!< EXT trigger connections. */
+    kINPUTMUX_Aoi0Out0ToExtTrigger  = 2U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToExtTrigger  = 3U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToExtTrigger  = 4U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToExtTrigger  = 5U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToExtTrigger   = 6U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToExtTrigger   = 7U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToExtTrigger   = 8U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ToExtTrigger   = 9U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ToExtTrigger   = 10U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ToExtTrigger   = 11U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ToExtTrigger   = 12U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ToExtTrigger   = 13U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToExtTrigger  = 14U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToExtTrigger  = 15U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToExtTrigger  = 16U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToExtTrigger  = 17U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart5ToExtTrigger   = 18U + (EXT_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Rtc1HZClkToExtTrigger = 19U + (EXT_TRIG0_REG << PMUX_SHIFT),
+
+    /*!< LPI2C0 trigger input connections. */
+    kINPUTMUX_Aoi0Out0ToLpi2c0Trigger           = 2U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToLpi2c0Trigger           = 3U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToLpi2c0Trigger           = 4U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToLpi2c0Trigger           = 5U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToLpi2c0Trigger            = 6U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToLpi2c0Trigger            = 7U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToLpi2c0Trigger            = 8U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToLpi2c0Trigger          = 9U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToLpi2c0Trigger          = 10U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToLpi2c0Trigger          = 11U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToLpi2c0Trigger          = 12U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToLpi2c0Trigger          = 13U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToLpi2c0Trigger          = 14U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToLpi2c0Trigger             = 15U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToLpi2c0Trigger            = 17U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToLpi2c0Trigger            = 18U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToLpi2c0Trigger            = 19U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToLpi2c0Trigger            = 20U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToLpi2c0Trigger            = 21U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToLpi2c0Trigger            = 22U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToLpi2c0Trigger            = 23U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToLpi2c0Trigger            = 24U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToLpi2c0Trigger = 25U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToLpi2c0Trigger = 26U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToLpi2c0Trigger = 27U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToLpi2c0Trigger = 28U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToLpi2c0Trigger = 29U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToLpi2c0Trigger                = 30U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToLpi2c0Trigger           = 31U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToLpi2c0Trigger           = 32U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToLpi2c0Trigger           = 33U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToLpi2c0Trigger           = 34U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToLpi2c0Trigger          = 35U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToLpi2c0Trigger          = 36U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToLpi2c0Trigger          = 37U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToLpi2c0Trigger          = 38U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToLpi2c0Trigger          = 39U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToLpi2c0Trigger          = 40U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToLpi2c0Trigger          = 41U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToLpi2c0Trigger          = 42U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
+
+    /*!< LPI2C1 trigger input connections. */
+    kINPUTMUX_Aoi0Out0ToLpi2c1Trigger           = 2U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToLpi2c1Trigger           = 3U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToLpi2c1Trigger           = 4U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToLpi2c1Trigger           = 5U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToLpi2c1Trigger            = 6U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToLpi2c1Trigger            = 7U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToLpi2c1Trigger            = 8U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToLpi2c1Trigger          = 9U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToLpi2c1Trigger          = 10U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToLpi2c1Trigger          = 11U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToLpi2c1Trigger          = 12U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToLpi2c1Trigger          = 13U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToLpi2c1Trigger          = 14U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToLpi2c1Trigger             = 15U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToLpi2c1Trigger            = 17U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToLpi2c1Trigger            = 18U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToLpi2c1Trigger            = 19U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToLpi2c1Trigger            = 20U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToLpi2c1Trigger            = 21U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToLpi2c1Trigger            = 22U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToLpi2c1Trigger            = 23U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToLpi2c1Trigger            = 24U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToLpi2c1Trigger = 25U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToLpi2c1Trigger = 26U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToLpi2c1Trigger = 27U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToLpi2c1Trigger = 28U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToLpi2c1Trigger = 29U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToLpi2c1Trigger                = 30U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToLpi2c1Trigger           = 31U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToLpi2c1Trigger           = 32U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToLpi2c1Trigger           = 33U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToLpi2c1Trigger           = 34U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToLpi2c1Trigger          = 35U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToLpi2c1Trigger          = 36U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToLpi2c1Trigger          = 37U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToLpi2c1Trigger          = 38U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToLpi2c1Trigger          = 39U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToLpi2c1Trigger          = 40U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToLpi2c1Trigger          = 41U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToLpi2c1Trigger          = 42U + (LPI2C1_TRIG_REG << PMUX_SHIFT),
+
+    /*!< LPI2C2 trigger input connections. */
+    kINPUTMUX_Aoi0Out0ToLpi2c2Trigger           = 2U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToLpi2c2Trigger           = 3U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToLpi2c2Trigger           = 4U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToLpi2c2Trigger           = 5U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToLpi2c2Trigger            = 6U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToLpi2c2Trigger            = 7U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToLpi2c2Trigger            = 8U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToLpi2c2Trigger          = 9U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToLpi2c2Trigger          = 10U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToLpi2c2Trigger          = 11U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToLpi2c2Trigger          = 12U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToLpi2c2Trigger          = 13U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToLpi2c2Trigger          = 14U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToLpi2c2Trigger             = 15U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToLpi2c2Trigger            = 17U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToLpi2c2Trigger            = 18U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToLpi2c2Trigger            = 19U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToLpi2c2Trigger            = 20U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToLpi2c2Trigger            = 21U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToLpi2c2Trigger            = 22U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToLpi2c2Trigger            = 23U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToLpi2c2Trigger            = 24U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToLpi2c2Trigger = 25U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToLpi2c2Trigger = 26U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToLpi2c2Trigger = 27U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToLpi2c2Trigger = 28U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToLpi2c2Trigger = 29U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToLpi2c2Trigger                = 30U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToLpi2c2Trigger           = 31U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToLpi2c2Trigger           = 32U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToLpi2c2Trigger           = 33U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToLpi2c2Trigger           = 34U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToLpi2c2Trigger          = 35U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToLpi2c2Trigger          = 36U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToLpi2c2Trigger          = 37U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToLpi2c2Trigger          = 38U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToLpi2c2Trigger          = 39U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToLpi2c2Trigger          = 40U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToLpi2c2Trigger          = 41U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToLpi2c2Trigger          = 42U + (LPI2C2_TRIG_REG << PMUX_SHIFT),
+
+    /*!< LPI2C3 trigger input connections. */
+    kINPUTMUX_Aoi0Out0ToLpi2c3Trigger           = 2U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToLpi2c3Trigger           = 3U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToLpi2c3Trigger           = 4U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToLpi2c3Trigger           = 5U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToLpi2c3Trigger            = 6U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToLpi2c3Trigger            = 7U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToLpi2c3Trigger            = 8U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToLpi2c3Trigger          = 9U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToLpi2c3Trigger          = 10U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToLpi2c3Trigger          = 11U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToLpi2c3Trigger          = 12U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToLpi2c3Trigger          = 13U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToLpi2c3Trigger          = 14U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToLpi2c3Trigger             = 15U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToLpi2c3Trigger            = 17U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToLpi2c3Trigger            = 18U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToLpi2c3Trigger            = 19U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToLpi2c3Trigger            = 20U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToLpi2c3Trigger            = 21U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToLpi2c3Trigger            = 22U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToLpi2c3Trigger            = 23U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToLpi2c3Trigger            = 24U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToLpi2c3Trigger = 25U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToLpi2c3Trigger = 26U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToLpi2c3Trigger = 27U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToLpi2c3Trigger = 28U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToLpi2c3Trigger = 29U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToLpi2c3Trigger                = 30U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToLpi2c3Trigger           = 31U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToLpi2c3Trigger           = 32U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToLpi2c3Trigger           = 33U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToLpi2c3Trigger           = 34U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToLpi2c3Trigger          = 35U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToLpi2c3Trigger          = 36U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToLpi2c3Trigger          = 37U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToLpi2c3Trigger          = 38U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToLpi2c3Trigger          = 39U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToLpi2c3Trigger          = 40U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToLpi2c3Trigger          = 41U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToLpi2c3Trigger          = 42U + (LPI2C3_TRIG_REG << PMUX_SHIFT),
+
+    /*!< LPSPI0 trigger input connections. */
+    kINPUTMUX_Aoi0Out0ToLpspi0Trigger           = 2U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToLpspi0Trigger           = 3U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToLpspi0Trigger           = 4U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToLpspi0Trigger           = 5U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToLpspi0Trigger            = 6U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToLpspi0Trigger            = 7U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToLpspi0Trigger            = 8U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToLpspi0Trigger          = 9U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToLpspi0Trigger          = 10U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToLpspi0Trigger          = 11U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToLpspi0Trigger          = 12U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToLpspi0Trigger          = 13U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToLpspi0Trigger          = 14U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToLpspi0Trigger             = 15U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToLpspi0Trigger            = 17U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToLpspi0Trigger            = 18U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToLpspi0Trigger            = 19U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToLpspi0Trigger            = 20U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToLpspi0Trigger            = 21U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToLpspi0Trigger            = 22U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToLpspi0Trigger            = 23U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToLpspi0Trigger            = 24U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToLpspi0Trigger = 25U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToLpspi0Trigger = 26U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToLpspi0Trigger = 27U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToLpspi0Trigger = 28U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToLpspi0Trigger = 29U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToLpspi0Trigger                = 30U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToLpspi0Trigger           = 31U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToLpspi0Trigger           = 32U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToLpspi0Trigger           = 33U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToLpspi0Trigger           = 34U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToLpspi0Trigger          = 35U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToLpspi0Trigger          = 36U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToLpspi0Trigger          = 37U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToLpspi0Trigger          = 38U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToLpspi0Trigger          = 39U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToLpspi0Trigger          = 40U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToLpspi0Trigger          = 41U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToLpspi0Trigger          = 42U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
+
+    /*!< LPSPI1 trigger input connections. */
+    kINPUTMUX_Aoi0Out0ToLpspi1Trigger           = 2U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToLpspi1Trigger           = 3U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToLpspi1Trigger           = 4U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToLpspi1Trigger           = 5U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToLpspi1Trigger            = 6U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToLpspi1Trigger            = 7U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToLpspi1Trigger            = 7U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToLpspi1Trigger          = 9U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToLpspi1Trigger          = 10U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToLpspi1Trigger          = 11U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToLpspi1Trigger          = 12U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToLpspi1Trigger          = 13U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToLpspi1Trigger          = 14U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToLpspi1Trigger             = 15U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToLpspi1Trigger            = 17U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToLpspi1Trigger            = 18U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToLpspi1Trigger            = 19U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToLpspi1Trigger            = 20U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToLpspi1Trigger            = 21U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToLpspi1Trigger            = 22U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToLpspi1Trigger            = 23U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToLpspi1Trigger            = 24U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToLpspi1Trigger = 25U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToLpspi1Trigger = 26U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToLpspi1Trigger = 27U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToLpspi1Trigger = 28U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToLpspi1Trigger = 29U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToLpspi1Trigger                = 30U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToLpspi1Trigger           = 31U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToLpspi1Trigger           = 32U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToLpspi1Trigger           = 33U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToLpspi1Trigger           = 34U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToLpspi1Trigger          = 35U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToLpspi1Trigger          = 36U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToLpspi1Trigger          = 37U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToLpspi1Trigger          = 38U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToLpspi1Trigger          = 39U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToLpspi1Trigger          = 40U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToLpspi1Trigger          = 41U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToLpspi1Trigger          = 42U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
+
+    /*!< LPUART0 trigger input connections. */
+    kINPUTMUX_Aoi0Out0ToLpuart0Trigger                = 2U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToLpuart0Trigger                = 3U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToLpuart0Trigger                = 4U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToLpuart0Trigger                = 5U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToLpuart0Trigger                 = 6U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToLpuart0Trigger                 = 7U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToLpuart0Trigger                 = 7U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToLpuart0Trigger               = 9U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToLpuart0Trigger               = 10U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToLpuart0Trigger               = 11U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToLpuart0Trigger               = 12U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToLpuart0Trigger               = 13U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToLpuart0Trigger               = 14U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToLpuart0Trigger                  = 15U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToLpuart0Trigger                 = 17U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToLpuart0Trigger                 = 18U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToLpuart0Trigger                 = 19U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToLpuart0Trigger                 = 20U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToLpuart0Trigger                 = 21U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToLpuart0Trigger                 = 22U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToLpuart0Trigger                 = 23U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToLpuart0Trigger                 = 24U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToLpuart0Trigger                 = 25U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToLpuart0Trigger                 = 26U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToLpuart0Trigger                = 27U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToLpuart0Trigger                = 28U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToLpuart0Trigger      = 29U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToLpuart0Trigger      = 30U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToLpuart0Trigger      = 31U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToLpuart0Trigger      = 32U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToLpuart0Trigger      = 33U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToLpuart0Trigger                     = 34U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart0Trigger = 35U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToLpuart0Trigger                = 36U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToLpuart0Trigger                = 37U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToLpuart0Trigger                = 38U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToLpuart0Trigger                = 39U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToLpuart0Trigger               = 40U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToLpuart0Trigger               = 41U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToLpuart0Trigger               = 42U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToLpuart0Trigger               = 43U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToLpuart0Trigger               = 44U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToLpuart0Trigger               = 45U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToLpuart0Trigger               = 46U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToLpuart0Trigger               = 47U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+
+    /*!< LPUART1 trigger input connections. */
+    kINPUTMUX_Aoi0Out0ToLpuart1Trigger                = 2U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToLpuart1Trigger                = 3U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToLpuart1Trigger                = 4U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToLpuart1Trigger                = 5U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToLpuart1Trigger                 = 6U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToLpuart1Trigger                 = 7U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToLpuart1Trigger                 = 8U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToLpuart1Trigger               = 9U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToLpuart1Trigger               = 10U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToLpuart1Trigger               = 11U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToLpuart1Trigger               = 12U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToLpuart1Trigger               = 13U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToLpuart1Trigger               = 14U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToLpuart1Trigger                  = 15U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToLpuart1Trigger                 = 17U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToLpuart1Trigger                 = 18U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToLpuart1Trigger                 = 19U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToLpuart1Trigger                 = 20U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToLpuart1Trigger                 = 21U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToLpuart1Trigger                 = 22U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToLpuart1Trigger                 = 23U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToLpuart1Trigger                 = 24U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToLpuart1Trigger                 = 25U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToLpuart1Trigger                 = 26U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToLpuart1Trigger                = 27U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToLpuart1Trigger                = 28U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToLpuart1Trigger      = 29U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToLpuart1Trigger      = 30U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToLpuart1Trigger      = 31U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToLpuart1Trigger      = 32U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToLpuart1Trigger      = 33U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToLpuart1Trigger                     = 34U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart1Trigger = 35U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToLpuart1Trigger                = 36U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToLpuart1Trigger                = 37U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToLpuart1Trigger                = 38U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToLpuart1Trigger                = 39U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToLpuart1Trigger               = 40U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToLpuart1Trigger               = 41U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToLpuart1Trigger               = 42U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToLpuart1Trigger               = 43U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToLpuart1Trigger               = 44U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToLpuart1Trigger               = 45U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToLpuart1Trigger               = 46U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToLpuart1Trigger               = 47U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+
+    /*!< LPUART2 trigger input connections. */
+    kINPUTMUX_Aoi0Out0ToLpuart2Trigger                = 2U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToLpuart2Trigger                = 3U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToLpuart2Trigger                = 4U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToLpuart2Trigger                = 5U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToLpuart2Trigger                 = 6U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToLpuart2Trigger                 = 7U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToLpuart2Trigger                 = 8U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToLpuart2Trigger               = 9U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToLpuart2Trigger               = 10U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToLpuart2Trigger               = 11U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToLpuart2Trigger               = 12U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToLpuart2Trigger               = 13U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToLpuart2Trigger               = 14U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToLpuart2Trigger                  = 15U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToLpuart2Trigger                 = 17U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToLpuart2Trigger                 = 18U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToLpuart2Trigger                 = 19U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToLpuart2Trigger                 = 20U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToLpuart2Trigger                 = 21U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToLpuart2Trigger                 = 22U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToLpuart2Trigger                 = 23U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToLpuart2Trigger                 = 24U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToLpuart2Trigger                 = 25U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToLpuart2Trigger                 = 26U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToLpuart2Trigger                = 27U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToLpuart2Trigger                = 28U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToLpuart2Trigger      = 29U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToLpuart2Trigger      = 30U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToLpuart2Trigger      = 31U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToLpuart2Trigger      = 32U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToLpuart2Trigger      = 33U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToLpuart2Trigger                     = 34U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart2Trigger = 35U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToLpuart2Trigger                = 36U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToLpuart2Trigger                = 37U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToLpuart2Trigger                = 38U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToLpuart2Trigger                = 39U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToLpuart2Trigger               = 40U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToLpuart2Trigger               = 41U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToLpuart2Trigger               = 42U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToLpuart2Trigger               = 43U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToLpuart2Trigger               = 44U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToLpuart2Trigger               = 45U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToLpuart2Trigger               = 46U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToLpuart2Trigger               = 47U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+
+    /*!< LPUART3 trigger input connections. */
+    kINPUTMUX_Aoi0Out0ToLpuart3Trigger                = 2U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToLpuart3Trigger                = 3U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToLpuart3Trigger                = 4U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToLpuart3Trigger                = 5U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToLpuart3Trigger                 = 6U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToLpuart3Trigger                 = 7U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToLpuart3Trigger                 = 8U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToLpuart3Trigger               = 9U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToLpuart3Trigger               = 10U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToLpuart3Trigger               = 11U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToLpuart3Trigger               = 12U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToLpuart3Trigger               = 13U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToLpuart3Trigger               = 14U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToLpuart3Trigger                  = 15U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToLpuart3Trigger                 = 17U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToLpuart3Trigger                 = 18U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToLpuart3Trigger                 = 19U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToLpuart3Trigger                 = 20U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToLpuart3Trigger                 = 21U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToLpuart3Trigger                 = 22U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToLpuart3Trigger                 = 23U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToLpuart3Trigger                 = 24U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToLpuart3Trigger                 = 25U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToLpuart3Trigger                 = 26U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToLpuart3Trigger                = 27U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToLpuart3Trigger                = 28U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToLpuart3Trigger      = 29U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToLpuart3Trigger      = 30U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToLpuart3Trigger      = 31U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToLpuart3Trigger      = 32U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToLpuart3Trigger      = 33U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToLpuart3Trigger                     = 34U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart3Trigger = 35U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToLpuart3Trigger                = 36U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToLpuart3Trigger                = 37U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToLpuart3Trigger                = 38U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToLpuart3Trigger                = 39U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToLpuart3Trigger               = 40U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToLpuart3Trigger               = 41U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToLpuart3Trigger               = 42U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToLpuart3Trigger               = 43U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToLpuart3Trigger               = 44U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToLpuart3Trigger               = 45U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToLpuart3Trigger               = 46U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToLpuart3Trigger               = 47U + (LPUART3_TRIG_REG << PMUX_SHIFT),
+
+    /*!< LPUART4 trigger input connections. */
+    kINPUTMUX_Aoi0Out0ToLpuart4Trigger                = 2U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToLpuart4Trigger                = 3U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToLpuart4Trigger                = 4U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToLpuart4Trigger                = 5U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToLpuart4Trigger                 = 6U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToLpuart4Trigger                 = 7U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToLpuart4Trigger                 = 8U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToLpuart4Trigger               = 9U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToLpuart4Trigger               = 10U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToLpuart4Trigger               = 11U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToLpuart4Trigger               = 12U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToLpuart4Trigger               = 13U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToLpuart4Trigger               = 14U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToLpuart4Trigger                  = 15U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToLpuart4Trigger                 = 17U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToLpuart4Trigger                 = 18U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToLpuart4Trigger                 = 19U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToLpuart4Trigger                 = 20U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToLpuart4Trigger                 = 21U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToLpuart4Trigger                 = 22U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToLpuart4Trigger                 = 23U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToLpuart4Trigger                 = 24U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToLpuart4Trigger                 = 25U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToLpuart4Trigger                 = 26U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToLpuart4Trigger                = 27U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToLpuart4Trigger                = 28U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToLpuart4Trigger      = 29U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToLpuart4Trigger      = 30U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToLpuart4Trigger      = 31U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToLpuart4Trigger      = 32U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToLpuart4Trigger      = 33U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToLpuart4Trigger                     = 34U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart4Trigger = 35U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToLpuart4Trigger                = 36U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToLpuart4Trigger                = 37U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToLpuart4Trigger                = 38U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToLpuart4Trigger                = 39U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToLpuart4Trigger               = 40U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToLpuart4Trigger               = 41U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToLpuart4Trigger               = 42U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToLpuart4Trigger               = 43U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToLpuart4Trigger               = 44U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToLpuart4Trigger               = 45U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToLpuart4Trigger               = 46U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToLpuart4Trigger               = 47U + (LPUART4_TRIG_REG << PMUX_SHIFT),
+
+    /*!< LPUART5 trigger input connections. */
+    kINPUTMUX_Aoi0Out0ToLpuart5Trigger                = 2U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToLpuart5Trigger                = 3U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToLpuart5Trigger                = 4U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToLpuart5Trigger                = 5U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToLpuart5Trigger                 = 6U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToLpuart5Trigger                 = 7U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToLpuart5Trigger                 = 8U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToLpuart5Trigger               = 9U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToLpuart5Trigger               = 10U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToLpuart5Trigger               = 11U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToLpuart5Trigger               = 12U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToLpuart5Trigger               = 13U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToLpuart5Trigger               = 14U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToLpuart5Trigger                  = 15U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToLpuart5Trigger                 = 17U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToLpuart5Trigger                 = 18U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToLpuart5Trigger                 = 19U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToLpuart5Trigger                 = 20U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToLpuart5Trigger                 = 21U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToLpuart5Trigger                 = 22U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToLpuart5Trigger                 = 23U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToLpuart5Trigger                 = 24U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToLpuart5Trigger                 = 25U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToLpuart5Trigger                 = 26U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToLpuart5Trigger                = 27U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToLpuart5Trigger                = 28U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToLpuart5Trigger      = 29U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToLpuart5Trigger      = 30U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToLpuart5Trigger      = 31U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToLpuart5Trigger      = 32U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToLpuart5Trigger      = 33U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToLpuart5Trigger                     = 34U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart5Trigger = 35U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToLpuart5Trigger                = 36U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToLpuart5Trigger                = 37U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToLpuart5Trigger                = 38U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToLpuart5Trigger                = 39U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToLpuart5Trigger               = 40U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToLpuart5Trigger               = 41U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToLpuart5Trigger               = 42U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToLpuart5Trigger               = 43U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh0ToLpuart5Trigger               = 44U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh1ToLpuart5Trigger               = 45U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh2ToLpuart5Trigger               = 46U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioCh3ToLpuart5Trigger               = 47U + (LPUART5_TRIG_REG << PMUX_SHIFT),
+
+    /*!< Flexio trigger0 input connections. */
+    kINPUTMUX_Aoi0Out0ToFlexioTrigger                   = 1U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToFlexioTrigger                   = 2U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToFlexioTrigger                   = 3U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToFlexioTrigger                   = 4U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp0ToFlexioTrigger                 = 5U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp1ToFlexioTrigger                 = 6U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp2ToFlexioTrigger                 = 7U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0Tcomp3ToFlexioTrigger                 = 8U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToFlexioTrigger                    = 9U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToFlexioTrigger                    = 10U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToFlexioTrigger                    = 11U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToFlexioTrigger                  = 12U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToFlexioTrigger                  = 13U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToFlexioTrigger                  = 14U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToFlexioTrigger                  = 15U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToFlexioTrigger                  = 16U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToFlexioTrigger                  = 17U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToFlexioTrigger                     = 18U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm0OutTrig0ToFlexioTrigger            = 20U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm1OutTrig0ToFlexioTrigger            = 21U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm2OutTrig0ToFlexioTrigger            = 22U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0Sm3OutTrig0ToFlexioTrigger            = 23U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToFlexioTrigger                    = 24U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToFlexioTrigger                    = 25U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToFlexioTrigger                    = 26U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToFlexioTrigger                    = 27U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToFlexioTrigger                    = 28U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToFlexioTrigger                    = 29U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToFlexioTrigger                    = 30U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToFlexioTrigger                    = 31U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToFlexioTrigger         = 32U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToFlexioTrigger         = 33U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToFlexioTrigger         = 34U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrig0ToFlexioTrigger         = 35U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToFlexioTrigger                        = 36U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1A0Trig0ToFlexioTrigger                = 37U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0MasterEndOfPacketToFlexioTrigger    = 38U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0SlaveEndOfPacketToFlexioTrigger     = 39U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1MasterEndOfPacketToFlexioTrigger    = 40U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1SlaveEndOfPacketToFlexioTrigger     = 41U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0EndOfFrameToFlexioTrigger           = 42U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0ReceivedDataWordToFlexioTrigger     = 43U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1EndOfFrameToFlexioTrigger           = 44U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1ReceivedDataWordToFlexioTrigger     = 45U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceivedDataWordToFlexioTrigger    = 46U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0TransmittedDataWordToFlexioTrigger = 47U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0ReceiveLineIdleToFlexioTrigger     = 48U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceivedDataWordToFlexioTrigger    = 49U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1TransmittedDataWordToFlexioTrigger = 50U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1ReceiveLineIdleToFlexioTrigger     = 51U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceivedDataWordToFlexioTrigger    = 52U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2TransmittedDataWordToFlexioTrigger = 53U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2ReceiveLineIdleToFlexioTrigger     = 54U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceivedDataWordToFlexioTrigger    = 55U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3TransmittedDataWordToFlexioTrigger = 56U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3ReceiveLineIdleToFlexioTrigger     = 57U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceivedDataWordToFlexioTrigger    = 58U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4TransmittedDataWordToFlexioTrigger = 59U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart4ReceiveLineIdleToFlexioTrigger     = 60U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out0ToFlexioTrigger                   = 61U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToFlexioTrigger                   = 62U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out2ToFlexioTrigger                   = 63U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out3ToFlexioTrigger                   = 64U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp0ToFlexioTrigger                 = 65U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp1ToFlexioTrigger                 = 66U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp2ToFlexioTrigger                 = 67U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1Tcomp3ToFlexioTrigger                 = 68U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToFlexioTrigger                  = 69U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToFlexioTrigger                  = 70U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToFlexioTrigger                  = 71U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToFlexioTrigger                  = 72U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm0OutTrig0ToFlexioTrigger            = 73U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm1OutTrig0ToFlexioTrigger            = 74U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm2OutTrig0ToFlexioTrigger            = 75U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1Sm3OutTrig0ToFlexioTrigger            = 75U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2MasterEndOfPacketToFlexioTrigger    = 77U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c2SlaveEndOfPacketToFlexioTrigger     = 78U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3MasterEndOfPacketToFlexioTrigger    = 79U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c3SlaveEndOfPacketToFlexioTrigger     = 80U + (FLEXIO_TRIG0_REG << PMUX_SHIFT),
+
+    /*!< SMARTDMA0 trigger input connections. */
+    kINPUTMUX_GpioP0_16ToSmartdma0Trigger           = (1U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP0_17ToSmartdma0Trigger           = (2U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP1_8ToSmartdma0Trigger            = (3U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP1_9ToSmartdma0Trigger            = (4U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP1_10ToSmartdma0Trigger           = (5U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP1_11ToSmartdma0Trigger           = (6U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP1_12ToSmartdma0Trigger           = (7U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP1_13ToSmartdma0Trigger           = (8U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP2_0ToSmartdma0Trigger            = (9U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP2_1ToSmartdma0Trigger            = (10U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP2_2ToSmartdma0Trigger            = (11U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP2_3ToSmartdma0Trigger            = (12U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP2_6ToSmartdma0Trigger            = (13U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP3_8ToSmartdma0Trigger            = (14U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP3_9ToSmartdma0Trigger            = (15U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP3_10ToSmartdma0Trigger           = (16U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP3_11ToSmartdma0Trigger           = (17U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_GpioP3_12ToSmartdma0Trigger           = (18U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrigToSmartdma0Trigger   = (19U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrigToSmartdma0Trigger   = (20U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrigToSmartdma0Trigger   = (21U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrigToSmartdma0Trigger   = (22U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio4PinEventTrigToSmartdma0Trigger   = (23U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_ArmTxevToSmartdma0Trigger             = (24U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToSmartdma0Trigger            = (25U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi1Out1ToSmartdma0Trigger            = (26U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_DmaIrqToSmartdma0Trigger              = (27U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_MauIrqToSmartdma0Trigger              = (28U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuIrqToSmartdma0Trigger              = (29U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToSmartdma0Trigger           = (30U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToSmartdma0Trigger           = (31U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToSmartdma0Trigger           = (32U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToSmartdma0Trigger           = (33U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToSmartdma0Trigger           = (34U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToSmartdma0Trigger           = (35U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M2ToSmartdma0Trigger           = (36U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M3ToSmartdma0Trigger           = (37U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M2ToSmartdma0Trigger           = (38U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M3ToSmartdma0Trigger           = (39U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_OstimerIrqToSmartdma0Trigger          = (40U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm0IrqToSmartdma0Trigger             = (41U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Pwm1IrqToSmartdma0Trigger             = (42U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc0IrqToSmartdma0Trigger             = (43U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Qdc1IrqToSmartdma0Trigger             = (44U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_RtcAlarmIrqToSmartdma0Trigger         = (45U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Rtc1hzIrqToSmartdma0Trigger           = (46U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_UtickIrqToSmartdma0Trigger            = (47U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_WdtIrqToSmartdma0Trigger              = (48U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_WakeupTimerIrqToSmartdma0Trigger      = (49U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Can0IrqToSmartdma0Trigger             = (50U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Can1IrqToSmartdma0Trigger             = (51U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioIrqToSmartdma0Trigger           = (52U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioShifer0dmareqToSmartdma0Trigger = (53U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioShifer1dmareqToSmartdma0Trigger = (54U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioShifer2dmareqToSmartdma0Trigger = (55U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_FlexioShifer3dmareqToSmartdma0Trigger = (56U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_I3c0IrqToSmartdma0Trigger             = (57U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c0IrqToSmartdma0Trigger           = (58U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpi2c1IrqToSmartdma0Trigger           = (59U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpspi0IrqToSmartdma0Trigger           = (60U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpspi1IrqToSmartdma0Trigger           = (61U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart0IrqToSmartdma0Trigger          = (62U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart1IrqToSmartdma0Trigger          = (63U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart2IrqToSmartdma0Trigger          = (64U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Lpuart3IrqToSmartdma0Trigger          = (65U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Usb0SofToSmartdma0Trigger             = (66U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc0IrqToSmartdma0Trigger             = (68U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc1IrqToSmartdma0Trigger             = (69U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc2IrqToSmartdma0Trigger             = (70U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Adc3IrqToSmartdma0Trigger             = (71U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0IrqToSmartdma0Trigger             = (72U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1IrqToSmartdma0Trigger             = (73U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2IrqToSmartdma0Trigger             = (74U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToSmartdma0Trigger             = (75U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToSmartdma0Trigger             = (76U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp2OutToSmartdma0Trigger             = (77U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_Dac0IrqToSmartdma0Trigger             = (78U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+    kINPUTMUX_SlcdIrqToSmartdma0Trigger             = (79U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT),
+} inputmux_connection_t;
+
+/*@}*/
+
+/*@}*/
+
+#endif /* _FSL_INPUTMUX_CONNECTIONS_ */
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_reset.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_reset.c
new file mode 100644
index 0000000000..7f9bea99c1
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_reset.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright 2023, NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_reset.h"
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.reset"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#define GET_REG_INDEX(x) ((uint32_t)(((uint32_t)(x) & 0xFF00U) >> 8))
+#define GET_BIT_INDEX(x) ((uint32_t)((uint32_t)(x) & 0x00FFU))
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * param peripheral Assert reset to this peripheral. The enum argument contains
+ * encoding of reset register and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
+{
+    uint32_t regIndex             = GET_REG_INDEX(peripheral);
+    uint32_t bitPos               = GET_BIT_INDEX(peripheral);
+    uint32_t bitMask              = 1UL << bitPos;
+    volatile uint32_t *pResetCtrl = &(MRCC0->MRCC_GLB_RST0);
+
+    if (peripheral == NotAvail_RSTn)
+    {
+        return;
+    }
+
+    assert(bitPos < 32u);
+    assert(regIndex < 3u);
+
+    /* Unlock clock configuration */
+    SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK;
+
+    /* reset register is in MRCC */
+    /* set bit */
+    if (regIndex == 0U)
+    {
+        MRCC0->MRCC_GLB_RST0_SET = bitMask;
+        pResetCtrl               = &(MRCC0->MRCC_GLB_RST0);
+    }
+    else if (regIndex == 1U)
+    {
+        MRCC0->MRCC_GLB_RST1_SET = bitMask;
+        pResetCtrl               = &(MRCC0->MRCC_GLB_RST1);
+    }
+    else if (regIndex == 2U)
+    {
+        MRCC0->MRCC_GLB_RST2_SET = bitMask;
+        pResetCtrl               = &(MRCC0->MRCC_GLB_RST2);
+    }
+    else
+    {
+        /* Added comments to prevent the violation of MISRA C-2012 rule 15.7 */
+    }
+    /* wait until it reads 0b1 */
+    while (0u == ((*pResetCtrl) & bitMask))
+    {
+    }
+
+    /* Freeze clock configuration */
+    SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK;
+}
+
+/*!
+ * brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * param peripheral Clear reset to this peripheral. The enum argument contains
+ * encoding of reset register and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
+{
+    uint32_t regIndex             = GET_REG_INDEX(peripheral);
+    uint32_t bitPos               = GET_BIT_INDEX(peripheral);
+    uint32_t bitMask              = 1UL << bitPos;
+    volatile uint32_t *pResetCtrl = &(MRCC0->MRCC_GLB_RST0);
+
+    assert(bitPos < 32u);
+    assert(regIndex < 3u);
+
+    /* Unlock clock configuration */
+    SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK;
+
+    /* reset register is in MRCC */
+    /* clear bit */
+    if (regIndex == 0U)
+    {
+        MRCC0->MRCC_GLB_RST0_CLR = bitMask;
+        pResetCtrl               = &(MRCC0->MRCC_GLB_RST0);
+    }
+    else if (regIndex == 1U)
+    {
+        MRCC0->MRCC_GLB_RST1_CLR = bitMask;
+        pResetCtrl               = &(MRCC0->MRCC_GLB_RST1);
+    }
+    else if (regIndex == 2U)
+    {
+        MRCC0->MRCC_GLB_RST2_CLR = bitMask;
+        pResetCtrl               = &(MRCC0->MRCC_GLB_RST2);
+    }
+    else
+    {
+        /* Added comments to prevent the violation of MISRA C-2012 rule 15.7 */
+    }
+    /* wait until it reads 0b0 */
+    while (bitMask == ((*pResetCtrl) & bitMask))
+    {
+    }
+
+    /* Freeze clock configuration */
+    SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK;
+}
+
+/*!
+ * brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * param peripheral Peripheral to reset. The enum argument contains encoding of
+ * reset register and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral)
+{
+    RESET_ClearPeripheralReset(peripheral);
+    RESET_SetPeripheralReset(peripheral);
+}
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_reset.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_reset.h
new file mode 100644
index 0000000000..98ba7f28d4
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_reset.h
@@ -0,0 +1,201 @@
+/*
+ * Copyright 2023, NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_RESET_H_
+#define _FSL_RESET_H_
+
+#include "fsl_device_registers.h"
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+
+/*!
+ * @addtogroup reset
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief reset driver version 2.4.0 */
+#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
+/*@}*/
+
+/*!
+ * @brief Enumeration for peripheral reset control bits
+ *
+ * Defines the enumeration for peripheral reset control bits in
+ * PRESETCTRL/ASYNCPRESETCTRL registers
+ */
+typedef enum _SYSCON_RSTn
+{
+    kINPUTMUX0_RST_SHIFT_RSTn = ((0U << 8U) | 0U),  /*!< INPUTMUX0 reset control */
+    kCTIMER0_RST_SHIFT_RSTn   = ((0U << 8U) | 2U),  /*!< CTIMER0   reset control */
+    kCTIMER1_RST_SHIFT_RSTn   = ((0U << 8U) | 3U),  /*!< CTIMER1   reset control */
+    kCTIMER2_RST_SHIFT_RSTn   = ((0U << 8U) | 4U),  /*!< CTIMER2   reset control */
+    kFREQME_RST_SHIFT_RSTn    = ((0U << 8U) | 7U),  /*!< FREQME    reset control */
+    kUTICK0_RST_SHIFT_RSTn    = ((0U << 8U) | 8U),  /*!< UTICK0    reset control */
+    kSMART_DMA_RST_SHIFT_RSTn = ((0U << 8U) | 10U), /*!< SMARTDMA0 reset control */
+    kDMA0_RST_SHIFT_RSTn      = ((0U << 8U) | 11U), /*!< DMA0      reset control */
+    kAOI0_RST_SHIFT_RSTn      = ((0U << 8U) | 12U), /*!< AOI0      reset control */
+    kCRC0_RST_SHIFT_RSTn      = ((0U << 8U) | 13U), /*!< CRC0      reset control */
+    kEIM0_RST_SHIFT_RSTn      = ((0U << 8U) | 14U), /*!< EIM0      reset control */
+    kERM0_RST_SHIFT_RSTn      = ((0U << 8U) | 15U), /*!< ERM0      reset control */
+    kAOI1_RST_SHIFT_RSTn      = ((0U << 8U) | 17U), /*!< AOI1      reset control */
+    kLPI2C0_RST_SHIFT_RSTn    = ((0U << 8U) | 19U), /*!< LPI2C0    reset control */
+    kLPI2C1_RST_SHIFT_RSTn    = ((0U << 8U) | 20U), /*!< LPI2C1    reset control */
+    kLPSPI0_RST_SHIFT_RSTn    = ((0U << 8U) | 21U), /*!< LPSPI0    reset control */
+    kLPSPI1_RST_SHIFT_RSTn    = ((0U << 8U) | 22U), /*!< LPSPI1    reset control */
+    kLPUART0_RST_SHIFT_RSTn   = ((0U << 8U) | 23U), /*!< LPUART0   reset control */
+    kLPUART1_RST_SHIFT_RSTn   = ((0U << 8U) | 24U), /*!< LPUART1   reset control */
+    kLPUART2_RST_SHIFT_RSTn   = ((0U << 8U) | 25U), /*!< LPUART2   reset control */
+    kLPUART3_RST_SHIFT_RSTn   = ((0U << 8U) | 26U), /*!< LPUART3   reset control */
+    kQDC0_RST_SHIFT_RSTn      = ((0U << 8U) | 29U), /*!< QDC0      reset control */
+    kQDC1_RST_SHIFT_RSTn      = ((0U << 8U) | 30U), /*!< QDC1      reset control */
+    kFLEXPWM0_RST_SHIFT_RSTn  = ((0U << 8U) | 31U), /*!< FLEXPWM0  reset control */
+    kFLEXPWM1_RST_SHIFT_RSTn  = ((1U << 8U) | 0U),  /*!< FLEXPWM1  reset control */
+    kOSTIMER0_RST_SHIFT_RSTn  = ((1U << 8U) | 1U),  /*!< OSTIMER0  reset control */
+    kADC0_RST_SHIFT_RSTn      = ((1U << 8U) | 2U),  /*!< ADC0      reset control */
+    kADC1_RST_SHIFT_RSTn      = ((1U << 8U) | 3U),  /*!< ADC1      reset control */
+    kCMP1_RST_SHIFT_RSTn      = ((1U << 8U) | 5U),  /*!< CMP1      reset control */
+    kCMP2_RST_SHIFT_RSTn      = ((1U << 8U) | 6U),  /*!< CMP2      reset control */
+    kOPAMP0_RST_SHIFT_RSTn    = ((1U << 8U) | 8U),  /*!< OPAMP0    reset control */
+    kOPAMP1_RST_SHIFT_RSTn    = ((1U << 8U) | 9U),  /*!< OPAMP1    reset control */
+    kOPAMP2_RST_SHIFT_RSTn    = ((1U << 8U) | 10U), /*!< OPAMP2    reset control */
+    kPORT0_RST_SHIFT_RSTn     = ((1U << 8U) | 12U), /*!< PORT0     reset control */
+    kPORT1_RST_SHIFT_RSTn     = ((1U << 8U) | 13U), /*!< PORT1     reset control */
+    kPORT2_RST_SHIFT_RSTn     = ((1U << 8U) | 14U), /*!< PORT2     reset control */
+    kPORT3_RST_SHIFT_RSTn     = ((1U << 8U) | 15U), /*!< PORT3     reset control */
+    kPORT4_RST_SHIFT_RSTn     = ((1U << 8U) | 16U), /*!< PORT4     reset control */
+    kFLEXCAN0_RST_SHIFT_RSTn  = ((1U << 8U) | 18U), /*!< FLEXCAN0  reset control */
+    kGPIO0_RST_SHIFT_RSTn     = ((2U << 8U) | 4U),  /*!< GPIO0     reset control */
+    kGPIO1_RST_SHIFT_RSTn     = ((2U << 8U) | 5U),  /*!< GPIO1     reset control */
+    kGPIO2_RST_SHIFT_RSTn     = ((2U << 8U) | 6U),  /*!< GPIO2     reset control */
+    kGPIO3_RST_SHIFT_RSTn     = ((2U << 8U) | 7U),  /*!< GPIO3     reset control */
+    kGPIO4_RST_SHIFT_RSTn     = ((2U << 8U) | 8U),  /*!< GPIO4     reset control */
+    kMAU0_RST_SHIFT_RSTn      = ((2U << 8U) | 9U),  /*!< MAU0      reset control */
+    NotAvail_RSTn             = (0xFFFFU),          /*!< No        reset control */
+} SYSCON_RSTn_t;
+
+/** Array initializers with peripheral reset bits **/
+/*! @brief Reset bits for AOI peripheral */
+#define AOI_RSTS {kAOI0_RST_SHIFT_RSTn, kAOI1_RST_SHIFT_RSTn}
+/*! @brief Reset bits for ADC peripheral */
+#define ADC_RSTS {kADC0_RST_SHIFT_RSTn, kADC1_RST_SHIFT_RSTn}
+/*! @brief Reset bits for CRC peripheral */
+#define CRC_RSTS {kCRC0_RST_SHIFT_RSTn}
+/*! @brief Reset bits for CTIMER peripheral */
+#define CTIMER_RSTS {kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn}
+/*! @brief Reset bits for DMA peripheral */
+#define DMA_RSTS_N {kDMA0_RST_SHIFT_RSTn}
+/*! @brief Reset bits for EIM peripheral */
+#define EIM_RSTS_N {kEIM0_RST_SHIFT_RSTn}
+/*! @brief Reset bits for ERM peripheral */
+#define ERM_RSTS_N {kERM0_RST_SHIFT_RSTn}
+/*! @brief Reset bits for EQDC peripheral */
+#define EQDC_RSTS {kQDC0_RST_SHIFT_RSTn, kQDC1_RST_SHIFT_RSTn}
+/*! @brief Reset bits for FLEXCAN peripheral */
+#define FLEXCAN_RSTS_N {kFLEXCAN0_RST_SHIFT_RSTn}
+/*! @brief Reset bits for FLEXPWM peripheral */
+#define FLEXPWM_RSTS_N {kFLEXPWM0_RST_SHIFT_RSTn, kFLEXPWM1_RST_SHIFT_RSTn}
+/*! @brief Reset bits for FREQME peripheral */
+#define FREQME_RSTS_N {kFREQME_RST_SHIFT_RSTn}
+/*! @brief Reset bits for GPIO peripheral */
+#define GPIO_RSTS_N \
+    {kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, kGPIO4_RST_SHIFT_RSTn}
+/*! @brief Reset bits for INPUTMUX peripheral */
+#define INPUTMUX_RSTS {kINPUTMUX0_RST_SHIFT_RSTn}
+/*! @brief Reset bits for LPUART peripheral */
+#define LPUART_RSTS              \
+    {                            \
+        kLPUART0_RST_SHIFT_RSTn, \
+        kLPUART1_RST_SHIFT_RSTn, \
+        kLPUART2_RST_SHIFT_RSTn, \
+        kLPUART3_RST_SHIFT_RSTn, \
+    }
+/*! @brief Reset bits for LPSPI peripheral */
+#define LPSPI_RSTS {kLPSPI0_RST_SHIFT_RSTn, kLPSPI1_RST_SHIFT_RSTn}
+/*! @brief Reset bits for LPI2C peripheral */
+#define LPI2C_RSTS {kLPI2C0_RST_SHIFT_RSTn, kLPI2C1_RST_SHIFT_RSTn}
+/*! @brief Reset bits for LPCMP peripheral */
+#define LPCMP_RSTS {NotAvail_RSTn, kCMP1_RST_SHIFT_RSTn, kCMP2_RST_SHIFT_RSTn}
+/*! @brief Reset bits for MAU peripheral */
+#define MAU_RSTS {kMAU0_RST_SHIFT_RSTn}
+/*! @brief Reset bits for OPAMP peripheral */
+#define OPAMP_RSTS {kOPAMP0_RST_SHIFT_RSTn, kOPAMP1_RST_SHIFT_RSTn, kOPAMP2_RST_SHIFT_RSTn}
+/*! @brief Reset bits for OSTIMER peripheral */
+#define OSTIMER_RSTS {kOSTIMER0_RST_SHIFT_RSTn}
+/*! @brief Reset bits for PORT peripheral */
+#define PORT_RSTS_N \
+    {kPORT0_RST_SHIFT_RSTn, kPORT1_RST_SHIFT_RSTn, kPORT2_RST_SHIFT_RSTn, kPORT3_RST_SHIFT_RSTn, kPORT4_RST_SHIFT_RSTn}
+/*! @brief Reset bits for SMARTDMA peripheral */
+#define SMARTDMA_RSTS {kSMART_DMA_RST_SHIFT_RSTn}
+/*! @brief Reset bits for UTICK peripheral */
+#define UTICK_RSTS {kUTICK0_RST_SHIFT_RSTn}
+
+typedef SYSCON_RSTn_t reset_ip_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * @param peripheral Assert reset to this peripheral. The enum argument contains
+ * encoding of reset register and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * @param peripheral Clear reset to this peripheral. The enum argument contains
+ * encoding of reset register and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * @param peripheral Peripheral to reset. The enum argument contains encoding of
+ * reset register and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Release peripheral module.
+ *
+ * Release peripheral module.
+ *
+ * @param peripheral Peripheral to release. The enum argument contains encoding
+ * of reset register and reset bit position in the reset register.
+ */
+static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)
+{
+    RESET_SetPeripheralReset(peripheral);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_RESET_H_ */
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_trdc_soc.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_trdc_soc.h
new file mode 100644
index 0000000000..aa4194892f
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_trdc_soc.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_TRDC_SOC_H_
+#define _FSL_TRDC_SOC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup trdc_soc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.trdc_soc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Driver version 2.0.0. */
+#define FSL_TRDC_SOC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#define TRDC_MBC_MEM_GLBCFG_NBLKS_MASK      0x000003FFUL
+#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_MASK  0x001F0000UL
+#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT 16U
+#define TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL(x)  (((uint32_t)(x) & 0xFUL) << 8U)
+#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL(x) (((uint32_t)(x) & 0x1UL) << 16U)
+
+/*!@brief TRDC feature */
+#define FSL_FEATURE_TRDC_DOMAIN_COUNT 1
+
+/*!@brief TRDC base address convert macro */
+#define TRDC_MBC_COUNT 1
+/*!@brief MBC register offset in TRDC_Type structure. */
+#define TRDC_MBC_OFFSET(x) 0x0000
+/*!@brief Offset between two MBC control block, useless if there is only one. */
+#define TRDC_MBC_ARRAY_STEP 0U
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _FSL_TRDC_SOC_H_ */
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/fsl_device_registers.h
new file mode 100644
index 0000000000..895514b603
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/fsl_device_registers.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2025 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/startup_MCXA344.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/startup_MCXA344.c
new file mode 100644
index 0000000000..ecb65b35a3
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/startup_MCXA344.c
@@ -0,0 +1,1464 @@
+//*****************************************************************************
+// MCXA344 startup code
+//
+// Version : 060825
+//*****************************************************************************
+//
+// Copyright 2016-2025 NXP
+//
+// SPDX-License-Identifier: BSD-3-Clause
+//*****************************************************************************
+#include <stdint.h>
+
+#if defined(DEBUG)
+#if defined(__GNUC__)
+#pragma GCC push_options
+#pragma GCC optimize("Og")
+#endif //(__GNUC__)
+#endif //(DEBUG)
+
+#if defined(__cplusplus)
+#if defined(__MCUXPRESSO)
+#if defined(__REDLIB__)
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+extern void __libc_init_array(void);
+}
+#endif //(__REDLIB__)
+#endif //(__MCUXPRESSO)
+#endif //(__cplusplus)
+
+#define WEAK __attribute__((weak))
+#if defined(__MCUXPRESSO)
+#define WEAK_AV __attribute__((weak, section(".after_vectors")))
+#else
+#define WEAK_AV __attribute__((weak))
+#endif //(__MCUXPRESSO)
+#define ALIAS(f) __attribute__((weak, alias(#f)))
+
+//*****************************************************************************
+#if defined(__cplusplus)
+extern "C" {
+#endif //(__cplusplus)
+
+//*****************************************************************************
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+//*****************************************************************************
+//*****************************************************************************
+// Declaration of external SystemInit function
+//*****************************************************************************
+extern void SystemInit(void);
+
+//*****************************************************************************
+// Forward declaration of the core exception handlers.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions.
+// If your application is a C++ one, then any interrupt handlers defined
+// in C++ files within in your main application will need to have C linkage
+// rather than C++ linkage. To do this, make sure that you are using extern "C"
+// { .... } around the interrupt handler within your main application code.
+//*****************************************************************************
+#if defined(__MCUXPRESSO)
+void ResetISR(void);
+#else
+void Reset_Handler(void);
+#endif //(__MCUXPRESSO)
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SecureFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void DefaultISR(void);
+
+//*****************************************************************************
+// Forward declaration of the application IRQ handlers. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over weak definitions below
+//*****************************************************************************
+WEAK void Reserved16_IRQHandler(void);
+WEAK void CMC_IRQHandler(void);
+WEAK void DMA_CH0_IRQHandler(void);
+WEAK void DMA_CH1_IRQHandler(void);
+WEAK void DMA_CH2_IRQHandler(void);
+WEAK void DMA_CH3_IRQHandler(void);
+WEAK void DMA_CH4_IRQHandler(void);
+WEAK void DMA_CH5_IRQHandler(void);
+WEAK void DMA_CH6_IRQHandler(void);
+WEAK void DMA_CH7_IRQHandler(void);
+WEAK void ERM0_SINGLE_BIT_IRQHandler(void);
+WEAK void ERM0_MULTI_BIT_IRQHandler(void);
+WEAK void FMU0_IRQHandler(void);
+WEAK void GLIKEY0_IRQHandler(void);
+WEAK void MBC0_IRQHandler(void);
+WEAK void SCG0_IRQHandler(void);
+WEAK void SPC0_IRQHandler(void);
+WEAK void Reserved33_IRQHandler(void);
+WEAK void WUU0_IRQHandler(void);
+WEAK void CAN0_IRQHandler(void);
+WEAK void Reserved36_IRQHandler(void);
+WEAK void Reserved37_IRQHandler(void);
+WEAK void Reserved38_IRQHandler(void);
+WEAK void Reserved39_IRQHandler(void);
+WEAK void Reserved40_IRQHandler(void);
+WEAK void Reserved41_IRQHandler(void);
+WEAK void LPI2C0_IRQHandler(void);
+WEAK void LPI2C1_IRQHandler(void);
+WEAK void LPSPI0_IRQHandler(void);
+WEAK void LPSPI1_IRQHandler(void);
+WEAK void Reserved46_IRQHandler(void);
+WEAK void LPUART0_IRQHandler(void);
+WEAK void LPUART1_IRQHandler(void);
+WEAK void LPUART2_IRQHandler(void);
+WEAK void LPUART3_IRQHandler(void);
+WEAK void Reserved51_IRQHandler(void);
+WEAK void Reserved52_IRQHandler(void);
+WEAK void Reserved53_IRQHandler(void);
+WEAK void CDOG0_IRQHandler(void);
+WEAK void CTIMER0_IRQHandler(void);
+WEAK void CTIMER1_IRQHandler(void);
+WEAK void CTIMER2_IRQHandler(void);
+WEAK void Reserved58_IRQHandler(void);
+WEAK void Reserved59_IRQHandler(void);
+WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void);
+WEAK void FLEXPWM0_FAULT_IRQHandler(void);
+WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void);
+WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void);
+WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void);
+WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void);
+WEAK void EQDC0_COMPARE_IRQHandler(void);
+WEAK void EQDC0_HOME_IRQHandler(void);
+WEAK void EQDC0_WATCHDOG_IRQHandler(void);
+WEAK void EQDC0_INDEX_IRQHandler(void);
+WEAK void FREQME0_IRQHandler(void);
+WEAK void LPTMR0_IRQHandler(void);
+WEAK void Reserved72_IRQHandler(void);
+WEAK void OS_EVENT_IRQHandler(void);
+WEAK void WAKETIMER0_IRQHandler(void);
+WEAK void UTICK0_IRQHandler(void);
+WEAK void WWDT0_IRQHandler(void);
+WEAK void Reserved77_IRQHandler(void);
+WEAK void ADC0_IRQHandler(void);
+WEAK void ADC1_IRQHandler(void);
+WEAK void CMP0_IRQHandler(void);
+WEAK void CMP1_IRQHandler(void);
+WEAK void CMP2_IRQHandler(void);
+WEAK void Reserved83_IRQHandler(void);
+WEAK void Reserved84_IRQHandler(void);
+WEAK void Reserved85_IRQHandler(void);
+WEAK void Reserved86_IRQHandler(void);
+WEAK void GPIO0_IRQHandler(void);
+WEAK void GPIO1_IRQHandler(void);
+WEAK void GPIO2_IRQHandler(void);
+WEAK void GPIO3_IRQHandler(void);
+WEAK void GPIO4_IRQHandler(void);
+WEAK void Reserved92_IRQHandler(void);
+WEAK void Reserved93_IRQHandler(void);
+WEAK void Reserved94_IRQHandler(void);
+WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void);
+WEAK void FLEXPWM1_FAULT_IRQHandler(void);
+WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void);
+WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void);
+WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void);
+WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void);
+WEAK void EQDC1_COMPARE_IRQHandler(void);
+WEAK void EQDC1_HOME_IRQHandler(void);
+WEAK void EQDC1_WATCHDOG_IRQHandler(void);
+WEAK void EQDC1_INDEX_IRQHandler(void);
+WEAK void Reserved105_IRQHandler(void);
+WEAK void Reserved106_IRQHandler(void);
+WEAK void Reserved107_IRQHandler(void);
+WEAK void Reserved108_IRQHandler(void);
+WEAK void Reserved109_IRQHandler(void);
+WEAK void Reserved110_IRQHandler(void);
+WEAK void Reserved111_IRQHandler(void);
+WEAK void Reserved112_IRQHandler(void);
+WEAK void Reserved113_IRQHandler(void);
+WEAK void Reserved114_IRQHandler(void);
+WEAK void Reserved115_IRQHandler(void);
+WEAK void Reserved116_IRQHandler(void);
+WEAK void Reserved117_IRQHandler(void);
+WEAK void Reserved118_IRQHandler(void);
+WEAK void Reserved119_IRQHandler(void);
+WEAK void Reserved120_IRQHandler(void);
+WEAK void Reserved121_IRQHandler(void);
+WEAK void Reserved122_IRQHandler(void);
+WEAK void MAU_IRQHandler(void);
+WEAK void SMARTDMA_IRQHandler(void);
+WEAK void Reserved125_IRQHandler(void);
+WEAK void Reserved126_IRQHandler(void);
+WEAK void Reserved127_IRQHandler(void);
+WEAK void Reserved128_IRQHandler(void);
+WEAK void Reserved129_IRQHandler(void);
+WEAK void Reserved130_IRQHandler(void);
+WEAK void Reserved131_IRQHandler(void);
+WEAK void Reserved132_IRQHandler(void);
+WEAK void Reserved133_IRQHandler(void);
+WEAK void Reserved134_IRQHandler(void);
+WEAK void RTC_IRQHandler(void);
+WEAK void RTC_1HZ_IRQHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the driver IRQ handlers. These are aliased
+// to the DefaultISR, which is a 'forever' loop. When the driver
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//*****************************************************************************
+void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CMC_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR);
+void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved33_DriverIRQHandler(void) ALIAS(DefaultISR);
+void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved39_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved40_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved51_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved52_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved58_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR);
+void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR);
+void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CMP2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved83_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved93_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved94_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved111_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR);
+void MAU_DriverIRQHandler(void) ALIAS(DefaultISR);
+void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved125_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR);
+void RTC_DriverIRQHandler(void) ALIAS(DefaultISR);
+void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR);
+
+//*****************************************************************************
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//*****************************************************************************
+#if defined(__MCUXPRESSO)
+#if defined(__REDLIB__)
+extern void __main(void);
+#else
+extern int main(void);
+#endif //(__REDLIB__)
+#elif defined(__ICCARM__)
+extern void __iar_program_start(void);
+#elif defined(__GNUC__)
+#if defined(__REDLIB__)
+extern void __main(void);
+#else
+extern void _start(void);
+#endif //(__REDLIB__)
+#else
+#error Unsupported toolchain!
+#endif //(__MCUXPRESSO)
+
+//*****************************************************************************
+// External declaration for the pointer from the Linker Script
+//*****************************************************************************
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[];
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+#define _vStackTop  Image$$ARM_LIB_STACK$$ZI$$Limit
+#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base
+#elif defined(__MCUXPRESSO)
+extern void _vStackTop(void);
+extern void _vStackBase(void);
+#define Reset_Handler ResetISR // To be compatible with other compilers
+#elif defined(__ICCARM__)
+#pragma segment = "CSTACK"
+#define _vStackTop  __section_end("CSTACK")
+#define _vStackBase __section_begin("CSTACK")
+#elif defined(__GNUC__)
+extern uint32_t __StackTop[];
+extern uint32_t __StackLimit[];
+
+#define _vStackTop  __StackTop
+#define _vStackBase __StackLimit
+
+extern uint32_t __etext[];
+extern uint32_t __data_start__[];
+extern uint32_t __data_end__[];
+
+extern uint32_t __bss_start__[];
+extern uint32_t __bss_end__[];
+#else
+#error Unsupported toolchain!
+#endif //(__CC_ARM) || (__ARMCC_VERSION)
+
+//*****************************************************************************
+#if defined(__cplusplus)
+} // extern "C"
+#endif //(__cplusplus)
+//*****************************************************************************
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//*****************************************************************************
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+extern void (*const __Vectors[])(void);
+#define __vector_table __Vectors
+__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = {
+#elif defined(__MCUXPRESSO)
+extern void (*const g_pfnVectors[])(void);
+extern void *__Vectors __attribute__((alias("g_pfnVectors")));
+#define __vector_table g_pfnVectors
+__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = {
+#elif defined(__ICCARM__)
+extern void (*const __vector_table[])(void);
+/* The vector table is not needed for initialization. */
+extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table")));
+__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = {
+#elif defined(__GNUC__)
+extern void (*const __isr_vector[])(void);
+#define __vector_table __isr_vector
+__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = {
+#else
+#error Unsupported toolchain!
+#endif //(__CC_ARM) || (__ARMCC_VERSION)
+    // Core Level - CM33
+    (void (*)())((uint32_t)_vStackTop), // The initial stack pointer
+    Reset_Handler,                      // The reset handler
+
+    NMI_Handler,                        // NMI Handler
+    HardFault_Handler,                  // Hard Fault Handler
+    MemManage_Handler,                  // MPU Fault Handler
+    BusFault_Handler,                   // Bus Fault Handler
+    UsageFault_Handler,                 // Usage Fault Handler
+    SecureFault_Handler,                // Secure Fault Handler
+    0,                                  // Reserved
+    0,                                  // Reserved
+    0,                                  // Reserved
+    SVC_Handler,                        // SVCall Handler
+    DebugMon_Handler,                   // Debug Monitor Handler
+    0,                                  // Reserved
+    PendSV_Handler,                     // PendSV Handler
+    SysTick_Handler,                    // SysTick Handler
+
+    // Chip Level - MCXA344
+    Reserved16_IRQHandler,            // 16 : Reserved interrupt
+    CMC_IRQHandler,                   // 17 : Core Mode Controller interrupt
+    DMA_CH0_IRQHandler,               // 18 : DMA3_0_CH0 error or transfer complete
+    DMA_CH1_IRQHandler,               // 19 : DMA3_0_CH1 error or transfer complete
+    DMA_CH2_IRQHandler,               // 20 : DMA3_0_CH2 error or transfer complete
+    DMA_CH3_IRQHandler,               // 21 : DMA3_0_CH3 error or transfer complete
+    DMA_CH4_IRQHandler,               // 22 : DMA3_0_CH4 error or transfer complete
+    DMA_CH5_IRQHandler,               // 23 : DMA3_0_CH5 error or transfer complete
+    DMA_CH6_IRQHandler,               // 24 : DMA3_0_CH6 error or transfer complete
+    DMA_CH7_IRQHandler,               // 25 : DMA3_0_CH7 error or transfer complete
+    ERM0_SINGLE_BIT_IRQHandler,       // 26 : ERM Single Bit error interrupt
+    ERM0_MULTI_BIT_IRQHandler,        // 27 : ERM Multi Bit error interrupt
+    FMU0_IRQHandler,                  // 28 : Flash Management Unit interrupt
+    GLIKEY0_IRQHandler,               // 29 : GLIKEY Interrupt
+    MBC0_IRQHandler,                  // 30 : MBC secure violation interrupt
+    SCG0_IRQHandler,                  // 31 : System Clock Generator interrupt
+    SPC0_IRQHandler,                  // 32 : System Power Controller interrupt
+    Reserved33_IRQHandler,            // 33 : Reserved interrupt
+    WUU0_IRQHandler,                  // 34 : Wake Up Unit interrupt
+    CAN0_IRQHandler,                  // 35 : Controller Area Network 0 interrupt
+    Reserved36_IRQHandler,            // 36 : Reserved interrupt
+    Reserved37_IRQHandler,            // 37 : Reserved interrupt
+    Reserved38_IRQHandler,            // 38 : Reserved interrupt
+    Reserved39_IRQHandler,            // 39 : Reserved interrupt
+    Reserved40_IRQHandler,            // 40 : Reserved interrupt
+    Reserved41_IRQHandler,            // 41 : Reserved interrupt
+    LPI2C0_IRQHandler,                // 42 : Low-Power Inter Integrated Circuit 0 interrupt
+    LPI2C1_IRQHandler,                // 43 : Low-Power Inter Integrated Circuit 1 interrupt
+    LPSPI0_IRQHandler,                // 44 : Low-Power Serial Peripheral Interface 0 interrupt
+    LPSPI1_IRQHandler,                // 45 : Low-Power Serial Peripheral Interface 1 interrupt
+    Reserved46_IRQHandler,            // 46 : Reserved interrupt
+    LPUART0_IRQHandler,               // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt
+    LPUART1_IRQHandler,               // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt
+    LPUART2_IRQHandler,               // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt
+    LPUART3_IRQHandler,               // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt
+    Reserved51_IRQHandler,            // 51 : Reserved interrupt
+    Reserved52_IRQHandler,            // 52 : Reserved interrupt
+    Reserved53_IRQHandler,            // 53 : Reserved interrupt
+    CDOG0_IRQHandler,                 // 54 : Code Watchdog Timer 0 interrupt
+    CTIMER0_IRQHandler,               // 55 : Standard counter/timer 0 interrupt
+    CTIMER1_IRQHandler,               // 56 : Standard counter/timer 1 interrupt
+    CTIMER2_IRQHandler,               // 57 : Standard counter/timer 2 interrupt
+    Reserved58_IRQHandler,            // 58 : Reserved interrupt
+    Reserved59_IRQHandler,            // 59 : Reserved interrupt
+    FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt
+    FLEXPWM0_FAULT_IRQHandler,        // 61 : FlexPWM0_fault interrupt
+    FLEXPWM0_SUBMODULE0_IRQHandler,   // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt
+    FLEXPWM0_SUBMODULE1_IRQHandler,   // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt
+    FLEXPWM0_SUBMODULE2_IRQHandler,   // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt
+    FLEXPWM0_SUBMODULE3_IRQHandler,   // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt
+    EQDC0_COMPARE_IRQHandler,         // 66 : Compare
+    EQDC0_HOME_IRQHandler,            // 67 : Home
+    EQDC0_WATCHDOG_IRQHandler,        // 68 : Watchdog / Simultaneous A and B Change
+    EQDC0_INDEX_IRQHandler,           // 69 : Index / Roll Over / Roll Under
+    FREQME0_IRQHandler,               // 70 : Frequency Measurement interrupt
+    LPTMR0_IRQHandler,                // 71 : Low Power Timer 0 interrupt
+    Reserved72_IRQHandler,            // 72 : Reserved interrupt
+    OS_EVENT_IRQHandler,              // 73 : OS event timer interrupt
+    WAKETIMER0_IRQHandler,            // 74 : Wake Timer Interrupt
+    UTICK0_IRQHandler,                // 75 : Micro-Tick Timer interrupt
+    WWDT0_IRQHandler,                 // 76 : Windowed Watchdog Timer 0 interrupt
+    Reserved77_IRQHandler,            // 77 : Reserved interrupt
+    ADC0_IRQHandler,                  // 78 : Analog-to-Digital Converter 0 interrupt
+    ADC1_IRQHandler,                  // 79 : Analog-to-Digital Converter 1 interrupt
+    CMP0_IRQHandler,                  // 80 : Comparator 0 interrupt
+    CMP1_IRQHandler,                  // 81 : Comparator 1 interrupt
+    CMP2_IRQHandler,                  // 82 : Comparator 2 interrupt
+    Reserved83_IRQHandler,            // 83 : Reserved interrupt
+    Reserved84_IRQHandler,            // 84 : Reserved interrupt
+    Reserved85_IRQHandler,            // 85 : Reserved interrupt
+    Reserved86_IRQHandler,            // 86 : Reserved interrupt
+    GPIO0_IRQHandler,                 // 87 : General Purpose Input/Output interrupt 0
+    GPIO1_IRQHandler,                 // 88 : General Purpose Input/Output interrupt 1
+    GPIO2_IRQHandler,                 // 89 : General Purpose Input/Output interrupt 2
+    GPIO3_IRQHandler,                 // 90 : General Purpose Input/Output interrupt 3
+    GPIO4_IRQHandler,                 // 91 : General Purpose Input/Output interrupt 4
+    Reserved92_IRQHandler,            // 92 : Reserved interrupt
+    Reserved93_IRQHandler,            // 93 : Reserved interrupt
+    Reserved94_IRQHandler,            // 94 : Reserved interrupt
+    FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt
+    FLEXPWM1_FAULT_IRQHandler,        // 96 : FlexPWM1_fault interrupt
+    FLEXPWM1_SUBMODULE0_IRQHandler,   // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt
+    FLEXPWM1_SUBMODULE1_IRQHandler,   // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt
+    FLEXPWM1_SUBMODULE2_IRQHandler,   // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt
+    FLEXPWM1_SUBMODULE3_IRQHandler,   // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt
+    EQDC1_COMPARE_IRQHandler,         // 101: Compare
+    EQDC1_HOME_IRQHandler,            // 102: Home
+    EQDC1_WATCHDOG_IRQHandler,        // 103: Watchdog / Simultaneous A and B Change
+    EQDC1_INDEX_IRQHandler,           // 104: Index / Roll Over / Roll Under
+    Reserved105_IRQHandler,           // 105: Reserved interrupt
+    Reserved106_IRQHandler,           // 106: Reserved interrupt
+    Reserved107_IRQHandler,           // 107: Reserved interrupt
+    Reserved108_IRQHandler,           // 108: Reserved interrupt
+    Reserved109_IRQHandler,           // 109: Reserved interrupt
+    Reserved110_IRQHandler,           // 110: Reserved interrupt
+    Reserved111_IRQHandler,           // 111: Reserved interrupt
+    Reserved112_IRQHandler,           // 112: Reserved interrupt
+    Reserved113_IRQHandler,           // 113: Reserved interrupt
+    Reserved114_IRQHandler,           // 114: Reserved interrupt
+    Reserved115_IRQHandler,           // 115: Reserved interrupt
+    Reserved116_IRQHandler,           // 116: Reserved interrupt
+    Reserved117_IRQHandler,           // 117: Reserved interrupt
+    Reserved118_IRQHandler,           // 118: Reserved interrupt
+    Reserved119_IRQHandler,           // 119: Reserved interrupt
+    Reserved120_IRQHandler,           // 120: Reserved interrupt
+    Reserved121_IRQHandler,           // 121: Reserved interrupt
+    Reserved122_IRQHandler,           // 122: Reserved interrupt
+    MAU_IRQHandler,                   // 123: MAU interrupt
+    SMARTDMA_IRQHandler,              // 124: SmartDMA interrupt
+    Reserved125_IRQHandler,           // 125: Reserved interrupt
+    Reserved126_IRQHandler,           // 126: Reserved interrupt
+    Reserved127_IRQHandler,           // 127: Reserved interrupt
+    Reserved128_IRQHandler,           // 128: Reserved interrupt
+    Reserved129_IRQHandler,           // 129: Reserved interrupt
+    Reserved130_IRQHandler,           // 130: Reserved interrupt
+    Reserved131_IRQHandler,           // 131: Reserved interrupt
+    Reserved132_IRQHandler,           // 132: Reserved interrupt
+    Reserved133_IRQHandler,           // 133: Reserved interrupt
+    Reserved134_IRQHandler,           // 134: Reserved interrupt
+    RTC_IRQHandler,                   // 135: RTC alarm interrupt
+    RTC_1HZ_IRQHandler,               // 136: RTC 1Hz interrupt
+};                                     /* End of __vector_table */
+
+#if defined(__MCUXPRESSO)
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors")));
+void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128)));
+unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors);
+#endif //(ENABLE_RAM_VECTOR_TABLE)
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart,
+                                                                    unsigned int start,
+                                                                    unsigned int len)
+{
+    unsigned int *pulDest = (unsigned int *)start;
+    unsigned int *pulSrc  = (unsigned int *)romstart;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = *pulSrc++;
+}
+
+__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len)
+{
+    unsigned int *pulDest = (unsigned int *)start;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+#endif //(__MCUXPRESSO)
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+__attribute__ ((used, section("InRoot$$Sections")))
+__attribute__ ((naked))
+#elif defined(__MCUXPRESSO)
+__attribute__ ((naked, section(".after_vectors.reset")))
+#elif defined(__ICCARM__)
+__stackless
+#elif defined(__GNUC__)
+__attribute__ ((naked))
+#endif //(__CC_ARM) || (__ARMCC_VERSION)
+void Reset_Handler(void)
+{
+    // Disable interrupts
+    __asm volatile("cpsid i");
+    // Config VTOR & MSP register
+    __asm volatile(
+        "LDR R0, =0xE000ED08  \n"
+        "STR %0, [R0]         \n"
+        "LDR R1, [%0]         \n"
+        "MSR MSP, R1          \n"
+        "MSR MSPLIM, %1       \n"
+        :
+        : "r"(__vector_table), "r"(_vStackBase)
+        : "r0", "r1");
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+    __asm volatile(
+        "LDR R0, =SystemInit \n"
+        "BLX R0              \n"
+        "cpsie i             \n"
+        "LDR R0, =__main     \n"
+        "BX  R0              \n");
+#elif defined(__MCUXPRESSO)
+    SystemInit();
+
+    //
+    // Copy the data sections from flash to SRAM.
+    //
+    unsigned int LoadAddr, ExeAddr, SectionLen;
+    unsigned int *SectionTableAddr;
+
+    // Load base address of Global Section Table
+    SectionTableAddr = &__data_section_table;
+
+    // Copy the data sections from flash to SRAM.
+    while (SectionTableAddr < &__data_section_table_end)
+    {
+        LoadAddr   = *SectionTableAddr++;
+        ExeAddr    = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        data_init(LoadAddr, ExeAddr, SectionLen);
+    }
+
+    // At this point, SectionTableAddr = &__bss_section_table;
+    // Zero fill the bss segment
+    while (SectionTableAddr < &__bss_section_table_end)
+    {
+        ExeAddr    = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        bss_init(ExeAddr, SectionLen);
+    }
+
+#if defined(__cplusplus)
+    //
+    // Call C++ library initialisation
+    //
+    __libc_init_array();
+#endif //(__cplusplus)
+
+    // Reenable interrupts
+    __asm volatile("cpsie i");
+
+#if defined(__REDLIB__)
+    // Call the Redlib library, which in turn calls main()
+    __main();
+#else
+    main();
+#endif //(__REDLIB__)
+#elif defined(__ICCARM__)
+    SystemInit();
+    // Reenable interrupts
+    __asm volatile("cpsie i");
+
+    __iar_program_start();
+#elif defined(__GNUC__)
+#if !defined(__NO_SYSTEM_INIT)
+    SystemInit();
+#endif //(__NO_SYSTEM_INIT)
+    /*     Loop to copy data from read only memory to RAM. The ranges
+     *      of copy from/to are specified by following symbols evaluated in
+     *      linker script.
+     *      1. __etext/_data_start__/__data_end__
+     *      Note: All must be aligned to 4 bytes boundary.
+     */
+    uint32_t *pDataSrc, *pDataDest;
+
+    pDataSrc  = (uint32_t *)__etext;
+    pDataDest = (uint32_t *)__data_start__;
+    while (pDataDest < __data_end__)
+    {
+        *pDataDest++ = *pDataSrc++;
+    }
+#if defined(__STARTUP_CLEAR_BSS)
+    /*     This part of work usually is done in C library startup code. Otherwise,
+     *     define this macro to enable it in this startup.
+     *
+     *     Loop to zero out BSS section, which uses following symbols
+     *     in linker script:
+     *      __bss_start__: start of BSS section. Must align to 4
+     *      __bss_end__: end of BSS section. Must align to 4
+     */
+    pDataDest = (uint32_t *)__bss_start__;
+    while (pDataDest < __bss_end__)
+    {
+        *pDataDest++ = 0U;
+    }
+#endif //(__STARTUP_CLEAR_BSS)
+
+    __asm volatile("cpsie i");
+
+#if !defined(__START)
+#if defined(__REDLIB__)
+#define __START __main
+#else
+#define __START _start
+#endif //(__REDLIB__)
+#endif //(__START)
+
+    __START();
+
+#endif //(__GNUC__)
+
+    //
+    // main() shouldn't return, but if it does, we'll just enter an infinite loop
+    //
+#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM)
+    while (1)
+    {
+        ;
+    }
+#endif //!(__ARMCC_VERSION) && !(__CC_ARM)
+}
+
+//*****************************************************************************
+// Default core exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+WEAK_AV void NMI_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void HardFault_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void MemManage_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void BusFault_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void UsageFault_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void SecureFault_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void SVC_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void DebugMon_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void PendSV_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void SysTick_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+//*****************************************************************************
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//*****************************************************************************
+WEAK_AV void DefaultISR(void)
+{
+    while (1)
+    {
+    }
+}
+
+//*****************************************************************************
+// Default application exception handlers. Override the ones here by defining
+// your own handler routines in your application code. These routines call
+// driver exception handlers or DefaultISR() if no driver exception
+// handler is included.
+//*****************************************************************************
+WEAK void Reserved16_IRQHandler(void)
+{
+    Reserved16_DriverIRQHandler();
+}
+
+WEAK void CMC_IRQHandler(void)
+{
+    CMC_DriverIRQHandler();
+}
+
+WEAK void DMA_CH0_IRQHandler(void)
+{
+    DMA_CH0_DriverIRQHandler();
+}
+
+WEAK void DMA_CH1_IRQHandler(void)
+{
+    DMA_CH1_DriverIRQHandler();
+}
+
+WEAK void DMA_CH2_IRQHandler(void)
+{
+    DMA_CH2_DriverIRQHandler();
+}
+
+WEAK void DMA_CH3_IRQHandler(void)
+{
+    DMA_CH3_DriverIRQHandler();
+}
+
+WEAK void DMA_CH4_IRQHandler(void)
+{
+    DMA_CH4_DriverIRQHandler();
+}
+
+WEAK void DMA_CH5_IRQHandler(void)
+{
+    DMA_CH5_DriverIRQHandler();
+}
+
+WEAK void DMA_CH6_IRQHandler(void)
+{
+    DMA_CH6_DriverIRQHandler();
+}
+
+WEAK void DMA_CH7_IRQHandler(void)
+{
+    DMA_CH7_DriverIRQHandler();
+}
+
+WEAK void ERM0_SINGLE_BIT_IRQHandler(void)
+{
+    ERM0_SINGLE_BIT_DriverIRQHandler();
+}
+
+WEAK void ERM0_MULTI_BIT_IRQHandler(void)
+{
+    ERM0_MULTI_BIT_DriverIRQHandler();
+}
+
+WEAK void FMU0_IRQHandler(void)
+{
+    FMU0_DriverIRQHandler();
+}
+
+WEAK void GLIKEY0_IRQHandler(void)
+{
+    GLIKEY0_DriverIRQHandler();
+}
+
+WEAK void MBC0_IRQHandler(void)
+{
+    MBC0_DriverIRQHandler();
+}
+
+WEAK void SCG0_IRQHandler(void)
+{
+    SCG0_DriverIRQHandler();
+}
+
+WEAK void SPC0_IRQHandler(void)
+{
+    SPC0_DriverIRQHandler();
+}
+
+WEAK void Reserved33_IRQHandler(void)
+{
+    Reserved33_DriverIRQHandler();
+}
+
+WEAK void WUU0_IRQHandler(void)
+{
+    WUU0_DriverIRQHandler();
+}
+
+WEAK void CAN0_IRQHandler(void)
+{
+    CAN0_DriverIRQHandler();
+}
+
+WEAK void Reserved36_IRQHandler(void)
+{
+    Reserved36_DriverIRQHandler();
+}
+
+WEAK void Reserved37_IRQHandler(void)
+{
+    Reserved37_DriverIRQHandler();
+}
+
+WEAK void Reserved38_IRQHandler(void)
+{
+    Reserved38_DriverIRQHandler();
+}
+
+WEAK void Reserved39_IRQHandler(void)
+{
+    Reserved39_DriverIRQHandler();
+}
+
+WEAK void Reserved40_IRQHandler(void)
+{
+    Reserved40_DriverIRQHandler();
+}
+
+WEAK void Reserved41_IRQHandler(void)
+{
+    Reserved41_DriverIRQHandler();
+}
+
+WEAK void LPI2C0_IRQHandler(void)
+{
+    LPI2C0_DriverIRQHandler();
+}
+
+WEAK void LPI2C1_IRQHandler(void)
+{
+    LPI2C1_DriverIRQHandler();
+}
+
+WEAK void LPSPI0_IRQHandler(void)
+{
+    LPSPI0_DriverIRQHandler();
+}
+
+WEAK void LPSPI1_IRQHandler(void)
+{
+    LPSPI1_DriverIRQHandler();
+}
+
+WEAK void Reserved46_IRQHandler(void)
+{
+    Reserved46_DriverIRQHandler();
+}
+
+WEAK void LPUART0_IRQHandler(void)
+{
+    LPUART0_DriverIRQHandler();
+}
+
+WEAK void LPUART1_IRQHandler(void)
+{
+    LPUART1_DriverIRQHandler();
+}
+
+WEAK void LPUART2_IRQHandler(void)
+{
+    LPUART2_DriverIRQHandler();
+}
+
+WEAK void LPUART3_IRQHandler(void)
+{
+    LPUART3_DriverIRQHandler();
+}
+
+WEAK void Reserved51_IRQHandler(void)
+{
+    Reserved51_DriverIRQHandler();
+}
+
+WEAK void Reserved52_IRQHandler(void)
+{
+    Reserved52_DriverIRQHandler();
+}
+
+WEAK void Reserved53_IRQHandler(void)
+{
+    Reserved53_DriverIRQHandler();
+}
+
+WEAK void CDOG0_IRQHandler(void)
+{
+    CDOG0_DriverIRQHandler();
+}
+
+WEAK void CTIMER0_IRQHandler(void)
+{
+    CTIMER0_DriverIRQHandler();
+}
+
+WEAK void CTIMER1_IRQHandler(void)
+{
+    CTIMER1_DriverIRQHandler();
+}
+
+WEAK void CTIMER2_IRQHandler(void)
+{
+    CTIMER2_DriverIRQHandler();
+}
+
+WEAK void Reserved58_IRQHandler(void)
+{
+    Reserved58_DriverIRQHandler();
+}
+
+WEAK void Reserved59_IRQHandler(void)
+{
+    Reserved59_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void)
+{
+    FLEXPWM0_RELOAD_ERROR_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_FAULT_IRQHandler(void)
+{
+    FLEXPWM0_FAULT_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void)
+{
+    FLEXPWM0_SUBMODULE0_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void)
+{
+    FLEXPWM0_SUBMODULE1_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void)
+{
+    FLEXPWM0_SUBMODULE2_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void)
+{
+    FLEXPWM0_SUBMODULE3_DriverIRQHandler();
+}
+
+WEAK void EQDC0_COMPARE_IRQHandler(void)
+{
+    EQDC0_COMPARE_DriverIRQHandler();
+}
+
+WEAK void EQDC0_HOME_IRQHandler(void)
+{
+    EQDC0_HOME_DriverIRQHandler();
+}
+
+WEAK void EQDC0_WATCHDOG_IRQHandler(void)
+{
+    EQDC0_WATCHDOG_DriverIRQHandler();
+}
+
+WEAK void EQDC0_INDEX_IRQHandler(void)
+{
+    EQDC0_INDEX_DriverIRQHandler();
+}
+
+WEAK void FREQME0_IRQHandler(void)
+{
+    FREQME0_DriverIRQHandler();
+}
+
+WEAK void LPTMR0_IRQHandler(void)
+{
+    LPTMR0_DriverIRQHandler();
+}
+
+WEAK void Reserved72_IRQHandler(void)
+{
+    Reserved72_DriverIRQHandler();
+}
+
+WEAK void OS_EVENT_IRQHandler(void)
+{
+    OS_EVENT_DriverIRQHandler();
+}
+
+WEAK void WAKETIMER0_IRQHandler(void)
+{
+    WAKETIMER0_DriverIRQHandler();
+}
+
+WEAK void UTICK0_IRQHandler(void)
+{
+    UTICK0_DriverIRQHandler();
+}
+
+WEAK void WWDT0_IRQHandler(void)
+{
+    WWDT0_DriverIRQHandler();
+}
+
+WEAK void Reserved77_IRQHandler(void)
+{
+    Reserved77_DriverIRQHandler();
+}
+
+WEAK void ADC0_IRQHandler(void)
+{
+    ADC0_DriverIRQHandler();
+}
+
+WEAK void ADC1_IRQHandler(void)
+{
+    ADC1_DriverIRQHandler();
+}
+
+WEAK void CMP0_IRQHandler(void)
+{
+    CMP0_DriverIRQHandler();
+}
+
+WEAK void CMP1_IRQHandler(void)
+{
+    CMP1_DriverIRQHandler();
+}
+
+WEAK void CMP2_IRQHandler(void)
+{
+    CMP2_DriverIRQHandler();
+}
+
+WEAK void Reserved83_IRQHandler(void)
+{
+    Reserved83_DriverIRQHandler();
+}
+
+WEAK void Reserved84_IRQHandler(void)
+{
+    Reserved84_DriverIRQHandler();
+}
+
+WEAK void Reserved85_IRQHandler(void)
+{
+    Reserved85_DriverIRQHandler();
+}
+
+WEAK void Reserved86_IRQHandler(void)
+{
+    Reserved86_DriverIRQHandler();
+}
+
+WEAK void GPIO0_IRQHandler(void)
+{
+    GPIO0_DriverIRQHandler();
+}
+
+WEAK void GPIO1_IRQHandler(void)
+{
+    GPIO1_DriverIRQHandler();
+}
+
+WEAK void GPIO2_IRQHandler(void)
+{
+    GPIO2_DriverIRQHandler();
+}
+
+WEAK void GPIO3_IRQHandler(void)
+{
+    GPIO3_DriverIRQHandler();
+}
+
+WEAK void GPIO4_IRQHandler(void)
+{
+    GPIO4_DriverIRQHandler();
+}
+
+WEAK void Reserved92_IRQHandler(void)
+{
+    Reserved92_DriverIRQHandler();
+}
+
+WEAK void Reserved93_IRQHandler(void)
+{
+    Reserved93_DriverIRQHandler();
+}
+
+WEAK void Reserved94_IRQHandler(void)
+{
+    Reserved94_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void)
+{
+    FLEXPWM1_RELOAD_ERROR_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_FAULT_IRQHandler(void)
+{
+    FLEXPWM1_FAULT_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void)
+{
+    FLEXPWM1_SUBMODULE0_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void)
+{
+    FLEXPWM1_SUBMODULE1_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void)
+{
+    FLEXPWM1_SUBMODULE2_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void)
+{
+    FLEXPWM1_SUBMODULE3_DriverIRQHandler();
+}
+
+WEAK void EQDC1_COMPARE_IRQHandler(void)
+{
+    EQDC1_COMPARE_DriverIRQHandler();
+}
+
+WEAK void EQDC1_HOME_IRQHandler(void)
+{
+    EQDC1_HOME_DriverIRQHandler();
+}
+
+WEAK void EQDC1_WATCHDOG_IRQHandler(void)
+{
+    EQDC1_WATCHDOG_DriverIRQHandler();
+}
+
+WEAK void EQDC1_INDEX_IRQHandler(void)
+{
+    EQDC1_INDEX_DriverIRQHandler();
+}
+
+WEAK void Reserved105_IRQHandler(void)
+{
+    Reserved105_DriverIRQHandler();
+}
+
+WEAK void Reserved106_IRQHandler(void)
+{
+    Reserved106_DriverIRQHandler();
+}
+
+WEAK void Reserved107_IRQHandler(void)
+{
+    Reserved107_DriverIRQHandler();
+}
+
+WEAK void Reserved108_IRQHandler(void)
+{
+    Reserved108_DriverIRQHandler();
+}
+
+WEAK void Reserved109_IRQHandler(void)
+{
+    Reserved109_DriverIRQHandler();
+}
+
+WEAK void Reserved110_IRQHandler(void)
+{
+    Reserved110_DriverIRQHandler();
+}
+
+WEAK void Reserved111_IRQHandler(void)
+{
+    Reserved111_DriverIRQHandler();
+}
+
+WEAK void Reserved112_IRQHandler(void)
+{
+    Reserved112_DriverIRQHandler();
+}
+
+WEAK void Reserved113_IRQHandler(void)
+{
+    Reserved113_DriverIRQHandler();
+}
+
+WEAK void Reserved114_IRQHandler(void)
+{
+    Reserved114_DriverIRQHandler();
+}
+
+WEAK void Reserved115_IRQHandler(void)
+{
+    Reserved115_DriverIRQHandler();
+}
+
+WEAK void Reserved116_IRQHandler(void)
+{
+    Reserved116_DriverIRQHandler();
+}
+
+WEAK void Reserved117_IRQHandler(void)
+{
+    Reserved117_DriverIRQHandler();
+}
+
+WEAK void Reserved118_IRQHandler(void)
+{
+    Reserved118_DriverIRQHandler();
+}
+
+WEAK void Reserved119_IRQHandler(void)
+{
+    Reserved119_DriverIRQHandler();
+}
+
+WEAK void Reserved120_IRQHandler(void)
+{
+    Reserved120_DriverIRQHandler();
+}
+
+WEAK void Reserved121_IRQHandler(void)
+{
+    Reserved121_DriverIRQHandler();
+}
+
+WEAK void Reserved122_IRQHandler(void)
+{
+    Reserved122_DriverIRQHandler();
+}
+
+WEAK void MAU_IRQHandler(void)
+{
+    MAU_DriverIRQHandler();
+}
+
+WEAK void SMARTDMA_IRQHandler(void)
+{
+    SMARTDMA_DriverIRQHandler();
+}
+
+WEAK void Reserved125_IRQHandler(void)
+{
+    Reserved125_DriverIRQHandler();
+}
+
+WEAK void Reserved126_IRQHandler(void)
+{
+    Reserved126_DriverIRQHandler();
+}
+
+WEAK void Reserved127_IRQHandler(void)
+{
+    Reserved127_DriverIRQHandler();
+}
+
+WEAK void Reserved128_IRQHandler(void)
+{
+    Reserved128_DriverIRQHandler();
+}
+
+WEAK void Reserved129_IRQHandler(void)
+{
+    Reserved129_DriverIRQHandler();
+}
+
+WEAK void Reserved130_IRQHandler(void)
+{
+    Reserved130_DriverIRQHandler();
+}
+
+WEAK void Reserved131_IRQHandler(void)
+{
+    Reserved131_DriverIRQHandler();
+}
+
+WEAK void Reserved132_IRQHandler(void)
+{
+    Reserved132_DriverIRQHandler();
+}
+
+WEAK void Reserved133_IRQHandler(void)
+{
+    Reserved133_DriverIRQHandler();
+}
+
+WEAK void Reserved134_IRQHandler(void)
+{
+    Reserved134_DriverIRQHandler();
+}
+
+WEAK void RTC_IRQHandler(void)
+{
+    RTC_DriverIRQHandler();
+}
+
+WEAK void RTC_1HZ_IRQHandler(void)
+{
+    RTC_1HZ_DriverIRQHandler();
+}
+
+//*****************************************************************************
+
+#if defined(DEBUG)
+#if defined(__GNUC__)
+#pragma GCC pop_options
+#endif //(__GNUC__)
+#endif //(DEBUG)
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/startup_MCXA344.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/startup_MCXA344.cpp
new file mode 100644
index 0000000000..ecb65b35a3
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/startup_MCXA344.cpp
@@ -0,0 +1,1464 @@
+//*****************************************************************************
+// MCXA344 startup code
+//
+// Version : 060825
+//*****************************************************************************
+//
+// Copyright 2016-2025 NXP
+//
+// SPDX-License-Identifier: BSD-3-Clause
+//*****************************************************************************
+#include <stdint.h>
+
+#if defined(DEBUG)
+#if defined(__GNUC__)
+#pragma GCC push_options
+#pragma GCC optimize("Og")
+#endif //(__GNUC__)
+#endif //(DEBUG)
+
+#if defined(__cplusplus)
+#if defined(__MCUXPRESSO)
+#if defined(__REDLIB__)
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+extern void __libc_init_array(void);
+}
+#endif //(__REDLIB__)
+#endif //(__MCUXPRESSO)
+#endif //(__cplusplus)
+
+#define WEAK __attribute__((weak))
+#if defined(__MCUXPRESSO)
+#define WEAK_AV __attribute__((weak, section(".after_vectors")))
+#else
+#define WEAK_AV __attribute__((weak))
+#endif //(__MCUXPRESSO)
+#define ALIAS(f) __attribute__((weak, alias(#f)))
+
+//*****************************************************************************
+#if defined(__cplusplus)
+extern "C" {
+#endif //(__cplusplus)
+
+//*****************************************************************************
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+//*****************************************************************************
+//*****************************************************************************
+// Declaration of external SystemInit function
+//*****************************************************************************
+extern void SystemInit(void);
+
+//*****************************************************************************
+// Forward declaration of the core exception handlers.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions.
+// If your application is a C++ one, then any interrupt handlers defined
+// in C++ files within in your main application will need to have C linkage
+// rather than C++ linkage. To do this, make sure that you are using extern "C"
+// { .... } around the interrupt handler within your main application code.
+//*****************************************************************************
+#if defined(__MCUXPRESSO)
+void ResetISR(void);
+#else
+void Reset_Handler(void);
+#endif //(__MCUXPRESSO)
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SecureFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void DefaultISR(void);
+
+//*****************************************************************************
+// Forward declaration of the application IRQ handlers. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over weak definitions below
+//*****************************************************************************
+WEAK void Reserved16_IRQHandler(void);
+WEAK void CMC_IRQHandler(void);
+WEAK void DMA_CH0_IRQHandler(void);
+WEAK void DMA_CH1_IRQHandler(void);
+WEAK void DMA_CH2_IRQHandler(void);
+WEAK void DMA_CH3_IRQHandler(void);
+WEAK void DMA_CH4_IRQHandler(void);
+WEAK void DMA_CH5_IRQHandler(void);
+WEAK void DMA_CH6_IRQHandler(void);
+WEAK void DMA_CH7_IRQHandler(void);
+WEAK void ERM0_SINGLE_BIT_IRQHandler(void);
+WEAK void ERM0_MULTI_BIT_IRQHandler(void);
+WEAK void FMU0_IRQHandler(void);
+WEAK void GLIKEY0_IRQHandler(void);
+WEAK void MBC0_IRQHandler(void);
+WEAK void SCG0_IRQHandler(void);
+WEAK void SPC0_IRQHandler(void);
+WEAK void Reserved33_IRQHandler(void);
+WEAK void WUU0_IRQHandler(void);
+WEAK void CAN0_IRQHandler(void);
+WEAK void Reserved36_IRQHandler(void);
+WEAK void Reserved37_IRQHandler(void);
+WEAK void Reserved38_IRQHandler(void);
+WEAK void Reserved39_IRQHandler(void);
+WEAK void Reserved40_IRQHandler(void);
+WEAK void Reserved41_IRQHandler(void);
+WEAK void LPI2C0_IRQHandler(void);
+WEAK void LPI2C1_IRQHandler(void);
+WEAK void LPSPI0_IRQHandler(void);
+WEAK void LPSPI1_IRQHandler(void);
+WEAK void Reserved46_IRQHandler(void);
+WEAK void LPUART0_IRQHandler(void);
+WEAK void LPUART1_IRQHandler(void);
+WEAK void LPUART2_IRQHandler(void);
+WEAK void LPUART3_IRQHandler(void);
+WEAK void Reserved51_IRQHandler(void);
+WEAK void Reserved52_IRQHandler(void);
+WEAK void Reserved53_IRQHandler(void);
+WEAK void CDOG0_IRQHandler(void);
+WEAK void CTIMER0_IRQHandler(void);
+WEAK void CTIMER1_IRQHandler(void);
+WEAK void CTIMER2_IRQHandler(void);
+WEAK void Reserved58_IRQHandler(void);
+WEAK void Reserved59_IRQHandler(void);
+WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void);
+WEAK void FLEXPWM0_FAULT_IRQHandler(void);
+WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void);
+WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void);
+WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void);
+WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void);
+WEAK void EQDC0_COMPARE_IRQHandler(void);
+WEAK void EQDC0_HOME_IRQHandler(void);
+WEAK void EQDC0_WATCHDOG_IRQHandler(void);
+WEAK void EQDC0_INDEX_IRQHandler(void);
+WEAK void FREQME0_IRQHandler(void);
+WEAK void LPTMR0_IRQHandler(void);
+WEAK void Reserved72_IRQHandler(void);
+WEAK void OS_EVENT_IRQHandler(void);
+WEAK void WAKETIMER0_IRQHandler(void);
+WEAK void UTICK0_IRQHandler(void);
+WEAK void WWDT0_IRQHandler(void);
+WEAK void Reserved77_IRQHandler(void);
+WEAK void ADC0_IRQHandler(void);
+WEAK void ADC1_IRQHandler(void);
+WEAK void CMP0_IRQHandler(void);
+WEAK void CMP1_IRQHandler(void);
+WEAK void CMP2_IRQHandler(void);
+WEAK void Reserved83_IRQHandler(void);
+WEAK void Reserved84_IRQHandler(void);
+WEAK void Reserved85_IRQHandler(void);
+WEAK void Reserved86_IRQHandler(void);
+WEAK void GPIO0_IRQHandler(void);
+WEAK void GPIO1_IRQHandler(void);
+WEAK void GPIO2_IRQHandler(void);
+WEAK void GPIO3_IRQHandler(void);
+WEAK void GPIO4_IRQHandler(void);
+WEAK void Reserved92_IRQHandler(void);
+WEAK void Reserved93_IRQHandler(void);
+WEAK void Reserved94_IRQHandler(void);
+WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void);
+WEAK void FLEXPWM1_FAULT_IRQHandler(void);
+WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void);
+WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void);
+WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void);
+WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void);
+WEAK void EQDC1_COMPARE_IRQHandler(void);
+WEAK void EQDC1_HOME_IRQHandler(void);
+WEAK void EQDC1_WATCHDOG_IRQHandler(void);
+WEAK void EQDC1_INDEX_IRQHandler(void);
+WEAK void Reserved105_IRQHandler(void);
+WEAK void Reserved106_IRQHandler(void);
+WEAK void Reserved107_IRQHandler(void);
+WEAK void Reserved108_IRQHandler(void);
+WEAK void Reserved109_IRQHandler(void);
+WEAK void Reserved110_IRQHandler(void);
+WEAK void Reserved111_IRQHandler(void);
+WEAK void Reserved112_IRQHandler(void);
+WEAK void Reserved113_IRQHandler(void);
+WEAK void Reserved114_IRQHandler(void);
+WEAK void Reserved115_IRQHandler(void);
+WEAK void Reserved116_IRQHandler(void);
+WEAK void Reserved117_IRQHandler(void);
+WEAK void Reserved118_IRQHandler(void);
+WEAK void Reserved119_IRQHandler(void);
+WEAK void Reserved120_IRQHandler(void);
+WEAK void Reserved121_IRQHandler(void);
+WEAK void Reserved122_IRQHandler(void);
+WEAK void MAU_IRQHandler(void);
+WEAK void SMARTDMA_IRQHandler(void);
+WEAK void Reserved125_IRQHandler(void);
+WEAK void Reserved126_IRQHandler(void);
+WEAK void Reserved127_IRQHandler(void);
+WEAK void Reserved128_IRQHandler(void);
+WEAK void Reserved129_IRQHandler(void);
+WEAK void Reserved130_IRQHandler(void);
+WEAK void Reserved131_IRQHandler(void);
+WEAK void Reserved132_IRQHandler(void);
+WEAK void Reserved133_IRQHandler(void);
+WEAK void Reserved134_IRQHandler(void);
+WEAK void RTC_IRQHandler(void);
+WEAK void RTC_1HZ_IRQHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the driver IRQ handlers. These are aliased
+// to the DefaultISR, which is a 'forever' loop. When the driver
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//*****************************************************************************
+void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CMC_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR);
+void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR);
+void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved33_DriverIRQHandler(void) ALIAS(DefaultISR);
+void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved39_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved40_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved51_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved52_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved58_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR);
+void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR);
+void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void CMP2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved83_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved93_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved94_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR);
+void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR);
+void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved111_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR);
+void MAU_DriverIRQHandler(void) ALIAS(DefaultISR);
+void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved125_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR);
+void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR);
+void RTC_DriverIRQHandler(void) ALIAS(DefaultISR);
+void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR);
+
+//*****************************************************************************
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//*****************************************************************************
+#if defined(__MCUXPRESSO)
+#if defined(__REDLIB__)
+extern void __main(void);
+#else
+extern int main(void);
+#endif //(__REDLIB__)
+#elif defined(__ICCARM__)
+extern void __iar_program_start(void);
+#elif defined(__GNUC__)
+#if defined(__REDLIB__)
+extern void __main(void);
+#else
+extern void _start(void);
+#endif //(__REDLIB__)
+#else
+#error Unsupported toolchain!
+#endif //(__MCUXPRESSO)
+
+//*****************************************************************************
+// External declaration for the pointer from the Linker Script
+//*****************************************************************************
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[];
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+#define _vStackTop  Image$$ARM_LIB_STACK$$ZI$$Limit
+#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base
+#elif defined(__MCUXPRESSO)
+extern void _vStackTop(void);
+extern void _vStackBase(void);
+#define Reset_Handler ResetISR // To be compatible with other compilers
+#elif defined(__ICCARM__)
+#pragma segment = "CSTACK"
+#define _vStackTop  __section_end("CSTACK")
+#define _vStackBase __section_begin("CSTACK")
+#elif defined(__GNUC__)
+extern uint32_t __StackTop[];
+extern uint32_t __StackLimit[];
+
+#define _vStackTop  __StackTop
+#define _vStackBase __StackLimit
+
+extern uint32_t __etext[];
+extern uint32_t __data_start__[];
+extern uint32_t __data_end__[];
+
+extern uint32_t __bss_start__[];
+extern uint32_t __bss_end__[];
+#else
+#error Unsupported toolchain!
+#endif //(__CC_ARM) || (__ARMCC_VERSION)
+
+//*****************************************************************************
+#if defined(__cplusplus)
+} // extern "C"
+#endif //(__cplusplus)
+//*****************************************************************************
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//*****************************************************************************
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+extern void (*const __Vectors[])(void);
+#define __vector_table __Vectors
+__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = {
+#elif defined(__MCUXPRESSO)
+extern void (*const g_pfnVectors[])(void);
+extern void *__Vectors __attribute__((alias("g_pfnVectors")));
+#define __vector_table g_pfnVectors
+__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = {
+#elif defined(__ICCARM__)
+extern void (*const __vector_table[])(void);
+/* The vector table is not needed for initialization. */
+extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table")));
+__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = {
+#elif defined(__GNUC__)
+extern void (*const __isr_vector[])(void);
+#define __vector_table __isr_vector
+__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = {
+#else
+#error Unsupported toolchain!
+#endif //(__CC_ARM) || (__ARMCC_VERSION)
+    // Core Level - CM33
+    (void (*)())((uint32_t)_vStackTop), // The initial stack pointer
+    Reset_Handler,                      // The reset handler
+
+    NMI_Handler,                        // NMI Handler
+    HardFault_Handler,                  // Hard Fault Handler
+    MemManage_Handler,                  // MPU Fault Handler
+    BusFault_Handler,                   // Bus Fault Handler
+    UsageFault_Handler,                 // Usage Fault Handler
+    SecureFault_Handler,                // Secure Fault Handler
+    0,                                  // Reserved
+    0,                                  // Reserved
+    0,                                  // Reserved
+    SVC_Handler,                        // SVCall Handler
+    DebugMon_Handler,                   // Debug Monitor Handler
+    0,                                  // Reserved
+    PendSV_Handler,                     // PendSV Handler
+    SysTick_Handler,                    // SysTick Handler
+
+    // Chip Level - MCXA344
+    Reserved16_IRQHandler,            // 16 : Reserved interrupt
+    CMC_IRQHandler,                   // 17 : Core Mode Controller interrupt
+    DMA_CH0_IRQHandler,               // 18 : DMA3_0_CH0 error or transfer complete
+    DMA_CH1_IRQHandler,               // 19 : DMA3_0_CH1 error or transfer complete
+    DMA_CH2_IRQHandler,               // 20 : DMA3_0_CH2 error or transfer complete
+    DMA_CH3_IRQHandler,               // 21 : DMA3_0_CH3 error or transfer complete
+    DMA_CH4_IRQHandler,               // 22 : DMA3_0_CH4 error or transfer complete
+    DMA_CH5_IRQHandler,               // 23 : DMA3_0_CH5 error or transfer complete
+    DMA_CH6_IRQHandler,               // 24 : DMA3_0_CH6 error or transfer complete
+    DMA_CH7_IRQHandler,               // 25 : DMA3_0_CH7 error or transfer complete
+    ERM0_SINGLE_BIT_IRQHandler,       // 26 : ERM Single Bit error interrupt
+    ERM0_MULTI_BIT_IRQHandler,        // 27 : ERM Multi Bit error interrupt
+    FMU0_IRQHandler,                  // 28 : Flash Management Unit interrupt
+    GLIKEY0_IRQHandler,               // 29 : GLIKEY Interrupt
+    MBC0_IRQHandler,                  // 30 : MBC secure violation interrupt
+    SCG0_IRQHandler,                  // 31 : System Clock Generator interrupt
+    SPC0_IRQHandler,                  // 32 : System Power Controller interrupt
+    Reserved33_IRQHandler,            // 33 : Reserved interrupt
+    WUU0_IRQHandler,                  // 34 : Wake Up Unit interrupt
+    CAN0_IRQHandler,                  // 35 : Controller Area Network 0 interrupt
+    Reserved36_IRQHandler,            // 36 : Reserved interrupt
+    Reserved37_IRQHandler,            // 37 : Reserved interrupt
+    Reserved38_IRQHandler,            // 38 : Reserved interrupt
+    Reserved39_IRQHandler,            // 39 : Reserved interrupt
+    Reserved40_IRQHandler,            // 40 : Reserved interrupt
+    Reserved41_IRQHandler,            // 41 : Reserved interrupt
+    LPI2C0_IRQHandler,                // 42 : Low-Power Inter Integrated Circuit 0 interrupt
+    LPI2C1_IRQHandler,                // 43 : Low-Power Inter Integrated Circuit 1 interrupt
+    LPSPI0_IRQHandler,                // 44 : Low-Power Serial Peripheral Interface 0 interrupt
+    LPSPI1_IRQHandler,                // 45 : Low-Power Serial Peripheral Interface 1 interrupt
+    Reserved46_IRQHandler,            // 46 : Reserved interrupt
+    LPUART0_IRQHandler,               // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt
+    LPUART1_IRQHandler,               // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt
+    LPUART2_IRQHandler,               // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt
+    LPUART3_IRQHandler,               // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt
+    Reserved51_IRQHandler,            // 51 : Reserved interrupt
+    Reserved52_IRQHandler,            // 52 : Reserved interrupt
+    Reserved53_IRQHandler,            // 53 : Reserved interrupt
+    CDOG0_IRQHandler,                 // 54 : Code Watchdog Timer 0 interrupt
+    CTIMER0_IRQHandler,               // 55 : Standard counter/timer 0 interrupt
+    CTIMER1_IRQHandler,               // 56 : Standard counter/timer 1 interrupt
+    CTIMER2_IRQHandler,               // 57 : Standard counter/timer 2 interrupt
+    Reserved58_IRQHandler,            // 58 : Reserved interrupt
+    Reserved59_IRQHandler,            // 59 : Reserved interrupt
+    FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt
+    FLEXPWM0_FAULT_IRQHandler,        // 61 : FlexPWM0_fault interrupt
+    FLEXPWM0_SUBMODULE0_IRQHandler,   // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt
+    FLEXPWM0_SUBMODULE1_IRQHandler,   // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt
+    FLEXPWM0_SUBMODULE2_IRQHandler,   // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt
+    FLEXPWM0_SUBMODULE3_IRQHandler,   // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt
+    EQDC0_COMPARE_IRQHandler,         // 66 : Compare
+    EQDC0_HOME_IRQHandler,            // 67 : Home
+    EQDC0_WATCHDOG_IRQHandler,        // 68 : Watchdog / Simultaneous A and B Change
+    EQDC0_INDEX_IRQHandler,           // 69 : Index / Roll Over / Roll Under
+    FREQME0_IRQHandler,               // 70 : Frequency Measurement interrupt
+    LPTMR0_IRQHandler,                // 71 : Low Power Timer 0 interrupt
+    Reserved72_IRQHandler,            // 72 : Reserved interrupt
+    OS_EVENT_IRQHandler,              // 73 : OS event timer interrupt
+    WAKETIMER0_IRQHandler,            // 74 : Wake Timer Interrupt
+    UTICK0_IRQHandler,                // 75 : Micro-Tick Timer interrupt
+    WWDT0_IRQHandler,                 // 76 : Windowed Watchdog Timer 0 interrupt
+    Reserved77_IRQHandler,            // 77 : Reserved interrupt
+    ADC0_IRQHandler,                  // 78 : Analog-to-Digital Converter 0 interrupt
+    ADC1_IRQHandler,                  // 79 : Analog-to-Digital Converter 1 interrupt
+    CMP0_IRQHandler,                  // 80 : Comparator 0 interrupt
+    CMP1_IRQHandler,                  // 81 : Comparator 1 interrupt
+    CMP2_IRQHandler,                  // 82 : Comparator 2 interrupt
+    Reserved83_IRQHandler,            // 83 : Reserved interrupt
+    Reserved84_IRQHandler,            // 84 : Reserved interrupt
+    Reserved85_IRQHandler,            // 85 : Reserved interrupt
+    Reserved86_IRQHandler,            // 86 : Reserved interrupt
+    GPIO0_IRQHandler,                 // 87 : General Purpose Input/Output interrupt 0
+    GPIO1_IRQHandler,                 // 88 : General Purpose Input/Output interrupt 1
+    GPIO2_IRQHandler,                 // 89 : General Purpose Input/Output interrupt 2
+    GPIO3_IRQHandler,                 // 90 : General Purpose Input/Output interrupt 3
+    GPIO4_IRQHandler,                 // 91 : General Purpose Input/Output interrupt 4
+    Reserved92_IRQHandler,            // 92 : Reserved interrupt
+    Reserved93_IRQHandler,            // 93 : Reserved interrupt
+    Reserved94_IRQHandler,            // 94 : Reserved interrupt
+    FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt
+    FLEXPWM1_FAULT_IRQHandler,        // 96 : FlexPWM1_fault interrupt
+    FLEXPWM1_SUBMODULE0_IRQHandler,   // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt
+    FLEXPWM1_SUBMODULE1_IRQHandler,   // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt
+    FLEXPWM1_SUBMODULE2_IRQHandler,   // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt
+    FLEXPWM1_SUBMODULE3_IRQHandler,   // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt
+    EQDC1_COMPARE_IRQHandler,         // 101: Compare
+    EQDC1_HOME_IRQHandler,            // 102: Home
+    EQDC1_WATCHDOG_IRQHandler,        // 103: Watchdog / Simultaneous A and B Change
+    EQDC1_INDEX_IRQHandler,           // 104: Index / Roll Over / Roll Under
+    Reserved105_IRQHandler,           // 105: Reserved interrupt
+    Reserved106_IRQHandler,           // 106: Reserved interrupt
+    Reserved107_IRQHandler,           // 107: Reserved interrupt
+    Reserved108_IRQHandler,           // 108: Reserved interrupt
+    Reserved109_IRQHandler,           // 109: Reserved interrupt
+    Reserved110_IRQHandler,           // 110: Reserved interrupt
+    Reserved111_IRQHandler,           // 111: Reserved interrupt
+    Reserved112_IRQHandler,           // 112: Reserved interrupt
+    Reserved113_IRQHandler,           // 113: Reserved interrupt
+    Reserved114_IRQHandler,           // 114: Reserved interrupt
+    Reserved115_IRQHandler,           // 115: Reserved interrupt
+    Reserved116_IRQHandler,           // 116: Reserved interrupt
+    Reserved117_IRQHandler,           // 117: Reserved interrupt
+    Reserved118_IRQHandler,           // 118: Reserved interrupt
+    Reserved119_IRQHandler,           // 119: Reserved interrupt
+    Reserved120_IRQHandler,           // 120: Reserved interrupt
+    Reserved121_IRQHandler,           // 121: Reserved interrupt
+    Reserved122_IRQHandler,           // 122: Reserved interrupt
+    MAU_IRQHandler,                   // 123: MAU interrupt
+    SMARTDMA_IRQHandler,              // 124: SmartDMA interrupt
+    Reserved125_IRQHandler,           // 125: Reserved interrupt
+    Reserved126_IRQHandler,           // 126: Reserved interrupt
+    Reserved127_IRQHandler,           // 127: Reserved interrupt
+    Reserved128_IRQHandler,           // 128: Reserved interrupt
+    Reserved129_IRQHandler,           // 129: Reserved interrupt
+    Reserved130_IRQHandler,           // 130: Reserved interrupt
+    Reserved131_IRQHandler,           // 131: Reserved interrupt
+    Reserved132_IRQHandler,           // 132: Reserved interrupt
+    Reserved133_IRQHandler,           // 133: Reserved interrupt
+    Reserved134_IRQHandler,           // 134: Reserved interrupt
+    RTC_IRQHandler,                   // 135: RTC alarm interrupt
+    RTC_1HZ_IRQHandler,               // 136: RTC 1Hz interrupt
+};                                     /* End of __vector_table */
+
+#if defined(__MCUXPRESSO)
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors")));
+void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128)));
+unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors);
+#endif //(ENABLE_RAM_VECTOR_TABLE)
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart,
+                                                                    unsigned int start,
+                                                                    unsigned int len)
+{
+    unsigned int *pulDest = (unsigned int *)start;
+    unsigned int *pulSrc  = (unsigned int *)romstart;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = *pulSrc++;
+}
+
+__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len)
+{
+    unsigned int *pulDest = (unsigned int *)start;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+#endif //(__MCUXPRESSO)
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+__attribute__ ((used, section("InRoot$$Sections")))
+__attribute__ ((naked))
+#elif defined(__MCUXPRESSO)
+__attribute__ ((naked, section(".after_vectors.reset")))
+#elif defined(__ICCARM__)
+__stackless
+#elif defined(__GNUC__)
+__attribute__ ((naked))
+#endif //(__CC_ARM) || (__ARMCC_VERSION)
+void Reset_Handler(void)
+{
+    // Disable interrupts
+    __asm volatile("cpsid i");
+    // Config VTOR & MSP register
+    __asm volatile(
+        "LDR R0, =0xE000ED08  \n"
+        "STR %0, [R0]         \n"
+        "LDR R1, [%0]         \n"
+        "MSR MSP, R1          \n"
+        "MSR MSPLIM, %1       \n"
+        :
+        : "r"(__vector_table), "r"(_vStackBase)
+        : "r0", "r1");
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+    __asm volatile(
+        "LDR R0, =SystemInit \n"
+        "BLX R0              \n"
+        "cpsie i             \n"
+        "LDR R0, =__main     \n"
+        "BX  R0              \n");
+#elif defined(__MCUXPRESSO)
+    SystemInit();
+
+    //
+    // Copy the data sections from flash to SRAM.
+    //
+    unsigned int LoadAddr, ExeAddr, SectionLen;
+    unsigned int *SectionTableAddr;
+
+    // Load base address of Global Section Table
+    SectionTableAddr = &__data_section_table;
+
+    // Copy the data sections from flash to SRAM.
+    while (SectionTableAddr < &__data_section_table_end)
+    {
+        LoadAddr   = *SectionTableAddr++;
+        ExeAddr    = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        data_init(LoadAddr, ExeAddr, SectionLen);
+    }
+
+    // At this point, SectionTableAddr = &__bss_section_table;
+    // Zero fill the bss segment
+    while (SectionTableAddr < &__bss_section_table_end)
+    {
+        ExeAddr    = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        bss_init(ExeAddr, SectionLen);
+    }
+
+#if defined(__cplusplus)
+    //
+    // Call C++ library initialisation
+    //
+    __libc_init_array();
+#endif //(__cplusplus)
+
+    // Reenable interrupts
+    __asm volatile("cpsie i");
+
+#if defined(__REDLIB__)
+    // Call the Redlib library, which in turn calls main()
+    __main();
+#else
+    main();
+#endif //(__REDLIB__)
+#elif defined(__ICCARM__)
+    SystemInit();
+    // Reenable interrupts
+    __asm volatile("cpsie i");
+
+    __iar_program_start();
+#elif defined(__GNUC__)
+#if !defined(__NO_SYSTEM_INIT)
+    SystemInit();
+#endif //(__NO_SYSTEM_INIT)
+    /*     Loop to copy data from read only memory to RAM. The ranges
+     *      of copy from/to are specified by following symbols evaluated in
+     *      linker script.
+     *      1. __etext/_data_start__/__data_end__
+     *      Note: All must be aligned to 4 bytes boundary.
+     */
+    uint32_t *pDataSrc, *pDataDest;
+
+    pDataSrc  = (uint32_t *)__etext;
+    pDataDest = (uint32_t *)__data_start__;
+    while (pDataDest < __data_end__)
+    {
+        *pDataDest++ = *pDataSrc++;
+    }
+#if defined(__STARTUP_CLEAR_BSS)
+    /*     This part of work usually is done in C library startup code. Otherwise,
+     *     define this macro to enable it in this startup.
+     *
+     *     Loop to zero out BSS section, which uses following symbols
+     *     in linker script:
+     *      __bss_start__: start of BSS section. Must align to 4
+     *      __bss_end__: end of BSS section. Must align to 4
+     */
+    pDataDest = (uint32_t *)__bss_start__;
+    while (pDataDest < __bss_end__)
+    {
+        *pDataDest++ = 0U;
+    }
+#endif //(__STARTUP_CLEAR_BSS)
+
+    __asm volatile("cpsie i");
+
+#if !defined(__START)
+#if defined(__REDLIB__)
+#define __START __main
+#else
+#define __START _start
+#endif //(__REDLIB__)
+#endif //(__START)
+
+    __START();
+
+#endif //(__GNUC__)
+
+    //
+    // main() shouldn't return, but if it does, we'll just enter an infinite loop
+    //
+#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM)
+    while (1)
+    {
+        ;
+    }
+#endif //!(__ARMCC_VERSION) && !(__CC_ARM)
+}
+
+//*****************************************************************************
+// Default core exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+WEAK_AV void NMI_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void HardFault_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void MemManage_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void BusFault_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void UsageFault_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void SecureFault_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void SVC_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void DebugMon_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void PendSV_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+WEAK_AV void SysTick_Handler(void)
+{
+    while (1)
+    {
+    }
+}
+
+//*****************************************************************************
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//*****************************************************************************
+WEAK_AV void DefaultISR(void)
+{
+    while (1)
+    {
+    }
+}
+
+//*****************************************************************************
+// Default application exception handlers. Override the ones here by defining
+// your own handler routines in your application code. These routines call
+// driver exception handlers or DefaultISR() if no driver exception
+// handler is included.
+//*****************************************************************************
+WEAK void Reserved16_IRQHandler(void)
+{
+    Reserved16_DriverIRQHandler();
+}
+
+WEAK void CMC_IRQHandler(void)
+{
+    CMC_DriverIRQHandler();
+}
+
+WEAK void DMA_CH0_IRQHandler(void)
+{
+    DMA_CH0_DriverIRQHandler();
+}
+
+WEAK void DMA_CH1_IRQHandler(void)
+{
+    DMA_CH1_DriverIRQHandler();
+}
+
+WEAK void DMA_CH2_IRQHandler(void)
+{
+    DMA_CH2_DriverIRQHandler();
+}
+
+WEAK void DMA_CH3_IRQHandler(void)
+{
+    DMA_CH3_DriverIRQHandler();
+}
+
+WEAK void DMA_CH4_IRQHandler(void)
+{
+    DMA_CH4_DriverIRQHandler();
+}
+
+WEAK void DMA_CH5_IRQHandler(void)
+{
+    DMA_CH5_DriverIRQHandler();
+}
+
+WEAK void DMA_CH6_IRQHandler(void)
+{
+    DMA_CH6_DriverIRQHandler();
+}
+
+WEAK void DMA_CH7_IRQHandler(void)
+{
+    DMA_CH7_DriverIRQHandler();
+}
+
+WEAK void ERM0_SINGLE_BIT_IRQHandler(void)
+{
+    ERM0_SINGLE_BIT_DriverIRQHandler();
+}
+
+WEAK void ERM0_MULTI_BIT_IRQHandler(void)
+{
+    ERM0_MULTI_BIT_DriverIRQHandler();
+}
+
+WEAK void FMU0_IRQHandler(void)
+{
+    FMU0_DriverIRQHandler();
+}
+
+WEAK void GLIKEY0_IRQHandler(void)
+{
+    GLIKEY0_DriverIRQHandler();
+}
+
+WEAK void MBC0_IRQHandler(void)
+{
+    MBC0_DriverIRQHandler();
+}
+
+WEAK void SCG0_IRQHandler(void)
+{
+    SCG0_DriverIRQHandler();
+}
+
+WEAK void SPC0_IRQHandler(void)
+{
+    SPC0_DriverIRQHandler();
+}
+
+WEAK void Reserved33_IRQHandler(void)
+{
+    Reserved33_DriverIRQHandler();
+}
+
+WEAK void WUU0_IRQHandler(void)
+{
+    WUU0_DriverIRQHandler();
+}
+
+WEAK void CAN0_IRQHandler(void)
+{
+    CAN0_DriverIRQHandler();
+}
+
+WEAK void Reserved36_IRQHandler(void)
+{
+    Reserved36_DriverIRQHandler();
+}
+
+WEAK void Reserved37_IRQHandler(void)
+{
+    Reserved37_DriverIRQHandler();
+}
+
+WEAK void Reserved38_IRQHandler(void)
+{
+    Reserved38_DriverIRQHandler();
+}
+
+WEAK void Reserved39_IRQHandler(void)
+{
+    Reserved39_DriverIRQHandler();
+}
+
+WEAK void Reserved40_IRQHandler(void)
+{
+    Reserved40_DriverIRQHandler();
+}
+
+WEAK void Reserved41_IRQHandler(void)
+{
+    Reserved41_DriverIRQHandler();
+}
+
+WEAK void LPI2C0_IRQHandler(void)
+{
+    LPI2C0_DriverIRQHandler();
+}
+
+WEAK void LPI2C1_IRQHandler(void)
+{
+    LPI2C1_DriverIRQHandler();
+}
+
+WEAK void LPSPI0_IRQHandler(void)
+{
+    LPSPI0_DriverIRQHandler();
+}
+
+WEAK void LPSPI1_IRQHandler(void)
+{
+    LPSPI1_DriverIRQHandler();
+}
+
+WEAK void Reserved46_IRQHandler(void)
+{
+    Reserved46_DriverIRQHandler();
+}
+
+WEAK void LPUART0_IRQHandler(void)
+{
+    LPUART0_DriverIRQHandler();
+}
+
+WEAK void LPUART1_IRQHandler(void)
+{
+    LPUART1_DriverIRQHandler();
+}
+
+WEAK void LPUART2_IRQHandler(void)
+{
+    LPUART2_DriverIRQHandler();
+}
+
+WEAK void LPUART3_IRQHandler(void)
+{
+    LPUART3_DriverIRQHandler();
+}
+
+WEAK void Reserved51_IRQHandler(void)
+{
+    Reserved51_DriverIRQHandler();
+}
+
+WEAK void Reserved52_IRQHandler(void)
+{
+    Reserved52_DriverIRQHandler();
+}
+
+WEAK void Reserved53_IRQHandler(void)
+{
+    Reserved53_DriverIRQHandler();
+}
+
+WEAK void CDOG0_IRQHandler(void)
+{
+    CDOG0_DriverIRQHandler();
+}
+
+WEAK void CTIMER0_IRQHandler(void)
+{
+    CTIMER0_DriverIRQHandler();
+}
+
+WEAK void CTIMER1_IRQHandler(void)
+{
+    CTIMER1_DriverIRQHandler();
+}
+
+WEAK void CTIMER2_IRQHandler(void)
+{
+    CTIMER2_DriverIRQHandler();
+}
+
+WEAK void Reserved58_IRQHandler(void)
+{
+    Reserved58_DriverIRQHandler();
+}
+
+WEAK void Reserved59_IRQHandler(void)
+{
+    Reserved59_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void)
+{
+    FLEXPWM0_RELOAD_ERROR_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_FAULT_IRQHandler(void)
+{
+    FLEXPWM0_FAULT_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void)
+{
+    FLEXPWM0_SUBMODULE0_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void)
+{
+    FLEXPWM0_SUBMODULE1_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void)
+{
+    FLEXPWM0_SUBMODULE2_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void)
+{
+    FLEXPWM0_SUBMODULE3_DriverIRQHandler();
+}
+
+WEAK void EQDC0_COMPARE_IRQHandler(void)
+{
+    EQDC0_COMPARE_DriverIRQHandler();
+}
+
+WEAK void EQDC0_HOME_IRQHandler(void)
+{
+    EQDC0_HOME_DriverIRQHandler();
+}
+
+WEAK void EQDC0_WATCHDOG_IRQHandler(void)
+{
+    EQDC0_WATCHDOG_DriverIRQHandler();
+}
+
+WEAK void EQDC0_INDEX_IRQHandler(void)
+{
+    EQDC0_INDEX_DriverIRQHandler();
+}
+
+WEAK void FREQME0_IRQHandler(void)
+{
+    FREQME0_DriverIRQHandler();
+}
+
+WEAK void LPTMR0_IRQHandler(void)
+{
+    LPTMR0_DriverIRQHandler();
+}
+
+WEAK void Reserved72_IRQHandler(void)
+{
+    Reserved72_DriverIRQHandler();
+}
+
+WEAK void OS_EVENT_IRQHandler(void)
+{
+    OS_EVENT_DriverIRQHandler();
+}
+
+WEAK void WAKETIMER0_IRQHandler(void)
+{
+    WAKETIMER0_DriverIRQHandler();
+}
+
+WEAK void UTICK0_IRQHandler(void)
+{
+    UTICK0_DriverIRQHandler();
+}
+
+WEAK void WWDT0_IRQHandler(void)
+{
+    WWDT0_DriverIRQHandler();
+}
+
+WEAK void Reserved77_IRQHandler(void)
+{
+    Reserved77_DriverIRQHandler();
+}
+
+WEAK void ADC0_IRQHandler(void)
+{
+    ADC0_DriverIRQHandler();
+}
+
+WEAK void ADC1_IRQHandler(void)
+{
+    ADC1_DriverIRQHandler();
+}
+
+WEAK void CMP0_IRQHandler(void)
+{
+    CMP0_DriverIRQHandler();
+}
+
+WEAK void CMP1_IRQHandler(void)
+{
+    CMP1_DriverIRQHandler();
+}
+
+WEAK void CMP2_IRQHandler(void)
+{
+    CMP2_DriverIRQHandler();
+}
+
+WEAK void Reserved83_IRQHandler(void)
+{
+    Reserved83_DriverIRQHandler();
+}
+
+WEAK void Reserved84_IRQHandler(void)
+{
+    Reserved84_DriverIRQHandler();
+}
+
+WEAK void Reserved85_IRQHandler(void)
+{
+    Reserved85_DriverIRQHandler();
+}
+
+WEAK void Reserved86_IRQHandler(void)
+{
+    Reserved86_DriverIRQHandler();
+}
+
+WEAK void GPIO0_IRQHandler(void)
+{
+    GPIO0_DriverIRQHandler();
+}
+
+WEAK void GPIO1_IRQHandler(void)
+{
+    GPIO1_DriverIRQHandler();
+}
+
+WEAK void GPIO2_IRQHandler(void)
+{
+    GPIO2_DriverIRQHandler();
+}
+
+WEAK void GPIO3_IRQHandler(void)
+{
+    GPIO3_DriverIRQHandler();
+}
+
+WEAK void GPIO4_IRQHandler(void)
+{
+    GPIO4_DriverIRQHandler();
+}
+
+WEAK void Reserved92_IRQHandler(void)
+{
+    Reserved92_DriverIRQHandler();
+}
+
+WEAK void Reserved93_IRQHandler(void)
+{
+    Reserved93_DriverIRQHandler();
+}
+
+WEAK void Reserved94_IRQHandler(void)
+{
+    Reserved94_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void)
+{
+    FLEXPWM1_RELOAD_ERROR_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_FAULT_IRQHandler(void)
+{
+    FLEXPWM1_FAULT_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void)
+{
+    FLEXPWM1_SUBMODULE0_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void)
+{
+    FLEXPWM1_SUBMODULE1_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void)
+{
+    FLEXPWM1_SUBMODULE2_DriverIRQHandler();
+}
+
+WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void)
+{
+    FLEXPWM1_SUBMODULE3_DriverIRQHandler();
+}
+
+WEAK void EQDC1_COMPARE_IRQHandler(void)
+{
+    EQDC1_COMPARE_DriverIRQHandler();
+}
+
+WEAK void EQDC1_HOME_IRQHandler(void)
+{
+    EQDC1_HOME_DriverIRQHandler();
+}
+
+WEAK void EQDC1_WATCHDOG_IRQHandler(void)
+{
+    EQDC1_WATCHDOG_DriverIRQHandler();
+}
+
+WEAK void EQDC1_INDEX_IRQHandler(void)
+{
+    EQDC1_INDEX_DriverIRQHandler();
+}
+
+WEAK void Reserved105_IRQHandler(void)
+{
+    Reserved105_DriverIRQHandler();
+}
+
+WEAK void Reserved106_IRQHandler(void)
+{
+    Reserved106_DriverIRQHandler();
+}
+
+WEAK void Reserved107_IRQHandler(void)
+{
+    Reserved107_DriverIRQHandler();
+}
+
+WEAK void Reserved108_IRQHandler(void)
+{
+    Reserved108_DriverIRQHandler();
+}
+
+WEAK void Reserved109_IRQHandler(void)
+{
+    Reserved109_DriverIRQHandler();
+}
+
+WEAK void Reserved110_IRQHandler(void)
+{
+    Reserved110_DriverIRQHandler();
+}
+
+WEAK void Reserved111_IRQHandler(void)
+{
+    Reserved111_DriverIRQHandler();
+}
+
+WEAK void Reserved112_IRQHandler(void)
+{
+    Reserved112_DriverIRQHandler();
+}
+
+WEAK void Reserved113_IRQHandler(void)
+{
+    Reserved113_DriverIRQHandler();
+}
+
+WEAK void Reserved114_IRQHandler(void)
+{
+    Reserved114_DriverIRQHandler();
+}
+
+WEAK void Reserved115_IRQHandler(void)
+{
+    Reserved115_DriverIRQHandler();
+}
+
+WEAK void Reserved116_IRQHandler(void)
+{
+    Reserved116_DriverIRQHandler();
+}
+
+WEAK void Reserved117_IRQHandler(void)
+{
+    Reserved117_DriverIRQHandler();
+}
+
+WEAK void Reserved118_IRQHandler(void)
+{
+    Reserved118_DriverIRQHandler();
+}
+
+WEAK void Reserved119_IRQHandler(void)
+{
+    Reserved119_DriverIRQHandler();
+}
+
+WEAK void Reserved120_IRQHandler(void)
+{
+    Reserved120_DriverIRQHandler();
+}
+
+WEAK void Reserved121_IRQHandler(void)
+{
+    Reserved121_DriverIRQHandler();
+}
+
+WEAK void Reserved122_IRQHandler(void)
+{
+    Reserved122_DriverIRQHandler();
+}
+
+WEAK void MAU_IRQHandler(void)
+{
+    MAU_DriverIRQHandler();
+}
+
+WEAK void SMARTDMA_IRQHandler(void)
+{
+    SMARTDMA_DriverIRQHandler();
+}
+
+WEAK void Reserved125_IRQHandler(void)
+{
+    Reserved125_DriverIRQHandler();
+}
+
+WEAK void Reserved126_IRQHandler(void)
+{
+    Reserved126_DriverIRQHandler();
+}
+
+WEAK void Reserved127_IRQHandler(void)
+{
+    Reserved127_DriverIRQHandler();
+}
+
+WEAK void Reserved128_IRQHandler(void)
+{
+    Reserved128_DriverIRQHandler();
+}
+
+WEAK void Reserved129_IRQHandler(void)
+{
+    Reserved129_DriverIRQHandler();
+}
+
+WEAK void Reserved130_IRQHandler(void)
+{
+    Reserved130_DriverIRQHandler();
+}
+
+WEAK void Reserved131_IRQHandler(void)
+{
+    Reserved131_DriverIRQHandler();
+}
+
+WEAK void Reserved132_IRQHandler(void)
+{
+    Reserved132_DriverIRQHandler();
+}
+
+WEAK void Reserved133_IRQHandler(void)
+{
+    Reserved133_DriverIRQHandler();
+}
+
+WEAK void Reserved134_IRQHandler(void)
+{
+    Reserved134_DriverIRQHandler();
+}
+
+WEAK void RTC_IRQHandler(void)
+{
+    RTC_DriverIRQHandler();
+}
+
+WEAK void RTC_1HZ_IRQHandler(void)
+{
+    RTC_1HZ_DriverIRQHandler();
+}
+
+//*****************************************************************************
+
+#if defined(DEBUG)
+#if defined(__GNUC__)
+#pragma GCC pop_options
+#endif //(__GNUC__)
+#endif //(DEBUG)
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/system_MCXA344.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/system_MCXA344.c
new file mode 100644
index 0000000000..1564064ca6
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/system_MCXA344.c
@@ -0,0 +1,115 @@
+/*
+** ###################################################################
+**     Processors:          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Compilers:
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    MCXAP144M180FS6_RM_Rev.1_DraftC
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MCXA344
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief Device specific configuration file for MCXA344 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+#if __has_include("fsl_clock.h")
+#include "fsl_clock.h"
+#endif
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Secure mode */
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Non-secure mode */
+  #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+    SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2));    /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2));    /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */
+#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+    SCB->NSACR |= ((3UL << 0) | (3UL << 10));   /* enable CP0, CP1, CP10, CP11 Non-secure Access */
+
+    /* Enable the LPCAC */
+    SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK;
+    SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK;
+
+    /* Route the PMC bandgap buffer signal to the ADC */
+    SPC0->CORELDO_CFG |= (1U << 24U);
+
+    /* Enables flash speculation */
+    SYSCON->NVM_CTRL &= ~(SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK | SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK);
+    SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK;
+
+  SystemInitHook();
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+#if __has_include("fsl_clock.h")
+    /* Get frequency of Core System */
+    SystemCoreClock = CLOCK_GetCoreSysClkFreq();
+#endif
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInitHook()
+   ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInitHook (void) {
+  /* Void implementation of the weak function. */
+}
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/system_MCXA344.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/system_MCXA344.h
new file mode 100644
index 0000000000..efb3dd9d9d
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/system_MCXA344.h
@@ -0,0 +1,116 @@
+/*
+** ###################################################################
+**     Processors:          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Compilers:
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    MCXAP144M180FS6_RM_Rev.1_DraftC
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MCXA344
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief Device specific configuration file for MCXA344 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_MCXA344_H_
+#define _SYSTEM_MCXA344_H_                       /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define DEFAULT_SYSTEM_CLOCK           12000000u           /* Default System clock value */
+#define CLK_RTC_32K_CLK                   32768u           /* RTC oscillator 32 kHz output (32k_clk */
+#define CLK_FRO_12MHZ                  12000000u           /* FRO 12 MHz (fro_12m) */
+#define CLK_FRO_32MHZ                  32000000u           /* FRO 32 MHz (fro_32m) */
+#define CLK_FRO_48MHZ                  48000000u           /* FRO 48 MHz (fro_48m) */
+
+#ifndef CLK_CLK_IN
+#define CLK_CLK_IN                     16000000u           /* Default CLK_IN pin clock */
+#endif /* CLK_CLK_IN */
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SYSTEM_MCXA344_H_ */
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/variable.cmake
new file mode 100644
index 0000000000..b5f6656d04
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/variable.cmake
@@ -0,0 +1,14 @@
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+#### chip related
+include(${SdkRootDirPath}/devices/MCX/variable.cmake)
+mcux_set_variable(device MCXA344)
+mcux_set_variable(device_root devices)
+mcux_set_variable(soc_series MCXA)
+mcux_set_variable(soc_periph periph3)
+mcux_set_variable(core_id_suffix_name "")
+mcux_set_variable(multicore_foldername .)
+
+#### Source record
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_ADC.h
new file mode 100644
index 0000000000..371328eb91
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_ADC.h
@@ -0,0 +1,1018 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for ADC
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_ADC.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for ADC
+ *
+ * CMSIS Peripheral Access Layer for ADC
+ */
+
+#if !defined(PERI_ADC_H_)
+#define PERI_ADC_H_                              /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Size of Registers Arrays */
+#define ADC_TCTRL_COUNT                           4u
+#define ADC_GCC_COUNT                             1u
+#define ADC_GCR_COUNT                             1u
+#define ADC_CMD_COUNT                             7u
+#define ADC_CV_COUNT                              7u
+#define ADC_CAL_GAR_COUNT                         34u
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t CTRL;                              /**< Control Register, offset: 0x10 */
+  __IO uint32_t STAT;                              /**< Status Register, offset: 0x14 */
+  __IO uint32_t IE;                                /**< Interrupt Enable Register, offset: 0x18 */
+  __IO uint32_t DE;                                /**< DMA Enable Register, offset: 0x1C */
+  __IO uint32_t CFG;                               /**< Configuration Register, offset: 0x20 */
+  __IO uint32_t PAUSE;                             /**< Pause Register, offset: 0x24 */
+       uint8_t RESERVED_1[12];
+  __IO uint32_t SWTRIG;                            /**< Software Trigger Register, offset: 0x34 */
+  __IO uint32_t TSTAT;                             /**< Trigger Status Register, offset: 0x38 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t OFSTRIM;                           /**< Offset Trim Register, offset: 0x40 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t HSTRIM;                            /**< High Speed Trim Register, offset: 0x48 */
+       uint8_t RESERVED_4[84];
+  __IO uint32_t TCTRL[ADC_TCTRL_COUNT];            /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_5[48];
+  __IO uint32_t FCTRL;                             /**< FIFO Control Register, offset: 0xE0 */
+       uint8_t RESERVED_6[12];
+  __I  uint32_t GCC[ADC_GCC_COUNT];                /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */
+       uint8_t RESERVED_7[4];
+  __IO uint32_t GCR[ADC_GCR_COUNT];                /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */
+       uint8_t RESERVED_8[4];
+  struct {                                         /* offset: 0x100, array step: 0x8 */
+    __IO uint32_t CMDL;                              /**< Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
+    __IO uint32_t CMDH;                              /**< Command High Buffer Register, array offset: 0x104, array step: 0x8 */
+  } CMD[ADC_CMD_COUNT];
+       uint8_t RESERVED_9[200];
+  __IO uint32_t CV[ADC_CV_COUNT];                  /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_10[228];
+  __I  uint32_t RESFIFO;                           /**< Data Result FIFO Register, offset: 0x300 */
+       uint8_t RESERVED_11[252];
+  __IO uint32_t CAL_GAR[ADC_CAL_GAR_COUNT];        /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */
+       uint8_t RESERVED_12[2928];
+  __IO uint32_t CFG2;                              /**< Configuration 2 Register, offset: 0xFF8 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+
+#define ADC_VERID_RES_MASK                       (0x1U)
+#define ADC_VERID_RES_SHIFT                      (0U)
+/*! RES - Resolution
+ *  0b0..Up to 12-bit single ended resolution supported (and 13-bit differential resolution if VERID[DIFFEN] = 1b).
+ *  0b1..Up to 16-bit single ended resolution supported (and 16-bit differential resolution if VERID[DIFFEN] = 1b).
+ */
+#define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
+
+#define ADC_VERID_DIFFEN_MASK                    (0x2U)
+#define ADC_VERID_DIFFEN_SHIFT                   (1U)
+/*! DIFFEN - Differential Supported
+ *  0b0..Differential operation not supported.
+ *  0b1..Differential operation supported.
+ */
+#define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
+
+#define ADC_VERID_MVI_MASK                       (0x8U)
+#define ADC_VERID_MVI_SHIFT                      (3U)
+/*! MVI - Multi Vref Implemented
+ *  0b0..Single voltage reference high (VREFH) input supported.
+ *  0b1..Multiple voltage reference high (VREFH) inputs supported.
+ */
+#define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
+
+#define ADC_VERID_CSW_MASK                       (0x70U)
+#define ADC_VERID_CSW_SHIFT                      (4U)
+/*! CSW - Channel Scale Width
+ *  0b000..Channel scaling not supported.
+ *  0b001..Channel scaling supported. 1-bit CSCALE control field.
+ *  0b110..Channel scaling supported. 6-bit CSCALE control field.
+ */
+#define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
+
+#define ADC_VERID_VR1RNGI_MASK                   (0x100U)
+#define ADC_VERID_VR1RNGI_SHIFT                  (8U)
+/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
+ *  0b0..Range control not required. CFG[VREF1RNG] is not implemented.
+ *  0b1..Range control required. CFG[VREF1RNG] is implemented.
+ */
+#define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
+
+#define ADC_VERID_IADCKI_MASK                    (0x200U)
+#define ADC_VERID_IADCKI_SHIFT                   (9U)
+/*! IADCKI - Internal ADC Clock Implemented
+ *  0b0..Internal clock source not implemented.
+ *  0b1..Internal clock source (and CFG[ADCKEN]) implemented.
+ */
+#define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
+
+#define ADC_VERID_CALOFSI_MASK                   (0x400U)
+#define ADC_VERID_CALOFSI_SHIFT                  (10U)
+/*! CALOFSI - Calibration Function Implemented
+ *  0b0..Calibration Not Implemented.
+ *  0b1..Calibration Implemented.
+ */
+#define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
+
+#define ADC_VERID_NUM_SEC_MASK                   (0x800U)
+#define ADC_VERID_NUM_SEC_SHIFT                  (11U)
+/*! NUM_SEC - Number of Single Ended Outputs Supported
+ *  0b0..This design supports one single ended conversion at a time.
+ *  0b1..This design supports two simultaneous single ended conversions.
+ */
+#define ADC_VERID_NUM_SEC(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)
+
+#define ADC_VERID_NUM_FIFO_MASK                  (0x7000U)
+#define ADC_VERID_NUM_FIFO_SHIFT                 (12U)
+/*! NUM_FIFO - Number of FIFOs
+ *  0b000..N/A
+ *  0b001..This design supports one result FIFO.
+ *  0b010..This design supports two result FIFOs.
+ *  0b011..This design supports three result FIFOs.
+ *  0b100..This design supports four result FIFOs.
+ */
+#define ADC_VERID_NUM_FIFO(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)
+
+#define ADC_VERID_MINOR_MASK                     (0xFF0000U)
+#define ADC_VERID_MINOR_SHIFT                    (16U)
+/*! MINOR - Minor Version Number */
+#define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
+
+#define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
+#define ADC_VERID_MAJOR_SHIFT                    (24U)
+/*! MAJOR - Major Version Number */
+#define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+
+#define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
+#define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
+/*! TRIG_NUM - Trigger Number */
+#define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
+
+#define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
+#define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
+/*! FIFOSIZE - Result FIFO Depth
+ *  0b00000001..Result FIFO depth = 2 dataword.
+ *  0b00000100..Result FIFO depth = 4 datawords.
+ *  0b00001000..Result FIFO depth = 8 datawords.
+ *  0b00010000..Result FIFO depth = 16 datawords.
+ *  0b00100000..Result FIFO depth = 32 datawords.
+ *  0b01000000..Result FIFO depth = 64 datawords.
+ */
+#define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
+
+#define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
+#define ADC_PARAM_CV_NUM_SHIFT                   (16U)
+/*! CV_NUM - Compare Value Number */
+#define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
+
+#define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
+#define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
+/*! CMD_NUM - Command Buffer Number */
+#define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
+/*! @} */
+
+/*! @name CTRL - Control Register */
+/*! @{ */
+
+#define ADC_CTRL_ADCEN_MASK                      (0x1U)
+#define ADC_CTRL_ADCEN_SHIFT                     (0U)
+/*! ADCEN - ADC Enable
+ *  0b0..ADC is disabled.
+ *  0b1..ADC is enabled.
+ */
+#define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
+
+#define ADC_CTRL_RST_MASK                        (0x2U)
+#define ADC_CTRL_RST_SHIFT                       (1U)
+/*! RST - Software Reset
+ *  0b0..ADC logic is not reset.
+ *  0b1..ADC logic is reset.
+ */
+#define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
+
+#define ADC_CTRL_DOZEN_MASK                      (0x4U)
+#define ADC_CTRL_DOZEN_SHIFT                     (2U)
+/*! DOZEN - Doze Enable
+ *  0b0..ADC is enabled in low power mode.
+ *  0b1..ADC is disabled in low power mode.
+ */
+#define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
+
+#define ADC_CTRL_CAL_REQ_MASK                    (0x8U)
+#define ADC_CTRL_CAL_REQ_SHIFT                   (3U)
+/*! CAL_REQ - Auto-Calibration Request
+ *  0b0..No request for hardware calibration has been made
+ *  0b1..A request for hardware calibration has been made
+ */
+#define ADC_CTRL_CAL_REQ(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK)
+
+#define ADC_CTRL_CALOFS_MASK                     (0x10U)
+#define ADC_CTRL_CALOFS_SHIFT                    (4U)
+/*! CALOFS - Offset Calibration Request
+ *  0b0..No request for offset calibration has been made
+ *  0b1..Request for offset calibration function
+ */
+#define ADC_CTRL_CALOFS(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK)
+
+#define ADC_CTRL_CALHS_MASK                      (0x40U)
+#define ADC_CTRL_CALHS_SHIFT                     (6U)
+/*! CALHS - High Speed Mode Trim Request
+ *  0b0..No request for high speed mode trim has been made
+ *  0b1..Request for high speed mode trim has been made
+ */
+#define ADC_CTRL_CALHS(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALHS_SHIFT)) & ADC_CTRL_CALHS_MASK)
+
+#define ADC_CTRL_RSTFIFO0_MASK                   (0x100U)
+#define ADC_CTRL_RSTFIFO0_SHIFT                  (8U)
+/*! RSTFIFO0 - Reset FIFO 0
+ *  0b0..No effect.
+ *  0b1..FIFO 0 is reset.
+ */
+#define ADC_CTRL_RSTFIFO0(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)
+
+#define ADC_CTRL_CAL_AVGS_MASK                   (0xF0000U)
+#define ADC_CTRL_CAL_AVGS_SHIFT                  (16U)
+/*! CAL_AVGS - Auto-Calibration Averages
+ *  0b0000..Single conversion.
+ *  0b0001..2 conversions averaged.
+ *  0b0010..4 conversions averaged.
+ *  0b0011..8 conversions averaged.
+ *  0b0100..16 conversions averaged.
+ *  0b0101..32 conversions averaged.
+ *  0b0110..64 conversions averaged.
+ *  0b0111..128 conversions averaged.
+ *  0b1000..256 conversions averaged.
+ *  0b1001..512 conversions averaged.
+ *  0b1010..1024 conversions averaged.
+ */
+#define ADC_CTRL_CAL_AVGS(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK)
+/*! @} */
+
+/*! @name STAT - Status Register */
+/*! @{ */
+
+#define ADC_STAT_RDY0_MASK                       (0x1U)
+#define ADC_STAT_RDY0_SHIFT                      (0U)
+/*! RDY0 - Result FIFO 0 Ready Flag
+ *  0b0..Result FIFO 0 data level not above watermark level.
+ *  0b1..Result FIFO 0 holding data above watermark level.
+ */
+#define ADC_STAT_RDY0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)
+
+#define ADC_STAT_FOF0_MASK                       (0x2U)
+#define ADC_STAT_FOF0_SHIFT                      (1U)
+/*! FOF0 - Result FIFO 0 Overflow Flag
+ *  0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared.
+ *  0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
+ */
+#define ADC_STAT_FOF0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)
+
+#define ADC_STAT_TEXC_INT_MASK                   (0x100U)
+#define ADC_STAT_TEXC_INT_SHIFT                  (8U)
+/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception
+ *  0b0..No trigger exceptions have occurred.
+ *  0b1..A trigger exception has occurred and is pending acknowledgement.
+ */
+#define ADC_STAT_TEXC_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)
+
+#define ADC_STAT_TCOMP_INT_MASK                  (0x200U)
+#define ADC_STAT_TCOMP_INT_SHIFT                 (9U)
+/*! TCOMP_INT - Interrupt Flag For Trigger Completion
+ *  0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.
+ *  0b1..Trigger sequence has been completed and all data is stored in the associated FIFO.
+ */
+#define ADC_STAT_TCOMP_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)
+
+#define ADC_STAT_CAL_RDY_MASK                    (0x400U)
+#define ADC_STAT_CAL_RDY_SHIFT                   (10U)
+/*! CAL_RDY - Calibration Ready
+ *  0b0..Calibration is incomplete or hasn't been ran.
+ *  0b1..The ADC is calibrated.
+ */
+#define ADC_STAT_CAL_RDY(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK)
+
+#define ADC_STAT_ADC_ACTIVE_MASK                 (0x800U)
+#define ADC_STAT_ADC_ACTIVE_SHIFT                (11U)
+/*! ADC_ACTIVE - ADC Active
+ *  0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
+ *  0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
+ */
+#define ADC_STAT_ADC_ACTIVE(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
+
+#define ADC_STAT_TRGACT_MASK                     (0x30000U)
+#define ADC_STAT_TRGACT_SHIFT                    (16U)
+/*! TRGACT - Trigger Active
+ *  0b00..Command (sequence) associated with Trigger 0 currently being executed.
+ *  0b01..Command (sequence) associated with Trigger 1 currently being executed.
+ *  0b10..Command (sequence) associated with Trigger 2 currently being executed.
+ *  0b11..Command (sequence) associated with Trigger 3 currently being executed.
+ */
+#define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
+
+#define ADC_STAT_CMDACT_MASK                     (0x7000000U)
+#define ADC_STAT_CMDACT_SHIFT                    (24U)
+/*! CMDACT - Command Active
+ *  0b000..No command is currently in progress.
+ *  0b001..Command 1 currently being executed.
+ *  0b010..Command 2 currently being executed.
+ *  0b011-0b111..Associated command number is currently being executed.
+ */
+#define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
+/*! @} */
+
+/*! @name IE - Interrupt Enable Register */
+/*! @{ */
+
+#define ADC_IE_FWMIE0_MASK                       (0x1U)
+#define ADC_IE_FWMIE0_SHIFT                      (0U)
+/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
+ *  0b0..FIFO 0 watermark interrupts are not enabled.
+ *  0b1..FIFO 0 watermark interrupts are enabled.
+ */
+#define ADC_IE_FWMIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)
+
+#define ADC_IE_FOFIE0_MASK                       (0x2U)
+#define ADC_IE_FOFIE0_SHIFT                      (1U)
+/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
+ *  0b0..FIFO 0 overflow interrupts are not enabled.
+ *  0b1..FIFO 0 overflow interrupts are enabled.
+ */
+#define ADC_IE_FOFIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)
+
+#define ADC_IE_TEXC_IE_MASK                      (0x100U)
+#define ADC_IE_TEXC_IE_SHIFT                     (8U)
+/*! TEXC_IE - Trigger Exception Interrupt Enable
+ *  0b0..Trigger exception interrupts are disabled.
+ *  0b1..Trigger exception interrupts are enabled.
+ */
+#define ADC_IE_TEXC_IE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)
+
+#define ADC_IE_TCOMP_IE_MASK                     (0xF0000U)
+#define ADC_IE_TCOMP_IE_SHIFT                    (16U)
+/*! TCOMP_IE - Trigger Completion Interrupt Enable
+ *  0b0000..Trigger completion interrupts are disabled.
+ *  0b0001..Trigger completion interrupts are enabled for trigger source 0 only.
+ *  0b0010..Trigger completion interrupts are enabled for trigger source 1 only.
+ *  0b0011-0b1110..Associated trigger completion interrupts are enabled.
+ *  0b1111..Trigger completion interrupts are enabled for every trigger source.
+ */
+#define ADC_IE_TCOMP_IE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
+/*! @} */
+
+/*! @name DE - DMA Enable Register */
+/*! @{ */
+
+#define ADC_DE_FWMDE0_MASK                       (0x1U)
+#define ADC_DE_FWMDE0_SHIFT                      (0U)
+/*! FWMDE0 - FIFO 0 Watermark DMA Enable
+ *  0b0..DMA request disabled.
+ *  0b1..DMA request enabled.
+ */
+#define ADC_DE_FWMDE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)
+/*! @} */
+
+/*! @name CFG - Configuration Register */
+/*! @{ */
+
+#define ADC_CFG_TPRICTRL_MASK                    (0x3U)
+#define ADC_CFG_TPRICTRL_SHIFT                   (0U)
+/*! TPRICTRL - ADC Trigger Priority Control
+ *  0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted
+ *        and the new command specified by the trigger is started.
+ *  0b01..If a higher priority trigger is received during command processing, the current command is stopped after
+ *        completing the current conversion. If averaging is enabled, the averaging loop will be completed.
+ *        However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced.
+ *  0b10..If a higher priority trigger is received during command processing, the current command will be
+ *        completed (averaging, looping, compare) before servicing the higher priority trigger.
+ *  0b11..
+ */
+#define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
+
+#define ADC_CFG_PWRSEL_MASK                      (0x20U)
+#define ADC_CFG_PWRSEL_SHIFT                     (5U)
+/*! PWRSEL - Power Configuration Select
+ *  0b0..Low power
+ *  0b1..High power
+ */
+#define ADC_CFG_PWRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
+
+#define ADC_CFG_REFSEL_MASK                      (0xC0U)
+#define ADC_CFG_REFSEL_SHIFT                     (6U)
+/*! REFSEL - Voltage Reference Selection
+ *  0b00..(Default) Option 1 setting.
+ *  0b01..Option 2 setting.
+ *  0b10..Option 3 setting.
+ *  0b11..Reserved
+ */
+#define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
+
+#define ADC_CFG_TRES_MASK                        (0x100U)
+#define ADC_CFG_TRES_SHIFT                       (8U)
+/*! TRES - Trigger Resume Enable
+ *  0b0..Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted.
+ *  0b1..Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted.
+ */
+#define ADC_CFG_TRES(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)
+
+#define ADC_CFG_TCMDRES_MASK                     (0x200U)
+#define ADC_CFG_TCMDRES_SHIFT                    (9U)
+/*! TCMDRES - Trigger Command Resume
+ *  0b0..Trigger sequences interrupted by a high priority trigger exception is automatically restarted.
+ *  0b1..Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception.
+ */
+#define ADC_CFG_TCMDRES(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)
+
+#define ADC_CFG_HPT_EXDI_MASK                    (0x400U)
+#define ADC_CFG_HPT_EXDI_SHIFT                   (10U)
+/*! HPT_EXDI - High Priority Trigger Exception Disable
+ *  0b0..High priority trigger exceptions are enabled.
+ *  0b1..High priority trigger exceptions are disabled.
+ */
+#define ADC_CFG_HPT_EXDI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)
+
+#define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
+#define ADC_CFG_PUDLY_SHIFT                      (16U)
+/*! PUDLY - Power Up Delay */
+#define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
+
+#define ADC_CFG_PWREN_MASK                       (0x10000000U)
+#define ADC_CFG_PWREN_SHIFT                      (28U)
+/*! PWREN - ADC Analog Pre-Enable
+ *  0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
+ *  0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
+ *       of higher DC current consumption). Note that a single power up delay (CFG[PUDLY]) is executed immediately
+ *       once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has
+ *       passed. After this initial delay expires the analog remains pre-enabled and no additional delays are
+ *       executed.
+ */
+#define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
+/*! @} */
+
+/*! @name PAUSE - Pause Register */
+/*! @{ */
+
+#define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
+#define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
+/*! PAUSEDLY - Pause Delay */
+#define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
+
+#define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
+#define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
+/*! PAUSEEN - PAUSE Option Enable
+ *  0b0..Pause operation disabled
+ *  0b1..Pause operation enabled
+ */
+#define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
+/*! @} */
+
+/*! @name SWTRIG - Software Trigger Register */
+/*! @{ */
+
+#define ADC_SWTRIG_SWT0_MASK                     (0x1U)
+#define ADC_SWTRIG_SWT0_SHIFT                    (0U)
+/*! SWT0 - Software Trigger 0 Event
+ *  0b0..No trigger 0 event generated.
+ *  0b1..Trigger 0 event generated.
+ */
+#define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
+
+#define ADC_SWTRIG_SWT1_MASK                     (0x2U)
+#define ADC_SWTRIG_SWT1_SHIFT                    (1U)
+/*! SWT1 - Software Trigger 1 Event
+ *  0b0..No trigger 1 event generated.
+ *  0b1..Trigger 1 event generated.
+ */
+#define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
+
+#define ADC_SWTRIG_SWT2_MASK                     (0x4U)
+#define ADC_SWTRIG_SWT2_SHIFT                    (2U)
+/*! SWT2 - Software Trigger 2 Event
+ *  0b0..No trigger 2 event generated.
+ *  0b1..Trigger 2 event generated.
+ */
+#define ADC_SWTRIG_SWT2(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
+
+#define ADC_SWTRIG_SWT3_MASK                     (0x8U)
+#define ADC_SWTRIG_SWT3_SHIFT                    (3U)
+/*! SWT3 - Software Trigger 3 Event
+ *  0b0..No trigger 3 event generated.
+ *  0b1..Trigger 3 event generated.
+ */
+#define ADC_SWTRIG_SWT3(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
+/*! @} */
+
+/*! @name TSTAT - Trigger Status Register */
+/*! @{ */
+
+#define ADC_TSTAT_TEXC_NUM_MASK                  (0xFU)
+#define ADC_TSTAT_TEXC_NUM_SHIFT                 (0U)
+/*! TEXC_NUM - Trigger Exception Number
+ *  0b0000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.
+ *  0b0001..Trigger 0 has been interrupted by a high priority exception.
+ *  0b0010..Trigger 1 has been interrupted by a high priority exception.
+ *  0b0011-0b1110..Associated trigger sequence has interrupted by a high priority exception.
+ *  0b1111..Every trigger sequence has been interrupted by a high priority exception.
+ */
+#define ADC_TSTAT_TEXC_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)
+
+#define ADC_TSTAT_TCOMP_FLAG_MASK                (0xF0000U)
+#define ADC_TSTAT_TCOMP_FLAG_SHIFT               (16U)
+/*! TCOMP_FLAG - Trigger Completion Flag
+ *  0b0000..No triggers have been completed. Trigger completion interrupts are disabled.
+ *  0b0001..Trigger 0 has been completed and trigger 0 has enabled completion interrupts.
+ *  0b0010..Trigger 1 has been completed and trigger 1 has enabled completion interrupts.
+ *  0b0011-0b1110..Associated trigger sequence has completed and has enabled completion interrupts.
+ *  0b1111..Every trigger sequence has been completed and every trigger has enabled completion interrupts.
+ */
+#define ADC_TSTAT_TCOMP_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
+/*! @} */
+
+/*! @name OFSTRIM - Offset Trim Register */
+/*! @{ */
+
+#define ADC_OFSTRIM_OFSTRIM_MASK                 (0x3FFU)
+#define ADC_OFSTRIM_OFSTRIM_SHIFT                (0U)
+/*! OFSTRIM - Trim for Offset */
+#define ADC_OFSTRIM_OFSTRIM(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_SHIFT)) & ADC_OFSTRIM_OFSTRIM_MASK)
+/*! @} */
+
+/*! @name HSTRIM - High Speed Trim Register */
+/*! @{ */
+
+#define ADC_HSTRIM_HSTRIM_MASK                   (0x1FU)
+#define ADC_HSTRIM_HSTRIM_SHIFT                  (0U)
+/*! HSTRIM - Trim for High Speed Conversions */
+#define ADC_HSTRIM_HSTRIM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_HSTRIM_HSTRIM_SHIFT)) & ADC_HSTRIM_HSTRIM_MASK)
+/*! @} */
+
+/*! @name TCTRL - Trigger Control Register */
+/*! @{ */
+
+#define ADC_TCTRL_HTEN_MASK                      (0x1U)
+#define ADC_TCTRL_HTEN_SHIFT                     (0U)
+/*! HTEN - Trigger Enable
+ *  0b0..Hardware trigger source disabled
+ *  0b1..Hardware trigger source enabled
+ */
+#define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
+
+#define ADC_TCTRL_TPRI_MASK                      (0x300U)
+#define ADC_TCTRL_TPRI_SHIFT                     (8U)
+/*! TPRI - Trigger Priority Setting
+ *  0b00..Set to highest priority, Level 1
+ *  0b01-0b10..Set to corresponding priority level
+ *  0b11..Set to lowest priority, Level 4
+ */
+#define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
+
+#define ADC_TCTRL_RSYNC_MASK                     (0x8000U)
+#define ADC_TCTRL_RSYNC_SHIFT                    (15U)
+/*! RSYNC - Trigger Resync */
+#define ADC_TCTRL_RSYNC(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)
+
+#define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
+#define ADC_TCTRL_TDLY_SHIFT                     (16U)
+/*! TDLY - Trigger Delay Select */
+#define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
+
+#define ADC_TCTRL_TSYNC_MASK                     (0x800000U)
+#define ADC_TCTRL_TSYNC_SHIFT                    (23U)
+/*! TSYNC - Trigger Synchronous Select */
+#define ADC_TCTRL_TSYNC(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TSYNC_SHIFT)) & ADC_TCTRL_TSYNC_MASK)
+
+#define ADC_TCTRL_TCMD_MASK                      (0x7000000U)
+#define ADC_TCTRL_TCMD_SHIFT                     (24U)
+/*! TCMD - Trigger Command Select
+ *  0b000..Not a valid selection from the command buffer. Trigger event is ignored.
+ *  0b001..CMD1 is executed
+ *  0b010-0b110..Corresponding CMD is executed
+ *  0b111..CMD7 is executed
+ */
+#define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
+/*! @} */
+
+/*! @name FCTRL - FIFO Control Register */
+/*! @{ */
+
+#define ADC_FCTRL_FCOUNT_MASK                    (0xFU)
+#define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
+/*! FCOUNT - Result FIFO Counter */
+#define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
+
+#define ADC_FCTRL_FWMARK_MASK                    (0x70000U)
+#define ADC_FCTRL_FWMARK_SHIFT                   (16U)
+/*! FWMARK - Watermark Level Selection */
+#define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
+/*! @} */
+
+/*! @name GCC - Gain Calibration Control */
+/*! @{ */
+
+#define ADC_GCC_GAIN_CAL_MASK                    (0xFFFFU)
+#define ADC_GCC_GAIN_CAL_SHIFT                   (0U)
+/*! GAIN_CAL - Gain Calibration Value */
+#define ADC_GCC_GAIN_CAL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK)
+
+#define ADC_GCC_RDY_MASK                         (0x1000000U)
+#define ADC_GCC_RDY_SHIFT                        (24U)
+/*! RDY - Gain Calibration Value Valid
+ *  0b0..The GAIN_CAL value is invalid. Run the hardware calibration routine for this value to be set.
+ *  0b1..The GAIN_CAL value is valid. GAIN_CAL should be used by software to derive GCRa[GCALR].
+ */
+#define ADC_GCC_RDY(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK)
+/*! @} */
+
+/*! @name GCR - Gain Calculation Result */
+/*! @{ */
+
+#define ADC_GCR_GCALR_MASK                       (0x1FFFFU)
+#define ADC_GCR_GCALR_SHIFT                      (0U)
+/*! GCALR - Gain Calculation Result */
+#define ADC_GCR_GCALR(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK)
+
+#define ADC_GCR_RDY_MASK                         (0x1000000U)
+#define ADC_GCR_RDY_SHIFT                        (24U)
+/*! RDY - Gain Calculation Ready
+ *  0b0..The GCALR value is invalid.
+ *  0b1..The GCALR value is valid.
+ */
+#define ADC_GCR_RDY(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK)
+/*! @} */
+
+/*! @name CMDL - Command Low Buffer Register */
+/*! @{ */
+
+#define ADC_CMDL_ADCH_MASK                       (0x1FU)
+#define ADC_CMDL_ADCH_SHIFT                      (0U)
+/*! ADCH - Input Channel Select
+ *  0b00000..Select CH0A.
+ *  0b00001..Select CH1A.
+ *  0b00010..Select CH2A.
+ *  0b00011..Select CH3A.
+ *  0b00100-0b11101..Select corresponding channel CHnA.
+ *  0b11110..Select CH30A.
+ *  0b11111..Select CH31A.
+ */
+#define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
+
+#define ADC_CMDL_CTYPE_MASK                      (0x60U)
+#define ADC_CMDL_CTYPE_SHIFT                     (5U)
+/*! CTYPE - Conversion Type
+ *  0b00..Single-Ended Mode. Only A side channel is converted.
+ *  0b01-0b11..Reserved.
+ */
+#define ADC_CMDL_CTYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK)
+
+#define ADC_CMDL_MODE_MASK                       (0x80U)
+#define ADC_CMDL_MODE_SHIFT                      (7U)
+/*! MODE - Select Resolution of Conversions
+ *  0b0..Standard resolution. Single-ended 12-bit conversion.
+ *  0b1..High resolution. Single-ended 16-bit conversion.
+ */
+#define ADC_CMDL_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK)
+/*! @} */
+
+/* The count of ADC_CMDL */
+#define ADC_CMDL_COUNT                           (7U)
+
+/*! @name CMDH - Command High Buffer Register */
+/*! @{ */
+
+#define ADC_CMDH_CMPEN_MASK                      (0x3U)
+#define ADC_CMDH_CMPEN_SHIFT                     (0U)
+/*! CMPEN - Compare Function Enable
+ *  0b00..Compare disabled.
+ *  0b01..Reserved
+ *  0b10..Compare enabled. Store on true.
+ *  0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
+ */
+#define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
+
+#define ADC_CMDH_WAIT_TRIG_MASK                  (0x4U)
+#define ADC_CMDH_WAIT_TRIG_SHIFT                 (2U)
+/*! WAIT_TRIG - Wait for Trigger Assertion before Execution.
+ *  0b0..This command will be automatically executed.
+ *  0b1..The active trigger must be asserted again before executing this command.
+ */
+#define ADC_CMDH_WAIT_TRIG(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)
+
+#define ADC_CMDH_LWI_MASK                        (0x80U)
+#define ADC_CMDH_LWI_SHIFT                       (7U)
+/*! LWI - Loop with Increment
+ *  0b0..Auto channel increment disabled
+ *  0b1..Auto channel increment enabled
+ */
+#define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
+
+#define ADC_CMDH_STS_MASK                        (0x700U)
+#define ADC_CMDH_STS_SHIFT                       (8U)
+/*! STS - Sample Time Select
+ *  0b000..Minimum sample time of 3.5 ADCK cycles.
+ *  0b001..3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time.
+ *  0b010..3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time.
+ *  0b011..3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time.
+ *  0b100..3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time.
+ *  0b101..3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time.
+ *  0b110..3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time.
+ *  0b111..3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time.
+ */
+#define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
+
+#define ADC_CMDH_AVGS_MASK                       (0xF000U)
+#define ADC_CMDH_AVGS_SHIFT                      (12U)
+/*! AVGS - Hardware Average Select
+ *  0b0000..Single conversion.
+ *  0b0001..2 conversions averaged.
+ *  0b0010..4 conversions averaged.
+ *  0b0011..8 conversions averaged.
+ *  0b0100..16 conversions averaged.
+ *  0b0101..32 conversions averaged.
+ *  0b0110..64 conversions averaged.
+ *  0b0111..128 conversions averaged.
+ *  0b1000..256 conversions averaged.
+ *  0b1001..512 conversions averaged.
+ *  0b1010..1024 conversions averaged.
+ */
+#define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
+
+#define ADC_CMDH_LOOP_MASK                       (0xF0000U)
+#define ADC_CMDH_LOOP_SHIFT                      (16U)
+/*! LOOP - Loop Count Select
+ *  0b0000..Looping not enabled. Command executes 1 time.
+ *  0b0001..Loop 1 time. Command executes 2 times.
+ *  0b0010..Loop 2 times. Command executes 3 times.
+ *  0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
+ *  0b1111..Loop 15 times. Command executes 16 times.
+ */
+#define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
+
+#define ADC_CMDH_NEXT_MASK                       (0x7000000U)
+#define ADC_CMDH_NEXT_SHIFT                      (24U)
+/*! NEXT - Next Command Select
+ *  0b000..No next command defined. Terminate conversions at completion of current command. If lower priority
+ *         trigger pending, begin command associated with lower priority trigger.
+ *  0b001..Select CMD1 command buffer register as next command.
+ *  0b010-0b110..Select corresponding CMD command buffer register as next command
+ *  0b111..Select CMD7 command buffer register as next command.
+ */
+#define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
+/*! @} */
+
+/* The count of ADC_CMDH */
+#define ADC_CMDH_COUNT                           (7U)
+
+/*! @name CV - Compare Value Register */
+/*! @{ */
+
+#define ADC_CV_CVL_MASK                          (0xFFFFU)
+#define ADC_CV_CVL_SHIFT                         (0U)
+/*! CVL - Compare Value Low */
+#define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
+
+#define ADC_CV_CVH_MASK                          (0xFFFF0000U)
+#define ADC_CV_CVH_SHIFT                         (16U)
+/*! CVH - Compare Value High */
+#define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
+/*! @} */
+
+/*! @name RESFIFO - Data Result FIFO Register */
+/*! @{ */
+
+#define ADC_RESFIFO_D_MASK                       (0xFFFFU)
+#define ADC_RESFIFO_D_SHIFT                      (0U)
+/*! D - Data Result */
+#define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
+
+#define ADC_RESFIFO_TSRC_MASK                    (0x30000U)
+#define ADC_RESFIFO_TSRC_SHIFT                   (16U)
+/*! TSRC - Trigger Source
+ *  0b00..Trigger source 0 initiated this conversion.
+ *  0b01..Trigger source 1 initiated this conversion.
+ *  0b10..Trigger source 2 initiated this conversion.
+ *  0b11..Trigger source 3 initiated this conversion.
+ */
+#define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
+
+#define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
+#define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
+/*! LOOPCNT - Loop Count Value
+ *  0b0000..Result is from initial conversion in command.
+ *  0b0001..Result is from second conversion in command.
+ *  0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
+ *  0b1111..Result is from 16th conversion in command.
+ */
+#define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
+
+#define ADC_RESFIFO_CMDSRC_MASK                  (0x7000000U)
+#define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
+/*! CMDSRC - Command Buffer Source
+ *  0b000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior
+ *         to an ADC conversion result dataword being stored to a RESFIFO buffer.
+ *  0b001..CMD1 buffer used as control settings for this conversion.
+ *  0b010-0b110..Corresponding command buffer used as control settings for this conversion.
+ *  0b111..CMD7 buffer used as control settings for this conversion.
+ */
+#define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
+
+#define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
+#define ADC_RESFIFO_VALID_SHIFT                  (31U)
+/*! VALID - FIFO Entry is Valid
+ *  0b0..FIFO is empty. Discard any read from RESFIFO.
+ *  0b1..FIFO record read from RESFIFO is valid.
+ */
+#define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
+/*! @} */
+
+/*! @name CAL_GAR - Calibration General A-Side Registers */
+/*! @{ */
+
+#define ADC_CAL_GAR_CAL_GAR_VAL_MASK             (0xFFFFU)
+#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT            (0U)
+/*! CAL_GAR_VAL - Calibration General A Side Register Element */
+#define ADC_CAL_GAR_CAL_GAR_VAL(x)               (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK)
+/*! @} */
+
+/*! @name CFG2 - Configuration 2 Register */
+/*! @{ */
+
+#define ADC_CFG2_JLEFT_MASK                      (0x100U)
+#define ADC_CFG2_JLEFT_SHIFT                     (8U)
+/*! JLEFT - Justified Left Enable register */
+#define ADC_CFG2_JLEFT(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_JLEFT_SHIFT)) & ADC_CFG2_JLEFT_MASK)
+
+#define ADC_CFG2_HS_MASK                         (0x200U)
+#define ADC_CFG2_HS_SHIFT                        (9U)
+/*! HS - High Speed Enable register
+ *  0b0..High speed conversion mode disabled
+ *  0b1..High speed conversion mode enabled
+ */
+#define ADC_CFG2_HS(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_HS_SHIFT)) & ADC_CFG2_HS_MASK)
+
+#define ADC_CFG2_HSEXTRA_MASK                    (0x400U)
+#define ADC_CFG2_HSEXTRA_SHIFT                   (10U)
+/*! HSEXTRA - High Speed Extra register
+ *  0b0..No extra cycle added
+ *  0b1..Extra cycle added
+ */
+#define ADC_CFG2_HSEXTRA(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_HSEXTRA_SHIFT)) & ADC_CFG2_HSEXTRA_MASK)
+
+#define ADC_CFG2_TUNE_MASK                       (0x3000U)
+#define ADC_CFG2_TUNE_SHIFT                      (12U)
+/*! TUNE - Tune Mode register */
+#define ADC_CFG2_TUNE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_TUNE_SHIFT)) & ADC_CFG2_TUNE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+/* Backward compatibility */
+#define ADC_CTRL_RSTFIFO_MASK                     ADC_CTRL_RSTFIFO0_MASK
+#define ADC_CTRL_RSTFIFO_SHIFT                    ADC_CTRL_RSTFIFO0_SHIFT
+#define ADC_CTRL_RSTFIFO(x)                       ADC_CTRL_RSTFIFO0(x)
+#define ADC_STAT_RDY_MASK                         ADC_STAT_RDY0_MASK
+#define ADC_STAT_RDY_SHIFT                        ADC_STAT_RDY0_SHIFT
+#define ADC_STAT_RDY(x)                           ADC_STAT_RDY0(x)
+#define ADC_STAT_FOF_MASK                         ADC_STAT_FOF0_MASK
+#define ADC_STAT_FOF_SHIFT                        ADC_STAT_FOF0_SHIFT
+#define ADC_STAT_FOF(x)                           ADC_STAT_FOF0(x)
+#define ADC_IE_FWMIE_MASK                         ADC_IE_FWMIE0_MASK
+#define ADC_IE_FWMIE_SHIFT                        ADC_IE_FWMIE0_SHIFT
+#define ADC_IE_FWMIE(x)                           ADC_IE_FWMIE0(x)
+#define ADC_IE_FOFIE_MASK                         ADC_IE_FOFIE0_MASK
+#define ADC_IE_FOFIE_SHIFT                        ADC_IE_FOFIE0_SHIFT
+#define ADC_IE_FOFIE(x)                           ADC_IE_FOFIE0(x)
+#define ADC_DE_FWMDE_MASK                         ADC_DE_FWMDE0_MASK
+#define ADC_DE_FWMDE_SHIFT                        ADC_DE_FWMDE0_SHIFT
+#define ADC_DE_FWMDE(x)                           ADC_DE_FWMDE0(x)
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_ADC_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_AOI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_AOI.h
new file mode 100644
index 0000000000..8e4698ff51
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_AOI.h
@@ -0,0 +1,322 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for AOI
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_AOI.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for AOI
+ *
+ * CMSIS Peripheral Access Layer for AOI
+ */
+
+#if !defined(PERI_AOI_H_)
+#define PERI_AOI_H_                              /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- AOI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
+ * @{
+ */
+
+/** AOI - Size of Registers Arrays */
+#define AOI_BFCRT_COUNT                           4u
+
+/** AOI - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x4 */
+    __IO uint16_t BFCRT01;                           /**< Boolean Function Term 0 and 1 Configuration for EVENT0..Boolean Function Term 0 and 1 Configuration for EVENT3, array offset: 0x0, array step: 0x4 */
+    __IO uint16_t BFCRT23;                           /**< Boolean Function Term 2 and 3 Configuration for EVENT0..Boolean Function Term 2 and 3 Configuration for EVENT3, array offset: 0x2, array step: 0x4 */
+  } BFCRT[AOI_BFCRT_COUNT];
+} AOI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- AOI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AOI_Register_Masks AOI Register Masks
+ * @{
+ */
+
+/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration for EVENT0..Boolean Function Term 0 and 1 Configuration for EVENT3 */
+/*! @{ */
+
+#define AOI_BFCRT01_PT1_DC_MASK                  (0x3U)
+#define AOI_BFCRT01_PT1_DC_SHIFT                 (0U)
+/*! PT1_DC - Product Term 1, Input D Configuration
+ *  0b00..Force input D to become 0
+ *  0b01..Pass input D
+ *  0b10..Complement input D
+ *  0b11..Force input D to become 1
+ */
+#define AOI_BFCRT01_PT1_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
+
+#define AOI_BFCRT01_PT1_CC_MASK                  (0xCU)
+#define AOI_BFCRT01_PT1_CC_SHIFT                 (2U)
+/*! PT1_CC - Product Term 1, Input C Configuration
+ *  0b00..Force input C to become 0
+ *  0b01..Pass input C
+ *  0b10..Complement input C
+ *  0b11..Force input C to become 1
+ */
+#define AOI_BFCRT01_PT1_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
+
+#define AOI_BFCRT01_PT1_BC_MASK                  (0x30U)
+#define AOI_BFCRT01_PT1_BC_SHIFT                 (4U)
+/*! PT1_BC - Product Term 1, Input B Configuration
+ *  0b00..Force input B to become 0
+ *  0b01..Pass input B
+ *  0b10..Complement input B
+ *  0b11..Force input B to become 1
+ */
+#define AOI_BFCRT01_PT1_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
+
+#define AOI_BFCRT01_PT1_AC_MASK                  (0xC0U)
+#define AOI_BFCRT01_PT1_AC_SHIFT                 (6U)
+/*! PT1_AC - Product Term 1, Input A Configuration
+ *  0b00..Force input A to become 0
+ *  0b01..Pass input A
+ *  0b10..Complement input A
+ *  0b11..Force input A to become 1
+ */
+#define AOI_BFCRT01_PT1_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
+
+#define AOI_BFCRT01_PT0_DC_MASK                  (0x300U)
+#define AOI_BFCRT01_PT0_DC_SHIFT                 (8U)
+/*! PT0_DC - Product Term 0, Input D Configuration
+ *  0b00..Force input D to become 0
+ *  0b01..Pass input D
+ *  0b10..Complement input D
+ *  0b11..Force input D to become 1
+ */
+#define AOI_BFCRT01_PT0_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
+
+#define AOI_BFCRT01_PT0_CC_MASK                  (0xC00U)
+#define AOI_BFCRT01_PT0_CC_SHIFT                 (10U)
+/*! PT0_CC - Product Term 0, Input C Configuration
+ *  0b00..Force input C to become 0
+ *  0b01..Pass input C
+ *  0b10..Complement input C
+ *  0b11..Force input C to become 1
+ */
+#define AOI_BFCRT01_PT0_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
+
+#define AOI_BFCRT01_PT0_BC_MASK                  (0x3000U)
+#define AOI_BFCRT01_PT0_BC_SHIFT                 (12U)
+/*! PT0_BC - Product Term 0, Input B Configuration
+ *  0b00..Force input B to become 0
+ *  0b01..Pass input B
+ *  0b10..Complement input B
+ *  0b11..Force input B to become 1
+ */
+#define AOI_BFCRT01_PT0_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
+
+#define AOI_BFCRT01_PT0_AC_MASK                  (0xC000U)
+#define AOI_BFCRT01_PT0_AC_SHIFT                 (14U)
+/*! PT0_AC - Product Term 0, Input A Configuration
+ *  0b00..Force input A to become 0
+ *  0b01..Pass input A
+ *  0b10..Complement input A
+ *  0b11..Force input A to become 1
+ */
+#define AOI_BFCRT01_PT0_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
+/*! @} */
+
+/* The count of AOI_BFCRT01 */
+#define AOI_BFCRT01_COUNT                        (4U)
+
+/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration for EVENT0..Boolean Function Term 2 and 3 Configuration for EVENT3 */
+/*! @{ */
+
+#define AOI_BFCRT23_PT3_DC_MASK                  (0x3U)
+#define AOI_BFCRT23_PT3_DC_SHIFT                 (0U)
+/*! PT3_DC - Product Term 3, Input D Configuration
+ *  0b00..Force input D to become 0
+ *  0b01..Pass input D
+ *  0b10..Complement input D
+ *  0b11..Force input D to become 1
+ */
+#define AOI_BFCRT23_PT3_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
+
+#define AOI_BFCRT23_PT3_CC_MASK                  (0xCU)
+#define AOI_BFCRT23_PT3_CC_SHIFT                 (2U)
+/*! PT3_CC - Product Term 3, Input C Configuration
+ *  0b00..Force input C to become 0
+ *  0b01..Pass input C
+ *  0b10..Complement input C
+ *  0b11..Force input C to become 1
+ */
+#define AOI_BFCRT23_PT3_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
+
+#define AOI_BFCRT23_PT3_BC_MASK                  (0x30U)
+#define AOI_BFCRT23_PT3_BC_SHIFT                 (4U)
+/*! PT3_BC - Product Term 3, Input B Configuration
+ *  0b00..Force input B to become 0
+ *  0b01..Pass input B
+ *  0b10..Complement input B
+ *  0b11..Force input B to become 1
+ */
+#define AOI_BFCRT23_PT3_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
+
+#define AOI_BFCRT23_PT3_AC_MASK                  (0xC0U)
+#define AOI_BFCRT23_PT3_AC_SHIFT                 (6U)
+/*! PT3_AC - Product Term 3, Input A Configuration
+ *  0b00..Force input A to become 0
+ *  0b01..Pass input A
+ *  0b10..Complement input A
+ *  0b11..Force input to become 1
+ */
+#define AOI_BFCRT23_PT3_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
+
+#define AOI_BFCRT23_PT2_DC_MASK                  (0x300U)
+#define AOI_BFCRT23_PT2_DC_SHIFT                 (8U)
+/*! PT2_DC - Product Term 2, Input D Configuration
+ *  0b00..Force input D to become 0
+ *  0b01..Pass input D
+ *  0b10..Complement input D
+ *  0b11..Force input D to become 1
+ */
+#define AOI_BFCRT23_PT2_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
+
+#define AOI_BFCRT23_PT2_CC_MASK                  (0xC00U)
+#define AOI_BFCRT23_PT2_CC_SHIFT                 (10U)
+/*! PT2_CC - Product Term 2, Input C Configuration
+ *  0b00..Force input C to become 0
+ *  0b01..Pass input C
+ *  0b10..Complement input C
+ *  0b11..Force input C to become 1
+ */
+#define AOI_BFCRT23_PT2_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
+
+#define AOI_BFCRT23_PT2_BC_MASK                  (0x3000U)
+#define AOI_BFCRT23_PT2_BC_SHIFT                 (12U)
+/*! PT2_BC - Product Term 2, Input B Configuration
+ *  0b00..Force input B to become 0
+ *  0b01..Pass input B
+ *  0b10..Complement input B
+ *  0b11..Force input B to become 1
+ */
+#define AOI_BFCRT23_PT2_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
+
+#define AOI_BFCRT23_PT2_AC_MASK                  (0xC000U)
+#define AOI_BFCRT23_PT2_AC_SHIFT                 (14U)
+/*! PT2_AC - Product Term 2, Input A Configuration
+ *  0b00..Force input A to become 0
+ *  0b01..Pass input A
+ *  0b10..Complement input A
+ *  0b11..Force input A to become 1
+ */
+#define AOI_BFCRT23_PT2_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
+/*! @} */
+
+/* The count of AOI_BFCRT23 */
+#define AOI_BFCRT23_COUNT                        (4U)
+
+
+/*!
+ * @}
+ */ /* end of group AOI_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group AOI_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_AOI_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CAN.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CAN.h
new file mode 100644
index 0000000000..e75c799b48
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CAN.h
@@ -0,0 +1,2255 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for CAN
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_CAN.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for CAN
+ *
+ * CMSIS Peripheral Access Layer for CAN
+ */
+
+#if !defined(PERI_CAN_H_)
+#define PERI_CAN_H_                              /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- CAN Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Size of Registers Arrays */
+#define CAN_MB_SIZE_MB_8B_GROUP_MB_8B_WORD_8B_COUNT 2u
+#define CAN_MB_SIZE_MB_8B_GROUP_MB_8B_COUNT       32u
+#define CAN_MB_SIZE_MB_16B_GROUP_MB_16B_WORD_16B_COUNT 4u
+#define CAN_MB_SIZE_MB_16B_GROUP_MB_16B_COUNT     21u
+#define CAN_MB_SIZE_MB_32B_GROUP_MB_32B_WORD_32B_COUNT 8u
+#define CAN_MB_SIZE_MB_32B_GROUP_MB_32B_COUNT     12u
+#define CAN_MB_SIZE_MB_64B_GROUP_MB_64B_WORD_64B_COUNT 16u
+#define CAN_MB_SIZE_MB_64B_GROUP_MB_64B_COUNT     7u
+#define CAN_MB_SIZE_MB_GROUP_MB_COUNT             32u
+#define CAN_RXIMR_COUNT                           32u
+#define CAN_WMB_COUNT                             4u
+#define CAN_ERFFEL_COUNT                          32u
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration, offset: 0x0 */
+  __IO uint32_t CTRL1;                             /**< Control 1, offset: 0x4 */
+  __IO uint32_t TIMER;                             /**< Free-Running Timer, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t RXMGMASK;                          /**< RX Message Buffers Global Mask, offset: 0x10 */
+  __IO uint32_t RX14MASK;                          /**< Receive 14 Mask, offset: 0x14 */
+  __IO uint32_t RX15MASK;                          /**< Receive 15 Mask, offset: 0x18 */
+  __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
+  __IO uint32_t ESR1;                              /**< Error and Status 1, offset: 0x20 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t IMASK1;                            /**< Interrupt Masks 1, offset: 0x28 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1, offset: 0x30 */
+  __IO uint32_t CTRL2;                             /**< Control 2, offset: 0x34 */
+  __I  uint32_t ESR2;                              /**< Error and Status 2, offset: 0x38 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t CRCR;                              /**< Cyclic Redundancy Check, offset: 0x44 */
+  __IO uint32_t RXFGMASK;                          /**< Legacy RX FIFO Global Mask, offset: 0x48 */
+  __I  uint32_t RXFIR;                             /**< Legacy RX FIFO Information, offset: 0x4C */
+  __IO uint32_t CBT;                               /**< CAN Bit Timing, offset: 0x50 */
+       uint8_t RESERVED_4[44];
+  union {                                          /* offset: 0x80 */
+    struct {                                         /* offset: 0x80, array step: 0x10 */
+      __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */
+      __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */
+      __IO uint32_t WORD[CAN_MB_SIZE_MB_8B_GROUP_MB_8B_WORD_8B_COUNT];     /**< Message Buffer 0 WORD_8B Register..Message Buffer 31 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */
+    } MB_8B[CAN_MB_SIZE_MB_8B_GROUP_MB_8B_COUNT];
+    struct {                                         /* offset: 0x80, array step: 0x18 */
+      __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18 */
+      __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18 */
+      __IO uint32_t WORD[CAN_MB_SIZE_MB_16B_GROUP_MB_16B_WORD_16B_COUNT];     /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */
+    } MB_16B[CAN_MB_SIZE_MB_16B_GROUP_MB_16B_COUNT];
+    struct {                                         /* offset: 0x80, array step: 0x28 */
+      __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28 */
+      __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28 */
+      __IO uint32_t WORD[CAN_MB_SIZE_MB_32B_GROUP_MB_32B_WORD_32B_COUNT];     /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */
+    } MB_32B[CAN_MB_SIZE_MB_32B_GROUP_MB_32B_COUNT];
+    struct {                                         /* offset: 0x80, array step: 0x48 */
+      __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48 */
+      __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48 */
+      __IO uint32_t WORD[CAN_MB_SIZE_MB_64B_GROUP_MB_64B_WORD_64B_COUNT];     /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */
+    } MB_64B[CAN_MB_SIZE_MB_64B_GROUP_MB_64B_COUNT];
+    struct {                                         /* offset: 0x80, array step: 0x10 */
+      __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */
+      __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */
+      __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register, array offset: 0x88, array step: 0x10 */
+      __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register, array offset: 0x8C, array step: 0x10 */
+    } MB[CAN_MB_SIZE_MB_GROUP_MB_COUNT];
+  };
+       uint8_t RESERVED_5[1536];
+  __IO uint32_t RXIMR[CAN_RXIMR_COUNT];            /**< Receive Individual Mask, array offset: 0x880, array step: 0x4 */
+       uint8_t RESERVED_6[512];
+  __IO uint32_t CTRL1_PN;                          /**< Pretended Networking Control 1, offset: 0xB00 */
+  __IO uint32_t CTRL2_PN;                          /**< Pretended Networking Control 2, offset: 0xB04 */
+  __IO uint32_t WU_MTC;                            /**< Pretended Networking Wake-Up Match, offset: 0xB08 */
+  __IO uint32_t FLT_ID1;                           /**< Pretended Networking ID Filter 1, offset: 0xB0C */
+  __IO uint32_t FLT_DLC;                           /**< Pretended Networking Data Length Code (DLC) Filter, offset: 0xB10 */
+  __IO uint32_t PL1_LO;                            /**< Pretended Networking Payload Low Filter 1, offset: 0xB14 */
+  __IO uint32_t PL1_HI;                            /**< Pretended Networking Payload High Filter 1, offset: 0xB18 */
+  __IO uint32_t FLT_ID2_IDMASK;                    /**< Pretended Networking ID Filter 2 or ID Mask, offset: 0xB1C */
+  __IO uint32_t PL2_PLMASK_LO;                     /**< Pretended Networking Payload Low Filter 2 and Payload Low Mask, offset: 0xB20 */
+  __IO uint32_t PL2_PLMASK_HI;                     /**< Pretended Networking Payload High Filter 2 and Payload High Mask, offset: 0xB24 */
+       uint8_t RESERVED_7[24];
+  struct {                                         /* offset: 0xB40, array step: 0x10 */
+    __I  uint32_t CS;                                /**< Wake-Up Message Buffer, array offset: 0xB40, array step: 0x10 */
+    __I  uint32_t ID;                                /**< Wake-Up Message Buffer for ID, array offset: 0xB44, array step: 0x10 */
+    __I  uint32_t D03;                               /**< Wake-Up Message Buffer for Data 0-3, array offset: 0xB48, array step: 0x10 */
+    __I  uint32_t D47;                               /**< Wake-Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */
+  } WMB[CAN_WMB_COUNT];
+       uint8_t RESERVED_8[112];
+  __IO uint32_t EPRS;                              /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */
+  __IO uint32_t ENCBT;                             /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */
+  __IO uint32_t EDCBT;                             /**< Enhanced Data Phase CAN Bit Timing, offset: 0xBF8 */
+  __IO uint32_t ETDC;                              /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */
+  __IO uint32_t FDCTRL;                            /**< CAN FD Control, offset: 0xC00 */
+  __IO uint32_t FDCBT;                             /**< CAN FD Bit Timing, offset: 0xC04 */
+  __I  uint32_t FDCRC;                             /**< CAN FD CRC, offset: 0xC08 */
+  __IO uint32_t ERFCR;                             /**< Enhanced RX FIFO Control, offset: 0xC0C */
+  __IO uint32_t ERFIER;                            /**< Enhanced RX FIFO Interrupt Enable, offset: 0xC10 */
+  __IO uint32_t ERFSR;                             /**< Enhanced RX FIFO Status, offset: 0xC14 */
+       uint8_t RESERVED_9[9192];
+  __IO uint32_t ERFFEL[CAN_ERFFEL_COUNT];          /**< Enhanced RX FIFO Filter Element, array offset: 0x3000, array step: 0x4 */
+} CAN_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CAN Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/*! @name MCR - Module Configuration */
+/*! @{ */
+
+#define CAN_MCR_MAXMB_MASK                       (0x7FU)
+#define CAN_MCR_MAXMB_SHIFT                      (0U)
+/*! MAXMB - Number of the Last Message Buffer */
+#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
+
+#define CAN_MCR_IDAM_MASK                        (0x300U)
+#define CAN_MCR_IDAM_SHIFT                       (8U)
+/*! IDAM - ID Acceptance Mode
+ *  0b00..Format A: One full ID (standard and extended) per ID filter table element.
+ *  0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
+ *  0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
+ *  0b11..Format D: All frames rejected.
+ */
+#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
+
+#define CAN_MCR_FDEN_MASK                        (0x800U)
+#define CAN_MCR_FDEN_SHIFT                       (11U)
+/*! FDEN - CAN FD Operation Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_MCR_FDEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
+
+#define CAN_MCR_AEN_MASK                         (0x1000U)
+#define CAN_MCR_AEN_SHIFT                        (12U)
+/*! AEN - Abort Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
+
+#define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
+#define CAN_MCR_LPRIOEN_SHIFT                    (13U)
+/*! LPRIOEN - Local Priority Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
+
+#define CAN_MCR_PNET_EN_MASK                     (0x4000U)
+#define CAN_MCR_PNET_EN_SHIFT                    (14U)
+/*! PNET_EN - Pretended Networking Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_MCR_PNET_EN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_PNET_EN_SHIFT)) & CAN_MCR_PNET_EN_MASK)
+
+#define CAN_MCR_DMA_MASK                         (0x8000U)
+#define CAN_MCR_DMA_SHIFT                        (15U)
+/*! DMA - DMA Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_MCR_DMA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
+
+#define CAN_MCR_IRMQ_MASK                        (0x10000U)
+#define CAN_MCR_IRMQ_SHIFT                       (16U)
+/*! IRMQ - Individual RX Masking and Queue Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
+
+#define CAN_MCR_SRXDIS_MASK                      (0x20000U)
+#define CAN_MCR_SRXDIS_SHIFT                     (17U)
+/*! SRXDIS - Self-Reception Disable
+ *  0b0..Enable
+ *  0b1..Disable
+ */
+#define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
+
+#define CAN_MCR_DOZE_MASK                        (0x40000U)
+#define CAN_MCR_DOZE_SHIFT                       (18U)
+/*! DOZE - Doze Mode Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
+
+#define CAN_MCR_WAKSRC_MASK                      (0x80000U)
+#define CAN_MCR_WAKSRC_SHIFT                     (19U)
+/*! WAKSRC - Wake-Up Source
+ *  0b0..No filter applied
+ *  0b1..Filter applied
+ */
+#define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
+
+#define CAN_MCR_LPMACK_MASK                      (0x100000U)
+#define CAN_MCR_LPMACK_SHIFT                     (20U)
+/*! LPMACK - Low-Power Mode Acknowledge
+ *  0b0..Not in a low-power mode
+ *  0b1..In a low-power mode
+ */
+#define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
+
+#define CAN_MCR_WRNEN_MASK                       (0x200000U)
+#define CAN_MCR_WRNEN_SHIFT                      (21U)
+/*! WRNEN - Warning Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
+
+#define CAN_MCR_SLFWAK_MASK                      (0x400000U)
+#define CAN_MCR_SLFWAK_SHIFT                     (22U)
+/*! SLFWAK - Self-Wake-Up Feature
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
+
+#define CAN_MCR_SUPV_MASK                        (0x800000U)
+#define CAN_MCR_SUPV_SHIFT                       (23U)
+/*! SUPV - Supervisor Mode
+ *  0b0..User mode
+ *  0b1..Supervisor mode
+ */
+#define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
+
+#define CAN_MCR_FRZACK_MASK                      (0x1000000U)
+#define CAN_MCR_FRZACK_SHIFT                     (24U)
+/*! FRZACK - Freeze Mode Acknowledge
+ *  0b0..Not in Freeze mode, prescaler running.
+ *  0b1..In Freeze mode, prescaler stopped.
+ */
+#define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
+
+#define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
+#define CAN_MCR_SOFTRST_SHIFT                    (25U)
+/*! SOFTRST - Soft Reset
+ *  0b0..No reset
+ *  0b1..Soft reset affects reset registers
+ */
+#define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
+
+#define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
+#define CAN_MCR_WAKMSK_SHIFT                     (26U)
+/*! WAKMSK - Wake-up Interrupt Mask
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
+
+#define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
+#define CAN_MCR_NOTRDY_SHIFT                     (27U)
+/*! NOTRDY - FlexCAN Not Ready
+ *  0b0..FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode.
+ *  0b1..FlexCAN is in Disable mode, Doze mode, Stop mode, or Freeze mode.
+ */
+#define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
+
+#define CAN_MCR_HALT_MASK                        (0x10000000U)
+#define CAN_MCR_HALT_SHIFT                       (28U)
+/*! HALT - Halt FlexCAN
+ *  0b0..No request
+ *  0b1..Enter Freeze mode, if MCR[FRZ] = 1.
+ */
+#define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
+
+#define CAN_MCR_RFEN_MASK                        (0x20000000U)
+#define CAN_MCR_RFEN_SHIFT                       (29U)
+/*! RFEN - Legacy RX FIFO Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
+
+#define CAN_MCR_FRZ_MASK                         (0x40000000U)
+#define CAN_MCR_FRZ_SHIFT                        (30U)
+/*! FRZ - Freeze Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
+
+#define CAN_MCR_MDIS_MASK                        (0x80000000U)
+#define CAN_MCR_MDIS_SHIFT                       (31U)
+/*! MDIS - Module Disable
+ *  0b0..Enable
+ *  0b1..Disable
+ */
+#define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
+/*! @} */
+
+/*! @name CTRL1 - Control 1 */
+/*! @{ */
+
+#define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
+#define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
+/*! PROPSEG - Propagation Segment */
+#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
+
+#define CAN_CTRL1_LOM_MASK                       (0x8U)
+#define CAN_CTRL1_LOM_SHIFT                      (3U)
+/*! LOM - Listen-Only Mode
+ *  0b0..Listen-Only mode is deactivated.
+ *  0b1..FlexCAN module operates in Listen-Only mode.
+ */
+#define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
+
+#define CAN_CTRL1_LBUF_MASK                      (0x10U)
+#define CAN_CTRL1_LBUF_SHIFT                     (4U)
+/*! LBUF - Lowest Buffer Transmitted First
+ *  0b0..Buffer with highest priority is transmitted first.
+ *  0b1..Lowest number buffer is transmitted first.
+ */
+#define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
+
+#define CAN_CTRL1_TSYN_MASK                      (0x20U)
+#define CAN_CTRL1_TSYN_SHIFT                     (5U)
+/*! TSYN - Timer Sync
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
+
+#define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
+#define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
+/*! BOFFREC - Bus Off Recovery
+ *  0b0..Enabled
+ *  0b1..Disabled
+ */
+#define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
+
+#define CAN_CTRL1_SMP_MASK                       (0x80U)
+#define CAN_CTRL1_SMP_SHIFT                      (7U)
+/*! SMP - CAN Bit Sampling
+ *  0b0..One sample is used to determine the bit value.
+ *  0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
+ *       preceding samples. A majority rule is used.
+ */
+#define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
+
+#define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
+#define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
+/*! RWRNMSK - RX Warning Interrupt Mask
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
+
+#define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
+#define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
+/*! TWRNMSK - TX Warning Interrupt Mask
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
+
+#define CAN_CTRL1_LPB_MASK                       (0x1000U)
+#define CAN_CTRL1_LPB_SHIFT                      (12U)
+/*! LPB - Loopback Mode
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
+
+#define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
+#define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
+/*! ERRMSK - Error Interrupt Mask
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
+#define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
+
+#define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
+#define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
+/*! BOFFMSK - Bus Off Interrupt Mask
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
+#define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
+
+#define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
+#define CAN_CTRL1_PSEG2_SHIFT                    (16U)
+/*! PSEG2 - Phase Segment 2 */
+#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
+
+#define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
+#define CAN_CTRL1_PSEG1_SHIFT                    (19U)
+/*! PSEG1 - Phase Segment 1 */
+#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
+
+#define CAN_CTRL1_RJW_MASK                       (0xC00000U)
+#define CAN_CTRL1_RJW_SHIFT                      (22U)
+/*! RJW - Resync Jump Width */
+#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
+
+#define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
+#define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
+/*! PRESDIV - Prescaler Division Factor */
+#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
+/*! @} */
+
+/*! @name TIMER - Free-Running Timer */
+/*! @{ */
+
+#define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
+#define CAN_TIMER_TIMER_SHIFT                    (0U)
+/*! TIMER - Timer Value */
+#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
+/*! @} */
+
+/*! @name RXMGMASK - RX Message Buffers Global Mask */
+/*! @{ */
+
+#define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
+#define CAN_RXMGMASK_MG_SHIFT                    (0U)
+/*! MG - Global Mask for RX Message Buffers */
+#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
+/*! @} */
+
+/*! @name RX14MASK - Receive 14 Mask */
+/*! @{ */
+
+#define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
+#define CAN_RX14MASK_RX14M_SHIFT                 (0U)
+/*! RX14M - RX Buffer 14 Mask Bits */
+#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
+/*! @} */
+
+/*! @name RX15MASK - Receive 15 Mask */
+/*! @{ */
+
+#define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
+#define CAN_RX15MASK_RX15M_SHIFT                 (0U)
+/*! RX15M - RX Buffer 15 Mask Bits */
+#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
+/*! @} */
+
+/*! @name ECR - Error Counter */
+/*! @{ */
+
+#define CAN_ECR_TXERRCNT_MASK                    (0xFFU)
+#define CAN_ECR_TXERRCNT_SHIFT                   (0U)
+/*! TXERRCNT - Transmit Error Counter */
+#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
+
+#define CAN_ECR_RXERRCNT_MASK                    (0xFF00U)
+#define CAN_ECR_RXERRCNT_SHIFT                   (8U)
+/*! RXERRCNT - Receive Error Counter */
+#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
+
+#define CAN_ECR_TXERRCNT_FAST_MASK               (0xFF0000U)
+#define CAN_ECR_TXERRCNT_FAST_SHIFT              (16U)
+/*! TXERRCNT_FAST - Transmit Error Counter for Fast Bits */
+#define CAN_ECR_TXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
+
+#define CAN_ECR_RXERRCNT_FAST_MASK               (0xFF000000U)
+#define CAN_ECR_RXERRCNT_FAST_SHIFT              (24U)
+/*! RXERRCNT_FAST - Receive Error Counter for Fast Bits */
+#define CAN_ECR_RXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
+/*! @} */
+
+/*! @name ESR1 - Error and Status 1 */
+/*! @{ */
+
+#define CAN_ESR1_WAKINT_MASK                     (0x1U)
+#define CAN_ESR1_WAKINT_SHIFT                    (0U)
+/*! WAKINT - Wake-up Interrupt Flag
+ *  0b0..No such occurrence.
+ *  0b1..Indicates that a recessive-to-dominant transition was received on the CAN bus.
+ */
+#define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
+
+#define CAN_ESR1_ERRINT_MASK                     (0x2U)
+#define CAN_ESR1_ERRINT_SHIFT                    (1U)
+/*! ERRINT - Error Interrupt Flag
+ *  0b0..No such occurrence.
+ *  0b1..Indicates setting of any error flag in the Error and Status register.
+ */
+#define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
+
+#define CAN_ESR1_BOFFINT_MASK                    (0x4U)
+#define CAN_ESR1_BOFFINT_SHIFT                   (2U)
+/*! BOFFINT - Bus Off Interrupt Flag
+ *  0b0..No such occurrence.
+ *  0b1..FlexCAN module entered Bus Off state.
+ */
+#define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
+
+#define CAN_ESR1_RX_MASK                         (0x8U)
+#define CAN_ESR1_RX_SHIFT                        (3U)
+/*! RX - FlexCAN in Reception Flag
+ *  0b0..Not receiving
+ *  0b1..Receiving
+ */
+#define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
+
+#define CAN_ESR1_FLTCONF_MASK                    (0x30U)
+#define CAN_ESR1_FLTCONF_SHIFT                   (4U)
+/*! FLTCONF - Fault Confinement State
+ *  0b00..Error Active
+ *  0b01..Error Passive
+ *  0b1x..Bus Off
+ */
+#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
+
+#define CAN_ESR1_TX_MASK                         (0x40U)
+#define CAN_ESR1_TX_SHIFT                        (6U)
+/*! TX - FlexCAN In Transmission
+ *  0b0..Not transmitting
+ *  0b1..Transmitting
+ */
+#define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
+
+#define CAN_ESR1_IDLE_MASK                       (0x80U)
+#define CAN_ESR1_IDLE_SHIFT                      (7U)
+/*! IDLE - Idle
+ *  0b0..Not IDLE
+ *  0b1..IDLE
+ */
+#define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
+
+#define CAN_ESR1_RXWRN_MASK                      (0x100U)
+#define CAN_ESR1_RXWRN_SHIFT                     (8U)
+/*! RXWRN - RX Error Warning Flag
+ *  0b0..No such occurrence.
+ *  0b1..RXERRCNT is greater than or equal to 96.
+ */
+#define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
+
+#define CAN_ESR1_TXWRN_MASK                      (0x200U)
+#define CAN_ESR1_TXWRN_SHIFT                     (9U)
+/*! TXWRN - TX Error Warning Flag
+ *  0b0..No such occurrence.
+ *  0b1..TXERRCNT is 96 or greater.
+ */
+#define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
+
+#define CAN_ESR1_STFERR_MASK                     (0x400U)
+#define CAN_ESR1_STFERR_SHIFT                    (10U)
+/*! STFERR - Stuffing Error Flag
+ *  0b0..No error
+ *  0b1..Error occurred since last read of this register.
+ */
+#define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
+
+#define CAN_ESR1_FRMERR_MASK                     (0x800U)
+#define CAN_ESR1_FRMERR_SHIFT                    (11U)
+/*! FRMERR - Form Error Flag
+ *  0b0..No error
+ *  0b1..Error occurred since last read of this register.
+ */
+#define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
+
+#define CAN_ESR1_CRCERR_MASK                     (0x1000U)
+#define CAN_ESR1_CRCERR_SHIFT                    (12U)
+/*! CRCERR - Cyclic Redundancy Check Error Flag
+ *  0b0..No error
+ *  0b1..Error occurred since last read of this register.
+ */
+#define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
+
+#define CAN_ESR1_ACKERR_MASK                     (0x2000U)
+#define CAN_ESR1_ACKERR_SHIFT                    (13U)
+/*! ACKERR - Acknowledge Error Flag
+ *  0b0..No error
+ *  0b1..Error occurred since last read of this register.
+ */
+#define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
+
+#define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
+#define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
+/*! BIT0ERR - Bit0 Error Flag
+ *  0b0..No such occurrence.
+ *  0b1..At least one bit sent as dominant is received as recessive.
+ */
+#define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
+
+#define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
+#define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
+/*! BIT1ERR - Bit1 Error Flag
+ *  0b0..No such occurrence.
+ *  0b1..At least one bit sent as recessive is received as dominant.
+ */
+#define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
+
+#define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
+#define CAN_ESR1_RWRNINT_SHIFT                   (16U)
+/*! RWRNINT - RX Warning Interrupt Flag
+ *  0b0..No such occurrence
+ *  0b1..RX error counter changed from less than 96 to greater than or equal to 96.
+ */
+#define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
+
+#define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
+#define CAN_ESR1_TWRNINT_SHIFT                   (17U)
+/*! TWRNINT - TX Warning Interrupt Flag
+ *  0b0..No such occurrence
+ *  0b1..TX error counter changed from less than 96 to greater than or equal to 96.
+ */
+#define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
+
+#define CAN_ESR1_SYNCH_MASK                      (0x40000U)
+#define CAN_ESR1_SYNCH_SHIFT                     (18U)
+/*! SYNCH - CAN Synchronization Status Flag
+ *  0b0..Not synchronized
+ *  0b1..Synchronized
+ */
+#define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
+
+#define CAN_ESR1_BOFFDONEINT_MASK                (0x80000U)
+#define CAN_ESR1_BOFFDONEINT_SHIFT               (19U)
+/*! BOFFDONEINT - Bus Off Done Interrupt Flag
+ *  0b0..No such occurrence
+ *  0b1..FlexCAN module has completed Bus Off process.
+ */
+#define CAN_ESR1_BOFFDONEINT(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
+
+#define CAN_ESR1_ERRINT_FAST_MASK                (0x100000U)
+#define CAN_ESR1_ERRINT_FAST_SHIFT               (20U)
+/*! ERRINT_FAST - Fast Error Interrupt Flag
+ *  0b0..No such occurrence.
+ *  0b1..Error flag set in the data phase of CAN FD frames that have BRS = 1.
+ */
+#define CAN_ESR1_ERRINT_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
+
+#define CAN_ESR1_ERROVR_MASK                     (0x200000U)
+#define CAN_ESR1_ERROVR_SHIFT                    (21U)
+/*! ERROVR - Error Overrun Flag
+ *  0b0..No overrun
+ *  0b1..Overrun
+ */
+#define CAN_ESR1_ERROVR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
+
+#define CAN_ESR1_STFERR_FAST_MASK                (0x4000000U)
+#define CAN_ESR1_STFERR_FAST_SHIFT               (26U)
+/*! STFERR_FAST - Fast Stuffing Error Flag
+ *  0b0..No such occurrence.
+ *  0b1..A stuffing error occurred since last read of this register.
+ */
+#define CAN_ESR1_STFERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
+
+#define CAN_ESR1_FRMERR_FAST_MASK                (0x8000000U)
+#define CAN_ESR1_FRMERR_FAST_SHIFT               (27U)
+/*! FRMERR_FAST - Fast Form Error Flag
+ *  0b0..No such occurrence.
+ *  0b1..A form error occurred since last read of this register.
+ */
+#define CAN_ESR1_FRMERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
+
+#define CAN_ESR1_CRCERR_FAST_MASK                (0x10000000U)
+#define CAN_ESR1_CRCERR_FAST_SHIFT               (28U)
+/*! CRCERR_FAST - Fast Cyclic Redundancy Check Error Flag
+ *  0b0..No such occurrence.
+ *  0b1..A CRC error occurred since last read of this register.
+ */
+#define CAN_ESR1_CRCERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
+
+#define CAN_ESR1_BIT0ERR_FAST_MASK               (0x40000000U)
+#define CAN_ESR1_BIT0ERR_FAST_SHIFT              (30U)
+/*! BIT0ERR_FAST - Fast Bit0 Error Flag
+ *  0b0..No such occurrence.
+ *  0b1..At least one bit transmitted as dominant is received as recessive.
+ */
+#define CAN_ESR1_BIT0ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
+
+#define CAN_ESR1_BIT1ERR_FAST_MASK               (0x80000000U)
+#define CAN_ESR1_BIT1ERR_FAST_SHIFT              (31U)
+/*! BIT1ERR_FAST - Fast Bit1 Error Flag
+ *  0b0..No such occurrence.
+ *  0b1..At least one bit transmitted as recessive is received as dominant.
+ */
+#define CAN_ESR1_BIT1ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
+/*! @} */
+
+/*! @name IMASK1 - Interrupt Masks 1 */
+/*! @{ */
+
+#define CAN_IMASK1_BUF31TO0M_MASK                (0xFFFFFFFFU)
+#define CAN_IMASK1_BUF31TO0M_SHIFT               (0U)
+/*! BUF31TO0M - Buffer MBi Mask */
+#define CAN_IMASK1_BUF31TO0M(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
+/*! @} */
+
+/*! @name IFLAG1 - Interrupt Flags 1 */
+/*! @{ */
+
+#define CAN_IFLAG1_BUF0I_MASK                    (0x1U)
+#define CAN_IFLAG1_BUF0I_SHIFT                   (0U)
+/*! BUF0I - Buffer MB0 Interrupt or Clear Legacy FIFO bit
+ *  0b0..MB0 has no occurrence of successfully completed transmission or reception.
+ *  0b1..MB0 has successfully completed transmission or reception.
+ */
+#define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
+
+#define CAN_IFLAG1_BUF4TO1I_MASK                 (0x1EU)
+#define CAN_IFLAG1_BUF4TO1I_SHIFT                (1U)
+/*! BUF4TO1I - Buffer MBi Interrupt or Reserved */
+#define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
+
+#define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
+#define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
+/*! BUF5I - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO
+ *  0b0..No occurrence of completed transmission or reception, or no frames available
+ *  0b1..MB5 completed transmission or reception, or frames available
+ */
+#define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
+
+#define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
+#define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
+/*! BUF6I - Buffer MB6 Interrupt or Legacy RX FIFO Warning
+ *  0b0..No occurrence of MB6 completing transmission or reception, or FIFO not almost full.
+ *  0b1..MB6 completed transmission or reception, or FIFO almost full.
+ */
+#define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
+
+#define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
+#define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
+/*! BUF7I - Buffer MB7 Interrupt or Legacy RX FIFO Overflow
+ *  0b0..No occurrence of MB7 completing transmission or reception, or no FIFO overflow.
+ *  0b1..MB7 completed transmission or reception, or FIFO overflow.
+ */
+#define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
+
+#define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
+#define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
+/*! BUF31TO8I - Buffer MBi Interrupt */
+#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
+/*! @} */
+
+/*! @name CTRL2 - Control 2 */
+/*! @{ */
+
+#define CAN_CTRL2_PES_MASK                       (0x1U)
+#define CAN_CTRL2_PES_SHIFT                      (0U)
+/*! PES - Payload Byte and Bit Order Selection
+ *  0b0..Big-endian
+ *  0b1..Little-endian
+ */
+#define CAN_CTRL2_PES(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PES_SHIFT)) & CAN_CTRL2_PES_MASK)
+
+#define CAN_CTRL2_ASD_MASK                       (0x2U)
+#define CAN_CTRL2_ASD_SHIFT                      (1U)
+/*! ASD - ACK Suppression Disable
+ *  0b0..Enabled
+ *  0b1..Disabled
+ */
+#define CAN_CTRL2_ASD(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ASD_SHIFT)) & CAN_CTRL2_ASD_MASK)
+
+#define CAN_CTRL2_EDFLTDIS_MASK                  (0x800U)
+#define CAN_CTRL2_EDFLTDIS_SHIFT                 (11U)
+/*! EDFLTDIS - Edge Filter Disable
+ *  0b0..Enabled
+ *  0b1..Disabled
+ */
+#define CAN_CTRL2_EDFLTDIS(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
+
+#define CAN_CTRL2_ISOCANFDEN_MASK                (0x1000U)
+#define CAN_CTRL2_ISOCANFDEN_SHIFT               (12U)
+/*! ISOCANFDEN - ISO CAN FD Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_CTRL2_ISOCANFDEN(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
+
+#define CAN_CTRL2_BTE_MASK                       (0x2000U)
+#define CAN_CTRL2_BTE_SHIFT                      (13U)
+/*! BTE - Bit Timing Expansion Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_CTRL2_BTE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK)
+
+#define CAN_CTRL2_PREXCEN_MASK                   (0x4000U)
+#define CAN_CTRL2_PREXCEN_SHIFT                  (14U)
+/*! PREXCEN - Protocol Exception Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define CAN_CTRL2_PREXCEN(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
+
+#define CAN_CTRL2_EACEN_MASK                     (0x10000U)
+#define CAN_CTRL2_EACEN_SHIFT                    (16U)
+/*! EACEN - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
+
+#define CAN_CTRL2_RRS_MASK                       (0x20000U)
+#define CAN_CTRL2_RRS_SHIFT                      (17U)
+/*! RRS - Remote Request Storing
+ *  0b0..Generated
+ *  0b1..Stored
+ */
+#define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
+
+#define CAN_CTRL2_MRP_MASK                       (0x40000U)
+#define CAN_CTRL2_MRP_SHIFT                      (18U)
+/*! MRP - Message Buffers Reception Priority
+ *  0b0..Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers.
+ *  0b1..Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO.
+ */
+#define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
+
+#define CAN_CTRL2_TASD_MASK                      (0xF80000U)
+#define CAN_CTRL2_TASD_SHIFT                     (19U)
+/*! TASD - Transmission Arbitration Start Delay */
+#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
+
+#define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
+#define CAN_CTRL2_RFFN_SHIFT                     (24U)
+/*! RFFN - Number of Legacy Receive FIFO Filters */
+#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
+
+#define CAN_CTRL2_BOFFDONEMSK_MASK               (0x40000000U)
+#define CAN_CTRL2_BOFFDONEMSK_SHIFT              (30U)
+/*! BOFFDONEMSK - Bus Off Done Interrupt Mask
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_CTRL2_BOFFDONEMSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
+
+#define CAN_CTRL2_ERRMSK_FAST_MASK               (0x80000000U)
+#define CAN_CTRL2_ERRMSK_FAST_SHIFT              (31U)
+/*! ERRMSK_FAST - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_CTRL2_ERRMSK_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
+/*! @} */
+
+/*! @name ESR2 - Error and Status 2 */
+/*! @{ */
+
+#define CAN_ESR2_IMB_MASK                        (0x2000U)
+#define CAN_ESR2_IMB_SHIFT                       (13U)
+/*! IMB - Inactive Message Buffer
+ *  0b0..Message buffer indicated by ESR2[LPTM] is not inactive.
+ *  0b1..At least one message buffer is inactive.
+ */
+#define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
+
+#define CAN_ESR2_VPS_MASK                        (0x4000U)
+#define CAN_ESR2_VPS_SHIFT                       (14U)
+/*! VPS - Valid Priority Status
+ *  0b0..Invalid
+ *  0b1..Valid
+ */
+#define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
+
+#define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
+#define CAN_ESR2_LPTM_SHIFT                      (16U)
+/*! LPTM - Lowest Priority TX Message Buffer */
+#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
+/*! @} */
+
+/*! @name CRCR - Cyclic Redundancy Check */
+/*! @{ */
+
+#define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
+#define CAN_CRCR_TXCRC_SHIFT                     (0U)
+/*! TXCRC - Transmitted CRC value */
+#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
+
+#define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
+#define CAN_CRCR_MBCRC_SHIFT                     (16U)
+/*! MBCRC - CRC Message Buffer */
+#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
+/*! @} */
+
+/*! @name RXFGMASK - Legacy RX FIFO Global Mask */
+/*! @{ */
+
+#define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
+#define CAN_RXFGMASK_FGM_SHIFT                   (0U)
+/*! FGM - Legacy RX FIFO Global Mask Bits */
+#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
+/*! @} */
+
+/*! @name RXFIR - Legacy RX FIFO Information */
+/*! @{ */
+
+#define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
+#define CAN_RXFIR_IDHIT_SHIFT                    (0U)
+/*! IDHIT - Identifier Acceptance Filter Hit Indicator */
+#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
+/*! @} */
+
+/*! @name CBT - CAN Bit Timing */
+/*! @{ */
+
+#define CAN_CBT_EPSEG2_MASK                      (0x1FU)
+#define CAN_CBT_EPSEG2_SHIFT                     (0U)
+/*! EPSEG2 - Extended Phase Segment 2 */
+#define CAN_CBT_EPSEG2(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
+
+#define CAN_CBT_EPSEG1_MASK                      (0x3E0U)
+#define CAN_CBT_EPSEG1_SHIFT                     (5U)
+/*! EPSEG1 - Extended Phase Segment 1 */
+#define CAN_CBT_EPSEG1(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
+
+#define CAN_CBT_EPROPSEG_MASK                    (0xFC00U)
+#define CAN_CBT_EPROPSEG_SHIFT                   (10U)
+/*! EPROPSEG - Extended Propagation Segment */
+#define CAN_CBT_EPROPSEG(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
+
+#define CAN_CBT_ERJW_MASK                        (0x1F0000U)
+#define CAN_CBT_ERJW_SHIFT                       (16U)
+/*! ERJW - Extended Resync Jump Width */
+#define CAN_CBT_ERJW(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
+
+#define CAN_CBT_EPRESDIV_MASK                    (0x7FE00000U)
+#define CAN_CBT_EPRESDIV_SHIFT                   (21U)
+/*! EPRESDIV - Extended Prescaler Division Factor */
+#define CAN_CBT_EPRESDIV(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
+
+#define CAN_CBT_BTF_MASK                         (0x80000000U)
+#define CAN_CBT_BTF_SHIFT                        (31U)
+/*! BTF - Bit Timing Format Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_CBT_BTF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
+/*! @} */
+
+/* The count of CAN_CS */
+#define CAN_CS_COUNT_MB8B                        (32U)
+
+/* The count of CAN_ID */
+#define CAN_ID_COUNT_MB8B                        (32U)
+
+/* The count of CAN_WORD */
+#define CAN_WORD_COUNT_MB8B                      (32U)
+
+/* The count of CAN_WORD */
+#define CAN_WORD_COUNT_MB8B2                     (2U)
+
+/* The count of CAN_CS */
+#define CAN_CS_COUNT_MB16B                       (21U)
+
+/* The count of CAN_ID */
+#define CAN_ID_COUNT_MB16B                       (21U)
+
+/* The count of CAN_WORD */
+#define CAN_WORD_COUNT_MB16B                     (21U)
+
+/* The count of CAN_WORD */
+#define CAN_WORD_COUNT_MB16B2                    (4U)
+
+/* The count of CAN_CS */
+#define CAN_CS_COUNT_MB32B                       (12U)
+
+/* The count of CAN_ID */
+#define CAN_ID_COUNT_MB32B                       (12U)
+
+/* The count of CAN_WORD */
+#define CAN_WORD_COUNT_MB32B                     (12U)
+
+/* The count of CAN_WORD */
+#define CAN_WORD_COUNT_MB32B2                    (8U)
+
+/*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */
+/*! @{ */
+
+#define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
+#define CAN_CS_TIME_STAMP_SHIFT                  (0U)
+/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
+ *    Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
+ *    appears on the CAN bus.
+ */
+#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
+
+#define CAN_CS_DLC_MASK                          (0xF0000U)
+#define CAN_CS_DLC_SHIFT                         (16U)
+/*! DLC - Length of the data to be stored/transmitted. */
+#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
+
+#define CAN_CS_RTR_MASK                          (0x100000U)
+#define CAN_CS_RTR_SHIFT                         (20U)
+/*! RTR - Remote Transmission Request. One/zero for remote/data frame. */
+#define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
+
+#define CAN_CS_IDE_MASK                          (0x200000U)
+#define CAN_CS_IDE_SHIFT                         (21U)
+/*! IDE - ID Extended. One/zero for extended/standard format frame. */
+#define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
+
+#define CAN_CS_SRR_MASK                          (0x400000U)
+#define CAN_CS_SRR_SHIFT                         (22U)
+/*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */
+#define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
+
+#define CAN_CS_CODE_MASK                         (0xF000000U)
+#define CAN_CS_CODE_SHIFT                        (24U)
+/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
+ *    the FlexCAN module itself, as part of the message buffer matching and arbitration process.
+ */
+#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
+
+#define CAN_CS_ESI_MASK                          (0x20000000U)
+#define CAN_CS_ESI_SHIFT                         (29U)
+/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */
+#define CAN_CS_ESI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
+
+#define CAN_CS_BRS_MASK                          (0x40000000U)
+#define CAN_CS_BRS_SHIFT                         (30U)
+/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */
+#define CAN_CS_BRS(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
+
+#define CAN_CS_EDL_MASK                          (0x80000000U)
+#define CAN_CS_EDL_SHIFT                         (31U)
+/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
+ *    The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
+ */
+#define CAN_CS_EDL(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
+/*! @} */
+
+/* The count of CAN_CS */
+#define CAN_CS_COUNT_MB64B                       (7U)
+
+/*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */
+/*! @{ */
+
+#define CAN_ID_EXT_MASK                          (0x3FFFFU)
+#define CAN_ID_EXT_SHIFT                         (0U)
+/*! EXT - Contains extended (LOW word) identifier of message buffer. */
+#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
+
+#define CAN_ID_STD_MASK                          (0x1FFC0000U)
+#define CAN_ID_STD_SHIFT                         (18U)
+/*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */
+#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
+
+#define CAN_ID_PRIO_MASK                         (0xE0000000U)
+#define CAN_ID_PRIO_SHIFT                        (29U)
+/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
+ *    makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
+ *    ID to define the transmission priority.
+ */
+#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
+/*! @} */
+
+/* The count of CAN_ID */
+#define CAN_ID_COUNT_MB64B                       (7U)
+
+/*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */
+/*! @{ */
+
+#define CAN_WORD_DATA_BYTE_3_MASK                (0xFFU)
+#define CAN_WORD_DATA_BYTE_3_SHIFT               (0U)
+/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_3(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
+
+#define CAN_WORD_DATA_BYTE_7_MASK                (0xFFU)
+#define CAN_WORD_DATA_BYTE_7_SHIFT               (0U)
+/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_7(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
+
+#define CAN_WORD_DATA_BYTE_11_MASK               (0xFFU)
+#define CAN_WORD_DATA_BYTE_11_SHIFT              (0U)
+/*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_11(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
+
+#define CAN_WORD_DATA_BYTE_15_MASK               (0xFFU)
+#define CAN_WORD_DATA_BYTE_15_SHIFT              (0U)
+/*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_15(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
+
+#define CAN_WORD_DATA_BYTE_19_MASK               (0xFFU)
+#define CAN_WORD_DATA_BYTE_19_SHIFT              (0U)
+/*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_19(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
+
+#define CAN_WORD_DATA_BYTE_23_MASK               (0xFFU)
+#define CAN_WORD_DATA_BYTE_23_SHIFT              (0U)
+/*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_23(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
+
+#define CAN_WORD_DATA_BYTE_27_MASK               (0xFFU)
+#define CAN_WORD_DATA_BYTE_27_SHIFT              (0U)
+/*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_27(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
+
+#define CAN_WORD_DATA_BYTE_31_MASK               (0xFFU)
+#define CAN_WORD_DATA_BYTE_31_SHIFT              (0U)
+/*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_31(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
+
+#define CAN_WORD_DATA_BYTE_35_MASK               (0xFFU)
+#define CAN_WORD_DATA_BYTE_35_SHIFT              (0U)
+/*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_35(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
+
+#define CAN_WORD_DATA_BYTE_39_MASK               (0xFFU)
+#define CAN_WORD_DATA_BYTE_39_SHIFT              (0U)
+/*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_39(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
+
+#define CAN_WORD_DATA_BYTE_43_MASK               (0xFFU)
+#define CAN_WORD_DATA_BYTE_43_SHIFT              (0U)
+/*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_43(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
+
+#define CAN_WORD_DATA_BYTE_47_MASK               (0xFFU)
+#define CAN_WORD_DATA_BYTE_47_SHIFT              (0U)
+/*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_47(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
+
+#define CAN_WORD_DATA_BYTE_51_MASK               (0xFFU)
+#define CAN_WORD_DATA_BYTE_51_SHIFT              (0U)
+/*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_51(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
+
+#define CAN_WORD_DATA_BYTE_55_MASK               (0xFFU)
+#define CAN_WORD_DATA_BYTE_55_SHIFT              (0U)
+/*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_55(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
+
+#define CAN_WORD_DATA_BYTE_59_MASK               (0xFFU)
+#define CAN_WORD_DATA_BYTE_59_SHIFT              (0U)
+/*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_59(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
+
+#define CAN_WORD_DATA_BYTE_63_MASK               (0xFFU)
+#define CAN_WORD_DATA_BYTE_63_SHIFT              (0U)
+/*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_63(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
+
+#define CAN_WORD_DATA_BYTE_2_MASK                (0xFF00U)
+#define CAN_WORD_DATA_BYTE_2_SHIFT               (8U)
+/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_2(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
+
+#define CAN_WORD_DATA_BYTE_6_MASK                (0xFF00U)
+#define CAN_WORD_DATA_BYTE_6_SHIFT               (8U)
+/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_6(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
+
+#define CAN_WORD_DATA_BYTE_10_MASK               (0xFF00U)
+#define CAN_WORD_DATA_BYTE_10_SHIFT              (8U)
+/*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_10(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
+
+#define CAN_WORD_DATA_BYTE_14_MASK               (0xFF00U)
+#define CAN_WORD_DATA_BYTE_14_SHIFT              (8U)
+/*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_14(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
+
+#define CAN_WORD_DATA_BYTE_18_MASK               (0xFF00U)
+#define CAN_WORD_DATA_BYTE_18_SHIFT              (8U)
+/*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_18(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
+
+#define CAN_WORD_DATA_BYTE_22_MASK               (0xFF00U)
+#define CAN_WORD_DATA_BYTE_22_SHIFT              (8U)
+/*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_22(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
+
+#define CAN_WORD_DATA_BYTE_26_MASK               (0xFF00U)
+#define CAN_WORD_DATA_BYTE_26_SHIFT              (8U)
+/*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_26(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
+
+#define CAN_WORD_DATA_BYTE_30_MASK               (0xFF00U)
+#define CAN_WORD_DATA_BYTE_30_SHIFT              (8U)
+/*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_30(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
+
+#define CAN_WORD_DATA_BYTE_34_MASK               (0xFF00U)
+#define CAN_WORD_DATA_BYTE_34_SHIFT              (8U)
+/*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_34(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
+
+#define CAN_WORD_DATA_BYTE_38_MASK               (0xFF00U)
+#define CAN_WORD_DATA_BYTE_38_SHIFT              (8U)
+/*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_38(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
+
+#define CAN_WORD_DATA_BYTE_42_MASK               (0xFF00U)
+#define CAN_WORD_DATA_BYTE_42_SHIFT              (8U)
+/*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_42(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
+
+#define CAN_WORD_DATA_BYTE_46_MASK               (0xFF00U)
+#define CAN_WORD_DATA_BYTE_46_SHIFT              (8U)
+/*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_46(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
+
+#define CAN_WORD_DATA_BYTE_50_MASK               (0xFF00U)
+#define CAN_WORD_DATA_BYTE_50_SHIFT              (8U)
+/*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_50(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
+
+#define CAN_WORD_DATA_BYTE_54_MASK               (0xFF00U)
+#define CAN_WORD_DATA_BYTE_54_SHIFT              (8U)
+/*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_54(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
+
+#define CAN_WORD_DATA_BYTE_58_MASK               (0xFF00U)
+#define CAN_WORD_DATA_BYTE_58_SHIFT              (8U)
+/*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_58(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
+
+#define CAN_WORD_DATA_BYTE_62_MASK               (0xFF00U)
+#define CAN_WORD_DATA_BYTE_62_SHIFT              (8U)
+/*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_62(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
+
+#define CAN_WORD_DATA_BYTE_1_MASK                (0xFF0000U)
+#define CAN_WORD_DATA_BYTE_1_SHIFT               (16U)
+/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_1(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
+
+#define CAN_WORD_DATA_BYTE_5_MASK                (0xFF0000U)
+#define CAN_WORD_DATA_BYTE_5_SHIFT               (16U)
+/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_5(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
+
+#define CAN_WORD_DATA_BYTE_9_MASK                (0xFF0000U)
+#define CAN_WORD_DATA_BYTE_9_SHIFT               (16U)
+/*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_9(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
+
+#define CAN_WORD_DATA_BYTE_13_MASK               (0xFF0000U)
+#define CAN_WORD_DATA_BYTE_13_SHIFT              (16U)
+/*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_13(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
+
+#define CAN_WORD_DATA_BYTE_17_MASK               (0xFF0000U)
+#define CAN_WORD_DATA_BYTE_17_SHIFT              (16U)
+/*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_17(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
+
+#define CAN_WORD_DATA_BYTE_21_MASK               (0xFF0000U)
+#define CAN_WORD_DATA_BYTE_21_SHIFT              (16U)
+/*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_21(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
+
+#define CAN_WORD_DATA_BYTE_25_MASK               (0xFF0000U)
+#define CAN_WORD_DATA_BYTE_25_SHIFT              (16U)
+/*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_25(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
+
+#define CAN_WORD_DATA_BYTE_29_MASK               (0xFF0000U)
+#define CAN_WORD_DATA_BYTE_29_SHIFT              (16U)
+/*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_29(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
+
+#define CAN_WORD_DATA_BYTE_33_MASK               (0xFF0000U)
+#define CAN_WORD_DATA_BYTE_33_SHIFT              (16U)
+/*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_33(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
+
+#define CAN_WORD_DATA_BYTE_37_MASK               (0xFF0000U)
+#define CAN_WORD_DATA_BYTE_37_SHIFT              (16U)
+/*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_37(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
+
+#define CAN_WORD_DATA_BYTE_41_MASK               (0xFF0000U)
+#define CAN_WORD_DATA_BYTE_41_SHIFT              (16U)
+/*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_41(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
+
+#define CAN_WORD_DATA_BYTE_45_MASK               (0xFF0000U)
+#define CAN_WORD_DATA_BYTE_45_SHIFT              (16U)
+/*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_45(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
+
+#define CAN_WORD_DATA_BYTE_49_MASK               (0xFF0000U)
+#define CAN_WORD_DATA_BYTE_49_SHIFT              (16U)
+/*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_49(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
+
+#define CAN_WORD_DATA_BYTE_53_MASK               (0xFF0000U)
+#define CAN_WORD_DATA_BYTE_53_SHIFT              (16U)
+/*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_53(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
+
+#define CAN_WORD_DATA_BYTE_57_MASK               (0xFF0000U)
+#define CAN_WORD_DATA_BYTE_57_SHIFT              (16U)
+/*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_57(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
+
+#define CAN_WORD_DATA_BYTE_61_MASK               (0xFF0000U)
+#define CAN_WORD_DATA_BYTE_61_SHIFT              (16U)
+/*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_61(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
+
+#define CAN_WORD_DATA_BYTE_0_MASK                (0xFF000000U)
+#define CAN_WORD_DATA_BYTE_0_SHIFT               (24U)
+/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_0(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
+
+#define CAN_WORD_DATA_BYTE_4_MASK                (0xFF000000U)
+#define CAN_WORD_DATA_BYTE_4_SHIFT               (24U)
+/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_4(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
+
+#define CAN_WORD_DATA_BYTE_8_MASK                (0xFF000000U)
+#define CAN_WORD_DATA_BYTE_8_SHIFT               (24U)
+/*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_8(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
+
+#define CAN_WORD_DATA_BYTE_12_MASK               (0xFF000000U)
+#define CAN_WORD_DATA_BYTE_12_SHIFT              (24U)
+/*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_12(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
+
+#define CAN_WORD_DATA_BYTE_16_MASK               (0xFF000000U)
+#define CAN_WORD_DATA_BYTE_16_SHIFT              (24U)
+/*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_16(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
+
+#define CAN_WORD_DATA_BYTE_20_MASK               (0xFF000000U)
+#define CAN_WORD_DATA_BYTE_20_SHIFT              (24U)
+/*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_20(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
+
+#define CAN_WORD_DATA_BYTE_24_MASK               (0xFF000000U)
+#define CAN_WORD_DATA_BYTE_24_SHIFT              (24U)
+/*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_24(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
+
+#define CAN_WORD_DATA_BYTE_28_MASK               (0xFF000000U)
+#define CAN_WORD_DATA_BYTE_28_SHIFT              (24U)
+/*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_28(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
+
+#define CAN_WORD_DATA_BYTE_32_MASK               (0xFF000000U)
+#define CAN_WORD_DATA_BYTE_32_SHIFT              (24U)
+/*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_32(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
+
+#define CAN_WORD_DATA_BYTE_36_MASK               (0xFF000000U)
+#define CAN_WORD_DATA_BYTE_36_SHIFT              (24U)
+/*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_36(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
+
+#define CAN_WORD_DATA_BYTE_40_MASK               (0xFF000000U)
+#define CAN_WORD_DATA_BYTE_40_SHIFT              (24U)
+/*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_40(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
+
+#define CAN_WORD_DATA_BYTE_44_MASK               (0xFF000000U)
+#define CAN_WORD_DATA_BYTE_44_SHIFT              (24U)
+/*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_44(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
+
+#define CAN_WORD_DATA_BYTE_48_MASK               (0xFF000000U)
+#define CAN_WORD_DATA_BYTE_48_SHIFT              (24U)
+/*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_48(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
+
+#define CAN_WORD_DATA_BYTE_52_MASK               (0xFF000000U)
+#define CAN_WORD_DATA_BYTE_52_SHIFT              (24U)
+/*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_52(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
+
+#define CAN_WORD_DATA_BYTE_56_MASK               (0xFF000000U)
+#define CAN_WORD_DATA_BYTE_56_SHIFT              (24U)
+/*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_56(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
+
+#define CAN_WORD_DATA_BYTE_60_MASK               (0xFF000000U)
+#define CAN_WORD_DATA_BYTE_60_SHIFT              (24U)
+/*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD_DATA_BYTE_60(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
+/*! @} */
+
+/* The count of CAN_WORD */
+#define CAN_WORD_COUNT_MB64B                     (7U)
+
+/* The count of CAN_WORD */
+#define CAN_WORD_COUNT_MB64B2                    (16U)
+
+/* The count of CAN_CS */
+#define CAN_CS_COUNT                             (32U)
+
+/* The count of CAN_ID */
+#define CAN_ID_COUNT                             (32U)
+
+/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register */
+/*! @{ */
+
+#define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
+#define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
+/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
+
+#define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
+#define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
+/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
+
+#define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
+#define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
+/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
+
+#define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
+#define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
+/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
+/*! @} */
+
+/* The count of CAN_WORD0 */
+#define CAN_WORD0_COUNT                          (32U)
+
+/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register */
+/*! @{ */
+
+#define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
+#define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
+/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */
+#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
+
+#define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
+#define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
+/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */
+#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
+
+#define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
+#define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
+/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */
+#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
+
+#define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
+#define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
+/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */
+#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
+/*! @} */
+
+/* The count of CAN_WORD1 */
+#define CAN_WORD1_COUNT                          (32U)
+
+/*! @name RXIMR - Receive Individual Mask */
+/*! @{ */
+
+#define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
+#define CAN_RXIMR_MI_SHIFT                       (0U)
+/*! MI - Individual Mask Bits */
+#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
+/*! @} */
+
+/*! @name CTRL1_PN - Pretended Networking Control 1 */
+/*! @{ */
+
+#define CAN_CTRL1_PN_FCS_MASK                    (0x3U)
+#define CAN_CTRL1_PN_FCS_SHIFT                   (0U)
+/*! FCS - Filtering Combination Selection
+ *  0b00..Message ID filtering only
+ *  0b01..Message ID filtering and payload filtering
+ *  0b10..Message ID filtering occurring a specified number of times
+ *  0b11..Message ID filtering and payload filtering a specified number of times
+ */
+#define CAN_CTRL1_PN_FCS(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_FCS_SHIFT)) & CAN_CTRL1_PN_FCS_MASK)
+
+#define CAN_CTRL1_PN_IDFS_MASK                   (0xCU)
+#define CAN_CTRL1_PN_IDFS_SHIFT                  (2U)
+/*! IDFS - ID Filtering Selection
+ *  0b00..Match ID contents to an exact target value
+ *  0b01..Match an ID value greater than or equal to a specified target value
+ *  0b10..Match an ID value smaller than or equal to a specified target value
+ *  0b11..Match an ID value within a range of values, inclusive
+ */
+#define CAN_CTRL1_PN_IDFS(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_IDFS_SHIFT)) & CAN_CTRL1_PN_IDFS_MASK)
+
+#define CAN_CTRL1_PN_PLFS_MASK                   (0x30U)
+#define CAN_CTRL1_PN_PLFS_SHIFT                  (4U)
+/*! PLFS - Payload Filtering Selection
+ *  0b00..Match payload contents to an exact target value
+ *  0b01..Match a payload value greater than or equal to a specified target value
+ *  0b10..Match a payload value smaller than or equal to a specified target value
+ *  0b11..Match upon a payload value within a range of values, inclusive
+ */
+#define CAN_CTRL1_PN_PLFS(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_PLFS_SHIFT)) & CAN_CTRL1_PN_PLFS_MASK)
+
+#define CAN_CTRL1_PN_NMATCH_MASK                 (0xFF00U)
+#define CAN_CTRL1_PN_NMATCH_SHIFT                (8U)
+/*! NMATCH - Number of Messages Matching the Same Filtering Criteria
+ *  0b00000001..Once
+ *  0b00000010..Twice
+ *  0b11111111..255 times
+ */
+#define CAN_CTRL1_PN_NMATCH(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_NMATCH_SHIFT)) & CAN_CTRL1_PN_NMATCH_MASK)
+
+#define CAN_CTRL1_PN_WUMF_MSK_MASK               (0x10000U)
+#define CAN_CTRL1_PN_WUMF_MSK_SHIFT              (16U)
+/*! WUMF_MSK - Wake-up by Matching Flag Mask
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_CTRL1_PN_WUMF_MSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WUMF_MSK_SHIFT)) & CAN_CTRL1_PN_WUMF_MSK_MASK)
+
+#define CAN_CTRL1_PN_WTOF_MSK_MASK               (0x20000U)
+#define CAN_CTRL1_PN_WTOF_MSK_SHIFT              (17U)
+/*! WTOF_MSK - Wake-up by Timeout Flag Mask
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_CTRL1_PN_WTOF_MSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WTOF_MSK_SHIFT)) & CAN_CTRL1_PN_WTOF_MSK_MASK)
+/*! @} */
+
+/*! @name CTRL2_PN - Pretended Networking Control 2 */
+/*! @{ */
+
+#define CAN_CTRL2_PN_MATCHTO_MASK                (0xFFFFU)
+#define CAN_CTRL2_PN_MATCHTO_SHIFT               (0U)
+/*! MATCHTO - Timeout for No Message Matching the Filtering Criteria */
+#define CAN_CTRL2_PN_MATCHTO(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PN_MATCHTO_SHIFT)) & CAN_CTRL2_PN_MATCHTO_MASK)
+/*! @} */
+
+/*! @name WU_MTC - Pretended Networking Wake-Up Match */
+/*! @{ */
+
+#define CAN_WU_MTC_MCOUNTER_MASK                 (0xFF00U)
+#define CAN_WU_MTC_MCOUNTER_SHIFT                (8U)
+/*! MCOUNTER - Number of Matches in Pretended Networking */
+#define CAN_WU_MTC_MCOUNTER(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_MCOUNTER_SHIFT)) & CAN_WU_MTC_MCOUNTER_MASK)
+
+#define CAN_WU_MTC_WUMF_MASK                     (0x10000U)
+#define CAN_WU_MTC_WUMF_SHIFT                    (16U)
+/*! WUMF - Wake-up by Match Flag
+ *  0b0..No event detected
+ *  0b1..Event detected
+ */
+#define CAN_WU_MTC_WUMF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WUMF_SHIFT)) & CAN_WU_MTC_WUMF_MASK)
+
+#define CAN_WU_MTC_WTOF_MASK                     (0x20000U)
+#define CAN_WU_MTC_WTOF_SHIFT                    (17U)
+/*! WTOF - Wake-up by Timeout Flag Bit
+ *  0b0..No event detected
+ *  0b1..Event detected
+ */
+#define CAN_WU_MTC_WTOF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WTOF_SHIFT)) & CAN_WU_MTC_WTOF_MASK)
+/*! @} */
+
+/*! @name FLT_ID1 - Pretended Networking ID Filter 1 */
+/*! @{ */
+
+#define CAN_FLT_ID1_FLT_ID1_MASK                 (0x1FFFFFFFU)
+#define CAN_FLT_ID1_FLT_ID1_SHIFT                (0U)
+/*! FLT_ID1 - ID Filter 1 for Pretended Networking filtering */
+#define CAN_FLT_ID1_FLT_ID1(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_ID1_SHIFT)) & CAN_FLT_ID1_FLT_ID1_MASK)
+
+#define CAN_FLT_ID1_FLT_RTR_MASK                 (0x20000000U)
+#define CAN_FLT_ID1_FLT_RTR_SHIFT                (29U)
+/*! FLT_RTR - Remote Transmission Request Filter
+ *  0b0..Reject remote frame (accept data frame)
+ *  0b1..Accept remote frame
+ */
+#define CAN_FLT_ID1_FLT_RTR(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_RTR_SHIFT)) & CAN_FLT_ID1_FLT_RTR_MASK)
+
+#define CAN_FLT_ID1_FLT_IDE_MASK                 (0x40000000U)
+#define CAN_FLT_ID1_FLT_IDE_SHIFT                (30U)
+/*! FLT_IDE - ID Extended Filter
+ *  0b0..Standard
+ *  0b1..Extended
+ */
+#define CAN_FLT_ID1_FLT_IDE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_IDE_SHIFT)) & CAN_FLT_ID1_FLT_IDE_MASK)
+/*! @} */
+
+/*! @name FLT_DLC - Pretended Networking Data Length Code (DLC) Filter */
+/*! @{ */
+
+#define CAN_FLT_DLC_FLT_DLC_HI_MASK              (0xFU)
+#define CAN_FLT_DLC_FLT_DLC_HI_SHIFT             (0U)
+/*! FLT_DLC_HI - Upper Limit for Length of Data Bytes Filter */
+#define CAN_FLT_DLC_FLT_DLC_HI(x)                (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_HI_SHIFT)) & CAN_FLT_DLC_FLT_DLC_HI_MASK)
+
+#define CAN_FLT_DLC_FLT_DLC_LO_MASK              (0xF0000U)
+#define CAN_FLT_DLC_FLT_DLC_LO_SHIFT             (16U)
+/*! FLT_DLC_LO - Lower Limit for Length of Data Bytes Filter */
+#define CAN_FLT_DLC_FLT_DLC_LO(x)                (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_LO_SHIFT)) & CAN_FLT_DLC_FLT_DLC_LO_MASK)
+/*! @} */
+
+/*! @name PL1_LO - Pretended Networking Payload Low Filter 1 */
+/*! @{ */
+
+#define CAN_PL1_LO_Data_byte_3_MASK              (0xFFU)
+#define CAN_PL1_LO_Data_byte_3_SHIFT             (0U)
+/*! Data_byte_3 - Data byte 3 */
+#define CAN_PL1_LO_Data_byte_3(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_3_SHIFT)) & CAN_PL1_LO_Data_byte_3_MASK)
+
+#define CAN_PL1_LO_Data_byte_2_MASK              (0xFF00U)
+#define CAN_PL1_LO_Data_byte_2_SHIFT             (8U)
+/*! Data_byte_2 - Data byte 2 */
+#define CAN_PL1_LO_Data_byte_2(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_2_SHIFT)) & CAN_PL1_LO_Data_byte_2_MASK)
+
+#define CAN_PL1_LO_Data_byte_1_MASK              (0xFF0000U)
+#define CAN_PL1_LO_Data_byte_1_SHIFT             (16U)
+/*! Data_byte_1 - Data byte 1 */
+#define CAN_PL1_LO_Data_byte_1(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_1_SHIFT)) & CAN_PL1_LO_Data_byte_1_MASK)
+
+#define CAN_PL1_LO_Data_byte_0_MASK              (0xFF000000U)
+#define CAN_PL1_LO_Data_byte_0_SHIFT             (24U)
+/*! Data_byte_0 - Data byte 0 */
+#define CAN_PL1_LO_Data_byte_0(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_0_SHIFT)) & CAN_PL1_LO_Data_byte_0_MASK)
+/*! @} */
+
+/*! @name PL1_HI - Pretended Networking Payload High Filter 1 */
+/*! @{ */
+
+#define CAN_PL1_HI_Data_byte_7_MASK              (0xFFU)
+#define CAN_PL1_HI_Data_byte_7_SHIFT             (0U)
+/*! Data_byte_7 - Data byte 7 */
+#define CAN_PL1_HI_Data_byte_7(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_7_SHIFT)) & CAN_PL1_HI_Data_byte_7_MASK)
+
+#define CAN_PL1_HI_Data_byte_6_MASK              (0xFF00U)
+#define CAN_PL1_HI_Data_byte_6_SHIFT             (8U)
+/*! Data_byte_6 - Data byte 6 */
+#define CAN_PL1_HI_Data_byte_6(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_6_SHIFT)) & CAN_PL1_HI_Data_byte_6_MASK)
+
+#define CAN_PL1_HI_Data_byte_5_MASK              (0xFF0000U)
+#define CAN_PL1_HI_Data_byte_5_SHIFT             (16U)
+/*! Data_byte_5 - Data byte 5 */
+#define CAN_PL1_HI_Data_byte_5(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_5_SHIFT)) & CAN_PL1_HI_Data_byte_5_MASK)
+
+#define CAN_PL1_HI_Data_byte_4_MASK              (0xFF000000U)
+#define CAN_PL1_HI_Data_byte_4_SHIFT             (24U)
+/*! Data_byte_4 - Data byte 4 */
+#define CAN_PL1_HI_Data_byte_4(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_4_SHIFT)) & CAN_PL1_HI_Data_byte_4_MASK)
+/*! @} */
+
+/*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 or ID Mask */
+/*! @{ */
+
+#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK   (0x1FFFFFFFU)
+#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT  (0U)
+/*! FLT_ID2_IDMASK - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering */
+#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x)     (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT)) & CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK)
+
+#define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK          (0x20000000U)
+#define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT         (29U)
+/*! RTR_MSK - Remote Transmission Request Mask
+ *  0b0..The corresponding bit in the filter is "don't care."
+ *  0b1..The corresponding bit in the filter is checked.
+ */
+#define CAN_FLT_ID2_IDMASK_RTR_MSK(x)            (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_RTR_MSK_MASK)
+
+#define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK          (0x40000000U)
+#define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT         (30U)
+/*! IDE_MSK - ID Extended Mask
+ *  0b0..The corresponding bit in the filter is "don't care."
+ *  0b1..The corresponding bit in the filter is checked.
+ */
+#define CAN_FLT_ID2_IDMASK_IDE_MSK(x)            (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_IDE_MSK_MASK)
+/*! @} */
+
+/*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 and Payload Low Mask */
+/*! @{ */
+
+#define CAN_PL2_PLMASK_LO_Data_byte_3_MASK       (0xFFU)
+#define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT      (0U)
+/*! Data_byte_3 - Data Byte 3 */
+#define CAN_PL2_PLMASK_LO_Data_byte_3(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_3_MASK)
+
+#define CAN_PL2_PLMASK_LO_Data_byte_2_MASK       (0xFF00U)
+#define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT      (8U)
+/*! Data_byte_2 - Data Byte 2 */
+#define CAN_PL2_PLMASK_LO_Data_byte_2(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_2_MASK)
+
+#define CAN_PL2_PLMASK_LO_Data_byte_1_MASK       (0xFF0000U)
+#define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT      (16U)
+/*! Data_byte_1 - Data Byte 1 */
+#define CAN_PL2_PLMASK_LO_Data_byte_1(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_1_MASK)
+
+#define CAN_PL2_PLMASK_LO_Data_byte_0_MASK       (0xFF000000U)
+#define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT      (24U)
+/*! Data_byte_0 - Data Byte 0 */
+#define CAN_PL2_PLMASK_LO_Data_byte_0(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_0_MASK)
+/*! @} */
+
+/*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 and Payload High Mask */
+/*! @{ */
+
+#define CAN_PL2_PLMASK_HI_Data_byte_7_MASK       (0xFFU)
+#define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT      (0U)
+/*! Data_byte_7 - Data Byte 7 */
+#define CAN_PL2_PLMASK_HI_Data_byte_7(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_7_MASK)
+
+#define CAN_PL2_PLMASK_HI_Data_byte_6_MASK       (0xFF00U)
+#define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT      (8U)
+/*! Data_byte_6 - Data Byte 6 */
+#define CAN_PL2_PLMASK_HI_Data_byte_6(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_6_MASK)
+
+#define CAN_PL2_PLMASK_HI_Data_byte_5_MASK       (0xFF0000U)
+#define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT      (16U)
+/*! Data_byte_5 - Data Byte 5 */
+#define CAN_PL2_PLMASK_HI_Data_byte_5(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_5_MASK)
+
+#define CAN_PL2_PLMASK_HI_Data_byte_4_MASK       (0xFF000000U)
+#define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT      (24U)
+/*! Data_byte_4 - Data Byte 4 */
+#define CAN_PL2_PLMASK_HI_Data_byte_4(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_4_MASK)
+/*! @} */
+
+/*! @name WMB_CS - Wake-Up Message Buffer */
+/*! @{ */
+
+#define CAN_WMB_CS_DLC_MASK                      (0xF0000U)
+#define CAN_WMB_CS_DLC_SHIFT                     (16U)
+/*! DLC - Length of Data in Bytes */
+#define CAN_WMB_CS_DLC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_DLC_SHIFT)) & CAN_WMB_CS_DLC_MASK)
+
+#define CAN_WMB_CS_RTR_MASK                      (0x100000U)
+#define CAN_WMB_CS_RTR_SHIFT                     (20U)
+/*! RTR - Remote Transmission Request
+ *  0b0..Data
+ *  0b1..Remote
+ */
+#define CAN_WMB_CS_RTR(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_RTR_SHIFT)) & CAN_WMB_CS_RTR_MASK)
+
+#define CAN_WMB_CS_IDE_MASK                      (0x200000U)
+#define CAN_WMB_CS_IDE_SHIFT                     (21U)
+/*! IDE - ID Extended Bit
+ *  0b0..Standard
+ *  0b1..Extended
+ */
+#define CAN_WMB_CS_IDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_IDE_SHIFT)) & CAN_WMB_CS_IDE_MASK)
+
+#define CAN_WMB_CS_SRR_MASK                      (0x400000U)
+#define CAN_WMB_CS_SRR_SHIFT                     (22U)
+/*! SRR - Substitute Remote Request
+ *  0b0..Dominant
+ *  0b1..Recessive
+ */
+#define CAN_WMB_CS_SRR(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_SRR_SHIFT)) & CAN_WMB_CS_SRR_MASK)
+/*! @} */
+
+/* The count of CAN_WMB_CS */
+#define CAN_WMB_CS_COUNT                         (4U)
+
+/*! @name WMB_ID - Wake-Up Message Buffer for ID */
+/*! @{ */
+
+#define CAN_WMB_ID_ID_MASK                       (0x1FFFFFFFU)
+#define CAN_WMB_ID_ID_SHIFT                      (0U)
+/*! ID - Received ID in Pretended Networking Mode */
+#define CAN_WMB_ID_ID(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_WMB_ID_ID_SHIFT)) & CAN_WMB_ID_ID_MASK)
+/*! @} */
+
+/* The count of CAN_WMB_ID */
+#define CAN_WMB_ID_COUNT                         (4U)
+
+/*! @name WMB_D03 - Wake-Up Message Buffer for Data 0-3 */
+/*! @{ */
+
+#define CAN_WMB_D03_Data_byte_3_MASK             (0xFFU)
+#define CAN_WMB_D03_Data_byte_3_SHIFT            (0U)
+/*! Data_byte_3 - Data Byte 3 */
+#define CAN_WMB_D03_Data_byte_3(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_3_SHIFT)) & CAN_WMB_D03_Data_byte_3_MASK)
+
+#define CAN_WMB_D03_Data_byte_2_MASK             (0xFF00U)
+#define CAN_WMB_D03_Data_byte_2_SHIFT            (8U)
+/*! Data_byte_2 - Data Byte 2 */
+#define CAN_WMB_D03_Data_byte_2(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_2_SHIFT)) & CAN_WMB_D03_Data_byte_2_MASK)
+
+#define CAN_WMB_D03_Data_byte_1_MASK             (0xFF0000U)
+#define CAN_WMB_D03_Data_byte_1_SHIFT            (16U)
+/*! Data_byte_1 - Data Byte 1 */
+#define CAN_WMB_D03_Data_byte_1(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_1_SHIFT)) & CAN_WMB_D03_Data_byte_1_MASK)
+
+#define CAN_WMB_D03_Data_byte_0_MASK             (0xFF000000U)
+#define CAN_WMB_D03_Data_byte_0_SHIFT            (24U)
+/*! Data_byte_0 - Data Byte 0 */
+#define CAN_WMB_D03_Data_byte_0(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_0_SHIFT)) & CAN_WMB_D03_Data_byte_0_MASK)
+/*! @} */
+
+/* The count of CAN_WMB_D03 */
+#define CAN_WMB_D03_COUNT                        (4U)
+
+/*! @name WMB_D47 - Wake-Up Message Buffer Register Data 4-7 */
+/*! @{ */
+
+#define CAN_WMB_D47_Data_byte_7_MASK             (0xFFU)
+#define CAN_WMB_D47_Data_byte_7_SHIFT            (0U)
+/*! Data_byte_7 - Data Byte 7 */
+#define CAN_WMB_D47_Data_byte_7(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_7_SHIFT)) & CAN_WMB_D47_Data_byte_7_MASK)
+
+#define CAN_WMB_D47_Data_byte_6_MASK             (0xFF00U)
+#define CAN_WMB_D47_Data_byte_6_SHIFT            (8U)
+/*! Data_byte_6 - Data Byte 6 */
+#define CAN_WMB_D47_Data_byte_6(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_6_SHIFT)) & CAN_WMB_D47_Data_byte_6_MASK)
+
+#define CAN_WMB_D47_Data_byte_5_MASK             (0xFF0000U)
+#define CAN_WMB_D47_Data_byte_5_SHIFT            (16U)
+/*! Data_byte_5 - Data Byte 5 */
+#define CAN_WMB_D47_Data_byte_5(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_5_SHIFT)) & CAN_WMB_D47_Data_byte_5_MASK)
+
+#define CAN_WMB_D47_Data_byte_4_MASK             (0xFF000000U)
+#define CAN_WMB_D47_Data_byte_4_SHIFT            (24U)
+/*! Data_byte_4 - Data Byte 4 */
+#define CAN_WMB_D47_Data_byte_4(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_4_SHIFT)) & CAN_WMB_D47_Data_byte_4_MASK)
+/*! @} */
+
+/* The count of CAN_WMB_D47 */
+#define CAN_WMB_D47_COUNT                        (4U)
+
+/*! @name EPRS - Enhanced CAN Bit Timing Prescalers */
+/*! @{ */
+
+#define CAN_EPRS_ENPRESDIV_MASK                  (0x3FFU)
+#define CAN_EPRS_ENPRESDIV_SHIFT                 (0U)
+/*! ENPRESDIV - Extended Nominal Prescaler Division Factor */
+#define CAN_EPRS_ENPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK)
+
+#define CAN_EPRS_EDPRESDIV_MASK                  (0x3FF0000U)
+#define CAN_EPRS_EDPRESDIV_SHIFT                 (16U)
+/*! EDPRESDIV - Extended Data Phase Prescaler Division Factor */
+#define CAN_EPRS_EDPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK)
+/*! @} */
+
+/*! @name ENCBT - Enhanced Nominal CAN Bit Timing */
+/*! @{ */
+
+#define CAN_ENCBT_NTSEG1_MASK                    (0xFFU)
+#define CAN_ENCBT_NTSEG1_SHIFT                   (0U)
+/*! NTSEG1 - Nominal Time Segment 1 */
+#define CAN_ENCBT_NTSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK)
+
+#define CAN_ENCBT_NTSEG2_MASK                    (0x7F000U)
+#define CAN_ENCBT_NTSEG2_SHIFT                   (12U)
+/*! NTSEG2 - Nominal Time Segment 2 */
+#define CAN_ENCBT_NTSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK)
+
+#define CAN_ENCBT_NRJW_MASK                      (0x1FC00000U)
+#define CAN_ENCBT_NRJW_SHIFT                     (22U)
+/*! NRJW - Nominal Resynchronization Jump Width */
+#define CAN_ENCBT_NRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK)
+/*! @} */
+
+/*! @name EDCBT - Enhanced Data Phase CAN Bit Timing */
+/*! @{ */
+
+#define CAN_EDCBT_DTSEG1_MASK                    (0x1FU)
+#define CAN_EDCBT_DTSEG1_SHIFT                   (0U)
+/*! DTSEG1 - Data Phase Segment 1 */
+#define CAN_EDCBT_DTSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK)
+
+#define CAN_EDCBT_DTSEG2_MASK                    (0xF000U)
+#define CAN_EDCBT_DTSEG2_SHIFT                   (12U)
+/*! DTSEG2 - Data Phase Time Segment 2 */
+#define CAN_EDCBT_DTSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK)
+
+#define CAN_EDCBT_DRJW_MASK                      (0x3C00000U)
+#define CAN_EDCBT_DRJW_SHIFT                     (22U)
+/*! DRJW - Data Phase Resynchronization Jump Width */
+#define CAN_EDCBT_DRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK)
+/*! @} */
+
+/*! @name ETDC - Enhanced Transceiver Delay Compensation */
+/*! @{ */
+
+#define CAN_ETDC_ETDCVAL_MASK                    (0xFFU)
+#define CAN_ETDC_ETDCVAL_SHIFT                   (0U)
+/*! ETDCVAL - Enhanced Transceiver Delay Compensation Value */
+#define CAN_ETDC_ETDCVAL(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK)
+
+#define CAN_ETDC_ETDCFAIL_MASK                   (0x8000U)
+#define CAN_ETDC_ETDCFAIL_SHIFT                  (15U)
+/*! ETDCFAIL - Transceiver Delay Compensation Fail
+ *  0b0..In range
+ *  0b1..Out of range
+ */
+#define CAN_ETDC_ETDCFAIL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK)
+
+#define CAN_ETDC_ETDCOFF_MASK                    (0x7F0000U)
+#define CAN_ETDC_ETDCOFF_SHIFT                   (16U)
+/*! ETDCOFF - Enhanced Transceiver Delay Compensation Offset */
+#define CAN_ETDC_ETDCOFF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK)
+
+#define CAN_ETDC_TDMDIS_MASK                     (0x40000000U)
+#define CAN_ETDC_TDMDIS_SHIFT                    (30U)
+/*! TDMDIS - Transceiver Delay Measurement Disable
+ *  0b0..Enable
+ *  0b1..Disable
+ */
+#define CAN_ETDC_TDMDIS(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK)
+
+#define CAN_ETDC_ETDCEN_MASK                     (0x80000000U)
+#define CAN_ETDC_ETDCEN_SHIFT                    (31U)
+/*! ETDCEN - Transceiver Delay Compensation Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_ETDC_ETDCEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK)
+/*! @} */
+
+/*! @name FDCTRL - CAN FD Control */
+/*! @{ */
+
+#define CAN_FDCTRL_TDCVAL_MASK                   (0x3FU)
+#define CAN_FDCTRL_TDCVAL_SHIFT                  (0U)
+/*! TDCVAL - Transceiver Delay Compensation Value */
+#define CAN_FDCTRL_TDCVAL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
+
+#define CAN_FDCTRL_TDCOFF_MASK                   (0x1F00U)
+#define CAN_FDCTRL_TDCOFF_SHIFT                  (8U)
+/*! TDCOFF - Transceiver Delay Compensation Offset */
+#define CAN_FDCTRL_TDCOFF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
+
+#define CAN_FDCTRL_TDCFAIL_MASK                  (0x4000U)
+#define CAN_FDCTRL_TDCFAIL_SHIFT                 (14U)
+/*! TDCFAIL - Transceiver Delay Compensation Fail
+ *  0b0..In range
+ *  0b1..Out of range
+ */
+#define CAN_FDCTRL_TDCFAIL(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
+
+#define CAN_FDCTRL_TDCEN_MASK                    (0x8000U)
+#define CAN_FDCTRL_TDCEN_SHIFT                   (15U)
+/*! TDCEN - Transceiver Delay Compensation Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_FDCTRL_TDCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
+
+#define CAN_FDCTRL_MBDSR0_MASK                   (0x30000U)
+#define CAN_FDCTRL_MBDSR0_SHIFT                  (16U)
+/*! MBDSR0 - Message Buffer Data Size for Region 0
+ *  0b00..8 bytes
+ *  0b01..16 bytes
+ *  0b10..32 bytes
+ *  0b11..64 bytes
+ */
+#define CAN_FDCTRL_MBDSR0(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
+
+#define CAN_FDCTRL_FDRATE_MASK                   (0x80000000U)
+#define CAN_FDCTRL_FDRATE_SHIFT                  (31U)
+/*! FDRATE - Bit Rate Switch Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_FDCTRL_FDRATE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
+/*! @} */
+
+/*! @name FDCBT - CAN FD Bit Timing */
+/*! @{ */
+
+#define CAN_FDCBT_FPSEG2_MASK                    (0x7U)
+#define CAN_FDCBT_FPSEG2_SHIFT                   (0U)
+/*! FPSEG2 - Fast Phase Segment 2 */
+#define CAN_FDCBT_FPSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
+
+#define CAN_FDCBT_FPSEG1_MASK                    (0xE0U)
+#define CAN_FDCBT_FPSEG1_SHIFT                   (5U)
+/*! FPSEG1 - Fast Phase Segment 1 */
+#define CAN_FDCBT_FPSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
+
+#define CAN_FDCBT_FPROPSEG_MASK                  (0x7C00U)
+#define CAN_FDCBT_FPROPSEG_SHIFT                 (10U)
+/*! FPROPSEG - Fast Propagation Segment */
+#define CAN_FDCBT_FPROPSEG(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
+
+#define CAN_FDCBT_FRJW_MASK                      (0x70000U)
+#define CAN_FDCBT_FRJW_SHIFT                     (16U)
+/*! FRJW - Fast Resync Jump Width */
+#define CAN_FDCBT_FRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
+
+#define CAN_FDCBT_FPRESDIV_MASK                  (0x3FF00000U)
+#define CAN_FDCBT_FPRESDIV_SHIFT                 (20U)
+/*! FPRESDIV - Fast Prescaler Division Factor */
+#define CAN_FDCBT_FPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
+/*! @} */
+
+/*! @name FDCRC - CAN FD CRC */
+/*! @{ */
+
+#define CAN_FDCRC_FD_TXCRC_MASK                  (0x1FFFFFU)
+#define CAN_FDCRC_FD_TXCRC_SHIFT                 (0U)
+/*! FD_TXCRC - Extended Transmitted CRC value */
+#define CAN_FDCRC_FD_TXCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
+
+#define CAN_FDCRC_FD_MBCRC_MASK                  (0x7F000000U)
+#define CAN_FDCRC_FD_MBCRC_SHIFT                 (24U)
+/*! FD_MBCRC - CRC Message Buffer Number for FD_TXCRC */
+#define CAN_FDCRC_FD_MBCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
+/*! @} */
+
+/*! @name ERFCR - Enhanced RX FIFO Control */
+/*! @{ */
+
+#define CAN_ERFCR_ERFWM_MASK                     (0x1FU)
+#define CAN_ERFCR_ERFWM_SHIFT                    (0U)
+/*! ERFWM - Enhanced RX FIFO Watermark */
+#define CAN_ERFCR_ERFWM(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK)
+
+#define CAN_ERFCR_NFE_MASK                       (0x3F00U)
+#define CAN_ERFCR_NFE_SHIFT                      (8U)
+/*! NFE - Number of Enhanced RX FIFO Filter Elements */
+#define CAN_ERFCR_NFE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK)
+
+#define CAN_ERFCR_NEXIF_MASK                     (0x7F0000U)
+#define CAN_ERFCR_NEXIF_SHIFT                    (16U)
+/*! NEXIF - Number of Extended ID Filter Elements */
+#define CAN_ERFCR_NEXIF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK)
+
+#define CAN_ERFCR_DMALW_MASK                     (0x7C000000U)
+#define CAN_ERFCR_DMALW_SHIFT                    (26U)
+/*! DMALW - DMA Last Word */
+#define CAN_ERFCR_DMALW(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK)
+
+#define CAN_ERFCR_ERFEN_MASK                     (0x80000000U)
+#define CAN_ERFCR_ERFEN_SHIFT                    (31U)
+/*! ERFEN - Enhanced RX FIFO enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_ERFCR_ERFEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
+/*! @} */
+
+/*! @name ERFIER - Enhanced RX FIFO Interrupt Enable */
+/*! @{ */
+
+#define CAN_ERFIER_ERFDAIE_MASK                  (0x10000000U)
+#define CAN_ERFIER_ERFDAIE_SHIFT                 (28U)
+/*! ERFDAIE - Enhanced RX FIFO Data Available Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_ERFIER_ERFDAIE(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK)
+
+#define CAN_ERFIER_ERFWMIIE_MASK                 (0x20000000U)
+#define CAN_ERFIER_ERFWMIIE_SHIFT                (29U)
+/*! ERFWMIIE - Enhanced RX FIFO Watermark Indication Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_ERFIER_ERFWMIIE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK)
+
+#define CAN_ERFIER_ERFOVFIE_MASK                 (0x40000000U)
+#define CAN_ERFIER_ERFOVFIE_SHIFT                (30U)
+/*! ERFOVFIE - Enhanced RX FIFO Overflow Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_ERFIER_ERFOVFIE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK)
+
+#define CAN_ERFIER_ERFUFWIE_MASK                 (0x80000000U)
+#define CAN_ERFIER_ERFUFWIE_SHIFT                (31U)
+/*! ERFUFWIE - Enhanced RX FIFO Underflow Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CAN_ERFIER_ERFUFWIE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK)
+/*! @} */
+
+/*! @name ERFSR - Enhanced RX FIFO Status */
+/*! @{ */
+
+#define CAN_ERFSR_ERFEL_MASK                     (0x3FU)
+#define CAN_ERFSR_ERFEL_SHIFT                    (0U)
+/*! ERFEL - Enhanced RX FIFO Elements */
+#define CAN_ERFSR_ERFEL(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK)
+
+#define CAN_ERFSR_ERFF_MASK                      (0x10000U)
+#define CAN_ERFSR_ERFF_SHIFT                     (16U)
+/*! ERFF - Enhanced RX FIFO Full Flag
+ *  0b0..Not full
+ *  0b1..Full
+ */
+#define CAN_ERFSR_ERFF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK)
+
+#define CAN_ERFSR_ERFE_MASK                      (0x20000U)
+#define CAN_ERFSR_ERFE_SHIFT                     (17U)
+/*! ERFE - Enhanced RX FIFO Empty Flag
+ *  0b0..Not empty
+ *  0b1..Empty
+ */
+#define CAN_ERFSR_ERFE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK)
+
+#define CAN_ERFSR_ERFCLR_MASK                    (0x8000000U)
+#define CAN_ERFSR_ERFCLR_SHIFT                   (27U)
+/*! ERFCLR - Enhanced RX FIFO Clear
+ *  0b0..No effect
+ *  0b1..Clear enhanced RX FIFO content
+ */
+#define CAN_ERFSR_ERFCLR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK)
+
+#define CAN_ERFSR_ERFDA_MASK                     (0x10000000U)
+#define CAN_ERFSR_ERFDA_SHIFT                    (28U)
+/*! ERFDA - Enhanced RX FIFO Data Available Flag
+ *  0b0..No such occurrence
+ *  0b1..At least one message stored in Enhanced RX FIFO
+ */
+#define CAN_ERFSR_ERFDA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK)
+
+#define CAN_ERFSR_ERFWMI_MASK                    (0x20000000U)
+#define CAN_ERFSR_ERFWMI_SHIFT                   (29U)
+/*! ERFWMI - Enhanced RX FIFO Watermark Indication Flag
+ *  0b0..No such occurrence
+ *  0b1..Number of messages in FIFO is greater than the watermark
+ */
+#define CAN_ERFSR_ERFWMI(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
+
+#define CAN_ERFSR_ERFOVF_MASK                    (0x40000000U)
+#define CAN_ERFSR_ERFOVF_SHIFT                   (30U)
+/*! ERFOVF - Enhanced RX FIFO Overflow Flag
+ *  0b0..No such occurrence
+ *  0b1..Overflow
+ */
+#define CAN_ERFSR_ERFOVF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK)
+
+#define CAN_ERFSR_ERFUFW_MASK                    (0x80000000U)
+#define CAN_ERFSR_ERFUFW_SHIFT                   (31U)
+/*! ERFUFW - Enhanced RX FIFO Underflow Flag
+ *  0b0..No such occurrence
+ *  0b1..Underflow
+ */
+#define CAN_ERFSR_ERFUFW(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK)
+/*! @} */
+
+/*! @name ERFFEL - Enhanced RX FIFO Filter Element */
+/*! @{ */
+
+#define CAN_ERFFEL_FEL_MASK                      (0xFFFFFFFFU)
+#define CAN_ERFFEL_FEL_SHIFT                     (0U)
+/*! FEL - Filter Element Bits */
+#define CAN_ERFFEL_FEL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_CAN_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CDOG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CDOG.h
new file mode 100644
index 0000000000..0b03de7e90
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CDOG.h
@@ -0,0 +1,472 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for CDOG
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_CDOG.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for CDOG
+ *
+ * CMSIS Peripheral Access Layer for CDOG
+ */
+
+#if !defined(PERI_CDOG_H_)
+#define PERI_CDOG_H_                             /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- CDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer
+ * @{
+ */
+
+/** CDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Control Register, offset: 0x0 */
+  __IO uint32_t RELOAD;                            /**< Instruction Timer Reload Register, offset: 0x4 */
+  __I  uint32_t INSTRUCTION_TIMER;                 /**< Instruction Timer Register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __I  uint32_t STATUS;                            /**< Status 1 Register, offset: 0x10 */
+  __I  uint32_t STATUS2;                           /**< Status 2 Register, offset: 0x14 */
+  __IO uint32_t FLAGS;                             /**< Flags Register, offset: 0x18 */
+  __IO uint32_t PERSISTENT;                        /**< Persistent Data Storage Register, offset: 0x1C */
+  __O  uint32_t START;                             /**< START Command Register, offset: 0x20 */
+  __O  uint32_t STOP;                              /**< STOP Command Register, offset: 0x24 */
+  __O  uint32_t RESTART;                           /**< RESTART Command Register, offset: 0x28 */
+  __O  uint32_t ADD;                               /**< ADD Command Register, offset: 0x2C */
+  __O  uint32_t ADD1;                              /**< ADD1 Command Register, offset: 0x30 */
+  __O  uint32_t ADD16;                             /**< ADD16 Command Register, offset: 0x34 */
+  __O  uint32_t ADD256;                            /**< ADD256 Command Register, offset: 0x38 */
+  __O  uint32_t SUB;                               /**< SUB Command Register, offset: 0x3C */
+  __O  uint32_t SUB1;                              /**< SUB1 Command Register, offset: 0x40 */
+  __O  uint32_t SUB16;                             /**< SUB16 Command Register, offset: 0x44 */
+  __O  uint32_t SUB256;                            /**< SUB256 Command Register, offset: 0x48 */
+  __O  uint32_t ASSERT16;                          /**< ASSERT16 Command Register, offset: 0x4C */
+} CDOG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CDOG_Register_Masks CDOG Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Control Register */
+/*! @{ */
+
+#define CDOG_CONTROL_LOCK_CTRL_MASK              (0x3U)
+#define CDOG_CONTROL_LOCK_CTRL_SHIFT             (0U)
+/*! LOCK_CTRL - Lock control
+ *  0b01..Locked
+ *  0b10..Unlocked
+ */
+#define CDOG_CONTROL_LOCK_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK)
+
+#define CDOG_CONTROL_TIMEOUT_CTRL_MASK           (0x1CU)
+#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT          (2U)
+/*! TIMEOUT_CTRL - TIMEOUT fault control
+ *  0b001..Enable reset
+ *  0b010..Enable interrupt
+ *  0b100..Disable both reset and interrupt
+ */
+#define CDOG_CONTROL_TIMEOUT_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK)
+
+#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK        (0xE0U)
+#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT       (5U)
+/*! MISCOMPARE_CTRL - MISCOMPARE fault control
+ *  0b001..Enable reset
+ *  0b010..Enable interrupt
+ *  0b100..Disable both reset and interrupt
+ */
+#define CDOG_CONTROL_MISCOMPARE_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK)
+
+#define CDOG_CONTROL_SEQUENCE_CTRL_MASK          (0x700U)
+#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT         (8U)
+/*! SEQUENCE_CTRL - SEQUENCE fault control
+ *  0b001..Enable reset
+ *  0b010..Enable interrupt
+ *  0b100..Disable both reset and interrupt
+ */
+#define CDOG_CONTROL_SEQUENCE_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK)
+
+#define CDOG_CONTROL_STATE_CTRL_MASK             (0x1C000U)
+#define CDOG_CONTROL_STATE_CTRL_SHIFT            (14U)
+/*! STATE_CTRL - STATE fault control
+ *  0b001..Enable reset
+ *  0b010..Enable interrupt
+ *  0b100..Disable both reset and interrupt
+ */
+#define CDOG_CONTROL_STATE_CTRL(x)               (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK)
+
+#define CDOG_CONTROL_ADDRESS_CTRL_MASK           (0xE0000U)
+#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT          (17U)
+/*! ADDRESS_CTRL - ADDRESS fault control
+ *  0b001..Enable reset
+ *  0b010..Enable interrupt
+ *  0b100..Disable both reset and interrupt
+ */
+#define CDOG_CONTROL_ADDRESS_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK)
+
+#define CDOG_CONTROL_IRQ_PAUSE_MASK              (0x30000000U)
+#define CDOG_CONTROL_IRQ_PAUSE_SHIFT             (28U)
+/*! IRQ_PAUSE - IRQ pause control
+ *  0b01..Keep the timer running
+ *  0b10..Stop the timer
+ */
+#define CDOG_CONTROL_IRQ_PAUSE(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK)
+
+#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK        (0xC0000000U)
+#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT       (30U)
+/*! DEBUG_HALT_CTRL - DEBUG_HALT control
+ *  0b01..Keep the timer running
+ *  0b10..Stop the timer
+ */
+#define CDOG_CONTROL_DEBUG_HALT_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK)
+/*! @} */
+
+/*! @name RELOAD - Instruction Timer Reload Register */
+/*! @{ */
+
+#define CDOG_RELOAD_RLOAD_MASK                   (0xFFFFFFFFU)
+#define CDOG_RELOAD_RLOAD_SHIFT                  (0U)
+/*! RLOAD - Instruction Timer reload value */
+#define CDOG_RELOAD_RLOAD(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK)
+/*! @} */
+
+/*! @name INSTRUCTION_TIMER - Instruction Timer Register */
+/*! @{ */
+
+#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK       (0xFFFFFFFFU)
+#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT      (0U)
+/*! INSTIM - Current value of the Instruction Timer */
+#define CDOG_INSTRUCTION_TIMER_INSTIM(x)         (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK)
+/*! @} */
+
+/*! @name STATUS - Status 1 Register */
+/*! @{ */
+
+#define CDOG_STATUS_NUMTOF_MASK                  (0xFFU)
+#define CDOG_STATUS_NUMTOF_SHIFT                 (0U)
+/*! NUMTOF - Number of TIMEOUT faults (FLAGS[TIMEOUT_FLAG]) since the last POR */
+#define CDOG_STATUS_NUMTOF(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK)
+
+#define CDOG_STATUS_NUMMISCOMPF_MASK             (0xFF00U)
+#define CDOG_STATUS_NUMMISCOMPF_SHIFT            (8U)
+/*! NUMMISCOMPF - Number of MISCOMPARE faults (FLAGS[MISCOMPARE_FLAG]) since the last POR */
+#define CDOG_STATUS_NUMMISCOMPF(x)               (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK)
+
+#define CDOG_STATUS_NUMILSEQF_MASK               (0xFF0000U)
+#define CDOG_STATUS_NUMILSEQF_SHIFT              (16U)
+/*! NUMILSEQF - Number of SEQUENCE faults (FLAGS[SEQUENCE_FLAG]) since the last POR */
+#define CDOG_STATUS_NUMILSEQF(x)                 (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK)
+
+#define CDOG_STATUS_CURST_MASK                   (0xF0000000U)
+#define CDOG_STATUS_CURST_SHIFT                  (28U)
+/*! CURST - Current State */
+#define CDOG_STATUS_CURST(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK)
+/*! @} */
+
+/*! @name STATUS2 - Status 2 Register */
+/*! @{ */
+
+#define CDOG_STATUS2_NUMCNTF_MASK                (0xFFU)
+#define CDOG_STATUS2_NUMCNTF_SHIFT               (0U)
+/*! NUMCNTF - Number of CONTROL faults (FLAGS[CONTROL_FLAG]) since the last POR */
+#define CDOG_STATUS2_NUMCNTF(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK)
+
+#define CDOG_STATUS2_NUMILLSTF_MASK              (0xFF00U)
+#define CDOG_STATUS2_NUMILLSTF_SHIFT             (8U)
+/*! NUMILLSTF - Number of STATE faults (FLAGS[STATE_FLAG]) since the last POR */
+#define CDOG_STATUS2_NUMILLSTF(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK)
+
+#define CDOG_STATUS2_NUMILLA_MASK                (0xFF0000U)
+#define CDOG_STATUS2_NUMILLA_SHIFT               (16U)
+/*! NUMILLA - Number of ADDRESS faults (FLAGS[ADDR_FLAG]) since the last POR */
+#define CDOG_STATUS2_NUMILLA(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK)
+/*! @} */
+
+/*! @name FLAGS - Flags Register */
+/*! @{ */
+
+#define CDOG_FLAGS_TO_FLAG_MASK                  (0x1U)
+#define CDOG_FLAGS_TO_FLAG_SHIFT                 (0U)
+/*! TO_FLAG - TIMEOUT fault flag
+ *  0b0..A TIMEOUT fault has not occurred
+ *  0b1..A TIMEOUT fault has occurred
+ */
+#define CDOG_FLAGS_TO_FLAG(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK)
+
+#define CDOG_FLAGS_MISCOM_FLAG_MASK              (0x2U)
+#define CDOG_FLAGS_MISCOM_FLAG_SHIFT             (1U)
+/*! MISCOM_FLAG - MISCOMPARE fault flag
+ *  0b0..A MISCOMPARE fault has not occurred
+ *  0b1..A MISCOMPARE fault has occurred
+ */
+#define CDOG_FLAGS_MISCOM_FLAG(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK)
+
+#define CDOG_FLAGS_SEQ_FLAG_MASK                 (0x4U)
+#define CDOG_FLAGS_SEQ_FLAG_SHIFT                (2U)
+/*! SEQ_FLAG - SEQUENCE fault flag
+ *  0b0..A SEQUENCE fault has not occurred
+ *  0b1..A SEQUENCE fault has occurred
+ */
+#define CDOG_FLAGS_SEQ_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK)
+
+#define CDOG_FLAGS_CNT_FLAG_MASK                 (0x8U)
+#define CDOG_FLAGS_CNT_FLAG_SHIFT                (3U)
+/*! CNT_FLAG - CONTROL fault flag
+ *  0b0..A CONTROL fault has not occurred
+ *  0b1..A CONTROL fault has occurred
+ */
+#define CDOG_FLAGS_CNT_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK)
+
+#define CDOG_FLAGS_STATE_FLAG_MASK               (0x10U)
+#define CDOG_FLAGS_STATE_FLAG_SHIFT              (4U)
+/*! STATE_FLAG - STATE fault flag
+ *  0b0..A STATE fault has not occurred
+ *  0b1..A STATE fault has occurred
+ */
+#define CDOG_FLAGS_STATE_FLAG(x)                 (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK)
+
+#define CDOG_FLAGS_ADDR_FLAG_MASK                (0x20U)
+#define CDOG_FLAGS_ADDR_FLAG_SHIFT               (5U)
+/*! ADDR_FLAG - ADDRESS fault flag
+ *  0b0..An ADDRESS fault has not occurred
+ *  0b1..An ADDRESS fault has occurred
+ */
+#define CDOG_FLAGS_ADDR_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK)
+
+#define CDOG_FLAGS_POR_FLAG_MASK                 (0x10000U)
+#define CDOG_FLAGS_POR_FLAG_SHIFT                (16U)
+/*! POR_FLAG - Power-on reset flag
+ *  0b0..A Power-on reset event has not occurred
+ *  0b1..A Power-on reset event has occurred
+ */
+#define CDOG_FLAGS_POR_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK)
+/*! @} */
+
+/*! @name PERSISTENT - Persistent Data Storage Register */
+/*! @{ */
+
+#define CDOG_PERSISTENT_PERSIS_MASK              (0xFFFFFFFFU)
+#define CDOG_PERSISTENT_PERSIS_SHIFT             (0U)
+/*! PERSIS - Persistent Storage */
+#define CDOG_PERSISTENT_PERSIS(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK)
+/*! @} */
+
+/*! @name START - START Command Register */
+/*! @{ */
+
+#define CDOG_START_STRT_MASK                     (0xFFFFFFFFU)
+#define CDOG_START_STRT_SHIFT                    (0U)
+/*! STRT - Start command */
+#define CDOG_START_STRT(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK)
+/*! @} */
+
+/*! @name STOP - STOP Command Register */
+/*! @{ */
+
+#define CDOG_STOP_STP_MASK                       (0xFFFFFFFFU)
+#define CDOG_STOP_STP_SHIFT                      (0U)
+/*! STP - Stop command */
+#define CDOG_STOP_STP(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK)
+/*! @} */
+
+/*! @name RESTART - RESTART Command Register */
+/*! @{ */
+
+#define CDOG_RESTART_RSTRT_MASK                  (0xFFFFFFFFU)
+#define CDOG_RESTART_RSTRT_SHIFT                 (0U)
+/*! RSTRT - Restart command */
+#define CDOG_RESTART_RSTRT(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK)
+/*! @} */
+
+/*! @name ADD - ADD Command Register */
+/*! @{ */
+
+#define CDOG_ADD_AD_MASK                         (0xFFFFFFFFU)
+#define CDOG_ADD_AD_SHIFT                        (0U)
+/*! AD - ADD Write Value */
+#define CDOG_ADD_AD(x)                           (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK)
+/*! @} */
+
+/*! @name ADD1 - ADD1 Command Register */
+/*! @{ */
+
+#define CDOG_ADD1_AD1_MASK                       (0xFFFFFFFFU)
+#define CDOG_ADD1_AD1_SHIFT                      (0U)
+/*! AD1 - ADD 1 */
+#define CDOG_ADD1_AD1(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK)
+/*! @} */
+
+/*! @name ADD16 - ADD16 Command Register */
+/*! @{ */
+
+#define CDOG_ADD16_AD16_MASK                     (0xFFFFFFFFU)
+#define CDOG_ADD16_AD16_SHIFT                    (0U)
+/*! AD16 - ADD 16 */
+#define CDOG_ADD16_AD16(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK)
+/*! @} */
+
+/*! @name ADD256 - ADD256 Command Register */
+/*! @{ */
+
+#define CDOG_ADD256_AD256_MASK                   (0xFFFFFFFFU)
+#define CDOG_ADD256_AD256_SHIFT                  (0U)
+/*! AD256 - ADD 256 */
+#define CDOG_ADD256_AD256(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK)
+/*! @} */
+
+/*! @name SUB - SUB Command Register */
+/*! @{ */
+
+#define CDOG_SUB_SB_MASK                         (0xFFFFFFFFU)
+#define CDOG_SUB_SB_SHIFT                        (0U)
+/*! SB - Subtract Write Value */
+#define CDOG_SUB_SB(x)                           (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_SB_SHIFT)) & CDOG_SUB_SB_MASK)
+/*! @} */
+
+/*! @name SUB1 - SUB1 Command Register */
+/*! @{ */
+
+#define CDOG_SUB1_SB1_MASK                       (0xFFFFFFFFU)
+#define CDOG_SUB1_SB1_SHIFT                      (0U)
+/*! SB1 - Subtract 1 */
+#define CDOG_SUB1_SB1(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_SB1_SHIFT)) & CDOG_SUB1_SB1_MASK)
+/*! @} */
+
+/*! @name SUB16 - SUB16 Command Register */
+/*! @{ */
+
+#define CDOG_SUB16_SB16_MASK                     (0xFFFFFFFFU)
+#define CDOG_SUB16_SB16_SHIFT                    (0U)
+/*! SB16 - Subtract 16 */
+#define CDOG_SUB16_SB16(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK)
+/*! @} */
+
+/*! @name SUB256 - SUB256 Command Register */
+/*! @{ */
+
+#define CDOG_SUB256_SB256_MASK                   (0xFFFFFFFFU)
+#define CDOG_SUB256_SB256_SHIFT                  (0U)
+/*! SB256 - Subtract 256 */
+#define CDOG_SUB256_SB256(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK)
+/*! @} */
+
+/*! @name ASSERT16 - ASSERT16 Command Register */
+/*! @{ */
+
+#define CDOG_ASSERT16_AST16_MASK                 (0xFFFFFFFFU)
+#define CDOG_ASSERT16_AST16_SHIFT                (0U)
+/*! AST16 - ASSERT16 Command */
+#define CDOG_ASSERT16_AST16(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_ASSERT16_AST16_SHIFT)) & CDOG_ASSERT16_AST16_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CDOG_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group CDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_CDOG_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CMC.h
new file mode 100644
index 0000000000..7ddcee0acc
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CMC.h
@@ -0,0 +1,767 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for CMC
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_CMC.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for CMC
+ *
+ * CMSIS Peripheral Access Layer for CMC
+ */
+
+#if !defined(PERI_CMC_H_)
+#define PERI_CMC_H_                              /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- CMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMC_Peripheral_Access_Layer CMC Peripheral Access Layer
+ * @{
+ */
+
+/** CMC - Size of Registers Arrays */
+#define CMC_PMCTRL_COUNT                          1u
+#define CMC_MR_COUNT                              1u
+#define CMC_FM_COUNT                              1u
+
+/** CMC - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t CKCTRL;                            /**< Clock Control, offset: 0x10 */
+  __IO uint32_t CKSTAT;                            /**< Clock Status, offset: 0x14 */
+  __IO uint32_t PMPROT;                            /**< Power Mode Protection, offset: 0x18 */
+  __IO uint32_t GPMCTRL;                           /**< Global Power Mode Control, offset: 0x1C */
+  __IO uint32_t PMCTRL[CMC_PMCTRL_COUNT];          /**< Power Mode Control, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[92];
+  __I  uint32_t SRS;                               /**< System Reset Status, offset: 0x80 */
+  __IO uint32_t RPC;                               /**< Reset Pin Control, offset: 0x84 */
+  __IO uint32_t SSRS;                              /**< Sticky System Reset Status, offset: 0x88 */
+  __IO uint32_t SRIE;                              /**< System Reset Interrupt Enable, offset: 0x8C */
+  __IO uint32_t SRIF;                              /**< System Reset Interrupt Flag, offset: 0x90 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t MR[CMC_MR_COUNT];                  /**< Mode, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_3[12];
+  __IO uint32_t FM[CMC_FM_COUNT];                  /**< Force Mode, array offset: 0xB0, array step: 0x4 */
+       uint8_t RESERVED_4[44];
+  __IO uint32_t FLASHCR;                           /**< Flash Control, offset: 0xE0 */
+       uint8_t RESERVED_5[44];
+  __IO uint32_t CORECTL;                           /**< Core Control, offset: 0x110 */
+       uint8_t RESERVED_6[12];
+  __IO uint32_t DBGCTL;                            /**< Debug Control, offset: 0x120 */
+} CMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMC_Register_Masks CMC Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID */
+/*! @{ */
+
+#define CMC_VERID_FEATURE_MASK                   (0xFFFFU)
+#define CMC_VERID_FEATURE_SHIFT                  (0U)
+/*! FEATURE - Feature Specification Number */
+#define CMC_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_VERID_FEATURE_SHIFT)) & CMC_VERID_FEATURE_MASK)
+
+#define CMC_VERID_MINOR_MASK                     (0xFF0000U)
+#define CMC_VERID_MINOR_SHIFT                    (16U)
+/*! MINOR - Minor Version Number */
+#define CMC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MINOR_SHIFT)) & CMC_VERID_MINOR_MASK)
+
+#define CMC_VERID_MAJOR_MASK                     (0xFF000000U)
+#define CMC_VERID_MAJOR_SHIFT                    (24U)
+/*! MAJOR - Major Version Number */
+#define CMC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MAJOR_SHIFT)) & CMC_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name CKCTRL - Clock Control */
+/*! @{ */
+
+#define CMC_CKCTRL_CKMODE_MASK                   (0xFU)
+#define CMC_CKCTRL_CKMODE_SHIFT                  (0U)
+/*! CKMODE - Clocking Mode
+ *  0b0000..Core clock is on
+ *  0b0001..Core clock is off
+ *  0b1111..Core, platform, and peripheral clocks are off, and core enters Low-Power mode
+ */
+#define CMC_CKCTRL_CKMODE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_CKMODE_SHIFT)) & CMC_CKCTRL_CKMODE_MASK)
+
+#define CMC_CKCTRL_LOCK_MASK                     (0x80000000U)
+#define CMC_CKCTRL_LOCK_SHIFT                    (31U)
+/*! LOCK - Lock
+ *  0b0..Allowed
+ *  0b1..Blocked
+ */
+#define CMC_CKCTRL_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_LOCK_SHIFT)) & CMC_CKCTRL_LOCK_MASK)
+/*! @} */
+
+/*! @name CKSTAT - Clock Status */
+/*! @{ */
+
+#define CMC_CKSTAT_CKMODE_MASK                   (0xFU)
+#define CMC_CKSTAT_CKMODE_SHIFT                  (0U)
+/*! CKMODE - Low Power Status
+ *  0b0000..Core clock is on
+ *  0b0001..Core clock is off
+ *  0b1111..Core, platform, and peripheral clocks are off, and core enters Low-Power mode
+ */
+#define CMC_CKSTAT_CKMODE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_CKMODE_SHIFT)) & CMC_CKSTAT_CKMODE_MASK)
+
+#define CMC_CKSTAT_WAKEUP_MASK                   (0xFF00U)
+#define CMC_CKSTAT_WAKEUP_SHIFT                  (8U)
+/*! WAKEUP - Wake-up Source */
+#define CMC_CKSTAT_WAKEUP(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_WAKEUP_SHIFT)) & CMC_CKSTAT_WAKEUP_MASK)
+
+#define CMC_CKSTAT_VALID_MASK                    (0x80000000U)
+#define CMC_CKSTAT_VALID_SHIFT                   (31U)
+/*! VALID - Clock Status Valid
+ *  0b0..Core clock not gated
+ *  0b1..Core clock was gated due to Low-Power mode entry
+ */
+#define CMC_CKSTAT_VALID(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_VALID_SHIFT)) & CMC_CKSTAT_VALID_MASK)
+/*! @} */
+
+/*! @name PMPROT - Power Mode Protection */
+/*! @{ */
+
+#define CMC_PMPROT_LPMODE_MASK                   (0xFU)
+#define CMC_PMPROT_LPMODE_SHIFT                  (0U)
+/*! LPMODE - Low-Power Mode
+ *  0b0000..Not allowed
+ *  0b0001..Allowed
+ *  0b0010..Allowed
+ *  0b0011..Allowed
+ *  0b0100..Allowed
+ *  0b0101..Allowed
+ *  0b0110..Allowed
+ *  0b0111..Allowed
+ *  0b1000..Allowed
+ *  0b1001..Allowed
+ *  0b1010..Allowed
+ *  0b1011..Allowed
+ *  0b1100..Allowed
+ *  0b1101..Allowed
+ *  0b1110..Allowed
+ *  0b1111..Allowed
+ */
+#define CMC_PMPROT_LPMODE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LPMODE_SHIFT)) & CMC_PMPROT_LPMODE_MASK)
+
+#define CMC_PMPROT_LOCK_MASK                     (0x80000000U)
+#define CMC_PMPROT_LOCK_SHIFT                    (31U)
+/*! LOCK - Lock Register
+ *  0b0..Allowed
+ *  0b1..Blocked
+ */
+#define CMC_PMPROT_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LOCK_SHIFT)) & CMC_PMPROT_LOCK_MASK)
+/*! @} */
+
+/*! @name GPMCTRL - Global Power Mode Control */
+/*! @{ */
+
+#define CMC_GPMCTRL_LPMODE_MASK                  (0xFU)
+#define CMC_GPMCTRL_LPMODE_SHIFT                 (0U)
+/*! LPMODE - Low-Power Mode */
+#define CMC_GPMCTRL_LPMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_GPMCTRL_LPMODE_SHIFT)) & CMC_GPMCTRL_LPMODE_MASK)
+/*! @} */
+
+/*! @name PMCTRL - Power Mode Control */
+/*! @{ */
+
+#define CMC_PMCTRL_LPMODE_MASK                   (0xFU)
+#define CMC_PMCTRL_LPMODE_SHIFT                  (0U)
+/*! LPMODE - Low-Power Mode
+ *  0b0000..Active/Sleep
+ *  0b0001..Deep Sleep
+ *  0b0011..Power Down
+ *  0b0111..Reserved
+ *  0b1111..Deep-Power Down
+ */
+#define CMC_PMCTRL_LPMODE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_PMCTRL_LPMODE_SHIFT)) & CMC_PMCTRL_LPMODE_MASK)
+/*! @} */
+
+/*! @name SRS - System Reset Status */
+/*! @{ */
+
+#define CMC_SRS_WAKEUP_MASK                      (0x1U)
+#define CMC_SRS_WAKEUP_SHIFT                     (0U)
+/*! WAKEUP - Wake-up Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SRS_WAKEUP(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WAKEUP_SHIFT)) & CMC_SRS_WAKEUP_MASK)
+
+#define CMC_SRS_POR_MASK                         (0x2U)
+#define CMC_SRS_POR_SHIFT                        (1U)
+/*! POR - Power-on Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SRS_POR(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_POR_SHIFT)) & CMC_SRS_POR_MASK)
+
+#define CMC_SRS_VD_MASK                          (0x4U)
+#define CMC_SRS_VD_SHIFT                         (2U)
+/*! VD - Voltage Detect Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SRS_VD(x)                            (((uint32_t)(((uint32_t)(x)) << CMC_SRS_VD_SHIFT)) & CMC_SRS_VD_MASK)
+
+#define CMC_SRS_WARM_MASK                        (0x10U)
+#define CMC_SRS_WARM_SHIFT                       (4U)
+/*! WARM - Warm Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SRS_WARM(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WARM_SHIFT)) & CMC_SRS_WARM_MASK)
+
+#define CMC_SRS_FATAL_MASK                       (0x20U)
+#define CMC_SRS_FATAL_SHIFT                      (5U)
+/*! FATAL - Fatal Reset
+ *  0b0..Reset was not generated
+ *  0b1..Reset was generated
+ */
+#define CMC_SRS_FATAL(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_FATAL_SHIFT)) & CMC_SRS_FATAL_MASK)
+
+#define CMC_SRS_PIN_MASK                         (0x100U)
+#define CMC_SRS_PIN_SHIFT                        (8U)
+/*! PIN - Pin Reset
+ *  0b0..Reset was not generated
+ *  0b1..Reset was generated
+ */
+#define CMC_SRS_PIN(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_PIN_SHIFT)) & CMC_SRS_PIN_MASK)
+
+#define CMC_SRS_DAP_MASK                         (0x200U)
+#define CMC_SRS_DAP_SHIFT                        (9U)
+/*! DAP - Debug Access Port Reset
+ *  0b0..Reset was not generated
+ *  0b1..Reset was generated
+ */
+#define CMC_SRS_DAP(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_DAP_SHIFT)) & CMC_SRS_DAP_MASK)
+
+#define CMC_SRS_RSTACK_MASK                      (0x400U)
+#define CMC_SRS_RSTACK_SHIFT                     (10U)
+/*! RSTACK - Reset Timeout
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SRS_RSTACK(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_RSTACK_SHIFT)) & CMC_SRS_RSTACK_MASK)
+
+#define CMC_SRS_LPACK_MASK                       (0x800U)
+#define CMC_SRS_LPACK_SHIFT                      (11U)
+/*! LPACK - Low Power Acknowledge Timeout Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SRS_LPACK(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LPACK_SHIFT)) & CMC_SRS_LPACK_MASK)
+
+#define CMC_SRS_SCG_MASK                         (0x1000U)
+#define CMC_SRS_SCG_SHIFT                        (12U)
+/*! SCG - System Clock Generation Reset
+ *  0b0..Reset is not generated
+ *  0b1..Reset is generated
+ */
+#define CMC_SRS_SCG(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SCG_SHIFT)) & CMC_SRS_SCG_MASK)
+
+#define CMC_SRS_WWDT0_MASK                       (0x2000U)
+#define CMC_SRS_WWDT0_SHIFT                      (13U)
+/*! WWDT0 - Windowed Watchdog 0 Reset
+ *  0b0..Reset is not generated
+ *  0b1..Reset is generated
+ */
+#define CMC_SRS_WWDT0(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WWDT0_SHIFT)) & CMC_SRS_WWDT0_MASK)
+
+#define CMC_SRS_SW_MASK                          (0x4000U)
+#define CMC_SRS_SW_SHIFT                         (14U)
+/*! SW - Software Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SRS_SW(x)                            (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SW_SHIFT)) & CMC_SRS_SW_MASK)
+
+#define CMC_SRS_LOCKUP_MASK                      (0x8000U)
+#define CMC_SRS_LOCKUP_SHIFT                     (15U)
+/*! LOCKUP - Lockup Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SRS_LOCKUP(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LOCKUP_SHIFT)) & CMC_SRS_LOCKUP_MASK)
+
+#define CMC_SRS_CDOG0_MASK                       (0x4000000U)
+#define CMC_SRS_CDOG0_SHIFT                      (26U)
+/*! CDOG0 - Code Watchdog 0 Reset
+ *  0b0..Reset is not generated
+ *  0b1..Reset is generated
+ */
+#define CMC_SRS_CDOG0(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CDOG0_SHIFT)) & CMC_SRS_CDOG0_MASK)
+
+#define CMC_SRS_JTAG_MASK                        (0x10000000U)
+#define CMC_SRS_JTAG_SHIFT                       (28U)
+/*! JTAG - JTAG System Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SRS_JTAG(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRS_JTAG_SHIFT)) & CMC_SRS_JTAG_MASK)
+/*! @} */
+
+/*! @name RPC - Reset Pin Control */
+/*! @{ */
+
+#define CMC_RPC_FILTCFG_MASK                     (0x1FU)
+#define CMC_RPC_FILTCFG_SHIFT                    (0U)
+/*! FILTCFG - Reset Filter Configuration */
+#define CMC_RPC_FILTCFG(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTCFG_SHIFT)) & CMC_RPC_FILTCFG_MASK)
+
+#define CMC_RPC_FILTEN_MASK                      (0x100U)
+#define CMC_RPC_FILTEN_SHIFT                     (8U)
+/*! FILTEN - Filter Enable
+ *  0b0..Disables
+ *  0b1..Enables
+ */
+#define CMC_RPC_FILTEN(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTEN_SHIFT)) & CMC_RPC_FILTEN_MASK)
+
+#define CMC_RPC_LPFEN_MASK                       (0x200U)
+#define CMC_RPC_LPFEN_SHIFT                      (9U)
+/*! LPFEN - Low-Power Filter Enable
+ *  0b0..Disables
+ *  0b1..Enables
+ */
+#define CMC_RPC_LPFEN(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_RPC_LPFEN_SHIFT)) & CMC_RPC_LPFEN_MASK)
+/*! @} */
+
+/*! @name SSRS - Sticky System Reset Status */
+/*! @{ */
+
+#define CMC_SSRS_WAKEUP_MASK                     (0x1U)
+#define CMC_SSRS_WAKEUP_SHIFT                    (0U)
+/*! WAKEUP - Wake-up Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SSRS_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WAKEUP_SHIFT)) & CMC_SSRS_WAKEUP_MASK)
+
+#define CMC_SSRS_POR_MASK                        (0x2U)
+#define CMC_SSRS_POR_SHIFT                       (1U)
+/*! POR - Power-on Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SSRS_POR(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_POR_SHIFT)) & CMC_SSRS_POR_MASK)
+
+#define CMC_SSRS_VD_MASK                         (0x4U)
+#define CMC_SSRS_VD_SHIFT                        (2U)
+/*! VD - Voltage Detect Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SSRS_VD(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_VD_SHIFT)) & CMC_SSRS_VD_MASK)
+
+#define CMC_SSRS_WARM_MASK                       (0x10U)
+#define CMC_SSRS_WARM_SHIFT                      (4U)
+/*! WARM - Warm Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SSRS_WARM(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WARM_SHIFT)) & CMC_SSRS_WARM_MASK)
+
+#define CMC_SSRS_FATAL_MASK                      (0x20U)
+#define CMC_SSRS_FATAL_SHIFT                     (5U)
+/*! FATAL - Fatal Reset
+ *  0b0..Reset was not generated
+ *  0b1..Reset was generated
+ */
+#define CMC_SSRS_FATAL(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_FATAL_SHIFT)) & CMC_SSRS_FATAL_MASK)
+
+#define CMC_SSRS_PIN_MASK                        (0x100U)
+#define CMC_SSRS_PIN_SHIFT                       (8U)
+/*! PIN - Pin Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SSRS_PIN(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_PIN_SHIFT)) & CMC_SSRS_PIN_MASK)
+
+#define CMC_SSRS_DAP_MASK                        (0x200U)
+#define CMC_SSRS_DAP_SHIFT                       (9U)
+/*! DAP - DAP Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SSRS_DAP(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_DAP_SHIFT)) & CMC_SSRS_DAP_MASK)
+
+#define CMC_SSRS_RSTACK_MASK                     (0x400U)
+#define CMC_SSRS_RSTACK_SHIFT                    (10U)
+/*! RSTACK - Reset Timeout
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SSRS_RSTACK(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_RSTACK_SHIFT)) & CMC_SSRS_RSTACK_MASK)
+
+#define CMC_SSRS_LPACK_MASK                      (0x800U)
+#define CMC_SSRS_LPACK_SHIFT                     (11U)
+/*! LPACK - Low Power Acknowledge Timeout Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SSRS_LPACK(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LPACK_SHIFT)) & CMC_SSRS_LPACK_MASK)
+
+#define CMC_SSRS_SCG_MASK                        (0x1000U)
+#define CMC_SSRS_SCG_SHIFT                       (12U)
+/*! SCG - System Clock Generation Reset
+ *  0b0..Reset is not generated
+ *  0b1..Reset is generated
+ */
+#define CMC_SSRS_SCG(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SCG_SHIFT)) & CMC_SSRS_SCG_MASK)
+
+#define CMC_SSRS_WWDT0_MASK                      (0x2000U)
+#define CMC_SSRS_WWDT0_SHIFT                     (13U)
+/*! WWDT0 - Windowed Watchdog 0 Reset
+ *  0b0..Reset is not generated
+ *  0b1..Reset is generated
+ */
+#define CMC_SSRS_WWDT0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WWDT0_SHIFT)) & CMC_SSRS_WWDT0_MASK)
+
+#define CMC_SSRS_SW_MASK                         (0x4000U)
+#define CMC_SSRS_SW_SHIFT                        (14U)
+/*! SW - Software Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SSRS_SW(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SW_SHIFT)) & CMC_SSRS_SW_MASK)
+
+#define CMC_SSRS_LOCKUP_MASK                     (0x8000U)
+#define CMC_SSRS_LOCKUP_SHIFT                    (15U)
+/*! LOCKUP - Lockup Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SSRS_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LOCKUP_SHIFT)) & CMC_SSRS_LOCKUP_MASK)
+
+#define CMC_SSRS_CDOG0_MASK                      (0x4000000U)
+#define CMC_SSRS_CDOG0_SHIFT                     (26U)
+/*! CDOG0 - Code Watchdog 0 Reset
+ *  0b0..Reset is not generated
+ *  0b1..Reset is generated
+ */
+#define CMC_SSRS_CDOG0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CDOG0_SHIFT)) & CMC_SSRS_CDOG0_MASK)
+
+#define CMC_SSRS_JTAG_MASK                       (0x10000000U)
+#define CMC_SSRS_JTAG_SHIFT                      (28U)
+/*! JTAG - JTAG System Reset
+ *  0b0..Reset not generated
+ *  0b1..Reset generated
+ */
+#define CMC_SSRS_JTAG(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_JTAG_SHIFT)) & CMC_SSRS_JTAG_MASK)
+/*! @} */
+
+/*! @name SRIE - System Reset Interrupt Enable */
+/*! @{ */
+
+#define CMC_SRIE_PIN_MASK                        (0x100U)
+#define CMC_SRIE_PIN_SHIFT                       (8U)
+/*! PIN - Pin Reset
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
+#define CMC_SRIE_PIN(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_PIN_SHIFT)) & CMC_SRIE_PIN_MASK)
+
+#define CMC_SRIE_DAP_MASK                        (0x200U)
+#define CMC_SRIE_DAP_SHIFT                       (9U)
+/*! DAP - DAP Reset
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
+#define CMC_SRIE_DAP(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_DAP_SHIFT)) & CMC_SRIE_DAP_MASK)
+
+#define CMC_SRIE_LPACK_MASK                      (0x800U)
+#define CMC_SRIE_LPACK_SHIFT                     (11U)
+/*! LPACK - Low Power Acknowledge Timeout Reset
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
+#define CMC_SRIE_LPACK(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LPACK_SHIFT)) & CMC_SRIE_LPACK_MASK)
+
+#define CMC_SRIE_SCG_MASK                        (0x1000U)
+#define CMC_SRIE_SCG_SHIFT                       (12U)
+/*! SCG - System Clock Generation Reset
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
+#define CMC_SRIE_SCG(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SCG_SHIFT)) & CMC_SRIE_SCG_MASK)
+
+#define CMC_SRIE_WWDT0_MASK                      (0x2000U)
+#define CMC_SRIE_WWDT0_SHIFT                     (13U)
+/*! WWDT0 - Windowed Watchdog 0 Reset
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
+#define CMC_SRIE_WWDT0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WWDT0_SHIFT)) & CMC_SRIE_WWDT0_MASK)
+
+#define CMC_SRIE_SW_MASK                         (0x4000U)
+#define CMC_SRIE_SW_SHIFT                        (14U)
+/*! SW - Software Reset
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
+#define CMC_SRIE_SW(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SW_SHIFT)) & CMC_SRIE_SW_MASK)
+
+#define CMC_SRIE_LOCKUP_MASK                     (0x8000U)
+#define CMC_SRIE_LOCKUP_SHIFT                    (15U)
+/*! LOCKUP - Lockup Reset
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
+#define CMC_SRIE_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LOCKUP_SHIFT)) & CMC_SRIE_LOCKUP_MASK)
+
+#define CMC_SRIE_CDOG0_MASK                      (0x4000000U)
+#define CMC_SRIE_CDOG0_SHIFT                     (26U)
+/*! CDOG0 - Code Watchdog 0 Reset
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
+#define CMC_SRIE_CDOG0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CDOG0_SHIFT)) & CMC_SRIE_CDOG0_MASK)
+/*! @} */
+
+/*! @name SRIF - System Reset Interrupt Flag */
+/*! @{ */
+
+#define CMC_SRIF_PIN_MASK                        (0x100U)
+#define CMC_SRIF_PIN_SHIFT                       (8U)
+/*! PIN - Pin Reset
+ *  0b0..Reset source not pending
+ *  0b1..Reset source pending
+ */
+#define CMC_SRIF_PIN(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_PIN_SHIFT)) & CMC_SRIF_PIN_MASK)
+
+#define CMC_SRIF_DAP_MASK                        (0x200U)
+#define CMC_SRIF_DAP_SHIFT                       (9U)
+/*! DAP - DAP Reset
+ *  0b0..Reset source not pending
+ *  0b1..Reset source pending
+ */
+#define CMC_SRIF_DAP(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_DAP_SHIFT)) & CMC_SRIF_DAP_MASK)
+
+#define CMC_SRIF_LPACK_MASK                      (0x800U)
+#define CMC_SRIF_LPACK_SHIFT                     (11U)
+/*! LPACK - Low Power Acknowledge Timeout Reset
+ *  0b0..Reset source not pending
+ *  0b1..Reset source pending
+ */
+#define CMC_SRIF_LPACK(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LPACK_SHIFT)) & CMC_SRIF_LPACK_MASK)
+
+#define CMC_SRIF_WWDT0_MASK                      (0x2000U)
+#define CMC_SRIF_WWDT0_SHIFT                     (13U)
+/*! WWDT0 - Windowed Watchdog 0 Reset
+ *  0b0..Reset source not pending
+ *  0b1..Reset source pending
+ */
+#define CMC_SRIF_WWDT0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WWDT0_SHIFT)) & CMC_SRIF_WWDT0_MASK)
+
+#define CMC_SRIF_SW_MASK                         (0x4000U)
+#define CMC_SRIF_SW_SHIFT                        (14U)
+/*! SW - Software Reset
+ *  0b0..Reset source not pending
+ *  0b1..Reset source pending
+ */
+#define CMC_SRIF_SW(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_SW_SHIFT)) & CMC_SRIF_SW_MASK)
+
+#define CMC_SRIF_LOCKUP_MASK                     (0x8000U)
+#define CMC_SRIF_LOCKUP_SHIFT                    (15U)
+/*! LOCKUP - Lockup Reset
+ *  0b0..Reset source not pending
+ *  0b1..Reset source pending
+ */
+#define CMC_SRIF_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LOCKUP_SHIFT)) & CMC_SRIF_LOCKUP_MASK)
+
+#define CMC_SRIF_CDOG0_MASK                      (0x4000000U)
+#define CMC_SRIF_CDOG0_SHIFT                     (26U)
+/*! CDOG0 - Code Watchdog 0 Reset
+ *  0b0..Reset source not pending
+ *  0b1..Reset source pending
+ */
+#define CMC_SRIF_CDOG0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CDOG0_SHIFT)) & CMC_SRIF_CDOG0_MASK)
+/*! @} */
+
+/*! @name MR - Mode */
+/*! @{ */
+
+#define CMC_MR_ISPMODE_n_MASK                    (0x1U)
+#define CMC_MR_ISPMODE_n_SHIFT                   (0U)
+/*! ISPMODE_n - In System Programming Mode */
+#define CMC_MR_ISPMODE_n(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_MR_ISPMODE_n_SHIFT)) & CMC_MR_ISPMODE_n_MASK)
+/*! @} */
+
+/*! @name FM - Force Mode */
+/*! @{ */
+
+#define CMC_FM_FORCECFG_MASK                     (0x1U)
+#define CMC_FM_FORCECFG_SHIFT                    (0U)
+/*! FORCECFG - Boot Configuration
+ *  0b0..No effect
+ *  0b1..Asserts
+ */
+#define CMC_FM_FORCECFG(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_FM_FORCECFG_SHIFT)) & CMC_FM_FORCECFG_MASK)
+/*! @} */
+
+/*! @name FLASHCR - Flash Control */
+/*! @{ */
+
+#define CMC_FLASHCR_FLASHDIS_MASK                (0x1U)
+#define CMC_FLASHCR_FLASHDIS_SHIFT               (0U)
+/*! FLASHDIS - Flash Disable
+ *  0b0..No effect
+ *  0b1..Flash memory is disabled
+ */
+#define CMC_FLASHCR_FLASHDIS(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDIS_SHIFT)) & CMC_FLASHCR_FLASHDIS_MASK)
+
+#define CMC_FLASHCR_FLASHDOZE_MASK               (0x2U)
+#define CMC_FLASHCR_FLASHDOZE_SHIFT              (1U)
+/*! FLASHDOZE - Flash Doze
+ *  0b0..No effect
+ *  0b1..Flash memory is disabled when core is sleeping (CKMODE > 0)
+ */
+#define CMC_FLASHCR_FLASHDOZE(x)                 (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDOZE_SHIFT)) & CMC_FLASHCR_FLASHDOZE_MASK)
+
+#define CMC_FLASHCR_FLASHWAKE_MASK               (0x4U)
+#define CMC_FLASHCR_FLASHWAKE_SHIFT              (2U)
+/*! FLASHWAKE - Flash Wake
+ *  0b0..No effect
+ *  0b1..Flash memory is not disabled during flash memory accesses
+ */
+#define CMC_FLASHCR_FLASHWAKE(x)                 (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHWAKE_SHIFT)) & CMC_FLASHCR_FLASHWAKE_MASK)
+/*! @} */
+
+/*! @name CORECTL - Core Control */
+/*! @{ */
+
+#define CMC_CORECTL_NPIE_MASK                    (0x1U)
+#define CMC_CORECTL_NPIE_SHIFT                   (0U)
+/*! NPIE - Non-maskable Pin Interrupt Enable
+ *  0b0..Disables
+ *  0b1..Enables
+ */
+#define CMC_CORECTL_NPIE(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_CORECTL_NPIE_SHIFT)) & CMC_CORECTL_NPIE_MASK)
+/*! @} */
+
+/*! @name DBGCTL - Debug Control */
+/*! @{ */
+
+#define CMC_DBGCTL_SOD_MASK                      (0x1U)
+#define CMC_DBGCTL_SOD_SHIFT                     (0U)
+/*! SOD - Sleep Or Debug
+ *  0b0..Remains enabled
+ *  0b1..Disabled
+ */
+#define CMC_DBGCTL_SOD(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_DBGCTL_SOD_SHIFT)) & CMC_DBGCTL_SOD_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CMC_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group CMC_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_CMC_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CRC.h
new file mode 100644
index 0000000000..7050db6667
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CRC.h
@@ -0,0 +1,404 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for CRC
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_CRC.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for CRC
+ *
+ * CMSIS Peripheral Access Layer for CRC
+ */
+
+#if !defined(PERI_CRC_H_)
+#define PERI_CRC_H_                              /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint8_t DATALL;                             /**< CRC_DATALL register, offset: 0x0 */
+      __IO uint8_t DATALU;                             /**< CRC_DATALU register, offset: 0x1 */
+      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register, offset: 0x2 */
+      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register, offset: 0x3 */
+    } ACCESS8BIT;
+    struct {                                         /* offset: 0x0 */
+      __IO uint16_t DATAL;                             /**< CRC_DATAL register, offset: 0x0 */
+      __IO uint16_t DATAH;                             /**< CRC_DATAH register, offset: 0x2 */
+    } ACCESS16BIT;
+    __IO uint32_t DATA;                              /**< Data, offset: 0x0 */
+  };
+  union {                                          /* offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register, offset: 0x4 */
+      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register, offset: 0x5 */
+      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register, offset: 0x6 */
+      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register, offset: 0x7 */
+    } GPOLY_ACCESS8BIT;
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register, offset: 0x4 */
+      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register, offset: 0x6 */
+    } GPOLY_ACCESS16BIT;
+    __IO uint32_t GPOLY;                             /**< Polynomial, offset: 0x4 */
+  };
+  union {                                          /* offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+           uint8_t RESERVED_0[3];
+      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register, offset: 0xB */
+    } CTRL_ACCESS8BIT;
+    __IO uint32_t CTRL;                              /**< Control, offset: 0x8 */
+  };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name DATALL - CRC_DATALL register */
+/*! @{ */
+
+#define CRC_DATALL_DATALL_MASK                   (0xFFU)
+#define CRC_DATALL_DATALL_SHIFT                  (0U)
+#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
+/*! @} */
+
+/*! @name DATALU - CRC_DATALU register */
+/*! @{ */
+
+#define CRC_DATALU_DATALU_MASK                   (0xFFU)
+#define CRC_DATALU_DATALU_SHIFT                  (0U)
+#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
+/*! @} */
+
+/*! @name DATAHL - CRC_DATAHL register */
+/*! @{ */
+
+#define CRC_DATAHL_DATAHL_MASK                   (0xFFU)
+#define CRC_DATAHL_DATAHL_SHIFT                  (0U)
+#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
+/*! @} */
+
+/*! @name DATAHU - CRC_DATAHU register */
+/*! @{ */
+
+#define CRC_DATAHU_DATAHU_MASK                   (0xFFU)
+#define CRC_DATAHU_DATAHU_SHIFT                  (0U)
+#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
+/*! @} */
+
+/*! @name DATAL - CRC_DATAL register */
+/*! @{ */
+
+#define CRC_DATAL_DATAL_MASK                     (0xFFFFU)
+#define CRC_DATAL_DATAL_SHIFT                    (0U)
+#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
+/*! @} */
+
+/*! @name DATAH - CRC_DATAH register */
+/*! @{ */
+
+#define CRC_DATAH_DATAH_MASK                     (0xFFFFU)
+#define CRC_DATAH_DATAH_SHIFT                    (0U)
+#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
+/*! @} */
+
+/*! @name DATA - Data */
+/*! @{ */
+
+#define CRC_DATA_LL_MASK                         (0xFFU)
+#define CRC_DATA_LL_SHIFT                        (0U)
+/*! LL - Lower Part of Low Byte */
+#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
+
+#define CRC_DATA_LU_MASK                         (0xFF00U)
+#define CRC_DATA_LU_SHIFT                        (8U)
+/*! LU - Upper Part of Low Byte */
+#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
+
+#define CRC_DATA_HL_MASK                         (0xFF0000U)
+#define CRC_DATA_HL_SHIFT                        (16U)
+/*! HL - Lower Part of High Byte */
+#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
+
+#define CRC_DATA_HU_MASK                         (0xFF000000U)
+#define CRC_DATA_HU_SHIFT                        (24U)
+/*! HU - Upper Part of High Byte */
+#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
+/*! @} */
+
+/*! @name GPOLYLL - CRC_GPOLYLL register */
+/*! @{ */
+
+#define CRC_GPOLYLL_GPOLYLL_MASK                 (0xFFU)
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                (0U)
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
+/*! @} */
+
+/*! @name GPOLYLU - CRC_GPOLYLU register */
+/*! @{ */
+
+#define CRC_GPOLYLU_GPOLYLU_MASK                 (0xFFU)
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                (0U)
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
+/*! @} */
+
+/*! @name GPOLYHL - CRC_GPOLYHL register */
+/*! @{ */
+
+#define CRC_GPOLYHL_GPOLYHL_MASK                 (0xFFU)
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                (0U)
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
+/*! @} */
+
+/*! @name GPOLYHU - CRC_GPOLYHU register */
+/*! @{ */
+
+#define CRC_GPOLYHU_GPOLYHU_MASK                 (0xFFU)
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                (0U)
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
+/*! @} */
+
+/*! @name GPOLYL - CRC_GPOLYL register */
+/*! @{ */
+
+#define CRC_GPOLYL_GPOLYL_MASK                   (0xFFFFU)
+#define CRC_GPOLYL_GPOLYL_SHIFT                  (0U)
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
+/*! @} */
+
+/*! @name GPOLYH - CRC_GPOLYH register */
+/*! @{ */
+
+#define CRC_GPOLYH_GPOLYH_MASK                   (0xFFFFU)
+#define CRC_GPOLYH_GPOLYH_SHIFT                  (0U)
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
+/*! @} */
+
+/*! @name GPOLY - Polynomial */
+/*! @{ */
+
+#define CRC_GPOLY_LOW_MASK                       (0xFFFFU)
+#define CRC_GPOLY_LOW_SHIFT                      (0U)
+/*! LOW - Low Half-Word */
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
+
+#define CRC_GPOLY_HIGH_MASK                      (0xFFFF0000U)
+#define CRC_GPOLY_HIGH_SHIFT                     (16U)
+/*! HIGH - High Half-Word */
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
+/*! @} */
+
+/*! @name CTRLHU - CRC_CTRLHU register */
+/*! @{ */
+
+#define CRC_CTRLHU_TCRC_MASK                     (0x1U)
+#define CRC_CTRLHU_TCRC_SHIFT                    (0U)
+/*! TCRC - TCRC
+ *  0b0..16 bits
+ *  0b1..32 bits
+ */
+#define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
+
+#define CRC_CTRLHU_WAS_MASK                      (0x2U)
+#define CRC_CTRLHU_WAS_SHIFT                     (1U)
+/*! WAS - Write as Seed
+ *  0b0..Data values
+ *  0b1..Seed values
+ */
+#define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
+
+#define CRC_CTRLHU_FXOR_MASK                     (0x4U)
+#define CRC_CTRLHU_FXOR_SHIFT                    (2U)
+/*! FXOR - Complement Read of CRC Data Register
+ *  0b0..Disables XOR on reading data.
+ *  0b1..Inverts or complements the read value of the CRC Data.
+ */
+#define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
+
+#define CRC_CTRLHU_TOTR_MASK                     (0x30U)
+#define CRC_CTRLHU_TOTR_SHIFT                    (4U)
+/*! TOTR - Transpose Type for Read
+ *  0b00..No transposition
+ *  0b01..Bits in bytes are transposed, but bytes are not transposed.
+ *  0b10..Both bits in bytes and bytes are transposed.
+ *  0b11..Only bytes are transposed, no bits in a byte are transposed.
+ */
+#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
+
+#define CRC_CTRLHU_TOT_MASK                      (0xC0U)
+#define CRC_CTRLHU_TOT_SHIFT                     (6U)
+/*! TOT - Transpose Type for Write
+ *  0b00..No transposition
+ *  0b01..Bits in bytes are transposed, but bytes are not transposed.
+ *  0b10..Both bits in bytes and bytes are transposed.
+ *  0b11..Only bytes are transposed, no bits in a byte are transposed.
+ */
+#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
+/*! @} */
+
+/*! @name CTRL - Control */
+/*! @{ */
+
+#define CRC_CTRL_TCRC_MASK                       (0x1000000U)
+#define CRC_CTRL_TCRC_SHIFT                      (24U)
+/*! TCRC - TCRC
+ *  0b0..16 bits
+ *  0b1..32 bits
+ */
+#define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
+
+#define CRC_CTRL_WAS_MASK                        (0x2000000U)
+#define CRC_CTRL_WAS_SHIFT                       (25U)
+/*! WAS - Write as Seed
+ *  0b0..Data values
+ *  0b1..Seed values
+ */
+#define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
+
+#define CRC_CTRL_FXOR_MASK                       (0x4000000U)
+#define CRC_CTRL_FXOR_SHIFT                      (26U)
+/*! FXOR - Complement Read of CRC Data Register
+ *  0b0..Disables XOR on reading data.
+ *  0b1..Inverts or complements the read value of the CRC Data.
+ */
+#define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
+
+#define CRC_CTRL_TOTR_MASK                       (0x30000000U)
+#define CRC_CTRL_TOTR_SHIFT                      (28U)
+/*! TOTR - Transpose Type for Read
+ *  0b00..No transposition
+ *  0b01..Bits in bytes are transposed, but bytes are not transposed.
+ *  0b10..Both bits in bytes and bytes are transposed.
+ *  0b11..Only bytes are transposed, no bits in a byte are transposed.
+ */
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
+
+#define CRC_CTRL_TOT_MASK                        (0xC0000000U)
+#define CRC_CTRL_TOT_SHIFT                       (30U)
+/*! TOT - Transpose Type for Write
+ *  0b00..No transposition
+ *  0b01..Bits in bytes are transposed, but bytes are not transposed.
+ *  0b10..Both bits in bytes and bytes are transposed.
+ *  0b11..Only bytes are transposed, no bits in a byte are transposed.
+ */
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_CRC_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CTIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CTIMER.h
new file mode 100644
index 0000000000..6a59e86ec5
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CTIMER.h
@@ -0,0 +1,681 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for CTIMER
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_CTIMER.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for CTIMER
+ *
+ * CMSIS Peripheral Access Layer for CTIMER
+ */
+
+#if !defined(PERI_CTIMER_H_)
+#define PERI_CTIMER_H_                           /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
+ * @{
+ */
+
+/** CTIMER - Size of Registers Arrays */
+#define CTIMER_MR_COUNT                           4u
+#define CTIMER_CR_COUNT                           4u
+#define CTIMER_MSR_COUNT                          4u
+
+/** CTIMER - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t IR;                                /**< Interrupt, offset: 0x0 */
+  __IO uint32_t TCR;                               /**< Timer Control, offset: 0x4 */
+  __IO uint32_t TC;                                /**< Timer Counter, offset: 0x8 */
+  __IO uint32_t PR;                                /**< Prescale, offset: 0xC */
+  __IO uint32_t PC;                                /**< Prescale Counter, offset: 0x10 */
+  __IO uint32_t MCR;                               /**< Match Control, offset: 0x14 */
+  __IO uint32_t MR[CTIMER_MR_COUNT];               /**< Match, array offset: 0x18, array step: 0x4 */
+  __IO uint32_t CCR;                               /**< Capture Control, offset: 0x28 */
+  __I  uint32_t CR[CTIMER_CR_COUNT];               /**< Capture, array offset: 0x2C, array step: 0x4 */
+  __IO uint32_t EMR;                               /**< External Match, offset: 0x3C */
+       uint8_t RESERVED_0[48];
+  __IO uint32_t CTCR;                              /**< Count Control, offset: 0x70 */
+  __IO uint32_t PWMC;                              /**< PWM Control, offset: 0x74 */
+  __IO uint32_t MSR[CTIMER_MSR_COUNT];             /**< Match Shadow, array offset: 0x78, array step: 0x4 */
+} CTIMER_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
+ * @{
+ */
+
+/*! @name IR - Interrupt */
+/*! @{ */
+
+#define CTIMER_IR_MR0INT_MASK                    (0x1U)
+#define CTIMER_IR_MR0INT_SHIFT                   (0U)
+/*! MR0INT - Interrupt Flag for Match Channel 0 Event */
+#define CTIMER_IR_MR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
+
+#define CTIMER_IR_MR1INT_MASK                    (0x2U)
+#define CTIMER_IR_MR1INT_SHIFT                   (1U)
+/*! MR1INT - Interrupt Flag for Match Channel 1 Event */
+#define CTIMER_IR_MR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
+
+#define CTIMER_IR_MR2INT_MASK                    (0x4U)
+#define CTIMER_IR_MR2INT_SHIFT                   (2U)
+/*! MR2INT - Interrupt Flag for Match Channel 2 Event */
+#define CTIMER_IR_MR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
+
+#define CTIMER_IR_MR3INT_MASK                    (0x8U)
+#define CTIMER_IR_MR3INT_SHIFT                   (3U)
+/*! MR3INT - Interrupt Flag for Match Channel 3 Event */
+#define CTIMER_IR_MR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
+
+#define CTIMER_IR_CR0INT_MASK                    (0x10U)
+#define CTIMER_IR_CR0INT_SHIFT                   (4U)
+/*! CR0INT - Interrupt Flag for Capture Channel 0 Event */
+#define CTIMER_IR_CR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
+
+#define CTIMER_IR_CR1INT_MASK                    (0x20U)
+#define CTIMER_IR_CR1INT_SHIFT                   (5U)
+/*! CR1INT - Interrupt Flag for Capture Channel 1 Event */
+#define CTIMER_IR_CR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
+
+#define CTIMER_IR_CR2INT_MASK                    (0x40U)
+#define CTIMER_IR_CR2INT_SHIFT                   (6U)
+/*! CR2INT - Interrupt Flag for Capture Channel 2 Event */
+#define CTIMER_IR_CR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
+
+#define CTIMER_IR_CR3INT_MASK                    (0x80U)
+#define CTIMER_IR_CR3INT_SHIFT                   (7U)
+/*! CR3INT - Interrupt Flag for Capture Channel 3 Event */
+#define CTIMER_IR_CR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
+/*! @} */
+
+/*! @name TCR - Timer Control */
+/*! @{ */
+
+#define CTIMER_TCR_CEN_MASK                      (0x1U)
+#define CTIMER_TCR_CEN_SHIFT                     (0U)
+/*! CEN - Counter Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CTIMER_TCR_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
+
+#define CTIMER_TCR_CRST_MASK                     (0x2U)
+#define CTIMER_TCR_CRST_SHIFT                    (1U)
+/*! CRST - Counter Reset Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CTIMER_TCR_CRST(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
+
+#define CTIMER_TCR_AGCEN_MASK                    (0x10U)
+#define CTIMER_TCR_AGCEN_SHIFT                   (4U)
+/*! AGCEN - Allow Global Count Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CTIMER_TCR_AGCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_AGCEN_SHIFT)) & CTIMER_TCR_AGCEN_MASK)
+
+#define CTIMER_TCR_ATCEN_MASK                    (0x20U)
+#define CTIMER_TCR_ATCEN_SHIFT                   (5U)
+/*! ATCEN - Allow Trigger Count Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CTIMER_TCR_ATCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_ATCEN_SHIFT)) & CTIMER_TCR_ATCEN_MASK)
+/*! @} */
+
+/*! @name TC - Timer Counter */
+/*! @{ */
+
+#define CTIMER_TC_TCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_TC_TCVAL_SHIFT                    (0U)
+/*! TCVAL - Timer Counter Value */
+#define CTIMER_TC_TCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
+/*! @} */
+
+/*! @name PR - Prescale */
+/*! @{ */
+
+#define CTIMER_PR_PRVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PR_PRVAL_SHIFT                    (0U)
+/*! PRVAL - Prescale Reload Value */
+#define CTIMER_PR_PRVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
+/*! @} */
+
+/*! @name PC - Prescale Counter */
+/*! @{ */
+
+#define CTIMER_PC_PCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PC_PCVAL_SHIFT                    (0U)
+/*! PCVAL - Prescale Counter Value */
+#define CTIMER_PC_PCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
+/*! @} */
+
+/*! @name MCR - Match Control */
+/*! @{ */
+
+#define CTIMER_MCR_MR0I_MASK                     (0x1U)
+#define CTIMER_MCR_MR0I_SHIFT                    (0U)
+/*! MR0I - Interrupt on MR0
+ *  0b0..Does not generate
+ *  0b1..Generates
+ */
+#define CTIMER_MCR_MR0I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
+
+#define CTIMER_MCR_MR0R_MASK                     (0x2U)
+#define CTIMER_MCR_MR0R_SHIFT                    (1U)
+/*! MR0R - Reset on MR0
+ *  0b0..Does not reset
+ *  0b1..Resets
+ */
+#define CTIMER_MCR_MR0R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
+
+#define CTIMER_MCR_MR0S_MASK                     (0x4U)
+#define CTIMER_MCR_MR0S_SHIFT                    (2U)
+/*! MR0S - Stop on MR0
+ *  0b0..Does not stop
+ *  0b1..Stops
+ */
+#define CTIMER_MCR_MR0S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
+
+#define CTIMER_MCR_MR1I_MASK                     (0x8U)
+#define CTIMER_MCR_MR1I_SHIFT                    (3U)
+/*! MR1I - Interrupt on MR1
+ *  0b0..Does not generate
+ *  0b1..Generates
+ */
+#define CTIMER_MCR_MR1I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
+
+#define CTIMER_MCR_MR1R_MASK                     (0x10U)
+#define CTIMER_MCR_MR1R_SHIFT                    (4U)
+/*! MR1R - Reset on MR1
+ *  0b0..Does not reset
+ *  0b1..Resets
+ */
+#define CTIMER_MCR_MR1R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
+
+#define CTIMER_MCR_MR1S_MASK                     (0x20U)
+#define CTIMER_MCR_MR1S_SHIFT                    (5U)
+/*! MR1S - Stop on MR1
+ *  0b0..Does not stop
+ *  0b1..Stops
+ */
+#define CTIMER_MCR_MR1S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
+
+#define CTIMER_MCR_MR2I_MASK                     (0x40U)
+#define CTIMER_MCR_MR2I_SHIFT                    (6U)
+/*! MR2I - Interrupt on MR2
+ *  0b0..Does not generate
+ *  0b1..Generates
+ */
+#define CTIMER_MCR_MR2I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
+
+#define CTIMER_MCR_MR2R_MASK                     (0x80U)
+#define CTIMER_MCR_MR2R_SHIFT                    (7U)
+/*! MR2R - Reset on MR2
+ *  0b0..Does not reset
+ *  0b1..Resets
+ */
+#define CTIMER_MCR_MR2R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
+
+#define CTIMER_MCR_MR2S_MASK                     (0x100U)
+#define CTIMER_MCR_MR2S_SHIFT                    (8U)
+/*! MR2S - Stop on MR2
+ *  0b0..Does not stop
+ *  0b1..Stops
+ */
+#define CTIMER_MCR_MR2S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
+
+#define CTIMER_MCR_MR3I_MASK                     (0x200U)
+#define CTIMER_MCR_MR3I_SHIFT                    (9U)
+/*! MR3I - Interrupt on MR3
+ *  0b0..Does not generate
+ *  0b1..Generates
+ */
+#define CTIMER_MCR_MR3I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
+
+#define CTIMER_MCR_MR3R_MASK                     (0x400U)
+#define CTIMER_MCR_MR3R_SHIFT                    (10U)
+/*! MR3R - Reset on MR3
+ *  0b0..Does not reset
+ *  0b1..Resets
+ */
+#define CTIMER_MCR_MR3R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
+
+#define CTIMER_MCR_MR3S_MASK                     (0x800U)
+#define CTIMER_MCR_MR3S_SHIFT                    (11U)
+/*! MR3S - Stop on MR3
+ *  0b0..Does not stop
+ *  0b1..Stops
+ */
+#define CTIMER_MCR_MR3S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
+
+#define CTIMER_MCR_MR0RL_MASK                    (0x1000000U)
+#define CTIMER_MCR_MR0RL_SHIFT                   (24U)
+/*! MR0RL - Reload MR
+ *  0b0..Does not reload
+ *  0b1..Reloads
+ */
+#define CTIMER_MCR_MR0RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
+
+#define CTIMER_MCR_MR1RL_MASK                    (0x2000000U)
+#define CTIMER_MCR_MR1RL_SHIFT                   (25U)
+/*! MR1RL - Reload MR
+ *  0b0..Does not reload
+ *  0b1..Reloads
+ */
+#define CTIMER_MCR_MR1RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
+
+#define CTIMER_MCR_MR2RL_MASK                    (0x4000000U)
+#define CTIMER_MCR_MR2RL_SHIFT                   (26U)
+/*! MR2RL - Reload MR
+ *  0b0..Does not reload
+ *  0b1..Reloads
+ */
+#define CTIMER_MCR_MR2RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
+
+#define CTIMER_MCR_MR3RL_MASK                    (0x8000000U)
+#define CTIMER_MCR_MR3RL_SHIFT                   (27U)
+/*! MR3RL - Reload MR
+ *  0b0..Does not reload
+ *  0b1..Reloads
+ */
+#define CTIMER_MCR_MR3RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
+/*! @} */
+
+/*! @name MR - Match */
+/*! @{ */
+
+#define CTIMER_MR_MATCH_MASK                     (0xFFFFFFFFU)
+#define CTIMER_MR_MATCH_SHIFT                    (0U)
+/*! MATCH - Timer Counter Match Value */
+#define CTIMER_MR_MATCH(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
+/*! @} */
+
+/*! @name CCR - Capture Control */
+/*! @{ */
+
+#define CTIMER_CCR_CAP0RE_MASK                   (0x1U)
+#define CTIMER_CCR_CAP0RE_SHIFT                  (0U)
+/*! CAP0RE - Rising Edge of Capture Channel 0
+ *  0b0..Does not load
+ *  0b1..Loads
+ */
+#define CTIMER_CCR_CAP0RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
+
+#define CTIMER_CCR_CAP0FE_MASK                   (0x2U)
+#define CTIMER_CCR_CAP0FE_SHIFT                  (1U)
+/*! CAP0FE - Falling Edge of Capture Channel 0
+ *  0b0..Does not load
+ *  0b1..Loads
+ */
+#define CTIMER_CCR_CAP0FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
+
+#define CTIMER_CCR_CAP0I_MASK                    (0x4U)
+#define CTIMER_CCR_CAP0I_SHIFT                   (2U)
+/*! CAP0I - Generate Interrupt on Channel 0 Capture Event
+ *  0b0..Does not generate
+ *  0b1..Generates
+ */
+#define CTIMER_CCR_CAP0I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
+
+#define CTIMER_CCR_CAP1RE_MASK                   (0x8U)
+#define CTIMER_CCR_CAP1RE_SHIFT                  (3U)
+/*! CAP1RE - Rising Edge of Capture Channel 1
+ *  0b0..Does not load
+ *  0b1..Loads
+ */
+#define CTIMER_CCR_CAP1RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
+
+#define CTIMER_CCR_CAP1FE_MASK                   (0x10U)
+#define CTIMER_CCR_CAP1FE_SHIFT                  (4U)
+/*! CAP1FE - Falling Edge of Capture Channel 1
+ *  0b0..Does not load
+ *  0b1..Loads
+ */
+#define CTIMER_CCR_CAP1FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
+
+#define CTIMER_CCR_CAP1I_MASK                    (0x20U)
+#define CTIMER_CCR_CAP1I_SHIFT                   (5U)
+/*! CAP1I - Generate Interrupt on Channel 1 Capture Event
+ *  0b0..Does not generates
+ *  0b1..Generates
+ */
+#define CTIMER_CCR_CAP1I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
+
+#define CTIMER_CCR_CAP2RE_MASK                   (0x40U)
+#define CTIMER_CCR_CAP2RE_SHIFT                  (6U)
+/*! CAP2RE - Rising Edge of Capture Channel 2
+ *  0b0..Does not load
+ *  0b1..Loads
+ */
+#define CTIMER_CCR_CAP2RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
+
+#define CTIMER_CCR_CAP2FE_MASK                   (0x80U)
+#define CTIMER_CCR_CAP2FE_SHIFT                  (7U)
+/*! CAP2FE - Falling Edge of Capture Channel 2
+ *  0b0..Does not load
+ *  0b1..Loads
+ */
+#define CTIMER_CCR_CAP2FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
+
+#define CTIMER_CCR_CAP2I_MASK                    (0x100U)
+#define CTIMER_CCR_CAP2I_SHIFT                   (8U)
+/*! CAP2I - Generate Interrupt on Channel 2 Capture Event
+ *  0b0..Does not generate
+ *  0b1..Generates
+ */
+#define CTIMER_CCR_CAP2I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
+
+#define CTIMER_CCR_CAP3RE_MASK                   (0x200U)
+#define CTIMER_CCR_CAP3RE_SHIFT                  (9U)
+/*! CAP3RE - Rising Edge of Capture Channel 3
+ *  0b0..Does not load
+ *  0b1..Loads
+ */
+#define CTIMER_CCR_CAP3RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
+
+#define CTIMER_CCR_CAP3FE_MASK                   (0x400U)
+#define CTIMER_CCR_CAP3FE_SHIFT                  (10U)
+/*! CAP3FE - Falling Edge of Capture Channel 3
+ *  0b0..Does not load
+ *  0b1..Loads
+ */
+#define CTIMER_CCR_CAP3FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
+
+#define CTIMER_CCR_CAP3I_MASK                    (0x800U)
+#define CTIMER_CCR_CAP3I_SHIFT                   (11U)
+/*! CAP3I - Generate Interrupt on Channel 3 Capture Event
+ *  0b0..Does not generate
+ *  0b1..Generates
+ */
+#define CTIMER_CCR_CAP3I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
+/*! @} */
+
+/*! @name CR - Capture */
+/*! @{ */
+
+#define CTIMER_CR_CAP_MASK                       (0xFFFFFFFFU)
+#define CTIMER_CR_CAP_SHIFT                      (0U)
+/*! CAP - Timer Counter Capture Value */
+#define CTIMER_CR_CAP(x)                         (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
+/*! @} */
+
+/*! @name EMR - External Match */
+/*! @{ */
+
+#define CTIMER_EMR_EM0_MASK                      (0x1U)
+#define CTIMER_EMR_EM0_SHIFT                     (0U)
+/*! EM0 - External Match 0
+ *  0b0..Low
+ *  0b1..High
+ */
+#define CTIMER_EMR_EM0(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
+
+#define CTIMER_EMR_EM1_MASK                      (0x2U)
+#define CTIMER_EMR_EM1_SHIFT                     (1U)
+/*! EM1 - External Match 1
+ *  0b0..Low
+ *  0b1..High
+ */
+#define CTIMER_EMR_EM1(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
+
+#define CTIMER_EMR_EM2_MASK                      (0x4U)
+#define CTIMER_EMR_EM2_SHIFT                     (2U)
+/*! EM2 - External Match 2
+ *  0b0..Low
+ *  0b1..High
+ */
+#define CTIMER_EMR_EM2(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
+
+#define CTIMER_EMR_EM3_MASK                      (0x8U)
+#define CTIMER_EMR_EM3_SHIFT                     (3U)
+/*! EM3 - External Match 3
+ *  0b0..Low
+ *  0b1..High
+ */
+#define CTIMER_EMR_EM3(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
+
+#define CTIMER_EMR_EMC0_MASK                     (0x30U)
+#define CTIMER_EMR_EMC0_SHIFT                    (4U)
+/*! EMC0 - External Match Control 0
+ *  0b00..Does nothing
+ *  0b01..Goes low
+ *  0b10..Goes high
+ *  0b11..Toggles
+ */
+#define CTIMER_EMR_EMC0(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
+
+#define CTIMER_EMR_EMC1_MASK                     (0xC0U)
+#define CTIMER_EMR_EMC1_SHIFT                    (6U)
+/*! EMC1 - External Match Control 1
+ *  0b00..Does nothing
+ *  0b01..Goes low
+ *  0b10..Goes high
+ *  0b11..Toggles
+ */
+#define CTIMER_EMR_EMC1(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
+
+#define CTIMER_EMR_EMC2_MASK                     (0x300U)
+#define CTIMER_EMR_EMC2_SHIFT                    (8U)
+/*! EMC2 - External Match Control 2
+ *  0b00..Does nothing
+ *  0b01..Goes low
+ *  0b10..Goes high
+ *  0b11..Toggles
+ */
+#define CTIMER_EMR_EMC2(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
+
+#define CTIMER_EMR_EMC3_MASK                     (0xC00U)
+#define CTIMER_EMR_EMC3_SHIFT                    (10U)
+/*! EMC3 - External Match Control 3
+ *  0b00..Does nothing
+ *  0b01..Goes low
+ *  0b10..Goes high
+ *  0b11..Toggles
+ */
+#define CTIMER_EMR_EMC3(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
+/*! @} */
+
+/*! @name CTCR - Count Control */
+/*! @{ */
+
+#define CTIMER_CTCR_CTMODE_MASK                  (0x3U)
+#define CTIMER_CTCR_CTMODE_SHIFT                 (0U)
+/*! CTMODE - Counter Timer Mode
+ *  0b00..Timer mode
+ *  0b01..Counter mode rising edge
+ *  0b10..Counter mode falling edge
+ *  0b11..Counter mode dual edge
+ */
+#define CTIMER_CTCR_CTMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
+
+#define CTIMER_CTCR_CINSEL_MASK                  (0xCU)
+#define CTIMER_CTCR_CINSEL_SHIFT                 (2U)
+/*! CINSEL - Count Input Select
+ *  0b00..Channel 0, CAPn[0] for CTIMERn
+ *  0b01..Channel 1, CAPn[1] for CTIMERn
+ *  0b10..Channel 2, CAPn[2] for CTIMERn
+ *  0b11..Channel 3, CAPn[3] for CTIMERn
+ */
+#define CTIMER_CTCR_CINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
+
+#define CTIMER_CTCR_ENCC_MASK                    (0x10U)
+#define CTIMER_CTCR_ENCC_SHIFT                   (4U)
+/*! ENCC - Capture Channel Enable */
+#define CTIMER_CTCR_ENCC(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
+
+#define CTIMER_CTCR_SELCC_MASK                   (0xE0U)
+#define CTIMER_CTCR_SELCC_SHIFT                  (5U)
+/*! SELCC - Edge Select
+ *  0b000..Capture channel 0 rising edge
+ *  0b001..Capture channel 0 falling edge
+ *  0b010..Capture channel 1 rising edge
+ *  0b011..Capture channel 1 falling edge
+ *  0b100..Capture channel 2 rising edge
+ *  0b101..Capture channel 2 falling edge
+ *  0b110..Capture channel 3 rising edge
+ *  0b111..Capture channel 3 falling edge
+ */
+#define CTIMER_CTCR_SELCC(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
+/*! @} */
+
+/*! @name PWMC - PWM Control */
+/*! @{ */
+
+#define CTIMER_PWMC_PWMEN0_MASK                  (0x1U)
+#define CTIMER_PWMC_PWMEN0_SHIFT                 (0U)
+/*! PWMEN0 - PWM Mode Enable for Channel 0
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CTIMER_PWMC_PWMEN0(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
+
+#define CTIMER_PWMC_PWMEN1_MASK                  (0x2U)
+#define CTIMER_PWMC_PWMEN1_SHIFT                 (1U)
+/*! PWMEN1 - PWM Mode Enable for Channel 1
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CTIMER_PWMC_PWMEN1(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
+
+#define CTIMER_PWMC_PWMEN2_MASK                  (0x4U)
+#define CTIMER_PWMC_PWMEN2_SHIFT                 (2U)
+/*! PWMEN2 - PWM Mode Enable for Channel 2
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CTIMER_PWMC_PWMEN2(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
+
+#define CTIMER_PWMC_PWMEN3_MASK                  (0x8U)
+#define CTIMER_PWMC_PWMEN3_SHIFT                 (3U)
+/*! PWMEN3 - PWM Mode Enable for Channel 3
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CTIMER_PWMC_PWMEN3(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
+/*! @} */
+
+/*! @name MSR - Match Shadow */
+/*! @{ */
+
+#define CTIMER_MSR_MATCH_SHADOW_MASK             (0xFFFFFFFFU)
+#define CTIMER_MSR_MATCH_SHADOW_SHIFT            (0U)
+/*! MATCH_SHADOW - Timer Counter Match Shadow Value */
+#define CTIMER_MSR_MATCH_SHADOW(x)               (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_CTIMER_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_DEBUGMAILBOX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_DEBUGMAILBOX.h
new file mode 100644
index 0000000000..d1171b7705
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_DEBUGMAILBOX.h
@@ -0,0 +1,225 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for DEBUGMAILBOX
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_DEBUGMAILBOX.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for DEBUGMAILBOX
+ *
+ * CMSIS Peripheral Access Layer for DEBUGMAILBOX
+ */
+
+#if !defined(PERI_DEBUGMAILBOX_H_)
+#define PERI_DEBUGMAILBOX_H_                     /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- DEBUGMAILBOX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DEBUGMAILBOX_Peripheral_Access_Layer DEBUGMAILBOX Peripheral Access Layer
+ * @{
+ */
+
+/** DEBUGMAILBOX - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSW;                               /**< Command and Status Word, offset: 0x0 */
+  __IO uint32_t REQUEST;                           /**< Request Value, offset: 0x4 */
+  __IO uint32_t RETURN;                            /**< Return Value, offset: 0x8 */
+       uint8_t RESERVED_0[240];
+  __I  uint32_t ID;                                /**< Identification, offset: 0xFC */
+} DEBUGMAILBOX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DEBUGMAILBOX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DEBUGMAILBOX_Register_Masks DEBUGMAILBOX Register Masks
+ * @{
+ */
+
+/*! @name CSW - Command and Status Word */
+/*! @{ */
+
+#define DEBUGMAILBOX_CSW_RESYNCH_REQ_MASK        (0x1U)
+#define DEBUGMAILBOX_CSW_RESYNCH_REQ_SHIFT       (0U)
+/*! RESYNCH_REQ - Resynchronization Request
+ *  0b0..No request
+ *  0b1..Request for resynchronization
+ */
+#define DEBUGMAILBOX_CSW_RESYNCH_REQ(x)          (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DEBUGMAILBOX_CSW_RESYNCH_REQ_MASK)
+
+#define DEBUGMAILBOX_CSW_REQ_PENDING_MASK        (0x2U)
+#define DEBUGMAILBOX_CSW_REQ_PENDING_SHIFT       (1U)
+/*! REQ_PENDING - Request Pending
+ *  0b0..No request pending
+ *  0b1..Request for resynchronization pending
+ */
+#define DEBUGMAILBOX_CSW_REQ_PENDING(x)          (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DEBUGMAILBOX_CSW_REQ_PENDING_MASK)
+
+#define DEBUGMAILBOX_CSW_DBG_OR_ERR_MASK         (0x4U)
+#define DEBUGMAILBOX_CSW_DBG_OR_ERR_SHIFT        (2U)
+/*! DBG_OR_ERR - DBGMB Overrun Error
+ *  0b0..No overrun
+ *  0b1..Overrun occurred
+ */
+#define DEBUGMAILBOX_CSW_DBG_OR_ERR(x)           (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DEBUGMAILBOX_CSW_DBG_OR_ERR_MASK)
+
+#define DEBUGMAILBOX_CSW_AHB_OR_ERR_MASK         (0x8U)
+#define DEBUGMAILBOX_CSW_AHB_OR_ERR_SHIFT        (3U)
+/*! AHB_OR_ERR - AHB Overrun Error
+ *  0b0..No overrun
+ *  0b1..Overrun occurred
+ */
+#define DEBUGMAILBOX_CSW_AHB_OR_ERR(x)           (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DEBUGMAILBOX_CSW_AHB_OR_ERR_MASK)
+
+#define DEBUGMAILBOX_CSW_SOFT_RESET_MASK         (0x10U)
+#define DEBUGMAILBOX_CSW_SOFT_RESET_SHIFT        (4U)
+/*! SOFT_RESET - Soft Reset
+ *  0b0..No effect
+ *  0b1..Reset
+ */
+#define DEBUGMAILBOX_CSW_SOFT_RESET(x)           (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DEBUGMAILBOX_CSW_SOFT_RESET_MASK)
+
+#define DEBUGMAILBOX_CSW_CHIP_RESET_REQ_MASK     (0x20U)
+#define DEBUGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT    (5U)
+/*! CHIP_RESET_REQ - Chip Reset Request
+ *  0b0..No effect
+ *  0b1..Reset
+ */
+#define DEBUGMAILBOX_CSW_CHIP_RESET_REQ(x)       (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DEBUGMAILBOX_CSW_CHIP_RESET_REQ_MASK)
+/*! @} */
+
+/*! @name REQUEST - Request Value */
+/*! @{ */
+
+#define DEBUGMAILBOX_REQUEST_REQUEST_MASK        (0xFFFFFFFFU)
+#define DEBUGMAILBOX_REQUEST_REQUEST_SHIFT       (0U)
+/*! REQUEST - Request Value */
+#define DEBUGMAILBOX_REQUEST_REQUEST(x)          (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_REQUEST_REQUEST_SHIFT)) & DEBUGMAILBOX_REQUEST_REQUEST_MASK)
+/*! @} */
+
+/*! @name RETURN - Return Value */
+/*! @{ */
+
+#define DEBUGMAILBOX_RETURN_RET_MASK             (0xFFFFFFFFU)
+#define DEBUGMAILBOX_RETURN_RET_SHIFT            (0U)
+/*! RET - Return Value */
+#define DEBUGMAILBOX_RETURN_RET(x)               (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_RETURN_RET_SHIFT)) & DEBUGMAILBOX_RETURN_RET_MASK)
+/*! @} */
+
+/*! @name ID - Identification */
+/*! @{ */
+
+#define DEBUGMAILBOX_ID_ID_MASK                  (0xFFFFFFFFU)
+#define DEBUGMAILBOX_ID_ID_SHIFT                 (0U)
+/*! ID - Identification Value */
+#define DEBUGMAILBOX_ID_ID(x)                    (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_ID_ID_SHIFT)) & DEBUGMAILBOX_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group DEBUGMAILBOX_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group DEBUGMAILBOX_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_DEBUGMAILBOX_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_DMA.h
new file mode 100644
index 0000000000..86a643cbd5
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_DMA.h
@@ -0,0 +1,1035 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for DMA
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_DMA.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for DMA
+ *
+ * CMSIS Peripheral Access Layer for DMA
+ */
+
+#if !defined(PERI_DMA_H_)
+#define PERI_DMA_H_                              /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+#if !defined(DMA_REQUEST_SOURCE_T_)
+#define DMA_REQUEST_SOURCE_T_
+/*!
+ * @addtogroup dma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+    kDma0RequestDisabled            = 0U,          /**< Disabled */
+    kDma0RequestWUU0                = 1U,          /**< WUU Wake up event */
+    kDma0RequestMuxFlexCan0DmaRequest = 2U,        /**< CAN0 DMA request */
+    kDma0RequestLPI2C0Rx            = 11U,         /**< LPI2C0 Receive request */
+    kDma0RequestLPI2C0Tx            = 12U,         /**< LPI2C0 Transmit request */
+    kDma0RequestLPI2C1Rx            = 13U,         /**< LPI2C1 Receive request */
+    kDma0RequestLPI2C1Tx            = 14U,         /**< LPI2C1 Transmit request */
+    kDma0RequestLPSPI0Rx            = 15U,         /**< LPSPI0 Receive request */
+    kDma0RequestLPSPI0Tx            = 16U,         /**< LPSPI0 Transmit request */
+    kDma0RequestLPSPI1Rx            = 17U,         /**< LPSPI1 Receive request */
+    kDma0RequestLPSPI1Tx            = 18U,         /**< LPSPI1 Transmit request */
+    kDma0RequestLPUART0Rx           = 21U,         /**< LPUART0 Receive request */
+    kDma0RequestLPUART0Tx           = 22U,         /**< LPUART0 Transmit request */
+    kDma0RequestLPUART1Rx           = 23U,         /**< LPUART1 Receive request */
+    kDma0RequestLPUART1Tx           = 24U,         /**< LPUART1 Transmit request */
+    kDma0RequestLPUART2Rx           = 25U,         /**< LPUART2 Receive request */
+    kDma0RequestLPUART2Tx           = 26U,         /**< LPUART2 Transmit request */
+    kDma0RequestLPUART3Rx           = 27U,         /**< LPUART3 Receive request */
+    kDma0RequestLPUART3Tx           = 28U,         /**< LPUART3 Transmit request */
+    kDma0RequestMuxCtimer0M0        = 31U,         /**< CTIMER0 Match channel 0 request */
+    kDma0RequestMuxCtimer0M1        = 32U,         /**< CTIMER0 Match channel 1 request */
+    kDma0RequestMuxCtimer1M0        = 33U,         /**< CTIMER1 Match channel 0 request */
+    kDma0RequestMuxCtimer1M1        = 34U,         /**< CTIMER1 Match channel 1 request */
+    kDma0RequestMuxCtimer2M0        = 35U,         /**< CTIMER2 Match channel 0 request */
+    kDma0RequestMuxCtimer2M1        = 36U,         /**< CTIMER2 Match channel 1 request */
+    kDma0RequestMuxFlexPWM0ReqCapt0 = 41U,         /**< FlexPWM0 capture0 request */
+    kDma0RequestMuxFlexPWM0ReqCapt1 = 42U,         /**< FlexPWM0 capture1 request */
+    kDma0RequestMuxFlexPWM0ReqCapt2 = 43U,         /**< FlexPWM0 capture2 request */
+    kDma0RequestMuxFlexPWM0ReqCapt3 = 44U,         /**< FlexPWM0 capture3 request */
+    kDma0RequestMuxFlexPWM0ReqVal0  = 45U,         /**< FlexPWM0 value0 request */
+    kDma0RequestMuxFlexPWM0ReqVal1  = 46U,         /**< FlexPWM0 value1 request */
+    kDma0RequestMuxFlexPWM0ReqVal2  = 47U,         /**< FlexPWM0 value2 request */
+    kDma0RequestMuxFlexPWM0ReqVal3  = 48U,         /**< FlexPWM0 value3 request */
+    kDma0RequestMuxLptmr0           = 49U,         /**< LPTMR0 Counter match event */
+    kDma0RequestMuxAdc0FifoRequest  = 51U,         /**< ADC0 FIFO request */
+    kDma0RequestMuxAdc1FifoRequest  = 52U,         /**< ADC1 FIFO request */
+    kDma0RequestMuxHsCmp0DmaRequest = 53U,         /**< CMP0 DMA_request */
+    kDma0RequestMuxHsCmp1DmaRequest = 54U,         /**< CMP1 DMA_request */
+    kDma0RequestMuxGpio0PinEventRequest0 = 60U,    /**< GPIO0 Pin event request 0 */
+    kDma0RequestMuxGpio1PinEventRequest0 = 61U,    /**< GPIO1 Pin event request 0 */
+    kDma0RequestMuxGpio2PinEventRequest0 = 62U,    /**< GPIO2 Pin event request 0 */
+    kDma0RequestMuxGpio3PinEventRequest0 = 63U,    /**< GPIO3 Pin event request 0 */
+    kDma0RequestMuxGpio4PinEventRequest0 = 64U,    /**< GPIO4 Pin event request 0 */
+    kDma0RequestMuxEqdc0            = 65U,         /**< EQDC0 DMA request for new buffered value  */
+    kDma0RequestMuxEqdc1            = 66U,         /**< EQDC1 DMA request for new buffered value  */
+    kDma0RequestMuxFlexPWM1ReqCapt0 = 79U,         /**< FlexPWM1 capture0 request */
+    kDma0RequestMuxFlexPWM1ReqCapt1 = 80U,         /**< FlexPWM1 capture1 request */
+    kDma0RequestMuxFlexPWM1ReqCapt2 = 81U,         /**< FlexPWM1 capture2 request */
+    kDma0RequestMuxFlexPWM1ReqCapt3 = 82U,         /**< FlexPWM1 capture3 request */
+    kDma0RequestMuxFlexPWM1ReqVal0  = 83U,         /**< FlexPWM1 value0 request */
+    kDma0RequestMuxFlexPWM1ReqVal1  = 84U,         /**< FlexPWM1 value1 request */
+    kDma0RequestMuxFlexPWM1ReqVal2  = 85U,         /**< FlexPWM1 value2 request */
+    kDma0RequestMuxFlexPWM1ReqVal3  = 86U,         /**< FlexPWM1 value2 request */
+    kDma0RequestMuxHsCmp2DmaRequest = 55U,         /**< CMP2 DMA_request */
+} dma_request_source_t;
+
+/* @} */
+#endif /* DMA_REQUEST_SOURCE_T_ */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Size of Registers Arrays */
+#define DMA_MP_GRPRI_COUNT                        8u
+#define DMA_CH_COUNT                              8u
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MP_CSR;                            /**< Management Page Control, offset: 0x0 */
+  __I  uint32_t MP_ES;                             /**< Management Page Error Status, offset: 0x4 */
+  __I  uint32_t MP_INT;                            /**< Management Page Interrupt Request Status, offset: 0x8 */
+  __I  uint32_t MP_HRS;                            /**< Management Page Hardware Request Status, offset: 0xC */
+       uint8_t RESERVED_0[240];
+  __IO uint32_t CH_GRPRI[DMA_MP_GRPRI_COUNT];      /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */
+       uint8_t RESERVED_1[3808];
+  struct {                                         /* offset: 0x1000, array step: 0x1000 */
+    __IO uint32_t CH_CSR;                            /**< Channel Control and Status, array offset: 0x1000, array step: 0x1000 */
+    __IO uint32_t CH_ES;                             /**< Channel Error Status, array offset: 0x1004, array step: 0x1000 */
+    __IO uint32_t CH_INT;                            /**< Channel Interrupt Status, array offset: 0x1008, array step: 0x1000 */
+    __IO uint32_t CH_SBR;                            /**< Channel System Bus, array offset: 0x100C, array step: 0x1000 */
+    __IO uint32_t CH_PRI;                            /**< Channel Priority, array offset: 0x1010, array step: 0x1000 */
+    __IO uint32_t CH_MUX;                            /**< Channel Multiplexor Configuration, array offset: 0x1014, array step: 0x1000 */
+         uint8_t RESERVED_0[8];
+    __IO uint32_t TCD_SADDR;                         /**< TCD Source Address, array offset: 0x1020, array step: 0x1000 */
+    __IO uint16_t TCD_SOFF;                          /**< TCD Signed Source Address Offset, array offset: 0x1024, array step: 0x1000 */
+    __IO uint16_t TCD_ATTR;                          /**< TCD Transfer Attributes, array offset: 0x1026, array step: 0x1000 */
+    union {                                          /* offset: 0x1028, array step: 0x1000 */
+      __IO uint32_t TCD_NBYTES_MLOFFNO;                /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */
+      __IO uint32_t TCD_NBYTES_MLOFFYES;               /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */
+    };
+    __IO uint32_t TCD_SLAST_SDA;                     /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x102C, array step: 0x1000 */
+    __IO uint32_t TCD_DADDR;                         /**< TCD Destination Address, array offset: 0x1030, array step: 0x1000 */
+    __IO uint16_t TCD_DOFF;                          /**< TCD Signed Destination Address Offset, array offset: 0x1034, array step: 0x1000 */
+    union {                                          /* offset: 0x1036, array step: 0x1000 */
+      __IO uint16_t TCD_CITER_ELINKNO;                 /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1036, array step: 0x1000 */
+      __IO uint16_t TCD_CITER_ELINKYES;                /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1036, array step: 0x1000 */
+    };
+    __IO uint32_t TCD_DLAST_SGA;                     /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x1038, array step: 0x1000 */
+    __IO uint16_t TCD_CSR;                           /**< TCD Control and Status, array offset: 0x103C, array step: 0x1000 */
+    union {                                          /* offset: 0x103E, array step: 0x1000 */
+      __IO uint16_t TCD_BITER_ELINKNO;                 /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x103E, array step: 0x1000 */
+      __IO uint16_t TCD_BITER_ELINKYES;                /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x103E, array step: 0x1000 */
+    };
+         uint8_t RESERVED_1[4032];
+  } CH[DMA_CH_COUNT];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name MP_CSR - Management Page Control */
+/*! @{ */
+
+#define DMA_MP_CSR_EDBG_MASK                     (0x2U)
+#define DMA_MP_CSR_EDBG_SHIFT                    (1U)
+/*! EDBG - Enable Debug
+ *  0b0..Debug mode disabled
+ *  0b1..Debug mode is enabled.
+ */
+#define DMA_MP_CSR_EDBG(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK)
+
+#define DMA_MP_CSR_ERCA_MASK                     (0x4U)
+#define DMA_MP_CSR_ERCA_SHIFT                    (2U)
+/*! ERCA - Enable Round Robin Channel Arbitration
+ *  0b0..Round-robin channel arbitration disabled
+ *  0b1..Round-robin channel arbitration enabled
+ */
+#define DMA_MP_CSR_ERCA(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK)
+
+#define DMA_MP_CSR_HAE_MASK                      (0x10U)
+#define DMA_MP_CSR_HAE_SHIFT                     (4U)
+/*! HAE - Halt After Error
+ *  0b0..Normal operation
+ *  0b1..Any error causes the HALT field to be set to 1
+ */
+#define DMA_MP_CSR_HAE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK)
+
+#define DMA_MP_CSR_HALT_MASK                     (0x20U)
+#define DMA_MP_CSR_HALT_SHIFT                    (5U)
+/*! HALT - Halt DMA Operations
+ *  0b0..Normal operation
+ *  0b1..Stall the start of any new channels
+ */
+#define DMA_MP_CSR_HALT(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK)
+
+#define DMA_MP_CSR_GCLC_MASK                     (0x40U)
+#define DMA_MP_CSR_GCLC_SHIFT                    (6U)
+/*! GCLC - Global Channel Linking Control
+ *  0b0..Channel linking disabled for all channels
+ *  0b1..Channel linking available and controlled by each channel's link settings
+ */
+#define DMA_MP_CSR_GCLC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK)
+
+#define DMA_MP_CSR_GMRC_MASK                     (0x80U)
+#define DMA_MP_CSR_GMRC_SHIFT                    (7U)
+/*! GMRC - Global Initiator ID Replication Control
+ *  0b0..Initiator ID replication disabled for all channels
+ *  0b1..Initiator ID replication available and controlled by each channel's CHn_SBR[EMI] setting
+ */
+#define DMA_MP_CSR_GMRC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK)
+
+#define DMA_MP_CSR_ECX_MASK                      (0x100U)
+#define DMA_MP_CSR_ECX_SHIFT                     (8U)
+/*! ECX - Cancel Transfer With Error
+ *  0b0..Normal operation
+ *  0b1..Cancel the remaining data transfer
+ */
+#define DMA_MP_CSR_ECX(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK)
+
+#define DMA_MP_CSR_CX_MASK                       (0x200U)
+#define DMA_MP_CSR_CX_SHIFT                      (9U)
+/*! CX - Cancel Transfer
+ *  0b0..Normal operation
+ *  0b1..Cancel the remaining data transfer
+ */
+#define DMA_MP_CSR_CX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK)
+
+#define DMA_MP_CSR_ACTIVE_ID_MASK                (0x7000000U)
+#define DMA_MP_CSR_ACTIVE_ID_SHIFT               (24U)
+/*! ACTIVE_ID - Active Channel ID */
+#define DMA_MP_CSR_ACTIVE_ID(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK)
+
+#define DMA_MP_CSR_ACTIVE_MASK                   (0x80000000U)
+#define DMA_MP_CSR_ACTIVE_SHIFT                  (31U)
+/*! ACTIVE - DMA Active Status
+ *  0b0..eDMA is idle
+ *  0b1..eDMA is executing a channel
+ */
+#define DMA_MP_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK)
+/*! @} */
+
+/*! @name MP_ES - Management Page Error Status */
+/*! @{ */
+
+#define DMA_MP_ES_DBE_MASK                       (0x1U)
+#define DMA_MP_ES_DBE_SHIFT                      (0U)
+/*! DBE - Destination Bus Error
+ *  0b0..No destination bus error
+ *  0b1..Last recorded error was a bus error on a destination write
+ */
+#define DMA_MP_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK)
+
+#define DMA_MP_ES_SBE_MASK                       (0x2U)
+#define DMA_MP_ES_SBE_SHIFT                      (1U)
+/*! SBE - Source Bus Error
+ *  0b0..No source bus error
+ *  0b1..Last recorded error was a bus error on a source read
+ */
+#define DMA_MP_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK)
+
+#define DMA_MP_ES_SGE_MASK                       (0x4U)
+#define DMA_MP_ES_SGE_SHIFT                      (2U)
+/*! SGE - Scatter/Gather Configuration Error
+ *  0b0..No scatter/gather configuration error
+ *  0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
+ */
+#define DMA_MP_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK)
+
+#define DMA_MP_ES_NCE_MASK                       (0x8U)
+#define DMA_MP_ES_NCE_SHIFT                      (3U)
+/*! NCE - NBYTES/CITER Configuration Error
+ *  0b0..No NBYTES/CITER configuration error
+ *  0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error
+ */
+#define DMA_MP_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK)
+
+#define DMA_MP_ES_DOE_MASK                       (0x10U)
+#define DMA_MP_ES_DOE_SHIFT                      (4U)
+/*! DOE - Destination Offset Error
+ *  0b0..No destination offset configuration error
+ *  0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
+ */
+#define DMA_MP_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK)
+
+#define DMA_MP_ES_DAE_MASK                       (0x20U)
+#define DMA_MP_ES_DAE_SHIFT                      (5U)
+/*! DAE - Destination Address Error
+ *  0b0..No destination address configuration error
+ *  0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
+ */
+#define DMA_MP_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK)
+
+#define DMA_MP_ES_SOE_MASK                       (0x40U)
+#define DMA_MP_ES_SOE_SHIFT                      (6U)
+/*! SOE - Source Offset Error
+ *  0b0..No source offset configuration error
+ *  0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
+ */
+#define DMA_MP_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK)
+
+#define DMA_MP_ES_SAE_MASK                       (0x80U)
+#define DMA_MP_ES_SAE_SHIFT                      (7U)
+/*! SAE - Source Address Error
+ *  0b0..No source address configuration error
+ *  0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
+ */
+#define DMA_MP_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK)
+
+#define DMA_MP_ES_ECX_MASK                       (0x100U)
+#define DMA_MP_ES_ECX_SHIFT                      (8U)
+/*! ECX - Transfer Canceled
+ *  0b0..No canceled transfers
+ *  0b1..Last recorded entry was a canceled transfer by the error cancel transfer input
+ */
+#define DMA_MP_ES_ECX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK)
+
+#define DMA_MP_ES_ERRCHN_MASK                    (0x7000000U)
+#define DMA_MP_ES_ERRCHN_SHIFT                   (24U)
+/*! ERRCHN - Error Channel Number or Canceled Channel Number */
+#define DMA_MP_ES_ERRCHN(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK)
+
+#define DMA_MP_ES_VLD_MASK                       (0x80000000U)
+#define DMA_MP_ES_VLD_SHIFT                      (31U)
+/*! VLD - Valid
+ *  0b0..No CHn_ES[ERR] fields are set to 1
+ *  0b1..At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared
+ */
+#define DMA_MP_ES_VLD(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK)
+/*! @} */
+
+/*! @name MP_INT - Management Page Interrupt Request Status */
+/*! @{ */
+
+#define DMA_MP_INT_INT_MASK                      (0xFFU)
+#define DMA_MP_INT_INT_SHIFT                     (0U)
+/*! INT - Interrupt Request Status */
+#define DMA_MP_INT_INT(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK)
+/*! @} */
+
+/*! @name MP_HRS - Management Page Hardware Request Status */
+/*! @{ */
+
+#define DMA_MP_HRS_HRS_MASK                      (0xFFFFFFFFU)
+#define DMA_MP_HRS_HRS_SHIFT                     (0U)
+/*! HRS - Hardware Request Status */
+#define DMA_MP_HRS_HRS(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK)
+/*! @} */
+
+/*! @name CH_GRPRI - Channel Arbitration Group */
+/*! @{ */
+
+#define DMA_CH_GRPRI_GRPRI_MASK                  (0x1FU)
+#define DMA_CH_GRPRI_GRPRI_SHIFT                 (0U)
+/*! GRPRI - Arbitration Group For Channel n */
+#define DMA_CH_GRPRI_GRPRI(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK)
+/*! @} */
+
+/* The count of DMA_CH_GRPRI */
+#define DMA_CH_GRPRI_COUNT                       (8U)
+
+/*! @name CH_CSR - Channel Control and Status */
+/*! @{ */
+
+#define DMA_CH_CSR_ERQ_MASK                      (0x1U)
+#define DMA_CH_CSR_ERQ_SHIFT                     (0U)
+/*! ERQ - Enable DMA Request
+ *  0b0..DMA hardware request signal for corresponding channel disabled
+ *  0b1..DMA hardware request signal for corresponding channel enabled
+ */
+#define DMA_CH_CSR_ERQ(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
+
+#define DMA_CH_CSR_EARQ_MASK                     (0x2U)
+#define DMA_CH_CSR_EARQ_SHIFT                    (1U)
+/*! EARQ - Enable Asynchronous DMA Request
+ *  0b0..Disable asynchronous DMA request for the channel
+ *  0b1..Enable asynchronous DMA request for the channel
+ */
+#define DMA_CH_CSR_EARQ(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK)
+
+#define DMA_CH_CSR_EEI_MASK                      (0x4U)
+#define DMA_CH_CSR_EEI_SHIFT                     (2U)
+/*! EEI - Enable Error Interrupt
+ *  0b0..Error signal for corresponding channel does not generate error interrupt
+ *  0b1..Assertion of error signal for corresponding channel generates error interrupt request
+ */
+#define DMA_CH_CSR_EEI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK)
+
+#define DMA_CH_CSR_EBW_MASK                      (0x8U)
+#define DMA_CH_CSR_EBW_SHIFT                     (3U)
+/*! EBW - Enable Buffered Writes
+ *  0b0..Buffered writes on system bus disabled
+ *  0b1..Buffered writes on system bus enabled
+ */
+#define DMA_CH_CSR_EBW(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK)
+
+#define DMA_CH_CSR_DONE_MASK                     (0x40000000U)
+#define DMA_CH_CSR_DONE_SHIFT                    (30U)
+/*! DONE - Channel Done */
+#define DMA_CH_CSR_DONE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK)
+
+#define DMA_CH_CSR_ACTIVE_MASK                   (0x80000000U)
+#define DMA_CH_CSR_ACTIVE_SHIFT                  (31U)
+/*! ACTIVE - Channel Active */
+#define DMA_CH_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK)
+/*! @} */
+
+/* The count of DMA_CH_CSR */
+#define DMA_CH_CSR_COUNT                         (8U)
+
+/*! @name CH_ES - Channel Error Status */
+/*! @{ */
+
+#define DMA_CH_ES_DBE_MASK                       (0x1U)
+#define DMA_CH_ES_DBE_SHIFT                      (0U)
+/*! DBE - Destination Bus Error
+ *  0b0..No destination bus error
+ *  0b1..Last recorded error was bus error on destination write
+ */
+#define DMA_CH_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK)
+
+#define DMA_CH_ES_SBE_MASK                       (0x2U)
+#define DMA_CH_ES_SBE_SHIFT                      (1U)
+/*! SBE - Source Bus Error
+ *  0b0..No source bus error
+ *  0b1..Last recorded error was bus error on source read
+ */
+#define DMA_CH_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK)
+
+#define DMA_CH_ES_SGE_MASK                       (0x4U)
+#define DMA_CH_ES_SGE_SHIFT                      (2U)
+/*! SGE - Scatter/Gather Configuration Error
+ *  0b0..No scatter/gather configuration error
+ *  0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
+ */
+#define DMA_CH_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK)
+
+#define DMA_CH_ES_NCE_MASK                       (0x8U)
+#define DMA_CH_ES_NCE_SHIFT                      (3U)
+/*! NCE - NBYTES/CITER Configuration Error
+ *  0b0..No NBYTES/CITER configuration error
+ *  0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields
+ */
+#define DMA_CH_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK)
+
+#define DMA_CH_ES_DOE_MASK                       (0x10U)
+#define DMA_CH_ES_DOE_SHIFT                      (4U)
+/*! DOE - Destination Offset Error
+ *  0b0..No destination offset configuration error
+ *  0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
+ */
+#define DMA_CH_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK)
+
+#define DMA_CH_ES_DAE_MASK                       (0x20U)
+#define DMA_CH_ES_DAE_SHIFT                      (5U)
+/*! DAE - Destination Address Error
+ *  0b0..No destination address configuration error
+ *  0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
+ */
+#define DMA_CH_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK)
+
+#define DMA_CH_ES_SOE_MASK                       (0x40U)
+#define DMA_CH_ES_SOE_SHIFT                      (6U)
+/*! SOE - Source Offset Error
+ *  0b0..No source offset configuration error
+ *  0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
+ */
+#define DMA_CH_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK)
+
+#define DMA_CH_ES_SAE_MASK                       (0x80U)
+#define DMA_CH_ES_SAE_SHIFT                      (7U)
+/*! SAE - Source Address Error
+ *  0b0..No source address configuration error
+ *  0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
+ */
+#define DMA_CH_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK)
+
+#define DMA_CH_ES_ERR_MASK                       (0x80000000U)
+#define DMA_CH_ES_ERR_SHIFT                      (31U)
+/*! ERR - Error In Channel
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_CH_ES_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK)
+/*! @} */
+
+/* The count of DMA_CH_ES */
+#define DMA_CH_ES_COUNT                          (8U)
+
+/*! @name CH_INT - Channel Interrupt Status */
+/*! @{ */
+
+#define DMA_CH_INT_INT_MASK                      (0x1U)
+#define DMA_CH_INT_INT_SHIFT                     (0U)
+/*! INT - Interrupt Request
+ *  0b0..Interrupt request for corresponding channel cleared
+ *  0b1..Interrupt request for corresponding channel active
+ */
+#define DMA_CH_INT_INT(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
+/*! @} */
+
+/* The count of DMA_CH_INT */
+#define DMA_CH_INT_COUNT                         (8U)
+
+/*! @name CH_SBR - Channel System Bus */
+/*! @{ */
+
+#define DMA_CH_SBR_MID_MASK                      (0xFU)
+#define DMA_CH_SBR_MID_SHIFT                     (0U)
+/*! MID - Initiator ID */
+#define DMA_CH_SBR_MID(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK)
+
+#define DMA_CH_SBR_PAL_MASK                      (0x8000U)
+#define DMA_CH_SBR_PAL_SHIFT                     (15U)
+/*! PAL - Privileged Access Level
+ *  0b0..User protection level for DMA transfers
+ *  0b1..Privileged protection level for DMA transfers
+ */
+#define DMA_CH_SBR_PAL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK)
+
+#define DMA_CH_SBR_EMI_MASK                      (0x10000U)
+#define DMA_CH_SBR_EMI_SHIFT                     (16U)
+/*! EMI - Enable Initiator ID Replication
+ *  0b0..Initiator ID replication is disabled
+ *  0b1..Initiator ID replication is enabled
+ */
+#define DMA_CH_SBR_EMI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK)
+/*! @} */
+
+/* The count of DMA_CH_SBR */
+#define DMA_CH_SBR_COUNT                         (8U)
+
+/*! @name CH_PRI - Channel Priority */
+/*! @{ */
+
+#define DMA_CH_PRI_APL_MASK                      (0x7U)
+#define DMA_CH_PRI_APL_SHIFT                     (0U)
+/*! APL - Arbitration Priority Level */
+#define DMA_CH_PRI_APL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK)
+
+#define DMA_CH_PRI_DPA_MASK                      (0x40000000U)
+#define DMA_CH_PRI_DPA_SHIFT                     (30U)
+/*! DPA - Disable Preempt Ability
+ *  0b0..Channel can suspend a lower-priority channel
+ *  0b1..Channel cannot suspend any other channel, regardless of channel priority
+ */
+#define DMA_CH_PRI_DPA(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK)
+
+#define DMA_CH_PRI_ECP_MASK                      (0x80000000U)
+#define DMA_CH_PRI_ECP_SHIFT                     (31U)
+/*! ECP - Enable Channel Preemption
+ *  0b0..Channel cannot be suspended by a higher-priority channel's service request
+ *  0b1..Channel can be temporarily suspended by a higher-priority channel's service request
+ */
+#define DMA_CH_PRI_ECP(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK)
+/*! @} */
+
+/* The count of DMA_CH_PRI */
+#define DMA_CH_PRI_COUNT                         (8U)
+
+/*! @name CH_MUX - Channel Multiplexor Configuration */
+/*! @{ */
+
+#define DMA_CH_MUX_SRC_MASK                      (0x7FU)
+#define DMA_CH_MUX_SRC_SHIFT                     (0U)
+/*! SRC - Service Request Source */
+#define DMA_CH_MUX_SRC(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK)
+/*! @} */
+
+/* The count of DMA_CH_MUX */
+#define DMA_CH_MUX_COUNT                         (8U)
+
+/*! @name TCD_SADDR - TCD Source Address */
+/*! @{ */
+
+#define DMA_TCD_SADDR_SADDR_MASK                 (0xFFFFFFFFU)
+#define DMA_TCD_SADDR_SADDR_SHIFT                (0U)
+/*! SADDR - Source Address */
+#define DMA_TCD_SADDR_SADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK)
+/*! @} */
+
+/* The count of DMA_TCD_SADDR */
+#define DMA_TCD_SADDR_COUNT                      (8U)
+
+/*! @name TCD_SOFF - TCD Signed Source Address Offset */
+/*! @{ */
+
+#define DMA_TCD_SOFF_SOFF_MASK                   (0xFFFFU)
+#define DMA_TCD_SOFF_SOFF_SHIFT                  (0U)
+/*! SOFF - Source Address Signed Offset */
+#define DMA_TCD_SOFF_SOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK)
+/*! @} */
+
+/* The count of DMA_TCD_SOFF */
+#define DMA_TCD_SOFF_COUNT                       (8U)
+
+/*! @name TCD_ATTR - TCD Transfer Attributes */
+/*! @{ */
+
+#define DMA_TCD_ATTR_DSIZE_MASK                  (0x7U)
+#define DMA_TCD_ATTR_DSIZE_SHIFT                 (0U)
+/*! DSIZE - Destination Data Transfer Size */
+#define DMA_TCD_ATTR_DSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK)
+
+#define DMA_TCD_ATTR_DMOD_MASK                   (0xF8U)
+#define DMA_TCD_ATTR_DMOD_SHIFT                  (3U)
+/*! DMOD - Destination Address Modulo */
+#define DMA_TCD_ATTR_DMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK)
+
+#define DMA_TCD_ATTR_SSIZE_MASK                  (0x700U)
+#define DMA_TCD_ATTR_SSIZE_SHIFT                 (8U)
+/*! SSIZE - Source Data Transfer Size
+ *  0b000..8-bit
+ *  0b001..16-bit
+ *  0b010..32-bit
+ *  0b011..64-bit
+ *  0b100..16-byte
+ *  0b101..32-byte
+ *  0b110..
+ *  0b111..
+ */
+#define DMA_TCD_ATTR_SSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK)
+
+#define DMA_TCD_ATTR_SMOD_MASK                   (0xF800U)
+#define DMA_TCD_ATTR_SMOD_SHIFT                  (11U)
+/*! SMOD - Source Address Modulo
+ *  0b00000..Source address modulo feature disabled
+ */
+#define DMA_TCD_ATTR_SMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK)
+/*! @} */
+
+/* The count of DMA_TCD_ATTR */
+#define DMA_TCD_ATTR_COUNT                       (8U)
+
+/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */
+/*! @{ */
+
+#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK       (0x3FFFFFFFU)
+#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT      (0U)
+/*! NBYTES - Number of Bytes To Transfer Per Service Request */
+#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)
+
+#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK        (0x40000000U)
+#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT       (30U)
+/*! DMLOE - Destination Minor Loop Offset Enable
+ *  0b0..Minor loop offset not applied to DADDR
+ *  0b1..Minor loop offset applied to DADDR
+ */
+#define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)
+
+#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK        (0x80000000U)
+#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT       (31U)
+/*! SMLOE - Source Minor Loop Offset Enable
+ *  0b0..Minor loop offset not applied to SADDR
+ *  0b1..Minor loop offset applied to SADDR
+ */
+#define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
+/*! @} */
+
+/* The count of DMA_TCD_NBYTES_MLOFFNO */
+#define DMA_TCD_NBYTES_MLOFFNO_COUNT             (8U)
+
+/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */
+/*! @{ */
+
+#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK      (0x3FFU)
+#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT     (0U)
+/*! NBYTES - Number of Bytes To Transfer Per Service Request */
+#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)        (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)
+
+#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK       (0x3FFFFC00U)
+#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT      (10U)
+/*! MLOFF - Minor Loop Offset */
+#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)
+
+#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK       (0x40000000U)
+#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT      (30U)
+/*! DMLOE - Destination Minor Loop Offset Enable
+ *  0b0..Minor loop offset not applied to DADDR
+ *  0b1..Minor loop offset applied to DADDR
+ */
+#define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)
+
+#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK       (0x80000000U)
+#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT      (31U)
+/*! SMLOE - Source Minor Loop Offset Enable
+ *  0b0..Minor loop offset not applied to SADDR
+ *  0b1..Minor loop offset applied to SADDR
+ */
+#define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
+/*! @} */
+
+/* The count of DMA_TCD_NBYTES_MLOFFYES */
+#define DMA_TCD_NBYTES_MLOFFYES_COUNT            (8U)
+
+/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */
+/*! @{ */
+
+#define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK         (0xFFFFFFFFU)
+#define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT        (0U)
+/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */
+#define DMA_TCD_SLAST_SDA_SLAST_SDA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK)
+/*! @} */
+
+/* The count of DMA_TCD_SLAST_SDA */
+#define DMA_TCD_SLAST_SDA_COUNT                  (8U)
+
+/*! @name TCD_DADDR - TCD Destination Address */
+/*! @{ */
+
+#define DMA_TCD_DADDR_DADDR_MASK                 (0xFFFFFFFFU)
+#define DMA_TCD_DADDR_DADDR_SHIFT                (0U)
+/*! DADDR - Destination Address */
+#define DMA_TCD_DADDR_DADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK)
+/*! @} */
+
+/* The count of DMA_TCD_DADDR */
+#define DMA_TCD_DADDR_COUNT                      (8U)
+
+/*! @name TCD_DOFF - TCD Signed Destination Address Offset */
+/*! @{ */
+
+#define DMA_TCD_DOFF_DOFF_MASK                   (0xFFFFU)
+#define DMA_TCD_DOFF_DOFF_SHIFT                  (0U)
+/*! DOFF - Destination Address Signed Offset */
+#define DMA_TCD_DOFF_DOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK)
+/*! @} */
+
+/* The count of DMA_TCD_DOFF */
+#define DMA_TCD_DOFF_COUNT                       (8U)
+
+/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */
+/*! @{ */
+
+#define DMA_TCD_CITER_ELINKNO_CITER_MASK         (0x7FFFU)
+#define DMA_TCD_CITER_ELINKNO_CITER_SHIFT        (0U)
+/*! CITER - Current Major Iteration Count */
+#define DMA_TCD_CITER_ELINKNO_CITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK)
+
+#define DMA_TCD_CITER_ELINKNO_ELINK_MASK         (0x8000U)
+#define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT        (15U)
+/*! ELINK - Enable Link
+ *  0b0..Channel-to-channel linking disabled
+ *  0b1..Channel-to-channel linking enabled
+ */
+#define DMA_TCD_CITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK)
+/*! @} */
+
+/* The count of DMA_TCD_CITER_ELINKNO */
+#define DMA_TCD_CITER_ELINKNO_COUNT              (8U)
+
+/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */
+/*! @{ */
+
+#define DMA_TCD_CITER_ELINKYES_CITER_MASK        (0x1FFU)
+#define DMA_TCD_CITER_ELINKYES_CITER_SHIFT       (0U)
+/*! CITER - Current Major Iteration Count */
+#define DMA_TCD_CITER_ELINKYES_CITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK)
+
+#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK       (0xE00U)
+#define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT      (9U)
+/*! LINKCH - Minor Loop Link Channel Number */
+#define DMA_TCD_CITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK)
+
+#define DMA_TCD_CITER_ELINKYES_ELINK_MASK        (0x8000U)
+#define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT       (15U)
+/*! ELINK - Enable Link
+ *  0b0..Channel-to-channel linking disabled
+ *  0b1..Channel-to-channel linking enabled
+ */
+#define DMA_TCD_CITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK)
+/*! @} */
+
+/* The count of DMA_TCD_CITER_ELINKYES */
+#define DMA_TCD_CITER_ELINKYES_COUNT             (8U)
+
+/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */
+/*! @{ */
+
+#define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK         (0xFFFFFFFFU)
+#define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT        (0U)
+/*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */
+#define DMA_TCD_DLAST_SGA_DLAST_SGA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK)
+/*! @} */
+
+/* The count of DMA_TCD_DLAST_SGA */
+#define DMA_TCD_DLAST_SGA_COUNT                  (8U)
+
+/*! @name TCD_CSR - TCD Control and Status */
+/*! @{ */
+
+#define DMA_TCD_CSR_START_MASK                   (0x1U)
+#define DMA_TCD_CSR_START_SHIFT                  (0U)
+/*! START - Channel Start
+ *  0b0..Channel not explicitly started
+ *  0b1..Channel explicitly started via a software-initiated service request
+ */
+#define DMA_TCD_CSR_START(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK)
+
+#define DMA_TCD_CSR_INTMAJOR_MASK                (0x2U)
+#define DMA_TCD_CSR_INTMAJOR_SHIFT               (1U)
+/*! INTMAJOR - Enable Interrupt If Major count complete
+ *  0b0..End-of-major loop interrupt disabled
+ *  0b1..End-of-major loop interrupt enabled
+ */
+#define DMA_TCD_CSR_INTMAJOR(x)                  (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK)
+
+#define DMA_TCD_CSR_INTHALF_MASK                 (0x4U)
+#define DMA_TCD_CSR_INTHALF_SHIFT                (2U)
+/*! INTHALF - Enable Interrupt If Major Counter Half-complete
+ *  0b0..Halfway point interrupt disabled
+ *  0b1..Halfway point interrupt enabled
+ */
+#define DMA_TCD_CSR_INTHALF(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK)
+
+#define DMA_TCD_CSR_DREQ_MASK                    (0x8U)
+#define DMA_TCD_CSR_DREQ_SHIFT                   (3U)
+/*! DREQ - Disable Request
+ *  0b0..No operation
+ *  0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests
+ */
+#define DMA_TCD_CSR_DREQ(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
+
+#define DMA_TCD_CSR_ESG_MASK                     (0x10U)
+#define DMA_TCD_CSR_ESG_SHIFT                    (4U)
+/*! ESG - Enable Scatter/Gather Processing
+ *  0b0..Current channel's TCD is normal format
+ *  0b1..Current channel's TCD specifies scatter/gather format.
+ */
+#define DMA_TCD_CSR_ESG(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK)
+
+#define DMA_TCD_CSR_MAJORELINK_MASK              (0x20U)
+#define DMA_TCD_CSR_MAJORELINK_SHIFT             (5U)
+/*! MAJORELINK - Enable Link When Major Loop Complete
+ *  0b0..Channel-to-channel linking disabled
+ *  0b1..Channel-to-channel linking enabled
+ */
+#define DMA_TCD_CSR_MAJORELINK(x)                (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK)
+
+#define DMA_TCD_CSR_EEOP_MASK                    (0x40U)
+#define DMA_TCD_CSR_EEOP_SHIFT                   (6U)
+/*! EEOP - Enable End-Of-Packet Processing
+ *  0b0..End-of-packet operation disabled
+ *  0b1..End-of-packet hardware input signal enabled
+ */
+#define DMA_TCD_CSR_EEOP(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK)
+
+#define DMA_TCD_CSR_ESDA_MASK                    (0x80U)
+#define DMA_TCD_CSR_ESDA_SHIFT                   (7U)
+/*! ESDA - Enable Store Destination Address
+ *  0b0..Ability to store destination address to system memory disabled
+ *  0b1..Ability to store destination address to system memory enabled
+ */
+#define DMA_TCD_CSR_ESDA(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK)
+
+#define DMA_TCD_CSR_MAJORLINKCH_MASK             (0x700U)
+#define DMA_TCD_CSR_MAJORLINKCH_SHIFT            (8U)
+/*! MAJORLINKCH - Major Loop Link Channel Number */
+#define DMA_TCD_CSR_MAJORLINKCH(x)               (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK)
+
+#define DMA_TCD_CSR_BWC_MASK                     (0xC000U)
+#define DMA_TCD_CSR_BWC_SHIFT                    (14U)
+/*! BWC - Bandwidth Control
+ *  0b00..No eDMA engine stalls
+ *  0b01..
+ *  0b10..eDMA engine stalls for 4 cycles after each R/W
+ *  0b11..eDMA engine stalls for 8 cycles after each R/W
+ */
+#define DMA_TCD_CSR_BWC(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK)
+/*! @} */
+
+/* The count of DMA_TCD_CSR */
+#define DMA_TCD_CSR_COUNT                        (8U)
+
+/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */
+/*! @{ */
+
+#define DMA_TCD_BITER_ELINKNO_BITER_MASK         (0x7FFFU)
+#define DMA_TCD_BITER_ELINKNO_BITER_SHIFT        (0U)
+/*! BITER - Starting Major Iteration Count */
+#define DMA_TCD_BITER_ELINKNO_BITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK)
+
+#define DMA_TCD_BITER_ELINKNO_ELINK_MASK         (0x8000U)
+#define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT        (15U)
+/*! ELINK - Enables Link
+ *  0b0..Channel-to-channel linking disabled
+ *  0b1..Channel-to-channel linking enabled
+ */
+#define DMA_TCD_BITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK)
+/*! @} */
+
+/* The count of DMA_TCD_BITER_ELINKNO */
+#define DMA_TCD_BITER_ELINKNO_COUNT              (8U)
+
+/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */
+/*! @{ */
+
+#define DMA_TCD_BITER_ELINKYES_BITER_MASK        (0x1FFU)
+#define DMA_TCD_BITER_ELINKYES_BITER_SHIFT       (0U)
+/*! BITER - Starting Major Iteration Count */
+#define DMA_TCD_BITER_ELINKYES_BITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK)
+
+#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK       (0xE00U)
+#define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT      (9U)
+/*! LINKCH - Link Channel Number */
+#define DMA_TCD_BITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK)
+
+#define DMA_TCD_BITER_ELINKYES_ELINK_MASK        (0x8000U)
+#define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT       (15U)
+/*! ELINK - Enable Link
+ *  0b0..Channel-to-channel linking disabled
+ *  0b1..Channel-to-channel linking enabled
+ */
+#define DMA_TCD_BITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK)
+/*! @} */
+
+/* The count of DMA_TCD_BITER_ELINKYES */
+#define DMA_TCD_BITER_ELINKYES_COUNT             (8U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_DMA_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_EIM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_EIM.h
new file mode 100644
index 0000000000..b7e86397a5
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_EIM.h
@@ -0,0 +1,254 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for EIM
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_EIM.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for EIM
+ *
+ * CMSIS Peripheral Access Layer for EIM
+ */
+
+#if !defined(PERI_EIM_H_)
+#define PERI_EIM_H_                              /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+#if !defined(EIM_MEMORY_CHANNEL_T_)
+#define EIM_MEMORY_CHANNEL_T_
+/*!
+ * @addtogroup eim_memory_channel
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the eim_memory_channel
+ *
+ * Defines the structure for the EIM resource collections.
+ */
+
+typedef enum _eim_memory_channel
+{
+    kEIM_MemoryChannelRAMA0         = 0U,          /**< Memory RAMA0 */
+} eim_memory_channel_t;
+
+/* @} */
+#endif /* EIM_MEMORY_CHANNEL_T_ */
+
+#if !defined(EIM_ERROR_INJECTION_CHANNEL_ENABLE_T_)
+#define EIM_ERROR_INJECTION_CHANNEL_ENABLE_T_
+/*!
+ * @addtogroup eim_error_injection_channel_enable
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the eim_error_injection_channel_enable
+ *
+ * Defines the structure for the EIM error injection resource collections.
+ */
+
+typedef enum _eim_error_injection_channel_enable
+{
+    kEIM_MemoryChannelRAMAEnable    = 0x80000000U, /**< Memory channel 0(RAMA0) error injection enable */
+} eim_error_injection_channel_enable_t;
+
+/* @} */
+#endif /* EIM_ERROR_INJECTION_CHANNEL_ENABLE_T_ */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- EIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer
+ * @{
+ */
+
+/** EIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t EIMCR;                             /**< Error Injection Module Configuration Register, offset: 0x0 */
+  __IO uint32_t EICHEN;                            /**< Error Injection Channel Enable register, offset: 0x4 */
+       uint8_t RESERVED_0[248];
+  __IO uint32_t EICHD0_WORD0;                      /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */
+  __IO uint32_t EICHD0_WORD1;                      /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */
+} EIM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EIM_Register_Masks EIM Register Masks
+ * @{
+ */
+
+/*! @name EIMCR - Error Injection Module Configuration Register */
+/*! @{ */
+
+#define EIM_EIMCR_GEIEN_MASK                     (0x1U)
+#define EIM_EIMCR_GEIEN_SHIFT                    (0U)
+/*! GEIEN - Global Error Injection Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define EIM_EIMCR_GEIEN(x)                       (((uint32_t)(((uint32_t)(x)) << EIM_EIMCR_GEIEN_SHIFT)) & EIM_EIMCR_GEIEN_MASK)
+/*! @} */
+
+/*! @name EICHEN - Error Injection Channel Enable register */
+/*! @{ */
+
+#define EIM_EICHEN_EICH0EN_MASK                  (0x80000000U)
+#define EIM_EICHEN_EICH0EN_SHIFT                 (31U)
+/*! EICH0EN - Error Injection Channel 0 Enable
+ *  0b0..Error injection is disabled on Error Injection Channel 0
+ *  0b1..Error injection is enabled on Error Injection Channel 0
+ */
+#define EIM_EICHEN_EICH0EN(x)                    (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH0EN_SHIFT)) & EIM_EICHEN_EICH0EN_MASK)
+/*! @} */
+
+/*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */
+/*! @{ */
+
+#define EIM_EICHD0_WORD0_CHKBIT_MASK_MASK        (0xFE000000U)
+#define EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT       (25U)
+/*! CHKBIT_MASK - Checkbit Mask */
+#define EIM_EICHD0_WORD0_CHKBIT_MASK(x)          (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK)
+/*! @} */
+
+/*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */
+/*! @{ */
+
+#define EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK      (0xFFFFFFFFU)
+#define EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT     (0U)
+/*! B0_3DATA_MASK - Data Mask Field */
+#define EIM_EICHD0_WORD1_B0_3DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group EIM_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group EIM_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_EIM_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_EQDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_EQDC.h
new file mode 100644
index 0000000000..f3fee6ae0e
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_EQDC.h
@@ -0,0 +1,1013 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for EQDC
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_EQDC.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for EQDC
+ *
+ * CMSIS Peripheral Access Layer for EQDC
+ */
+
+#if !defined(PERI_EQDC_H_)
+#define PERI_EQDC_H_                             /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- EQDC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EQDC_Peripheral_Access_Layer EQDC Peripheral Access Layer
+ * @{
+ */
+
+/** EQDC - Register Layout Typedef */
+typedef struct {
+  __IO uint16_t CTRL;                              /**< Control Register, offset: 0x0 */
+  __IO uint16_t CTRL2;                             /**< Control 2 Register, offset: 0x2 */
+  __IO uint16_t FILT;                              /**< Input Filter Register, offset: 0x4 */
+  __I  uint16_t LASTEDGE;                          /**< Last Edge Time Register, offset: 0x6 */
+  __I  uint16_t POSDPER;                           /**< Position Difference Period Counter Register, offset: 0x8 */
+  __I  uint16_t POSDPERBFR;                        /**< Position Difference Period Buffer Register, offset: 0xA */
+  __IO uint16_t UPOS;                              /**< Upper Position Counter Register, offset: 0xC */
+  __IO uint16_t LPOS;                              /**< Lower Position Counter Register, offset: 0xE */
+  __IO uint16_t POSD;                              /**< Position Difference Counter Register, offset: 0x10 */
+  __I  uint16_t POSDH;                             /**< Position Difference Hold Register, offset: 0x12 */
+  __I  uint16_t UPOSH;                             /**< Upper Position Hold Register, offset: 0x14 */
+  __I  uint16_t LPOSH;                             /**< Lower Position Hold Register, offset: 0x16 */
+  __I  uint16_t LASTEDGEH;                         /**< Last Edge Time Hold Register, offset: 0x18 */
+  __I  uint16_t POSDPERH;                          /**< Position Difference Period Hold Register, offset: 0x1A */
+  __I  uint16_t REVH;                              /**< Revolution Hold Register, offset: 0x1C */
+  __IO uint16_t REV;                               /**< Revolution Counter Register, offset: 0x1E */
+  __IO uint16_t UINIT;                             /**< Upper Initialization Register, offset: 0x20 */
+  __IO uint16_t LINIT;                             /**< Lower Initialization Register, offset: 0x22 */
+  __IO uint16_t UMOD;                              /**< Upper Modulus Register, offset: 0x24 */
+  __IO uint16_t LMOD;                              /**< Lower Modulus Register, offset: 0x26 */
+  __IO uint16_t UCOMP0;                            /**< Upper Position Compare Register 0, offset: 0x28 */
+  __IO uint16_t LCOMP0;                            /**< Lower Position Compare Register 0, offset: 0x2A */
+  union {                                          /* offset: 0x2C */
+    __O  uint16_t UCOMP1;                            /**< Upper Position Compare 1, offset: 0x2C */
+    __I  uint16_t UPOSH1;                            /**< Upper Position Holder Register 1, offset: 0x2C */
+  };
+  union {                                          /* offset: 0x2E */
+    __O  uint16_t LCOMP1;                            /**< Lower Position Compare 1, offset: 0x2E */
+    __I  uint16_t LPOSH1;                            /**< Lower Position Holder Register 1, offset: 0x2E */
+  };
+  union {                                          /* offset: 0x30 */
+    __O  uint16_t UCOMP2;                            /**< Upper Position Compare 2, offset: 0x30 */
+    __I  uint16_t UPOSH2;                            /**< Upper Position Holder Register 3, offset: 0x30 */
+  };
+  union {                                          /* offset: 0x32 */
+    __O  uint16_t LCOMP2;                            /**< Lower Position Compare 2, offset: 0x32 */
+    __I  uint16_t LPOSH2;                            /**< Lower Position Holder Register 2, offset: 0x32 */
+  };
+  union {                                          /* offset: 0x34 */
+    __O  uint16_t UCOMP3;                            /**< Upper Position Compare 3, offset: 0x34 */
+    __I  uint16_t UPOSH3;                            /**< Upper Position Holder Register 3, offset: 0x34 */
+  };
+  union {                                          /* offset: 0x36 */
+    __O  uint16_t LCOMP3;                            /**< Lower Position Compare 3, offset: 0x36 */
+    __I  uint16_t LPOSH3;                            /**< Lower Position Holder Register 3, offset: 0x36 */
+  };
+  __IO uint16_t INTCTRL;                           /**< Interrupt Control Register, offset: 0x38 */
+  __IO uint16_t WTR;                               /**< Watchdog Timeout Register, offset: 0x3A */
+  __IO uint16_t IMR;                               /**< Input Monitor Register, offset: 0x3C */
+  __IO uint16_t TST;                               /**< Test Register, offset: 0x3E */
+       uint8_t RESERVED_0[16];
+  __I  uint16_t UVERID;                            /**< Upper VERID, offset: 0x50 */
+  __I  uint16_t LVERID;                            /**< Lower VERID, offset: 0x52 */
+} EQDC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EQDC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EQDC_Register_Masks EQDC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control Register */
+/*! @{ */
+
+#define EQDC_CTRL_LDOK_MASK                      (0x1U)
+#define EQDC_CTRL_LDOK_SHIFT                     (0U)
+/*! LDOK - Load Okay
+ *  0b0..No loading action taken. Users can write new values to buffered registers (writing into outer-set of these buffered registers)
+ *  0b1..Outer-set values are ready to be loaded into inner-set and take effect. The loading time point depends on CTRL2[LDMOD].
+ */
+#define EQDC_CTRL_LDOK(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_LDOK_SHIFT)) & EQDC_CTRL_LDOK_MASK)
+
+#define EQDC_CTRL_DMAEN_MASK                     (0x2U)
+#define EQDC_CTRL_DMAEN_SHIFT                    (1U)
+/*! DMAEN - DMA Enable
+ *  0b0..DMA is disabled
+ *  0b1..DMA is enabled. DMA request asserts automatically when the values in the outer-set of buffered compare
+ *       registers (UCOMP0/LCOMP0;UCOMP1/LCOMP1;UCOMP2/LCOMP2;UCOMP3/LCOMP3), initial registers(UINIT/LINIT) and
+ *       modulus registers (UMOD/LMOD) are loaded into the inner-set of buffer and then LDOK is cleared automatically.
+ *       After the completion of this DMA transfer, LDOK is set automatically, it ensures outer-set values can be
+ *       loaded into inner-set which in turn triggers DMA again.
+ */
+#define EQDC_CTRL_DMAEN(x)                       (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_DMAEN_SHIFT)) & EQDC_CTRL_DMAEN_MASK)
+
+#define EQDC_CTRL_WDE_MASK                       (0x4U)
+#define EQDC_CTRL_WDE_SHIFT                      (2U)
+/*! WDE - Watchdog Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define EQDC_CTRL_WDE(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDE_SHIFT)) & EQDC_CTRL_WDE_MASK)
+
+#define EQDC_CTRL_WDIE_MASK                      (0x8U)
+#define EQDC_CTRL_WDIE_SHIFT                     (3U)
+/*! WDIE - Watchdog Timeout Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define EQDC_CTRL_WDIE(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDIE_SHIFT)) & EQDC_CTRL_WDIE_MASK)
+
+#define EQDC_CTRL_WDIRQ_MASK                     (0x10U)
+#define EQDC_CTRL_WDIRQ_SHIFT                    (4U)
+/*! WDIRQ - Watchdog Timeout Interrupt Request
+ *  0b0..No Watchdog timeout interrupt has occurred
+ *  0b1..Watchdog timeout interrupt has occurred
+ */
+#define EQDC_CTRL_WDIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDIRQ_SHIFT)) & EQDC_CTRL_WDIRQ_MASK)
+
+#define EQDC_CTRL_XNE_MASK                       (0x20U)
+#define EQDC_CTRL_XNE_SHIFT                      (5U)
+/*! XNE - Select Positive/Negative Edge of INDEX/PRESET Pulse
+ *  0b0..Use positive edge of INDEX/PRESET pulse
+ *  0b1..Use negative edge of INDEX/PRESET pulse
+ */
+#define EQDC_CTRL_XNE(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XNE_SHIFT)) & EQDC_CTRL_XNE_MASK)
+
+#define EQDC_CTRL_XIP_MASK                       (0x40U)
+#define EQDC_CTRL_XIP_SHIFT                      (6U)
+/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS
+ *  0b0..INDEX pulse does not initialize the position counter
+ *  0b1..INDEX pulse initializes the position counter
+ */
+#define EQDC_CTRL_XIP(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIP_SHIFT)) & EQDC_CTRL_XIP_MASK)
+
+#define EQDC_CTRL_XIE_MASK                       (0x80U)
+#define EQDC_CTRL_XIE_SHIFT                      (7U)
+/*! XIE - INDEX/PRESET Pulse Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define EQDC_CTRL_XIE(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIE_SHIFT)) & EQDC_CTRL_XIE_MASK)
+
+#define EQDC_CTRL_XIRQ_MASK                      (0x100U)
+#define EQDC_CTRL_XIRQ_SHIFT                     (8U)
+/*! XIRQ - INDEX/PRESET Pulse Interrupt Request
+ *  0b0..INDEX/PRESET pulse has not occurred
+ *  0b1..INDEX/PRESET pulse has occurred
+ */
+#define EQDC_CTRL_XIRQ(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIRQ_SHIFT)) & EQDC_CTRL_XIRQ_MASK)
+
+#define EQDC_CTRL_PH1_MASK                       (0x200U)
+#define EQDC_CTRL_PH1_SHIFT                      (9U)
+/*! PH1 - Enable Single Phase Mode
+ *  0b0..Standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal.
+ *  0b1..Single phase mode, bypass the quadrature decoder, refer to CTRL2[CMODE] description
+ */
+#define EQDC_CTRL_PH1(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_PH1_SHIFT)) & EQDC_CTRL_PH1_MASK)
+
+#define EQDC_CTRL_REV_MASK                       (0x400U)
+#define EQDC_CTRL_REV_SHIFT                      (10U)
+/*! REV - Enable Reverse Direction Counting
+ *  0b0..Count normally and the position counter initialization uses upper/lower initialization register UINIT/LINIT
+ *  0b1..Count in the reverse direction and the position counter initialization uses upper/lower modulus register UMOD/LMOD
+ */
+#define EQDC_CTRL_REV(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_REV_SHIFT)) & EQDC_CTRL_REV_MASK)
+
+#define EQDC_CTRL_SWIP_MASK                      (0x800U)
+#define EQDC_CTRL_SWIP_SHIFT                     (11U)
+/*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS
+ *  0b0..No action
+ *  0b1..Initialize position counter
+ */
+#define EQDC_CTRL_SWIP(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_SWIP_SHIFT)) & EQDC_CTRL_SWIP_MASK)
+
+#define EQDC_CTRL_HNE_MASK                       (0x1000U)
+#define EQDC_CTRL_HNE_SHIFT                      (12U)
+/*! HNE - Use Negative Edge of HOME/ENABLE Input
+ *  0b0..When CTRL[OPMODE] = 0,use HOME positive edge to trigger initialization of position counters. When
+ *       CTRL[OPMODE] = 1,use ENABLE high level to enable POS/POSD/WDG/REV counters
+ *  0b1..When CTRL[OPMODE] = 0,use HOME negative edge to trigger initialization of position counters. When
+ *       CTRL[OPMODE] = 1,use ENABLE low level to enable POS/POSD/WDG/REV counters
+ */
+#define EQDC_CTRL_HNE(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HNE_SHIFT)) & EQDC_CTRL_HNE_MASK)
+
+#define EQDC_CTRL_HIP_MASK                       (0x2000U)
+#define EQDC_CTRL_HIP_SHIFT                      (13U)
+/*! HIP - Enable HOME to Initialize Position Counter UPOS/LPOS
+ *  0b0..No action
+ *  0b1..HOME signal initializes the position counter
+ */
+#define EQDC_CTRL_HIP(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIP_SHIFT)) & EQDC_CTRL_HIP_MASK)
+
+#define EQDC_CTRL_HIE_MASK                       (0x4000U)
+#define EQDC_CTRL_HIE_SHIFT                      (14U)
+/*! HIE - HOME/ENABLE Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define EQDC_CTRL_HIE(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIE_SHIFT)) & EQDC_CTRL_HIE_MASK)
+
+#define EQDC_CTRL_HIRQ_MASK                      (0x8000U)
+#define EQDC_CTRL_HIRQ_SHIFT                     (15U)
+/*! HIRQ - HOME/ENABLE Signal Transition Interrupt Request
+ *  0b0..No transition on the HOME/ENABLE signal has occurred
+ *  0b1..A transition on the HOME/ENABLE signal has occurred
+ */
+#define EQDC_CTRL_HIRQ(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIRQ_SHIFT)) & EQDC_CTRL_HIRQ_MASK)
+/*! @} */
+
+/*! @name CTRL2 - Control 2 Register */
+/*! @{ */
+
+#define EQDC_CTRL2_UPDHLD_MASK                   (0x1U)
+#define EQDC_CTRL2_UPDHLD_SHIFT                  (0U)
+/*! UPDHLD - Update Hold Registers */
+#define EQDC_CTRL2_UPDHLD(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_UPDHLD_SHIFT)) & EQDC_CTRL2_UPDHLD_MASK)
+
+#define EQDC_CTRL2_UPDPOS_MASK                   (0x2U)
+#define EQDC_CTRL2_UPDPOS_SHIFT                  (1U)
+/*! UPDPOS - Update Position Registers */
+#define EQDC_CTRL2_UPDPOS(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_UPDPOS_SHIFT)) & EQDC_CTRL2_UPDPOS_MASK)
+
+#define EQDC_CTRL2_OPMODE_MASK                   (0x4U)
+#define EQDC_CTRL2_OPMODE_SHIFT                  (2U)
+/*! OPMODE - Operation Mode Select
+ *  0b0..Decode Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to function of INDEX and HOME.
+ *  0b1..Count Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to functions of PRESET and ENABLE. In
+ *       this mode: (1)only when ENABLE=1, all counters (position/position difference/revolution/watchdog) can run,
+ *       when ENABLE=0, all counters (position/position difference/revolution/watchdog) can't run. (2) the rising
+ *       edge of PRESET input can initialize position/revolution/watchdog counters (position counter initialization
+ *       also need referring to bit CTRL[REV]).
+ */
+#define EQDC_CTRL2_OPMODE(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_OPMODE_SHIFT)) & EQDC_CTRL2_OPMODE_MASK)
+
+#define EQDC_CTRL2_LDMOD_MASK                    (0x8U)
+#define EQDC_CTRL2_LDMOD_SHIFT                   (3U)
+/*! LDMOD - Buffered Register Load (Update) Mode Select
+ *  0b0..Buffered registers are loaded and take effect immediately upon CTRL[LDOK] is set.
+ *  0b1..Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
+ */
+#define EQDC_CTRL2_LDMOD(x)                      (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_LDMOD_SHIFT)) & EQDC_CTRL2_LDMOD_MASK)
+
+#define EQDC_CTRL2_REVMOD_MASK                   (0x100U)
+#define EQDC_CTRL2_REVMOD_SHIFT                  (8U)
+/*! REVMOD - Revolution Counter Modulus Enable
+ *  0b0..Use INDEX pulse to increment/decrement revolution counter (REV)
+ *  0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV)
+ */
+#define EQDC_CTRL2_REVMOD(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_REVMOD_SHIFT)) & EQDC_CTRL2_REVMOD_MASK)
+
+#define EQDC_CTRL2_OUTCTL_MASK                   (0x200U)
+#define EQDC_CTRL2_OUTCTL_SHIFT                  (9U)
+/*! OUTCTL - Output Control
+ *  0b0..POS_MATCH[x](x range is 0-3) is asserted when the Position Counter is equal to according compare value
+ *       (UCOMPx/LCOMPx)(x range is 0-3), and de-asserted when the Position Counter not equal to the compare value
+ *       (UCOMPx/LCOMPx)(x range is 0-3)
+ *  0b1..All POS_MATCH[x](x range is 0-3) are asserted a pulse, when the UPOS, LPOS, REV, or POSD registers are read
+ */
+#define EQDC_CTRL2_OUTCTL(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_OUTCTL_SHIFT)) & EQDC_CTRL2_OUTCTL_MASK)
+
+#define EQDC_CTRL2_PMEN_MASK                     (0x400U)
+#define EQDC_CTRL2_PMEN_SHIFT                    (10U)
+/*! PMEN - Period measurement function enable
+ *  0b0..Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS or REV is read.
+ *  0b1..Period measurement functions are used. POSD is loaded into POSDH and then cleared only when POSD is read.
+ */
+#define EQDC_CTRL2_PMEN(x)                       (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_PMEN_SHIFT)) & EQDC_CTRL2_PMEN_MASK)
+
+#define EQDC_CTRL2_EMIP_MASK                     (0x800U)
+#define EQDC_CTRL2_EMIP_SHIFT                    (11U)
+/*! EMIP - Enables/disables the position counter to be initialized by Index Event Edge Mark
+ *  0b0..disables the position counter to be initialized by Index Event Edge Mark
+ *  0b1..enables the position counter to be initialized by Index Event Edge Mark.
+ */
+#define EQDC_CTRL2_EMIP(x)                       (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_EMIP_SHIFT)) & EQDC_CTRL2_EMIP_MASK)
+
+#define EQDC_CTRL2_INITPOS_MASK                  (0x1000U)
+#define EQDC_CTRL2_INITPOS_SHIFT                 (12U)
+/*! INITPOS - Initial Position Register
+ *  0b0..Don't initialize position counter on rising edge of TRIGGER
+ *  0b1..Initialize position counter on rising edge of TRIGGER
+ */
+#define EQDC_CTRL2_INITPOS(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_INITPOS_SHIFT)) & EQDC_CTRL2_INITPOS_MASK)
+
+#define EQDC_CTRL2_ONCE_MASK                     (0x2000U)
+#define EQDC_CTRL2_ONCE_SHIFT                    (13U)
+/*! ONCE - Count Once
+ *  0b0..Position counter counts repeatedly
+ *  0b1..Position counter counts until roll-over or roll-under, then stop.
+ */
+#define EQDC_CTRL2_ONCE(x)                       (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_ONCE_SHIFT)) & EQDC_CTRL2_ONCE_MASK)
+
+#define EQDC_CTRL2_CMODE_MASK                    (0xC000U)
+#define EQDC_CTRL2_CMODE_SHIFT                   (14U)
+/*! CMODE - Counting Mode */
+#define EQDC_CTRL2_CMODE(x)                      (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_CMODE_SHIFT)) & EQDC_CTRL2_CMODE_MASK)
+/*! @} */
+
+/*! @name FILT - Input Filter Register */
+/*! @{ */
+
+#define EQDC_FILT_FILT_PER_MASK                  (0xFFU)
+#define EQDC_FILT_FILT_PER_SHIFT                 (0U)
+/*! FILT_PER - Input Filter Sample Period */
+#define EQDC_FILT_FILT_PER(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_PER_SHIFT)) & EQDC_FILT_FILT_PER_MASK)
+
+#define EQDC_FILT_FILT_CNT_MASK                  (0x700U)
+#define EQDC_FILT_FILT_CNT_SHIFT                 (8U)
+/*! FILT_CNT - Input Filter Sample Count */
+#define EQDC_FILT_FILT_CNT(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_CNT_SHIFT)) & EQDC_FILT_FILT_CNT_MASK)
+
+#define EQDC_FILT_FILT_CS_MASK                   (0x800U)
+#define EQDC_FILT_FILT_CS_SHIFT                  (11U)
+/*! FILT_CS - Filter Clock Source selection
+ *  0b0..Peripheral Clock
+ *  0b1..Prescaled peripheral clock by PRSC
+ */
+#define EQDC_FILT_FILT_CS(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_CS_SHIFT)) & EQDC_FILT_FILT_CS_MASK)
+
+#define EQDC_FILT_PRSC_MASK                      (0xF000U)
+#define EQDC_FILT_PRSC_SHIFT                     (12U)
+/*! PRSC - Prescaler */
+#define EQDC_FILT_PRSC(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_PRSC_SHIFT)) & EQDC_FILT_PRSC_MASK)
+/*! @} */
+
+/*! @name LASTEDGE - Last Edge Time Register */
+/*! @{ */
+
+#define EQDC_LASTEDGE_LASTEDGE_MASK              (0xFFFFU)
+#define EQDC_LASTEDGE_LASTEDGE_SHIFT             (0U)
+/*! LASTEDGE - Last Edge Time Counter */
+#define EQDC_LASTEDGE_LASTEDGE(x)                (((uint16_t)(((uint16_t)(x)) << EQDC_LASTEDGE_LASTEDGE_SHIFT)) & EQDC_LASTEDGE_LASTEDGE_MASK)
+/*! @} */
+
+/*! @name POSDPER - Position Difference Period Counter Register */
+/*! @{ */
+
+#define EQDC_POSDPER_POSDPER_MASK                (0xFFFFU)
+#define EQDC_POSDPER_POSDPER_SHIFT               (0U)
+/*! POSDPER - Position difference period */
+#define EQDC_POSDPER_POSDPER(x)                  (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPER_POSDPER_SHIFT)) & EQDC_POSDPER_POSDPER_MASK)
+/*! @} */
+
+/*! @name POSDPERBFR - Position Difference Period Buffer Register */
+/*! @{ */
+
+#define EQDC_POSDPERBFR_POSDPERBFR_MASK          (0xFFFFU)
+#define EQDC_POSDPERBFR_POSDPERBFR_SHIFT         (0U)
+/*! POSDPERBFR - Position difference period buffer */
+#define EQDC_POSDPERBFR_POSDPERBFR(x)            (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPERBFR_POSDPERBFR_SHIFT)) & EQDC_POSDPERBFR_POSDPERBFR_MASK)
+/*! @} */
+
+/*! @name UPOS - Upper Position Counter Register */
+/*! @{ */
+
+#define EQDC_UPOS_POS_MASK                       (0xFFFFU)
+#define EQDC_UPOS_POS_SHIFT                      (0U)
+/*! POS - POS */
+#define EQDC_UPOS_POS(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_UPOS_POS_SHIFT)) & EQDC_UPOS_POS_MASK)
+/*! @} */
+
+/*! @name LPOS - Lower Position Counter Register */
+/*! @{ */
+
+#define EQDC_LPOS_POS_MASK                       (0xFFFFU)
+#define EQDC_LPOS_POS_SHIFT                      (0U)
+/*! POS - POS */
+#define EQDC_LPOS_POS(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_LPOS_POS_SHIFT)) & EQDC_LPOS_POS_MASK)
+/*! @} */
+
+/*! @name POSD - Position Difference Counter Register */
+/*! @{ */
+
+#define EQDC_POSD_POSD_MASK                      (0xFFFFU)
+#define EQDC_POSD_POSD_SHIFT                     (0U)
+/*! POSD - POSD */
+#define EQDC_POSD_POSD(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_POSD_POSD_SHIFT)) & EQDC_POSD_POSD_MASK)
+/*! @} */
+
+/*! @name POSDH - Position Difference Hold Register */
+/*! @{ */
+
+#define EQDC_POSDH_POSDH_MASK                    (0xFFFFU)
+#define EQDC_POSDH_POSDH_SHIFT                   (0U)
+/*! POSDH - POSDH */
+#define EQDC_POSDH_POSDH(x)                      (((uint16_t)(((uint16_t)(x)) << EQDC_POSDH_POSDH_SHIFT)) & EQDC_POSDH_POSDH_MASK)
+/*! @} */
+
+/*! @name UPOSH - Upper Position Hold Register */
+/*! @{ */
+
+#define EQDC_UPOSH_POSH_MASK                     (0xFFFFU)
+#define EQDC_UPOSH_POSH_SHIFT                    (0U)
+/*! POSH - POSH */
+#define EQDC_UPOSH_POSH(x)                       (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH_POSH_SHIFT)) & EQDC_UPOSH_POSH_MASK)
+/*! @} */
+
+/*! @name LPOSH - Lower Position Hold Register */
+/*! @{ */
+
+#define EQDC_LPOSH_LPOSH_MASK                    (0xFFFFU)
+#define EQDC_LPOSH_LPOSH_SHIFT                   (0U)
+/*! LPOSH - POSH */
+#define EQDC_LPOSH_LPOSH(x)                      (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH_LPOSH_SHIFT)) & EQDC_LPOSH_LPOSH_MASK)
+/*! @} */
+
+/*! @name LASTEDGEH - Last Edge Time Hold Register */
+/*! @{ */
+
+#define EQDC_LASTEDGEH_LASTEDGEH_MASK            (0xFFFFU)
+#define EQDC_LASTEDGEH_LASTEDGEH_SHIFT           (0U)
+/*! LASTEDGEH - Last Edge Time Hold */
+#define EQDC_LASTEDGEH_LASTEDGEH(x)              (((uint16_t)(((uint16_t)(x)) << EQDC_LASTEDGEH_LASTEDGEH_SHIFT)) & EQDC_LASTEDGEH_LASTEDGEH_MASK)
+/*! @} */
+
+/*! @name POSDPERH - Position Difference Period Hold Register */
+/*! @{ */
+
+#define EQDC_POSDPERH_POSDPERH_MASK              (0xFFFFU)
+#define EQDC_POSDPERH_POSDPERH_SHIFT             (0U)
+/*! POSDPERH - Position difference period hold */
+#define EQDC_POSDPERH_POSDPERH(x)                (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPERH_POSDPERH_SHIFT)) & EQDC_POSDPERH_POSDPERH_MASK)
+/*! @} */
+
+/*! @name REVH - Revolution Hold Register */
+/*! @{ */
+
+#define EQDC_REVH_REVH_MASK                      (0xFFFFU)
+#define EQDC_REVH_REVH_SHIFT                     (0U)
+/*! REVH - REVH */
+#define EQDC_REVH_REVH(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_REVH_REVH_SHIFT)) & EQDC_REVH_REVH_MASK)
+/*! @} */
+
+/*! @name REV - Revolution Counter Register */
+/*! @{ */
+
+#define EQDC_REV_REV_MASK                        (0xFFFFU)
+#define EQDC_REV_REV_SHIFT                       (0U)
+/*! REV - REV */
+#define EQDC_REV_REV(x)                          (((uint16_t)(((uint16_t)(x)) << EQDC_REV_REV_SHIFT)) & EQDC_REV_REV_MASK)
+/*! @} */
+
+/*! @name UINIT - Upper Initialization Register */
+/*! @{ */
+
+#define EQDC_UINIT_INIT_MASK                     (0xFFFFU)
+#define EQDC_UINIT_INIT_SHIFT                    (0U)
+/*! INIT - INIT */
+#define EQDC_UINIT_INIT(x)                       (((uint16_t)(((uint16_t)(x)) << EQDC_UINIT_INIT_SHIFT)) & EQDC_UINIT_INIT_MASK)
+/*! @} */
+
+/*! @name LINIT - Lower Initialization Register */
+/*! @{ */
+
+#define EQDC_LINIT_INIT_MASK                     (0xFFFFU)
+#define EQDC_LINIT_INIT_SHIFT                    (0U)
+/*! INIT - INIT */
+#define EQDC_LINIT_INIT(x)                       (((uint16_t)(((uint16_t)(x)) << EQDC_LINIT_INIT_SHIFT)) & EQDC_LINIT_INIT_MASK)
+/*! @} */
+
+/*! @name UMOD - Upper Modulus Register */
+/*! @{ */
+
+#define EQDC_UMOD_MOD_MASK                       (0xFFFFU)
+#define EQDC_UMOD_MOD_SHIFT                      (0U)
+/*! MOD - MOD */
+#define EQDC_UMOD_MOD(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_UMOD_MOD_SHIFT)) & EQDC_UMOD_MOD_MASK)
+/*! @} */
+
+/*! @name LMOD - Lower Modulus Register */
+/*! @{ */
+
+#define EQDC_LMOD_MOD_MASK                       (0xFFFFU)
+#define EQDC_LMOD_MOD_SHIFT                      (0U)
+/*! MOD - MOD */
+#define EQDC_LMOD_MOD(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_LMOD_MOD_SHIFT)) & EQDC_LMOD_MOD_MASK)
+/*! @} */
+
+/*! @name UCOMP0 - Upper Position Compare Register 0 */
+/*! @{ */
+
+#define EQDC_UCOMP0_UCOMP0_MASK                  (0xFFFFU)
+#define EQDC_UCOMP0_UCOMP0_SHIFT                 (0U)
+/*! UCOMP0 - UCOMP0 */
+#define EQDC_UCOMP0_UCOMP0(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP0_UCOMP0_SHIFT)) & EQDC_UCOMP0_UCOMP0_MASK)
+/*! @} */
+
+/*! @name LCOMP0 - Lower Position Compare Register 0 */
+/*! @{ */
+
+#define EQDC_LCOMP0_LCOMP0_MASK                  (0xFFFFU)
+#define EQDC_LCOMP0_LCOMP0_SHIFT                 (0U)
+/*! LCOMP0 - LCOMP0 */
+#define EQDC_LCOMP0_LCOMP0(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP0_LCOMP0_SHIFT)) & EQDC_LCOMP0_LCOMP0_MASK)
+/*! @} */
+
+/*! @name UCOMP1 - Upper Position Compare 1 */
+/*! @{ */
+
+#define EQDC_UCOMP1_UCOMP1_MASK                  (0xFFFFU)
+#define EQDC_UCOMP1_UCOMP1_SHIFT                 (0U)
+/*! UCOMP1 - UCOMP1 */
+#define EQDC_UCOMP1_UCOMP1(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP1_UCOMP1_SHIFT)) & EQDC_UCOMP1_UCOMP1_MASK)
+/*! @} */
+
+/*! @name UPOSH1 - Upper Position Holder Register 1 */
+/*! @{ */
+
+#define EQDC_UPOSH1_UPOSH1_MASK                  (0xFFFFU)
+#define EQDC_UPOSH1_UPOSH1_SHIFT                 (0U)
+/*! UPOSH1 - UPOSH1 */
+#define EQDC_UPOSH1_UPOSH1(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH1_UPOSH1_SHIFT)) & EQDC_UPOSH1_UPOSH1_MASK)
+/*! @} */
+
+/*! @name LCOMP1 - Lower Position Compare 1 */
+/*! @{ */
+
+#define EQDC_LCOMP1_LCOMP1_MASK                  (0xFFFFU)
+#define EQDC_LCOMP1_LCOMP1_SHIFT                 (0U)
+/*! LCOMP1 - LCOMP1 */
+#define EQDC_LCOMP1_LCOMP1(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP1_LCOMP1_SHIFT)) & EQDC_LCOMP1_LCOMP1_MASK)
+/*! @} */
+
+/*! @name LPOSH1 - Lower Position Holder Register 1 */
+/*! @{ */
+
+#define EQDC_LPOSH1_LPOSH1_MASK                  (0xFFFFU)
+#define EQDC_LPOSH1_LPOSH1_SHIFT                 (0U)
+/*! LPOSH1 - LPOSH1 */
+#define EQDC_LPOSH1_LPOSH1(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH1_LPOSH1_SHIFT)) & EQDC_LPOSH1_LPOSH1_MASK)
+/*! @} */
+
+/*! @name UCOMP2 - Upper Position Compare 2 */
+/*! @{ */
+
+#define EQDC_UCOMP2_UCOMP2_MASK                  (0xFFFFU)
+#define EQDC_UCOMP2_UCOMP2_SHIFT                 (0U)
+/*! UCOMP2 - UCOMP2 */
+#define EQDC_UCOMP2_UCOMP2(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP2_UCOMP2_SHIFT)) & EQDC_UCOMP2_UCOMP2_MASK)
+/*! @} */
+
+/*! @name UPOSH2 - Upper Position Holder Register 3 */
+/*! @{ */
+
+#define EQDC_UPOSH2_UPOSH2_MASK                  (0xFFFFU)
+#define EQDC_UPOSH2_UPOSH2_SHIFT                 (0U)
+/*! UPOSH2 - UPOSH2 */
+#define EQDC_UPOSH2_UPOSH2(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH2_UPOSH2_SHIFT)) & EQDC_UPOSH2_UPOSH2_MASK)
+/*! @} */
+
+/*! @name LCOMP2 - Lower Position Compare 2 */
+/*! @{ */
+
+#define EQDC_LCOMP2_LCOMP2_MASK                  (0xFFFFU)
+#define EQDC_LCOMP2_LCOMP2_SHIFT                 (0U)
+/*! LCOMP2 - LCOMP2 */
+#define EQDC_LCOMP2_LCOMP2(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP2_LCOMP2_SHIFT)) & EQDC_LCOMP2_LCOMP2_MASK)
+/*! @} */
+
+/*! @name LPOSH2 - Lower Position Holder Register 2 */
+/*! @{ */
+
+#define EQDC_LPOSH2_LPOSH2_MASK                  (0xFFFFU)
+#define EQDC_LPOSH2_LPOSH2_SHIFT                 (0U)
+/*! LPOSH2 - LPOSH2 */
+#define EQDC_LPOSH2_LPOSH2(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH2_LPOSH2_SHIFT)) & EQDC_LPOSH2_LPOSH2_MASK)
+/*! @} */
+
+/*! @name UCOMP3 - Upper Position Compare 3 */
+/*! @{ */
+
+#define EQDC_UCOMP3_UCOMP3_MASK                  (0xFFFFU)
+#define EQDC_UCOMP3_UCOMP3_SHIFT                 (0U)
+/*! UCOMP3 - UCOMP3 */
+#define EQDC_UCOMP3_UCOMP3(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP3_UCOMP3_SHIFT)) & EQDC_UCOMP3_UCOMP3_MASK)
+/*! @} */
+
+/*! @name UPOSH3 - Upper Position Holder Register 3 */
+/*! @{ */
+
+#define EQDC_UPOSH3_UPOSH3_MASK                  (0xFFFFU)
+#define EQDC_UPOSH3_UPOSH3_SHIFT                 (0U)
+/*! UPOSH3 - UPOSH3 */
+#define EQDC_UPOSH3_UPOSH3(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH3_UPOSH3_SHIFT)) & EQDC_UPOSH3_UPOSH3_MASK)
+/*! @} */
+
+/*! @name LCOMP3 - Lower Position Compare 3 */
+/*! @{ */
+
+#define EQDC_LCOMP3_LCOMP3_MASK                  (0xFFFFU)
+#define EQDC_LCOMP3_LCOMP3_SHIFT                 (0U)
+/*! LCOMP3 - LCOMP3 */
+#define EQDC_LCOMP3_LCOMP3(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP3_LCOMP3_SHIFT)) & EQDC_LCOMP3_LCOMP3_MASK)
+/*! @} */
+
+/*! @name LPOSH3 - Lower Position Holder Register 3 */
+/*! @{ */
+
+#define EQDC_LPOSH3_LPOSH3_MASK                  (0xFFFFU)
+#define EQDC_LPOSH3_LPOSH3_SHIFT                 (0U)
+/*! LPOSH3 - LPOSH3 */
+#define EQDC_LPOSH3_LPOSH3(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH3_LPOSH3_SHIFT)) & EQDC_LPOSH3_LPOSH3_MASK)
+/*! @} */
+
+/*! @name INTCTRL - Interrupt Control Register */
+/*! @{ */
+
+#define EQDC_INTCTRL_SABIE_MASK                  (0x1U)
+#define EQDC_INTCTRL_SABIE_SHIFT                 (0U)
+/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define EQDC_INTCTRL_SABIE(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_SABIE_SHIFT)) & EQDC_INTCTRL_SABIE_MASK)
+
+#define EQDC_INTCTRL_SABIRQ_MASK                 (0x2U)
+#define EQDC_INTCTRL_SABIRQ_SHIFT                (1U)
+/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request
+ *  0b0..No simultaneous change of PHASEA and PHASEB has occurred
+ *  0b1..A simultaneous change of PHASEA and PHASEB has occurred
+ */
+#define EQDC_INTCTRL_SABIRQ(x)                   (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_SABIRQ_SHIFT)) & EQDC_INTCTRL_SABIRQ_MASK)
+
+#define EQDC_INTCTRL_DIRIE_MASK                  (0x4U)
+#define EQDC_INTCTRL_DIRIE_SHIFT                 (2U)
+/*! DIRIE - Count direction change interrupt enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define EQDC_INTCTRL_DIRIE(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_DIRIE_SHIFT)) & EQDC_INTCTRL_DIRIE_MASK)
+
+#define EQDC_INTCTRL_DIRIRQ_MASK                 (0x8U)
+#define EQDC_INTCTRL_DIRIRQ_SHIFT                (3U)
+/*! DIRIRQ - Count direction change interrupt
+ *  0b0..Count direction unchanged
+ *  0b1..Count direction changed
+ */
+#define EQDC_INTCTRL_DIRIRQ(x)                   (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_DIRIRQ_SHIFT)) & EQDC_INTCTRL_DIRIRQ_MASK)
+
+#define EQDC_INTCTRL_RUIE_MASK                   (0x10U)
+#define EQDC_INTCTRL_RUIE_SHIFT                  (4U)
+/*! RUIE - Roll-under Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define EQDC_INTCTRL_RUIE(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_RUIE_SHIFT)) & EQDC_INTCTRL_RUIE_MASK)
+
+#define EQDC_INTCTRL_RUIRQ_MASK                  (0x20U)
+#define EQDC_INTCTRL_RUIRQ_SHIFT                 (5U)
+/*! RUIRQ - Roll-under Interrupt Request
+ *  0b0..No roll-under has occurred
+ *  0b1..Roll-under has occurred
+ */
+#define EQDC_INTCTRL_RUIRQ(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_RUIRQ_SHIFT)) & EQDC_INTCTRL_RUIRQ_MASK)
+
+#define EQDC_INTCTRL_ROIE_MASK                   (0x40U)
+#define EQDC_INTCTRL_ROIE_SHIFT                  (6U)
+/*! ROIE - Roll-over Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define EQDC_INTCTRL_ROIE(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_ROIE_SHIFT)) & EQDC_INTCTRL_ROIE_MASK)
+
+#define EQDC_INTCTRL_ROIRQ_MASK                  (0x80U)
+#define EQDC_INTCTRL_ROIRQ_SHIFT                 (7U)
+/*! ROIRQ - Roll-over Interrupt Request
+ *  0b0..No roll-over has occurred
+ *  0b1..Roll-over has occurred
+ */
+#define EQDC_INTCTRL_ROIRQ(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_ROIRQ_SHIFT)) & EQDC_INTCTRL_ROIRQ_MASK)
+
+#define EQDC_INTCTRL_CMP0IE_MASK                 (0x100U)
+#define EQDC_INTCTRL_CMP0IE_SHIFT                (8U)
+/*! CMP0IE - Compare 0 Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define EQDC_INTCTRL_CMP0IE(x)                   (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP0IE_SHIFT)) & EQDC_INTCTRL_CMP0IE_MASK)
+
+#define EQDC_INTCTRL_CMP0IRQ_MASK                (0x200U)
+#define EQDC_INTCTRL_CMP0IRQ_SHIFT               (9U)
+/*! CMP0IRQ - Compare 0 Interrupt Request
+ *  0b0..No match has occurred (the position counter does not match the COMP0 value)
+ *  0b1..COMP match has occurred (the position counter matches the COMP0 value)
+ */
+#define EQDC_INTCTRL_CMP0IRQ(x)                  (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP0IRQ_SHIFT)) & EQDC_INTCTRL_CMP0IRQ_MASK)
+
+#define EQDC_INTCTRL_CMP1IE_MASK                 (0x400U)
+#define EQDC_INTCTRL_CMP1IE_SHIFT                (10U)
+/*! CMP1IE - Compare1 Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define EQDC_INTCTRL_CMP1IE(x)                   (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP1IE_SHIFT)) & EQDC_INTCTRL_CMP1IE_MASK)
+
+#define EQDC_INTCTRL_CMP1IRQ_MASK                (0x800U)
+#define EQDC_INTCTRL_CMP1IRQ_SHIFT               (11U)
+/*! CMP1IRQ - Compare1 Interrupt Request
+ *  0b0..No match has occurred (the position counter does not match the COMP1 value)
+ *  0b1..COMP1 match has occurred (the position counter matches the COMP1 value)
+ */
+#define EQDC_INTCTRL_CMP1IRQ(x)                  (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP1IRQ_SHIFT)) & EQDC_INTCTRL_CMP1IRQ_MASK)
+
+#define EQDC_INTCTRL_CMP2IE_MASK                 (0x1000U)
+#define EQDC_INTCTRL_CMP2IE_SHIFT                (12U)
+/*! CMP2IE - Compare2 Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define EQDC_INTCTRL_CMP2IE(x)                   (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP2IE_SHIFT)) & EQDC_INTCTRL_CMP2IE_MASK)
+
+#define EQDC_INTCTRL_CMP2IRQ_MASK                (0x2000U)
+#define EQDC_INTCTRL_CMP2IRQ_SHIFT               (13U)
+/*! CMP2IRQ - Compare2 Interrupt Request
+ *  0b0..No match has occurred (the position counter does not match the COMP2 value)
+ *  0b1..COMP2 match has occurred (the position counter matches the COMP2 value)
+ */
+#define EQDC_INTCTRL_CMP2IRQ(x)                  (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP2IRQ_SHIFT)) & EQDC_INTCTRL_CMP2IRQ_MASK)
+
+#define EQDC_INTCTRL_CMP3IE_MASK                 (0x4000U)
+#define EQDC_INTCTRL_CMP3IE_SHIFT                (14U)
+/*! CMP3IE - Compare3 Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define EQDC_INTCTRL_CMP3IE(x)                   (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP3IE_SHIFT)) & EQDC_INTCTRL_CMP3IE_MASK)
+
+#define EQDC_INTCTRL_CMP3IRQ_MASK                (0x8000U)
+#define EQDC_INTCTRL_CMP3IRQ_SHIFT               (15U)
+/*! CMP3IRQ - Compare3 Interrupt Request
+ *  0b0..No match has occurred (the position counter does not match the COMP3 value)
+ *  0b1..COMP3 match has occurred (the position counter matches the COMP3 value)
+ */
+#define EQDC_INTCTRL_CMP3IRQ(x)                  (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP3IRQ_SHIFT)) & EQDC_INTCTRL_CMP3IRQ_MASK)
+/*! @} */
+
+/*! @name WTR - Watchdog Timeout Register */
+/*! @{ */
+
+#define EQDC_WTR_WDOG_MASK                       (0xFFFFU)
+#define EQDC_WTR_WDOG_SHIFT                      (0U)
+/*! WDOG - WDOG */
+#define EQDC_WTR_WDOG(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_WTR_WDOG_SHIFT)) & EQDC_WTR_WDOG_MASK)
+/*! @} */
+
+/*! @name IMR - Input Monitor Register */
+/*! @{ */
+
+#define EQDC_IMR_HOME_ENABLE_MASK                (0x1U)
+#define EQDC_IMR_HOME_ENABLE_SHIFT               (0U)
+/*! HOME_ENABLE - HOME_ENABLE */
+#define EQDC_IMR_HOME_ENABLE(x)                  (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_HOME_ENABLE_SHIFT)) & EQDC_IMR_HOME_ENABLE_MASK)
+
+#define EQDC_IMR_INDEX_PRESET_MASK               (0x2U)
+#define EQDC_IMR_INDEX_PRESET_SHIFT              (1U)
+/*! INDEX_PRESET - INDEX_PRESET */
+#define EQDC_IMR_INDEX_PRESET(x)                 (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_INDEX_PRESET_SHIFT)) & EQDC_IMR_INDEX_PRESET_MASK)
+
+#define EQDC_IMR_PHB_MASK                        (0x4U)
+#define EQDC_IMR_PHB_SHIFT                       (2U)
+/*! PHB - PHB */
+#define EQDC_IMR_PHB(x)                          (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_PHB_SHIFT)) & EQDC_IMR_PHB_MASK)
+
+#define EQDC_IMR_PHA_MASK                        (0x8U)
+#define EQDC_IMR_PHA_SHIFT                       (3U)
+/*! PHA - PHA */
+#define EQDC_IMR_PHA(x)                          (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_PHA_SHIFT)) & EQDC_IMR_PHA_MASK)
+
+#define EQDC_IMR_FHOM_ENA_MASK                   (0x10U)
+#define EQDC_IMR_FHOM_ENA_SHIFT                  (4U)
+/*! FHOM_ENA - filter operation on HOME/ENABLE input */
+#define EQDC_IMR_FHOM_ENA(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FHOM_ENA_SHIFT)) & EQDC_IMR_FHOM_ENA_MASK)
+
+#define EQDC_IMR_FIND_PRE_MASK                   (0x20U)
+#define EQDC_IMR_FIND_PRE_SHIFT                  (5U)
+/*! FIND_PRE - filter operation on INDEX/PRESET input */
+#define EQDC_IMR_FIND_PRE(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FIND_PRE_SHIFT)) & EQDC_IMR_FIND_PRE_MASK)
+
+#define EQDC_IMR_FPHB_MASK                       (0x40U)
+#define EQDC_IMR_FPHB_SHIFT                      (6U)
+/*! FPHB - filter operation on PHASEB input */
+#define EQDC_IMR_FPHB(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FPHB_SHIFT)) & EQDC_IMR_FPHB_MASK)
+
+#define EQDC_IMR_FPHA_MASK                       (0x80U)
+#define EQDC_IMR_FPHA_SHIFT                      (7U)
+/*! FPHA - filter operation on PHASEA input */
+#define EQDC_IMR_FPHA(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FPHA_SHIFT)) & EQDC_IMR_FPHA_MASK)
+
+#define EQDC_IMR_CMPF0_MASK                      (0x100U)
+#define EQDC_IMR_CMPF0_SHIFT                     (8U)
+/*! CMPF0 - Position Compare 0 Flag Output
+ *  0b0..When the position counter is less than value of COMP0 register
+ *  0b1..When the position counter is greater or equal than value of COMP0 register
+ */
+#define EQDC_IMR_CMPF0(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMPF0_SHIFT)) & EQDC_IMR_CMPF0_MASK)
+
+#define EQDC_IMR_CMP1F_MASK                      (0x200U)
+#define EQDC_IMR_CMP1F_SHIFT                     (9U)
+/*! CMP1F - Position Compare1 Flag Output
+ *  0b0..When the position counter is less than value of COMP1 register
+ *  0b1..When the position counter is greater or equal than value of COMP1 register
+ */
+#define EQDC_IMR_CMP1F(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP1F_SHIFT)) & EQDC_IMR_CMP1F_MASK)
+
+#define EQDC_IMR_CMP2F_MASK                      (0x400U)
+#define EQDC_IMR_CMP2F_SHIFT                     (10U)
+/*! CMP2F - Position Compare2 Flag Output
+ *  0b0..When the position counter is less than value of COMP2 register
+ *  0b1..When the position counter is greater or equal than value of COMP2 register
+ */
+#define EQDC_IMR_CMP2F(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP2F_SHIFT)) & EQDC_IMR_CMP2F_MASK)
+
+#define EQDC_IMR_CMP3F_MASK                      (0x800U)
+#define EQDC_IMR_CMP3F_SHIFT                     (11U)
+/*! CMP3F - Position Compare3 Flag Output
+ *  0b0..When the position counter value is less than value of COMP3 register
+ *  0b1..When the position counter is greater or equal than value of COMP3 register
+ */
+#define EQDC_IMR_CMP3F(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP3F_SHIFT)) & EQDC_IMR_CMP3F_MASK)
+
+#define EQDC_IMR_DIRH_MASK                       (0x4000U)
+#define EQDC_IMR_DIRH_SHIFT                      (14U)
+/*! DIRH - Count Direction Flag Hold */
+#define EQDC_IMR_DIRH(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_DIRH_SHIFT)) & EQDC_IMR_DIRH_MASK)
+
+#define EQDC_IMR_DIR_MASK                        (0x8000U)
+#define EQDC_IMR_DIR_SHIFT                       (15U)
+/*! DIR - Count Direction Flag Output
+ *  0b0..Current count was in the down direction
+ *  0b1..Current count was in the up direction
+ */
+#define EQDC_IMR_DIR(x)                          (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_DIR_SHIFT)) & EQDC_IMR_DIR_MASK)
+/*! @} */
+
+/*! @name TST - Test Register */
+/*! @{ */
+
+#define EQDC_TST_TEST_COUNT_MASK                 (0xFFU)
+#define EQDC_TST_TEST_COUNT_SHIFT                (0U)
+/*! TEST_COUNT - TEST_COUNT */
+#define EQDC_TST_TEST_COUNT(x)                   (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEST_COUNT_SHIFT)) & EQDC_TST_TEST_COUNT_MASK)
+
+#define EQDC_TST_TEST_PERIOD_MASK                (0x1F00U)
+#define EQDC_TST_TEST_PERIOD_SHIFT               (8U)
+/*! TEST_PERIOD - TEST_PERIOD */
+#define EQDC_TST_TEST_PERIOD(x)                  (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEST_PERIOD_SHIFT)) & EQDC_TST_TEST_PERIOD_MASK)
+
+#define EQDC_TST_QDN_MASK                        (0x2000U)
+#define EQDC_TST_QDN_SHIFT                       (13U)
+/*! QDN - Quadrature Decoder Negative Signal
+ *  0b0..Generates a positive quadrature decoder signal
+ *  0b1..Generates a negative quadrature decoder signal
+ */
+#define EQDC_TST_QDN(x)                          (((uint16_t)(((uint16_t)(x)) << EQDC_TST_QDN_SHIFT)) & EQDC_TST_QDN_MASK)
+
+#define EQDC_TST_TCE_MASK                        (0x4000U)
+#define EQDC_TST_TCE_SHIFT                       (14U)
+/*! TCE - Test Counter Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define EQDC_TST_TCE(x)                          (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TCE_SHIFT)) & EQDC_TST_TCE_MASK)
+
+#define EQDC_TST_TEN_MASK                        (0x8000U)
+#define EQDC_TST_TEN_SHIFT                       (15U)
+/*! TEN - Test Mode Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define EQDC_TST_TEN(x)                          (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEN_SHIFT)) & EQDC_TST_TEN_MASK)
+/*! @} */
+
+/*! @name UVERID - Upper VERID */
+/*! @{ */
+
+#define EQDC_UVERID_UVERID_MASK                  (0xFFFFU)
+#define EQDC_UVERID_UVERID_SHIFT                 (0U)
+/*! UVERID - UVERID */
+#define EQDC_UVERID_UVERID(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_UVERID_UVERID_SHIFT)) & EQDC_UVERID_UVERID_MASK)
+/*! @} */
+
+/*! @name LVERID - Lower VERID */
+/*! @{ */
+
+#define EQDC_LVERID_LVERID_MASK                  (0xFFFFU)
+#define EQDC_LVERID_LVERID_SHIFT                 (0U)
+/*! LVERID - LVERID */
+#define EQDC_LVERID_LVERID(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_LVERID_LVERID_SHIFT)) & EQDC_LVERID_LVERID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group EQDC_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group EQDC_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_EQDC_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_ERM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_ERM.h
new file mode 100644
index 0000000000..5d288ec862
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_ERM.h
@@ -0,0 +1,300 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for ERM
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_ERM.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for ERM
+ *
+ * CMSIS Peripheral Access Layer for ERM
+ */
+
+#if !defined(PERI_ERM_H_)
+#define PERI_ERM_H_                              /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+#if !defined(ERM_MEMORY_CHANNEL_T_)
+#define ERM_MEMORY_CHANNEL_T_
+/*!
+ * @addtogroup erm_memory_channel
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the erm_memory_channel
+ *
+ * Defines the structure for the ERM resource collections.
+ */
+
+typedef enum _erm_memory_channel
+{
+    kERM_MemoryChannelRAMA0         = 0U,          /**< Memory RAMA0 */
+    kERM_MemoryChannelFLASH         = 1U,          /**< Memory FLASH */
+} erm_memory_channel_t;
+
+/* @} */
+#endif /* ERM_MEMORY_CHANNEL_T_ */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ERM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ERM_Peripheral_Access_Layer ERM Peripheral Access Layer
+ * @{
+ */
+
+/** ERM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR0;                               /**< ERM Configuration Register 0, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t SR0;                               /**< ERM Status Register 0, offset: 0x10 */
+       uint8_t RESERVED_1[236];
+  __I  uint32_t EAR0;                              /**< ERM Memory 0 Error Address Register, offset: 0x100 */
+  __I  uint32_t SYN0;                              /**< ERM Memory 0 Syndrome Register, offset: 0x104 */
+  __IO uint32_t CORR_ERR_CNT0;                     /**< ERM Memory 0 Correctable Error Count Register, offset: 0x108 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t CORR_ERR_CNT1;                     /**< ERM Memory 1 Correctable Error Count Register, offset: 0x118 */
+} ERM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ERM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ERM_Register_Masks ERM Register Masks
+ * @{
+ */
+
+/*! @name CR0 - ERM Configuration Register 0 */
+/*! @{ */
+
+#define ERM_CR0_ENCIE1_MASK                      (0x4000000U)
+#define ERM_CR0_ENCIE1_SHIFT                     (26U)
+/*! ENCIE1 - ENCIE1
+ *  0b0..Interrupt notification of Memory 1 non-correctable error events is disabled.
+ *  0b1..Interrupt notification of Memory 1 non-correctable error events is enabled.
+ */
+#define ERM_CR0_ENCIE1(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE1_SHIFT)) & ERM_CR0_ENCIE1_MASK)
+
+#define ERM_CR0_ESCIE1_MASK                      (0x8000000U)
+#define ERM_CR0_ESCIE1_SHIFT                     (27U)
+/*! ESCIE1 - ESCIE1
+ *  0b0..Interrupt notification of Memory 1 single-bit correction events is disabled.
+ *  0b1..Interrupt notification of Memory 1 single-bit correction events is enabled.
+ */
+#define ERM_CR0_ESCIE1(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE1_SHIFT)) & ERM_CR0_ESCIE1_MASK)
+
+#define ERM_CR0_ENCIE0_MASK                      (0x40000000U)
+#define ERM_CR0_ENCIE0_SHIFT                     (30U)
+/*! ENCIE0 - ENCIE0
+ *  0b0..Interrupt notification of Memory 0 non-correctable error events is disabled.
+ *  0b1..Interrupt notification of Memory 0 non-correctable error events is enabled.
+ */
+#define ERM_CR0_ENCIE0(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE0_SHIFT)) & ERM_CR0_ENCIE0_MASK)
+
+#define ERM_CR0_ESCIE0_MASK                      (0x80000000U)
+#define ERM_CR0_ESCIE0_SHIFT                     (31U)
+/*! ESCIE0 - ESCIE0
+ *  0b0..Interrupt notification of Memory 0 single-bit correction events is disabled.
+ *  0b1..Interrupt notification of Memory 0 single-bit correction events is enabled.
+ */
+#define ERM_CR0_ESCIE0(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE0_SHIFT)) & ERM_CR0_ESCIE0_MASK)
+/*! @} */
+
+/*! @name SR0 - ERM Status Register 0 */
+/*! @{ */
+
+#define ERM_SR0_NCE1_MASK                        (0x4000000U)
+#define ERM_SR0_NCE1_SHIFT                       (26U)
+/*! NCE1 - NCE1
+ *  0b0..No non-correctable error event on Memory 1 detected.
+ *  0b1..Non-correctable error event on Memory 1 detected.
+ */
+#define ERM_SR0_NCE1(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE1_SHIFT)) & ERM_SR0_NCE1_MASK)
+
+#define ERM_SR0_SBC1_MASK                        (0x8000000U)
+#define ERM_SR0_SBC1_SHIFT                       (27U)
+/*! SBC1 - SBC1
+ *  0b0..No single-bit correction event on Memory 1 detected.
+ *  0b1..Single-bit correction event on Memory 1 detected.
+ */
+#define ERM_SR0_SBC1(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC1_SHIFT)) & ERM_SR0_SBC1_MASK)
+
+#define ERM_SR0_NCE0_MASK                        (0x40000000U)
+#define ERM_SR0_NCE0_SHIFT                       (30U)
+/*! NCE0 - NCE0
+ *  0b0..No non-correctable error event on Memory 0 detected.
+ *  0b1..Non-correctable error event on Memory 0 detected.
+ */
+#define ERM_SR0_NCE0(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE0_SHIFT)) & ERM_SR0_NCE0_MASK)
+
+#define ERM_SR0_SBC0_MASK                        (0x80000000U)
+#define ERM_SR0_SBC0_SHIFT                       (31U)
+/*! SBC0 - SBC0
+ *  0b0..No single-bit correction event on Memory 0 detected.
+ *  0b1..Single-bit correction event on Memory 0 detected.
+ */
+#define ERM_SR0_SBC0(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC0_SHIFT)) & ERM_SR0_SBC0_MASK)
+/*! @} */
+
+/*! @name EAR0 - ERM Memory 0 Error Address Register */
+/*! @{ */
+
+#define ERM_EAR0_EAR_MASK                        (0xFFFFFFFFU)
+#define ERM_EAR0_EAR_SHIFT                       (0U)
+/*! EAR - EAR */
+#define ERM_EAR0_EAR(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_EAR0_EAR_SHIFT)) & ERM_EAR0_EAR_MASK)
+/*! @} */
+
+/*! @name SYN0 - ERM Memory 0 Syndrome Register */
+/*! @{ */
+
+#define ERM_SYN0_SYNDROME_MASK                   (0xFF000000U)
+#define ERM_SYN0_SYNDROME_SHIFT                  (24U)
+/*! SYNDROME - SYNDROME */
+#define ERM_SYN0_SYNDROME(x)                     (((uint32_t)(((uint32_t)(x)) << ERM_SYN0_SYNDROME_SHIFT)) & ERM_SYN0_SYNDROME_MASK)
+/*! @} */
+
+/*! @name CORR_ERR_CNT0 - ERM Memory 0 Correctable Error Count Register */
+/*! @{ */
+
+#define ERM_CORR_ERR_CNT0_COUNT_MASK             (0xFFU)
+#define ERM_CORR_ERR_CNT0_COUNT_SHIFT            (0U)
+/*! COUNT - Memory n Correctable Error Count */
+#define ERM_CORR_ERR_CNT0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT0_COUNT_SHIFT)) & ERM_CORR_ERR_CNT0_COUNT_MASK)
+/*! @} */
+
+/*! @name CORR_ERR_CNT1 - ERM Memory 1 Correctable Error Count Register */
+/*! @{ */
+
+#define ERM_CORR_ERR_CNT1_COUNT_MASK             (0xFFU)
+#define ERM_CORR_ERR_CNT1_COUNT_SHIFT            (0U)
+/*! COUNT - Memory n Correctable Error Count */
+#define ERM_CORR_ERR_CNT1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT1_COUNT_SHIFT)) & ERM_CORR_ERR_CNT1_COUNT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ERM_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group ERM_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_ERM_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FMC.h
new file mode 100644
index 0000000000..6b6c474648
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FMC.h
@@ -0,0 +1,264 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for FMC
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_FMC.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for FMC
+ *
+ * CMSIS Peripheral Access Layer for FMC
+ */
+
+#if !defined(PERI_FMC_H_)
+#define PERI_FMC_H_                              /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- FMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[32];
+  __IO uint32_t REMAP;                             /**< Data Remap, offset: 0x20 */
+       uint8_t RESERVED_1[988];
+  __IO uint32_t FCCR;                              /**< Flash Cache Control Register, offset: 0x400 */
+  __IO uint32_t FCAR;                              /**< Flash Cache Access Register, offset: 0x404 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t FCTG;                              /**< Flash Cache Tag, offset: 0x40C */
+       uint8_t RESERVED_3[16];
+  __IO uint32_t FCLN0;                             /**< Flash Cache Line Num0, offset: 0x420 */
+  __IO uint32_t FCLN1;                             /**< Flash Cache Line Num1, offset: 0x424 */
+  __IO uint32_t FCLN2;                             /**< Flash Cache Line Num2, offset: 0x428 */
+  __IO uint32_t FCLN3;                             /**< Flash Cache Line Num3, offset: 0x42C */
+} FMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/*! @name REMAP - Data Remap */
+/*! @{ */
+
+#define FMC_REMAP_REMAPLK_MASK                   (0x1U)
+#define FMC_REMAP_REMAPLK_SHIFT                  (0U)
+/*! REMAPLK - Remap Lock Enable
+ *  0b0..Lock disabled: can write to REMAP
+ *  0b1..Lock enabled: cannot write to REMAP
+ */
+#define FMC_REMAP_REMAPLK(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_REMAP_REMAPLK_SHIFT)) & FMC_REMAP_REMAPLK_MASK)
+
+#define FMC_REMAP_LIM_MASK                       (0x7F0000U)
+#define FMC_REMAP_LIM_SHIFT                      (16U)
+/*! LIM - LIM Remapping Address */
+#define FMC_REMAP_LIM(x)                         (((uint32_t)(((uint32_t)(x)) << FMC_REMAP_LIM_SHIFT)) & FMC_REMAP_LIM_MASK)
+
+#define FMC_REMAP_LIMDP_MASK                     (0x7F000000U)
+#define FMC_REMAP_LIMDP_SHIFT                    (24U)
+/*! LIMDP - LIMDP Remapping Address */
+#define FMC_REMAP_LIMDP(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_REMAP_LIMDP_SHIFT)) & FMC_REMAP_LIMDP_MASK)
+/*! @} */
+
+/*! @name FCCR - Flash Cache Control Register */
+/*! @{ */
+
+#define FMC_FCCR_WAY_LOCK_MASK                   (0xFU)
+#define FMC_FCCR_WAY_LOCK_SHIFT                  (0U)
+/*! WAY_LOCK - Cache Way Lock */
+#define FMC_FCCR_WAY_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_FCCR_WAY_LOCK_SHIFT)) & FMC_FCCR_WAY_LOCK_MASK)
+
+#define FMC_FCCR_LOCK_MASK                       (0x80000000U)
+#define FMC_FCCR_LOCK_SHIFT                      (31U)
+/*! LOCK - Lock Flash Cache Control
+ *  0b0..allows access and use of flash cache program model.
+ *  0b1..blocks all flash cache peripheral accesses and Lock program model till next reset - the flash cache will
+ *       continue to operate as configured before being locked, but no changes to the flash cache control are
+ *       possible until the next reset and all reads of flash cache program model registers return zeros. FCCR: Support
+ *       read, Write invalid. FCAR/FCTG/FCLN0/FCLN1/FCLN2/FCLN3: Read returns zeros, Write invalid.
+ */
+#define FMC_FCCR_LOCK(x)                         (((uint32_t)(((uint32_t)(x)) << FMC_FCCR_LOCK_SHIFT)) & FMC_FCCR_LOCK_MASK)
+/*! @} */
+
+/*! @name FCAR - Flash Cache Access Register */
+/*! @{ */
+
+#define FMC_FCAR_CACHES_WAY_NUM_MASK             (0x3U)
+#define FMC_FCAR_CACHES_WAY_NUM_SHIFT            (0U)
+/*! CACHES_WAY_NUM - Flash Cache Way Number */
+#define FMC_FCAR_CACHES_WAY_NUM(x)               (((uint32_t)(((uint32_t)(x)) << FMC_FCAR_CACHES_WAY_NUM_SHIFT)) & FMC_FCAR_CACHES_WAY_NUM_MASK)
+
+#define FMC_FCAR_CACHES_SET_NUM_MASK             (0x10U)
+#define FMC_FCAR_CACHES_SET_NUM_SHIFT            (4U)
+/*! CACHES_SET_NUM - Flash Cache Set Number */
+#define FMC_FCAR_CACHES_SET_NUM(x)               (((uint32_t)(((uint32_t)(x)) << FMC_FCAR_CACHES_SET_NUM_SHIFT)) & FMC_FCAR_CACHES_SET_NUM_MASK)
+
+#define FMC_FCAR_TYPE_MASK                       (0xC0000000U)
+#define FMC_FCAR_TYPE_SHIFT                      (30U)
+/*! TYPE - Operation of cache type */
+#define FMC_FCAR_TYPE(x)                         (((uint32_t)(((uint32_t)(x)) << FMC_FCAR_TYPE_SHIFT)) & FMC_FCAR_TYPE_MASK)
+/*! @} */
+
+/*! @name FCTG - Flash Cache Tag */
+/*! @{ */
+
+#define FMC_FCTG_VALID_MASK                      (0x1U)
+#define FMC_FCTG_VALID_SHIFT                     (0U)
+/*! VALID - Flash Cache Tag Valid Bit */
+#define FMC_FCTG_VALID(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_FCTG_VALID_SHIFT)) & FMC_FCTG_VALID_MASK)
+
+#define FMC_FCTG_ADDESS_MASK                     (0xFFFFC0U)
+#define FMC_FCTG_ADDESS_SHIFT                    (6U)
+/*! ADDESS - Flash Cache Tag Address Bit[23:6] */
+#define FMC_FCTG_ADDESS(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_FCTG_ADDESS_SHIFT)) & FMC_FCTG_ADDESS_MASK)
+/*! @} */
+
+/*! @name FCLN0 - Flash Cache Line Num0 */
+/*! @{ */
+
+#define FMC_FCLN0_DATAWxSyLM_MASK                (0xFFFFFFFFU)
+#define FMC_FCLN0_DATAWxSyLM_SHIFT               (0U)
+/*! DATAWxSyLM - The lowermost word (bits [31:0]) of Flash Cache Line Data */
+#define FMC_FCLN0_DATAWxSyLM(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_FCLN0_DATAWxSyLM_SHIFT)) & FMC_FCLN0_DATAWxSyLM_MASK)
+/*! @} */
+
+/*! @name FCLN1 - Flash Cache Line Num1 */
+/*! @{ */
+
+#define FMC_FCLN1_DATAWxSyML_MASK                (0xFFFFFFFFU)
+#define FMC_FCLN1_DATAWxSyML_SHIFT               (0U)
+/*! DATAWxSyML - The mid-lower word (bits [63:32]) of Flash Cache Line Data */
+#define FMC_FCLN1_DATAWxSyML(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_FCLN1_DATAWxSyML_SHIFT)) & FMC_FCLN1_DATAWxSyML_MASK)
+/*! @} */
+
+/*! @name FCLN2 - Flash Cache Line Num2 */
+/*! @{ */
+
+#define FMC_FCLN2_DATAWxSyMU_MASK                (0xFFFFFFFFU)
+#define FMC_FCLN2_DATAWxSyMU_SHIFT               (0U)
+/*! DATAWxSyMU - The mid-upper word (bits [95:64]) of Flash Cache Line Data */
+#define FMC_FCLN2_DATAWxSyMU(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_FCLN2_DATAWxSyMU_SHIFT)) & FMC_FCLN2_DATAWxSyMU_MASK)
+/*! @} */
+
+/*! @name FCLN3 - Flash Cache Line Num3 */
+/*! @{ */
+
+#define FMC_FCLN3_DATAWxSyUM_MASK                (0xFFFFFFFFU)
+#define FMC_FCLN3_DATAWxSyUM_SHIFT               (0U)
+/*! DATAWxSyUM - The uppermost word (bits [127:96]) of Flash Cache Line Data */
+#define FMC_FCLN3_DATAWxSyUM(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_FCLN3_DATAWxSyUM_SHIFT)) & FMC_FCLN3_DATAWxSyUM_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_FMC_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FMU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FMU.h
new file mode 100644
index 0000000000..a6e51be6ad
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FMU.h
@@ -0,0 +1,345 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for FMU
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_FMU.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for FMU
+ *
+ * CMSIS Peripheral Access Layer for FMU
+ */
+
+#if !defined(PERI_FMU_H_)
+#define PERI_FMU_H_                              /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- FMU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMU_Peripheral_Access_Layer FMU Peripheral Access Layer
+ * @{
+ */
+
+/** FMU - Size of Registers Arrays */
+#define FMU_FCCOB_COUNT                           8u
+
+/** FMU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t FSTAT;                             /**< Flash Status Register, offset: 0x0 */
+  __IO uint32_t FCNFG;                             /**< Flash Configuration Register, offset: 0x4 */
+  __IO uint32_t FCTRL;                             /**< Flash Control Register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t FCCOB[FMU_FCCOB_COUNT];            /**< Flash Common Command Object Registers, array offset: 0x10, array step: 0x4 */
+} FMU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FMU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMU_Register_Masks FMU Register Masks
+ * @{
+ */
+
+/*! @name FSTAT - Flash Status Register */
+/*! @{ */
+
+#define FMU_FSTAT_FAIL_MASK                      (0x1U)
+#define FMU_FSTAT_FAIL_SHIFT                     (0U)
+/*! FAIL - Command Fail Flag
+ *  0b0..Error not detected
+ *  0b1..Error detected
+ */
+#define FMU_FSTAT_FAIL(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_FAIL_SHIFT)) & FMU_FSTAT_FAIL_MASK)
+
+#define FMU_FSTAT_CMDABT_MASK                    (0x4U)
+#define FMU_FSTAT_CMDABT_SHIFT                   (2U)
+/*! CMDABT - Command Abort Flag
+ *  0b0..No command abort detected
+ *  0b1..Command abort detected
+ */
+#define FMU_FSTAT_CMDABT(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDABT_SHIFT)) & FMU_FSTAT_CMDABT_MASK)
+
+#define FMU_FSTAT_PVIOL_MASK                     (0x10U)
+#define FMU_FSTAT_PVIOL_SHIFT                    (4U)
+/*! PVIOL - Command Protection Violation Flag
+ *  0b0..No protection violation detected
+ *  0b1..Protection violation detected
+ */
+#define FMU_FSTAT_PVIOL(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PVIOL_SHIFT)) & FMU_FSTAT_PVIOL_MASK)
+
+#define FMU_FSTAT_ACCERR_MASK                    (0x20U)
+#define FMU_FSTAT_ACCERR_SHIFT                   (5U)
+/*! ACCERR - Command Access Error Flag
+ *  0b0..No access error detected
+ *  0b1..Access error detected
+ */
+#define FMU_FSTAT_ACCERR(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_ACCERR_SHIFT)) & FMU_FSTAT_ACCERR_MASK)
+
+#define FMU_FSTAT_CWSABT_MASK                    (0x40U)
+#define FMU_FSTAT_CWSABT_SHIFT                   (6U)
+/*! CWSABT - Command Write Sequence Abort Flag
+ *  0b0..Command write sequence not aborted
+ *  0b1..Command write sequence aborted
+ */
+#define FMU_FSTAT_CWSABT(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CWSABT_SHIFT)) & FMU_FSTAT_CWSABT_MASK)
+
+#define FMU_FSTAT_CCIF_MASK                      (0x80U)
+#define FMU_FSTAT_CCIF_SHIFT                     (7U)
+/*! CCIF - Command Complete Interrupt Flag
+ *  0b0..Flash command, initialization, or power mode recovery in progress
+ *  0b1..Flash command, initialization, or power mode recovery has completed
+ */
+#define FMU_FSTAT_CCIF(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CCIF_SHIFT)) & FMU_FSTAT_CCIF_MASK)
+
+#define FMU_FSTAT_CMDPRT_MASK                    (0x300U)
+#define FMU_FSTAT_CMDPRT_SHIFT                   (8U)
+/*! CMDPRT - Command protection level
+ *  0b00..Secure, normal access
+ *  0b01..Secure, privileged access
+ *  0b10..Nonsecure, normal access
+ *  0b11..Nonsecure, privileged access
+ */
+#define FMU_FSTAT_CMDPRT(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDPRT_SHIFT)) & FMU_FSTAT_CMDPRT_MASK)
+
+#define FMU_FSTAT_CMDP_MASK                      (0x800U)
+#define FMU_FSTAT_CMDP_SHIFT                     (11U)
+/*! CMDP - Command protection status flag
+ *  0b0..Command protection level and domain ID are stale
+ *  0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set
+ */
+#define FMU_FSTAT_CMDP(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDP_SHIFT)) & FMU_FSTAT_CMDP_MASK)
+
+#define FMU_FSTAT_CMDDID_MASK                    (0xF000U)
+#define FMU_FSTAT_CMDDID_SHIFT                   (12U)
+/*! CMDDID - Command domain ID */
+#define FMU_FSTAT_CMDDID(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDDID_SHIFT)) & FMU_FSTAT_CMDDID_MASK)
+
+#define FMU_FSTAT_DFDIF_MASK                     (0x10000U)
+#define FMU_FSTAT_DFDIF_SHIFT                    (16U)
+/*! DFDIF - Double Bit Fault Detect Interrupt Flag
+ *  0b0..Double bit fault not detected during a valid flash read access
+ *  0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access
+ */
+#define FMU_FSTAT_DFDIF(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_DFDIF_SHIFT)) & FMU_FSTAT_DFDIF_MASK)
+
+#define FMU_FSTAT_SALV_USED_MASK                 (0x20000U)
+#define FMU_FSTAT_SALV_USED_SHIFT                (17U)
+/*! SALV_USED - Salvage Used for Erase operation
+ *  0b0..Salvage not used during last operation
+ *  0b1..Salvage used during the last erase operation
+ */
+#define FMU_FSTAT_SALV_USED(x)                   (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_SALV_USED_SHIFT)) & FMU_FSTAT_SALV_USED_MASK)
+
+#define FMU_FSTAT_PEWEN_MASK                     (0x3000000U)
+#define FMU_FSTAT_PEWEN_SHIFT                    (24U)
+/*! PEWEN - Program-Erase Write Enable Control
+ *  0b00..Writes are not enabled
+ *  0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase)
+ *  0b10..Writes are enabled for one flash or IFR page (page programming)
+ *  0b11..Reserved
+ */
+#define FMU_FSTAT_PEWEN(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PEWEN_SHIFT)) & FMU_FSTAT_PEWEN_MASK)
+
+#define FMU_FSTAT_PERDY_MASK                     (0x80000000U)
+#define FMU_FSTAT_PERDY_SHIFT                    (31U)
+/*! PERDY - Program-Erase Ready Control/Status Flag
+ *  0b0..Program or sector erase command operation not stalled
+ *  0b1..Program or sector erase command operation ready to execute
+ */
+#define FMU_FSTAT_PERDY(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PERDY_SHIFT)) & FMU_FSTAT_PERDY_MASK)
+/*! @} */
+
+/*! @name FCNFG - Flash Configuration Register */
+/*! @{ */
+
+#define FMU_FCNFG_CCIE_MASK                      (0x80U)
+#define FMU_FCNFG_CCIE_SHIFT                     (7U)
+/*! CCIE - Command Complete Interrupt Enable
+ *  0b0..Command complete interrupt disabled
+ *  0b1..Command complete interrupt enabled
+ */
+#define FMU_FCNFG_CCIE(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_CCIE_SHIFT)) & FMU_FCNFG_CCIE_MASK)
+
+#define FMU_FCNFG_ERSREQ_MASK                    (0x100U)
+#define FMU_FCNFG_ERSREQ_SHIFT                   (8U)
+/*! ERSREQ - Mass Erase Request
+ *  0b0..No request or request complete
+ *  0b1..Request to run the Mass Erase operation
+ */
+#define FMU_FCNFG_ERSREQ(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSREQ_SHIFT)) & FMU_FCNFG_ERSREQ_MASK)
+
+#define FMU_FCNFG_DFDIE_MASK                     (0x10000U)
+#define FMU_FCNFG_DFDIE_SHIFT                    (16U)
+/*! DFDIE - Double Bit Fault Detect Interrupt Enable
+ *  0b0..Double bit fault detect interrupt disabled
+ *  0b1..Double bit fault detect interrupt enabled
+ */
+#define FMU_FCNFG_DFDIE(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_DFDIE_SHIFT)) & FMU_FCNFG_DFDIE_MASK)
+
+#define FMU_FCNFG_ERSIEN0_MASK                   (0xF000000U)
+#define FMU_FCNFG_ERSIEN0_SHIFT                  (24U)
+/*! ERSIEN0 - Erase IFR Sector Enable - Block 0
+ *  0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command
+ *  0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command
+ */
+#define FMU_FCNFG_ERSIEN0(x)                     (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN0_SHIFT)) & FMU_FCNFG_ERSIEN0_MASK)
+
+#define FMU_FCNFG_ERSIEN1_MASK                   (0xF0000000U)
+#define FMU_FCNFG_ERSIEN1_SHIFT                  (28U)
+/*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs)
+ *  0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command
+ *  0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command
+ */
+#define FMU_FCNFG_ERSIEN1(x)                     (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
+/*! @} */
+
+/*! @name FCTRL - Flash Control Register */
+/*! @{ */
+
+#define FMU_FCTRL_RWSC_MASK                      (0xFU)
+#define FMU_FCTRL_RWSC_SHIFT                     (0U)
+/*! RWSC - Read Wait-State Control */
+#define FMU_FCTRL_RWSC(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_RWSC_SHIFT)) & FMU_FCTRL_RWSC_MASK)
+
+#define FMU_FCTRL_LSACTIVE_MASK                  (0x100U)
+#define FMU_FCTRL_LSACTIVE_SHIFT                 (8U)
+/*! LSACTIVE - Low speed active mode
+ *  0b0..Full speed active mode requested
+ *  0b1..Low speed active mode requested
+ */
+#define FMU_FCTRL_LSACTIVE(x)                    (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_LSACTIVE_SHIFT)) & FMU_FCTRL_LSACTIVE_MASK)
+
+#define FMU_FCTRL_FDFD_MASK                      (0x10000U)
+#define FMU_FCTRL_FDFD_SHIFT                     (16U)
+/*! FDFD - Force Double Bit Fault Detect
+ *  0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller
+ *  0b1..FSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt
+ *       request is generated if the DFDIE bit is set.
+ */
+#define FMU_FCTRL_FDFD(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_FDFD_SHIFT)) & FMU_FCTRL_FDFD_MASK)
+
+#define FMU_FCTRL_ABTREQ_MASK                    (0x1000000U)
+#define FMU_FCTRL_ABTREQ_SHIFT                   (24U)
+/*! ABTREQ - Abort Request
+ *  0b0..No request to abort a command write sequence
+ *  0b1..Request to abort a command write sequence
+ */
+#define FMU_FCTRL_ABTREQ(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_ABTREQ_SHIFT)) & FMU_FCTRL_ABTREQ_MASK)
+/*! @} */
+
+/*! @name FCCOB - Flash Common Command Object Registers */
+/*! @{ */
+
+#define FMU_FCCOB_CCOBn_MASK                     (0xFFFFFFFFU)
+#define FMU_FCCOB_CCOBn_SHIFT                    (0U)
+/*! CCOBn - CCOBn */
+#define FMU_FCCOB_CCOBn(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FCCOB_CCOBn_SHIFT)) & FMU_FCCOB_CCOBn_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FMU_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group FMU_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_FMU_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FREQME.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FREQME.h
new file mode 100644
index 0000000000..84fb636dbf
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FREQME.h
@@ -0,0 +1,336 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for FREQME
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_FREQME.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for FREQME
+ *
+ * CMSIS Peripheral Access Layer for FREQME
+ */
+
+#if !defined(PERI_FREQME_H_)
+#define PERI_FREQME_H_                           /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- FREQME Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer
+ * @{
+ */
+
+/** FREQME - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    __I  uint32_t CTRL_R;                            /**< Control (in Read mode), offset: 0x0 */
+    __O  uint32_t CTRL_W;                            /**< Control (in Write mode), offset: 0x0 */
+  };
+  __IO uint32_t CTRLSTAT;                          /**< Control Status, offset: 0x4 */
+  __IO uint32_t MIN;                               /**< Minimum, offset: 0x8 */
+  __IO uint32_t MAX;                               /**< Maximum, offset: 0xC */
+} FREQME_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FREQME Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FREQME_Register_Masks FREQME Register Masks
+ * @{
+ */
+
+/*! @name CTRL_R - Control (in Read mode) */
+/*! @{ */
+
+#define FREQME_CTRL_R_RESULT_MASK                (0x7FFFFFFFU)
+#define FREQME_CTRL_R_RESULT_SHIFT               (0U)
+#define FREQME_CTRL_R_RESULT(x)                  (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_RESULT_SHIFT)) & FREQME_CTRL_R_RESULT_MASK)
+
+#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK   (0x80000000U)
+#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT  (31U)
+/*! MEASURE_IN_PROGRESS - Measurement In Progress
+ *  0b0..Complete
+ *  0b1..In progress
+ */
+#define FREQME_CTRL_R_MEASURE_IN_PROGRESS(x)     (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK)
+/*! @} */
+
+/*! @name CTRL_W - Control (in Write mode) */
+/*! @{ */
+
+#define FREQME_CTRL_W_REF_SCALE_MASK             (0x1FU)
+#define FREQME_CTRL_W_REF_SCALE_SHIFT            (0U)
+/*! REF_SCALE - Reference Clock Scaling Factor */
+#define FREQME_CTRL_W_REF_SCALE(x)               (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_REF_SCALE_SHIFT)) & FREQME_CTRL_W_REF_SCALE_MASK)
+
+#define FREQME_CTRL_W_PULSE_MODE_MASK            (0x100U)
+#define FREQME_CTRL_W_PULSE_MODE_SHIFT           (8U)
+/*! PULSE_MODE - Pulse Width Measurement Mode Select
+ *  0b0..Frequency Measurement mode
+ *  0b1..Pulse Width Measurement mode
+ */
+#define FREQME_CTRL_W_PULSE_MODE(x)              (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_MODE_SHIFT)) & FREQME_CTRL_W_PULSE_MODE_MASK)
+
+#define FREQME_CTRL_W_PULSE_POL_MASK             (0x200U)
+#define FREQME_CTRL_W_PULSE_POL_SHIFT            (9U)
+/*! PULSE_POL - Pulse Polarity
+ *  0b0..High period
+ *  0b1..Low period
+ */
+#define FREQME_CTRL_W_PULSE_POL(x)               (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_POL_SHIFT)) & FREQME_CTRL_W_PULSE_POL_MASK)
+
+#define FREQME_CTRL_W_LT_MIN_INT_EN_MASK         (0x1000U)
+#define FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT        (12U)
+/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define FREQME_CTRL_W_LT_MIN_INT_EN(x)           (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRL_W_LT_MIN_INT_EN_MASK)
+
+#define FREQME_CTRL_W_GT_MAX_INT_EN_MASK         (0x2000U)
+#define FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT        (13U)
+/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define FREQME_CTRL_W_GT_MAX_INT_EN(x)           (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRL_W_GT_MAX_INT_EN_MASK)
+
+#define FREQME_CTRL_W_RESULT_READY_INT_EN_MASK   (0x4000U)
+#define FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT  (14U)
+/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define FREQME_CTRL_W_RESULT_READY_INT_EN(x)     (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRL_W_RESULT_READY_INT_EN_MASK)
+
+#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK    (0x40000000U)
+#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT   (30U)
+/*! CONTINUOUS_MODE_EN - Continuous Mode Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define FREQME_CTRL_W_CONTINUOUS_MODE_EN(x)      (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK)
+
+#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK   (0x80000000U)
+#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT  (31U)
+/*! MEASURE_IN_PROGRESS - Measurement In Progress
+ *  0b0..Terminates measurement
+ *  0b1..Initiates measurement
+ */
+#define FREQME_CTRL_W_MEASURE_IN_PROGRESS(x)     (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK)
+/*! @} */
+
+/*! @name CTRLSTAT - Control Status */
+/*! @{ */
+
+#define FREQME_CTRLSTAT_REF_SCALE_MASK           (0x1FU)
+#define FREQME_CTRLSTAT_REF_SCALE_SHIFT          (0U)
+/*! REF_SCALE - Reference Scale */
+#define FREQME_CTRLSTAT_REF_SCALE(x)             (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_REF_SCALE_SHIFT)) & FREQME_CTRLSTAT_REF_SCALE_MASK)
+
+#define FREQME_CTRLSTAT_PULSE_MODE_MASK          (0x100U)
+#define FREQME_CTRLSTAT_PULSE_MODE_SHIFT         (8U)
+/*! PULSE_MODE - Pulse Mode
+ *  0b0..Frequency Measurement mode
+ *  0b1..Pulse Width Measurement mode
+ */
+#define FREQME_CTRLSTAT_PULSE_MODE(x)            (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_MODE_SHIFT)) & FREQME_CTRLSTAT_PULSE_MODE_MASK)
+
+#define FREQME_CTRLSTAT_PULSE_POL_MASK           (0x200U)
+#define FREQME_CTRLSTAT_PULSE_POL_SHIFT          (9U)
+/*! PULSE_POL - Pulse Polarity
+ *  0b0..High period
+ *  0b1..Low period
+ */
+#define FREQME_CTRLSTAT_PULSE_POL(x)             (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_POL_SHIFT)) & FREQME_CTRLSTAT_PULSE_POL_MASK)
+
+#define FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK       (0x1000U)
+#define FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT      (12U)
+/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define FREQME_CTRLSTAT_LT_MIN_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK)
+
+#define FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK       (0x2000U)
+#define FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT      (13U)
+/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define FREQME_CTRLSTAT_GT_MAX_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK)
+
+#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK (0x4000U)
+#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT (14U)
+/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define FREQME_CTRLSTAT_RESULT_READY_INT_EN(x)   (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK)
+
+#define FREQME_CTRLSTAT_LT_MIN_STAT_MASK         (0x1000000U)
+#define FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT        (24U)
+/*! LT_MIN_STAT - Less Than Minimum Results Status
+ *  0b0..Greater than MIN[MIN_VALUE]
+ *  0b1..Less than MIN[MIN_VALUE]
+ */
+#define FREQME_CTRLSTAT_LT_MIN_STAT(x)           (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_STAT_MASK)
+
+#define FREQME_CTRLSTAT_GT_MAX_STAT_MASK         (0x2000000U)
+#define FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT        (25U)
+/*! GT_MAX_STAT - Greater Than Maximum Result Status
+ *  0b0..Less than MAX[MAX_VALUE]
+ *  0b1..Greater than MAX[MAX_VALUE]
+ */
+#define FREQME_CTRLSTAT_GT_MAX_STAT(x)           (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_STAT_MASK)
+
+#define FREQME_CTRLSTAT_RESULT_READY_STAT_MASK   (0x4000000U)
+#define FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT  (26U)
+/*! RESULT_READY_STAT - Result Ready Status
+ *  0b0..Not complete
+ *  0b1..Complete
+ */
+#define FREQME_CTRLSTAT_RESULT_READY_STAT(x)     (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_STAT_MASK)
+
+#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK  (0x40000000U)
+#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT (30U)
+/*! CONTINUOUS_MODE_EN - Continuous Mode Enable Status
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN(x)    (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK)
+
+#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK (0x80000000U)
+#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT (31U)
+/*! MEASURE_IN_PROGRESS - Measurement in Progress Status
+ *  0b0..Not in progress
+ *  0b1..In progress
+ */
+#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS(x)   (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK)
+/*! @} */
+
+/*! @name MIN - Minimum */
+/*! @{ */
+
+#define FREQME_MIN_MIN_VALUE_MASK                (0x7FFFFFFFU)
+#define FREQME_MIN_MIN_VALUE_SHIFT               (0U)
+/*! MIN_VALUE - Minimum Value */
+#define FREQME_MIN_MIN_VALUE(x)                  (((uint32_t)(((uint32_t)(x)) << FREQME_MIN_MIN_VALUE_SHIFT)) & FREQME_MIN_MIN_VALUE_MASK)
+/*! @} */
+
+/*! @name MAX - Maximum */
+/*! @{ */
+
+#define FREQME_MAX_MAX_VALUE_MASK                (0x7FFFFFFFU)
+#define FREQME_MAX_MAX_VALUE_SHIFT               (0U)
+/*! MAX_VALUE - Maximum Value */
+#define FREQME_MAX_MAX_VALUE(x)                  (((uint32_t)(((uint32_t)(x)) << FREQME_MAX_MAX_VALUE_SHIFT)) & FREQME_MAX_MAX_VALUE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FREQME_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group FREQME_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_FREQME_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_GLIKEY.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_GLIKEY.h
new file mode 100644
index 0000000000..cc7da88d3e
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_GLIKEY.h
@@ -0,0 +1,322 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for GLIKEY
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_GLIKEY.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for GLIKEY
+ *
+ * CMSIS Peripheral Access Layer for GLIKEY
+ */
+
+#if !defined(PERI_GLIKEY_H_)
+#define PERI_GLIKEY_H_                           /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- GLIKEY Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GLIKEY_Peripheral_Access_Layer GLIKEY Peripheral Access Layer
+ * @{
+ */
+
+/** GLIKEY - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL_0;                            /**< Control Register 0 SFR, offset: 0x0 */
+  __IO uint32_t CTRL_1;                            /**< Control Register 1 SFR, offset: 0x4 */
+  __IO uint32_t INTR_CTRL;                         /**< Interrupt Control, offset: 0x8 */
+  __I  uint32_t STATUS;                            /**< Status, offset: 0xC */
+       uint8_t RESERVED_0[236];
+  __I  uint32_t VERSION;                           /**< IP Version, offset: 0xFC */
+} GLIKEY_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GLIKEY Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GLIKEY_Register_Masks GLIKEY Register Masks
+ * @{
+ */
+
+/*! @name CTRL_0 - Control Register 0 SFR */
+/*! @{ */
+
+#define GLIKEY_CTRL_0_WRITE_INDEX_MASK           (0xFFU)
+#define GLIKEY_CTRL_0_WRITE_INDEX_SHIFT          (0U)
+/*! WRITE_INDEX - Write Index */
+#define GLIKEY_CTRL_0_WRITE_INDEX(x)             (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_WRITE_INDEX_SHIFT)) & GLIKEY_CTRL_0_WRITE_INDEX_MASK)
+
+#define GLIKEY_CTRL_0_RESERVED15_MASK            (0xFF00U)
+#define GLIKEY_CTRL_0_RESERVED15_SHIFT           (8U)
+/*! RESERVED15 - Reserved for Future Use */
+#define GLIKEY_CTRL_0_RESERVED15(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_RESERVED15_SHIFT)) & GLIKEY_CTRL_0_RESERVED15_MASK)
+
+#define GLIKEY_CTRL_0_WR_EN_0_MASK               (0x30000U)
+#define GLIKEY_CTRL_0_WR_EN_0_SHIFT              (16U)
+/*! WR_EN_0 - Write Enable 0 */
+#define GLIKEY_CTRL_0_WR_EN_0(x)                 (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_WR_EN_0_SHIFT)) & GLIKEY_CTRL_0_WR_EN_0_MASK)
+
+#define GLIKEY_CTRL_0_SFT_RST_MASK               (0x40000U)
+#define GLIKEY_CTRL_0_SFT_RST_SHIFT              (18U)
+/*! SFT_RST - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0
+ *  0b0..No effect
+ *  0b1..Triggers the soft reset
+ */
+#define GLIKEY_CTRL_0_SFT_RST(x)                 (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_SFT_RST_SHIFT)) & GLIKEY_CTRL_0_SFT_RST_MASK)
+
+#define GLIKEY_CTRL_0_RESERVED31_MASK            (0xFFF80000U)
+#define GLIKEY_CTRL_0_RESERVED31_SHIFT           (19U)
+/*! RESERVED31 - Reserved for Future Use */
+#define GLIKEY_CTRL_0_RESERVED31(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_RESERVED31_SHIFT)) & GLIKEY_CTRL_0_RESERVED31_MASK)
+/*! @} */
+
+/*! @name CTRL_1 - Control Register 1 SFR */
+/*! @{ */
+
+#define GLIKEY_CTRL_1_READ_INDEX_MASK            (0xFFU)
+#define GLIKEY_CTRL_1_READ_INDEX_SHIFT           (0U)
+/*! READ_INDEX - Index status, Writing an index value to this register will request the block to return the lock status of this index. */
+#define GLIKEY_CTRL_1_READ_INDEX(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_READ_INDEX_SHIFT)) & GLIKEY_CTRL_1_READ_INDEX_MASK)
+
+#define GLIKEY_CTRL_1_RESERVED15_MASK            (0xFF00U)
+#define GLIKEY_CTRL_1_RESERVED15_SHIFT           (8U)
+/*! RESERVED15 - Reserved for Future Use */
+#define GLIKEY_CTRL_1_RESERVED15(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_RESERVED15_SHIFT)) & GLIKEY_CTRL_1_RESERVED15_MASK)
+
+#define GLIKEY_CTRL_1_WR_EN_1_MASK               (0x30000U)
+#define GLIKEY_CTRL_1_WR_EN_1_SHIFT              (16U)
+/*! WR_EN_1 - Write Enable One */
+#define GLIKEY_CTRL_1_WR_EN_1(x)                 (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_WR_EN_1_SHIFT)) & GLIKEY_CTRL_1_WR_EN_1_MASK)
+
+#define GLIKEY_CTRL_1_SFR_LOCK_MASK              (0x3C0000U)
+#define GLIKEY_CTRL_1_SFR_LOCK_SHIFT             (18U)
+/*! SFR_LOCK - LOCK register for GLIKEY */
+#define GLIKEY_CTRL_1_SFR_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_SFR_LOCK_SHIFT)) & GLIKEY_CTRL_1_SFR_LOCK_MASK)
+
+#define GLIKEY_CTRL_1_RESERVED31_MASK            (0xFFC00000U)
+#define GLIKEY_CTRL_1_RESERVED31_SHIFT           (22U)
+/*! RESERVED31 - Reserved for Future Use */
+#define GLIKEY_CTRL_1_RESERVED31(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_RESERVED31_SHIFT)) & GLIKEY_CTRL_1_RESERVED31_MASK)
+/*! @} */
+
+/*! @name INTR_CTRL - Interrupt Control */
+/*! @{ */
+
+#define GLIKEY_INTR_CTRL_INT_EN_MASK             (0x1U)
+#define GLIKEY_INTR_CTRL_INT_EN_SHIFT            (0U)
+/*! INT_EN - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port */
+#define GLIKEY_INTR_CTRL_INT_EN(x)               (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_EN_SHIFT)) & GLIKEY_INTR_CTRL_INT_EN_MASK)
+
+#define GLIKEY_INTR_CTRL_INT_CLR_MASK            (0x2U)
+#define GLIKEY_INTR_CTRL_INT_CLR_SHIFT           (1U)
+/*! INT_CLR - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0 */
+#define GLIKEY_INTR_CTRL_INT_CLR(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_CLR_SHIFT)) & GLIKEY_INTR_CTRL_INT_CLR_MASK)
+
+#define GLIKEY_INTR_CTRL_INT_SET_MASK            (0x4U)
+#define GLIKEY_INTR_CTRL_INT_SET_SHIFT           (2U)
+/*! INT_SET - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0
+ *  0b0..No effect
+ *  0b1..Triggers interrupt
+ */
+#define GLIKEY_INTR_CTRL_INT_SET(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_SET_SHIFT)) & GLIKEY_INTR_CTRL_INT_SET_MASK)
+
+#define GLIKEY_INTR_CTRL_RESERVED31_MASK         (0xFFFFFFF8U)
+#define GLIKEY_INTR_CTRL_RESERVED31_SHIFT        (3U)
+/*! RESERVED31 - Reserved for Future Use */
+#define GLIKEY_INTR_CTRL_RESERVED31(x)           (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_RESERVED31_SHIFT)) & GLIKEY_INTR_CTRL_RESERVED31_MASK)
+/*! @} */
+
+/*! @name STATUS - Status */
+/*! @{ */
+
+#define GLIKEY_STATUS_INT_STATUS_MASK            (0x1U)
+#define GLIKEY_STATUS_INT_STATUS_SHIFT           (0U)
+/*! INT_STATUS - Interrupt Status.
+ *  0b0..No effect
+ *  0b1..Triggers interrupt
+ */
+#define GLIKEY_STATUS_INT_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_INT_STATUS_SHIFT)) & GLIKEY_STATUS_INT_STATUS_MASK)
+
+#define GLIKEY_STATUS_LOCK_STATUS_MASK           (0x2U)
+#define GLIKEY_STATUS_LOCK_STATUS_SHIFT          (1U)
+/*! LOCK_STATUS - Provides the current lock status of indexes.
+ *  0b0..Current read index is not locked
+ *  0b1..Current read index is locked
+ */
+#define GLIKEY_STATUS_LOCK_STATUS(x)             (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_LOCK_STATUS_SHIFT)) & GLIKEY_STATUS_LOCK_STATUS_MASK)
+
+#define GLIKEY_STATUS_ERROR_STATUS_MASK          (0x1CU)
+#define GLIKEY_STATUS_ERROR_STATUS_SHIFT         (2U)
+/*! ERROR_STATUS - Status of the Error
+ *  0b000..No error
+ *  0b001..FSM error has occurred
+ *  0b010..Write index out of the bound (OOB) error
+ *  0b011..Write index OOB and FSM error
+ *  0b100..Read index OOB error
+ *  0b110..Write index and read index OOB error
+ *  0b111..Read index OOB, write index OOB, and FSM error
+ */
+#define GLIKEY_STATUS_ERROR_STATUS(x)            (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_ERROR_STATUS_SHIFT)) & GLIKEY_STATUS_ERROR_STATUS_MASK)
+
+#define GLIKEY_STATUS_RESERVED18_MASK            (0x7FFE0U)
+#define GLIKEY_STATUS_RESERVED18_SHIFT           (5U)
+/*! RESERVED18 - Reserved for Future Use */
+#define GLIKEY_STATUS_RESERVED18(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_RESERVED18_SHIFT)) & GLIKEY_STATUS_RESERVED18_MASK)
+
+#define GLIKEY_STATUS_FSM_STATE_MASK             (0xFFF80000U)
+#define GLIKEY_STATUS_FSM_STATE_SHIFT            (19U)
+/*! FSM_STATE - Status of FSM */
+#define GLIKEY_STATUS_FSM_STATE(x)               (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_FSM_STATE_SHIFT)) & GLIKEY_STATUS_FSM_STATE_MASK)
+/*! @} */
+
+/*! @name VERSION - IP Version */
+/*! @{ */
+
+#define GLIKEY_VERSION_RESERVED3_MASK            (0xFU)
+#define GLIKEY_VERSION_RESERVED3_SHIFT           (0U)
+/*! Reserved3 - Reserved */
+#define GLIKEY_VERSION_RESERVED3(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED3_SHIFT)) & GLIKEY_VERSION_RESERVED3_MASK)
+
+#define GLIKEY_VERSION_RESERVED7_MASK            (0xF0U)
+#define GLIKEY_VERSION_RESERVED7_SHIFT           (4U)
+/*! Reserved7 - Reserved */
+#define GLIKEY_VERSION_RESERVED7(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED7_SHIFT)) & GLIKEY_VERSION_RESERVED7_MASK)
+
+#define GLIKEY_VERSION_RESERVED11_MASK           (0xF00U)
+#define GLIKEY_VERSION_RESERVED11_SHIFT          (8U)
+/*! Reserved11 - Reserved */
+#define GLIKEY_VERSION_RESERVED11(x)             (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED11_SHIFT)) & GLIKEY_VERSION_RESERVED11_MASK)
+
+#define GLIKEY_VERSION_RESERVED15_MASK           (0xF000U)
+#define GLIKEY_VERSION_RESERVED15_SHIFT          (12U)
+/*! Reserved15 - Reserved */
+#define GLIKEY_VERSION_RESERVED15(x)             (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED15_SHIFT)) & GLIKEY_VERSION_RESERVED15_MASK)
+
+#define GLIKEY_VERSION_MILESTONE_MASK            (0x30000U)
+#define GLIKEY_VERSION_MILESTONE_SHIFT           (16U)
+/*! MILESTONE - Release milestone. 00-PREL, 01-BR, 10-SI, 11-GO. */
+#define GLIKEY_VERSION_MILESTONE(x)              (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_MILESTONE_SHIFT)) & GLIKEY_VERSION_MILESTONE_MASK)
+
+#define GLIKEY_VERSION_FSM_CONFIG_MASK           (0x40000U)
+#define GLIKEY_VERSION_FSM_CONFIG_SHIFT          (18U)
+/*! FSM_CONFIG - 0:4 step, 1:8 step */
+#define GLIKEY_VERSION_FSM_CONFIG(x)             (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_FSM_CONFIG_SHIFT)) & GLIKEY_VERSION_FSM_CONFIG_MASK)
+
+#define GLIKEY_VERSION_INDEX_CONFIG_MASK         (0x7F80000U)
+#define GLIKEY_VERSION_INDEX_CONFIG_SHIFT        (19U)
+/*! INDEX_CONFIG - Configured number of addressable indexes */
+#define GLIKEY_VERSION_INDEX_CONFIG(x)           (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_INDEX_CONFIG_SHIFT)) & GLIKEY_VERSION_INDEX_CONFIG_MASK)
+
+#define GLIKEY_VERSION_RESERVED31_MASK           (0xF8000000U)
+#define GLIKEY_VERSION_RESERVED31_SHIFT          (27U)
+/*! Reserved31 - Reserved for Future Use */
+#define GLIKEY_VERSION_RESERVED31(x)             (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED31_SHIFT)) & GLIKEY_VERSION_RESERVED31_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group GLIKEY_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group GLIKEY_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_GLIKEY_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_GPIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_GPIO.h
new file mode 100644
index 0000000000..2cdbc39818
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_GPIO.h
@@ -0,0 +1,2662 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for GPIO
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_GPIO.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for GPIO
+ *
+ * CMSIS Peripheral Access Layer for GPIO
+ */
+
+#if !defined(PERI_GPIO_H_)
+#define PERI_GPIO_H_                             /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Size of Registers Arrays */
+#define GPIO_PDR_COUNT                            32u
+#define GPIO_ICR_COUNT                            32u
+#define GPIO_ISFR_COUNT                           1u
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
+       uint8_t RESERVED_0[56];
+  __IO uint32_t PDOR;                              /**< Port Data Output, offset: 0x40 */
+  __IO uint32_t PSOR;                              /**< Port Set Output, offset: 0x44 */
+  __IO uint32_t PCOR;                              /**< Port Clear Output, offset: 0x48 */
+  __IO uint32_t PTOR;                              /**< Port Toggle Output, offset: 0x4C */
+  __I  uint32_t PDIR;                              /**< Port Data Input, offset: 0x50 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction, offset: 0x54 */
+  __IO uint32_t PIDR;                              /**< Port Input Disable, offset: 0x58 */
+       uint8_t RESERVED_1[4];
+  __IO uint8_t PDR[GPIO_PDR_COUNT];                /**< Pin Data, array offset: 0x60, array step: 0x1 */
+  __IO uint32_t ICR[GPIO_ICR_COUNT];               /**< Interrupt Control 0..Interrupt Control 31, array offset: 0x80, array step: 0x4 */
+  __IO uint32_t GICLR;                             /**< Global Interrupt Control Low, offset: 0x100 */
+  __IO uint32_t GICHR;                             /**< Global Interrupt Control High, offset: 0x104 */
+       uint8_t RESERVED_2[24];
+  __IO uint32_t ISFR[GPIO_ISFR_COUNT];             /**< Interrupt Status Flag, array offset: 0x120, array step: 0x4 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID */
+/*! @{ */
+
+#define GPIO_VERID_FEATURE_MASK                  (0xFFFFU)
+#define GPIO_VERID_FEATURE_SHIFT                 (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000000..Basic implementation
+ *  0b0000000000000001..Protection registers implemented
+ */
+#define GPIO_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_FEATURE_SHIFT)) & GPIO_VERID_FEATURE_MASK)
+
+#define GPIO_VERID_MINOR_MASK                    (0xFF0000U)
+#define GPIO_VERID_MINOR_SHIFT                   (16U)
+/*! MINOR - Minor Version Number */
+#define GPIO_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MINOR_SHIFT)) & GPIO_VERID_MINOR_MASK)
+
+#define GPIO_VERID_MAJOR_MASK                    (0xFF000000U)
+#define GPIO_VERID_MAJOR_SHIFT                   (24U)
+/*! MAJOR - Major Version Number */
+#define GPIO_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MAJOR_SHIFT)) & GPIO_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter */
+/*! @{ */
+
+#define GPIO_PARAM_IRQNUM_MASK                   (0xFU)
+#define GPIO_PARAM_IRQNUM_SHIFT                  (0U)
+/*! IRQNUM - Interrupt Number */
+#define GPIO_PARAM_IRQNUM(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_PARAM_IRQNUM_SHIFT)) & GPIO_PARAM_IRQNUM_MASK)
+/*! @} */
+
+/*! @name PDOR - Port Data Output */
+/*! @{ */
+
+#define GPIO_PDOR_PDO0_MASK                      (0x1U)
+#define GPIO_PDOR_PDO0_SHIFT                     (0U)
+/*! PDO0 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO0_SHIFT)) & GPIO_PDOR_PDO0_MASK)
+
+#define GPIO_PDOR_PDO1_MASK                      (0x2U)
+#define GPIO_PDOR_PDO1_SHIFT                     (1U)
+/*! PDO1 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO1_SHIFT)) & GPIO_PDOR_PDO1_MASK)
+
+#define GPIO_PDOR_PDO2_MASK                      (0x4U)
+#define GPIO_PDOR_PDO2_SHIFT                     (2U)
+/*! PDO2 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO2_SHIFT)) & GPIO_PDOR_PDO2_MASK)
+
+#define GPIO_PDOR_PDO3_MASK                      (0x8U)
+#define GPIO_PDOR_PDO3_SHIFT                     (3U)
+/*! PDO3 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO3_SHIFT)) & GPIO_PDOR_PDO3_MASK)
+
+#define GPIO_PDOR_PDO4_MASK                      (0x10U)
+#define GPIO_PDOR_PDO4_SHIFT                     (4U)
+/*! PDO4 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO4_SHIFT)) & GPIO_PDOR_PDO4_MASK)
+
+#define GPIO_PDOR_PDO5_MASK                      (0x20U)
+#define GPIO_PDOR_PDO5_SHIFT                     (5U)
+/*! PDO5 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO5_SHIFT)) & GPIO_PDOR_PDO5_MASK)
+
+#define GPIO_PDOR_PDO6_MASK                      (0x40U)
+#define GPIO_PDOR_PDO6_SHIFT                     (6U)
+/*! PDO6 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO6_SHIFT)) & GPIO_PDOR_PDO6_MASK)
+
+#define GPIO_PDOR_PDO7_MASK                      (0x80U)
+#define GPIO_PDOR_PDO7_SHIFT                     (7U)
+/*! PDO7 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO7_SHIFT)) & GPIO_PDOR_PDO7_MASK)
+
+#define GPIO_PDOR_PDO8_MASK                      (0x100U)
+#define GPIO_PDOR_PDO8_SHIFT                     (8U)
+/*! PDO8 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO8_SHIFT)) & GPIO_PDOR_PDO8_MASK)
+
+#define GPIO_PDOR_PDO9_MASK                      (0x200U)
+#define GPIO_PDOR_PDO9_SHIFT                     (9U)
+/*! PDO9 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO9_SHIFT)) & GPIO_PDOR_PDO9_MASK)
+
+#define GPIO_PDOR_PDO10_MASK                     (0x400U)
+#define GPIO_PDOR_PDO10_SHIFT                    (10U)
+/*! PDO10 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO10_SHIFT)) & GPIO_PDOR_PDO10_MASK)
+
+#define GPIO_PDOR_PDO11_MASK                     (0x800U)
+#define GPIO_PDOR_PDO11_SHIFT                    (11U)
+/*! PDO11 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO11_SHIFT)) & GPIO_PDOR_PDO11_MASK)
+
+#define GPIO_PDOR_PDO12_MASK                     (0x1000U)
+#define GPIO_PDOR_PDO12_SHIFT                    (12U)
+/*! PDO12 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO12_SHIFT)) & GPIO_PDOR_PDO12_MASK)
+
+#define GPIO_PDOR_PDO13_MASK                     (0x2000U)
+#define GPIO_PDOR_PDO13_SHIFT                    (13U)
+/*! PDO13 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO13_SHIFT)) & GPIO_PDOR_PDO13_MASK)
+
+#define GPIO_PDOR_PDO14_MASK                     (0x4000U)
+#define GPIO_PDOR_PDO14_SHIFT                    (14U)
+/*! PDO14 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO14_SHIFT)) & GPIO_PDOR_PDO14_MASK)
+
+#define GPIO_PDOR_PDO15_MASK                     (0x8000U)
+#define GPIO_PDOR_PDO15_SHIFT                    (15U)
+/*! PDO15 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO15_SHIFT)) & GPIO_PDOR_PDO15_MASK)
+
+#define GPIO_PDOR_PDO16_MASK                     (0x10000U)
+#define GPIO_PDOR_PDO16_SHIFT                    (16U)
+/*! PDO16 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO16_SHIFT)) & GPIO_PDOR_PDO16_MASK)
+
+#define GPIO_PDOR_PDO17_MASK                     (0x20000U)
+#define GPIO_PDOR_PDO17_SHIFT                    (17U)
+/*! PDO17 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO17_SHIFT)) & GPIO_PDOR_PDO17_MASK)
+
+#define GPIO_PDOR_PDO18_MASK                     (0x40000U)
+#define GPIO_PDOR_PDO18_SHIFT                    (18U)
+/*! PDO18 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO18_SHIFT)) & GPIO_PDOR_PDO18_MASK)
+
+#define GPIO_PDOR_PDO19_MASK                     (0x80000U)
+#define GPIO_PDOR_PDO19_SHIFT                    (19U)
+/*! PDO19 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO19_SHIFT)) & GPIO_PDOR_PDO19_MASK)
+
+#define GPIO_PDOR_PDO20_MASK                     (0x100000U)
+#define GPIO_PDOR_PDO20_SHIFT                    (20U)
+/*! PDO20 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO20_SHIFT)) & GPIO_PDOR_PDO20_MASK)
+
+#define GPIO_PDOR_PDO21_MASK                     (0x200000U)
+#define GPIO_PDOR_PDO21_SHIFT                    (21U)
+/*! PDO21 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO21_SHIFT)) & GPIO_PDOR_PDO21_MASK)
+
+#define GPIO_PDOR_PDO22_MASK                     (0x400000U)
+#define GPIO_PDOR_PDO22_SHIFT                    (22U)
+/*! PDO22 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO22_SHIFT)) & GPIO_PDOR_PDO22_MASK)
+
+#define GPIO_PDOR_PDO23_MASK                     (0x800000U)
+#define GPIO_PDOR_PDO23_SHIFT                    (23U)
+/*! PDO23 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO23_SHIFT)) & GPIO_PDOR_PDO23_MASK)
+
+#define GPIO_PDOR_PDO24_MASK                     (0x1000000U)
+#define GPIO_PDOR_PDO24_SHIFT                    (24U)
+/*! PDO24 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO24_SHIFT)) & GPIO_PDOR_PDO24_MASK)
+
+#define GPIO_PDOR_PDO25_MASK                     (0x2000000U)
+#define GPIO_PDOR_PDO25_SHIFT                    (25U)
+/*! PDO25 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO25_SHIFT)) & GPIO_PDOR_PDO25_MASK)
+
+#define GPIO_PDOR_PDO26_MASK                     (0x4000000U)
+#define GPIO_PDOR_PDO26_SHIFT                    (26U)
+/*! PDO26 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO26_SHIFT)) & GPIO_PDOR_PDO26_MASK)
+
+#define GPIO_PDOR_PDO27_MASK                     (0x8000000U)
+#define GPIO_PDOR_PDO27_SHIFT                    (27U)
+/*! PDO27 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO27_SHIFT)) & GPIO_PDOR_PDO27_MASK)
+
+#define GPIO_PDOR_PDO28_MASK                     (0x10000000U)
+#define GPIO_PDOR_PDO28_SHIFT                    (28U)
+/*! PDO28 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO28_SHIFT)) & GPIO_PDOR_PDO28_MASK)
+
+#define GPIO_PDOR_PDO29_MASK                     (0x20000000U)
+#define GPIO_PDOR_PDO29_SHIFT                    (29U)
+/*! PDO29 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO29_SHIFT)) & GPIO_PDOR_PDO29_MASK)
+
+#define GPIO_PDOR_PDO30_MASK                     (0x40000000U)
+#define GPIO_PDOR_PDO30_SHIFT                    (30U)
+/*! PDO30 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO30_SHIFT)) & GPIO_PDOR_PDO30_MASK)
+
+#define GPIO_PDOR_PDO31_MASK                     (0x80000000U)
+#define GPIO_PDOR_PDO31_SHIFT                    (31U)
+/*! PDO31 - Port Data Output
+ *  0b0..Logic level 0
+ *  0b1..Logic level 1
+ */
+#define GPIO_PDOR_PDO31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO31_SHIFT)) & GPIO_PDOR_PDO31_MASK)
+/*! @} */
+
+/*! @name PSOR - Port Set Output */
+/*! @{ */
+
+#define GPIO_PSOR_PTSO0_MASK                     (0x1U)
+#define GPIO_PSOR_PTSO0_SHIFT                    (0U)
+/*! PTSO0 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO0(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO0_SHIFT)) & GPIO_PSOR_PTSO0_MASK)
+
+#define GPIO_PSOR_PTSO1_MASK                     (0x2U)
+#define GPIO_PSOR_PTSO1_SHIFT                    (1U)
+/*! PTSO1 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO1(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO1_SHIFT)) & GPIO_PSOR_PTSO1_MASK)
+
+#define GPIO_PSOR_PTSO2_MASK                     (0x4U)
+#define GPIO_PSOR_PTSO2_SHIFT                    (2U)
+/*! PTSO2 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO2(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO2_SHIFT)) & GPIO_PSOR_PTSO2_MASK)
+
+#define GPIO_PSOR_PTSO3_MASK                     (0x8U)
+#define GPIO_PSOR_PTSO3_SHIFT                    (3U)
+/*! PTSO3 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO3(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO3_SHIFT)) & GPIO_PSOR_PTSO3_MASK)
+
+#define GPIO_PSOR_PTSO4_MASK                     (0x10U)
+#define GPIO_PSOR_PTSO4_SHIFT                    (4U)
+/*! PTSO4 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO4(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO4_SHIFT)) & GPIO_PSOR_PTSO4_MASK)
+
+#define GPIO_PSOR_PTSO5_MASK                     (0x20U)
+#define GPIO_PSOR_PTSO5_SHIFT                    (5U)
+/*! PTSO5 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO5(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO5_SHIFT)) & GPIO_PSOR_PTSO5_MASK)
+
+#define GPIO_PSOR_PTSO6_MASK                     (0x40U)
+#define GPIO_PSOR_PTSO6_SHIFT                    (6U)
+/*! PTSO6 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO6(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO6_SHIFT)) & GPIO_PSOR_PTSO6_MASK)
+
+#define GPIO_PSOR_PTSO7_MASK                     (0x80U)
+#define GPIO_PSOR_PTSO7_SHIFT                    (7U)
+/*! PTSO7 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO7(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO7_SHIFT)) & GPIO_PSOR_PTSO7_MASK)
+
+#define GPIO_PSOR_PTSO8_MASK                     (0x100U)
+#define GPIO_PSOR_PTSO8_SHIFT                    (8U)
+/*! PTSO8 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO8(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO8_SHIFT)) & GPIO_PSOR_PTSO8_MASK)
+
+#define GPIO_PSOR_PTSO9_MASK                     (0x200U)
+#define GPIO_PSOR_PTSO9_SHIFT                    (9U)
+/*! PTSO9 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO9(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO9_SHIFT)) & GPIO_PSOR_PTSO9_MASK)
+
+#define GPIO_PSOR_PTSO10_MASK                    (0x400U)
+#define GPIO_PSOR_PTSO10_SHIFT                   (10U)
+/*! PTSO10 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO10(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO10_SHIFT)) & GPIO_PSOR_PTSO10_MASK)
+
+#define GPIO_PSOR_PTSO11_MASK                    (0x800U)
+#define GPIO_PSOR_PTSO11_SHIFT                   (11U)
+/*! PTSO11 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO11(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO11_SHIFT)) & GPIO_PSOR_PTSO11_MASK)
+
+#define GPIO_PSOR_PTSO12_MASK                    (0x1000U)
+#define GPIO_PSOR_PTSO12_SHIFT                   (12U)
+/*! PTSO12 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO12(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO12_SHIFT)) & GPIO_PSOR_PTSO12_MASK)
+
+#define GPIO_PSOR_PTSO13_MASK                    (0x2000U)
+#define GPIO_PSOR_PTSO13_SHIFT                   (13U)
+/*! PTSO13 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO13(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO13_SHIFT)) & GPIO_PSOR_PTSO13_MASK)
+
+#define GPIO_PSOR_PTSO14_MASK                    (0x4000U)
+#define GPIO_PSOR_PTSO14_SHIFT                   (14U)
+/*! PTSO14 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO14(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO14_SHIFT)) & GPIO_PSOR_PTSO14_MASK)
+
+#define GPIO_PSOR_PTSO15_MASK                    (0x8000U)
+#define GPIO_PSOR_PTSO15_SHIFT                   (15U)
+/*! PTSO15 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO15(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO15_SHIFT)) & GPIO_PSOR_PTSO15_MASK)
+
+#define GPIO_PSOR_PTSO16_MASK                    (0x10000U)
+#define GPIO_PSOR_PTSO16_SHIFT                   (16U)
+/*! PTSO16 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO16(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO16_SHIFT)) & GPIO_PSOR_PTSO16_MASK)
+
+#define GPIO_PSOR_PTSO17_MASK                    (0x20000U)
+#define GPIO_PSOR_PTSO17_SHIFT                   (17U)
+/*! PTSO17 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO17(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO17_SHIFT)) & GPIO_PSOR_PTSO17_MASK)
+
+#define GPIO_PSOR_PTSO18_MASK                    (0x40000U)
+#define GPIO_PSOR_PTSO18_SHIFT                   (18U)
+/*! PTSO18 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO18(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO18_SHIFT)) & GPIO_PSOR_PTSO18_MASK)
+
+#define GPIO_PSOR_PTSO19_MASK                    (0x80000U)
+#define GPIO_PSOR_PTSO19_SHIFT                   (19U)
+/*! PTSO19 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO19(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO19_SHIFT)) & GPIO_PSOR_PTSO19_MASK)
+
+#define GPIO_PSOR_PTSO20_MASK                    (0x100000U)
+#define GPIO_PSOR_PTSO20_SHIFT                   (20U)
+/*! PTSO20 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO20(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO20_SHIFT)) & GPIO_PSOR_PTSO20_MASK)
+
+#define GPIO_PSOR_PTSO21_MASK                    (0x200000U)
+#define GPIO_PSOR_PTSO21_SHIFT                   (21U)
+/*! PTSO21 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO21(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO21_SHIFT)) & GPIO_PSOR_PTSO21_MASK)
+
+#define GPIO_PSOR_PTSO22_MASK                    (0x400000U)
+#define GPIO_PSOR_PTSO22_SHIFT                   (22U)
+/*! PTSO22 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO22(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO22_SHIFT)) & GPIO_PSOR_PTSO22_MASK)
+
+#define GPIO_PSOR_PTSO23_MASK                    (0x800000U)
+#define GPIO_PSOR_PTSO23_SHIFT                   (23U)
+/*! PTSO23 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO23(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO23_SHIFT)) & GPIO_PSOR_PTSO23_MASK)
+
+#define GPIO_PSOR_PTSO24_MASK                    (0x1000000U)
+#define GPIO_PSOR_PTSO24_SHIFT                   (24U)
+/*! PTSO24 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO24(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO24_SHIFT)) & GPIO_PSOR_PTSO24_MASK)
+
+#define GPIO_PSOR_PTSO25_MASK                    (0x2000000U)
+#define GPIO_PSOR_PTSO25_SHIFT                   (25U)
+/*! PTSO25 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO25(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO25_SHIFT)) & GPIO_PSOR_PTSO25_MASK)
+
+#define GPIO_PSOR_PTSO26_MASK                    (0x4000000U)
+#define GPIO_PSOR_PTSO26_SHIFT                   (26U)
+/*! PTSO26 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO26(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO26_SHIFT)) & GPIO_PSOR_PTSO26_MASK)
+
+#define GPIO_PSOR_PTSO27_MASK                    (0x8000000U)
+#define GPIO_PSOR_PTSO27_SHIFT                   (27U)
+/*! PTSO27 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO27(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO27_SHIFT)) & GPIO_PSOR_PTSO27_MASK)
+
+#define GPIO_PSOR_PTSO28_MASK                    (0x10000000U)
+#define GPIO_PSOR_PTSO28_SHIFT                   (28U)
+/*! PTSO28 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO28(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO28_SHIFT)) & GPIO_PSOR_PTSO28_MASK)
+
+#define GPIO_PSOR_PTSO29_MASK                    (0x20000000U)
+#define GPIO_PSOR_PTSO29_SHIFT                   (29U)
+/*! PTSO29 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO29(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO29_SHIFT)) & GPIO_PSOR_PTSO29_MASK)
+
+#define GPIO_PSOR_PTSO30_MASK                    (0x40000000U)
+#define GPIO_PSOR_PTSO30_SHIFT                   (30U)
+/*! PTSO30 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO30(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO30_SHIFT)) & GPIO_PSOR_PTSO30_MASK)
+
+#define GPIO_PSOR_PTSO31_MASK                    (0x80000000U)
+#define GPIO_PSOR_PTSO31_SHIFT                   (31U)
+/*! PTSO31 - Port Set Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 1
+ */
+#define GPIO_PSOR_PTSO31(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO31_SHIFT)) & GPIO_PSOR_PTSO31_MASK)
+/*! @} */
+
+/*! @name PCOR - Port Clear Output */
+/*! @{ */
+
+#define GPIO_PCOR_PTCO0_MASK                     (0x1U)
+#define GPIO_PCOR_PTCO0_SHIFT                    (0U)
+/*! PTCO0 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO0(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO0_SHIFT)) & GPIO_PCOR_PTCO0_MASK)
+
+#define GPIO_PCOR_PTCO1_MASK                     (0x2U)
+#define GPIO_PCOR_PTCO1_SHIFT                    (1U)
+/*! PTCO1 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO1(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO1_SHIFT)) & GPIO_PCOR_PTCO1_MASK)
+
+#define GPIO_PCOR_PTCO2_MASK                     (0x4U)
+#define GPIO_PCOR_PTCO2_SHIFT                    (2U)
+/*! PTCO2 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO2(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO2_SHIFT)) & GPIO_PCOR_PTCO2_MASK)
+
+#define GPIO_PCOR_PTCO3_MASK                     (0x8U)
+#define GPIO_PCOR_PTCO3_SHIFT                    (3U)
+/*! PTCO3 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO3(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO3_SHIFT)) & GPIO_PCOR_PTCO3_MASK)
+
+#define GPIO_PCOR_PTCO4_MASK                     (0x10U)
+#define GPIO_PCOR_PTCO4_SHIFT                    (4U)
+/*! PTCO4 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO4(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO4_SHIFT)) & GPIO_PCOR_PTCO4_MASK)
+
+#define GPIO_PCOR_PTCO5_MASK                     (0x20U)
+#define GPIO_PCOR_PTCO5_SHIFT                    (5U)
+/*! PTCO5 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO5(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO5_SHIFT)) & GPIO_PCOR_PTCO5_MASK)
+
+#define GPIO_PCOR_PTCO6_MASK                     (0x40U)
+#define GPIO_PCOR_PTCO6_SHIFT                    (6U)
+/*! PTCO6 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO6(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO6_SHIFT)) & GPIO_PCOR_PTCO6_MASK)
+
+#define GPIO_PCOR_PTCO7_MASK                     (0x80U)
+#define GPIO_PCOR_PTCO7_SHIFT                    (7U)
+/*! PTCO7 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO7(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO7_SHIFT)) & GPIO_PCOR_PTCO7_MASK)
+
+#define GPIO_PCOR_PTCO8_MASK                     (0x100U)
+#define GPIO_PCOR_PTCO8_SHIFT                    (8U)
+/*! PTCO8 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO8(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO8_SHIFT)) & GPIO_PCOR_PTCO8_MASK)
+
+#define GPIO_PCOR_PTCO9_MASK                     (0x200U)
+#define GPIO_PCOR_PTCO9_SHIFT                    (9U)
+/*! PTCO9 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO9(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO9_SHIFT)) & GPIO_PCOR_PTCO9_MASK)
+
+#define GPIO_PCOR_PTCO10_MASK                    (0x400U)
+#define GPIO_PCOR_PTCO10_SHIFT                   (10U)
+/*! PTCO10 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO10(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO10_SHIFT)) & GPIO_PCOR_PTCO10_MASK)
+
+#define GPIO_PCOR_PTCO11_MASK                    (0x800U)
+#define GPIO_PCOR_PTCO11_SHIFT                   (11U)
+/*! PTCO11 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO11(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO11_SHIFT)) & GPIO_PCOR_PTCO11_MASK)
+
+#define GPIO_PCOR_PTCO12_MASK                    (0x1000U)
+#define GPIO_PCOR_PTCO12_SHIFT                   (12U)
+/*! PTCO12 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO12(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO12_SHIFT)) & GPIO_PCOR_PTCO12_MASK)
+
+#define GPIO_PCOR_PTCO13_MASK                    (0x2000U)
+#define GPIO_PCOR_PTCO13_SHIFT                   (13U)
+/*! PTCO13 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO13(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO13_SHIFT)) & GPIO_PCOR_PTCO13_MASK)
+
+#define GPIO_PCOR_PTCO14_MASK                    (0x4000U)
+#define GPIO_PCOR_PTCO14_SHIFT                   (14U)
+/*! PTCO14 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO14(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO14_SHIFT)) & GPIO_PCOR_PTCO14_MASK)
+
+#define GPIO_PCOR_PTCO15_MASK                    (0x8000U)
+#define GPIO_PCOR_PTCO15_SHIFT                   (15U)
+/*! PTCO15 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO15(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO15_SHIFT)) & GPIO_PCOR_PTCO15_MASK)
+
+#define GPIO_PCOR_PTCO16_MASK                    (0x10000U)
+#define GPIO_PCOR_PTCO16_SHIFT                   (16U)
+/*! PTCO16 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO16(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO16_SHIFT)) & GPIO_PCOR_PTCO16_MASK)
+
+#define GPIO_PCOR_PTCO17_MASK                    (0x20000U)
+#define GPIO_PCOR_PTCO17_SHIFT                   (17U)
+/*! PTCO17 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO17(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO17_SHIFT)) & GPIO_PCOR_PTCO17_MASK)
+
+#define GPIO_PCOR_PTCO18_MASK                    (0x40000U)
+#define GPIO_PCOR_PTCO18_SHIFT                   (18U)
+/*! PTCO18 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO18(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO18_SHIFT)) & GPIO_PCOR_PTCO18_MASK)
+
+#define GPIO_PCOR_PTCO19_MASK                    (0x80000U)
+#define GPIO_PCOR_PTCO19_SHIFT                   (19U)
+/*! PTCO19 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO19(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO19_SHIFT)) & GPIO_PCOR_PTCO19_MASK)
+
+#define GPIO_PCOR_PTCO20_MASK                    (0x100000U)
+#define GPIO_PCOR_PTCO20_SHIFT                   (20U)
+/*! PTCO20 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO20(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO20_SHIFT)) & GPIO_PCOR_PTCO20_MASK)
+
+#define GPIO_PCOR_PTCO21_MASK                    (0x200000U)
+#define GPIO_PCOR_PTCO21_SHIFT                   (21U)
+/*! PTCO21 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO21(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO21_SHIFT)) & GPIO_PCOR_PTCO21_MASK)
+
+#define GPIO_PCOR_PTCO22_MASK                    (0x400000U)
+#define GPIO_PCOR_PTCO22_SHIFT                   (22U)
+/*! PTCO22 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO22(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO22_SHIFT)) & GPIO_PCOR_PTCO22_MASK)
+
+#define GPIO_PCOR_PTCO23_MASK                    (0x800000U)
+#define GPIO_PCOR_PTCO23_SHIFT                   (23U)
+/*! PTCO23 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO23(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO23_SHIFT)) & GPIO_PCOR_PTCO23_MASK)
+
+#define GPIO_PCOR_PTCO24_MASK                    (0x1000000U)
+#define GPIO_PCOR_PTCO24_SHIFT                   (24U)
+/*! PTCO24 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO24(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO24_SHIFT)) & GPIO_PCOR_PTCO24_MASK)
+
+#define GPIO_PCOR_PTCO25_MASK                    (0x2000000U)
+#define GPIO_PCOR_PTCO25_SHIFT                   (25U)
+/*! PTCO25 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO25(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO25_SHIFT)) & GPIO_PCOR_PTCO25_MASK)
+
+#define GPIO_PCOR_PTCO26_MASK                    (0x4000000U)
+#define GPIO_PCOR_PTCO26_SHIFT                   (26U)
+/*! PTCO26 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO26(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO26_SHIFT)) & GPIO_PCOR_PTCO26_MASK)
+
+#define GPIO_PCOR_PTCO27_MASK                    (0x8000000U)
+#define GPIO_PCOR_PTCO27_SHIFT                   (27U)
+/*! PTCO27 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO27(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO27_SHIFT)) & GPIO_PCOR_PTCO27_MASK)
+
+#define GPIO_PCOR_PTCO28_MASK                    (0x10000000U)
+#define GPIO_PCOR_PTCO28_SHIFT                   (28U)
+/*! PTCO28 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO28(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO28_SHIFT)) & GPIO_PCOR_PTCO28_MASK)
+
+#define GPIO_PCOR_PTCO29_MASK                    (0x20000000U)
+#define GPIO_PCOR_PTCO29_SHIFT                   (29U)
+/*! PTCO29 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO29(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO29_SHIFT)) & GPIO_PCOR_PTCO29_MASK)
+
+#define GPIO_PCOR_PTCO30_MASK                    (0x40000000U)
+#define GPIO_PCOR_PTCO30_SHIFT                   (30U)
+/*! PTCO30 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO30(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO30_SHIFT)) & GPIO_PCOR_PTCO30_MASK)
+
+#define GPIO_PCOR_PTCO31_MASK                    (0x80000000U)
+#define GPIO_PCOR_PTCO31_SHIFT                   (31U)
+/*! PTCO31 - Port Clear Output
+ *  0b0..No change
+ *  0b1..Corresponding field in PDOR becomes 0
+ */
+#define GPIO_PCOR_PTCO31(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO31_SHIFT)) & GPIO_PCOR_PTCO31_MASK)
+/*! @} */
+
+/*! @name PTOR - Port Toggle Output */
+/*! @{ */
+
+#define GPIO_PTOR_PTTO0_MASK                     (0x1U)
+#define GPIO_PTOR_PTTO0_SHIFT                    (0U)
+/*! PTTO0 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO0(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO0_SHIFT)) & GPIO_PTOR_PTTO0_MASK)
+
+#define GPIO_PTOR_PTTO1_MASK                     (0x2U)
+#define GPIO_PTOR_PTTO1_SHIFT                    (1U)
+/*! PTTO1 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO1(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO1_SHIFT)) & GPIO_PTOR_PTTO1_MASK)
+
+#define GPIO_PTOR_PTTO2_MASK                     (0x4U)
+#define GPIO_PTOR_PTTO2_SHIFT                    (2U)
+/*! PTTO2 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO2(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO2_SHIFT)) & GPIO_PTOR_PTTO2_MASK)
+
+#define GPIO_PTOR_PTTO3_MASK                     (0x8U)
+#define GPIO_PTOR_PTTO3_SHIFT                    (3U)
+/*! PTTO3 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO3(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO3_SHIFT)) & GPIO_PTOR_PTTO3_MASK)
+
+#define GPIO_PTOR_PTTO4_MASK                     (0x10U)
+#define GPIO_PTOR_PTTO4_SHIFT                    (4U)
+/*! PTTO4 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO4(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO4_SHIFT)) & GPIO_PTOR_PTTO4_MASK)
+
+#define GPIO_PTOR_PTTO5_MASK                     (0x20U)
+#define GPIO_PTOR_PTTO5_SHIFT                    (5U)
+/*! PTTO5 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO5(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO5_SHIFT)) & GPIO_PTOR_PTTO5_MASK)
+
+#define GPIO_PTOR_PTTO6_MASK                     (0x40U)
+#define GPIO_PTOR_PTTO6_SHIFT                    (6U)
+/*! PTTO6 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO6(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO6_SHIFT)) & GPIO_PTOR_PTTO6_MASK)
+
+#define GPIO_PTOR_PTTO7_MASK                     (0x80U)
+#define GPIO_PTOR_PTTO7_SHIFT                    (7U)
+/*! PTTO7 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO7(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO7_SHIFT)) & GPIO_PTOR_PTTO7_MASK)
+
+#define GPIO_PTOR_PTTO8_MASK                     (0x100U)
+#define GPIO_PTOR_PTTO8_SHIFT                    (8U)
+/*! PTTO8 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO8(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO8_SHIFT)) & GPIO_PTOR_PTTO8_MASK)
+
+#define GPIO_PTOR_PTTO9_MASK                     (0x200U)
+#define GPIO_PTOR_PTTO9_SHIFT                    (9U)
+/*! PTTO9 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO9(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO9_SHIFT)) & GPIO_PTOR_PTTO9_MASK)
+
+#define GPIO_PTOR_PTTO10_MASK                    (0x400U)
+#define GPIO_PTOR_PTTO10_SHIFT                   (10U)
+/*! PTTO10 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO10(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO10_SHIFT)) & GPIO_PTOR_PTTO10_MASK)
+
+#define GPIO_PTOR_PTTO11_MASK                    (0x800U)
+#define GPIO_PTOR_PTTO11_SHIFT                   (11U)
+/*! PTTO11 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO11(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO11_SHIFT)) & GPIO_PTOR_PTTO11_MASK)
+
+#define GPIO_PTOR_PTTO12_MASK                    (0x1000U)
+#define GPIO_PTOR_PTTO12_SHIFT                   (12U)
+/*! PTTO12 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO12(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO12_SHIFT)) & GPIO_PTOR_PTTO12_MASK)
+
+#define GPIO_PTOR_PTTO13_MASK                    (0x2000U)
+#define GPIO_PTOR_PTTO13_SHIFT                   (13U)
+/*! PTTO13 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO13(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO13_SHIFT)) & GPIO_PTOR_PTTO13_MASK)
+
+#define GPIO_PTOR_PTTO14_MASK                    (0x4000U)
+#define GPIO_PTOR_PTTO14_SHIFT                   (14U)
+/*! PTTO14 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO14(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO14_SHIFT)) & GPIO_PTOR_PTTO14_MASK)
+
+#define GPIO_PTOR_PTTO15_MASK                    (0x8000U)
+#define GPIO_PTOR_PTTO15_SHIFT                   (15U)
+/*! PTTO15 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO15(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO15_SHIFT)) & GPIO_PTOR_PTTO15_MASK)
+
+#define GPIO_PTOR_PTTO16_MASK                    (0x10000U)
+#define GPIO_PTOR_PTTO16_SHIFT                   (16U)
+/*! PTTO16 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO16(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO16_SHIFT)) & GPIO_PTOR_PTTO16_MASK)
+
+#define GPIO_PTOR_PTTO17_MASK                    (0x20000U)
+#define GPIO_PTOR_PTTO17_SHIFT                   (17U)
+/*! PTTO17 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO17(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO17_SHIFT)) & GPIO_PTOR_PTTO17_MASK)
+
+#define GPIO_PTOR_PTTO18_MASK                    (0x40000U)
+#define GPIO_PTOR_PTTO18_SHIFT                   (18U)
+/*! PTTO18 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO18(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO18_SHIFT)) & GPIO_PTOR_PTTO18_MASK)
+
+#define GPIO_PTOR_PTTO19_MASK                    (0x80000U)
+#define GPIO_PTOR_PTTO19_SHIFT                   (19U)
+/*! PTTO19 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO19(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO19_SHIFT)) & GPIO_PTOR_PTTO19_MASK)
+
+#define GPIO_PTOR_PTTO20_MASK                    (0x100000U)
+#define GPIO_PTOR_PTTO20_SHIFT                   (20U)
+/*! PTTO20 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO20(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO20_SHIFT)) & GPIO_PTOR_PTTO20_MASK)
+
+#define GPIO_PTOR_PTTO21_MASK                    (0x200000U)
+#define GPIO_PTOR_PTTO21_SHIFT                   (21U)
+/*! PTTO21 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO21(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO21_SHIFT)) & GPIO_PTOR_PTTO21_MASK)
+
+#define GPIO_PTOR_PTTO22_MASK                    (0x400000U)
+#define GPIO_PTOR_PTTO22_SHIFT                   (22U)
+/*! PTTO22 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO22(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO22_SHIFT)) & GPIO_PTOR_PTTO22_MASK)
+
+#define GPIO_PTOR_PTTO23_MASK                    (0x800000U)
+#define GPIO_PTOR_PTTO23_SHIFT                   (23U)
+/*! PTTO23 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO23(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO23_SHIFT)) & GPIO_PTOR_PTTO23_MASK)
+
+#define GPIO_PTOR_PTTO24_MASK                    (0x1000000U)
+#define GPIO_PTOR_PTTO24_SHIFT                   (24U)
+/*! PTTO24 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO24(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO24_SHIFT)) & GPIO_PTOR_PTTO24_MASK)
+
+#define GPIO_PTOR_PTTO25_MASK                    (0x2000000U)
+#define GPIO_PTOR_PTTO25_SHIFT                   (25U)
+/*! PTTO25 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO25(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO25_SHIFT)) & GPIO_PTOR_PTTO25_MASK)
+
+#define GPIO_PTOR_PTTO26_MASK                    (0x4000000U)
+#define GPIO_PTOR_PTTO26_SHIFT                   (26U)
+/*! PTTO26 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO26(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO26_SHIFT)) & GPIO_PTOR_PTTO26_MASK)
+
+#define GPIO_PTOR_PTTO27_MASK                    (0x8000000U)
+#define GPIO_PTOR_PTTO27_SHIFT                   (27U)
+/*! PTTO27 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO27(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO27_SHIFT)) & GPIO_PTOR_PTTO27_MASK)
+
+#define GPIO_PTOR_PTTO28_MASK                    (0x10000000U)
+#define GPIO_PTOR_PTTO28_SHIFT                   (28U)
+/*! PTTO28 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO28(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO28_SHIFT)) & GPIO_PTOR_PTTO28_MASK)
+
+#define GPIO_PTOR_PTTO29_MASK                    (0x20000000U)
+#define GPIO_PTOR_PTTO29_SHIFT                   (29U)
+/*! PTTO29 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO29(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO29_SHIFT)) & GPIO_PTOR_PTTO29_MASK)
+
+#define GPIO_PTOR_PTTO30_MASK                    (0x40000000U)
+#define GPIO_PTOR_PTTO30_SHIFT                   (30U)
+/*! PTTO30 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO30(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO30_SHIFT)) & GPIO_PTOR_PTTO30_MASK)
+
+#define GPIO_PTOR_PTTO31_MASK                    (0x80000000U)
+#define GPIO_PTOR_PTTO31_SHIFT                   (31U)
+/*! PTTO31 - Port Toggle Output
+ *  0b0..No change
+ *  0b1..Set to the inverse of its current logic state
+ */
+#define GPIO_PTOR_PTTO31(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO31_SHIFT)) & GPIO_PTOR_PTTO31_MASK)
+/*! @} */
+
+/*! @name PDIR - Port Data Input */
+/*! @{ */
+
+#define GPIO_PDIR_PDI0_MASK                      (0x1U)
+#define GPIO_PDIR_PDI0_SHIFT                     (0U)
+/*! PDI0 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI0_SHIFT)) & GPIO_PDIR_PDI0_MASK)
+
+#define GPIO_PDIR_PDI1_MASK                      (0x2U)
+#define GPIO_PDIR_PDI1_SHIFT                     (1U)
+/*! PDI1 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI1_SHIFT)) & GPIO_PDIR_PDI1_MASK)
+
+#define GPIO_PDIR_PDI2_MASK                      (0x4U)
+#define GPIO_PDIR_PDI2_SHIFT                     (2U)
+/*! PDI2 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI2_SHIFT)) & GPIO_PDIR_PDI2_MASK)
+
+#define GPIO_PDIR_PDI3_MASK                      (0x8U)
+#define GPIO_PDIR_PDI3_SHIFT                     (3U)
+/*! PDI3 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI3_SHIFT)) & GPIO_PDIR_PDI3_MASK)
+
+#define GPIO_PDIR_PDI4_MASK                      (0x10U)
+#define GPIO_PDIR_PDI4_SHIFT                     (4U)
+/*! PDI4 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI4_SHIFT)) & GPIO_PDIR_PDI4_MASK)
+
+#define GPIO_PDIR_PDI5_MASK                      (0x20U)
+#define GPIO_PDIR_PDI5_SHIFT                     (5U)
+/*! PDI5 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI5_SHIFT)) & GPIO_PDIR_PDI5_MASK)
+
+#define GPIO_PDIR_PDI6_MASK                      (0x40U)
+#define GPIO_PDIR_PDI6_SHIFT                     (6U)
+/*! PDI6 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI6_SHIFT)) & GPIO_PDIR_PDI6_MASK)
+
+#define GPIO_PDIR_PDI7_MASK                      (0x80U)
+#define GPIO_PDIR_PDI7_SHIFT                     (7U)
+/*! PDI7 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI7_SHIFT)) & GPIO_PDIR_PDI7_MASK)
+
+#define GPIO_PDIR_PDI8_MASK                      (0x100U)
+#define GPIO_PDIR_PDI8_SHIFT                     (8U)
+/*! PDI8 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI8_SHIFT)) & GPIO_PDIR_PDI8_MASK)
+
+#define GPIO_PDIR_PDI9_MASK                      (0x200U)
+#define GPIO_PDIR_PDI9_SHIFT                     (9U)
+/*! PDI9 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI9_SHIFT)) & GPIO_PDIR_PDI9_MASK)
+
+#define GPIO_PDIR_PDI10_MASK                     (0x400U)
+#define GPIO_PDIR_PDI10_SHIFT                    (10U)
+/*! PDI10 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI10_SHIFT)) & GPIO_PDIR_PDI10_MASK)
+
+#define GPIO_PDIR_PDI11_MASK                     (0x800U)
+#define GPIO_PDIR_PDI11_SHIFT                    (11U)
+/*! PDI11 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI11_SHIFT)) & GPIO_PDIR_PDI11_MASK)
+
+#define GPIO_PDIR_PDI12_MASK                     (0x1000U)
+#define GPIO_PDIR_PDI12_SHIFT                    (12U)
+/*! PDI12 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI12_SHIFT)) & GPIO_PDIR_PDI12_MASK)
+
+#define GPIO_PDIR_PDI13_MASK                     (0x2000U)
+#define GPIO_PDIR_PDI13_SHIFT                    (13U)
+/*! PDI13 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI13_SHIFT)) & GPIO_PDIR_PDI13_MASK)
+
+#define GPIO_PDIR_PDI14_MASK                     (0x4000U)
+#define GPIO_PDIR_PDI14_SHIFT                    (14U)
+/*! PDI14 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI14_SHIFT)) & GPIO_PDIR_PDI14_MASK)
+
+#define GPIO_PDIR_PDI15_MASK                     (0x8000U)
+#define GPIO_PDIR_PDI15_SHIFT                    (15U)
+/*! PDI15 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI15_SHIFT)) & GPIO_PDIR_PDI15_MASK)
+
+#define GPIO_PDIR_PDI16_MASK                     (0x10000U)
+#define GPIO_PDIR_PDI16_SHIFT                    (16U)
+/*! PDI16 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI16_SHIFT)) & GPIO_PDIR_PDI16_MASK)
+
+#define GPIO_PDIR_PDI17_MASK                     (0x20000U)
+#define GPIO_PDIR_PDI17_SHIFT                    (17U)
+/*! PDI17 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI17_SHIFT)) & GPIO_PDIR_PDI17_MASK)
+
+#define GPIO_PDIR_PDI18_MASK                     (0x40000U)
+#define GPIO_PDIR_PDI18_SHIFT                    (18U)
+/*! PDI18 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI18_SHIFT)) & GPIO_PDIR_PDI18_MASK)
+
+#define GPIO_PDIR_PDI19_MASK                     (0x80000U)
+#define GPIO_PDIR_PDI19_SHIFT                    (19U)
+/*! PDI19 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI19_SHIFT)) & GPIO_PDIR_PDI19_MASK)
+
+#define GPIO_PDIR_PDI20_MASK                     (0x100000U)
+#define GPIO_PDIR_PDI20_SHIFT                    (20U)
+/*! PDI20 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI20_SHIFT)) & GPIO_PDIR_PDI20_MASK)
+
+#define GPIO_PDIR_PDI21_MASK                     (0x200000U)
+#define GPIO_PDIR_PDI21_SHIFT                    (21U)
+/*! PDI21 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI21_SHIFT)) & GPIO_PDIR_PDI21_MASK)
+
+#define GPIO_PDIR_PDI22_MASK                     (0x400000U)
+#define GPIO_PDIR_PDI22_SHIFT                    (22U)
+/*! PDI22 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI22_SHIFT)) & GPIO_PDIR_PDI22_MASK)
+
+#define GPIO_PDIR_PDI23_MASK                     (0x800000U)
+#define GPIO_PDIR_PDI23_SHIFT                    (23U)
+/*! PDI23 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI23_SHIFT)) & GPIO_PDIR_PDI23_MASK)
+
+#define GPIO_PDIR_PDI24_MASK                     (0x1000000U)
+#define GPIO_PDIR_PDI24_SHIFT                    (24U)
+/*! PDI24 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI24_SHIFT)) & GPIO_PDIR_PDI24_MASK)
+
+#define GPIO_PDIR_PDI25_MASK                     (0x2000000U)
+#define GPIO_PDIR_PDI25_SHIFT                    (25U)
+/*! PDI25 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI25_SHIFT)) & GPIO_PDIR_PDI25_MASK)
+
+#define GPIO_PDIR_PDI26_MASK                     (0x4000000U)
+#define GPIO_PDIR_PDI26_SHIFT                    (26U)
+/*! PDI26 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI26_SHIFT)) & GPIO_PDIR_PDI26_MASK)
+
+#define GPIO_PDIR_PDI27_MASK                     (0x8000000U)
+#define GPIO_PDIR_PDI27_SHIFT                    (27U)
+/*! PDI27 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI27_SHIFT)) & GPIO_PDIR_PDI27_MASK)
+
+#define GPIO_PDIR_PDI28_MASK                     (0x10000000U)
+#define GPIO_PDIR_PDI28_SHIFT                    (28U)
+/*! PDI28 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI28_SHIFT)) & GPIO_PDIR_PDI28_MASK)
+
+#define GPIO_PDIR_PDI29_MASK                     (0x20000000U)
+#define GPIO_PDIR_PDI29_SHIFT                    (29U)
+/*! PDI29 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI29_SHIFT)) & GPIO_PDIR_PDI29_MASK)
+
+#define GPIO_PDIR_PDI30_MASK                     (0x40000000U)
+#define GPIO_PDIR_PDI30_SHIFT                    (30U)
+/*! PDI30 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI30_SHIFT)) & GPIO_PDIR_PDI30_MASK)
+
+#define GPIO_PDIR_PDI31_MASK                     (0x80000000U)
+#define GPIO_PDIR_PDI31_SHIFT                    (31U)
+/*! PDI31 - Port Data Input
+ *  0b0..Logic 0
+ *  0b1..Logic 1
+ */
+#define GPIO_PDIR_PDI31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI31_SHIFT)) & GPIO_PDIR_PDI31_MASK)
+/*! @} */
+
+/*! @name PDDR - Port Data Direction */
+/*! @{ */
+
+#define GPIO_PDDR_PDD0_MASK                      (0x1U)
+#define GPIO_PDDR_PDD0_SHIFT                     (0U)
+/*! PDD0 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD0_SHIFT)) & GPIO_PDDR_PDD0_MASK)
+
+#define GPIO_PDDR_PDD1_MASK                      (0x2U)
+#define GPIO_PDDR_PDD1_SHIFT                     (1U)
+/*! PDD1 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD1_SHIFT)) & GPIO_PDDR_PDD1_MASK)
+
+#define GPIO_PDDR_PDD2_MASK                      (0x4U)
+#define GPIO_PDDR_PDD2_SHIFT                     (2U)
+/*! PDD2 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD2_SHIFT)) & GPIO_PDDR_PDD2_MASK)
+
+#define GPIO_PDDR_PDD3_MASK                      (0x8U)
+#define GPIO_PDDR_PDD3_SHIFT                     (3U)
+/*! PDD3 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD3_SHIFT)) & GPIO_PDDR_PDD3_MASK)
+
+#define GPIO_PDDR_PDD4_MASK                      (0x10U)
+#define GPIO_PDDR_PDD4_SHIFT                     (4U)
+/*! PDD4 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD4_SHIFT)) & GPIO_PDDR_PDD4_MASK)
+
+#define GPIO_PDDR_PDD5_MASK                      (0x20U)
+#define GPIO_PDDR_PDD5_SHIFT                     (5U)
+/*! PDD5 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD5_SHIFT)) & GPIO_PDDR_PDD5_MASK)
+
+#define GPIO_PDDR_PDD6_MASK                      (0x40U)
+#define GPIO_PDDR_PDD6_SHIFT                     (6U)
+/*! PDD6 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD6_SHIFT)) & GPIO_PDDR_PDD6_MASK)
+
+#define GPIO_PDDR_PDD7_MASK                      (0x80U)
+#define GPIO_PDDR_PDD7_SHIFT                     (7U)
+/*! PDD7 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD7_SHIFT)) & GPIO_PDDR_PDD7_MASK)
+
+#define GPIO_PDDR_PDD8_MASK                      (0x100U)
+#define GPIO_PDDR_PDD8_SHIFT                     (8U)
+/*! PDD8 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD8_SHIFT)) & GPIO_PDDR_PDD8_MASK)
+
+#define GPIO_PDDR_PDD9_MASK                      (0x200U)
+#define GPIO_PDDR_PDD9_SHIFT                     (9U)
+/*! PDD9 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD9_SHIFT)) & GPIO_PDDR_PDD9_MASK)
+
+#define GPIO_PDDR_PDD10_MASK                     (0x400U)
+#define GPIO_PDDR_PDD10_SHIFT                    (10U)
+/*! PDD10 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD10_SHIFT)) & GPIO_PDDR_PDD10_MASK)
+
+#define GPIO_PDDR_PDD11_MASK                     (0x800U)
+#define GPIO_PDDR_PDD11_SHIFT                    (11U)
+/*! PDD11 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD11_SHIFT)) & GPIO_PDDR_PDD11_MASK)
+
+#define GPIO_PDDR_PDD12_MASK                     (0x1000U)
+#define GPIO_PDDR_PDD12_SHIFT                    (12U)
+/*! PDD12 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD12_SHIFT)) & GPIO_PDDR_PDD12_MASK)
+
+#define GPIO_PDDR_PDD13_MASK                     (0x2000U)
+#define GPIO_PDDR_PDD13_SHIFT                    (13U)
+/*! PDD13 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD13_SHIFT)) & GPIO_PDDR_PDD13_MASK)
+
+#define GPIO_PDDR_PDD14_MASK                     (0x4000U)
+#define GPIO_PDDR_PDD14_SHIFT                    (14U)
+/*! PDD14 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD14_SHIFT)) & GPIO_PDDR_PDD14_MASK)
+
+#define GPIO_PDDR_PDD15_MASK                     (0x8000U)
+#define GPIO_PDDR_PDD15_SHIFT                    (15U)
+/*! PDD15 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD15_SHIFT)) & GPIO_PDDR_PDD15_MASK)
+
+#define GPIO_PDDR_PDD16_MASK                     (0x10000U)
+#define GPIO_PDDR_PDD16_SHIFT                    (16U)
+/*! PDD16 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD16_SHIFT)) & GPIO_PDDR_PDD16_MASK)
+
+#define GPIO_PDDR_PDD17_MASK                     (0x20000U)
+#define GPIO_PDDR_PDD17_SHIFT                    (17U)
+/*! PDD17 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD17_SHIFT)) & GPIO_PDDR_PDD17_MASK)
+
+#define GPIO_PDDR_PDD18_MASK                     (0x40000U)
+#define GPIO_PDDR_PDD18_SHIFT                    (18U)
+/*! PDD18 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD18_SHIFT)) & GPIO_PDDR_PDD18_MASK)
+
+#define GPIO_PDDR_PDD19_MASK                     (0x80000U)
+#define GPIO_PDDR_PDD19_SHIFT                    (19U)
+/*! PDD19 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD19_SHIFT)) & GPIO_PDDR_PDD19_MASK)
+
+#define GPIO_PDDR_PDD20_MASK                     (0x100000U)
+#define GPIO_PDDR_PDD20_SHIFT                    (20U)
+/*! PDD20 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD20_SHIFT)) & GPIO_PDDR_PDD20_MASK)
+
+#define GPIO_PDDR_PDD21_MASK                     (0x200000U)
+#define GPIO_PDDR_PDD21_SHIFT                    (21U)
+/*! PDD21 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD21_SHIFT)) & GPIO_PDDR_PDD21_MASK)
+
+#define GPIO_PDDR_PDD22_MASK                     (0x400000U)
+#define GPIO_PDDR_PDD22_SHIFT                    (22U)
+/*! PDD22 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD22_SHIFT)) & GPIO_PDDR_PDD22_MASK)
+
+#define GPIO_PDDR_PDD23_MASK                     (0x800000U)
+#define GPIO_PDDR_PDD23_SHIFT                    (23U)
+/*! PDD23 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD23_SHIFT)) & GPIO_PDDR_PDD23_MASK)
+
+#define GPIO_PDDR_PDD24_MASK                     (0x1000000U)
+#define GPIO_PDDR_PDD24_SHIFT                    (24U)
+/*! PDD24 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD24_SHIFT)) & GPIO_PDDR_PDD24_MASK)
+
+#define GPIO_PDDR_PDD25_MASK                     (0x2000000U)
+#define GPIO_PDDR_PDD25_SHIFT                    (25U)
+/*! PDD25 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD25_SHIFT)) & GPIO_PDDR_PDD25_MASK)
+
+#define GPIO_PDDR_PDD26_MASK                     (0x4000000U)
+#define GPIO_PDDR_PDD26_SHIFT                    (26U)
+/*! PDD26 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD26_SHIFT)) & GPIO_PDDR_PDD26_MASK)
+
+#define GPIO_PDDR_PDD27_MASK                     (0x8000000U)
+#define GPIO_PDDR_PDD27_SHIFT                    (27U)
+/*! PDD27 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD27_SHIFT)) & GPIO_PDDR_PDD27_MASK)
+
+#define GPIO_PDDR_PDD28_MASK                     (0x10000000U)
+#define GPIO_PDDR_PDD28_SHIFT                    (28U)
+/*! PDD28 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD28_SHIFT)) & GPIO_PDDR_PDD28_MASK)
+
+#define GPIO_PDDR_PDD29_MASK                     (0x20000000U)
+#define GPIO_PDDR_PDD29_SHIFT                    (29U)
+/*! PDD29 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD29_SHIFT)) & GPIO_PDDR_PDD29_MASK)
+
+#define GPIO_PDDR_PDD30_MASK                     (0x40000000U)
+#define GPIO_PDDR_PDD30_SHIFT                    (30U)
+/*! PDD30 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD30_SHIFT)) & GPIO_PDDR_PDD30_MASK)
+
+#define GPIO_PDDR_PDD31_MASK                     (0x80000000U)
+#define GPIO_PDDR_PDD31_SHIFT                    (31U)
+/*! PDD31 - Port Data Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define GPIO_PDDR_PDD31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD31_SHIFT)) & GPIO_PDDR_PDD31_MASK)
+/*! @} */
+
+/*! @name PIDR - Port Input Disable */
+/*! @{ */
+
+#define GPIO_PIDR_PID0_MASK                      (0x1U)
+#define GPIO_PIDR_PID0_SHIFT                     (0U)
+/*! PID0 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID0_SHIFT)) & GPIO_PIDR_PID0_MASK)
+
+#define GPIO_PIDR_PID1_MASK                      (0x2U)
+#define GPIO_PIDR_PID1_SHIFT                     (1U)
+/*! PID1 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID1_SHIFT)) & GPIO_PIDR_PID1_MASK)
+
+#define GPIO_PIDR_PID2_MASK                      (0x4U)
+#define GPIO_PIDR_PID2_SHIFT                     (2U)
+/*! PID2 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID2_SHIFT)) & GPIO_PIDR_PID2_MASK)
+
+#define GPIO_PIDR_PID3_MASK                      (0x8U)
+#define GPIO_PIDR_PID3_SHIFT                     (3U)
+/*! PID3 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID3_SHIFT)) & GPIO_PIDR_PID3_MASK)
+
+#define GPIO_PIDR_PID4_MASK                      (0x10U)
+#define GPIO_PIDR_PID4_SHIFT                     (4U)
+/*! PID4 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID4_SHIFT)) & GPIO_PIDR_PID4_MASK)
+
+#define GPIO_PIDR_PID5_MASK                      (0x20U)
+#define GPIO_PIDR_PID5_SHIFT                     (5U)
+/*! PID5 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID5_SHIFT)) & GPIO_PIDR_PID5_MASK)
+
+#define GPIO_PIDR_PID6_MASK                      (0x40U)
+#define GPIO_PIDR_PID6_SHIFT                     (6U)
+/*! PID6 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID6_SHIFT)) & GPIO_PIDR_PID6_MASK)
+
+#define GPIO_PIDR_PID7_MASK                      (0x80U)
+#define GPIO_PIDR_PID7_SHIFT                     (7U)
+/*! PID7 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID7_SHIFT)) & GPIO_PIDR_PID7_MASK)
+
+#define GPIO_PIDR_PID8_MASK                      (0x100U)
+#define GPIO_PIDR_PID8_SHIFT                     (8U)
+/*! PID8 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID8_SHIFT)) & GPIO_PIDR_PID8_MASK)
+
+#define GPIO_PIDR_PID9_MASK                      (0x200U)
+#define GPIO_PIDR_PID9_SHIFT                     (9U)
+/*! PID9 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID9_SHIFT)) & GPIO_PIDR_PID9_MASK)
+
+#define GPIO_PIDR_PID10_MASK                     (0x400U)
+#define GPIO_PIDR_PID10_SHIFT                    (10U)
+/*! PID10 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID10_SHIFT)) & GPIO_PIDR_PID10_MASK)
+
+#define GPIO_PIDR_PID11_MASK                     (0x800U)
+#define GPIO_PIDR_PID11_SHIFT                    (11U)
+/*! PID11 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID11_SHIFT)) & GPIO_PIDR_PID11_MASK)
+
+#define GPIO_PIDR_PID12_MASK                     (0x1000U)
+#define GPIO_PIDR_PID12_SHIFT                    (12U)
+/*! PID12 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID12_SHIFT)) & GPIO_PIDR_PID12_MASK)
+
+#define GPIO_PIDR_PID13_MASK                     (0x2000U)
+#define GPIO_PIDR_PID13_SHIFT                    (13U)
+/*! PID13 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID13_SHIFT)) & GPIO_PIDR_PID13_MASK)
+
+#define GPIO_PIDR_PID14_MASK                     (0x4000U)
+#define GPIO_PIDR_PID14_SHIFT                    (14U)
+/*! PID14 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID14_SHIFT)) & GPIO_PIDR_PID14_MASK)
+
+#define GPIO_PIDR_PID15_MASK                     (0x8000U)
+#define GPIO_PIDR_PID15_SHIFT                    (15U)
+/*! PID15 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID15_SHIFT)) & GPIO_PIDR_PID15_MASK)
+
+#define GPIO_PIDR_PID16_MASK                     (0x10000U)
+#define GPIO_PIDR_PID16_SHIFT                    (16U)
+/*! PID16 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID16_SHIFT)) & GPIO_PIDR_PID16_MASK)
+
+#define GPIO_PIDR_PID17_MASK                     (0x20000U)
+#define GPIO_PIDR_PID17_SHIFT                    (17U)
+/*! PID17 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID17_SHIFT)) & GPIO_PIDR_PID17_MASK)
+
+#define GPIO_PIDR_PID18_MASK                     (0x40000U)
+#define GPIO_PIDR_PID18_SHIFT                    (18U)
+/*! PID18 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID18_SHIFT)) & GPIO_PIDR_PID18_MASK)
+
+#define GPIO_PIDR_PID19_MASK                     (0x80000U)
+#define GPIO_PIDR_PID19_SHIFT                    (19U)
+/*! PID19 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID19_SHIFT)) & GPIO_PIDR_PID19_MASK)
+
+#define GPIO_PIDR_PID20_MASK                     (0x100000U)
+#define GPIO_PIDR_PID20_SHIFT                    (20U)
+/*! PID20 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID20_SHIFT)) & GPIO_PIDR_PID20_MASK)
+
+#define GPIO_PIDR_PID21_MASK                     (0x200000U)
+#define GPIO_PIDR_PID21_SHIFT                    (21U)
+/*! PID21 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID21_SHIFT)) & GPIO_PIDR_PID21_MASK)
+
+#define GPIO_PIDR_PID22_MASK                     (0x400000U)
+#define GPIO_PIDR_PID22_SHIFT                    (22U)
+/*! PID22 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID22_SHIFT)) & GPIO_PIDR_PID22_MASK)
+
+#define GPIO_PIDR_PID23_MASK                     (0x800000U)
+#define GPIO_PIDR_PID23_SHIFT                    (23U)
+/*! PID23 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID23_SHIFT)) & GPIO_PIDR_PID23_MASK)
+
+#define GPIO_PIDR_PID24_MASK                     (0x1000000U)
+#define GPIO_PIDR_PID24_SHIFT                    (24U)
+/*! PID24 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID24_SHIFT)) & GPIO_PIDR_PID24_MASK)
+
+#define GPIO_PIDR_PID25_MASK                     (0x2000000U)
+#define GPIO_PIDR_PID25_SHIFT                    (25U)
+/*! PID25 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID25_SHIFT)) & GPIO_PIDR_PID25_MASK)
+
+#define GPIO_PIDR_PID26_MASK                     (0x4000000U)
+#define GPIO_PIDR_PID26_SHIFT                    (26U)
+/*! PID26 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID26_SHIFT)) & GPIO_PIDR_PID26_MASK)
+
+#define GPIO_PIDR_PID27_MASK                     (0x8000000U)
+#define GPIO_PIDR_PID27_SHIFT                    (27U)
+/*! PID27 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID27_SHIFT)) & GPIO_PIDR_PID27_MASK)
+
+#define GPIO_PIDR_PID28_MASK                     (0x10000000U)
+#define GPIO_PIDR_PID28_SHIFT                    (28U)
+/*! PID28 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID28_SHIFT)) & GPIO_PIDR_PID28_MASK)
+
+#define GPIO_PIDR_PID29_MASK                     (0x20000000U)
+#define GPIO_PIDR_PID29_SHIFT                    (29U)
+/*! PID29 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID29_SHIFT)) & GPIO_PIDR_PID29_MASK)
+
+#define GPIO_PIDR_PID30_MASK                     (0x40000000U)
+#define GPIO_PIDR_PID30_SHIFT                    (30U)
+/*! PID30 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID30_SHIFT)) & GPIO_PIDR_PID30_MASK)
+
+#define GPIO_PIDR_PID31_MASK                     (0x80000000U)
+#define GPIO_PIDR_PID31_SHIFT                    (31U)
+/*! PID31 - Port Input Disable
+ *  0b0..Configured for general-purpose input
+ *  0b1..Disabled for general-purpose input
+ */
+#define GPIO_PIDR_PID31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID31_SHIFT)) & GPIO_PIDR_PID31_MASK)
+/*! @} */
+
+/*! @name PDR - Pin Data */
+/*! @{ */
+
+#define GPIO_PDR_PD_MASK                         (0x1U)
+#define GPIO_PDR_PD_SHIFT                        (0U)
+/*! PD - Pin Data (I/O)
+ *  0b0..Logic zero
+ *  0b1..Logic one
+ */
+#define GPIO_PDR_PD(x)                           (((uint8_t)(((uint8_t)(x)) << GPIO_PDR_PD_SHIFT)) & GPIO_PDR_PD_MASK)
+/*! @} */
+
+/*! @name ICR - Interrupt Control 0..Interrupt Control 31 */
+/*! @{ */
+
+#define GPIO_ICR_IRQC_MASK                       (0xF0000U)
+#define GPIO_ICR_IRQC_SHIFT                      (16U)
+/*! IRQC - Interrupt Configuration
+ *  0b0000..ISF is disabled
+ *  0b0001..ISF and DMA request on rising edge
+ *  0b0010..ISF and DMA request on falling edge
+ *  0b0011..ISF and DMA request on either edge
+ *  0b0100..Reserved
+ *  0b0101..ISF sets on rising edge
+ *  0b0110..ISF sets on falling edge
+ *  0b0111..ISF sets on either edge
+ *  0b1000..ISF and interrupt when logic 0
+ *  0b1001..ISF and interrupt on rising edge
+ *  0b1010..ISF and interrupt on falling edge
+ *  0b1011..ISF and Interrupt on either edge
+ *  0b1100..ISF and interrupt when logic 1
+ *  0b1101..Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers
+ *          to generate the output trigger for use by other peripherals)
+ *  0b1110..Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other
+ *          enabled triggers to generate the output trigger for use by other peripherals)
+ *  0b1111..Reserved
+ */
+#define GPIO_ICR_IRQC(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQC_SHIFT)) & GPIO_ICR_IRQC_MASK)
+
+#define GPIO_ICR_ISF_MASK                        (0x1000000U)
+#define GPIO_ICR_ISF_SHIFT                       (24U)
+/*! ISF - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ICR_ISF(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_ISF_SHIFT)) & GPIO_ICR_ISF_MASK)
+/*! @} */
+
+/*! @name GICLR - Global Interrupt Control Low */
+/*! @{ */
+
+#define GPIO_GICLR_GIWE0_MASK                    (0x1U)
+#define GPIO_GICLR_GIWE0_SHIFT                   (0U)
+/*! GIWE0 - Global Interrupt Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define GPIO_GICLR_GIWE0(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE0_SHIFT)) & GPIO_GICLR_GIWE0_MASK)
+
+#define GPIO_GICLR_GIWE1_MASK                    (0x2U)
+#define GPIO_GICLR_GIWE1_SHIFT                   (1U)
+/*! GIWE1 - Global Interrupt Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define GPIO_GICLR_GIWE1(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE1_SHIFT)) & GPIO_GICLR_GIWE1_MASK)
+
+#define GPIO_GICLR_GIWE2_MASK                    (0x4U)
+#define GPIO_GICLR_GIWE2_SHIFT                   (2U)
+/*! GIWE2 - Global Interrupt Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define GPIO_GICLR_GIWE2(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE2_SHIFT)) & GPIO_GICLR_GIWE2_MASK)
+
+#define GPIO_GICLR_GIWE3_MASK                    (0x8U)
+#define GPIO_GICLR_GIWE3_SHIFT                   (3U)
+/*! GIWE3 - Global Interrupt Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define GPIO_GICLR_GIWE3(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE3_SHIFT)) & GPIO_GICLR_GIWE3_MASK)
+
+#define GPIO_GICLR_GIWE4_MASK                    (0x10U)
+#define GPIO_GICLR_GIWE4_SHIFT                   (4U)
+/*! GIWE4 - Global Interrupt Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define GPIO_GICLR_GIWE4(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE4_SHIFT)) & GPIO_GICLR_GIWE4_MASK)
+
+#define GPIO_GICLR_GIWE5_MASK                    (0x20U)
+#define GPIO_GICLR_GIWE5_SHIFT                   (5U)
+/*! GIWE5 - Global Interrupt Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define GPIO_GICLR_GIWE5(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE5_SHIFT)) & GPIO_GICLR_GIWE5_MASK)
+
+#define GPIO_GICLR_GIWE6_MASK                    (0x40U)
+#define GPIO_GICLR_GIWE6_SHIFT                   (6U)
+/*! GIWE6 - Global Interrupt Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define GPIO_GICLR_GIWE6(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE6_SHIFT)) & GPIO_GICLR_GIWE6_MASK)
+
+#define GPIO_GICLR_GIWE7_MASK                    (0x80U)
+#define GPIO_GICLR_GIWE7_SHIFT                   (7U)
+/*! GIWE7 - Global Interrupt Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define GPIO_GICLR_GIWE7(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE7_SHIFT)) & GPIO_GICLR_GIWE7_MASK)
+
+#define GPIO_GICLR_GIWE8_MASK                    (0x100U)
+#define GPIO_GICLR_GIWE8_SHIFT                   (8U)
+/*! GIWE8 - Global Interrupt Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define GPIO_GICLR_GIWE8(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE8_SHIFT)) & GPIO_GICLR_GIWE8_MASK)
+
+#define GPIO_GICLR_GIWE9_MASK                    (0x200U)
+#define GPIO_GICLR_GIWE9_SHIFT                   (9U)
+/*! GIWE9 - Global Interrupt Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define GPIO_GICLR_GIWE9(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE9_SHIFT)) & GPIO_GICLR_GIWE9_MASK)
+
+#define GPIO_GICLR_GIWE10_MASK                   (0x400U)
+#define GPIO_GICLR_GIWE10_SHIFT                  (10U)
+/*! GIWE10 - Global Interrupt Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define GPIO_GICLR_GIWE10(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE10_SHIFT)) & GPIO_GICLR_GIWE10_MASK)
+
+#define GPIO_GICLR_GIWE11_MASK                   (0x800U)
+#define GPIO_GICLR_GIWE11_SHIFT                  (11U)
+/*! GIWE11 - Global Interrupt Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define GPIO_GICLR_GIWE11(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE11_SHIFT)) & GPIO_GICLR_GIWE11_MASK)
+
+#define GPIO_GICLR_GIWE12_MASK                   (0x1000U)
+#define GPIO_GICLR_GIWE12_SHIFT                  (12U)
+/*! GIWE12 - Global Interrupt Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define GPIO_GICLR_GIWE12(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE12_SHIFT)) & GPIO_GICLR_GIWE12_MASK)
+
+#define GPIO_GICLR_GIWE13_MASK                   (0x2000U)
+#define GPIO_GICLR_GIWE13_SHIFT                  (13U)
+/*! GIWE13 - Global Interrupt Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define GPIO_GICLR_GIWE13(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE13_SHIFT)) & GPIO_GICLR_GIWE13_MASK)
+
+#define GPIO_GICLR_GIWE14_MASK                   (0x4000U)
+#define GPIO_GICLR_GIWE14_SHIFT                  (14U)
+/*! GIWE14 - Global Interrupt Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define GPIO_GICLR_GIWE14(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE14_SHIFT)) & GPIO_GICLR_GIWE14_MASK)
+
+#define GPIO_GICLR_GIWE15_MASK                   (0x8000U)
+#define GPIO_GICLR_GIWE15_SHIFT                  (15U)
+/*! GIWE15 - Global Interrupt Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define GPIO_GICLR_GIWE15(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE15_SHIFT)) & GPIO_GICLR_GIWE15_MASK)
+
+#define GPIO_GICLR_GIWD_MASK                     (0xFFFF0000U)
+#define GPIO_GICLR_GIWD_SHIFT                    (16U)
+/*! GIWD - Global Interrupt Write Data */
+#define GPIO_GICLR_GIWD(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWD_SHIFT)) & GPIO_GICLR_GIWD_MASK)
+/*! @} */
+
+/*! @name GICHR - Global Interrupt Control High */
+/*! @{ */
+
+#define GPIO_GICHR_GIWE16_MASK                   (0x1U)
+#define GPIO_GICHR_GIWE16_SHIFT                  (0U)
+/*! GIWE16 - Global Interrupt Write Enable
+ *  0b0..Not updated.
+ *  0b1..Updated
+ */
+#define GPIO_GICHR_GIWE16(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE16_SHIFT)) & GPIO_GICHR_GIWE16_MASK)
+
+#define GPIO_GICHR_GIWE17_MASK                   (0x2U)
+#define GPIO_GICHR_GIWE17_SHIFT                  (1U)
+/*! GIWE17 - Global Interrupt Write Enable
+ *  0b0..Not updated.
+ *  0b1..Updated
+ */
+#define GPIO_GICHR_GIWE17(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE17_SHIFT)) & GPIO_GICHR_GIWE17_MASK)
+
+#define GPIO_GICHR_GIWE18_MASK                   (0x4U)
+#define GPIO_GICHR_GIWE18_SHIFT                  (2U)
+/*! GIWE18 - Global Interrupt Write Enable
+ *  0b0..Not updated.
+ *  0b1..Updated
+ */
+#define GPIO_GICHR_GIWE18(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE18_SHIFT)) & GPIO_GICHR_GIWE18_MASK)
+
+#define GPIO_GICHR_GIWE19_MASK                   (0x8U)
+#define GPIO_GICHR_GIWE19_SHIFT                  (3U)
+/*! GIWE19 - Global Interrupt Write Enable
+ *  0b0..Not updated.
+ *  0b1..Updated
+ */
+#define GPIO_GICHR_GIWE19(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE19_SHIFT)) & GPIO_GICHR_GIWE19_MASK)
+
+#define GPIO_GICHR_GIWE20_MASK                   (0x10U)
+#define GPIO_GICHR_GIWE20_SHIFT                  (4U)
+/*! GIWE20 - Global Interrupt Write Enable
+ *  0b0..Not updated.
+ *  0b1..Updated
+ */
+#define GPIO_GICHR_GIWE20(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE20_SHIFT)) & GPIO_GICHR_GIWE20_MASK)
+
+#define GPIO_GICHR_GIWE21_MASK                   (0x20U)
+#define GPIO_GICHR_GIWE21_SHIFT                  (5U)
+/*! GIWE21 - Global Interrupt Write Enable
+ *  0b0..Not updated.
+ *  0b1..Updated
+ */
+#define GPIO_GICHR_GIWE21(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE21_SHIFT)) & GPIO_GICHR_GIWE21_MASK)
+
+#define GPIO_GICHR_GIWE22_MASK                   (0x40U)
+#define GPIO_GICHR_GIWE22_SHIFT                  (6U)
+/*! GIWE22 - Global Interrupt Write Enable
+ *  0b0..Not updated.
+ *  0b1..Updated
+ */
+#define GPIO_GICHR_GIWE22(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE22_SHIFT)) & GPIO_GICHR_GIWE22_MASK)
+
+#define GPIO_GICHR_GIWE23_MASK                   (0x80U)
+#define GPIO_GICHR_GIWE23_SHIFT                  (7U)
+/*! GIWE23 - Global Interrupt Write Enable
+ *  0b0..Not updated.
+ *  0b1..Updated
+ */
+#define GPIO_GICHR_GIWE23(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE23_SHIFT)) & GPIO_GICHR_GIWE23_MASK)
+
+#define GPIO_GICHR_GIWE24_MASK                   (0x100U)
+#define GPIO_GICHR_GIWE24_SHIFT                  (8U)
+/*! GIWE24 - Global Interrupt Write Enable
+ *  0b0..Not updated.
+ *  0b1..Updated
+ */
+#define GPIO_GICHR_GIWE24(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE24_SHIFT)) & GPIO_GICHR_GIWE24_MASK)
+
+#define GPIO_GICHR_GIWE25_MASK                   (0x200U)
+#define GPIO_GICHR_GIWE25_SHIFT                  (9U)
+/*! GIWE25 - Global Interrupt Write Enable
+ *  0b0..Not updated.
+ *  0b1..Updated
+ */
+#define GPIO_GICHR_GIWE25(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE25_SHIFT)) & GPIO_GICHR_GIWE25_MASK)
+
+#define GPIO_GICHR_GIWE26_MASK                   (0x400U)
+#define GPIO_GICHR_GIWE26_SHIFT                  (10U)
+/*! GIWE26 - Global Interrupt Write Enable
+ *  0b0..Not updated.
+ *  0b1..Updated
+ */
+#define GPIO_GICHR_GIWE26(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE26_SHIFT)) & GPIO_GICHR_GIWE26_MASK)
+
+#define GPIO_GICHR_GIWE27_MASK                   (0x800U)
+#define GPIO_GICHR_GIWE27_SHIFT                  (11U)
+/*! GIWE27 - Global Interrupt Write Enable
+ *  0b0..Not updated.
+ *  0b1..Updated
+ */
+#define GPIO_GICHR_GIWE27(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE27_SHIFT)) & GPIO_GICHR_GIWE27_MASK)
+
+#define GPIO_GICHR_GIWE28_MASK                   (0x1000U)
+#define GPIO_GICHR_GIWE28_SHIFT                  (12U)
+/*! GIWE28 - Global Interrupt Write Enable
+ *  0b0..Not updated.
+ *  0b1..Updated
+ */
+#define GPIO_GICHR_GIWE28(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE28_SHIFT)) & GPIO_GICHR_GIWE28_MASK)
+
+#define GPIO_GICHR_GIWE29_MASK                   (0x2000U)
+#define GPIO_GICHR_GIWE29_SHIFT                  (13U)
+/*! GIWE29 - Global Interrupt Write Enable
+ *  0b0..Not updated.
+ *  0b1..Updated
+ */
+#define GPIO_GICHR_GIWE29(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE29_SHIFT)) & GPIO_GICHR_GIWE29_MASK)
+
+#define GPIO_GICHR_GIWE30_MASK                   (0x4000U)
+#define GPIO_GICHR_GIWE30_SHIFT                  (14U)
+/*! GIWE30 - Global Interrupt Write Enable
+ *  0b0..Not updated.
+ *  0b1..Updated
+ */
+#define GPIO_GICHR_GIWE30(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE30_SHIFT)) & GPIO_GICHR_GIWE30_MASK)
+
+#define GPIO_GICHR_GIWE31_MASK                   (0x8000U)
+#define GPIO_GICHR_GIWE31_SHIFT                  (15U)
+/*! GIWE31 - Global Interrupt Write Enable
+ *  0b0..Not updated.
+ *  0b1..Updated
+ */
+#define GPIO_GICHR_GIWE31(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE31_SHIFT)) & GPIO_GICHR_GIWE31_MASK)
+
+#define GPIO_GICHR_GIWD_MASK                     (0xFFFF0000U)
+#define GPIO_GICHR_GIWD_SHIFT                    (16U)
+/*! GIWD - Global Interrupt Write Data */
+#define GPIO_GICHR_GIWD(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWD_SHIFT)) & GPIO_GICHR_GIWD_MASK)
+/*! @} */
+
+/*! @name ISFR - Interrupt Status Flag */
+/*! @{ */
+
+#define GPIO_ISFR_ISF0_MASK                      (0x1U)
+#define GPIO_ISFR_ISF0_SHIFT                     (0U)
+/*! ISF0 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF0_SHIFT)) & GPIO_ISFR_ISF0_MASK)
+
+#define GPIO_ISFR_ISF1_MASK                      (0x2U)
+#define GPIO_ISFR_ISF1_SHIFT                     (1U)
+/*! ISF1 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF1_SHIFT)) & GPIO_ISFR_ISF1_MASK)
+
+#define GPIO_ISFR_ISF2_MASK                      (0x4U)
+#define GPIO_ISFR_ISF2_SHIFT                     (2U)
+/*! ISF2 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF2_SHIFT)) & GPIO_ISFR_ISF2_MASK)
+
+#define GPIO_ISFR_ISF3_MASK                      (0x8U)
+#define GPIO_ISFR_ISF3_SHIFT                     (3U)
+/*! ISF3 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF3_SHIFT)) & GPIO_ISFR_ISF3_MASK)
+
+#define GPIO_ISFR_ISF4_MASK                      (0x10U)
+#define GPIO_ISFR_ISF4_SHIFT                     (4U)
+/*! ISF4 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF4_SHIFT)) & GPIO_ISFR_ISF4_MASK)
+
+#define GPIO_ISFR_ISF5_MASK                      (0x20U)
+#define GPIO_ISFR_ISF5_SHIFT                     (5U)
+/*! ISF5 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF5_SHIFT)) & GPIO_ISFR_ISF5_MASK)
+
+#define GPIO_ISFR_ISF6_MASK                      (0x40U)
+#define GPIO_ISFR_ISF6_SHIFT                     (6U)
+/*! ISF6 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF6_SHIFT)) & GPIO_ISFR_ISF6_MASK)
+
+#define GPIO_ISFR_ISF7_MASK                      (0x80U)
+#define GPIO_ISFR_ISF7_SHIFT                     (7U)
+/*! ISF7 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF7_SHIFT)) & GPIO_ISFR_ISF7_MASK)
+
+#define GPIO_ISFR_ISF8_MASK                      (0x100U)
+#define GPIO_ISFR_ISF8_SHIFT                     (8U)
+/*! ISF8 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF8_SHIFT)) & GPIO_ISFR_ISF8_MASK)
+
+#define GPIO_ISFR_ISF9_MASK                      (0x200U)
+#define GPIO_ISFR_ISF9_SHIFT                     (9U)
+/*! ISF9 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF9_SHIFT)) & GPIO_ISFR_ISF9_MASK)
+
+#define GPIO_ISFR_ISF10_MASK                     (0x400U)
+#define GPIO_ISFR_ISF10_SHIFT                    (10U)
+/*! ISF10 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF10_SHIFT)) & GPIO_ISFR_ISF10_MASK)
+
+#define GPIO_ISFR_ISF11_MASK                     (0x800U)
+#define GPIO_ISFR_ISF11_SHIFT                    (11U)
+/*! ISF11 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF11_SHIFT)) & GPIO_ISFR_ISF11_MASK)
+
+#define GPIO_ISFR_ISF12_MASK                     (0x1000U)
+#define GPIO_ISFR_ISF12_SHIFT                    (12U)
+/*! ISF12 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF12_SHIFT)) & GPIO_ISFR_ISF12_MASK)
+
+#define GPIO_ISFR_ISF13_MASK                     (0x2000U)
+#define GPIO_ISFR_ISF13_SHIFT                    (13U)
+/*! ISF13 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF13_SHIFT)) & GPIO_ISFR_ISF13_MASK)
+
+#define GPIO_ISFR_ISF14_MASK                     (0x4000U)
+#define GPIO_ISFR_ISF14_SHIFT                    (14U)
+/*! ISF14 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF14_SHIFT)) & GPIO_ISFR_ISF14_MASK)
+
+#define GPIO_ISFR_ISF15_MASK                     (0x8000U)
+#define GPIO_ISFR_ISF15_SHIFT                    (15U)
+/*! ISF15 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF15_SHIFT)) & GPIO_ISFR_ISF15_MASK)
+
+#define GPIO_ISFR_ISF16_MASK                     (0x10000U)
+#define GPIO_ISFR_ISF16_SHIFT                    (16U)
+/*! ISF16 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF16_SHIFT)) & GPIO_ISFR_ISF16_MASK)
+
+#define GPIO_ISFR_ISF17_MASK                     (0x20000U)
+#define GPIO_ISFR_ISF17_SHIFT                    (17U)
+/*! ISF17 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF17_SHIFT)) & GPIO_ISFR_ISF17_MASK)
+
+#define GPIO_ISFR_ISF18_MASK                     (0x40000U)
+#define GPIO_ISFR_ISF18_SHIFT                    (18U)
+/*! ISF18 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF18_SHIFT)) & GPIO_ISFR_ISF18_MASK)
+
+#define GPIO_ISFR_ISF19_MASK                     (0x80000U)
+#define GPIO_ISFR_ISF19_SHIFT                    (19U)
+/*! ISF19 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF19_SHIFT)) & GPIO_ISFR_ISF19_MASK)
+
+#define GPIO_ISFR_ISF20_MASK                     (0x100000U)
+#define GPIO_ISFR_ISF20_SHIFT                    (20U)
+/*! ISF20 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF20_SHIFT)) & GPIO_ISFR_ISF20_MASK)
+
+#define GPIO_ISFR_ISF21_MASK                     (0x200000U)
+#define GPIO_ISFR_ISF21_SHIFT                    (21U)
+/*! ISF21 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF21_SHIFT)) & GPIO_ISFR_ISF21_MASK)
+
+#define GPIO_ISFR_ISF22_MASK                     (0x400000U)
+#define GPIO_ISFR_ISF22_SHIFT                    (22U)
+/*! ISF22 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF22_SHIFT)) & GPIO_ISFR_ISF22_MASK)
+
+#define GPIO_ISFR_ISF23_MASK                     (0x800000U)
+#define GPIO_ISFR_ISF23_SHIFT                    (23U)
+/*! ISF23 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF23_SHIFT)) & GPIO_ISFR_ISF23_MASK)
+
+#define GPIO_ISFR_ISF24_MASK                     (0x1000000U)
+#define GPIO_ISFR_ISF24_SHIFT                    (24U)
+/*! ISF24 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF24_SHIFT)) & GPIO_ISFR_ISF24_MASK)
+
+#define GPIO_ISFR_ISF25_MASK                     (0x2000000U)
+#define GPIO_ISFR_ISF25_SHIFT                    (25U)
+/*! ISF25 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF25_SHIFT)) & GPIO_ISFR_ISF25_MASK)
+
+#define GPIO_ISFR_ISF26_MASK                     (0x4000000U)
+#define GPIO_ISFR_ISF26_SHIFT                    (26U)
+/*! ISF26 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF26_SHIFT)) & GPIO_ISFR_ISF26_MASK)
+
+#define GPIO_ISFR_ISF27_MASK                     (0x8000000U)
+#define GPIO_ISFR_ISF27_SHIFT                    (27U)
+/*! ISF27 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF27_SHIFT)) & GPIO_ISFR_ISF27_MASK)
+
+#define GPIO_ISFR_ISF28_MASK                     (0x10000000U)
+#define GPIO_ISFR_ISF28_SHIFT                    (28U)
+/*! ISF28 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF28_SHIFT)) & GPIO_ISFR_ISF28_MASK)
+
+#define GPIO_ISFR_ISF29_MASK                     (0x20000000U)
+#define GPIO_ISFR_ISF29_SHIFT                    (29U)
+/*! ISF29 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF29_SHIFT)) & GPIO_ISFR_ISF29_MASK)
+
+#define GPIO_ISFR_ISF30_MASK                     (0x40000000U)
+#define GPIO_ISFR_ISF30_SHIFT                    (30U)
+/*! ISF30 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF30_SHIFT)) & GPIO_ISFR_ISF30_MASK)
+
+#define GPIO_ISFR_ISF31_MASK                     (0x80000000U)
+#define GPIO_ISFR_ISF31_SHIFT                    (31U)
+/*! ISF31 - Interrupt Status Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define GPIO_ISFR_ISF31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF31_SHIFT)) & GPIO_ISFR_ISF31_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_GPIO_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_INPUTMUX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_INPUTMUX.h
new file mode 100644
index 0000000000..1c003127e6
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_INPUTMUX.h
@@ -0,0 +1,5123 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for INPUTMUX
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_INPUTMUX.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for INPUTMUX
+ *
+ * CMSIS Peripheral Access Layer for INPUTMUX
+ */
+
+#if !defined(PERI_INPUTMUX_H_)
+#define PERI_INPUTMUX_H_                         /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- INPUTMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
+ * @{
+ */
+
+/** INPUTMUX - Size of Registers Arrays */
+#define INPUTMUX_CTIMERA_COUNT                    4u
+#define INPUTMUX_CTIMERB_COUNT                    4u
+#define INPUTMUX_CTIMERC_COUNT                    4u
+#define INPUTMUX_SMARTDMA_TRIGGER_INPUTN_COUNT    8u
+#define INPUTMUX_AOI1_INPUTM_COUNT                16u
+#define INPUTMUX_ADC0_TRIGM_COUNT                 4u
+#define INPUTMUX_ADC1_TRIGM_COUNT                 4u
+#define INPUTMUX_FLEXPWM0_FAULT_COUNT             4u
+#define INPUTMUX_FLEXPWM1_FAULT_COUNT             4u
+#define INPUTMUX_AOI0_INPUTK_COUNT                16u
+#define INPUTMUX_EXT_TRIGN_COUNT                  8u
+#define INPUTMUX_TRIGFILP_COUNT                   12u
+
+/** INPUTMUX - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[32];
+  __IO uint32_t CTIMER0CAP[INPUTMUX_CTIMERA_COUNT]; /**< Capture select register for CTIMER inputs, array offset: 0x20, array step: 0x4 */
+  __IO uint32_t TIMER0TRIG;                        /**< Trigger register for TIMER0, offset: 0x30 */
+       uint8_t RESERVED_1[12];
+  __IO uint32_t CTIMER1CAP[INPUTMUX_CTIMERB_COUNT]; /**< Capture select register for CTIMER inputs, array offset: 0x40, array step: 0x4 */
+  __IO uint32_t TIMER1TRIG;                        /**< Trigger register for TIMER1, offset: 0x50 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t CTIMER2CAP[INPUTMUX_CTIMERC_COUNT]; /**< Capture select register for CTIMER inputs, array offset: 0x60, array step: 0x4 */
+  __IO uint32_t TIMER2TRIG;                        /**< Trigger register for TIMER2 inputs, offset: 0x70 */
+       uint8_t RESERVED_3[44];
+  __IO uint32_t SMARTDMA_TRIG[INPUTMUX_SMARTDMA_TRIGGER_INPUTN_COUNT]; /**< SmartDMA Trigger Input Connections, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_4[192];
+  __IO uint32_t FREQMEAS_REF;                      /**< Selection for frequency measurement reference clock, offset: 0x180 */
+  __IO uint32_t FREQMEAS_TAR;                      /**< Selection for frequency measurement reference clock, offset: 0x184 */
+       uint8_t RESERVED_5[120];
+  __IO uint32_t AOI1_INPUT[INPUTMUX_AOI1_INPUTM_COUNT]; /**< AOI1 trigger input connections 0, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_6[32];
+  __IO uint32_t CMP0_TRIG;                         /**< CMP0 input connections, offset: 0x260 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t ADC0_TRIG[INPUTMUX_ADC0_TRIGM_COUNT]; /**< ADC Trigger input connections, array offset: 0x280, array step: 0x4 */
+       uint8_t RESERVED_8[48];
+  __IO uint32_t ADC1_TRIG[INPUTMUX_ADC1_TRIGM_COUNT]; /**< ADC Trigger input connections, array offset: 0x2C0, array step: 0x4 */
+       uint8_t RESERVED_9[144];
+  __IO uint32_t QDC0_TRIG;                         /**< QDC0 Trigger Input Connections, offset: 0x360 */
+  __IO uint32_t QDC0_HOME;                         /**< QDC0 Trigger Input Connections, offset: 0x364 */
+  __IO uint32_t QDC0_INDEX;                        /**< QDC0 Trigger Input Connections, offset: 0x368 */
+  __IO uint32_t QDC0_PHASEB;                       /**< QDC0 Trigger Input Connections, offset: 0x36C */
+  __IO uint32_t QDC0_PHASEA;                       /**< QDC0 Trigger Input Connections, offset: 0x370 */
+  __IO uint32_t QDC0_ICAP1;                        /**< QDC0 Trigger Input Connections, offset: 0x374 */
+  __IO uint32_t QDC0_ICAP2;                        /**< QDC0 Trigger Input Connections, offset: 0x378 */
+  __IO uint32_t QDC0_ICAP3;                        /**< QDC0 Trigger Input Connections, offset: 0x37C */
+  __IO uint32_t QDC1_TRIG;                         /**< QDC1 Trigger Input Connections, offset: 0x380 */
+  __IO uint32_t QDC1_HOME;                         /**< QDC1 Trigger Input Connections, offset: 0x384 */
+  __IO uint32_t QDC1_INDEX;                        /**< QDC1 Trigger Input Connections, offset: 0x388 */
+  __IO uint32_t QDC1_PHASEB;                       /**< QDC1 Trigger Input Connections, offset: 0x38C */
+  __IO uint32_t QDC1_PHASEA;                       /**< QDC1 Trigger Input Connections, offset: 0x390 */
+  __IO uint32_t QDC1_ICAP1;                        /**< QDC1 Trigger Input Connections, offset: 0x394 */
+  __IO uint32_t QDC1_ICAP2;                        /**< QDC1 Trigger Input Connections, offset: 0x398 */
+  __IO uint32_t QDC1_ICAP3;                        /**< QDC1 Trigger Input Connections, offset: 0x39C */
+  __IO uint32_t FLEXPWM0_SM0_EXTA0;                /**< PWM0 input trigger connections, offset: 0x3A0 */
+  __IO uint32_t FLEXPWM0_SM0_EXTSYNC;              /**< PWM0 input trigger connections, offset: 0x3A4 */
+  __IO uint32_t FLEXPWM0_SM1_EXTA;                 /**< PWM0 input trigger connections, offset: 0x3A8 */
+  __IO uint32_t FLEXPWM0_SM1_EXTSYNC;              /**< PWM0 input trigger connections, offset: 0x3AC */
+  __IO uint32_t FLEXPWM0_SM2_EXTA;                 /**< PWM0 input trigger connections, offset: 0x3B0 */
+  __IO uint32_t FLEXPWM0_SM2_EXTSYNC;              /**< PWM0 input trigger connections, offset: 0x3B4 */
+  __IO uint32_t FLEXPWM0_SM3_EXTA0;                /**< PWM0 input trigger connections, offset: 0x3B8 */
+  __IO uint32_t FLEXPWM0_SM3_EXTSYNC;              /**< PWM0 input trigger connections, offset: 0x3BC */
+  __IO uint32_t FLEXPWM0_FAULT[INPUTMUX_FLEXPWM0_FAULT_COUNT]; /**< PWM0 Fault Input Trigger Connections, array offset: 0x3C0, array step: 0x4 */
+  __IO uint32_t FLEXPWM0_FORCE;                    /**< PWM0 input trigger connections, offset: 0x3D0 */
+       uint8_t RESERVED_10[12];
+  __IO uint32_t FLEXPWM1_SM0_EXTA0;                /**< PWM1 input trigger connections, offset: 0x3E0 */
+  __IO uint32_t FLEXPWM1_SM0_EXTSYNC;              /**< PWM1 input trigger connections, offset: 0x3E4 */
+  __IO uint32_t FLEXPWM1_SM1_EXTA;                 /**< PWM1 input trigger connections, offset: 0x3E8 */
+  __IO uint32_t FLEXPWM1_SM1_EXTSYNC;              /**< PWM1 input trigger connections, offset: 0x3EC */
+  __IO uint32_t FLEXPWM1_SM2_EXTA;                 /**< PWM1 input trigger connections, offset: 0x3F0 */
+  __IO uint32_t FLEXPWM1_SM2_EXTSYNC;              /**< PWM1 input trigger connections, offset: 0x3F4 */
+  __IO uint32_t FLEXPWM1_SM3_EXTA0;                /**< PWM1 input trigger connections, offset: 0x3F8 */
+  __IO uint32_t FLEXPWM1_SM3_EXTSYNC;              /**< PWM1 input trigger connections, offset: 0x3FC */
+  __IO uint32_t FLEXPWM1_FAULT[INPUTMUX_FLEXPWM1_FAULT_COUNT]; /**< PWM1 Fault Input Trigger Connections, array offset: 0x400, array step: 0x4 */
+  __IO uint32_t FLEXPWM1_FORCE;                    /**< PWM1 input trigger connections, offset: 0x410 */
+       uint8_t RESERVED_11[12];
+  __IO uint32_t PWM0_EXT_CLK;                      /**< PWM0 external clock trigger, offset: 0x420 */
+  __IO uint32_t PWM1_EXT_CLK;                      /**< PWM1 external clock trigger, offset: 0x424 */
+       uint8_t RESERVED_12[24];
+  __IO uint32_t AOI0_INPUT[INPUTMUX_AOI0_INPUTK_COUNT]; /**< AOI0 trigger input connections 0, array offset: 0x440, array step: 0x4 */
+       uint8_t RESERVED_13[64];
+  __IO uint32_t TRIG_OUT[INPUTMUX_EXT_TRIGN_COUNT]; /**< EXT trigger connections, array offset: 0x4C0, array step: 0x4 */
+  __IO uint32_t CMP1_TRIG;                         /**< CMP1 input connections, offset: 0x4E0 */
+       uint8_t RESERVED_14[28];
+  __IO uint32_t CMP2_TRIG;                         /**< CMP2 input connections, offset: 0x500 */
+       uint8_t RESERVED_15[156];
+  __IO uint32_t LPI2C0_TRIG;                       /**< LPI2C0 trigger input connections, offset: 0x5A0 */
+       uint8_t RESERVED_16[28];
+  __IO uint32_t LPI2C1_TRIG;                       /**< LPI2C1 trigger input connections, offset: 0x5C0 */
+       uint8_t RESERVED_17[28];
+  __IO uint32_t LPSPI0_TRIG;                       /**< LPSPI0 trigger input connections, offset: 0x5E0 */
+       uint8_t RESERVED_18[28];
+  __IO uint32_t LPSPI1_TRIG;                       /**< LPSPI1 trigger input connections, offset: 0x600 */
+       uint8_t RESERVED_19[28];
+  __IO uint32_t LPUART0r;                          /**< LPUART0 trigger input connections, offset: 0x620, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART0' */
+       uint8_t RESERVED_20[28];
+  __IO uint32_t LPUART1r;                          /**< LPUART1 trigger input connections, offset: 0x640, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART1' */
+       uint8_t RESERVED_21[28];
+  __IO uint32_t LPUART2r;                          /**< LPUART2 trigger input connections, offset: 0x660, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART2' */
+       uint8_t RESERVED_22[28];
+  __IO uint32_t LPUART3r;                          /**< LPUART3 trigger input connections, offset: 0x680, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART3' */
+       uint8_t RESERVED_23[892];
+  __IO uint32_t TRIGFIL_PRSC;                      /**< Trigger filter prescaller, offset: 0xA00 */
+  __I  uint32_t TRIGFIL_STAT0;                     /**< Trigger filter stat, offset: 0xA04 */
+       uint8_t RESERVED_24[8];
+  __IO uint32_t TRIGFIL[INPUTMUX_TRIGFILP_COUNT];  /**< TRIGFIL control, array offset: 0xA10, array step: 0x4 */
+} INPUTMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- INPUTMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
+ * @{
+ */
+
+/*! @name CTIMERA_CTIMER0CAP - Capture select register for CTIMER inputs */
+/*! @{ */
+
+#define INPUTMUX_CTIMERA_CTIMER0CAP_INP_MASK     (0x7FU)
+#define INPUTMUX_CTIMERA_CTIMER0CAP_INP_SHIFT    (0U)
+/*! INP - Input number for CTIMER0
+ *  0b0000000..Reserved
+ *  0b0000001..CT_INP0 input is selected
+ *  0b0000010..CT_INP1 input is selected
+ *  0b0000011..CT_INP2 input is selected
+ *  0b0000100..CT_INP3 input is selected
+ *  0b0000101..CT_INP4 input is selected
+ *  0b0000110..CT_INP5 input is selected
+ *  0b0000111..CT_INP6 input is selected
+ *  0b0001000..CT_INP7 input is selected
+ *  0b0001001..CT_INP8 input is selected
+ *  0b0001010..CT_INP9 input is selected
+ *  0b0001011..CT_INP10 input is selected
+ *  0b0001100..Reserved
+ *  0b0001101..CT_INP12 input is selected
+ *  0b0001110..CT_INP13 input is selected
+ *  0b0001111..CT_INP14 input is selected
+ *  0b0010000..CT_INP15 input is selected
+ *  0b0010001..CT_INP16 input is selected
+ *  0b0010010..CT_INP17 input is selected
+ *  0b0010011..CT_INP18 input is selected
+ *  0b0010100..CT_INP19 input is selected
+ *  0b0010101..Reserved
+ *  0b0010110..AOI0_OUT0 input is selected
+ *  0b0010111..AOI0_OUT1 input is selected
+ *  0b0011000..AOI0_OUT2 input is selected
+ *  0b0011001..AOI0_OUT3 input is selected
+ *  0b0011010..ADC0_tcomp[0]
+ *  0b0011011..ADC0_tcomp[1]
+ *  0b0011100..ADC0_tcomp[2]
+ *  0b0011101..ADC0_tcomp[3] input is selected
+ *  0b0011110..CMP0_OUT is selected
+ *  0b0011111..CMP1_OUT is selected
+ *  0b0100000..CMP2_OUT is selected
+ *  0b0100001..CTimer1_MAT1 input is selected
+ *  0b0100010..CTimer1_MAT2 input is selected
+ *  0b0100011..CTimer1_MAT3 input is selected
+ *  0b0100100..CTimer2_MAT1 input is selected
+ *  0b0100101..CTimer2_MAT2 input is selected
+ *  0b0100110..CTimer2_MAT3 input is selected
+ *  0b0100111..QDC0_CMP_FLAG0 is selected
+ *  0b0101000..QDC0_CMP_FLAG1 input is selected
+ *  0b0101001..QDC0_CMP_FLAG2 input is selected
+ *  0b0101010..QDC0_CMP_FLAG3 input is selected
+ *  0b0101011..QDC0_POS_MATCH0 input is selected
+ *  0b0101100..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0101101..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0101110..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0101111..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0110000..LPI2C0 Master End of Packet input is selected
+ *  0b0110001..LPI2C0 Slave End of Packet input is selected
+ *  0b0110010..LPI2C1 Master End of Packet input is selected
+ *  0b0110011..LPI2C1 Slave End of Packet input is selected
+ *  0b0110100..LPSPI0 End of Frame input is selected
+ *  0b0110101..LPSPI0 Received Data Word input is selected
+ *  0b0110110..LPSPI1 End of Frame input is selected
+ *  0b0110111..LPSPI1 Received Data Word input is selected
+ *  0b0111000..LPUART0 Received Data Word input is selected
+ *  0b0111001..LPUART0 Transmitted Data Word input is selected
+ *  0b0111010..LPUART0 Receive Line Idle input is selected
+ *  0b0111011..LPUART1 Received Data Word input is selected
+ *  0b0111100..LPUART1 Transmitted Data Word input is selected
+ *  0b0111101..LPUART1 Receive Line Idle input is selected
+ *  0b0111110..LPUART2 Received Data Word input is selected
+ *  0b0111111..LPUART2 Transmitted Data Word input is selected
+ *  0b1000000..LPUART2 Receive Line Idle input is selected
+ *  0b1000001..LPUART3 Received Data Word input is selected
+ *  0b1000010..LPUART3 Transmitted Data Word input is selected
+ *  0b1000011..LPUART3 Receive Line Idle input is selected
+ *  0b1000100..Reserved
+ *  0b1000101..Reserved
+ *  0b1000110..Reserved
+ *  0b1000111..AOI1_OUT0 input is selected
+ *  0b1001000..AOI1_OUT1 input is selected
+ *  0b1001001..AOI1_OUT2 input is selected
+ *  0b1001010..AOI1_OUT3 input is selected
+ *  0b1001011..ADC1_tcomp[0] input is selected
+ *  0b1001100..ADC1_tcomp[1] input is selected
+ *  0b1001101..ADC1_tcomp[2] input is selected
+ *  0b1001110..ADC1_tcomp[3] input is selected
+ *  0b1001111..Reserved
+ *  0b1010000..Reserved
+ *  0b1010001..Reserved
+ *  0b1010010..Reserved
+ *  0b1010011..Reserved
+ *  0b1010100..Reserved
+ *  0b1010101..QDC1_CMP_FLAG0 input is selected
+ *  0b1010110..QDC1_CMP_FLAG1 input is selected
+ *  0b1010111..QDC1_CMP_FLAG2 input is selected
+ *  0b1011000..QDC1_CMP_FLAG3 input is selected
+ *  0b1011001..QDC1_POS_MATCH0 input is selected
+ *  0b1011010..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b1011011..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b1011100..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b1011101..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b1011110..Reserved
+ *  0b1011111..Reserved
+ *  0b1100000..Reserved
+ *  0b1100001..Reserved
+ *  0b1100010..Reserved
+ *  0b1100011..Reserved
+ *  0b1100100..Reserved
+ *  0b1100101..Reserved
+ *  0b1100110..Reserved
+ *  0b1100111..Reserved
+ *  0b1101000..Reserved
+ *  0b1101001..Reserved
+ *  0b1101010..Reserved
+ *  0b1101011..Reserved
+ *  0b1101100..Reserved
+ *  0b1101101..Reserved
+ *  0b1101110..Reserved
+ *  0b1101111..Reserved
+ *  0b1110000..Reserved
+ */
+#define INPUTMUX_CTIMERA_CTIMER0CAP_INP(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERA_CTIMER0CAP_INP_SHIFT)) & INPUTMUX_CTIMERA_CTIMER0CAP_INP_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_CTIMERA_CTIMER0CAP */
+#define INPUTMUX_CTIMERA_CTIMER0CAP_COUNT        (4U)
+
+/*! @name TIMER0TRIG - Trigger register for TIMER0 */
+/*! @{ */
+
+#define INPUTMUX_TIMER0TRIG_INP_MASK             (0x7FU)
+#define INPUTMUX_TIMER0TRIG_INP_SHIFT            (0U)
+/*! INP - Input number for CTIMER0
+ *  0b0000000..Reserved
+ *  0b0000001..CT_INP0 input is selected
+ *  0b0000010..CT_INP1 input is selected
+ *  0b0000011..CT_INP2 input is selected
+ *  0b0000100..CT_INP3 input is selected
+ *  0b0000101..CT_INP4 input is selected
+ *  0b0000110..CT_INP5 input is selected
+ *  0b0000111..CT_INP6 input is selected
+ *  0b0001000..CT_INP7 input is selected
+ *  0b0001001..CT_INP8 input is selected
+ *  0b0001010..CT_INP9 input is selected
+ *  0b0001011..CT_INP10 input is selected
+ *  0b0001100..Reserved
+ *  0b0001101..CT_INP12 input is selected
+ *  0b0001110..CT_INP13 input is selected
+ *  0b0001111..CT_INP14 input is selected
+ *  0b0010000..CT_INP15 input is selected
+ *  0b0010001..CT_INP16 input is selected
+ *  0b0010010..CT_INP17 input is selected
+ *  0b0010011..CT_INP18 input is selected
+ *  0b0010100..CT_INP19 input is selected
+ *  0b0010101..Reserved
+ *  0b0010110..AOI0_OUT0 input is selected
+ *  0b0010111..AOI0_OUT1 input is selected
+ *  0b0011000..AOI0_OUT2 input is selected
+ *  0b0011001..AOI0_OUT3 input is selected
+ *  0b0011010..ADC0_tcomp[0]
+ *  0b0011011..ADC0_tcomp[1]
+ *  0b0011100..ADC0_tcomp[2]
+ *  0b0011101..ADC0_tcomp[3] input is selected
+ *  0b0011110..CMP0_OUT is selected
+ *  0b0011111..CMP1_OUT is selected
+ *  0b0100000..CMP2_OUT is selected
+ *  0b0100001..CTimer1_MAT1 input is selected
+ *  0b0100010..CTimer1_MAT2 input is selected
+ *  0b0100011..CTimer1_MAT3 input is selected
+ *  0b0100100..CTimer2_MAT1 input is selected
+ *  0b0100101..CTimer2_MAT2 input is selected
+ *  0b0100110..CTimer2_MAT3 input is selected
+ *  0b0100111..QDC0_CMP_FLAG0 is selected
+ *  0b0101000..QDC0_CMP_FLAG1 input is selected
+ *  0b0101001..QDC0_CMP_FLAG2 input is selected
+ *  0b0101010..QDC0_CMP_FLAG3 input is selected
+ *  0b0101011..QDC0_POS_MATCH0 input is selected
+ *  0b0101100..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0101101..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0101110..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0101111..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0110000..LPI2C0 Master End of Packet input is selected
+ *  0b0110001..LPI2C0 Slave End of Packet input is selected
+ *  0b0110010..LPI2C1 Master End of Packet input is selected
+ *  0b0110011..LPI2C1 Slave End of Packet input is selected
+ *  0b0110100..LPSPI0 End of Frame input is selected
+ *  0b0110101..LPSPI0 Received Data Word input is selected
+ *  0b0110110..LPSPI1 End of Frame input is selected
+ *  0b0110111..LPSPI1 Received Data Word input is selected
+ *  0b0111000..LPUART0 Received Data Word input is selected
+ *  0b0111001..LPUART0 Transmitted Data Word input is selected
+ *  0b0111010..LPUART0 Receive Line Idle input is selected
+ *  0b0111011..LPUART1 Received Data Word input is selected
+ *  0b0111100..LPUART1 Transmitted Data Word input is selected
+ *  0b0111101..LPUART1 Receive Line Idle input is selected
+ *  0b0111110..LPUART2 Received Data Word input is selected
+ *  0b0111111..LPUART2 Transmitted Data Word input is selected
+ *  0b1000000..LPUART2 Receive Line Idle input is selected
+ *  0b1000001..LPUART3 Received Data Word input is selected
+ *  0b1000010..LPUART3 Transmitted Data Word input is selected
+ *  0b1000011..LPUART3 Receive Line Idle input is selected
+ *  0b1000100..Reserved
+ *  0b1000101..Reserved
+ *  0b1000110..Reserved
+ *  0b1000111..AOI1_OUT0 input is selected
+ *  0b1001000..AOI1_OUT1 input is selected
+ *  0b1001001..AOI1_OUT2 input is selected
+ *  0b1001010..AOI1_OUT3 input is selected
+ *  0b1001011..ADC1_tcomp[0] input is selected
+ *  0b1001100..ADC1_tcomp[1] input is selected
+ *  0b1001101..ADC1_tcomp[2] input is selected
+ *  0b1001110..ADC1_tcomp[3] input is selected
+ *  0b1001111..Reserved
+ *  0b1010000..Reserved
+ *  0b1010001..Reserved
+ *  0b1010010..Reserved
+ *  0b1010011..Reserved
+ *  0b1010100..Reserved
+ *  0b1010101..QDC1_CMP_FLAG0 input is selected
+ *  0b1010110..QDC1_CMP_FLAG1 input is selected
+ *  0b1010111..QDC1_CMP_FLAG2 input is selected
+ *  0b1011000..QDC1_CMP_FLAG3 input is selected
+ *  0b1011001..QDC1_POS_MATCH0 input is selected
+ *  0b1011010..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b1011011..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b1011100..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b1011101..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b1011110..Reserved
+ *  0b1011111..Reserved
+ *  0b1100000..Reserved
+ *  0b1100001..Reserved
+ *  0b1100010..Reserved
+ *  0b1100011..Reserved
+ *  0b1100100..Reserved
+ *  0b1100101..Reserved
+ *  0b1100110..Reserved
+ *  0b1100111..Reserved
+ *  0b1101000..Reserved
+ *  0b1101001..Reserved
+ *  0b1101010..Reserved
+ *  0b1101011..Reserved
+ *  0b1101100..Reserved
+ *  0b1101101..Reserved
+ *  0b1101110..Reserved
+ *  0b1101111..Reserved
+ *  0b1110000..Reserved
+ */
+#define INPUTMUX_TIMER0TRIG_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0TRIG_INP_SHIFT)) & INPUTMUX_TIMER0TRIG_INP_MASK)
+/*! @} */
+
+/*! @name CTIMERB_CTIMER1CAP - Capture select register for CTIMER inputs */
+/*! @{ */
+
+#define INPUTMUX_CTIMERB_CTIMER1CAP_INP_MASK     (0x7FU)
+#define INPUTMUX_CTIMERB_CTIMER1CAP_INP_SHIFT    (0U)
+/*! INP - Input number for CTIMER1
+ *  0b0000000..Reserved
+ *  0b0000001..CT_INP0 input is selected
+ *  0b0000010..CT_INP1 input is selected
+ *  0b0000011..CT_INP2 input is selected
+ *  0b0000100..CT_INP3 input is selected
+ *  0b0000101..CT_INP4 input is selected
+ *  0b0000110..CT_INP5 input is selected
+ *  0b0000111..CT_INP6 input is selected
+ *  0b0001000..CT_INP7 input is selected
+ *  0b0001001..CT_INP8 input is selected
+ *  0b0001010..CT_INP9 input is selected
+ *  0b0001011..CT_INP10 input is selected
+ *  0b0001100..Reserved
+ *  0b0001101..CT_INP12 input is selected
+ *  0b0001110..CT_INP13 input is selected
+ *  0b0001111..CT_INP14 input is selected
+ *  0b0010000..CT_INP15 input is selected
+ *  0b0010001..CT_INP16 input is selected
+ *  0b0010010..CT_INP17 input is selected
+ *  0b0010011..CT_INP18 input is selected
+ *  0b0010100..CT_INP19 input is selected
+ *  0b0010101..Reserved
+ *  0b0010110..AOI0_OUT0 input is selected
+ *  0b0010111..AOI0_OUT1 input is selected
+ *  0b0011000..AOI0_OUT2 input is selected
+ *  0b0011001..AOI0_OUT3 input is selected
+ *  0b0011010..ADC0_tcomp[0]
+ *  0b0011011..ADC0_tcomp[1]
+ *  0b0011100..ADC0_tcomp[2]
+ *  0b0011101..ADC0_tcomp[3] input is selected
+ *  0b0011110..CMP0_OUT is selected
+ *  0b0011111..CMP1_OUT is selected
+ *  0b0100000..CMP2_OUT is selected
+ *  0b0100001..CTimer0_MAT1 input is selected
+ *  0b0100010..CTimer0_MAT2 input is selected
+ *  0b0100011..CTimer0_MAT3 input is selected
+ *  0b0100100..CTimer2_MAT1 input is selected
+ *  0b0100101..CTimer2_MAT2 input is selected
+ *  0b0100110..CTimer2_MAT3 input is selected
+ *  0b0100111..QDC0_CMP_FLAG0 is selected
+ *  0b0101000..QDC0_CMP_FLAG1 input is selected
+ *  0b0101001..QDC0_CMP_FLAG2 input is selected
+ *  0b0101010..QDC0_CMP_FLAG3 input is selected
+ *  0b0101011..QDC0_POS_MATCH0 input is selected
+ *  0b0101100..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0101101..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0101110..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0101111..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0110000..LPI2C0 Master End of Packet input is selected
+ *  0b0110001..LPI2C0 Slave End of Packet input is selected
+ *  0b0110010..LPI2C1 Master End of Packet input is selected
+ *  0b0110011..LPI2C1 Slave End of Packet input is selected
+ *  0b0110100..LPSPI0 End of Frame input is selected
+ *  0b0110101..LPSPI0 Received Data Word input is selected
+ *  0b0110110..LPSPI1 End of Frame input is selected
+ *  0b0110111..LPSPI1 Received Data Word input is selected
+ *  0b0111000..LPUART0 Received Data Word input is selected
+ *  0b0111001..LPUART0 Transmitted Data Word input is selected
+ *  0b0111010..LPUART0 Receive Line Idle input is selected
+ *  0b0111011..LPUART1 Received Data Word input is selected
+ *  0b0111100..LPUART1 Transmitted Data Word input is selected
+ *  0b0111101..LPUART1 Receive Line Idle input is selected
+ *  0b0111110..LPUART2 Received Data Word input is selected
+ *  0b0111111..LPUART2 Transmitted Data Word input is selected
+ *  0b1000000..LPUART2 Receive Line Idle input is selected
+ *  0b1000001..LPUART3 Received Data Word input is selected
+ *  0b1000010..LPUART3 Transmitted Data Word input is selected
+ *  0b1000011..LPUART3 Receive Line Idle input is selected
+ *  0b1000100..Reserved
+ *  0b1000101..Reserved
+ *  0b1000110..Reserved
+ *  0b1000111..AOI1_OUT0 input is selected
+ *  0b1001000..AOI1_OUT1 input is selected
+ *  0b1001001..AOI1_OUT2 input is selected
+ *  0b1001010..AOI1_OUT3 input is selected
+ *  0b1001011..ADC1_tcomp[0] input is selected
+ *  0b1001100..ADC1_tcomp[1] input is selected
+ *  0b1001101..ADC1_tcomp[2] input is selected
+ *  0b1001110..ADC1_tcomp[3] input is selected
+ *  0b1001111..Reserved
+ *  0b1010000..Reserved
+ *  0b1010001..Reserved
+ *  0b1010010..Reserved
+ *  0b1010011..Reserved
+ *  0b1010100..Reserved
+ *  0b1010101..QDC1_CMP_FLAG0 input is selected
+ *  0b1010110..QDC1_CMP_FLAG1 input is selected
+ *  0b1010111..QDC1_CMP_FLAG2 input is selected
+ *  0b1011000..QDC1_CMP_FLAG3 input is selected
+ *  0b1011001..QDC1_POS_MATCH0 input is selected
+ *  0b1011010..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b1011011..PWM1_SM1_MUX_TRIGmbc_bt_spec0 input is selected
+ *  0b1011100..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b1011101..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b1011110..Reserved
+ *  0b1011111..Reserved
+ *  0b1100000..Reserved
+ *  0b1100001..Reserved
+ *  0b1100010..Reserved
+ *  0b1100011..Reserved
+ *  0b1100100..Reserved
+ *  0b1100101..Reserved
+ *  0b1100110..Reserved
+ *  0b1100111..Reserved
+ *  0b1101000..Reserved
+ *  0b1101001..Reserved
+ *  0b1101010..Reserved
+ *  0b1101011..Reserved
+ *  0b1101100..Reserved
+ *  0b1101101..Reserved
+ *  0b1101110..Reserved
+ *  0b1101111..Reserved
+ *  0b1110000..Reserved
+ */
+#define INPUTMUX_CTIMERB_CTIMER1CAP_INP(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERB_CTIMER1CAP_INP_SHIFT)) & INPUTMUX_CTIMERB_CTIMER1CAP_INP_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_CTIMERB_CTIMER1CAP */
+#define INPUTMUX_CTIMERB_CTIMER1CAP_COUNT        (4U)
+
+/*! @name TIMER1TRIG - Trigger register for TIMER1 */
+/*! @{ */
+
+#define INPUTMUX_TIMER1TRIG_INP_MASK             (0x7FU)
+#define INPUTMUX_TIMER1TRIG_INP_SHIFT            (0U)
+/*! INP - Input number for CTIMER1
+ *  0b0000000..Reserved
+ *  0b0000001..CT_INP0 input is selected
+ *  0b0000010..CT_INP1 input is selected
+ *  0b0000011..CT_INP2 input is selected
+ *  0b0000100..CT_INP3 input is selected
+ *  0b0000101..CT_INP4 input is selected
+ *  0b0000110..CT_INP5 input is selected
+ *  0b0000111..CT_INP6 input is selected
+ *  0b0001000..CT_INP7 input is selected
+ *  0b0001001..CT_INP8 input is selected
+ *  0b0001010..CT_INP9 input is selected
+ *  0b0001011..CT_INP10 input is selected
+ *  0b0001100..Reserved
+ *  0b0001101..CT_INP12 input is selected
+ *  0b0001110..CT_INP13 input is selected
+ *  0b0001111..CT_INP14 input is selected
+ *  0b0010000..CT_INP15 input is selected
+ *  0b0010001..CT_INP16 input is selected
+ *  0b0010010..CT_INP17 input is selected
+ *  0b0010011..CT_INP18 input is selected
+ *  0b0010100..CT_INP19 input is selected
+ *  0b0010101..Reserved
+ *  0b0010110..AOI0_OUT0 input is selected
+ *  0b0010111..AOI0_OUT1 input is selected
+ *  0b0011000..AOI0_OUT2 input is selected
+ *  0b0011001..AOI0_OUT3 input is selected
+ *  0b0011010..ADC0_tcomp[0]
+ *  0b0011011..ADC0_tcomp[1]
+ *  0b0011100..ADC0_tcomp[2]
+ *  0b0011101..ADC0_tcomp[3] input is selected
+ *  0b0011110..CMP0_OUT is selected
+ *  0b0011111..CMP1_OUT is selected
+ *  0b0100000..CMP2_OUT is selected
+ *  0b0100001..CTimer0_MAT1 input is selected
+ *  0b0100010..CTimer0_MAT2 input is selected
+ *  0b0100011..CTimer0_MAT3 input is selected
+ *  0b0100100..CTimer2_MAT1 input is selected
+ *  0b0100101..CTimer2_MAT2 input is selected
+ *  0b0100110..CTimer2_MAT3 input is selected
+ *  0b0100111..QDC0_CMP_FLAG0 is selected
+ *  0b0101000..QDC0_CMP_FLAG1 input is selected
+ *  0b0101001..QDC0_CMP_FLAG2 input is selected
+ *  0b0101010..QDC0_CMP_FLAG3 input is selected
+ *  0b0101011..QDC0_POS_MATCH0 input is selected
+ *  0b0101100..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0101101..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0101110..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0101111..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0110000..LPI2C0 Master End of Packet input is selected
+ *  0b0110001..LPI2C0 Slave End of Packet input is selected
+ *  0b0110010..LPI2C1 Master End of Packet input is selected
+ *  0b0110011..LPI2C1 Slave End of Packet input is selected
+ *  0b0110100..LPSPI0 End of Frame input is selected
+ *  0b0110101..LPSPI0 Received Data Word input is selected
+ *  0b0110110..LPSPI1 End of Frame input is selected
+ *  0b0110111..LPSPI1 Received Data Word input is selected
+ *  0b0111000..LPUART0 Received Data Word input is selected
+ *  0b0111001..LPUART0 Transmitted Data Word input is selected
+ *  0b0111010..LPUART0 Receive Line Idle input is selected
+ *  0b0111011..LPUART1 Received Data Word input is selected
+ *  0b0111100..LPUART1 Transmitted Data Word input is selected
+ *  0b0111101..LPUART1 Receive Line Idle input is selected
+ *  0b0111110..LPUART2 Received Data Word input is selected
+ *  0b0111111..LPUART2 Transmitted Data Word input is selected
+ *  0b1000000..LPUART2 Receive Line Idle input is selected
+ *  0b1000001..LPUART3 Received Data Word input is selected
+ *  0b1000010..LPUART3 Transmitted Data Word input is selected
+ *  0b1000011..LPUART3 Receive Line Idle input is selected
+ *  0b1000100..Reserved
+ *  0b1000101..Reserved
+ *  0b1000110..Reserved
+ *  0b1000111..AOI1_OUT0 input is selected
+ *  0b1001000..AOI1_OUT1 input is selected
+ *  0b1001001..AOI1_OUT2 input is selected
+ *  0b1001010..AOI1_OUT3 input is selected
+ *  0b1001011..ADC1_tcomp[0] input is selected
+ *  0b1001100..ADC1_tcomp[1] input is selected
+ *  0b1001101..ADC1_tcomp[2] input is selected
+ *  0b1001110..ADC1_tcomp[3] input is selected
+ *  0b1001111..Reserved
+ *  0b1010000..Reserved
+ *  0b1010001..Reserved
+ *  0b1010010..Reserved
+ *  0b1010011..Reserved
+ *  0b1010100..Reserved
+ *  0b1010101..QDC1_CMP_FLAG0 input is selected
+ *  0b1010110..QDC1_CMP_FLAG1 input is selected
+ *  0b1010111..QDC1_CMP_FLAG2 input is selected
+ *  0b1011000..QDC1_CMP_FLAG3 input is selected
+ *  0b1011001..QDC1_POS_MATCH0 input is selected
+ *  0b1011010..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b1011011..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b1011100..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b1011101..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b1011110..Reserved
+ *  0b1011111..Reserved
+ *  0b1100000..Reserved
+ *  0b1100001..Reserved
+ *  0b1100010..Reserved
+ *  0b1100011..Reserved
+ *  0b1100100..Reserved
+ *  0b1100101..Reserved
+ *  0b1100110..Reserved
+ *  0b1100111..Reserved
+ *  0b1101000..Reserved
+ *  0b1101001..Reserved
+ *  0b1101010..Reserved
+ *  0b1101011..Reserved
+ *  0b1101100..Reserved
+ *  0b1101101..Reserved
+ *  0b1101110..Reserved
+ *  0b1101111..Reserved
+ *  0b1110000..Reserved
+ */
+#define INPUTMUX_TIMER1TRIG_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1TRIG_INP_SHIFT)) & INPUTMUX_TIMER1TRIG_INP_MASK)
+/*! @} */
+
+/*! @name CTIMERC_CTIMER2CAP - Capture select register for CTIMER inputs */
+/*! @{ */
+
+#define INPUTMUX_CTIMERC_CTIMER2CAP_INP_MASK     (0x7FU)
+#define INPUTMUX_CTIMERC_CTIMER2CAP_INP_SHIFT    (0U)
+/*! INP - Input number for CTIMER2
+ *  0b0000000..Reserved
+ *  0b0000001..CT_INP0 input is selected
+ *  0b0000010..CT_INP1 input is selected
+ *  0b0000011..CT_INP2 input is selected
+ *  0b0000100..CT_INP3 input is selected
+ *  0b0000101..CT_INP4 input is selected
+ *  0b0000110..CT_INP5 input is selected
+ *  0b0000111..CT_INP6 input is selected
+ *  0b0001000..CT_INP7 input is selected
+ *  0b0001001..CT_INP8 input is selected
+ *  0b0001010..CT_INP9 input is selected
+ *  0b0001011..CT_INP10 input is selected
+ *  0b0001100..Reserved
+ *  0b0001101..CT_INP12 input is selected
+ *  0b0001110..CT_INP13 input is selected
+ *  0b0001111..CT_INP14 input is selected
+ *  0b0010000..CT_INP15 input is selected
+ *  0b0010001..CT_INP16 input is selected
+ *  0b0010010..CT_INP17 input is selected
+ *  0b0010011..CT_INP18 input is selected
+ *  0b0010100..CT_INP19 input is selected
+ *  0b0010101..Reserved
+ *  0b0010110..AOI0_OUT0 input is selected
+ *  0b0010111..AOI0_OUT1 input is selected
+ *  0b0011000..AOI0_OUT2 input is selected
+ *  0b0011001..AOI0_OUT3 input is selected
+ *  0b0011010..ADC0_tcomp[0]
+ *  0b0011011..ADC0_tcomp[1]
+ *  0b0011100..ADC0_tcomp[2]
+ *  0b0011101..ADC0_tcomp[3] input is selected
+ *  0b0011110..CMP0_OUT is selected
+ *  0b0011111..CMP1_OUT is selected
+ *  0b0100000..CMP2_OUT is selected
+ *  0b0100001..CTimer0_MAT1 input is selected
+ *  0b0100010..CTimer0_MAT2 input is selected
+ *  0b0100011..CTimer0_MAT3 input is selected
+ *  0b0100100..CTimer1_MAT1 input is selected
+ *  0b0100101..CTimer1_MAT2 input is selected
+ *  0b0100110..CTimer1_MAT3 input is selected
+ *  0b0100111..QDC0_CMP_FLAG0 is selected
+ *  0b0101000..QDC0_CMP_FLAG1 input is selected
+ *  0b0101001..QDC0_CMP_FLAG2 input is selected
+ *  0b0101010..QDC0_CMP_FLAG3 input is selected
+ *  0b0101011..QDC0_POS_MATCH0 input is selected
+ *  0b0101100..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0101101..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0101110..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0101111..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0110000..LPI2C0 Master End of Packet input is selected
+ *  0b0110001..LPI2C0 Slave End of Packet input is selected
+ *  0b0110010..LPI2C1 Master End of Packet input is selected
+ *  0b0110011..LPI2C1 Slave End of Packet input is selected
+ *  0b0110100..LPSPI0 End of Frame input is selected
+ *  0b0110101..LPSPI0 Received Data Word input is selected
+ *  0b0110110..LPSPI1 End of Frame input is selected
+ *  0b0110111..LPSPI1 Received Data Word input is selected
+ *  0b0111000..LPUART0 Received Data Word input is selected
+ *  0b0111001..LPUART0 Transmitted Data Word input is selected
+ *  0b0111010..LPUART0 Receive Line Idle input is selected
+ *  0b0111011..LPUART1 Received Data Word input is selected
+ *  0b0111100..LPUART1 Transmitted Data Word input is selected
+ *  0b0111101..LPUART1 Receive Line Idle input is selected
+ *  0b0111110..LPUART2 Received Data Word input is selected
+ *  0b0111111..LPUART2 Transmitted Data Word input is selected
+ *  0b1000000..LPUART2 Receive Line Idle input is selected
+ *  0b1000001..LPUART3 Received Data Word input is selected
+ *  0b1000010..LPUART3 Transmitted Data Word input is selected
+ *  0b1000011..LPUART3 Receive Line Idle input is selected
+ *  0b1000100..Reserved
+ *  0b1000101..Reserved
+ *  0b1000110..Reserved
+ *  0b1000111..AOI1_OUT0 input is selected
+ *  0b1001000..AOI1_OUT1 input is selected
+ *  0b1001001..AOI1_OUT2 input is selected
+ *  0b1001010..AOI1_OUT3 input is selected
+ *  0b1001011..ADC1_tcomp[0] input is selected
+ *  0b1001100..ADC1_tcomp[1] input is selected
+ *  0b1001101..ADC1_tcomp[2] input is selected
+ *  0b1001110..ADC1_tcomp[3] input is selected
+ *  0b1001111..Reserved
+ *  0b1010000..Reserved
+ *  0b1010001..Reserved
+ *  0b1010010..Reserved
+ *  0b1010011..Reserved
+ *  0b1010100..Reserved
+ *  0b1010101..QDC1_CMP_FLAG0 input is selected
+ *  0b1010110..QDC1_CMP_FLAG1 input is selected
+ *  0b1010111..QDC1_CMP_FLAG2 input is selected
+ *  0b1011000..QDC1_CMP_FLAG3 input is selected
+ *  0b1011001..QDC1_POS_MATCH0 input is selected
+ *  0b1011010..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b1011011..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b1011100..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b1011101..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b1011110..Reserved
+ *  0b1011111..Reserved
+ *  0b1100000..Reserved
+ *  0b1100001..Reserved
+ *  0b1100010..Reserved
+ *  0b1100011..Reserved
+ *  0b1100100..Reserved
+ *  0b1100101..Reserved
+ *  0b1100110..Reserved
+ *  0b1100111..Reserved
+ *  0b1101000..Reserved
+ *  0b1101001..Reserved
+ *  0b1101010..Reserved
+ *  0b1101011..Reserved
+ *  0b1101100..Reserved
+ *  0b1101101..Reserved
+ *  0b1101110..Reserved
+ *  0b1101111..Reserved
+ *  0b1110000..Reserved
+ */
+#define INPUTMUX_CTIMERC_CTIMER2CAP_INP(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERC_CTIMER2CAP_INP_SHIFT)) & INPUTMUX_CTIMERC_CTIMER2CAP_INP_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_CTIMERC_CTIMER2CAP */
+#define INPUTMUX_CTIMERC_CTIMER2CAP_COUNT        (4U)
+
+/*! @name TIMER2TRIG - Trigger register for TIMER2 inputs */
+/*! @{ */
+
+#define INPUTMUX_TIMER2TRIG_INP_MASK             (0x7FU)
+#define INPUTMUX_TIMER2TRIG_INP_SHIFT            (0U)
+/*! INP - Input number for CTIMER2
+ *  0b0000000..Reserved
+ *  0b0000001..CT_INP0 input is selected
+ *  0b0000010..CT_INP1 input is selected
+ *  0b0000011..CT_INP2 input is selected
+ *  0b0000100..CT_INP3 input is selected
+ *  0b0000101..CT_INP4 input is selected
+ *  0b0000110..CT_INP5 input is selected
+ *  0b0000111..CT_INP6 input is selected
+ *  0b0001000..CT_INP7 input is selected
+ *  0b0001001..CT_INP8 input is selected
+ *  0b0001010..CT_INP9 input is selected
+ *  0b0001011..CT_INP10 input is selected
+ *  0b0001100..Reserved
+ *  0b0001101..CT_INP12 input is selected
+ *  0b0001110..CT_INP13 input is selected
+ *  0b0001111..CT_INP14 input is selected
+ *  0b0010000..CT_INP15 input is selected
+ *  0b0010001..CT_INP16 input is selected
+ *  0b0010010..CT_INP17 input is selected
+ *  0b0010011..CT_INP18 input is selected
+ *  0b0010100..CT_INP19 input is selected
+ *  0b0010101..Reserved
+ *  0b0010110..AOI0_OUT0 input is selected
+ *  0b0010111..AOI0_OUT1 input is selected
+ *  0b0011000..AOI0_OUT2 input is selected
+ *  0b0011001..AOI0_OUT3 input is selected
+ *  0b0011010..ADC0_tcomp[0]
+ *  0b0011011..ADC0_tcomp[1]
+ *  0b0011100..ADC0_tcomp[2]
+ *  0b0011101..ADC0_tcomp[3] input is selected
+ *  0b0011110..CMP0_OUT is selected
+ *  0b0011111..CMP1_OUT is selected
+ *  0b0100000..CMP2_OUT is selected
+ *  0b0100001..CTimer0_MAT1 input is selected
+ *  0b0100010..CTimer0_MAT2 input is selected
+ *  0b0100011..CTimer0_MAT3 input is selected
+ *  0b0100100..CTimer1_MAT1 input is selected
+ *  0b0100101..CTimer1_MAT2 input is selected
+ *  0b0100110..CTimer1_MAT3 input is selected
+ *  0b0100111..QDC0_CMP_FLAG0 is selected
+ *  0b0101000..QDC0_CMP_FLAG1 input is selected
+ *  0b0101001..QDC0_CMP_FLAG2 input is selected
+ *  0b0101010..QDC0_CMP_FLAG3 input is selected
+ *  0b0101011..QDC0_POS_MATCH0 input is selected
+ *  0b0101100..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0101101..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0101110..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0101111..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0110000..LPI2C0 Master End of Packet input is selected
+ *  0b0110001..LPI2C0 Slave End of Packet input is selected
+ *  0b0110010..LPI2C1 Master End of Packet input is selected
+ *  0b0110011..LPI2C1 Slave End of Packet input is selected
+ *  0b0110100..LPSPI0 End of Frame input is selected
+ *  0b0110101..LPSPI0 Received Data Word input is selected
+ *  0b0110110..LPSPI1 End of Frame input is selected
+ *  0b0110111..LPSPI1 Received Data Word input is selected
+ *  0b0111000..LPUART0 Received Data Word input is selected
+ *  0b0111001..LPUART0 Transmitted Data Word input is selected
+ *  0b0111010..LPUART0 Receive Line Idle input is selected
+ *  0b0111011..LPUART1 Received Data Word input is selected
+ *  0b0111100..LPUART1 Transmitted Data Word input is selected
+ *  0b0111101..LPUART1 Receive Line Idle input is selected
+ *  0b0111110..LPUART2 Received Data Word input is selected
+ *  0b0111111..LPUART2 Transmitted Data Word input is selected
+ *  0b1000000..LPUART2 Receive Line Idle input is selected
+ *  0b1000001..LPUART3 Received Data Word input is selected
+ *  0b1000010..LPUART3 Transmitted Data Word input is selected
+ *  0b1000011..LPUART3 Receive Line Idle input is selected
+ *  0b1000100..Reserved
+ *  0b1000101..Reserved
+ *  0b1000110..Reserved
+ *  0b1000111..AOI1_OUT0 input is selected
+ *  0b1001000..AOI1_OUT1 input is selected
+ *  0b1001001..AOI1_OUT2 input is selected
+ *  0b1001010..AOI1_OUT3 input is selected
+ *  0b1001011..ADC1_tcomp[0] input is selected
+ *  0b1001100..ADC1_tcomp[1] input is selected
+ *  0b1001101..ADC1_tcomp[2] input is selected
+ *  0b1001110..ADC1_tcomp[3] input is selected
+ *  0b1001111..Reserved
+ *  0b1010000..Reserved
+ *  0b1010001..Reserved
+ *  0b1010010..Reserved
+ *  0b1010011..Reserved
+ *  0b1010100..Reserved
+ *  0b1010101..QDC1_CMP_FLAG0 input is selected
+ *  0b1010110..QDC1_CMP_FLAG1 input is selected
+ *  0b1010111..QDC1_CMP_FLAG2 input is selected
+ *  0b1011000..QDC1_CMP_FLAG3 input is selected
+ *  0b1011001..QDC1_POS_MATCH0 input is selected
+ *  0b1011010..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b1011011..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b1011100..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b1011101..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b1011110..Reserved
+ *  0b1011111..Reserved
+ *  0b1100000..Reserved
+ *  0b1100001..Reserved
+ *  0b1100010..Reserved
+ *  0b1100011..Reserved
+ *  0b1100100..Reserved
+ *  0b1100101..Reserved
+ *  0b1100110..Reserved
+ *  0b1100111..Reserved
+ *  0b1101000..Reserved
+ *  0b1101001..Reserved
+ *  0b1101010..Reserved
+ *  0b1101011..Reserved
+ *  0b1101100..Reserved
+ *  0b1101101..Reserved
+ *  0b1101110..Reserved
+ *  0b1101111..Reserved
+ *  0b1110000..Reserved
+ */
+#define INPUTMUX_TIMER2TRIG_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2TRIG_INP_SHIFT)) & INPUTMUX_TIMER2TRIG_INP_MASK)
+/*! @} */
+
+/*! @name SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG - SmartDMA Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_INP_MASK (0x7FU)
+#define INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_INP_SHIFT (0U)
+/*! INP - Input number for FlexIO0.
+ *  0b0000000..Reserved
+ *  0b0000001..GPIO P0_16 input is selected
+ *  0b0000010..GPIO P0_17 input is selected
+ *  0b0000011..GPIO P1_8 input is selected
+ *  0b0000100..GPIO P1_9 input is selected
+ *  0b0000101..GPIO P1_10 input is selected
+ *  0b0000110..GPIO P1_11 input is selected
+ *  0b0000111..GPIO P1_12 input is selected
+ *  0b0001000..GPIO P1_13 input is selected
+ *  0b0001001..GPIO P2_0 input is selected
+ *  0b0001010..GPIO P2_1 input is selected
+ *  0b0001011..GPIO P2_2 input is selected
+ *  0b0001100..GPIO P2_3 input is selected
+ *  0b0001101..GPIO P2_6 input is selected
+ *  0b0001110..GPIO P3_8 input is selected
+ *  0b0001111..GPIO P3_9 input is selected
+ *  0b0010000..GPIO P3_10 input is selected
+ *  0b0010001..GPIO P3_11 input is selected
+ *  0b0010010..GPIO P3_12 input is seclected
+ *  0b0010011..GPIO0 Pin Event Trig input is selected
+ *  0b0010100..GPIO1 Pin Event Trig input is selected
+ *  0b0010101..GPIO2 Pin Event Trig input is selected
+ *  0b0010110..GPIO3 Pin Event Trig input is selected
+ *  0b0010111..GPIO4 Pin Event Trig input is selected
+ *  0b0011000..ARM_TXEV input is selected
+ *  0b0011001..AOI0_OUT0 input is selected
+ *  0b0011010..AOI1_OUT1 input is selected
+ *  0b0011011..DMA_IRQ input is selected
+ *  0b0011100..MAU_IRQ input is selected
+ *  0b0011101..WUU_IRQ input is selected
+ *  0b0011110..CTimer0_MAT2 input is selected
+ *  0b0011111..CTimer0_MAT3 input is selected
+ *  0b0100000..CTimer1_MAT2 input is selected
+ *  0b0100001..CTimer1_MAT3 input is selected
+ *  0b0100010..CTimer2_MAT2 input is selected
+ *  0b0100011..CTimer2_MAT3 input is selected
+ *  0b0100100..Reserved
+ *  0b0100101..Reserved
+ *  0b0100110..Reserved
+ *  0b0100111..Reserved
+ *  0b0101000..OSTIMER_IRQ input is selected
+ *  0b0101001..PWM0_IRQ input is selected
+ *  0b0101010..PWM1_IRQ input is selected
+ *  0b0101011..QDC0_IRQ input is selected
+ *  0b0101100..QDC1_IRQ input is selected
+ *  0b0101101..RTC_Alarm_IRQ input is selected
+ *  0b0101110..RTC_1Hz_IRQ input is selected
+ *  0b0101111..uTICK_IRQ input is selected
+ *  0b0110000..WDT_IRQ input is selected
+ *  0b0110001..Wakeup_Timer_IRQ input is selected
+ *  0b0110010..CAN0_IRQ input is selected
+ *  0b0110011..Reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..LPI2C0_IRQ input is selected
+ *  0b0111011..LPI2C1_IRQ input is selected
+ *  0b0111100..LPSPI0_IRQ input is selected
+ *  0b0111101..LPSPI1_IRQ input is selected
+ *  0b0111110..LPUART0_IRQ input is selected
+ *  0b0111111..LPUART1_IRQ input is selected
+ *  0b1000000..LPUART2_IRQ input is selected
+ *  0b1000001..LPUART3_IRQ input is selected
+ *  0b1000010..USB0_SOF input is selected
+ *  0b1000011..Reserved
+ *  0b1000100..ADC0_IRQ input is selected
+ *  0b1000101..ADC1_IRQ input is selected
+ *  0b1000110..ADC2_IRQ input is selected
+ *  0b1000111..ADC3_IRQ input is selected
+ *  0b1001000..CMP0_IRQ input is selected
+ *  0b1001001..CMP1_IRQ input is selected
+ *  0b1001010..CMP2_IRQ input is selected
+ *  0b1001011..CMP0_OUT input is selected
+ *  0b1001100..CMP1_OUT input is selected
+ *  0b1001101..CMP2_OUT input is selected
+ *  0b1001110..DAC0_IRQ input is selected
+ *  0b1001111..SLCD_IRQ input is selected
+ */
+#define INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_INP_SHIFT)) & INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_INP_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG */
+#define INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_COUNT (8U)
+
+/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */
+/*! @{ */
+
+#define INPUTMUX_FREQMEAS_REF_INP_MASK           (0x7FU)
+#define INPUTMUX_FREQMEAS_REF_INP_SHIFT          (0U)
+/*! INP - Clock source number (binary value) for frequency measure function target clock.
+ *  0b0000000..Reserved
+ *  0b0000001..clk_in input is selected
+ *  0b0000010..FRO_OSC_12M input is selected
+ *  0b0000011..fro_hf_div input is selected
+ *  0b0000100..Reserved
+ *  0b0000101..clk_16k[1] input is selected
+ *  0b0000110..SLOW_CLK input is selected
+ *  0b0000111..FREQME_CLK_IN0 input is selected
+ *  0b0001000..FREQME_CLK_IN1 input is selected input is selected
+ *  0b0001001..AOI0_OUT0 input is selected
+ *  0b0001010..AOI0_OUT1
+ *  0b0001011..PWM0_SM0_MUX_TRIG0
+ *  0b0001100..PWM0_SM0_MUX_TRIG1
+ *  0b0001101..PWM0_SM1_MUX_TRIG0
+ *  0b0001110..PWM0_SM1_MUX_TRIG1
+ *  0b0001111..PWM0_SM2_MUX_TRIG0
+ *  0b0010000..PWM0_SM2_MUX_TRIG1
+ *  0b0010001..PWM0_SM3_MUX_TRIG0
+ *  0b0010010..PWM0_SM3_MUX_TRIG1
+ *  0b0010011..Reserved
+ *  0b0010100..Reserved
+ *  0b0010101..Reserved
+ *  0b0010110..Reserved
+ *  0b0010111..Reserved
+ *  0b0011000..Reserved
+ *  0b0011001..Reserved
+ *  0b0011010..Reserved
+ *  0b0011011..Reserved
+ *  0b0011100..Reserved
+ *  0b0011101..Reserved
+ *  0b0011110..Reserved
+ *  0b0011111..Reserved
+ *  0b0100000..AOI1_OUT0 input is selected
+ *  0b0100001..AOI1_OUT1 input is selected
+ *  0b0100010..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b0100011..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b0100100..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b0100101..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b0100110..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b0100111..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b0101000..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b0101001..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FREQMEAS_REF_INP(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_INP_SHIFT)) & INPUTMUX_FREQMEAS_REF_INP_MASK)
+/*! @} */
+
+/*! @name FREQMEAS_TAR - Selection for frequency measurement reference clock */
+/*! @{ */
+
+#define INPUTMUX_FREQMEAS_TAR_INP_MASK           (0x7FU)
+#define INPUTMUX_FREQMEAS_TAR_INP_SHIFT          (0U)
+/*! INP - Clock source number (binary value) for frequency measure function target clock.
+ *  0b0000000..Reserved
+ *  0b0000001..clk_in input is selected
+ *  0b0000010..FRO_OSC_12M input is selected
+ *  0b0000011..fro_hf_div input is selected
+ *  0b0000100..Reserved
+ *  0b0000101..clk_16k[1] input is selected
+ *  0b0000110..SLOW_CLK input is selected
+ *  0b0000111..FREQME_CLK_IN0 input is selected
+ *  0b0001000..FREQME_CLK_IN1 input is selected input is selected
+ *  0b0001001..AOI0_OUT0 input is selected
+ *  0b0001010..AOI0_OUT1
+ *  0b0001011..PWM0_SM0_MUX_TRIG0
+ *  0b0001100..PWM0_SM0_MUX_TRIG1
+ *  0b0001101..PWM0_SM1_MUX_TRIG0
+ *  0b0001110..PWM0_SM1_MUX_TRIG1
+ *  0b0001111..PWM0_SM2_MUX_TRIG0
+ *  0b0010000..PWM0_SM2_MUX_TRIG1
+ *  0b0010001..PWM0_SM3_MUX_TRIG0
+ *  0b0010010..PWM0_SM3_MUX_TRIG1
+ *  0b0010011..Reserved
+ *  0b0010100..Reserved
+ *  0b0010101..Reserved
+ *  0b0010110..Reserved
+ *  0b0010111..Reserved
+ *  0b0011000..Reserved
+ *  0b0011001..Reserved
+ *  0b0011010..Reserved
+ *  0b0011011..Reserved
+ *  0b0011100..Reserved
+ *  0b0011101..Reserved
+ *  0b0011110..Reserved
+ *  0b0011111..Reserved
+ *  0b0100000..AOI1_OUT0 input is selected
+ *  0b0100001..AOI1_OUT1 input is selected
+ *  0b0100010..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b0100011..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b0100100..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b0100101..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b0100110..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b0100111..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b0101000..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b0101001..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FREQMEAS_TAR_INP(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TAR_INP_SHIFT)) & INPUTMUX_FREQMEAS_TAR_INP_MASK)
+/*! @} */
+
+/*! @name AOI1_INPUTM_AOI1_INPUT - AOI1 trigger input connections 0 */
+/*! @{ */
+
+#define INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP_MASK (0x7FU)
+#define INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP_SHIFT (0U)
+/*! INP - AOI0 trigger input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ADC0_tcomp[0] input is selected
+ *  0b0000010..ADC0_tcomp[1] input is selected
+ *  0b0000011..ADC0_tcomp[2] input is selected
+ *  0b0000100..ADC0_tcomp[3] input is selected
+ *  0b0000101..CMP0_OUT input is selected
+ *  0b0000110..CMP1_OUT input is selected
+ *  0b0000111..CMP2_OUT input is selected
+ *  0b0001000..CTimer0_MAT0 input is selected
+ *  0b0001001..CTimer0_MAT1 input is selected
+ *  0b0001010..CTimer0_MAT2 input is selected
+ *  0b0001011..CTimer0_MAT3 input is selected
+ *  0b0001100..CTimer1_MAT0
+ *  0b0001101..CTimer1_MAT1 input is selected
+ *  0b0001110..CTimer1_MAT2 input is selected
+ *  0b0001111..CTimer1_MAT3 input is selected
+ *  0b0010000..CTimer2_MAT0 input is selected
+ *  0b0010001..CTimer2_MAT1 input is selected
+ *  0b0010010..CTimer2_MAT2 input is selected
+ *  0b0010011..CTimer2_MAT3 input is selected
+ *  0b0010100..LPTMR0 input is selected
+ *  0b0010101..Reserved
+ *  0b0010110..QDC0_CMP_FLAG0 input is selected
+ *  0b0010111..QDC0_CMP_FLAG1 input is selected
+ *  0b0011000..QDC0_CMP_FLAG2 input is selected
+ *  0b0011001..QDC0_CMP_FLAG3 input is selected
+ *  0b0011010..QDC0_POS_MATCH input is selected
+ *  0b0011011..PWM0_SM0_MUX_TRIG0 0 input is selected
+ *  0b0011100..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0011101..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0011110..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0011111..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0100000..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0100001..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0100010..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0100011..TRIG_IN0 input is selected
+ *  0b0100100..TRIG_IN1 input is selected
+ *  0b0100101..TRIG_IN2 input is selected
+ *  0b0100110..TRIG_IN3 input is selected
+ *  0b0100111..TRIG_IN4 input is selected
+ *  0b0101000..TRIG_IN5 input is selected
+ *  0b0101001..TRIG_IN6 input is selected
+ *  0b0101010..TRIG_IN7 input is selected
+ *  0b0101011..TRIG_IN8 input is selected
+ *  0b0101100..TRIG_IN9 input is selected
+ *  0b0101101..TRIG_IN10 input is selected
+ *  0b0101110..TRIG_IN11 input is selected
+ *  0b0101111..GPIO0 Pin Event Trig 0 input is selected
+ *  0b0110000..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0110001..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0110010..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0110011..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0110100..ADC1_tcomp[0] input is selected
+ *  0b0110101..ADC1_tcomp[1] input is selected
+ *  0b0110110..ADC1_tcomp[2] input is selected
+ *  0b0110111..ADC1_tcomp[3] input is selected
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..Reserved
+ *  0b0111111..Reserved
+ *  0b1000000..Reserved
+ *  0b1000001..Reserved
+ *  0b1000010..Reserved
+ *  0b1000011..Reserved
+ *  0b1000100..QDC1_CMP_FLAG0 input is selected
+ *  0b1000101..QDC1_CMP_FLAG1 input is selected
+ *  0b1000110..QDC1_CMP_FLAG2 input is selected
+ *  0b1000111..QDC1_CMP_FLAG3 input is selected
+ *  0b1001000..QDC1_POS_MATCH0 input is selected
+ *  0b1001001..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b1001010..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b1001011..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b1001100..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b1001101..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b1001110..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b1001111..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1010000..PWM1_SM3_MUX_TRIG1 input is selected
+ *  0b1010001..PWM0_SM0_A_Output
+ *  0b1010010..PWM0_SM0_B_Output
+ *  0b1010011..PWM0_SM1_A_Output
+ *  0b1010100..PWM0_SM1_B_Output
+ *  0b1010101..PWM0_SM2_A_Output
+ *  0b1010110..PWM0_SM2_B_Output
+ *  0b1010111..PWM0_SM3_A_Output
+ *  0b1011000..PWM0_SM3_B_Output
+ *  0b1011001..Reserved
+ *  0b1011010..Reserved
+ *  0b1011011..Reserved
+ *  0b1011100..Reserved
+ *  0b1011101..Reserved
+ *  0b1011110..Reserved
+ *  0b1011111..Reserved
+ *  0b1100000..Reserved
+ */
+#define INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP_SHIFT)) & INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_AOI1_INPUTM_AOI1_INPUT */
+#define INPUTMUX_AOI1_INPUTM_AOI1_INPUT_COUNT    (16U)
+
+/*! @name CMP0_TRIG - CMP0 input connections */
+/*! @{ */
+
+#define INPUTMUX_CMP0_TRIG_TRIGIN_MASK           (0x3FU)
+#define INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT          (0U)
+/*! TRIGIN - CMP0 input trigger
+ *  0b000000..Reserved
+ *  0b000001..Reserved
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP1_OUT input is selected
+ *  0b000111..CMP2_OUT input is selected
+ *  0b001000..CTimer0_MAT0 input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer1_MAT0
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer2_MAT0 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..LPTMR0 input is selected
+ *  0b001111..Reserved
+ *  0b010000..QDC0_POS_MATCH0
+ *  0b010001..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b010010..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b010011..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b010100..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b010101..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b010110..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b010111..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b011000..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b011001..GPIO0 Pin Event Trig 0 input is selected
+ *  0b011010..GPIO1 Pin Event Trig 0 input is selected
+ *  0b011011..GPIO2 Pin Event Trig 0 input is selected
+ *  0b011100..GPIO3 Pin Event Trig 0 input is selected
+ *  0b011101..GPIO4 Pin Event Trig 0 input is selected
+ *  0b011110..WUU input is selected
+ *  0b011111..AOI1_OUT0 input is selected
+ *  0b100000..AOI1_OUT1 input is selected
+ *  0b100001..AOI1_OUT2 input is selected
+ *  0b100010..AOI1_OUT3 input is selected
+ *  0b100011..Reserved
+ *  0b100100..Reserved
+ *  0b100101..Reserved
+ *  0b100110..Reserved
+ *  0b100111..Reserved
+ *  0b101000..Reserved
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..QDC1_POS_MATCH0 input is selected
+ *  0b110000..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b110001..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b110010..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b110011..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b110100..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b110101..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b110110..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b110111..PWM1_SM2_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_CMP0_TRIG_TRIGIN(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP0_TRIG_TRIGIN_MASK)
+/*! @} */
+
+/*! @name ADC0_TRIGM_ADC0_TRIG - ADC Trigger input connections */
+/*! @{ */
+
+#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK (0x3FU)
+#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT (0U)
+/*! TRIGIN - ADC0 trigger inputs
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT0 input is selected
+ *  0b001010..CTimer0_MAT1 input is selected
+ *  0b001011..CTimer1_MAT0 input is selected
+ *  0b001100..CTimer1_MAT1 input is selected
+ *  0b001101..CTimer2_MAT0 input is selected
+ *  0b001110..CTimer2_MAT1 input is selected
+ *  0b001111..LPTMR0 input is selected
+ *  0b010000..Reserved
+ *  0b010001..QDC0_POS_MATCH0 input is selected
+ *  0b010010..PWM0_SM0_OUT_TRIG0 input is selected
+ *  0b010011..PWM0_SM0_OUT_TRIG1 input is selected
+ *  0b010100..PWM0_SM1_OUT_TRIG0 input is selected
+ *  0b010101..PWM0_SM1_OUT_TRIG1 input is selected
+ *  0b010110..PWM0_SM2_OUT_TRIG0 input is selected
+ *  0b010111..PWM0_SM2_OUT_TRIG1 input is selected
+ *  0b011000..PWM0_SM3_OUT_TRIG0 input is selected
+ *  0b011001..PWM0_SM3_OUT_TRIG1 input is selected
+ *  0b011010..GPIO0 Pin Event Trig 0 input is selected
+ *  0b011011..GPIO1 Pin Event Trig 0 input is selected
+ *  0b011100..GPIO2 Pin Event Trig 0 input is selected
+ *  0b011101..GPIO3 Pin Event Trig 0 input is selected
+ *  0b011110..GPIO4 Pin Event Trig 0 input is selected
+ *  0b011111..WUU
+ *  0b100000..Reserved
+ *  0b100001..AOI1_OUT0 input is selected
+ *  0b100010..AOI1_OUT1 input is selected
+ *  0b100011..AOI1_OUT2 input is selected
+ *  0b100100..AOI1_OUT3 input is selected
+ *  0b100101..ADC1_tcomp[0] input is selected
+ *  0b100110..ADC1_tcomp[1] input is selected
+ *  0b100111..ADC1_tcomp[2] input is selected
+ *  0b101000..ADC1_tcomp[3] input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_POS_MATCH0 input is selected
+ *  0b110010..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b110011..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b110100..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b110101..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b110110..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b110111..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b111000..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b111001..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_ADC0_TRIGM_ADC0_TRIG */
+#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_COUNT      (4U)
+
+/*! @name ADC1_TRIGM_ADC1_TRIG - ADC Trigger input connections */
+/*! @{ */
+
+#define INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN_MASK (0x3FU)
+#define INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN_SHIFT (0U)
+/*! TRIGIN - ADC0 trigger inputs
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT0 input is selected
+ *  0b001010..CTimer0_MAT1 input is selected
+ *  0b001011..CTimer1_MAT0 input is selected
+ *  0b001100..CTimer1_MAT1 input is selected
+ *  0b001101..CTimer2_MAT0 input is selected
+ *  0b001110..CTimer2_MAT1 input is selected
+ *  0b001111..LPTMR0 input is selected
+ *  0b010000..Reserved
+ *  0b010001..QDC0_POS_MATCH0 input is selected
+ *  0b010010..PWM0_SM0_OUT_TRIG0 input is selected
+ *  0b010011..PWM0_SM0_OUT_TRIG1 input is selected
+ *  0b010100..PWM0_SM1_OUT_TRIG0 input is selected
+ *  0b010101..PWM0_SM1_OUT_TRIG1 input is selected
+ *  0b010110..PWM0_SM2_OUT_TRIG0 input is selected
+ *  0b010111..PWM0_SM2_OUT_TRIG1 input is selected
+ *  0b011000..PWM0_SM3_OUT_TRIG0 input is selected
+ *  0b011001..PWM0_SM3_OUT_TRIG1 input is selected
+ *  0b011010..GPIO0 Pin Event Trig 0 input is selected
+ *  0b011011..GPIO1 Pin Event Trig 0 input is selected
+ *  0b011100..GPIO2 Pin Event Trig 0 input is selected
+ *  0b011101..GPIO3 Pin Event Trig 0 input is selected
+ *  0b011110..GPIO4 Pin Event Trig 0 input is selected
+ *  0b011111..WUU
+ *  0b100000..Reserved
+ *  0b100001..AOI1_OUT0 input is selected
+ *  0b100010..AOI1_OUT1 input is selected
+ *  0b100011..AOI1_OUT2 input is selected
+ *  0b100100..AOI1_OUT3 input is selected
+ *  0b100101..ADC0_tcomp[0] input is selected
+ *  0b100110..ADC0_tcomp[1] input is selected
+ *  0b100111..ADC0_tcomp[2] input is selected
+ *  0b101000..ADC0_tcomp[3] input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_POS_MATCH0 input is selected
+ *  0b110010..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b110011..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b110100..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b110101..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b110110..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b110111..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b111000..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b111001..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_ADC1_TRIGM_ADC1_TRIG */
+#define INPUTMUX_ADC1_TRIGM_ADC1_TRIG_COUNT      (4U)
+
+/*! @name QDC0_TRIG - QDC0 Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_QDC0_TRIG_INP_MASK              (0x7FU)
+#define INPUTMUX_QDC0_TRIG_INP_SHIFT             (0U)
+/*! INP - QDC0 input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ARM_TXEV input is selected
+ *  0b0000010..AOI0_OUT0 input is selected
+ *  0b0000011..AOI0_OUT1 input is selected
+ *  0b0000100..AOI0_OUT2 input is selected
+ *  0b0000101..AOI0_OUT3 input is selected
+ *  0b0000110..CMP0_OUT input is selected
+ *  0b0000111..CMP1_OUT input is selected
+ *  0b0001000..CMP2_OUT input is selected
+ *  0b0001001..CTimer0_MAT2 input is selected
+ *  0b0001010..CTimer0_MAT3
+ *  0b0001011..CTimer1_MAT2 input is selected
+ *  0b0001100..CTimer1_MAT3 input is selected
+ *  0b0001101..CTimer2_MAT2 input is selected
+ *  0b0001110..CTimer2_MAT3 input is selected
+ *  0b0001111..Reserved
+ *  0b0010000..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0010001..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0010010..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0010011..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0010100..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0010101..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0010110..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0010111..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0011000..TRIG_IN0 input is selected
+ *  0b0011001..TRIG_IN1 input is selected
+ *  0b0011010..TRIG_IN2 input is selected
+ *  0b0011011..TRIG_IN3 input is selected
+ *  0b0011100..TRIG_IN4 input is selected
+ *  0b0011101..TRIG_IN5 input is selected
+ *  0b0011110..TRIG_IN6 input is selected
+ *  0b0011111..TRIG_IN7 input is selected
+ *  0b0100000..TRIG_IN8 input is selected
+ *  0b0100001..TRIG_IN9 input is selected
+ *  0b0100010..TRIG_IN10 input is selected
+ *  0b0100011..TRIG_IN11 input is selected
+ *  0b0100100..GPIO0 Pin Event Trig 0 is selected
+ *  0b0100101..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0100110..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0100111..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0101000..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0101001..AOI1_OUT0 input is selected
+ *  0b0101010..AOI1_OUT1 input is selected
+ *  0b0101011..AOI1_OUT2 input is selected
+ *  0b0101100..AOI1_OUT3 input is selected
+ *  0b0101101..Reserved
+ *  0b0101110..Reserved
+ *  0b0101111..Reserved
+ *  0b0110000..Reserved
+ *  0b0110001..Reserved
+ *  0b0110010..Reserved
+ *  0b0110011..Reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..PWM1_SM0_OUT_TRIG0 input is selected
+ *  0b0111111..PWM1_SM0_OUT_TRIG1 input is selected
+ *  0b1000000..PWM1_SM1_OUT_TRIG0 input is selected
+ *  0b1000001..PWM1_SM1_OUT_TRIG1 input is selected
+ *  0b1000010..PWM1_SM2_OUT_TRIG0 input is selected
+ *  0b1000011..PWM1_SM2_OUT_TRIG1 input is selected
+ *  0b1000100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1000101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_QDC0_TRIG_INP(x)                (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_TRIG_INP_SHIFT)) & INPUTMUX_QDC0_TRIG_INP_MASK)
+/*! @} */
+
+/*! @name QDC0_HOME - QDC0 Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_QDC0_HOME_INP_MASK              (0x7FU)
+#define INPUTMUX_QDC0_HOME_INP_SHIFT             (0U)
+/*! INP - QDC0 input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ARM_TXEV input is selected
+ *  0b0000010..AOI0_OUT0 input is selected
+ *  0b0000011..AOI0_OUT1 input is selected
+ *  0b0000100..AOI0_OUT2 input is selected
+ *  0b0000101..AOI0_OUT3 input is selected
+ *  0b0000110..CMP0_OUT input is selected
+ *  0b0000111..CMP1_OUT input is selected
+ *  0b0001000..CMP2_OUT input is selected
+ *  0b0001001..CTimer0_MAT2 input is selected
+ *  0b0001010..CTimer0_MAT3
+ *  0b0001011..CTimer1_MAT2 input is selected
+ *  0b0001100..CTimer1_MAT3 input is selected
+ *  0b0001101..CTimer2_MAT2 input is selected
+ *  0b0001110..CTimer2_MAT3 input is selected
+ *  0b0001111..Reserved
+ *  0b0010000..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0010001..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0010010..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0010011..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0010100..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0010101..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0010110..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0010111..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0011000..TRIG_IN0 input is selected
+ *  0b0011001..TRIG_IN1 input is selected
+ *  0b0011010..TRIG_IN2 input is selected
+ *  0b0011011..TRIG_IN3 input is selected
+ *  0b0011100..TRIG_IN4 input is selected
+ *  0b0011101..TRIG_IN5 input is selected
+ *  0b0011110..TRIG_IN6 input is selected
+ *  0b0011111..TRIG_IN7 input is selected
+ *  0b0100000..TRIG_IN8 input is selected
+ *  0b0100001..TRIG_IN9 input is selected
+ *  0b0100010..TRIG_IN10 input is selected
+ *  0b0100011..TRIG_IN11 input is selected
+ *  0b0100100..GPIO0 Pin Event Trig 0 is selected
+ *  0b0100101..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0100110..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0100111..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0101000..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0101001..AOI1_OUT0 input is selected
+ *  0b0101010..AOI1_OUT1 input is selected
+ *  0b0101011..AOI1_OUT2 input is selected
+ *  0b0101100..AOI1_OUT3 input is selected
+ *  0b0101101..Reserved
+ *  0b0101110..Reserved
+ *  0b0101111..Reserved
+ *  0b0110000..Reserved
+ *  0b0110001..Reserved
+ *  0b0110010..Reserved
+ *  0b0110011..Reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..PWM1_SM0_OUT_TRIG0 input is selected
+ *  0b0111111..PWM1_SM0_OUT_TRIG1 input is selected
+ *  0b1000000..PWM1_SM1_OUT_TRIG0 input is selected
+ *  0b1000001..PWM1_SM1_OUT_TRIG1 input is selected
+ *  0b1000010..PWM1_SM2_OUT_TRIG0 input is selected
+ *  0b1000011..PWM1_SM2_OUT_TRIG1 input is selected
+ *  0b1000100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1000101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_QDC0_HOME_INP(x)                (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_HOME_INP_SHIFT)) & INPUTMUX_QDC0_HOME_INP_MASK)
+/*! @} */
+
+/*! @name QDC0_INDEX - QDC0 Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_QDC0_INDEX_INP_MASK             (0x7FU)
+#define INPUTMUX_QDC0_INDEX_INP_SHIFT            (0U)
+/*! INP - QDC0 input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ARM_TXEV input is selected
+ *  0b0000010..AOI0_OUT0 input is selected
+ *  0b0000011..AOI0_OUT1 input is selected
+ *  0b0000100..AOI0_OUT2 input is selected
+ *  0b0000101..AOI0_OUT3 input is selected
+ *  0b0000110..CMP0_OUT input is selected
+ *  0b0000111..CMP1_OUT input is selected
+ *  0b0001000..CMP2_OUT input is selected
+ *  0b0001001..CTimer0_MAT2 input is selected
+ *  0b0001010..CTimer0_MAT3
+ *  0b0001011..CTimer1_MAT2 input is selected
+ *  0b0001100..CTimer1_MAT3 input is selected
+ *  0b0001101..CTimer2_MAT2 input is selected
+ *  0b0001110..CTimer2_MAT3 input is selected
+ *  0b0001111..Reserved
+ *  0b0010000..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0010001..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0010010..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0010011..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0010100..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0010101..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0010110..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0010111..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0011000..TRIG_IN0 input is selected
+ *  0b0011001..TRIG_IN1 input is selected
+ *  0b0011010..TRIG_IN2 input is selected
+ *  0b0011011..TRIG_IN3 input is selected
+ *  0b0011100..TRIG_IN4 input is selected
+ *  0b0011101..TRIG_IN5 input is selected
+ *  0b0011110..TRIG_IN6 input is selected
+ *  0b0011111..TRIG_IN7 input is selected
+ *  0b0100000..TRIG_IN8 input is selected
+ *  0b0100001..TRIG_IN9 input is selected
+ *  0b0100010..TRIG_IN10 input is selected
+ *  0b0100011..TRIG_IN11 input is selected
+ *  0b0100100..GPIO0 Pin Event Trig 0 is selected
+ *  0b0100101..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0100110..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0100111..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0101000..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0101001..AOI1_OUT0 input is selected
+ *  0b0101010..AOI1_OUT1 input is selected
+ *  0b0101011..AOI1_OUT2 input is selected
+ *  0b0101100..AOI1_OUT3 input is selected
+ *  0b0101101..Reserved
+ *  0b0101110..Reserved
+ *  0b0101111..Reserved
+ *  0b0110000..Reserved
+ *  0b0110001..Reserved
+ *  0b0110010..Reserved
+ *  0b0110011..Reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..PWM1_SM0_OUT_TRIG0 input is selected
+ *  0b0111111..PWM1_SM0_OUT_TRIG1 input is selected
+ *  0b1000000..PWM1_SM1_OUT_TRIG0 input is selected
+ *  0b1000001..PWM1_SM1_OUT_TRIG1 input is selected
+ *  0b1000010..PWM1_SM2_OUT_TRIG0 input is selected
+ *  0b1000011..PWM1_SM2_OUT_TRIG1 input is selected
+ *  0b1000100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1000101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_QDC0_INDEX_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_INDEX_INP_SHIFT)) & INPUTMUX_QDC0_INDEX_INP_MASK)
+/*! @} */
+
+/*! @name QDC0_PHASEB - QDC0 Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_QDC0_PHASEB_INP_MASK            (0x7FU)
+#define INPUTMUX_QDC0_PHASEB_INP_SHIFT           (0U)
+/*! INP - QDC0 input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ARM_TXEV input is selected
+ *  0b0000010..AOI0_OUT0 input is selected
+ *  0b0000011..AOI0_OUT1 input is selected
+ *  0b0000100..AOI0_OUT2 input is selected
+ *  0b0000101..AOI0_OUT3 input is selected
+ *  0b0000110..CMP0_OUT input is selected
+ *  0b0000111..CMP1_OUT input is selected
+ *  0b0001000..CMP2_OUT input is selected
+ *  0b0001001..CTimer0_MAT2 input is selected
+ *  0b0001010..CTimer0_MAT3
+ *  0b0001011..CTimer1_MAT2 input is selected
+ *  0b0001100..CTimer1_MAT3 input is selected
+ *  0b0001101..CTimer2_MAT2 input is selected
+ *  0b0001110..CTimer2_MAT3 input is selected
+ *  0b0001111..Reserved
+ *  0b0010000..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0010001..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0010010..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0010011..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0010100..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0010101..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0010110..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0010111..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0011000..TRIG_IN0 input is selected
+ *  0b0011001..TRIG_IN1 input is selected
+ *  0b0011010..TRIG_IN2 input is selected
+ *  0b0011011..TRIG_IN3 input is selected
+ *  0b0011100..TRIG_IN4 input is selected
+ *  0b0011101..TRIG_IN5 input is selected
+ *  0b0011110..TRIG_IN6 input is selected
+ *  0b0011111..TRIG_IN7 input is selected
+ *  0b0100000..TRIG_IN8 input is selected
+ *  0b0100001..TRIG_IN9 input is selected
+ *  0b0100010..TRIG_IN10 input is selected
+ *  0b0100011..TRIG_IN11 input is selected
+ *  0b0100100..GPIO0 Pin Event Trig 0 is selected
+ *  0b0100101..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0100110..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0100111..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0101000..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0101001..AOI1_OUT0 input is selected
+ *  0b0101010..AOI1_OUT1 input is selected
+ *  0b0101011..AOI1_OUT2 input is selected
+ *  0b0101100..AOI1_OUT3 input is selected
+ *  0b0101101..Reserved
+ *  0b0101110..Reserved
+ *  0b0101111..Reserved
+ *  0b0110000..Reserved
+ *  0b0110001..Reserved
+ *  0b0110010..Reserved
+ *  0b0110011..Reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..PWM1_SM0_OUT_TRIG0 input is selected
+ *  0b0111111..PWM1_SM0_OUT_TRIG1 input is selected
+ *  0b1000000..PWM1_SM1_OUT_TRIG0 input is selected
+ *  0b1000001..PWM1_SM1_OUT_TRIG1 input is selected
+ *  0b1000010..PWM1_SM2_OUT_TRIG0 input is selected
+ *  0b1000011..PWM1_SM2_OUT_TRIG1 input is selected
+ *  0b1000100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1000101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_QDC0_PHASEB_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_PHASEB_INP_SHIFT)) & INPUTMUX_QDC0_PHASEB_INP_MASK)
+/*! @} */
+
+/*! @name QDC0_PHASEA - QDC0 Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_QDC0_PHASEA_INP_MASK            (0x7FU)
+#define INPUTMUX_QDC0_PHASEA_INP_SHIFT           (0U)
+/*! INP - QDC0 input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ARM_TXEV input is selected
+ *  0b0000010..AOI0_OUT0 input is selected
+ *  0b0000011..AOI0_OUT1 input is selected
+ *  0b0000100..AOI0_OUT2 input is selected
+ *  0b0000101..AOI0_OUT3 input is selected
+ *  0b0000110..CMP0_OUT input is selected
+ *  0b0000111..CMP1_OUT input is selected
+ *  0b0001000..CMP2_OUT input is selected
+ *  0b0001001..CTimer0_MAT2 input is selected
+ *  0b0001010..CTimer0_MAT3
+ *  0b0001011..CTimer1_MAT2 input is selected
+ *  0b0001100..CTimer1_MAT3 input is selected
+ *  0b0001101..CTimer2_MAT2 input is selected
+ *  0b0001110..CTimer2_MAT3 input is selected
+ *  0b0001111..Reserved
+ *  0b0010000..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0010001..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0010010..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0010011..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0010100..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0010101..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0010110..Reserved
+ *  0b0010111..Reserved
+ *  0b0011000..TRIG_IN0 input is selected
+ *  0b0011001..TRIG_IN1 input is selected
+ *  0b0011010..TRIG_IN2 input is selected
+ *  0b0011011..TRIG_IN3 input is selected
+ *  0b0011100..TRIG_IN4 input is selected
+ *  0b0011101..TRIG_IN5 input is selected
+ *  0b0011110..TRIG_IN6 input is selected
+ *  0b0011111..TRIG_IN7 input is selected
+ *  0b0100000..TRIG_IN8 input is selected
+ *  0b0100001..TRIG_IN9 input is selected
+ *  0b0100010..TRIG_IN10 input is selected
+ *  0b0100011..TRIG_IN11 input is selected
+ *  0b0100100..GPIO0 Pin Event Trig 0 is selected
+ *  0b0100101..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0100110..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0100111..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0101000..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0101001..AOI1_OUT0 input is selected
+ *  0b0101010..AOI1_OUT1 input is selected
+ *  0b0101011..AOI1_OUT2 input is selected
+ *  0b0101100..AOI1_OUT3 input is selected
+ *  0b0101101..Reserved
+ *  0b0101110..Reserved
+ *  0b0101111..Reserved
+ *  0b0110000..Reserved
+ *  0b0110001..Reserved
+ *  0b0110010..Reserved
+ *  0b0110011..Reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..PWM1_SM0_OUT_TRIG0 input is selected
+ *  0b0111111..PWM1_SM0_OUT_TRIG1 input is selected
+ *  0b1000000..PWM1_SM1_OUT_TRIG0 input is selected
+ *  0b1000001..PWM1_SM1_OUT_TRIG1 input is selected
+ *  0b1000010..PWM1_SM2_OUT_TRIG0 input is selected
+ *  0b1000011..PWM1_SM2_OUT_TRIG1 input is selected
+ *  0b1000100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1000101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_QDC0_PHASEA_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_PHASEA_INP_SHIFT)) & INPUTMUX_QDC0_PHASEA_INP_MASK)
+/*! @} */
+
+/*! @name QDC0_ICAP1 - QDC0 Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_QDC0_ICAP1_INP_MASK             (0x7FU)
+#define INPUTMUX_QDC0_ICAP1_INP_SHIFT            (0U)
+/*! INP - QDC0 input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ARM_TXEV input is selected
+ *  0b0000010..AOI0_OUT0 input is selected
+ *  0b0000011..AOI0_OUT1 input is selected
+ *  0b0000100..AOI0_OUT2 input is selected
+ *  0b0000101..AOI0_OUT3 input is selected
+ *  0b0000110..CMP0_OUT input is selected
+ *  0b0000111..CMP1_OUT input is selected
+ *  0b0001000..CMP2_OUT input is selected
+ *  0b0001001..CTimer0_MAT2 input is selected
+ *  0b0001010..CTimer0_MAT3
+ *  0b0001011..CTimer1_MAT2 input is selected
+ *  0b0001100..CTimer1_MAT3 input is selected
+ *  0b0001101..CTimer2_MAT2 input is selected
+ *  0b0001110..CTimer2_MAT3 input is selected
+ *  0b0001111..Reserved
+ *  0b0010000..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0010001..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0010010..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0010011..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0010100..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0010101..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0010110..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0010111..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0011000..TRIG_IN0 input is selected
+ *  0b0011001..TRIG_IN1 input is selected
+ *  0b0011010..TRIG_IN2 input is selected
+ *  0b0011011..TRIG_IN3 input is selected
+ *  0b0011100..TRIG_IN4 input is selected
+ *  0b0011101..TRIG_IN5 input is selected
+ *  0b0011110..TRIG_IN6 input is selected
+ *  0b0011111..TRIG_IN7 input is selected
+ *  0b0100000..TRIG_IN8 input is selected
+ *  0b0100001..TRIG_IN9 input is selected
+ *  0b0100010..TRIG_IN10 input is selected
+ *  0b0100011..TRIG_IN11 input is selected
+ *  0b0100100..GPIO0 Pin Event Trig 0 is selected
+ *  0b0100101..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0100110..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0100111..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0101000..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0101001..AOI1_OUT0 input is selected
+ *  0b0101010..AOI1_OUT1 input is selected
+ *  0b0101011..AOI1_OUT2 input is selected
+ *  0b0101100..AOI1_OUT3 input is selected
+ *  0b0101101..Reserved
+ *  0b0101110..Reserved
+ *  0b0101111..Reserved
+ *  0b0110000..Reserved
+ *  0b0110001..Reserved
+ *  0b0110010..Reserved
+ *  0b0110011..Reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..PWM1_SM0_OUT_TRIG0 input is selected
+ *  0b0111111..PWM1_SM0_OUT_TRIG1 input is selected
+ *  0b1000000..PWM1_SM1_OUT_TRIG0 input is selected
+ *  0b1000001..PWM1_SM1_OUT_TRIG1 input is selected
+ *  0b1000010..PWM1_SM2_OUT_TRIG0 input is selected
+ *  0b1000011..PWM1_SM2_OUT_TRIG1 input is selected
+ *  0b1000100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1000101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_QDC0_ICAP1_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_ICAP1_INP_SHIFT)) & INPUTMUX_QDC0_ICAP1_INP_MASK)
+/*! @} */
+
+/*! @name QDC0_ICAP2 - QDC0 Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_QDC0_ICAP2_INP_MASK             (0x7FU)
+#define INPUTMUX_QDC0_ICAP2_INP_SHIFT            (0U)
+/*! INP - QDC0 input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ARM_TXEV input is selected
+ *  0b0000010..AOI0_OUT0 input is selected
+ *  0b0000011..AOI0_OUT1 input is selected
+ *  0b0000100..AOI0_OUT2 input is selected
+ *  0b0000101..AOI0_OUT3 input is selected
+ *  0b0000110..CMP0_OUT input is selected
+ *  0b0000111..CMP1_OUT input is selected
+ *  0b0001000..CMP2_OUT input is selected
+ *  0b0001001..CTimer0_MAT2 input is selected
+ *  0b0001010..CTimer0_MAT3
+ *  0b0001011..CTimer1_MAT2 input is selected
+ *  0b0001100..CTimer1_MAT3 input is selected
+ *  0b0001101..CTimer2_MAT2 input is selected
+ *  0b0001110..CTimer2_MAT3 input is selected
+ *  0b0001111..Reserved
+ *  0b0010000..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0010001..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0010010..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0010011..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0010100..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0010101..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0010110..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0010111..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0011000..TRIG_IN0 input is selected
+ *  0b0011001..TRIG_IN1 input is selected
+ *  0b0011010..TRIG_IN2 input is selected
+ *  0b0011011..TRIG_IN3 input is selected
+ *  0b0011100..TRIG_IN4 input is selected
+ *  0b0011101..TRIG_IN5 input is selected
+ *  0b0011110..TRIG_IN6 input is selected
+ *  0b0011111..TRIG_IN7 input is selected
+ *  0b0100000..TRIG_IN8 input is selected
+ *  0b0100001..TRIG_IN9 input is selected
+ *  0b0100010..TRIG_IN10 input is selected
+ *  0b0100011..TRIG_IN11 input is selected
+ *  0b0100100..GPIO0 Pin Event Trig 0 is selected
+ *  0b0100101..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0100110..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0100111..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0101000..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0101001..AOI1_OUT0 input is selected
+ *  0b0101010..AOI1_OUT1 input is selected
+ *  0b0101011..AOI1_OUT2 input is selected
+ *  0b0101100..AOI1_OUT3 input is selected
+ *  0b0101101..Reserved
+ *  0b0101110..Reserved
+ *  0b0101111..Reserved
+ *  0b0110000..Reserved
+ *  0b0110001..Reserved
+ *  0b0110010..Reserved
+ *  0b0110011..Reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..PWM1_SM0_OUT_TRIG0 input is selected
+ *  0b0111111..PWM1_SM0_OUT_TRIG1 input is selected
+ *  0b1000000..PWM1_SM1_OUT_TRIG0 input is selected
+ *  0b1000001..PWM1_SM1_OUT_TRIG1 input is selected
+ *  0b1000010..PWM1_SM2_OUT_TRIG0 input is selected
+ *  0b1000011..PWM1_SM2_OUT_TRIG1 input is selected
+ *  0b1000100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1000101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_QDC0_ICAP2_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_ICAP2_INP_SHIFT)) & INPUTMUX_QDC0_ICAP2_INP_MASK)
+/*! @} */
+
+/*! @name QDC0_ICAP3 - QDC0 Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_QDC0_ICAP3_INP_MASK             (0x7FU)
+#define INPUTMUX_QDC0_ICAP3_INP_SHIFT            (0U)
+/*! INP - QDC0 input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ARM_TXEV input is selected
+ *  0b0000010..AOI0_OUT0 input is selected
+ *  0b0000011..AOI0_OUT1 input is selected
+ *  0b0000100..AOI0_OUT2 input is selected
+ *  0b0000101..AOI0_OUT3 input is selected
+ *  0b0000110..CMP0_OUT input is selected
+ *  0b0000111..CMP1_OUT input is selected
+ *  0b0001000..CMP2_OUT input is selected
+ *  0b0001001..CTimer0_MAT2 input is selected
+ *  0b0001010..CTimer0_MAT3
+ *  0b0001011..CTimer1_MAT2 input is selected
+ *  0b0001100..CTimer1_MAT3 input is selected
+ *  0b0001101..CTimer2_MAT2 input is selected
+ *  0b0001110..CTimer2_MAT3 input is selected
+ *  0b0001111..Reserved
+ *  0b0010000..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0010001..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0010010..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0010011..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0010100..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0010101..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0010110..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0010111..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0011000..TRIG_IN0 input is selected
+ *  0b0011001..TRIG_IN1 input is selected
+ *  0b0011010..TRIG_IN2 input is selected
+ *  0b0011011..TRIG_IN3 input is selected
+ *  0b0011100..TRIG_IN4 input is selected
+ *  0b0011101..TRIG_IN5 input is selected
+ *  0b0011110..TRIG_IN6 input is selected
+ *  0b0011111..TRIG_IN7 input is selected
+ *  0b0100000..TRIG_IN8 input is selected
+ *  0b0100001..TRIG_IN9 input is selected
+ *  0b0100010..TRIG_IN10 input is selected
+ *  0b0100011..TRIG_IN11 input is selected
+ *  0b0100100..GPIO0 Pin Event Trig 0 is selected
+ *  0b0100101..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0100110..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0100111..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0101000..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0101001..AOI1_OUT0 input is selected
+ *  0b0101010..AOI1_OUT1 input is selected
+ *  0b0101011..AOI1_OUT2 input is selected
+ *  0b0101100..AOI1_OUT3 input is selected
+ *  0b0101101..Reserved
+ *  0b0101110..Reserved
+ *  0b0101111..Reserved
+ *  0b0110000..Reserved
+ *  0b0110001..Reserved
+ *  0b0110010..Reserved
+ *  0b0110011..reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..PWM1_SM0_OUT_TRIG0 input is selected
+ *  0b0111111..PWM1_SM0_OUT_TRIG1 input is selected
+ *  0b1000000..PWM1_SM1_OUT_TRIG0 input is selected
+ *  0b1000001..PWM1_SM1_OUT_TRIG1 input is selected
+ *  0b1000010..PWM1_SM2_OUT_TRIG0 input is selected
+ *  0b1000011..PWM1_SM2_OUT_TRIG1 input is selected
+ *  0b1000100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1000101..PWM0_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_QDC0_ICAP3_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_ICAP3_INP_SHIFT)) & INPUTMUX_QDC0_ICAP3_INP_MASK)
+/*! @} */
+
+/*! @name QDC1_TRIG - QDC1 Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_QDC1_TRIG_INP_MASK              (0x7FU)
+#define INPUTMUX_QDC1_TRIG_INP_SHIFT             (0U)
+/*! INP - QDC1 input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ARM_TXEV input is selected
+ *  0b0000010..AOI0_OUT0 input is selected
+ *  0b0000011..AOI0_OUT1 input is selected
+ *  0b0000100..AOI0_OUT2 input is selected
+ *  0b0000101..AOI0_OUT3 input is selected
+ *  0b0000110..CMP0_OUT input is selected
+ *  0b0000111..CMP1_OUT input is selected
+ *  0b0001000..CMP2_OUT input is selected
+ *  0b0001001..CTimer0_MAT2 input is selected
+ *  0b0001010..CTimer0_MAT3
+ *  0b0001011..CTimer1_MAT2 input is selected
+ *  0b0001100..CTimer1_MAT3 input is selected
+ *  0b0001101..CTimer2_MAT2 input is selected
+ *  0b0001110..CTimer2_MAT3 input is selected
+ *  0b0001111..Reserved
+ *  0b0010000..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0010001..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0010010..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0010011..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0010100..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0010101..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0010110..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0010111..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0011000..TRIG_IN0 input is selected
+ *  0b0011001..TRIG_IN1 input is selected
+ *  0b0011010..TRIG_IN2 input is selected
+ *  0b0011011..TRIG_IN3 input is selected
+ *  0b0011100..TRIG_IN4 input is selected
+ *  0b0011101..TRIG_IN5 input is selected
+ *  0b0011110..TRIG_IN6 input is selected
+ *  0b0011111..TRIG_IN7 input is selected
+ *  0b0100000..TRIG_IN8 input is selected
+ *  0b0100001..TRIG_IN9 input is selected
+ *  0b0100010..TRIG_IN10 input is selected
+ *  0b0100011..TRIG_IN11 input is selected
+ *  0b0100100..GPIO0 Pin Event Trig 0 is selected
+ *  0b0100101..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0100110..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0100111..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0101000..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0101001..AOI1_OUT0 input is selected
+ *  0b0101010..AOI1_OUT1 input is selected
+ *  0b0101011..AOI1_OUT2 input is selected
+ *  0b0101100..AOI1_OUT3 input is selected
+ *  0b0101101..Reserved
+ *  0b0101110..Reserved
+ *  0b0101111..Reserved
+ *  0b0110000..Reserved
+ *  0b0110001..Reserved
+ *  0b0110010..Reserved
+ *  0b0110011..Reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..PWM1_SM0_OUT_TRIG0 input is selected
+ *  0b0111111..PWM1_SM0_OUT_TRIG1 input is selected
+ *  0b1000000..PWM1_SM1_OUT_TRIG0 input is selected
+ *  0b1000001..PWM1_SM1_OUT_TRIG1 input is selected
+ *  0b1000010..PWM1_SM2_OUT_TRIG0 input is selected
+ *  0b1000011..PWM1_SM2_OUT_TRIG1 input is selected
+ *  0b1000100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1000101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_QDC1_TRIG_INP(x)                (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_TRIG_INP_SHIFT)) & INPUTMUX_QDC1_TRIG_INP_MASK)
+/*! @} */
+
+/*! @name QDC1_HOME - QDC1 Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_QDC1_HOME_INP_MASK              (0x7FU)
+#define INPUTMUX_QDC1_HOME_INP_SHIFT             (0U)
+/*! INP - QDC1 input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ARM_TXEV input is selected
+ *  0b0000010..AOI0_OUT0 input is selected
+ *  0b0000011..AOI0_OUT1 input is selected
+ *  0b0000100..AOI0_OUT2 input is selected
+ *  0b0000101..AOI0_OUT3 input is selected
+ *  0b0000110..CMP0_OUT input is selected
+ *  0b0000111..CMP1_OUT input is selected
+ *  0b0001000..CMP2_OUT input is selected
+ *  0b0001001..CTimer0_MAT2 input is selected
+ *  0b0001010..CTimer0_MAT3
+ *  0b0001011..CTimer1_MAT2 input is selected
+ *  0b0001100..CTimer1_MAT3 input is selected
+ *  0b0001101..CTimer2_MAT2 input is selected
+ *  0b0001110..CTimer2_MAT3 input is selected
+ *  0b0001111..Reserved
+ *  0b0010000..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0010001..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0010010..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0010011..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0010100..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0010101..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0010110..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0010111..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0011000..TRIG_IN0 input is selected
+ *  0b0011001..TRIG_IN1 input is selected
+ *  0b0011010..TRIG_IN2 input is selected
+ *  0b0011011..TRIG_IN3 input is selected
+ *  0b0011100..TRIG_IN4 input is selected
+ *  0b0011101..TRIG_IN5 input is selected
+ *  0b0011110..TRIG_IN6 input is selected
+ *  0b0011111..TRIG_IN7 input is selected
+ *  0b0100000..TRIG_IN8 input is selected
+ *  0b0100001..TRIG_IN9 input is selected
+ *  0b0100010..TRIG_IN10 input is selected
+ *  0b0100011..TRIG_IN11 input is selected
+ *  0b0100100..GPIO0 Pin Event Trig 0 is selected
+ *  0b0100101..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0100110..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0100111..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0101000..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0101001..AOI1_OUT0 input is selected
+ *  0b0101010..AOI1_OUT1 input is selected
+ *  0b0101011..AOI1_OUT2 input is selected
+ *  0b0101100..AOI1_OUT3 input is selected
+ *  0b0101101..Reserved
+ *  0b0101110..Reserved
+ *  0b0101111..Reserved
+ *  0b0110000..Reserved
+ *  0b0110001..Reserved
+ *  0b0110010..Reserved
+ *  0b0110011..Reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..PWM1_SM0_OUT_TRIG0 input is selected
+ *  0b0111111..PWM1_SM0_OUT_TRIG1 input is selected
+ *  0b1000000..PWM1_SM1_OUT_TRIG0 input is selected
+ *  0b1000001..PWM1_SM1_OUT_TRIG1 input is selected
+ *  0b1000010..PWM1_SM2_OUT_TRIG0 input is selected
+ *  0b1000011..PWM1_SM2_OUT_TRIG1 input is selected
+ *  0b1000100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1000101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_QDC1_HOME_INP(x)                (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_HOME_INP_SHIFT)) & INPUTMUX_QDC1_HOME_INP_MASK)
+/*! @} */
+
+/*! @name QDC1_INDEX - QDC1 Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_QDC1_INDEX_INP_MASK             (0x7FU)
+#define INPUTMUX_QDC1_INDEX_INP_SHIFT            (0U)
+/*! INP - QDC1 input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ARM_TXEV input is selected
+ *  0b0000010..AOI0_OUT0 input is selected
+ *  0b0000011..AOI0_OUT1 input is selected
+ *  0b0000100..AOI0_OUT2 input is selected
+ *  0b0000101..AOI0_OUT3 input is selected
+ *  0b0000110..CMP0_OUT input is selected
+ *  0b0000111..CMP1_OUT input is selected
+ *  0b0001000..>CMP2_OUT input is selected
+ *  0b0001001..CTimer0_MAT2 input is selected
+ *  0b0001010..CTimer0_MAT3
+ *  0b0001011..CTimer1_MAT2 input is selected
+ *  0b0001100..CTimer1_MAT3 input is selected
+ *  0b0001101..CTimer2_MAT2 input is selected
+ *  0b0001110..CTimer2_MAT3 input is selected
+ *  0b0001111..Reserved
+ *  0b0010000..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0010001..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0010010..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0010011..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0010100..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0010101..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0010110..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0010111..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0011000..TRIG_IN0 input is selected
+ *  0b0011001..TRIG_IN1 input is selected
+ *  0b0011010..TRIG_IN2 input is selected
+ *  0b0011011..TRIG_IN3 input is selected
+ *  0b0011100..TRIG_IN4 input is selected
+ *  0b0011101..TRIG_IN5 input is selected
+ *  0b0011110..TRIG_IN6 input is selected
+ *  0b0011111..TRIG_IN7 input is selected
+ *  0b0100000..TRIG_IN8 input is selected
+ *  0b0100001..TRIG_IN9 input is selected
+ *  0b0100010..TRIG_IN10 input is selected
+ *  0b0100011..TRIG_IN11 input is selected
+ *  0b0100100..GPIO0 Pin Event Trig 0 is selected
+ *  0b0100101..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0100110..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0100111..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0101000..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0101001..AOI1_OUT0 input is selected
+ *  0b0101010..AOI1_OUT1 input is selected
+ *  0b0101011..AOI1_OUT2 input is selected
+ *  0b0101100..AOI1_OUT3 input is selected
+ *  0b0101101..Reserved
+ *  0b0101110..Reserved
+ *  0b0101111..Reserved
+ *  0b0110000..Reserved
+ *  0b0110001..Reserved
+ *  0b0110010..Reserved
+ *  0b0110011..Reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..PWM1_SM0_OUT_TRIG0 input is selected
+ *  0b0111111..PWM1_SM0_OUT_TRIG1 input is selected
+ *  0b1000000..PWM1_SM1_OUT_TRIG0 input is selected
+ *  0b1000001..PWM1_SM1_OUT_TRIG1 input is selected
+ *  0b1000010..PWM1_SM2_OUT_TRIG0 input is selected
+ *  0b1000011..PWM1_SM2_OUT_TRIG1 input is selected
+ *  0b1000100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1000101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_QDC1_INDEX_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_INDEX_INP_SHIFT)) & INPUTMUX_QDC1_INDEX_INP_MASK)
+/*! @} */
+
+/*! @name QDC1_PHASEB - QDC1 Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_QDC1_PHASEB_INP_MASK            (0x7FU)
+#define INPUTMUX_QDC1_PHASEB_INP_SHIFT           (0U)
+/*! INP - QDC1 input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ARM_TXEV input is selected
+ *  0b0000010..AOI0_OUT0 input is selected
+ *  0b0000011..AOI0_OUT1 input is selected
+ *  0b0000100..AOI0_OUT2 input is selected
+ *  0b0000101..AOI0_OUT3 input is selected
+ *  0b0000110..CMP0_OUT input is selected
+ *  0b0000111..CMP1_OUT input is selected
+ *  0b0001000..CMP2_OUT input is selected
+ *  0b0001001..CTimer0_MAT2 input is selected
+ *  0b0001010..CTimer0_MAT3
+ *  0b0001011..CTimer1_MAT2 input is selected
+ *  0b0001100..CTimer1_MAT3 input is selected
+ *  0b0001101..CTimer2_MAT2 input is selected
+ *  0b0001110..CTimer2_MAT3 input is selected
+ *  0b0001111..Reserved
+ *  0b0010000..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0010001..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0010010..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0010011..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0010100..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0010101..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0010110..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0010111..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0011000..TRIG_IN0 input is selected
+ *  0b0011001..TRIG_IN1 input is selected
+ *  0b0011010..TRIG_IN2 input is selected
+ *  0b0011011..TRIG_IN3 input is selected
+ *  0b0011100..TRIG_IN4 input is selected
+ *  0b0011101..TRIG_IN5 input is selected
+ *  0b0011110..TRIG_IN6 input is selected
+ *  0b0011111..TRIG_IN7 input is selected
+ *  0b0100000..TRIG_IN8 input is selected
+ *  0b0100001..TRIG_IN9 input is selected
+ *  0b0100010..TRIG_IN10 input is selected
+ *  0b0100011..TRIG_IN11 input is selected
+ *  0b0100100..GPIO0 Pin Event Trig 0 is selected
+ *  0b0100101..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0100110..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0100111..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0101000..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0101001..AOI1_OUT0 input is selected
+ *  0b0101010..AOI1_OUT1 input is selected
+ *  0b0101011..AOI1_OUT2 input is selected
+ *  0b0101100..AOI1_OUT3 input is selected
+ *  0b0101101..Reserved
+ *  0b0101110..Reserved
+ *  0b0101111..Reserved
+ *  0b0110000..Reserved
+ *  0b0110001..Reserved
+ *  0b0110010..Reserved
+ *  0b0110011..Reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..PWM1_SM0_OUT_TRIG0 input is selected
+ *  0b0111111..PWM1_SM0_OUT_TRIG1 input is selected
+ *  0b1000000..PWM1_SM1_OUT_TRIG0 input is selected
+ *  0b1000001..PWM1_SM1_OUT_TRIG1 input is selected
+ *  0b1000010..PWM1_SM2_OUT_TRIG0 input is selected
+ *  0b1000011..PWM1_SM2_OUT_TRIG1 input is selected
+ *  0b1000100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1000101..PWM1_SM3_MUX_TRIG1 inout is selected
+ */
+#define INPUTMUX_QDC1_PHASEB_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_PHASEB_INP_SHIFT)) & INPUTMUX_QDC1_PHASEB_INP_MASK)
+/*! @} */
+
+/*! @name QDC1_PHASEA - QDC1 Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_QDC1_PHASEA_INP_MASK            (0x7FU)
+#define INPUTMUX_QDC1_PHASEA_INP_SHIFT           (0U)
+/*! INP - QDC0 input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ARM_TXEV input is selected
+ *  0b0000010..AOI0_OUT0 input is selected
+ *  0b0000011..AOI0_OUT1 input is selected
+ *  0b0000100..AOI0_OUT2 input is selected
+ *  0b0000101..AOI0_OUT3 input is selected
+ *  0b0000110..CMP0_OUT input is selected
+ *  0b0000111..CMP1_OUT input is selected
+ *  0b0001000..CMP2_OUT input is selected
+ *  0b0001001..CTimer0_MAT2 input is selected
+ *  0b0001010..CTimer0_MAT3
+ *  0b0001011..CTimer1_MAT2 input is selected
+ *  0b0001100..CTimer1_MAT3 input is selected
+ *  0b0001101..CTimer2_MAT2 input is selected
+ *  0b0001110..CTimer2_MAT3 input is selected
+ *  0b0001111..Reserved
+ *  0b0010000..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0010001..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0010010..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0010011..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0010100..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0010101..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0010110..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0010111..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0011000..TRIG_IN0 input is selected
+ *  0b0011001..TRIG_IN1 input is selected
+ *  0b0011010..TRIG_IN2 input is selected
+ *  0b0011011..TRIG_IN3 input is selected
+ *  0b0011100..TRIG_IN4 input is selected
+ *  0b0011101..TRIG_IN5 input is selected
+ *  0b0011110..TRIG_IN6 input is selected
+ *  0b0011111..TRIG_IN7 input is selected
+ *  0b0100000..TRIG_IN8 input is selected
+ *  0b0100001..TRIG_IN9 input is selected
+ *  0b0100010..TRIG_IN10 input is selected
+ *  0b0100011..TRIG_IN11 input is selected
+ *  0b0100100..GPIO0 Pin Event Trig 0 is selected
+ *  0b0100101..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0100110..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0100111..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0101000..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0101001..AOI1_OUT0 input is selected
+ *  0b0101010..AOI1_OUT1 input is selected
+ *  0b0101011..AOI1_OUT2 input is selected
+ *  0b0101100..AOI1_OUT3 input is selected
+ *  0b0101101..Reserved
+ *  0b0101110..Reserved
+ *  0b0101111..Reserved
+ *  0b0110000..Reserved
+ *  0b0110001..Reserved
+ *  0b0110010..Reserved
+ *  0b0110011..Reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..PWM1_SM0_OUT_TRIG0 input is selected
+ *  0b0111111..PWM1_SM0_OUT_TRIG1 input is selected
+ *  0b1000000..PWM1_SM1_OUT_TRIG0 input is selected
+ *  0b1000001..PWM1_SM1_OUT_TRIG1 input is selected
+ *  0b1000010..PWM1_SM2_OUT_TRIG0 input is selected
+ *  0b1000011..PWM1_SM2_OUT_TRIG1 input is selected
+ *  0b1000100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1000101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_QDC1_PHASEA_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_PHASEA_INP_SHIFT)) & INPUTMUX_QDC1_PHASEA_INP_MASK)
+/*! @} */
+
+/*! @name QDC1_ICAP1 - QDC1 Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_QDC1_ICAP1_INP_MASK             (0x7FU)
+#define INPUTMUX_QDC1_ICAP1_INP_SHIFT            (0U)
+/*! INP - QDC1 input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ARM_TXEV input is selected
+ *  0b0000010..AOI0_OUT0 input is selected
+ *  0b0000011..AOI0_OUT1 input is selected
+ *  0b0000100..AOI0_OUT2 input is selected
+ *  0b0000101..AOI0_OUT3 input is selected
+ *  0b0000110..CMP0_OUT input is selected
+ *  0b0000111..CMP1_OUT input is selected
+ *  0b0001000..CMP2_OUT input is selected
+ *  0b0001001..CTimer0_MAT2 input is selected
+ *  0b0001010..CTimer0_MAT3
+ *  0b0001011..CTimer1_MAT2 input is selected
+ *  0b0001100..CTimer1_MAT3 input is selected
+ *  0b0001101..CTimer2_MAT2 input is selected
+ *  0b0001110..CTimer2_MAT3 input is selected
+ *  0b0001111..Reserved
+ *  0b0010000..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0010001..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0010010..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0010011..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0010100..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0010101..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0010110..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0010111..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0011000..TRIG_IN0 input is selected
+ *  0b0011001..TRIG_IN1 input is selected
+ *  0b0011010..TRIG_IN2 input is selected
+ *  0b0011011..TRIG_IN3 input is selected
+ *  0b0011100..TRIG_IN4 input is selected
+ *  0b0011101..TRIG_IN5 input is selected
+ *  0b0011110..TRIG_IN6 input is selected
+ *  0b0011111..TRIG_IN7 input is selected
+ *  0b0100000..TRIG_IN8 input is selected
+ *  0b0100001..TRIG_IN9 input is selected
+ *  0b0100010..TRIG_IN10 input is selected
+ *  0b0100011..TRIG_IN11 input is selected
+ *  0b0100100..GPIO0 Pin Event Trig 0 is selected
+ *  0b0100101..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0100110..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0100111..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0101000..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0101001..AOI1_OUT0 input is selected
+ *  0b0101010..AOI1_OUT1 input is selected
+ *  0b0101011..AOI1_OUT2 input is selected
+ *  0b0101100..AOI1_OUT3 input is selected
+ *  0b0101101..Reserved
+ *  0b0101110..Reserved
+ *  0b0101111..Reserved
+ *  0b0110000..Reserved
+ *  0b0110001..Reserved
+ *  0b0110010..Reserved
+ *  0b0110011..Reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..PWM1_SM0_OUT_TRIG0 input is selected
+ *  0b0111111..PWM1_SM0_OUT_TRIG1 input is selected
+ *  0b1000000..PWM1_SM1_OUT_TRIG0 input is selected
+ *  0b1000001..PWM1_SM1_OUT_TRIG1 input is selected
+ *  0b1000010..PWM1_SM2_OUT_TRIG0 input is selected
+ *  0b1000011..PWM1_SM2_OUT_TRIG1 input is selected
+ *  0b1000100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1000101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_QDC1_ICAP1_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_ICAP1_INP_SHIFT)) & INPUTMUX_QDC1_ICAP1_INP_MASK)
+/*! @} */
+
+/*! @name QDC1_ICAP2 - QDC1 Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_QDC1_ICAP2_INP_MASK             (0x7FU)
+#define INPUTMUX_QDC1_ICAP2_INP_SHIFT            (0U)
+/*! INP - QDC1 input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ARM_TXEV input is selected
+ *  0b0000010..AOI0_OUT0 input is selected
+ *  0b0000011..AOI0_OUT1 input is selected
+ *  0b0000100..AOI0_OUT2 input is selected
+ *  0b0000101..AOI0_OUT3 input is selected
+ *  0b0000110..CMP0_OUT input is selected
+ *  0b0000111..CMP1_OUT input is selected
+ *  0b0001000..CMP2_OUT input is selected
+ *  0b0001001..CTimer0_MAT2 input is selected
+ *  0b0001010..CTimer0_MAT3
+ *  0b0001011..CTimer1_MAT2 input is selected
+ *  0b0001100..CTimer1_MAT3 input is selected
+ *  0b0001101..CTimer2_MAT2 input is selected
+ *  0b0001110..CTimer2_MAT3 input is selected
+ *  0b0001111..Reserved
+ *  0b0010000..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0010001..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0010010..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0010011..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0010100..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0010101..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0010110..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0010111..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0011000..TRIG_IN0 input is selected
+ *  0b0011001..TRIG_IN1 input is selected
+ *  0b0011010..TRIG_IN2 input is selected
+ *  0b0011011..TRIG_IN3 input is selected
+ *  0b0011100..TRIG_IN4 input is selected
+ *  0b0011101..TRIG_IN5 input is selected
+ *  0b0011110..TRIG_IN6 input is selected
+ *  0b0011111..TRIG_IN7 input is selected
+ *  0b0100000..TRIG_IN8 input is selected
+ *  0b0100001..TRIG_IN9 input is selected
+ *  0b0100010..TRIG_IN10 input is selected
+ *  0b0100011..TRIG_IN11 input is selected
+ *  0b0100100..GPIO0 Pin Event Trig 0 is selected
+ *  0b0100101..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0100110..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0100111..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0101000..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0101001..AOI1_OUT0 input is selected
+ *  0b0101010..AOI1_OUT1 input is selected
+ *  0b0101011..AOI1_OUT2 input is selected
+ *  0b0101100..AOI1_OUT3 input is selected
+ *  0b0101101..Reserved
+ *  0b0101110..Reserved
+ *  0b0101111..Reserved
+ *  0b0110000..Reserved
+ *  0b0110001..Reserved
+ *  0b0110010..Reserved
+ *  0b0110011..Reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..PWM1_SM0_OUT_TRIG0 input is selected
+ *  0b0111111..PWM1_SM0_OUT_TRIG1 input is selected
+ *  0b1000000..PWM1_SM1_OUT_TRIG0 input is selected
+ *  0b1000001..PWM1_SM1_OUT_TRIG1 input is selected
+ *  0b1000010..PWM1_SM2_OUT_TRIG0 input is selected
+ *  0b1000011..PWM1_SM2_OUT_TRIG1 input is selected
+ *  0b1000100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1000101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_QDC1_ICAP2_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_ICAP2_INP_SHIFT)) & INPUTMUX_QDC1_ICAP2_INP_MASK)
+/*! @} */
+
+/*! @name QDC1_ICAP3 - QDC1 Trigger Input Connections */
+/*! @{ */
+
+#define INPUTMUX_QDC1_ICAP3_INP_MASK             (0x7FU)
+#define INPUTMUX_QDC1_ICAP3_INP_SHIFT            (0U)
+/*! INP - QDC1 input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ARM_TXEV input is selected
+ *  0b0000010..AOI0_OUT0 input is selected
+ *  0b0000011..AOI0_OUT1 input is selected
+ *  0b0000100..AOI0_OUT2 input is selected
+ *  0b0000101..AOI0_OUT3 input is selected
+ *  0b0000110..CMP0_OUT input is selected
+ *  0b0000111..CMP1_OUT input is selected
+ *  0b0001000..CMP2_OUT input is selected
+ *  0b0001001..CTimer0_MAT2 input is selected
+ *  0b0001010..CTimer0_MAT3
+ *  0b0001011..CTimer1_MAT2 input is selected
+ *  0b0001100..CTimer1_MAT3 input is selected
+ *  0b0001101..CTimer2_MAT2 input is selected
+ *  0b0001110..CTimer2_MAT3 input is selected
+ *  0b0001111..Reserved
+ *  0b0010000..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b0010001..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0010010..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0010011..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0010100..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0010101..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0010110..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0010111..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0011000..TRIG_IN0 input is selected
+ *  0b0011001..TRIG_IN1 input is selected
+ *  0b0011010..TRIG_IN2 input is selected
+ *  0b0011011..TRIG_IN3 input is selected
+ *  0b0011100..TRIG_IN4 input is selected
+ *  0b0011101..TRIG_IN5 input is selected
+ *  0b0011110..TRIG_IN6 input is selected
+ *  0b0011111..TRIG_IN7 input is selected
+ *  0b0100000..TRIG_IN8 input is selected
+ *  0b0100001..TRIG_IN9 input is selected
+ *  0b0100010..TRIG_IN10 input is selected
+ *  0b0100011..TRIG_IN11 input is selected
+ *  0b0100100..GPIO0 Pin Event Trig 0 is selected
+ *  0b0100101..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0100110..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0100111..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0101000..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0101001..AOI1_OUT0 input is selected
+ *  0b0101010..AOI1_OUT1 input is selected
+ *  0b0101011..AOI1_OUT2 input is selected
+ *  0b0101100..AOI1_OUT3 input is selected
+ *  0b0101101..Reserved
+ *  0b0101110..Reserved
+ *  0b0101111..Reserved
+ *  0b0110000..Reserved
+ *  0b0110001..Reserved
+ *  0b0110010..Reserved
+ *  0b0110011..Reserved
+ *  0b0110100..Reserved
+ *  0b0110101..Reserved
+ *  0b0110110..Reserved
+ *  0b0110111..Reserved
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..PWM1_SM0_OUT_TRIG0 input is selected
+ *  0b0111111..PWM1_SM0_OUT_TRIG1 input is selected
+ *  0b1000000..PWM1_SM1_OUT_TRIG0 input is selected
+ *  0b1000001..PWM1_SM1_OUT_TRIG1 input is selected
+ *  0b1000010..PWM1_SM2_OUT_TRIG0 input is selected
+ *  0b1000011..PWM1_SM2_OUT_TRIG1 input is selected
+ *  0b1000100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1000101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_QDC1_ICAP3_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_ICAP3_INP_SHIFT)) & INPUTMUX_QDC1_ICAP3_INP_MASK)
+/*! @} */
+
+/*! @name FLEXPWM0_SM0_EXTA0 - PWM0 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_MASK  (0x3FU)
+#define INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_SHIFT (0U)
+/*! TRIGIN - EXTA input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM0_SM0_EXTSYNC - PWM0 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN_MASK (0x3FU)
+#define INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN_SHIFT (0U)
+/*! TRIGIN - EXTSYNC input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM0_SM1_EXTA - PWM0 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN_MASK   (0x3FU)
+#define INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN_SHIFT  (0U)
+/*! TRIGIN - EXTA input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM0_SM1_EXTSYNC - PWM0 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN_MASK (0x3FU)
+#define INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN_SHIFT (0U)
+/*! TRIGIN - EXTSYNC input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM0_SM2_EXTA - PWM0 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN_MASK   (0x3FU)
+#define INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN_SHIFT  (0U)
+/*! TRIGIN - EXTA input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM0_SM2_EXTSYNC - PWM0 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN_MASK (0x3FU)
+#define INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN_SHIFT (0U)
+/*! TRIGIN - EXTSYNC input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM0_SM3_EXTA0 - PWM0 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM0_SM3_EXTA0_TRIGIN_MASK  (0x3FU)
+#define INPUTMUX_FLEXPWM0_SM3_EXTA0_TRIGIN_SHIFT (0U)
+/*! TRIGIN - EXTA input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM0_SM3_EXTA0_TRIGIN(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM3_EXTA0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM3_EXTA0_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM0_SM3_EXTSYNC - PWM0 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM0_SM3_EXTSYNC_TRIGIN_MASK (0x3FU)
+#define INPUTMUX_FLEXPWM0_SM3_EXTSYNC_TRIGIN_SHIFT (0U)
+/*! TRIGIN - EXTSYNC input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM0_SM3_EXTSYNC_TRIGIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM3_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM3_EXTSYNC_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM0_FAULT - PWM0 Fault Input Trigger Connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM0_FAULT_TRIGIN_MASK      (0x3FU)
+#define INPUTMUX_FLEXPWM0_FAULT_TRIGIN_SHIFT     (0U)
+/*! TRIGIN - FAULT input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM0_FAULT_TRIGIN(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_FAULT_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM0_FORCE - PWM0 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM0_FORCE_TRIGIN_MASK      (0x3FU)
+#define INPUTMUX_FLEXPWM0_FORCE_TRIGIN_SHIFT     (0U)
+/*! TRIGIN - Trigger input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM1_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM0_FORCE_TRIGIN(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_FORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_FORCE_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM1_SM0_EXTA0 - PWM1 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN_MASK  (0x3FU)
+#define INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN_SHIFT (0U)
+/*! TRIGIN - EXTA input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM0_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM1_SM0_EXTSYNC - PWM1 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN_MASK (0x3FU)
+#define INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN_SHIFT (0U)
+/*! TRIGIN - EXTSYNC input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM0_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM1_SM1_EXTA - PWM1 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN_MASK   (0x3FU)
+#define INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN_SHIFT  (0U)
+/*! TRIGIN - EXTA input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM0_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM1_SM1_EXTSYNC - PWM1 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN_MASK (0x3FU)
+#define INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN_SHIFT (0U)
+/*! TRIGIN - EXTSYNC input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM0_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM1_SM2_EXTA - PWM1 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN_MASK   (0x3FU)
+#define INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN_SHIFT  (0U)
+/*! TRIGIN - EXTA input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM0_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM1_SM2_EXTSYNC - PWM1 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN_MASK (0x3FU)
+#define INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN_SHIFT (0U)
+/*! TRIGIN - EXTSYNC input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM0_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM1_SM3_EXTA0 - PWM1 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM1_SM3_EXTA0_TRIGIN_MASK  (0x3FU)
+#define INPUTMUX_FLEXPWM1_SM3_EXTA0_TRIGIN_SHIFT (0U)
+/*! TRIGIN - EXTA input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM0_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM1_SM3_EXTA0_TRIGIN(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM3_EXTA0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM3_EXTA0_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM1_SM3_EXTSYNC - PWM1 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM1_SM3_EXTSYNC_TRIGIN_MASK (0x3FU)
+#define INPUTMUX_FLEXPWM1_SM3_EXTSYNC_TRIGIN_SHIFT (0U)
+/*! TRIGIN - EXTSYNC input connections for PWM0
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM0_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM1_SM3_EXTSYNC_TRIGIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM3_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM3_EXTSYNC_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM1_FAULT - PWM1 Fault Input Trigger Connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK      (0x3FU)
+#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT     (0U)
+/*! TRIGIN - FAULT input connections for PWM1
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM0_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK)
+/*! @} */
+
+/*! @name FLEXPWM1_FORCE - PWM1 input trigger connections */
+/*! @{ */
+
+#define INPUTMUX_FLEXPWM1_FORCE_TRIGIN_MASK      (0x3FU)
+#define INPUTMUX_FLEXPWM1_FORCE_TRIGIN_SHIFT     (0U)
+/*! TRIGIN - Trigger input connections for PWM1
+ *  0b000000..Reserved
+ *  0b000001..ARM_TXEV input is selected
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..QDC0_CMP_FLAG0 input is selected
+ *  0b010000..QDC0_CMP_FLAG1 input is selected
+ *  0b010001..QDC0_CMP_FLAG2 input is selected
+ *  0b010010..QDC0_CMP_FLAG3 input is selected
+ *  0b010011..QDC0_POS_MATCH0 input is selected
+ *  0b010100..TRIG_IN0 input is selected
+ *  0b010101..TRIG_IN1 input is selected
+ *  0b010110..TRIG_IN2 input is selected
+ *  0b010111..TRIG_IN3 input is selected
+ *  0b011000..TRIG_IN4 input is selected
+ *  0b011001..TRIG_IN5 input is selected
+ *  0b011010..TRIG_IN6 input is selected
+ *  0b011011..TRIG_IN7 input is selected
+ *  0b011100..TRIG_IN8 input is selected
+ *  0b011101..TRIG_IN9 input is selected
+ *  0b011110..TRIG_IN10 input is selected
+ *  0b011111..TRIG_IN11 input is selected
+ *  0b100000..GPIO0 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO1 Pin Event Trig 0 input is selected
+ *  0b100010..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100011..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100100..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100101..AOI1_OUT0 input is selected
+ *  0b100110..AOI1_OUT1 input is selected
+ *  0b100111..AOI1_OUT2 input is selected
+ *  0b101000..AOI1_OUT3 input is selected
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..QDC1_CMP_FLAG0 input is selected
+ *  0b110010..QDC1_CMP_FLAG1 input is selected
+ *  0b110011..QDC1_CMP_FLAG2 input is selected
+ *  0b110100..QDC1_CMP_FLAG3 input is selected
+ *  0b110101..QDC1_POS_MATCH0 input is selected
+ *  0b110110..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b110111..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b111000..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b111001..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b111010..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b111011..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b111100..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b111101..PWM0_SM3_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_FLEXPWM1_FORCE_TRIGIN(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_FORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_FORCE_TRIGIN_MASK)
+/*! @} */
+
+/*! @name PWM0_EXT_CLK - PWM0 external clock trigger */
+/*! @{ */
+
+#define INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK        (0xFU)
+#define INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT       (0U)
+/*! TRIGIN - Trigger input connections for PWM
+ *  0b0000..Reserved
+ *  0b0001..clk_16k[1] input is selected
+ *  0b0010..clk_in input is selected
+ *  0b0011..AOI0_OUT0 input is selected
+ *  0b0100..AOI0_OUT1 input is selected
+ *  0b0101..EXTTRIG_IN0 input is selected
+ *  0b0110..EXTTRIG_IN7 input is selected
+ *  0b0111..AOI1_OUT0 input is selected
+ *  0b1000..AOI1_OUT1 input is selected
+ */
+#define INPUTMUX_PWM0_EXT_CLK_TRIGIN(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK)
+/*! @} */
+
+/*! @name PWM1_EXT_CLK - PWM1 external clock trigger */
+/*! @{ */
+
+#define INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK        (0xFU)
+#define INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT       (0U)
+/*! TRIGIN - Trigger input connections for PWM
+ *  0b0000..Reserved
+ *  0b0001..clk_16k[1] input is selected
+ *  0b0010..clk_in input is selected
+ *  0b0011..AOI0_OUT0 input is selected
+ *  0b0100..AOI0_OUT1 input is selected
+ *  0b0101..EXTTRIG_IN0 input is selected
+ *  0b0110..EXTTRIG_IN7 input is selected
+ *  0b0111..AOI1_OUT0 input is selected
+ *  0b1000..AOI1_OUT1 input is selected
+ */
+#define INPUTMUX_PWM1_EXT_CLK_TRIGIN(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK)
+/*! @} */
+
+/*! @name AOI0_INPUTK_AOI0_INPUT - AOI0 trigger input connections 0 */
+/*! @{ */
+
+#define INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP_MASK (0x7FU)
+#define INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP_SHIFT (0U)
+/*! INP - AOI0 trigger input connections
+ *  0b0000000..Reserved
+ *  0b0000001..ADC0_tcomp[0] input is selected
+ *  0b0000010..ADC0_tcomp[1] input is selected
+ *  0b0000011..ADC0_tcomp[2] input is selected
+ *  0b0000100..ADC0_tcomp[3] input is selected
+ *  0b0000101..CMP0_OUT input is selected
+ *  0b0000110..CMP1_OUT input is selected
+ *  0b0000111..CMP2_OUT input is selected
+ *  0b0001000..CTimer0_MAT0 input is selected
+ *  0b0001001..CTimer0_MAT1 input is selected
+ *  0b0001010..CTimer0_MAT2 input is selected
+ *  0b0001011..CTimer0_MAT3 input is selected
+ *  0b0001100..CTimer1_MAT0
+ *  0b0001101..CTimer1_MAT1 input is selected
+ *  0b0001110..CTimer1_MAT2 input is selected
+ *  0b0001111..CTimer1_MAT3 input is selected
+ *  0b0010000..CTimer2_MAT0 input is selected
+ *  0b0010001..CTimer2_MAT1 input is selected
+ *  0b0010010..CTimer2_MAT2 input is selected
+ *  0b0010011..CTimer2_MAT3 input is selected
+ *  0b0010100..LPTMR0 input is selected
+ *  0b0010101..Reserved
+ *  0b0010110..QDC0_CMP_FLAG0 input is selected
+ *  0b0010111..QDC0_CMP_FLAG1 input is selected
+ *  0b0011000..QDC0_CMP_FLAG2 input is selected
+ *  0b0011001..QDC0_CMP_FLAG3 input is selected
+ *  0b0011010..QDC0_POS_MATCH input is selected
+ *  0b0011011..PWM0_SM0_MUX_TRIG0 0 input is selected
+ *  0b0011100..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b0011101..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b0011110..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b0011111..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b0100000..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b0100001..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b0100010..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b0100011..TRIG_IN0 input is selected
+ *  0b0100100..TRIG_IN1 input is selected
+ *  0b0100101..TRIG_IN2 input is selected
+ *  0b0100110..TRIG_IN3 input is selected
+ *  0b0100111..TRIG_IN4 input is selected
+ *  0b0101000..TRIG_IN5 input is selected
+ *  0b0101001..TRIG_IN6 input is selected
+ *  0b0101010..TRIG_IN7 input is selected
+ *  0b0101011..TRIG_IN8 input is selected
+ *  0b0101100..TRIG_IN9 input is selected
+ *  0b0101101..TRIG_IN10 input is selected
+ *  0b0101110..TRIG_IN11 input is selected
+ *  0b0101111..GPIO0 Pin Event Trig 0 input is selected
+ *  0b0110000..GPIO1 Pin Event Trig 0 input is selected
+ *  0b0110001..GPIO2 Pin Event Trig 0 input is selected
+ *  0b0110010..GPIO3 Pin Event Trig 0 input is selected
+ *  0b0110011..GPIO4 Pin Event Trig 0 input is selected
+ *  0b0110100..ADC1_tcomp[0] input is selected
+ *  0b0110101..ADC1_tcomp[1] input is selected
+ *  0b0110110..ADC1_tcomp[2] input is selected
+ *  0b0110111..ADC1_tcomp[3] input is selected
+ *  0b0111000..Reserved
+ *  0b0111001..Reserved
+ *  0b0111010..Reserved
+ *  0b0111011..Reserved
+ *  0b0111100..Reserved
+ *  0b0111101..Reserved
+ *  0b0111110..Reserved
+ *  0b0111111..Reserved
+ *  0b1000000..Reserved
+ *  0b1000001..Reserved
+ *  0b1000010..Reserved
+ *  0b1000011..Reserved
+ *  0b1000100..QDC1_CMP_FLAG0 input is selected
+ *  0b1000101..QDC1_CMP_FLAG1 input is selected
+ *  0b1000110..QDC1_CMP_FLAG2 input is selected
+ *  0b1000111..QDC1_CMP_FLAG3 input is selected
+ *  0b1001000..QDC1_POS_MATCH0 input is selected
+ *  0b1001001..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b1001010..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b1001011..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b1001100..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b1001101..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b1001110..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b1001111..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b1010000..PWM1_SM3_MUX_TRIG1 input is selected
+ *  0b1010001..PWM0_SM0_A_Output
+ *  0b1010010..PWM0_SM0_B_Output
+ *  0b1010011..PWM0_SM1_A_Output
+ *  0b1010100..PWM0_SM1_B_Output
+ *  0b1010101..PWM0_SM2_A_Output
+ *  0b1010110..PWM0_SM2_B_Output
+ *  0b1010111..PWM0_SM3_A_Output
+ *  0b1011000..PWM0_SM3_B_Output
+ *  0b1011001..Reserved
+ *  0b1011010..Reserved
+ *  0b1011011..Reserved
+ *  0b1011100..Reserved
+ *  0b1011101..Reserved
+ *  0b1011110..Reserved
+ *  0b1011111..Reserved
+ *  0b1100000..Reserved
+ */
+#define INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP_SHIFT)) & INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_AOI0_INPUTK_AOI0_INPUT */
+#define INPUTMUX_AOI0_INPUTK_AOI0_INPUT_COUNT    (16U)
+
+/*! @name EXT_TRIGN_TRIG_OUT - EXT trigger connections */
+/*! @{ */
+
+#define INPUTMUX_EXT_TRIGN_TRIG_OUT_INP_MASK     (0x1FU)
+#define INPUTMUX_EXT_TRIGN_TRIG_OUT_INP_SHIFT    (0U)
+/*! INP - EXT trigger input connections
+ *  0b00000..Reserved
+ *  0b00001..Reserved
+ *  0b00010..AOI0_OUT0 input is selected
+ *  0b00011..AOI0_OUT1 input is selected
+ *  0b00100..AOI0_OUT2 input is selected
+ *  0b00101..AOI0_OUT3 input is selected
+ *  0b00110..CMP0_OUT input is selected
+ *  0b00111..CMP1_OUT input is selected
+ *  0b01000..CMP2_OUT input is selected
+ *  0b01001..LPUART0 ipp_do_lpuart_txd input is selected
+ *  0b01010..LPUART1 ipp_do_lpuart_txd input is selected
+ *  0b01011..LPUART2 ipp_do_lpuart_txd input is selected
+ *  0b01100..LPUART3 ipp_do_lpuart_txd input is selected
+ *  0b01101..Reserved
+ *  0b01110..AOI1_OUT0 input is selected
+ *  0b01111..AOI1_OUT1 input is selected
+ *  0b10000..AOI1_OUT2 input is selected
+ *  0b10001..RTC_1Hz_CLK input is selected
+ *  0b10010..Reserved
+ */
+#define INPUTMUX_EXT_TRIGN_TRIG_OUT_INP(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIGN_TRIG_OUT_INP_SHIFT)) & INPUTMUX_EXT_TRIGN_TRIG_OUT_INP_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_EXT_TRIGN_TRIG_OUT */
+#define INPUTMUX_EXT_TRIGN_TRIG_OUT_COUNT        (8U)
+
+/*! @name CMP1_TRIG - CMP1 input connections */
+/*! @{ */
+
+#define INPUTMUX_CMP1_TRIG_TRIGIN_MASK           (0x3FU)
+#define INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT          (0U)
+/*! TRIGIN - CMP0 input trigger
+ *  0b000000..Reserved
+ *  0b000001..Reserved
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP2_OUT input is selected
+ *  0b001000..CTimer0_MAT0 input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer1_MAT0
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer2_MAT0 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..LPTMR0 input is selected
+ *  0b001111..Reserved
+ *  0b010000..QDC0_POS_MATCH0
+ *  0b010001..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b010010..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b010011..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b010100..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b010101..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b010110..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b010111..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b011000..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b011001..GPIO0 Pin Event Trig 0 input is selected
+ *  0b011010..GPIO1 Pin Event Trig 0 input is selected
+ *  0b011011..GPIO2 Pin Event Trig 0 input is selected
+ *  0b011100..GPIO3 Pin Event Trig 0 input is selected
+ *  0b011101..GPIO4 Pin Event Trig 0 input is selected
+ *  0b011110..WUU input is selected
+ *  0b011111..AOI1_OUT0 input is selected
+ *  0b100000..AOI1_OUT1 input is selected
+ *  0b100001..AOI1_OUT2 input is selected
+ *  0b100010..AOI1_OUT3 input is selected
+ *  0b100011..Reserved
+ *  0b100100..Reserved
+ *  0b100101..Reserved
+ *  0b100110..Reserved
+ *  0b100111..Reserved
+ *  0b101000..Reserved
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..QDC1_POS_MATCH0 input is selected
+ *  0b110000..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b110001..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b110010..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b110011..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b110100..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b110101..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b110110..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b110111..PWM1_SM2_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_CMP1_TRIG_TRIGIN(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP1_TRIG_TRIGIN_MASK)
+/*! @} */
+
+/*! @name CMP2_TRIG - CMP2 input connections */
+/*! @{ */
+
+#define INPUTMUX_CMP2_TRIG_TRIGIN_MASK           (0x3FU)
+#define INPUTMUX_CMP2_TRIG_TRIGIN_SHIFT          (0U)
+/*! TRIGIN - CMP0 input trigger
+ *  0b000000..Reserved
+ *  0b000001..Reserved
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CTimer0_MAT0 input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer1_MAT0
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer2_MAT0 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..LPTMR0 input is selected
+ *  0b001111..Reserved
+ *  0b010000..QDC0_POS_MATCH0
+ *  0b010001..PWM0_SM0_MUX_TRIG0 input is selected
+ *  0b010010..PWM0_SM0_MUX_TRIG1 input is selected
+ *  0b010011..PWM0_SM1_MUX_TRIG0 input is selected
+ *  0b010100..PWM0_SM1_MUX_TRIG1 input is selected
+ *  0b010101..PWM0_SM2_MUX_TRIG0 input is selected
+ *  0b010110..PWM0_SM2_MUX_TRIG1 input is selected
+ *  0b010111..PWM0_SM3_MUX_TRIG0 input is selected
+ *  0b011000..PWM0_SM3_MUX_TRIG1 input is selected
+ *  0b011001..GPIO0 Pin Event Trig 0 input is selected
+ *  0b011010..GPIO1 Pin Event Trig 0 input is selected
+ *  0b011011..GPIO2 Pin Event Trig 0 input is selected
+ *  0b011100..GPIO3 Pin Event Trig 0 input is selected
+ *  0b011101..GPIO4 Pin Event Trig 0 input is selected
+ *  0b011110..WUU input is selected
+ *  0b011111..AOI1_OUT0 input is selected
+ *  0b100000..AOI1_OUT1 input is selected
+ *  0b100001..AOI1_OUT2 input is selected
+ *  0b100010..AOI1_OUT3 input is selected
+ *  0b100011..Reserved
+ *  0b100100..Reserved
+ *  0b100101..Reserved
+ *  0b100110..Reserved
+ *  0b100111..Reserved
+ *  0b101000..Reserved
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..QDC1_POS_MATCH0 input is selected
+ *  0b110000..PWM1_SM0_MUX_TRIG0 input is selected
+ *  0b110001..PWM1_SM0_MUX_TRIG1 input is selected
+ *  0b110010..PWM1_SM1_MUX_TRIG0 input is selected
+ *  0b110011..PWM1_SM1_MUX_TRIG1 input is selected
+ *  0b110100..PWM1_SM2_MUX_TRIG0 input is selected
+ *  0b110101..PWM1_SM2_MUX_TRIG1 input is selected
+ *  0b110110..PWM1_SM3_MUX_TRIG0 input is selected
+ *  0b110111..PWM1_SM2_MUX_TRIG1 input is selected
+ */
+#define INPUTMUX_CMP2_TRIG_TRIGIN(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP2_TRIG_TRIGIN_MASK)
+/*! @} */
+
+/*! @name LPI2C0_TRIG - LPI2C0 trigger input connections */
+/*! @{ */
+
+#define INPUTMUX_LPI2C0_TRIG_INP_MASK            (0x3FU)
+#define INPUTMUX_LPI2C0_TRIG_INP_SHIFT           (0U)
+/*! INP - LPI2C0 trigger input connections
+ *  0b000000..Reserved
+ *  0b000001..Reserved
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT0 input is selected
+ *  0b001010..CTimer0_MAT1 input is selected
+ *  0b001011..CTimer1_MAT0 input is selected
+ *  0b001100..CTimer1_MAT1 input is selected
+ *  0b001101..CTimer2_MAT0 input is selected
+ *  0b001110..CTimer2_MAT1 input is selected
+ *  0b001111..LPTMR0 input is selected
+ *  0b010000..Reserved
+ *  0b010001..TRIG_IN0 input is selected
+ *  0b010010..TRIG_IN1 input is selected
+ *  0b010011..TRIG_IN2 input is selected
+ *  0b010100..TRIG_IN3 input is selected
+ *  0b010101..TRIG_IN4 input is selected
+ *  0b010110..TRIG_IN5 input is selected
+ *  0b010111..TRIG_IN6 input is selected
+ *  0b011000..TRIG_IN7 input is selected
+ *  0b011001..GPIO0 Pin Event Trig 0 input is selected
+ *  0b011010..GPIO1 Pin Event Trig 0 input is selected
+ *  0b011011..GPIO2 Pin Event Trig 0 input is selected
+ *  0b011100..GPIO3 Pin Event Trig 0 input is selected
+ *  0b011101..GPIO4 Pin Event Trig 0 input is selected
+ *  0b011110..WUU input is selected
+ *  0b011111..AOI1_OUT0 input is selected
+ *  0b100000..AOI1_OUT1 input is selected
+ *  0b100001..AOI1_OUT2 input is selected
+ *  0b100010..AOI1_OUT3 input is selected
+ *  0b100011..Reserved
+ *  0b100100..Reserved
+ *  0b100101..Reserved
+ *  0b100110..Reserved
+ *  0b100111..Reserved
+ *  0b101000..Reserved
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ */
+#define INPUTMUX_LPI2C0_TRIG_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPI2C0_TRIG_INP_SHIFT)) & INPUTMUX_LPI2C0_TRIG_INP_MASK)
+/*! @} */
+
+/*! @name LPI2C1_TRIG - LPI2C1 trigger input connections */
+/*! @{ */
+
+#define INPUTMUX_LPI2C1_TRIG_INP_MASK            (0x3FU)
+#define INPUTMUX_LPI2C1_TRIG_INP_SHIFT           (0U)
+/*! INP - LPI2C1 trigger input connections
+ *  0b000000..Reserved
+ *  0b000001..Reserved
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT0 input is selected
+ *  0b001010..CTimer0_MAT1 input is selected
+ *  0b001011..CTimer1_MAT0 input is selected
+ *  0b001100..CTimer1_MAT1 input is selected
+ *  0b001101..CTimer2_MAT0 input is selected
+ *  0b001110..CTimer2_MAT1 input is selected
+ *  0b001111..LPTMR0 input is selected
+ *  0b010000..Reserved
+ *  0b010001..TRIG_IN0 input is selected
+ *  0b010010..TRIG_IN1 input is selected
+ *  0b010011..TRIG_IN2 input is selected
+ *  0b010100..TRIG_IN3 input is selected
+ *  0b010101..TRIG_IN4 input is selected
+ *  0b010110..TRIG_IN5 input is selected
+ *  0b010111..TRIG_IN6 input is selected
+ *  0b011000..TRIG_IN7 input is selected
+ *  0b011001..GPIO0 Pin Event Trig 0 input is selected
+ *  0b011010..GPIO1 Pin Event Trig 0 input is selected
+ *  0b011011..GPIO2 Pin Event Trig 0 input is selected
+ *  0b011100..GPIO3 Pin Event Trig 0 input is selected
+ *  0b011101..GPIO4 Pin Event Trig 0 input is selected
+ *  0b011110..WUU input is selected
+ *  0b011111..AOI1_OUT0 input is selected
+ *  0b100000..AOI1_OUT1 input is selected
+ *  0b100001..AOI1_OUT2 input is selected
+ *  0b100010..AOI1_OUT3 input is selected
+ *  0b100011..Reserved
+ *  0b100100..Reserved
+ *  0b100101..Reserved
+ *  0b100110..Reserved
+ *  0b100111..Reserved
+ *  0b101000..Reserved
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ */
+#define INPUTMUX_LPI2C1_TRIG_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPI2C1_TRIG_INP_SHIFT)) & INPUTMUX_LPI2C1_TRIG_INP_MASK)
+/*! @} */
+
+/*! @name LPSPI0_TRIG - LPSPI0 trigger input connections */
+/*! @{ */
+
+#define INPUTMUX_LPSPI0_TRIG_INP_MASK            (0x3FU)
+#define INPUTMUX_LPSPI0_TRIG_INP_SHIFT           (0U)
+/*! INP - LPSPI0 trigger input connections
+ *  0b000000..Reserved
+ *  0b000001..Reserved
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP3_OUT input is selected
+ *  0b001001..CTimer0_MAT1 input is selected
+ *  0b001010..CTimer0_MAT2 input is selected
+ *  0b001011..CTimer1_MAT1 input is selected
+ *  0b001100..CTimer1_MAT2 input is selected
+ *  0b001101..CTimer2_MAT1 input is selected
+ *  0b001110..CTimer2_MAT2 input is selected
+ *  0b001111..LPTMR0 input is selected
+ *  0b010000..Reserved
+ *  0b010001..TRIG_IN0 input is selected
+ *  0b010010..TRIG_IN1 input is selected
+ *  0b010011..TRIG_IN2 input is selected
+ *  0b010100..TRIG_IN3 input is selected
+ *  0b010101..TRIG_IN4 input is selected
+ *  0b010110..TRIG_IN5 input is selected
+ *  0b010111..TRIG_IN6 input is selected
+ *  0b011000..TRIG_IN7 input is selected
+ *  0b011001..GPIO0 Pin Event Trig 0 input is selected
+ *  0b011010..GPIO1 Pin Event Trig 0 input is selected
+ *  0b011011..GPIO2 Pin Event Trig 0 input is selected
+ *  0b011100..GPIO3 Pin Event Trig 0 input is selected
+ *  0b011101..GPIO4 Pin Event Trig 0 input is selected
+ *  0b011110..WUU input is selected
+ *  0b011111..AOI1_OUT0 input is selected
+ *  0b100000..AOI1_OUT1 input is selected
+ *  0b100001..AOI1_OUT2 input is selected
+ *  0b100010..AOI1_OUT3 input is selected
+ *  0b100011..Reserved
+ *  0b100100..Reserved
+ *  0b100101..Reserved
+ *  0b100110..Reserved
+ *  0b100111..Reserved
+ *  0b101000..Reserved
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ */
+#define INPUTMUX_LPSPI0_TRIG_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPSPI0_TRIG_INP_SHIFT)) & INPUTMUX_LPSPI0_TRIG_INP_MASK)
+/*! @} */
+
+/*! @name LPSPI1_TRIG - LPSPI1 trigger input connections */
+/*! @{ */
+
+#define INPUTMUX_LPSPI1_TRIG_INP_MASK            (0x3FU)
+#define INPUTMUX_LPSPI1_TRIG_INP_SHIFT           (0U)
+/*! INP - LPSPI1 trigger input connections
+ *  0b000000..Reserved
+ *  0b000001..Reserved
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT1 input is selected
+ *  0b001010..CTimer0_MAT2 input is selected
+ *  0b001011..CTimer1_MAT1 input is selected
+ *  0b001100..CTimer1_MAT2 input is selected
+ *  0b001101..CTimer2_MAT1 input is selected
+ *  0b001110..CTimer2_MAT2 input is selected
+ *  0b001111..LPTMR0 input is selected
+ *  0b010000..Reserved
+ *  0b010001..TRIG_IN0 input is selected
+ *  0b010010..TRIG_IN1 input is selected
+ *  0b010011..TRIG_IN2 input is selected
+ *  0b010100..TRIG_IN3 input is selected
+ *  0b010101..TRIG_IN4 input is selected
+ *  0b010110..TRIG_IN5 input is selected
+ *  0b010111..TRIG_IN6 input is selected
+ *  0b011000..TRIG_IN7 input is selected
+ *  0b011001..GPIO0 Pin Event Trig 0 input is selected
+ *  0b011010..GPIO1 Pin Event Trig 0 input is selected
+ *  0b011011..GPIO2 Pin Event Trig 0 input is selected
+ *  0b011100..GPIO3 Pin Event Trig 0 input is selected
+ *  0b011101..GPIO4 Pin Event Trig 0 input is selected
+ *  0b011110..WUU input is selected
+ *  0b011111..AOI1_OUT0 input is selected
+ *  0b100000..AOI1_OUT1 input is selected
+ *  0b100001..AOI1_OUT2 input is selected
+ *  0b100010..AOI1_OUT3 input is selected
+ *  0b100011..Reserved
+ *  0b100100..Reserved
+ *  0b100101..Reserved
+ *  0b100110..Reserved
+ *  0b100111..Reserved
+ *  0b101000..Reserved
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ */
+#define INPUTMUX_LPSPI1_TRIG_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPSPI1_TRIG_INP_SHIFT)) & INPUTMUX_LPSPI1_TRIG_INP_MASK)
+/*! @} */
+
+/*! @name LPUART0 - LPUART0 trigger input connections */
+/*! @{ */
+
+#define INPUTMUX_LPUART0_INP_MASK                (0x3FU)
+#define INPUTMUX_LPUART0_INP_SHIFT               (0U)
+/*! INP - LPUART0 trigger input connections
+ *  0b000000..Reserved
+ *  0b000001..Reserved
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..LPTMR0 input is selected
+ *  0b010000..Reserved
+ *  0b010001..TRIG_IN0 input is selected
+ *  0b010010..TRIG_IN1 input is selected
+ *  0b010011..TRIG_IN2 input is selected
+ *  0b010100..TRIG_IN3 input is selected
+ *  0b010101..TRIG_IN4 input is selected
+ *  0b010110..TRIG_IN5 input is selected
+ *  0b010111..TRIG_IN6 input is selected
+ *  0b011000..TRIG_IN7 input is selected
+ *  0b011001..TRIG_IN8 input is selected
+ *  0b011010..TRIG_IN9 input is selected
+ *  0b011011..TRIG_IN10 input is selected
+ *  0b011100..TRIG_IN11 input is selected
+ *  0b011101..GPIO0 Pin Event Trig 0 input is selected
+ *  0b011110..GPIO1 Pin Event Trig 0 input is selected
+ *  0b011111..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100000..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100010..WUU selected
+ *  0b100011..Reserved
+ *  0b100100..AOI1_OUT0 input is selected
+ *  0b100101..AOI1_OUT1 input is selected
+ *  0b100110..AOI1_OUT2 input is selected
+ *  0b100111..AOI1_OUT3 input is selected
+ *  0b101000..Reserved
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ */
+#define INPUTMUX_LPUART0_INP(x)                  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART0_INP_SHIFT)) & INPUTMUX_LPUART0_INP_MASK)
+/*! @} */
+
+/*! @name LPUART1 - LPUART1 trigger input connections */
+/*! @{ */
+
+#define INPUTMUX_LPUART1_INP_MASK                (0x3FU)
+#define INPUTMUX_LPUART1_INP_SHIFT               (0U)
+/*! INP - LPUART1 trigger input connections
+ *  0b000000..Reserved
+ *  0b000001..Reserved
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..LPTMR0 input is selected
+ *  0b010000..Reserved
+ *  0b010001..TRIG_IN0 input is selected
+ *  0b010010..TRIG_IN1 input is selected
+ *  0b010011..TRIG_IN2 input is selected
+ *  0b010100..TRIG_IN3 input is selected
+ *  0b010101..TRIG_IN4 input is selected
+ *  0b010110..TRIG_IN5 input is selected
+ *  0b010111..TRIG_IN6 input is selected
+ *  0b011000..TRIG_IN7 input is selected
+ *  0b011001..TRIG_IN8 input is selected
+ *  0b011010..TRIG_IN9 input is selected
+ *  0b011011..TRIG_IN10 input is selected
+ *  0b011100..TRIG_IN11 input is selected
+ *  0b011101..GPIO0 Pin Event Trig 0 input is selected
+ *  0b011110..GPIO1 Pin Event Trig 0 input is selected
+ *  0b011111..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100000..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100010..WUU selected
+ *  0b100011..Reserved
+ *  0b100100..AOI1_OUT0 input is selected
+ *  0b100101..AOI1_OUT1 input is selected
+ *  0b100110..AOI1_OUT2 input is selected
+ *  0b100111..AOI1_OUT3 input is selected
+ *  0b101000..Reserved
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ */
+#define INPUTMUX_LPUART1_INP(x)                  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART1_INP_SHIFT)) & INPUTMUX_LPUART1_INP_MASK)
+/*! @} */
+
+/*! @name LPUART2 - LPUART2 trigger input connections */
+/*! @{ */
+
+#define INPUTMUX_LPUART2_INP_MASK                (0x3FU)
+#define INPUTMUX_LPUART2_INP_SHIFT               (0U)
+/*! INP - LPUART2 trigger input connections
+ *  0b000000..Reserved
+ *  0b000001..Reserved
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..LPTMR0 input is selected
+ *  0b010000..Reserved
+ *  0b010001..TRIG_IN0 input is selected
+ *  0b010010..TRIG_IN1 input is selected
+ *  0b010011..TRIG_IN2 input is selected
+ *  0b010100..TRIG_IN3 input is selected
+ *  0b010101..TRIG_IN4 input is selected
+ *  0b010110..TRIG_IN5 input is selected
+ *  0b010111..TRIG_IN6 input is selected
+ *  0b011000..TRIG_IN7 input is selected
+ *  0b011001..TRIG_IN8 input is selected
+ *  0b011010..TRIG_IN9 input is selected
+ *  0b011011..TRIG_IN10 input is selected
+ *  0b011100..TRIG_IN11 input is selected
+ *  0b011101..GPIO0 Pin Event Trig 0 input is selected
+ *  0b011110..GPIO1 Pin Event Trig 0 input is selected
+ *  0b011111..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100000..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100010..WUU selected
+ *  0b100011..UReserved
+ *  0b100100..AOI1_OUT0 input is selected
+ *  0b100101..AOI1_OUT1 input is selected
+ *  0b100110..AOI1_OUT2 input is selected
+ *  0b100111..AOI1_OUT3 input is selected
+ *  0b101000..Reserved
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ */
+#define INPUTMUX_LPUART2_INP(x)                  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART2_INP_SHIFT)) & INPUTMUX_LPUART2_INP_MASK)
+/*! @} */
+
+/*! @name LPUART3 - LPUART3 trigger input connections */
+/*! @{ */
+
+#define INPUTMUX_LPUART3_INP_MASK                (0x3FU)
+#define INPUTMUX_LPUART3_INP_SHIFT               (0U)
+/*! INP - LPUART3 trigger input connections
+ *  0b000000..Reserved
+ *  0b000001..Reserved
+ *  0b000010..AOI0_OUT0 input is selected
+ *  0b000011..AOI0_OUT1 input is selected
+ *  0b000100..AOI0_OUT2 input is selected
+ *  0b000101..AOI0_OUT3 input is selected
+ *  0b000110..CMP0_OUT input is selected
+ *  0b000111..CMP1_OUT input is selected
+ *  0b001000..CMP2_OUT input is selected
+ *  0b001001..CTimer0_MAT2 input is selected
+ *  0b001010..CTimer0_MAT3 input is selected
+ *  0b001011..CTimer1_MAT2 input is selected
+ *  0b001100..CTimer1_MAT3 input is selected
+ *  0b001101..CTimer2_MAT2 input is selected
+ *  0b001110..CTimer2_MAT3 input is selected
+ *  0b001111..LPTMR0 input is selected
+ *  0b010000..Reserved
+ *  0b010001..TRIG_IN0 input is selected
+ *  0b010010..TRIG_IN1 input is selected
+ *  0b010011..TRIG_IN2 input is selected
+ *  0b010100..TRIG_IN3 input is selected
+ *  0b010101..TRIG_IN4 input is selected
+ *  0b010110..TRIG_IN5 input is selected
+ *  0b010111..TRIG_IN6 input is selected
+ *  0b011000..TRIG_IN7 input is selected
+ *  0b011001..TRIG_IN8 input is selected
+ *  0b011010..TRIG_IN9 input is selected
+ *  0b011011..TRIG_IN10 input is selected
+ *  0b011100..TRIG_IN11 input is selected
+ *  0b011101..GPIO0 Pin Event Trig 0 input is selected
+ *  0b011110..GPIO1 Pin Event Trig 0 input is selected
+ *  0b011111..GPIO2 Pin Event Trig 0 input is selected
+ *  0b100000..GPIO3 Pin Event Trig 0 input is selected
+ *  0b100001..GPIO4 Pin Event Trig 0 input is selected
+ *  0b100010..WUU selected
+ *  0b100011..Reserved
+ *  0b100100..AOI1_OUT0 input is selected
+ *  0b100101..AOI1_OUT1 input is selected
+ *  0b100110..AOI1_OUT2 input is selected
+ *  0b100111..AOI1_OUT3 input is selected
+ *  0b101000..Reserved
+ *  0b101001..Reserved
+ *  0b101010..Reserved
+ *  0b101011..Reserved
+ *  0b101100..Reserved
+ *  0b101101..Reserved
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ */
+#define INPUTMUX_LPUART3_INP(x)                  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART3_INP_SHIFT)) & INPUTMUX_LPUART3_INP_MASK)
+/*! @} */
+
+/*! @name TRIGFIL_PRSC - Trigger filter prescaller */
+/*! @{ */
+
+#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_VAL_MASK (0x3U)
+#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_VAL_SHIFT (0U)
+/*! FILT_SCALE_VAL - Filter Prescaller Value
+ *  0b00..Bypass the clock
+ *  0b01..Divide 2
+ *  0b10..Divide 4
+ *  0b11..Divide 8
+ */
+#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_VAL(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_VAL_SHIFT)) & INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_VAL_MASK)
+
+#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_EN_MASK (0x80000000U)
+#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_EN_SHIFT (31U)
+/*! FILT_SCALE_EN - Enable trigger filter prescaller
+ *  0b0..Disable prescaller
+ *  0b1..Enabled prescaller
+ */
+#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_EN(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_EN_SHIFT)) & INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_EN_MASK)
+/*! @} */
+
+/*! @name TRIGFIL_STAT0 - Trigger filter stat */
+/*! @{ */
+
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN0_VAL_MASK (0x1U)
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN0_VAL_SHIFT (0U)
+/*! TRIG_IN0_VAL - TRIG_IN value
+ *  0b0..TRIG_IN0 is 0
+ *  0b1..TRIG_IN0 is 1
+ */
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN0_VAL(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN0_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN0_VAL_MASK)
+
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN1_VAL_MASK (0x2U)
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN1_VAL_SHIFT (1U)
+/*! TRIG_IN1_VAL - TRIG_IN value
+ *  0b0..TRIG_IN1 is 0
+ *  0b1..TRIG_IN1 is 1
+ */
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN1_VAL(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN1_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN1_VAL_MASK)
+
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN2_VAL_MASK (0x4U)
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN2_VAL_SHIFT (2U)
+/*! TRIG_IN2_VAL - TRIG_IN value
+ *  0b0..TRIG_IN2 is 0
+ *  0b1..TRIG_IN2 is 1
+ */
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN2_VAL(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN2_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN2_VAL_MASK)
+
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN3_VAL_MASK (0x8U)
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN3_VAL_SHIFT (3U)
+/*! TRIG_IN3_VAL - TRIG_IN value
+ *  0b0..TRIG_IN3 is 0
+ *  0b1..TRIG_IN3 is 1
+ */
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN3_VAL(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN3_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN3_VAL_MASK)
+
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN4_VAL_MASK (0x10U)
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN4_VAL_SHIFT (4U)
+/*! TRIG_IN4_VAL - TRIG_IN value
+ *  0b0..TRIG_IN4 is 0
+ *  0b1..TRIG_IN4 is 1
+ */
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN4_VAL(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN4_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN4_VAL_MASK)
+
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN5_VAL_MASK (0x20U)
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN5_VAL_SHIFT (5U)
+/*! TRIG_IN5_VAL - TRIG_IN value
+ *  0b0..TRIG_IN5 is 0
+ *  0b1..TRIG_IN5 is 1
+ */
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN5_VAL(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN5_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN5_VAL_MASK)
+
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN6_VAL_MASK (0x40U)
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN6_VAL_SHIFT (6U)
+/*! TRIG_IN6_VAL - TRIG_IN value
+ *  0b0..TRIG_IN6 is 0
+ *  0b1..TRIG_IN6 is 1
+ */
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN6_VAL(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN6_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN6_VAL_MASK)
+
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN7_VAL_MASK (0x80U)
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN7_VAL_SHIFT (7U)
+/*! TRIG_IN7_VAL - TRIG_IN value
+ *  0b0..TRIG_IN7 is 0
+ *  0b1..TRIG_IN7 is 1
+ */
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN7_VAL(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN7_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN7_VAL_MASK)
+
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN8_VAL_MASK (0x100U)
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN8_VAL_SHIFT (8U)
+/*! TRIG_IN8_VAL - TRIG_IN value
+ *  0b0..TRIG_IN8 is 0
+ *  0b1..TRIG_IN8 is 1
+ */
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN8_VAL(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN8_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN8_VAL_MASK)
+
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN9_VAL_MASK (0x200U)
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN9_VAL_SHIFT (9U)
+/*! TRIG_IN9_VAL - TRIG_IN value
+ *  0b0..TRIG_IN9 is 0
+ *  0b1..TRIG_IN9 is 1
+ */
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN9_VAL(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN9_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN9_VAL_MASK)
+
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN10_VAL_MASK (0x400U)
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN10_VAL_SHIFT (10U)
+/*! TRIG_IN10_VAL - TRIG_IN value
+ *  0b0..TRIG_IN10 is 0
+ *  0b1..TRIG_IN10 is 1
+ */
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN10_VAL(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN10_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN10_VAL_MASK)
+
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN11_VAL_MASK (0x800U)
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN11_VAL_SHIFT (11U)
+/*! TRIG_IN11_VAL - TRIG_IN value
+ *  0b0..TRIG_IN11 is 0
+ *  0b1..TRIG_IN11 is 1
+ */
+#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN11_VAL(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN11_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN11_VAL_MASK)
+/*! @} */
+
+/*! @name TRIGFILP_TRIGFIL - TRIGFIL control */
+/*! @{ */
+
+#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_PER_MASK  (0xFFU)
+#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_PER_SHIFT (0U)
+/*! FILT_PER - Input Filter Sample Period */
+#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_PER(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFILP_TRIGFIL_FILT_PER_SHIFT)) & INPUTMUX_TRIGFILP_TRIGFIL_FILT_PER_MASK)
+
+#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_CNT_MASK  (0x700U)
+#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_CNT_SHIFT (8U)
+/*! FILT_CNT - Input Filter Sample Count */
+#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_CNT(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFILP_TRIGFIL_FILT_CNT_SHIFT)) & INPUTMUX_TRIGFILP_TRIGFIL_FILT_CNT_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_TRIGFILP_TRIGFIL */
+#define INPUTMUX_TRIGFILP_TRIGFIL_COUNT          (12U)
+
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_INPUTMUX_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPCMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPCMP.h
new file mode 100644
index 0000000000..6872b029df
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPCMP.h
@@ -0,0 +1,821 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for LPCMP
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_LPCMP.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for LPCMP
+ *
+ * CMSIS Peripheral Access Layer for LPCMP
+ */
+
+#if !defined(PERI_LPCMP_H_)
+#define PERI_LPCMP_H_                            /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- LPCMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPCMP_Peripheral_Access_Layer LPCMP Peripheral Access Layer
+ * @{
+ */
+
+/** LPCMP - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
+  __IO uint32_t CCR0;                              /**< Comparator Control Register 0, offset: 0x8 */
+  __IO uint32_t CCR1;                              /**< Comparator Control Register 1, offset: 0xC */
+  __IO uint32_t CCR2;                              /**< Comparator Control Register 2, offset: 0x10 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t DCR;                               /**< DAC Control, offset: 0x18 */
+  __IO uint32_t IER;                               /**< Interrupt Enable, offset: 0x1C */
+  __IO uint32_t CSR;                               /**< Comparator Status, offset: 0x20 */
+  __IO uint32_t RRCR0;                             /**< Round Robin Control Register 0, offset: 0x24 */
+  __IO uint32_t RRCR1;                             /**< Round Robin Control Register 1, offset: 0x28 */
+  __IO uint32_t RRCSR;                             /**< Round Robin Control and Status, offset: 0x2C */
+  __IO uint32_t RRSR;                              /**< Round Robin Status, offset: 0x30 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t RRCR2;                             /**< Round Robin Control Register 2, offset: 0x38 */
+} LPCMP_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPCMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPCMP_Register_Masks LPCMP Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID */
+/*! @{ */
+
+#define LPCMP_VERID_FEATURE_MASK                 (0xFFFFU)
+#define LPCMP_VERID_FEATURE_SHIFT                (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000001..Round robin feature
+ */
+#define LPCMP_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_FEATURE_SHIFT)) & LPCMP_VERID_FEATURE_MASK)
+
+#define LPCMP_VERID_MINOR_MASK                   (0xFF0000U)
+#define LPCMP_VERID_MINOR_SHIFT                  (16U)
+/*! MINOR - Minor Version Number */
+#define LPCMP_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MINOR_SHIFT)) & LPCMP_VERID_MINOR_MASK)
+
+#define LPCMP_VERID_MAJOR_MASK                   (0xFF000000U)
+#define LPCMP_VERID_MAJOR_SHIFT                  (24U)
+/*! MAJOR - Major Version Number */
+#define LPCMP_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MAJOR_SHIFT)) & LPCMP_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter */
+/*! @{ */
+
+#define LPCMP_PARAM_DAC_RES_MASK                 (0xFU)
+#define LPCMP_PARAM_DAC_RES_SHIFT                (0U)
+/*! DAC_RES - DAC Resolution
+ *  0b0000..4-bit DAC
+ *  0b0001..6-bit DAC
+ *  0b0010..8-bit DAC
+ *  0b0011..10-bit DAC
+ *  0b0100..12-bit DAC
+ *  0b0101..14-bit DAC
+ *  0b0110..16-bit DAC
+ */
+#define LPCMP_PARAM_DAC_RES(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_PARAM_DAC_RES_SHIFT)) & LPCMP_PARAM_DAC_RES_MASK)
+/*! @} */
+
+/*! @name CCR0 - Comparator Control Register 0 */
+/*! @{ */
+
+#define LPCMP_CCR0_CMP_EN_MASK                   (0x1U)
+#define LPCMP_CCR0_CMP_EN_SHIFT                  (0U)
+/*! CMP_EN - Comparator Enable
+ *  0b0..Disable (The analog logic remains off and consumes no power.)
+ *  0b1..Enable
+ */
+#define LPCMP_CCR0_CMP_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK)
+
+#define LPCMP_CCR0_CMP_STOP_EN_MASK              (0x2U)
+#define LPCMP_CCR0_CMP_STOP_EN_SHIFT             (1U)
+/*! CMP_STOP_EN - Comparator Deep sleep Mode Enable
+ *  0b0..Disables the analog comparator regardless of CMP_EN.
+ *  0b1..Allows CMP_EN to enable the analog comparator.
+ */
+#define LPCMP_CCR0_CMP_STOP_EN(x)                (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_STOP_EN_SHIFT)) & LPCMP_CCR0_CMP_STOP_EN_MASK)
+/*! @} */
+
+/*! @name CCR1 - Comparator Control Register 1 */
+/*! @{ */
+
+#define LPCMP_CCR1_WINDOW_EN_MASK                (0x1U)
+#define LPCMP_CCR1_WINDOW_EN_SHIFT               (0U)
+/*! WINDOW_EN - Windowing Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPCMP_CCR1_WINDOW_EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK)
+
+#define LPCMP_CCR1_SAMPLE_EN_MASK                (0x2U)
+#define LPCMP_CCR1_SAMPLE_EN_SHIFT               (1U)
+/*! SAMPLE_EN - Sampling Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPCMP_CCR1_SAMPLE_EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK)
+
+#define LPCMP_CCR1_DMA_EN_MASK                   (0x4U)
+#define LPCMP_CCR1_DMA_EN_SHIFT                  (2U)
+/*! DMA_EN - DMA Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPCMP_CCR1_DMA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK)
+
+#define LPCMP_CCR1_COUT_INV_MASK                 (0x8U)
+#define LPCMP_CCR1_COUT_INV_SHIFT                (3U)
+/*! COUT_INV - Comparator Invert
+ *  0b0..Do not invert
+ *  0b1..Invert
+ */
+#define LPCMP_CCR1_COUT_INV(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_INV_SHIFT)) & LPCMP_CCR1_COUT_INV_MASK)
+
+#define LPCMP_CCR1_COUT_SEL_MASK                 (0x10U)
+#define LPCMP_CCR1_COUT_SEL_SHIFT                (4U)
+/*! COUT_SEL - Comparator Output Select
+ *  0b0..Use COUT (filtered)
+ *  0b1..Use COUTA (unfiltered)
+ */
+#define LPCMP_CCR1_COUT_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_SEL_SHIFT)) & LPCMP_CCR1_COUT_SEL_MASK)
+
+#define LPCMP_CCR1_COUT_PEN_MASK                 (0x20U)
+#define LPCMP_CCR1_COUT_PEN_SHIFT                (5U)
+/*! COUT_PEN - Comparator Output Pin Enable
+ *  0b0..Not available
+ *  0b1..Available
+ */
+#define LPCMP_CCR1_COUT_PEN(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_PEN_SHIFT)) & LPCMP_CCR1_COUT_PEN_MASK)
+
+#define LPCMP_CCR1_COUTA_OWEN_MASK               (0x40U)
+#define LPCMP_CCR1_COUTA_OWEN_SHIFT              (6U)
+/*! COUTA_OWEN - COUTA_OW Enable
+ *  0b0..COUTA holds the last sampled value.
+ *  0b1..Enables the COUTA signal value to be defined by COUTA_OW.
+ */
+#define LPCMP_CCR1_COUTA_OWEN(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OWEN_SHIFT)) & LPCMP_CCR1_COUTA_OWEN_MASK)
+
+#define LPCMP_CCR1_COUTA_OW_MASK                 (0x80U)
+#define LPCMP_CCR1_COUTA_OW_SHIFT                (7U)
+/*! COUTA_OW - COUTA Output Level for Closed Window
+ *  0b0..COUTA is 0
+ *  0b1..COUTA is 1
+ */
+#define LPCMP_CCR1_COUTA_OW(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OW_SHIFT)) & LPCMP_CCR1_COUTA_OW_MASK)
+
+#define LPCMP_CCR1_WINDOW_INV_MASK               (0x100U)
+#define LPCMP_CCR1_WINDOW_INV_SHIFT              (8U)
+/*! WINDOW_INV - WINDOW/SAMPLE Signal Invert
+ *  0b0..Do not invert
+ *  0b1..Invert
+ */
+#define LPCMP_CCR1_WINDOW_INV(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_INV_SHIFT)) & LPCMP_CCR1_WINDOW_INV_MASK)
+
+#define LPCMP_CCR1_WINDOW_CLS_MASK               (0x200U)
+#define LPCMP_CCR1_WINDOW_CLS_SHIFT              (9U)
+/*! WINDOW_CLS - COUT Event Window Close
+ *  0b0..COUT event cannot close the window
+ *  0b1..COUT event can close the window
+ */
+#define LPCMP_CCR1_WINDOW_CLS(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_CLS_SHIFT)) & LPCMP_CCR1_WINDOW_CLS_MASK)
+
+#define LPCMP_CCR1_EVT_SEL_MASK                  (0xC00U)
+#define LPCMP_CCR1_EVT_SEL_SHIFT                 (10U)
+/*! EVT_SEL - COUT Event Select
+ *  0b00..Rising edge
+ *  0b01..Falling edge
+ *  0b1x..Both edges
+ */
+#define LPCMP_CCR1_EVT_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_SHIFT)) & LPCMP_CCR1_EVT_SEL_MASK)
+
+#define LPCMP_CCR1_FUNC_CLK_SEL_MASK             (0x3000U)
+#define LPCMP_CCR1_FUNC_CLK_SEL_SHIFT            (12U)
+/*! FUNC_CLK_SEL - Functional Clock Source Select
+ *  0b00..Select functional clock source 0
+ *  0b01..Select functional clock source 1
+ *  0b10..Select functional clock source 2
+ *  0b11..Select functional clock source 3
+ */
+#define LPCMP_CCR1_FUNC_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FUNC_CLK_SEL_SHIFT)) & LPCMP_CCR1_FUNC_CLK_SEL_MASK)
+
+#define LPCMP_CCR1_FILT_CNT_MASK                 (0x70000U)
+#define LPCMP_CCR1_FILT_CNT_SHIFT                (16U)
+/*! FILT_CNT - Filter Sample Count
+ *  0b000..Filter is bypassed: COUT = COUTA
+ *  0b001..1 consecutive sample (Comparator output is simply sampled.)
+ *  0b010..2 consecutive samples
+ *  0b011..3 consecutive samples
+ *  0b100..4 consecutive samples
+ *  0b101..5 consecutive samples
+ *  0b110..6 consecutive samples
+ *  0b111..7 consecutive samples
+ */
+#define LPCMP_CCR1_FILT_CNT(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_CNT_SHIFT)) & LPCMP_CCR1_FILT_CNT_MASK)
+
+#define LPCMP_CCR1_FILT_PER_MASK                 (0xFF000000U)
+#define LPCMP_CCR1_FILT_PER_SHIFT                (24U)
+/*! FILT_PER - Filter Sample Period */
+#define LPCMP_CCR1_FILT_PER(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_PER_SHIFT)) & LPCMP_CCR1_FILT_PER_MASK)
+/*! @} */
+
+/*! @name CCR2 - Comparator Control Register 2 */
+/*! @{ */
+
+#define LPCMP_CCR2_CMP_HPMD_MASK                 (0x1U)
+#define LPCMP_CCR2_CMP_HPMD_SHIFT                (0U)
+/*! CMP_HPMD - CMP High Power Mode Select
+ *  0b0..Low power (speed) comparison mode
+ *  0b1..High power (speed) comparison mode
+ */
+#define LPCMP_CCR2_CMP_HPMD(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_HPMD_SHIFT)) & LPCMP_CCR2_CMP_HPMD_MASK)
+
+#define LPCMP_CCR2_CMP_NPMD_MASK                 (0x2U)
+#define LPCMP_CCR2_CMP_NPMD_SHIFT                (1U)
+/*! CMP_NPMD - CMP Nano Power Mode Select
+ *  0b0..Disables CMP Nano power mode. CCR2[CMP_HPMD] determines the mode for the comparator.
+ *  0b1..Enables CMP Nano power mode.
+ */
+#define LPCMP_CCR2_CMP_NPMD(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_NPMD_SHIFT)) & LPCMP_CCR2_CMP_NPMD_MASK)
+
+#define LPCMP_CCR2_HYSTCTR_MASK                  (0x30U)
+#define LPCMP_CCR2_HYSTCTR_SHIFT                 (4U)
+/*! HYSTCTR - Comparator Hysteresis Control
+ *  0b00..Level 0: Analog comparator hysteresis 0 mV.
+ *  0b01..Level 1: Analog comparator hysteresis 10 mV.
+ *  0b10..Level 2: Analog comparator hysteresis 20 mV.
+ *  0b11..Level 3: Analog comparator hysteresis 30 mV.
+ */
+#define LPCMP_CCR2_HYSTCTR(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK)
+
+#define LPCMP_CCR2_PSEL_MASK                     (0x70000U)
+#define LPCMP_CCR2_PSEL_SHIFT                    (16U)
+/*! PSEL - Plus Input MUX Select
+ *  0b000..Input 0p
+ *  0b001..Input 1p
+ *  0b010..Input 2p
+ *  0b011..Input 3p
+ *  0b100..Input 4p
+ *  0b101..Input 5p
+ *  0b110..Reserved
+ *  0b111..Internal DAC output
+ */
+#define LPCMP_CCR2_PSEL(x)                       (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_PSEL_SHIFT)) & LPCMP_CCR2_PSEL_MASK)
+
+#define LPCMP_CCR2_MSEL_MASK                     (0x700000U)
+#define LPCMP_CCR2_MSEL_SHIFT                    (20U)
+/*! MSEL - Minus Input MUX Select
+ *  0b000..Input 0m
+ *  0b001..Input 1m
+ *  0b010..Input 2m
+ *  0b011..Input 3m
+ *  0b100..Input 4m
+ *  0b101..Input 5m
+ *  0b110..Reserved
+ *  0b111..Internal DAC output
+ */
+#define LPCMP_CCR2_MSEL(x)                       (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_MSEL_SHIFT)) & LPCMP_CCR2_MSEL_MASK)
+/*! @} */
+
+/*! @name DCR - DAC Control */
+/*! @{ */
+
+#define LPCMP_DCR_DAC_EN_MASK                    (0x1U)
+#define LPCMP_DCR_DAC_EN_SHIFT                   (0U)
+/*! DAC_EN - DAC Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPCMP_DCR_DAC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK)
+
+#define LPCMP_DCR_DAC_HPMD_MASK                  (0x2U)
+#define LPCMP_DCR_DAC_HPMD_SHIFT                 (1U)
+/*! DAC_HPMD - DAC High Power Mode
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPCMP_DCR_DAC_HPMD(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK)
+
+#define LPCMP_DCR_VRSEL_MASK                     (0x100U)
+#define LPCMP_DCR_VRSEL_SHIFT                    (8U)
+/*! VRSEL - DAC Reference High Voltage Source Select
+ *  0b0..VREFH0
+ *  0b1..VREFH1
+ */
+#define LPCMP_DCR_VRSEL(x)                       (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK)
+
+#define LPCMP_DCR_DAC_DATA_MASK                  (0xFF0000U)
+#define LPCMP_DCR_DAC_DATA_SHIFT                 (16U)
+/*! DAC_DATA - DAC Output Voltage Select */
+#define LPCMP_DCR_DAC_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_DATA_SHIFT)) & LPCMP_DCR_DAC_DATA_MASK)
+/*! @} */
+
+/*! @name IER - Interrupt Enable */
+/*! @{ */
+
+#define LPCMP_IER_CFR_IE_MASK                    (0x1U)
+#define LPCMP_IER_CFR_IE_SHIFT                   (0U)
+/*! CFR_IE - Comparator Flag Rising Interrupt Enable
+ *  0b0..Disables the comparator flag rising interrupt.
+ *  0b1..Enables the comparator flag rising interrupt when CFR is set.
+ */
+#define LPCMP_IER_CFR_IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFR_IE_SHIFT)) & LPCMP_IER_CFR_IE_MASK)
+
+#define LPCMP_IER_CFF_IE_MASK                    (0x2U)
+#define LPCMP_IER_CFF_IE_SHIFT                   (1U)
+/*! CFF_IE - Comparator Flag Falling Interrupt Enable
+ *  0b0..Disables the comparator flag falling interrupt.
+ *  0b1..Enables the comparator flag falling interrupt when CFF is set.
+ */
+#define LPCMP_IER_CFF_IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFF_IE_SHIFT)) & LPCMP_IER_CFF_IE_MASK)
+
+#define LPCMP_IER_RRF_IE_MASK                    (0x4U)
+#define LPCMP_IER_RRF_IE_SHIFT                   (2U)
+/*! RRF_IE - Round-Robin Flag Interrupt Enable
+ *  0b0..Disables the round-robin flag interrupt.
+ *  0b1..Enables the round-robin flag interrupt when the comparison result changes for a given channel.
+ */
+#define LPCMP_IER_RRF_IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_RRF_IE_SHIFT)) & LPCMP_IER_RRF_IE_MASK)
+/*! @} */
+
+/*! @name CSR - Comparator Status */
+/*! @{ */
+
+#define LPCMP_CSR_CFR_MASK                       (0x1U)
+#define LPCMP_CSR_CFR_SHIFT                      (0U)
+/*! CFR - Analog Comparator Flag Rising
+ *  0b0..Not detected
+ *  0b1..Detected
+ */
+#define LPCMP_CSR_CFR(x)                         (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFR_SHIFT)) & LPCMP_CSR_CFR_MASK)
+
+#define LPCMP_CSR_CFF_MASK                       (0x2U)
+#define LPCMP_CSR_CFF_SHIFT                      (1U)
+/*! CFF - Analog Comparator Flag Falling
+ *  0b0..Not detected
+ *  0b1..Detected
+ */
+#define LPCMP_CSR_CFF(x)                         (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFF_SHIFT)) & LPCMP_CSR_CFF_MASK)
+
+#define LPCMP_CSR_RRF_MASK                       (0x4U)
+#define LPCMP_CSR_RRF_SHIFT                      (2U)
+/*! RRF - Round-Robin Flag
+ *  0b0..Not detected
+ *  0b1..Detected
+ */
+#define LPCMP_CSR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_RRF_SHIFT)) & LPCMP_CSR_RRF_MASK)
+
+#define LPCMP_CSR_COUT_MASK                      (0x100U)
+#define LPCMP_CSR_COUT_SHIFT                     (8U)
+/*! COUT - Analog Comparator Output */
+#define LPCMP_CSR_COUT(x)                        (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_COUT_SHIFT)) & LPCMP_CSR_COUT_MASK)
+/*! @} */
+
+/*! @name RRCR0 - Round Robin Control Register 0 */
+/*! @{ */
+
+#define LPCMP_RRCR0_RR_EN_MASK                   (0x1U)
+#define LPCMP_RRCR0_RR_EN_SHIFT                  (0U)
+/*! RR_EN - Round-Robin Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPCMP_RRCR0_RR_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
+
+#define LPCMP_RRCR0_RR_TRG_SEL_MASK              (0x2U)
+#define LPCMP_RRCR0_RR_TRG_SEL_SHIFT             (1U)
+/*! RR_TRG_SEL - Round-Robin Trigger Select
+ *  0b0..External trigger
+ *  0b1..Internal trigger
+ */
+#define LPCMP_RRCR0_RR_TRG_SEL(x)                (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_TRG_SEL_SHIFT)) & LPCMP_RRCR0_RR_TRG_SEL_MASK)
+
+#define LPCMP_RRCR0_RR_EXTTRG_SEL_MASK           (0x3CU)
+#define LPCMP_RRCR0_RR_EXTTRG_SEL_SHIFT          (2U)
+/*! RR_EXTTRG_SEL - External Trigger Source Select
+ *  0b0000..Select external trigger source 0
+ *  0b0001..Select external trigger source 1
+ *  0b0010..Select external trigger source 2
+ *  0b0011..Select external trigger source 3
+ *  0b0100..Select external trigger source 4
+ *  0b0101..Select external trigger source 5
+ *  0b0110..Select external trigger source 6
+ *  0b0111..Select external trigger source 7
+ *  0b1000..Select external trigger source 8
+ *  0b1001..Select external trigger source 9
+ *  0b1010..Select external trigger source 10
+ *  0b1011..Select external trigger source 11
+ *  0b1100..Select external trigger source 12
+ *  0b1101..Select external trigger source 13
+ *  0b1110..Select external trigger source 14
+ *  0b1111..Select external trigger source 15
+ */
+#define LPCMP_RRCR0_RR_EXTTRG_SEL(x)             (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EXTTRG_SEL_SHIFT)) & LPCMP_RRCR0_RR_EXTTRG_SEL_MASK)
+
+#define LPCMP_RRCR0_RR_NSAM_MASK                 (0x300U)
+#define LPCMP_RRCR0_RR_NSAM_SHIFT                (8U)
+/*! RR_NSAM - Number of Sample Clocks
+ *  0b00..0 clock
+ *  0b01..1 clock
+ *  0b10..2 clocks
+ *  0b11..3 clocks
+ */
+#define LPCMP_RRCR0_RR_NSAM(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCMP_RRCR0_RR_NSAM_MASK)
+
+#define LPCMP_RRCR0_RR_CLK_SEL_MASK              (0x3000U)
+#define LPCMP_RRCR0_RR_CLK_SEL_SHIFT             (12U)
+/*! RR_CLK_SEL - Round Robin Clock Source Select
+ *  0b00..Select Round Robin clock Source 0
+ *  0b01..Select Round Robin clock Source 1
+ *  0b10..Select Round Robin clock Source 2
+ *  0b11..Select Round Robin clock Source 3
+ */
+#define LPCMP_RRCR0_RR_CLK_SEL(x)                (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_CLK_SEL_SHIFT)) & LPCMP_RRCR0_RR_CLK_SEL_MASK)
+
+#define LPCMP_RRCR0_RR_INITMOD_MASK              (0x3F0000U)
+#define LPCMP_RRCR0_RR_INITMOD_SHIFT             (16U)
+/*! RR_INITMOD - Initialization Delay Modulus
+ *  0b000000..63 cycles (same as 111111b)
+ *  0b000001-0b111111..1 to 63 cycles
+ */
+#define LPCMP_RRCR0_RR_INITMOD(x)                (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_INITMOD_SHIFT)) & LPCMP_RRCR0_RR_INITMOD_MASK)
+
+#define LPCMP_RRCR0_RR_SAMPLE_CNT_MASK           (0xF000000U)
+#define LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT          (24U)
+/*! RR_SAMPLE_CNT - Number of Sample for One Channel
+ *  0b0000..1 samples
+ *  0b0001..2 samples
+ *  0b0010..3 samples
+ *  0b0011..4 samples
+ *  0b0100..5 samples
+ *  0b0101..6 samples
+ *  0b0110..7 samples
+ *  0b0111..8 samples
+ *  0b1000..9 samples
+ *  0b1001..10 samples
+ *  0b1010..11 samples
+ *  0b1011..12 samples
+ *  0b1100..13 samples
+ *  0b1101..14 samples
+ *  0b1110..15 samples
+ *  0b1111..16 samples
+ */
+#define LPCMP_RRCR0_RR_SAMPLE_CNT(x)             (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_CNT_MASK)
+
+#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK     (0xF0000000U)
+#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT    (28U)
+/*! RR_SAMPLE_THRESHOLD - Sample Time Threshold
+ *  0b0000..At least 1 sampled "1", the final result is "1"
+ *  0b0001..At least 2 sampled "1", the final result is "1"
+ *  0b0010..At least 3 sampled "1", the final result is "1"
+ *  0b0011..At least 4 sampled "1", the final result is "1"
+ *  0b0100..At least 5 sampled "1", the final result is "1"
+ *  0b0101..At least 6 sampled "1", the final result is "1"
+ *  0b0110..At least 7 sampled "1", the final result is "1"
+ *  0b0111..At least 8 sampled "1", the final result is "1"
+ *  0b1000..At least 9 sampled "1", the final result is "1"
+ *  0b1001..At least 10 sampled "1", the final result is "1"
+ *  0b1010..At least 11 sampled "1", the final result is "1"
+ *  0b1011..At least 12 sampled "1", the final result is "1"
+ *  0b1100..At least 13 sampled "1", the final result is "1"
+ *  0b1101..At least 14 sampled "1", the final result is "1"
+ *  0b1110..At least 15 sampled "1", the final result is "1"
+ *  0b1111..At least 16 sampled "1", the final result is "1"
+ */
+#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD(x)       (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK)
+/*! @} */
+
+/*! @name RRCR1 - Round Robin Control Register 1 */
+/*! @{ */
+
+#define LPCMP_RRCR1_RR_CH0EN_MASK                (0x1U)
+#define LPCMP_RRCR1_RR_CH0EN_SHIFT               (0U)
+/*! RR_CH0EN - Channel 0 Input Enable in Trigger Mode
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPCMP_RRCR1_RR_CH0EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
+
+#define LPCMP_RRCR1_RR_CH1EN_MASK                (0x2U)
+#define LPCMP_RRCR1_RR_CH1EN_SHIFT               (1U)
+/*! RR_CH1EN - Channel 1 Input Enable in Trigger Mode
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPCMP_RRCR1_RR_CH1EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH1EN_SHIFT)) & LPCMP_RRCR1_RR_CH1EN_MASK)
+
+#define LPCMP_RRCR1_RR_CH2EN_MASK                (0x4U)
+#define LPCMP_RRCR1_RR_CH2EN_SHIFT               (2U)
+/*! RR_CH2EN - Channel 2 Input Enable in Trigger Mode
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPCMP_RRCR1_RR_CH2EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH2EN_SHIFT)) & LPCMP_RRCR1_RR_CH2EN_MASK)
+
+#define LPCMP_RRCR1_RR_CH3EN_MASK                (0x8U)
+#define LPCMP_RRCR1_RR_CH3EN_SHIFT               (3U)
+/*! RR_CH3EN - Channel 3 Input Enable in Trigger Mode
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPCMP_RRCR1_RR_CH3EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH3EN_SHIFT)) & LPCMP_RRCR1_RR_CH3EN_MASK)
+
+#define LPCMP_RRCR1_RR_CH4EN_MASK                (0x10U)
+#define LPCMP_RRCR1_RR_CH4EN_SHIFT               (4U)
+/*! RR_CH4EN - Channel 4 Input Enable in Trigger Mode
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPCMP_RRCR1_RR_CH4EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH4EN_SHIFT)) & LPCMP_RRCR1_RR_CH4EN_MASK)
+
+#define LPCMP_RRCR1_RR_CH5EN_MASK                (0x20U)
+#define LPCMP_RRCR1_RR_CH5EN_SHIFT               (5U)
+/*! RR_CH5EN - Channel 5 Input Enable in Trigger Mode
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPCMP_RRCR1_RR_CH5EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH5EN_SHIFT)) & LPCMP_RRCR1_RR_CH5EN_MASK)
+
+#define LPCMP_RRCR1_RR_CH6EN_MASK                (0x40U)
+#define LPCMP_RRCR1_RR_CH6EN_SHIFT               (6U)
+/*! RR_CH6EN - Channel 6 Input Enable in Trigger Mode
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPCMP_RRCR1_RR_CH6EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH6EN_SHIFT)) & LPCMP_RRCR1_RR_CH6EN_MASK)
+
+#define LPCMP_RRCR1_RR_CH7EN_MASK                (0x80U)
+#define LPCMP_RRCR1_RR_CH7EN_SHIFT               (7U)
+/*! RR_CH7EN - Channel 7 Input Enable in Trigger Mode
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPCMP_RRCR1_RR_CH7EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH7EN_SHIFT)) & LPCMP_RRCR1_RR_CH7EN_MASK)
+
+#define LPCMP_RRCR1_FIXP_MASK                    (0x10000U)
+#define LPCMP_RRCR1_FIXP_SHIFT                   (16U)
+/*! FIXP - Fixed Port
+ *  0b0..Fix the plus port. Sweep only the inputs to the minus port.
+ *  0b1..Fix the minus port. Sweep only the inputs to the plus port.
+ */
+#define LPCMP_RRCR1_FIXP(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXP_SHIFT)) & LPCMP_RRCR1_FIXP_MASK)
+
+#define LPCMP_RRCR1_FIXCH_MASK                   (0x700000U)
+#define LPCMP_RRCR1_FIXCH_SHIFT                  (20U)
+/*! FIXCH - Fixed Channel Select
+ *  0b000..Channel 0
+ *  0b001..Channel 1
+ *  0b010..Channel 2
+ *  0b011..Channel 3
+ *  0b100..Channel 4
+ *  0b101..Channel 5
+ *  0b110..Channel 6
+ *  0b111..Channel 7
+ */
+#define LPCMP_RRCR1_FIXCH(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXCH_SHIFT)) & LPCMP_RRCR1_FIXCH_MASK)
+/*! @} */
+
+/*! @name RRCSR - Round Robin Control and Status */
+/*! @{ */
+
+#define LPCMP_RRCSR_RR_CH0OUT_MASK               (0x1U)
+#define LPCMP_RRCSR_RR_CH0OUT_SHIFT              (0U)
+/*! RR_CH0OUT - Comparison Result for Channel 0 */
+#define LPCMP_RRCSR_RR_CH0OUT(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH0OUT_SHIFT)) & LPCMP_RRCSR_RR_CH0OUT_MASK)
+
+#define LPCMP_RRCSR_RR_CH1OUT_MASK               (0x2U)
+#define LPCMP_RRCSR_RR_CH1OUT_SHIFT              (1U)
+/*! RR_CH1OUT - Comparison Result for Channel 1 */
+#define LPCMP_RRCSR_RR_CH1OUT(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH1OUT_SHIFT)) & LPCMP_RRCSR_RR_CH1OUT_MASK)
+
+#define LPCMP_RRCSR_RR_CH2OUT_MASK               (0x4U)
+#define LPCMP_RRCSR_RR_CH2OUT_SHIFT              (2U)
+/*! RR_CH2OUT - Comparison Result for Channel 2 */
+#define LPCMP_RRCSR_RR_CH2OUT(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH2OUT_SHIFT)) & LPCMP_RRCSR_RR_CH2OUT_MASK)
+
+#define LPCMP_RRCSR_RR_CH3OUT_MASK               (0x8U)
+#define LPCMP_RRCSR_RR_CH3OUT_SHIFT              (3U)
+/*! RR_CH3OUT - Comparison Result for Channel 3 */
+#define LPCMP_RRCSR_RR_CH3OUT(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH3OUT_SHIFT)) & LPCMP_RRCSR_RR_CH3OUT_MASK)
+
+#define LPCMP_RRCSR_RR_CH4OUT_MASK               (0x10U)
+#define LPCMP_RRCSR_RR_CH4OUT_SHIFT              (4U)
+/*! RR_CH4OUT - Comparison Result for Channel 4 */
+#define LPCMP_RRCSR_RR_CH4OUT(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH4OUT_SHIFT)) & LPCMP_RRCSR_RR_CH4OUT_MASK)
+
+#define LPCMP_RRCSR_RR_CH5OUT_MASK               (0x20U)
+#define LPCMP_RRCSR_RR_CH5OUT_SHIFT              (5U)
+/*! RR_CH5OUT - Comparison Result for Channel 5 */
+#define LPCMP_RRCSR_RR_CH5OUT(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH5OUT_SHIFT)) & LPCMP_RRCSR_RR_CH5OUT_MASK)
+
+#define LPCMP_RRCSR_RR_CH6OUT_MASK               (0x40U)
+#define LPCMP_RRCSR_RR_CH6OUT_SHIFT              (6U)
+/*! RR_CH6OUT - Comparison Result for Channel 6 */
+#define LPCMP_RRCSR_RR_CH6OUT(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH6OUT_SHIFT)) & LPCMP_RRCSR_RR_CH6OUT_MASK)
+
+#define LPCMP_RRCSR_RR_CH7OUT_MASK               (0x80U)
+#define LPCMP_RRCSR_RR_CH7OUT_SHIFT              (7U)
+/*! RR_CH7OUT - Comparison Result for Channel 7 */
+#define LPCMP_RRCSR_RR_CH7OUT(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH7OUT_SHIFT)) & LPCMP_RRCSR_RR_CH7OUT_MASK)
+/*! @} */
+
+/*! @name RRSR - Round Robin Status */
+/*! @{ */
+
+#define LPCMP_RRSR_RR_CH0F_MASK                  (0x1U)
+#define LPCMP_RRSR_RR_CH0F_SHIFT                 (0U)
+/*! RR_CH0F - Channel 0 Input Changed Flag
+ *  0b0..No different
+ *  0b1..Different
+ */
+#define LPCMP_RRSR_RR_CH0F(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH0F_SHIFT)) & LPCMP_RRSR_RR_CH0F_MASK)
+
+#define LPCMP_RRSR_RR_CH1F_MASK                  (0x2U)
+#define LPCMP_RRSR_RR_CH1F_SHIFT                 (1U)
+/*! RR_CH1F - Channel 1 Input Changed Flag
+ *  0b0..No different
+ *  0b1..Different
+ */
+#define LPCMP_RRSR_RR_CH1F(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH1F_SHIFT)) & LPCMP_RRSR_RR_CH1F_MASK)
+
+#define LPCMP_RRSR_RR_CH2F_MASK                  (0x4U)
+#define LPCMP_RRSR_RR_CH2F_SHIFT                 (2U)
+/*! RR_CH2F - Channel 2 Input Changed Flag
+ *  0b0..No different
+ *  0b1..Different
+ */
+#define LPCMP_RRSR_RR_CH2F(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH2F_SHIFT)) & LPCMP_RRSR_RR_CH2F_MASK)
+
+#define LPCMP_RRSR_RR_CH3F_MASK                  (0x8U)
+#define LPCMP_RRSR_RR_CH3F_SHIFT                 (3U)
+/*! RR_CH3F - Channel 3 Input Changed Flag
+ *  0b0..No different
+ *  0b1..Different
+ */
+#define LPCMP_RRSR_RR_CH3F(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH3F_SHIFT)) & LPCMP_RRSR_RR_CH3F_MASK)
+
+#define LPCMP_RRSR_RR_CH4F_MASK                  (0x10U)
+#define LPCMP_RRSR_RR_CH4F_SHIFT                 (4U)
+/*! RR_CH4F - Channel 4 Input Changed Flag
+ *  0b0..No different
+ *  0b1..Different
+ */
+#define LPCMP_RRSR_RR_CH4F(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH4F_SHIFT)) & LPCMP_RRSR_RR_CH4F_MASK)
+
+#define LPCMP_RRSR_RR_CH5F_MASK                  (0x20U)
+#define LPCMP_RRSR_RR_CH5F_SHIFT                 (5U)
+/*! RR_CH5F - Channel 5 Input Changed Flag
+ *  0b0..No different
+ *  0b1..Different
+ */
+#define LPCMP_RRSR_RR_CH5F(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH5F_SHIFT)) & LPCMP_RRSR_RR_CH5F_MASK)
+
+#define LPCMP_RRSR_RR_CH6F_MASK                  (0x40U)
+#define LPCMP_RRSR_RR_CH6F_SHIFT                 (6U)
+/*! RR_CH6F - Channel 6 Input Changed Flag
+ *  0b0..No different
+ *  0b1..Different
+ */
+#define LPCMP_RRSR_RR_CH6F(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH6F_SHIFT)) & LPCMP_RRSR_RR_CH6F_MASK)
+
+#define LPCMP_RRSR_RR_CH7F_MASK                  (0x80U)
+#define LPCMP_RRSR_RR_CH7F_SHIFT                 (7U)
+/*! RR_CH7F - Channel 7 Input Changed Flag
+ *  0b0..No different
+ *  0b1..Different
+ */
+#define LPCMP_RRSR_RR_CH7F(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH7F_SHIFT)) & LPCMP_RRSR_RR_CH7F_MASK)
+/*! @} */
+
+/*! @name RRCR2 - Round Robin Control Register 2 */
+/*! @{ */
+
+#define LPCMP_RRCR2_RR_TIMER_RELOAD_MASK         (0xFFFFFFFU)
+#define LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT        (0U)
+/*! RR_TIMER_RELOAD - Number of Sample Clocks */
+#define LPCMP_RRCR2_RR_TIMER_RELOAD(x)           (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT)) & LPCMP_RRCR2_RR_TIMER_RELOAD_MASK)
+
+#define LPCMP_RRCR2_RR_TIMER_EN_MASK             (0x80000000U)
+#define LPCMP_RRCR2_RR_TIMER_EN_SHIFT            (31U)
+/*! RR_TIMER_EN - Round-Robin Internal Timer Enable
+ *  0b0..Disables
+ *  0b1..Enables
+ */
+#define LPCMP_RRCR2_RR_TIMER_EN(x)               (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_EN_SHIFT)) & LPCMP_RRCR2_RR_TIMER_EN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPCMP_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group LPCMP_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_LPCMP_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPI2C.h
new file mode 100644
index 0000000000..d09c1db503
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPI2C.h
@@ -0,0 +1,1428 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for LPI2C
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_LPI2C.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for LPI2C
+ *
+ * CMSIS Peripheral Access Layer for LPI2C
+ */
+
+#if !defined(PERI_LPI2C_H_)
+#define PERI_LPI2C_H_                            /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- LPI2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
+ * @{
+ */
+
+/** LPI2C - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t MCR;                               /**< Controller Control, offset: 0x10 */
+  __IO uint32_t MSR;                               /**< Controller Status, offset: 0x14 */
+  __IO uint32_t MIER;                              /**< Controller Interrupt Enable, offset: 0x18 */
+  __IO uint32_t MDER;                              /**< Controller DMA Enable, offset: 0x1C */
+  __IO uint32_t MCFGR0;                            /**< Controller Configuration 0, offset: 0x20 */
+  __IO uint32_t MCFGR1;                            /**< Controller Configuration 1, offset: 0x24 */
+  __IO uint32_t MCFGR2;                            /**< Controller Configuration 2, offset: 0x28 */
+  __IO uint32_t MCFGR3;                            /**< Controller Configuration 3, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t MDMR;                              /**< Controller Data Match, offset: 0x40 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t MCCR0;                             /**< Controller Clock Configuration 0, offset: 0x48 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t MCCR1;                             /**< Controller Clock Configuration 1, offset: 0x50 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t MFCR;                              /**< Controller FIFO Control, offset: 0x58 */
+  __I  uint32_t MFSR;                              /**< Controller FIFO Status, offset: 0x5C */
+  __O  uint32_t MTDR;                              /**< Controller Transmit Data, offset: 0x60 */
+       uint8_t RESERVED_5[12];
+  __I  uint32_t MRDR;                              /**< Controller Receive Data, offset: 0x70 */
+       uint8_t RESERVED_6[4];
+  __I  uint32_t MRDROR;                            /**< Controller Receive Data Read Only, offset: 0x78 */
+       uint8_t RESERVED_7[148];
+  __IO uint32_t SCR;                               /**< Target Control, offset: 0x110 */
+  __IO uint32_t SSR;                               /**< Target Status, offset: 0x114 */
+  __IO uint32_t SIER;                              /**< Target Interrupt Enable, offset: 0x118 */
+  __IO uint32_t SDER;                              /**< Target DMA Enable, offset: 0x11C */
+  __IO uint32_t SCFGR0;                            /**< Target Configuration 0, offset: 0x120 */
+  __IO uint32_t SCFGR1;                            /**< Target Configuration 1, offset: 0x124 */
+  __IO uint32_t SCFGR2;                            /**< Target Configuration 2, offset: 0x128 */
+       uint8_t RESERVED_8[20];
+  __IO uint32_t SAMR;                              /**< Target Address Match, offset: 0x140 */
+       uint8_t RESERVED_9[12];
+  __I  uint32_t SASR;                              /**< Target Address Status, offset: 0x150 */
+  __IO uint32_t STAR;                              /**< Target Transmit ACK, offset: 0x154 */
+       uint8_t RESERVED_10[8];
+  __O  uint32_t STDR;                              /**< Target Transmit Data, offset: 0x160 */
+       uint8_t RESERVED_11[12];
+  __I  uint32_t SRDR;                              /**< Target Receive Data, offset: 0x170 */
+       uint8_t RESERVED_12[4];
+  __I  uint32_t SRDROR;                            /**< Target Receive Data Read Only, offset: 0x178 */
+} LPI2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPI2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID */
+/*! @{ */
+
+#define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
+#define LPI2C_VERID_FEATURE_SHIFT                (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000010..Controller only, with standard feature set
+ *  0b0000000000000011..Controller and target, with standard feature set
+ */
+#define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
+
+#define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
+#define LPI2C_VERID_MINOR_SHIFT                  (16U)
+/*! MINOR - Minor Version Number */
+#define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
+
+#define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
+#define LPI2C_VERID_MAJOR_SHIFT                  (24U)
+/*! MAJOR - Major Version Number */
+#define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter */
+/*! @{ */
+
+#define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
+#define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
+/*! MTXFIFO - Controller Transmit FIFO Size */
+#define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
+
+#define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
+#define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
+/*! MRXFIFO - Controller Receive FIFO Size */
+#define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
+/*! @} */
+
+/*! @name MCR - Controller Control */
+/*! @{ */
+
+#define LPI2C_MCR_MEN_MASK                       (0x1U)
+#define LPI2C_MCR_MEN_SHIFT                      (0U)
+/*! MEN - Controller Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
+
+#define LPI2C_MCR_RST_MASK                       (0x2U)
+#define LPI2C_MCR_RST_SHIFT                      (1U)
+/*! RST - Software Reset
+ *  0b0..No effect
+ *  0b1..Reset
+ */
+#define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
+
+#define LPI2C_MCR_DOZEN_MASK                     (0x4U)
+#define LPI2C_MCR_DOZEN_SHIFT                    (2U)
+/*! DOZEN - Doze Mode Enable
+ *  0b0..Enable
+ *  0b1..Disable
+ */
+#define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
+
+#define LPI2C_MCR_DBGEN_MASK                     (0x8U)
+#define LPI2C_MCR_DBGEN_SHIFT                    (3U)
+/*! DBGEN - Debug Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
+
+#define LPI2C_MCR_RTF_MASK                       (0x100U)
+#define LPI2C_MCR_RTF_SHIFT                      (8U)
+/*! RTF - Reset Transmit FIFO
+ *  0b0..No effect
+ *  0b1..Reset transmit FIFO
+ */
+#define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
+
+#define LPI2C_MCR_RRF_MASK                       (0x200U)
+#define LPI2C_MCR_RRF_SHIFT                      (9U)
+/*! RRF - Reset Receive FIFO
+ *  0b0..No effect
+ *  0b1..Reset receive FIFO
+ */
+#define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
+/*! @} */
+
+/*! @name MSR - Controller Status */
+/*! @{ */
+
+#define LPI2C_MSR_TDF_MASK                       (0x1U)
+#define LPI2C_MSR_TDF_SHIFT                      (0U)
+/*! TDF - Transmit Data Flag
+ *  0b0..Transmit data not requested
+ *  0b1..Transmit data requested
+ */
+#define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
+
+#define LPI2C_MSR_RDF_MASK                       (0x2U)
+#define LPI2C_MSR_RDF_SHIFT                      (1U)
+/*! RDF - Receive Data Flag
+ *  0b0..Receive data not ready
+ *  0b1..Receive data ready
+ */
+#define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
+
+#define LPI2C_MSR_EPF_MASK                       (0x100U)
+#define LPI2C_MSR_EPF_SHIFT                      (8U)
+/*! EPF - End Packet Flag
+ *  0b0..No Stop or repeated Start generated
+ *  0b0..No effect
+ *  0b1..Clear the flag
+ *  0b1..Stop or repeated Start generated
+ */
+#define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
+
+#define LPI2C_MSR_SDF_MASK                       (0x200U)
+#define LPI2C_MSR_SDF_SHIFT                      (9U)
+/*! SDF - Stop Detect Flag
+ *  0b0..No Stop condition generated
+ *  0b0..No effect
+ *  0b1..Clear the flag
+ *  0b1..Stop condition generated
+ */
+#define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
+
+#define LPI2C_MSR_NDF_MASK                       (0x400U)
+#define LPI2C_MSR_NDF_SHIFT                      (10U)
+/*! NDF - NACK Detect Flag
+ *  0b0..No effect
+ *  0b0..No unexpected NACK detected
+ *  0b1..Clear the flag
+ *  0b1..Unexpected NACK detected
+ */
+#define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
+
+#define LPI2C_MSR_ALF_MASK                       (0x800U)
+#define LPI2C_MSR_ALF_SHIFT                      (11U)
+/*! ALF - Arbitration Lost Flag
+ *  0b0..Controller did not lose arbitration
+ *  0b0..No effect
+ *  0b1..Clear the flag
+ *  0b1..Controller lost arbitration
+ */
+#define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
+
+#define LPI2C_MSR_FEF_MASK                       (0x1000U)
+#define LPI2C_MSR_FEF_SHIFT                      (12U)
+/*! FEF - FIFO Error Flag
+ *  0b0..No FIFO error
+ *  0b0..No effect
+ *  0b1..Clear the flag
+ *  0b1..FIFO error
+ */
+#define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
+
+#define LPI2C_MSR_PLTF_MASK                      (0x2000U)
+#define LPI2C_MSR_PLTF_SHIFT                     (13U)
+/*! PLTF - Pin Low Timeout Flag
+ *  0b0..No effect
+ *  0b0..Pin low timeout did not occur
+ *  0b1..Clear the flag
+ *  0b1..Pin low timeout occurred
+ */
+#define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
+
+#define LPI2C_MSR_DMF_MASK                       (0x4000U)
+#define LPI2C_MSR_DMF_SHIFT                      (14U)
+/*! DMF - Data Match Flag
+ *  0b0..Matching data not received
+ *  0b0..No effect
+ *  0b1..Clear the flag
+ *  0b1..Matching data received
+ */
+#define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
+
+#define LPI2C_MSR_STF_MASK                       (0x8000U)
+#define LPI2C_MSR_STF_SHIFT                      (15U)
+/*! STF - Start Flag
+ *  0b0..No effect
+ *  0b0..Start condition not detected
+ *  0b1..Clear the flag
+ *  0b1..Start condition detected
+ */
+#define LPI2C_MSR_STF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK)
+
+#define LPI2C_MSR_MBF_MASK                       (0x1000000U)
+#define LPI2C_MSR_MBF_SHIFT                      (24U)
+/*! MBF - Controller Busy Flag
+ *  0b0..Idle
+ *  0b1..Busy
+ */
+#define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
+
+#define LPI2C_MSR_BBF_MASK                       (0x2000000U)
+#define LPI2C_MSR_BBF_SHIFT                      (25U)
+/*! BBF - Bus Busy Flag
+ *  0b0..Idle
+ *  0b1..Busy
+ */
+#define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
+/*! @} */
+
+/*! @name MIER - Controller Interrupt Enable */
+/*! @{ */
+
+#define LPI2C_MIER_TDIE_MASK                     (0x1U)
+#define LPI2C_MIER_TDIE_SHIFT                    (0U)
+/*! TDIE - Transmit Data Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
+
+#define LPI2C_MIER_RDIE_MASK                     (0x2U)
+#define LPI2C_MIER_RDIE_SHIFT                    (1U)
+/*! RDIE - Receive Data Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
+
+#define LPI2C_MIER_EPIE_MASK                     (0x100U)
+#define LPI2C_MIER_EPIE_SHIFT                    (8U)
+/*! EPIE - End Packet Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
+
+#define LPI2C_MIER_SDIE_MASK                     (0x200U)
+#define LPI2C_MIER_SDIE_SHIFT                    (9U)
+/*! SDIE - Stop Detect Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
+
+#define LPI2C_MIER_NDIE_MASK                     (0x400U)
+#define LPI2C_MIER_NDIE_SHIFT                    (10U)
+/*! NDIE - NACK Detect Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
+
+#define LPI2C_MIER_ALIE_MASK                     (0x800U)
+#define LPI2C_MIER_ALIE_SHIFT                    (11U)
+/*! ALIE - Arbitration Lost Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
+
+#define LPI2C_MIER_FEIE_MASK                     (0x1000U)
+#define LPI2C_MIER_FEIE_SHIFT                    (12U)
+/*! FEIE - FIFO Error Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
+
+#define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
+#define LPI2C_MIER_PLTIE_SHIFT                   (13U)
+/*! PLTIE - Pin Low Timeout Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
+
+#define LPI2C_MIER_DMIE_MASK                     (0x4000U)
+#define LPI2C_MIER_DMIE_SHIFT                    (14U)
+/*! DMIE - Data Match Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
+
+#define LPI2C_MIER_STIE_MASK                     (0x8000U)
+#define LPI2C_MIER_STIE_SHIFT                    (15U)
+/*! STIE - Start Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_MIER_STIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK)
+/*! @} */
+
+/*! @name MDER - Controller DMA Enable */
+/*! @{ */
+
+#define LPI2C_MDER_TDDE_MASK                     (0x1U)
+#define LPI2C_MDER_TDDE_SHIFT                    (0U)
+/*! TDDE - Transmit Data DMA Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
+
+#define LPI2C_MDER_RDDE_MASK                     (0x2U)
+#define LPI2C_MDER_RDDE_SHIFT                    (1U)
+/*! RDDE - Receive Data DMA Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
+/*! @} */
+
+/*! @name MCFGR0 - Controller Configuration 0 */
+/*! @{ */
+
+#define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
+#define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
+/*! HREN - Host Request Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
+
+#define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
+#define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
+/*! HRPOL - Host Request Polarity
+ *  0b0..Active low
+ *  0b1..Active high
+ */
+#define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
+
+#define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
+#define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
+/*! HRSEL - Host Request Select
+ *  0b0..Host request input is pin HREQ
+ *  0b1..Host request input is input trigger
+ */
+#define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
+
+#define LPI2C_MCFGR0_HRDIR_MASK                  (0x8U)
+#define LPI2C_MCFGR0_HRDIR_SHIFT                 (3U)
+/*! HRDIR - Host Request Direction
+ *  0b0..HREQ pin is input (for LPI2C controller)
+ *  0b1..HREQ pin is output (for LPI2C target)
+ */
+#define LPI2C_MCFGR0_HRDIR(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRDIR_SHIFT)) & LPI2C_MCFGR0_HRDIR_MASK)
+
+#define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
+#define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
+/*! CIRFIFO - Circular FIFO Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
+
+#define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
+#define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
+/*! RDMO - Receive Data Match Only
+ *  0b0..Received data is stored in the receive FIFO
+ *  0b1..Received data is discarded unless MSR[DMF] is set
+ */
+#define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
+
+#define LPI2C_MCFGR0_RELAX_MASK                  (0x10000U)
+#define LPI2C_MCFGR0_RELAX_SHIFT                 (16U)
+/*! RELAX - Relaxed Mode
+ *  0b0..Normal transfer
+ *  0b1..Relaxed transfer
+ */
+#define LPI2C_MCFGR0_RELAX(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK)
+
+#define LPI2C_MCFGR0_ABORT_MASK                  (0x20000U)
+#define LPI2C_MCFGR0_ABORT_SHIFT                 (17U)
+/*! ABORT - Abort Transfer
+ *  0b0..Normal transfer
+ *  0b1..Abort existing transfer and do not start a new one
+ */
+#define LPI2C_MCFGR0_ABORT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK)
+/*! @} */
+
+/*! @name MCFGR1 - Controller Configuration 1 */
+/*! @{ */
+
+#define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
+#define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
+/*! PRESCALE - Prescaler
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 4
+ *  0b011..Divide by 8
+ *  0b100..Divide by 16
+ *  0b101..Divide by 32
+ *  0b110..Divide by 64
+ *  0b111..Divide by 128
+ */
+#define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
+
+#define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
+#define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
+/*! AUTOSTOP - Automatic Stop Generation
+ *  0b0..No effect
+ *  0b1..Stop automatically generated
+ */
+#define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
+
+#define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
+#define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
+/*! IGNACK - Ignore NACK
+ *  0b0..No effect
+ *  0b1..Treat a received NACK as an ACK
+ */
+#define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
+
+#define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
+#define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
+/*! TIMECFG - Timeout Configuration
+ *  0b0..SCL
+ *  0b1..SCL or SDA
+ */
+#define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
+
+#define LPI2C_MCFGR1_STOPCFG_MASK                (0x800U)
+#define LPI2C_MCFGR1_STOPCFG_SHIFT               (11U)
+/*! STOPCFG - Stop Configuration
+ *  0b0..Any Stop condition
+ *  0b1..Last Stop condition
+ */
+#define LPI2C_MCFGR1_STOPCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK)
+
+#define LPI2C_MCFGR1_STARTCFG_MASK               (0x1000U)
+#define LPI2C_MCFGR1_STARTCFG_SHIFT              (12U)
+/*! STARTCFG - Start Configuration
+ *  0b0..Sets when both I2C bus and LPI2C controller are idle
+ *  0b1..Sets when I2C bus is idle
+ */
+#define LPI2C_MCFGR1_STARTCFG(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK)
+
+#define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
+#define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
+/*! MATCFG - Match Configuration
+ *  0b000..Match is disabled
+ *  0b001..Reserved
+ *  0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1]
+ *  0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1]
+ *  0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1)
+ *  0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1)
+ *  0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1])
+ *  0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1])
+ */
+#define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
+
+#define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
+#define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
+/*! PINCFG - Pin Configuration
+ *  0b000..Two-pin open drain mode
+ *  0b001..Two-pin output only mode (Ultra-Fast mode)
+ *  0b010..Two-pin push-pull mode
+ *  0b011..Four-pin push-pull mode
+ *  0b100..Two-pin open-drain mode with separate LPI2C target
+ *  0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target
+ *  0b110..Two-pin push-pull mode with separate LPI2C target
+ *  0b111..Four-pin push-pull mode (inverted outputs)
+ */
+#define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
+/*! @} */
+
+/*! @name MCFGR2 - Controller Configuration 2 */
+/*! @{ */
+
+#define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
+#define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
+/*! BUSIDLE - Bus Idle Timeout */
+#define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
+
+#define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
+#define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
+/*! FILTSCL - Glitch Filter SCL */
+#define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
+
+#define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
+#define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
+/*! FILTSDA - Glitch Filter SDA */
+#define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
+/*! @} */
+
+/*! @name MCFGR3 - Controller Configuration 3 */
+/*! @{ */
+
+#define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
+#define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
+/*! PINLOW - Pin Low Timeout */
+#define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
+/*! @} */
+
+/*! @name MDMR - Controller Data Match */
+/*! @{ */
+
+#define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
+#define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
+/*! MATCH0 - Match 0 Value */
+#define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
+
+#define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
+#define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
+/*! MATCH1 - Match 1 Value */
+#define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
+/*! @} */
+
+/*! @name MCCR0 - Controller Clock Configuration 0 */
+/*! @{ */
+
+#define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
+#define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
+/*! CLKLO - Clock Low Period */
+#define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
+
+#define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
+#define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
+/*! CLKHI - Clock High Period */
+#define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
+
+#define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
+#define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
+/*! SETHOLD - Setup Hold Delay */
+#define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
+
+#define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
+#define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
+/*! DATAVD - Data Valid Delay */
+#define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
+/*! @} */
+
+/*! @name MCCR1 - Controller Clock Configuration 1 */
+/*! @{ */
+
+#define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
+#define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
+/*! CLKLO - Clock Low Period */
+#define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
+
+#define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
+#define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
+/*! CLKHI - Clock High Period */
+#define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
+
+#define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
+#define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
+/*! SETHOLD - Setup Hold Delay */
+#define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
+
+#define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
+#define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
+/*! DATAVD - Data Valid Delay */
+#define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
+/*! @} */
+
+/*! @name MFCR - Controller FIFO Control */
+/*! @{ */
+
+#define LPI2C_MFCR_TXWATER_MASK                  (0x3U)
+#define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
+/*! TXWATER - Transmit FIFO Watermark */
+#define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
+
+#define LPI2C_MFCR_RXWATER_MASK                  (0x30000U)
+#define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
+/*! RXWATER - Receive FIFO Watermark */
+#define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
+/*! @} */
+
+/*! @name MFSR - Controller FIFO Status */
+/*! @{ */
+
+#define LPI2C_MFSR_TXCOUNT_MASK                  (0x7U)
+#define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
+/*! TXCOUNT - Transmit FIFO Count */
+#define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
+
+#define LPI2C_MFSR_RXCOUNT_MASK                  (0x70000U)
+#define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
+/*! RXCOUNT - Receive FIFO Count */
+#define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
+/*! @} */
+
+/*! @name MTDR - Controller Transmit Data */
+/*! @{ */
+
+#define LPI2C_MTDR_DATA_MASK                     (0xFFU)
+#define LPI2C_MTDR_DATA_SHIFT                    (0U)
+/*! DATA - Transmit Data */
+#define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
+
+#define LPI2C_MTDR_CMD_MASK                      (0x700U)
+#define LPI2C_MTDR_CMD_SHIFT                     (8U)
+/*! CMD - Command Data
+ *  0b000..Transmit the value in DATA[7:0]
+ *  0b001..Receive (DATA[7:0] + 1) bytes
+ *  0b010..Generate Stop condition on I2C bus
+ *  0b011..Receive and discard (DATA[7:0] + 1) bytes
+ *  0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0]
+ *  0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned)
+ *  0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode
+ *  0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned)
+ */
+#define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
+/*! @} */
+
+/*! @name MRDR - Controller Receive Data */
+/*! @{ */
+
+#define LPI2C_MRDR_DATA_MASK                     (0xFFU)
+#define LPI2C_MRDR_DATA_SHIFT                    (0U)
+/*! DATA - Receive Data */
+#define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
+
+#define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
+#define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
+/*! RXEMPTY - Receive Empty
+ *  0b0..Not empty
+ *  0b1..Empty
+ */
+#define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
+/*! @} */
+
+/*! @name MRDROR - Controller Receive Data Read Only */
+/*! @{ */
+
+#define LPI2C_MRDROR_DATA_MASK                   (0xFFU)
+#define LPI2C_MRDROR_DATA_SHIFT                  (0U)
+/*! DATA - Receive Data */
+#define LPI2C_MRDROR_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK)
+
+#define LPI2C_MRDROR_RXEMPTY_MASK                (0x4000U)
+#define LPI2C_MRDROR_RXEMPTY_SHIFT               (14U)
+/*! RXEMPTY - RX Empty
+ *  0b0..Not empty
+ *  0b1..Empty
+ */
+#define LPI2C_MRDROR_RXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK)
+/*! @} */
+
+/*! @name SCR - Target Control */
+/*! @{ */
+
+#define LPI2C_SCR_SEN_MASK                       (0x1U)
+#define LPI2C_SCR_SEN_SHIFT                      (0U)
+/*! SEN - Target Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
+
+#define LPI2C_SCR_RST_MASK                       (0x2U)
+#define LPI2C_SCR_RST_SHIFT                      (1U)
+/*! RST - Software Reset
+ *  0b0..Not reset
+ *  0b1..Reset
+ */
+#define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
+
+#define LPI2C_SCR_FILTEN_MASK                    (0x10U)
+#define LPI2C_SCR_FILTEN_SHIFT                   (4U)
+/*! FILTEN - Filter Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
+
+#define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
+#define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
+/*! FILTDZ - Filter Doze Enable
+ *  0b0..Enable
+ *  0b1..Disable
+ */
+#define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
+
+#define LPI2C_SCR_RTF_MASK                       (0x100U)
+#define LPI2C_SCR_RTF_SHIFT                      (8U)
+/*! RTF - Reset Transmit FIFO
+ *  0b0..No effect
+ *  0b1..STDR is now empty
+ */
+#define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
+
+#define LPI2C_SCR_RRF_MASK                       (0x200U)
+#define LPI2C_SCR_RRF_SHIFT                      (9U)
+/*! RRF - Reset Receive FIFO
+ *  0b0..No effect
+ *  0b1..SRDR is now empty
+ */
+#define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
+/*! @} */
+
+/*! @name SSR - Target Status */
+/*! @{ */
+
+#define LPI2C_SSR_TDF_MASK                       (0x1U)
+#define LPI2C_SSR_TDF_SHIFT                      (0U)
+/*! TDF - Transmit Data Flag
+ *  0b0..Transmit data not requested
+ *  0b1..Transmit data is requested
+ */
+#define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
+
+#define LPI2C_SSR_RDF_MASK                       (0x2U)
+#define LPI2C_SSR_RDF_SHIFT                      (1U)
+/*! RDF - Receive Data Flag
+ *  0b0..Not ready
+ *  0b1..Ready
+ */
+#define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
+
+#define LPI2C_SSR_AVF_MASK                       (0x4U)
+#define LPI2C_SSR_AVF_SHIFT                      (2U)
+/*! AVF - Address Valid Flag
+ *  0b0..Not valid
+ *  0b1..Valid
+ */
+#define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
+
+#define LPI2C_SSR_TAF_MASK                       (0x8U)
+#define LPI2C_SSR_TAF_SHIFT                      (3U)
+/*! TAF - Transmit ACK Flag
+ *  0b0..Not required
+ *  0b1..Required
+ */
+#define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
+
+#define LPI2C_SSR_RSF_MASK                       (0x100U)
+#define LPI2C_SSR_RSF_SHIFT                      (8U)
+/*! RSF - Repeated Start Flag
+ *  0b0..No effect
+ *  0b0..No repeated Start detected
+ *  0b1..Clear the flag
+ *  0b1..Repeated Start detected
+ */
+#define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
+
+#define LPI2C_SSR_SDF_MASK                       (0x200U)
+#define LPI2C_SSR_SDF_SHIFT                      (9U)
+/*! SDF - Stop Detect Flag
+ *  0b0..No Stop detected
+ *  0b0..No effect
+ *  0b1..Clear the flag
+ *  0b1..Stop detected
+ */
+#define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
+
+#define LPI2C_SSR_BEF_MASK                       (0x400U)
+#define LPI2C_SSR_BEF_SHIFT                      (10U)
+/*! BEF - Bit Error Flag
+ *  0b0..No bit error occurred
+ *  0b0..No effect
+ *  0b1..Bit error occurred
+ *  0b1..Clear the flag
+ */
+#define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
+
+#define LPI2C_SSR_FEF_MASK                       (0x800U)
+#define LPI2C_SSR_FEF_SHIFT                      (11U)
+/*! FEF - FIFO Error Flag
+ *  0b0..No FIFO error
+ *  0b0..No effect
+ *  0b1..Clear the flag
+ *  0b1..FIFO error
+ */
+#define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
+
+#define LPI2C_SSR_AM0F_MASK                      (0x1000U)
+#define LPI2C_SSR_AM0F_SHIFT                     (12U)
+/*! AM0F - Address Match 0 Flag
+ *  0b0..ADDR0 matching address not received
+ *  0b1..ADDR0 matching address received
+ */
+#define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
+
+#define LPI2C_SSR_AM1F_MASK                      (0x2000U)
+#define LPI2C_SSR_AM1F_SHIFT                     (13U)
+/*! AM1F - Address Match 1 Flag
+ *  0b0..Matching address not received
+ *  0b1..Matching address received
+ */
+#define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
+
+#define LPI2C_SSR_GCF_MASK                       (0x4000U)
+#define LPI2C_SSR_GCF_SHIFT                      (14U)
+/*! GCF - General Call Flag
+ *  0b0..General call address disabled or not detected
+ *  0b1..General call address detected
+ */
+#define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
+
+#define LPI2C_SSR_SARF_MASK                      (0x8000U)
+#define LPI2C_SSR_SARF_SHIFT                     (15U)
+/*! SARF - SMBus Alert Response Flag
+ *  0b0..Disabled or not detected
+ *  0b1..Enabled and detected
+ */
+#define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
+
+#define LPI2C_SSR_SBF_MASK                       (0x1000000U)
+#define LPI2C_SSR_SBF_SHIFT                      (24U)
+/*! SBF - Target Busy Flag
+ *  0b0..Idle
+ *  0b1..Busy
+ */
+#define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
+
+#define LPI2C_SSR_BBF_MASK                       (0x2000000U)
+#define LPI2C_SSR_BBF_SHIFT                      (25U)
+/*! BBF - Bus Busy Flag
+ *  0b0..Idle
+ *  0b1..Busy
+ */
+#define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
+/*! @} */
+
+/*! @name SIER - Target Interrupt Enable */
+/*! @{ */
+
+#define LPI2C_SIER_TDIE_MASK                     (0x1U)
+#define LPI2C_SIER_TDIE_SHIFT                    (0U)
+/*! TDIE - Transmit Data Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
+
+#define LPI2C_SIER_RDIE_MASK                     (0x2U)
+#define LPI2C_SIER_RDIE_SHIFT                    (1U)
+/*! RDIE - Receive Data Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
+
+#define LPI2C_SIER_AVIE_MASK                     (0x4U)
+#define LPI2C_SIER_AVIE_SHIFT                    (2U)
+/*! AVIE - Address Valid Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
+
+#define LPI2C_SIER_TAIE_MASK                     (0x8U)
+#define LPI2C_SIER_TAIE_SHIFT                    (3U)
+/*! TAIE - Transmit ACK Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
+
+#define LPI2C_SIER_RSIE_MASK                     (0x100U)
+#define LPI2C_SIER_RSIE_SHIFT                    (8U)
+/*! RSIE - Repeated Start Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
+
+#define LPI2C_SIER_SDIE_MASK                     (0x200U)
+#define LPI2C_SIER_SDIE_SHIFT                    (9U)
+/*! SDIE - Stop Detect Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
+
+#define LPI2C_SIER_BEIE_MASK                     (0x400U)
+#define LPI2C_SIER_BEIE_SHIFT                    (10U)
+/*! BEIE - Bit Error Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
+
+#define LPI2C_SIER_FEIE_MASK                     (0x800U)
+#define LPI2C_SIER_FEIE_SHIFT                    (11U)
+/*! FEIE - FIFO Error Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
+
+#define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
+#define LPI2C_SIER_AM0IE_SHIFT                   (12U)
+/*! AM0IE - Address Match 0 Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
+
+#define LPI2C_SIER_AM1IE_MASK                    (0x2000U)
+#define LPI2C_SIER_AM1IE_SHIFT                   (13U)
+/*! AM1IE - Address Match 1 Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SIER_AM1IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK)
+
+#define LPI2C_SIER_GCIE_MASK                     (0x4000U)
+#define LPI2C_SIER_GCIE_SHIFT                    (14U)
+/*! GCIE - General Call Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
+
+#define LPI2C_SIER_SARIE_MASK                    (0x8000U)
+#define LPI2C_SIER_SARIE_SHIFT                   (15U)
+/*! SARIE - SMBus Alert Response Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
+/*! @} */
+
+/*! @name SDER - Target DMA Enable */
+/*! @{ */
+
+#define LPI2C_SDER_TDDE_MASK                     (0x1U)
+#define LPI2C_SDER_TDDE_SHIFT                    (0U)
+/*! TDDE - Transmit Data DMA Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
+
+#define LPI2C_SDER_RDDE_MASK                     (0x2U)
+#define LPI2C_SDER_RDDE_SHIFT                    (1U)
+/*! RDDE - Receive Data DMA Enable
+ *  0b0..Disable DMA request
+ *  0b1..Enable DMA request
+ */
+#define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
+
+#define LPI2C_SDER_AVDE_MASK                     (0x4U)
+#define LPI2C_SDER_AVDE_SHIFT                    (2U)
+/*! AVDE - Address Valid DMA Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
+
+#define LPI2C_SDER_RSDE_MASK                     (0x100U)
+#define LPI2C_SDER_RSDE_SHIFT                    (8U)
+/*! RSDE - Repeated Start DMA Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SDER_RSDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK)
+
+#define LPI2C_SDER_SDDE_MASK                     (0x200U)
+#define LPI2C_SDER_SDDE_SHIFT                    (9U)
+/*! SDDE - Stop Detect DMA Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SDER_SDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK)
+/*! @} */
+
+/*! @name SCFGR0 - Target Configuration 0 */
+/*! @{ */
+
+#define LPI2C_SCFGR0_RDREQ_MASK                  (0x1U)
+#define LPI2C_SCFGR0_RDREQ_SHIFT                 (0U)
+/*! RDREQ - Read Request
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SCFGR0_RDREQ(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK)
+
+#define LPI2C_SCFGR0_RDACK_MASK                  (0x2U)
+#define LPI2C_SCFGR0_RDACK_SHIFT                 (1U)
+/*! RDACK - Read Acknowledge Flag
+ *  0b0..Read Request not acknowledged
+ *  0b1..Read Request acknowledged
+ */
+#define LPI2C_SCFGR0_RDACK(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK)
+/*! @} */
+
+/*! @name SCFGR1 - Target Configuration 1 */
+/*! @{ */
+
+#define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
+#define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
+/*! ADRSTALL - Address SCL Stall
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
+
+#define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
+#define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
+/*! RXSTALL - RX SCL Stall
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
+
+#define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
+#define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
+/*! TXDSTALL - Transmit Data SCL Stall
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
+
+#define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
+#define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
+/*! ACKSTALL - ACK SCL Stall
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
+
+#define LPI2C_SCFGR1_RXNACK_MASK                 (0x10U)
+#define LPI2C_SCFGR1_RXNACK_SHIFT                (4U)
+/*! RXNACK - Receive NACK
+ *  0b0..ACK or NACK always determined by STAR[TXNACK]
+ *  0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK]
+ */
+#define LPI2C_SCFGR1_RXNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK)
+
+#define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
+#define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
+/*! GCEN - General Call Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
+
+#define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
+#define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
+/*! SAEN - SMBus Alert Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
+
+#define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
+#define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
+/*! TXCFG - Transmit Flag Configuration
+ *  0b0..SSR[TDF] is set only during a target-transmit transfer when STDR is empty
+ *  0b1..SSR[TDF] is set whenever STDR is empty
+ */
+#define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
+
+#define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
+#define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
+/*! RXCFG - Receive Data Configuration
+ *  0b0..Return received data, clear SSR[RDF]
+ *  0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear SSR[RDF] when SSR[AFV] is not set
+ */
+#define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
+
+#define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
+#define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
+/*! IGNACK - Ignore NACK
+ *  0b0..End transfer on NACK
+ *  0b1..Do not end transfer on NACK
+ */
+#define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
+
+#define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
+#define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
+/*! HSMEN - HS Mode Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
+
+#define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
+#define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
+/*! ADDRCFG - Address Configuration
+ *  0b000..Address match 0 (7-bit)
+ *  0b001..Address match 0 (10-bit)
+ *  0b010..Address match 0 (7-bit) or address match 1 (7-bit)
+ *  0b011..Address match 0 (10-bit) or address match 1 (10-bit)
+ *  0b100..Address match 0 (7-bit) or address match 1 (10-bit)
+ *  0b101..Address match 0 (10-bit) or address match 1 (7-bit)
+ *  0b110..From address match 0 (7-bit) to address match 1 (7-bit)
+ *  0b111..From address match 0 (10-bit) to address match 1 (10-bit)
+ */
+#define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
+
+#define LPI2C_SCFGR1_RXALL_MASK                  (0x1000000U)
+#define LPI2C_SCFGR1_RXALL_SHIFT                 (24U)
+/*! RXALL - Receive All
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPI2C_SCFGR1_RXALL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK)
+
+#define LPI2C_SCFGR1_RSCFG_MASK                  (0x2000000U)
+#define LPI2C_SCFGR1_RSCFG_SHIFT                 (25U)
+/*! RSCFG - Repeated Start Configuration
+ *  0b0..Any repeated Start condition following an address match
+ *  0b1..Any repeated Start condition
+ */
+#define LPI2C_SCFGR1_RSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK)
+
+#define LPI2C_SCFGR1_SDCFG_MASK                  (0x4000000U)
+#define LPI2C_SCFGR1_SDCFG_SHIFT                 (26U)
+/*! SDCFG - Stop Detect Configuration
+ *  0b0..Any Stop condition following an address match
+ *  0b1..Any Stop condition
+ */
+#define LPI2C_SCFGR1_SDCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK)
+/*! @} */
+
+/*! @name SCFGR2 - Target Configuration 2 */
+/*! @{ */
+
+#define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
+#define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
+/*! CLKHOLD - Clock Hold Time */
+#define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
+
+#define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
+#define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
+/*! DATAVD - Data Valid Delay */
+#define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
+
+#define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
+#define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
+/*! FILTSCL - Glitch Filter SCL */
+#define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
+
+#define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
+#define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
+/*! FILTSDA - Glitch Filter SDA */
+#define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
+/*! @} */
+
+/*! @name SAMR - Target Address Match */
+/*! @{ */
+
+#define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
+#define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
+/*! ADDR0 - Address 0 Value */
+#define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
+
+#define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
+#define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
+/*! ADDR1 - Address 1 Value */
+#define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
+/*! @} */
+
+/*! @name SASR - Target Address Status */
+/*! @{ */
+
+#define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
+#define LPI2C_SASR_RADDR_SHIFT                   (0U)
+/*! RADDR - Received Address */
+#define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
+
+#define LPI2C_SASR_ANV_MASK                      (0x4000U)
+#define LPI2C_SASR_ANV_SHIFT                     (14U)
+/*! ANV - Address Not Valid
+ *  0b0..Valid
+ *  0b1..Not valid
+ */
+#define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
+/*! @} */
+
+/*! @name STAR - Target Transmit ACK */
+/*! @{ */
+
+#define LPI2C_STAR_TXNACK_MASK                   (0x1U)
+#define LPI2C_STAR_TXNACK_SHIFT                  (0U)
+/*! TXNACK - Transmit NACK
+ *  0b0..Transmit ACK
+ *  0b1..Transmit NACK
+ */
+#define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
+/*! @} */
+
+/*! @name STDR - Target Transmit Data */
+/*! @{ */
+
+#define LPI2C_STDR_DATA_MASK                     (0xFFU)
+#define LPI2C_STDR_DATA_SHIFT                    (0U)
+/*! DATA - Transmit Data */
+#define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
+/*! @} */
+
+/*! @name SRDR - Target Receive Data */
+/*! @{ */
+
+#define LPI2C_SRDR_DATA_MASK                     (0xFFU)
+#define LPI2C_SRDR_DATA_SHIFT                    (0U)
+/*! DATA - Received Data */
+#define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
+
+#define LPI2C_SRDR_RADDR_MASK                    (0x700U)
+#define LPI2C_SRDR_RADDR_SHIFT                   (8U)
+/*! RADDR - Received Address */
+#define LPI2C_SRDR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK)
+
+#define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
+#define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
+/*! RXEMPTY - Receive Empty
+ *  0b0..Not empty
+ *  0b1..Empty
+ */
+#define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
+
+#define LPI2C_SRDR_SOF_MASK                      (0x8000U)
+#define LPI2C_SRDR_SOF_SHIFT                     (15U)
+/*! SOF - Start of Frame
+ *  0b0..Not first
+ *  0b1..First
+ */
+#define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
+/*! @} */
+
+/*! @name SRDROR - Target Receive Data Read Only */
+/*! @{ */
+
+#define LPI2C_SRDROR_DATA_MASK                   (0xFFU)
+#define LPI2C_SRDROR_DATA_SHIFT                  (0U)
+/*! DATA - Receive Data */
+#define LPI2C_SRDROR_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK)
+
+#define LPI2C_SRDROR_RADDR_MASK                  (0x700U)
+#define LPI2C_SRDROR_RADDR_SHIFT                 (8U)
+/*! RADDR - Received Address */
+#define LPI2C_SRDROR_RADDR(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK)
+
+#define LPI2C_SRDROR_RXEMPTY_MASK                (0x4000U)
+#define LPI2C_SRDROR_RXEMPTY_SHIFT               (14U)
+/*! RXEMPTY - Receive Empty
+ *  0b0..Not empty
+ *  0b1..Empty
+ */
+#define LPI2C_SRDROR_RXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK)
+
+#define LPI2C_SRDROR_SOF_MASK                    (0x8000U)
+#define LPI2C_SRDROR_SOF_SHIFT                   (15U)
+/*! SOF - Start of Frame
+ *  0b0..Not the first
+ *  0b1..First
+ */
+#define LPI2C_SRDROR_SOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPI2C_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group LPI2C_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_LPI2C_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPSPI.h
new file mode 100644
index 0000000000..30451e9531
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPSPI.h
@@ -0,0 +1,860 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for LPSPI
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_LPSPI.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for LPSPI
+ *
+ * CMSIS Peripheral Access Layer for LPSPI
+ */
+
+#if !defined(PERI_LPSPI_H_)
+#define PERI_LPSPI_H_                            /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- LPSPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
+ * @{
+ */
+
+/** LPSPI - Size of Registers Arrays */
+#define LPSPI_TDBR_COUNT                          128u
+#define LPSPI_RDBR_COUNT                          128u
+
+/** LPSPI - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t CR;                                /**< Control, offset: 0x10 */
+  __IO uint32_t SR;                                /**< Status, offset: 0x14 */
+  __IO uint32_t IER;                               /**< Interrupt Enable, offset: 0x18 */
+  __IO uint32_t DER;                               /**< DMA Enable, offset: 0x1C */
+  __IO uint32_t CFGR0;                             /**< Configuration 0, offset: 0x20 */
+  __IO uint32_t CFGR1;                             /**< Configuration 1, offset: 0x24 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t DMR0;                              /**< Data Match 0, offset: 0x30 */
+  __IO uint32_t DMR1;                              /**< Data Match 1, offset: 0x34 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t CCR;                               /**< Clock Configuration, offset: 0x40 */
+  __IO uint32_t CCR1;                              /**< Clock Configuration 1, offset: 0x44 */
+       uint8_t RESERVED_3[16];
+  __IO uint32_t FCR;                               /**< FIFO Control, offset: 0x58 */
+  __I  uint32_t FSR;                               /**< FIFO Status, offset: 0x5C */
+  __IO uint32_t TCR;                               /**< Transmit Command, offset: 0x60 */
+  __O  uint32_t TDR;                               /**< Transmit Data, offset: 0x64 */
+       uint8_t RESERVED_4[8];
+  __I  uint32_t RSR;                               /**< Receive Status, offset: 0x70 */
+  __I  uint32_t RDR;                               /**< Receive Data, offset: 0x74 */
+  __I  uint32_t RDROR;                             /**< Receive Data Read Only, offset: 0x78 */
+       uint8_t RESERVED_5[896];
+  __O  uint32_t TCBR;                              /**< Transmit Command Burst, offset: 0x3FC */
+  __O  uint32_t TDBR[LPSPI_TDBR_COUNT];            /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */
+  __I  uint32_t RDBR[LPSPI_RDBR_COUNT];            /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */
+} LPSPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPSPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID */
+/*! @{ */
+
+#define LPSPI_VERID_FEATURE_MASK                 (0xFFFFU)
+#define LPSPI_VERID_FEATURE_SHIFT                (0U)
+/*! FEATURE - Module Identification Number
+ *  0b0000000000000100..Standard feature set supporting a 32-bit shift register.
+ */
+#define LPSPI_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
+
+#define LPSPI_VERID_MINOR_MASK                   (0xFF0000U)
+#define LPSPI_VERID_MINOR_SHIFT                  (16U)
+/*! MINOR - Minor Version Number */
+#define LPSPI_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
+
+#define LPSPI_VERID_MAJOR_MASK                   (0xFF000000U)
+#define LPSPI_VERID_MAJOR_SHIFT                  (24U)
+/*! MAJOR - Major Version Number */
+#define LPSPI_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter */
+/*! @{ */
+
+#define LPSPI_PARAM_TXFIFO_MASK                  (0xFFU)
+#define LPSPI_PARAM_TXFIFO_SHIFT                 (0U)
+/*! TXFIFO - Transmit FIFO Size */
+#define LPSPI_PARAM_TXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
+
+#define LPSPI_PARAM_RXFIFO_MASK                  (0xFF00U)
+#define LPSPI_PARAM_RXFIFO_SHIFT                 (8U)
+/*! RXFIFO - Receive FIFO Size */
+#define LPSPI_PARAM_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
+
+#define LPSPI_PARAM_PCSNUM_MASK                  (0xFF0000U)
+#define LPSPI_PARAM_PCSNUM_SHIFT                 (16U)
+/*! PCSNUM - PCS Number */
+#define LPSPI_PARAM_PCSNUM(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
+/*! @} */
+
+/*! @name CR - Control */
+/*! @{ */
+
+#define LPSPI_CR_MEN_MASK                        (0x1U)
+#define LPSPI_CR_MEN_SHIFT                       (0U)
+/*! MEN - Module Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_CR_MEN(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
+
+#define LPSPI_CR_RST_MASK                        (0x2U)
+#define LPSPI_CR_RST_SHIFT                       (1U)
+/*! RST - Software Reset
+ *  0b0..Not reset
+ *  0b1..Reset
+ */
+#define LPSPI_CR_RST(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
+
+#define LPSPI_CR_DBGEN_MASK                      (0x8U)
+#define LPSPI_CR_DBGEN_SHIFT                     (3U)
+/*! DBGEN - Debug Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_CR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
+
+#define LPSPI_CR_RTF_MASK                        (0x100U)
+#define LPSPI_CR_RTF_SHIFT                       (8U)
+/*! RTF - Reset Transmit FIFO
+ *  0b0..No effect
+ *  0b1..Reset
+ */
+#define LPSPI_CR_RTF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
+
+#define LPSPI_CR_RRF_MASK                        (0x200U)
+#define LPSPI_CR_RRF_SHIFT                       (9U)
+/*! RRF - Reset Receive FIFO
+ *  0b0..No effect
+ *  0b1..Reset
+ */
+#define LPSPI_CR_RRF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
+/*! @} */
+
+/*! @name SR - Status */
+/*! @{ */
+
+#define LPSPI_SR_TDF_MASK                        (0x1U)
+#define LPSPI_SR_TDF_SHIFT                       (0U)
+/*! TDF - Transmit Data Flag
+ *  0b0..Transmit data not requested
+ *  0b1..Transmit data requested
+ */
+#define LPSPI_SR_TDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
+
+#define LPSPI_SR_RDF_MASK                        (0x2U)
+#define LPSPI_SR_RDF_SHIFT                       (1U)
+/*! RDF - Receive Data Flag
+ *  0b0..Receive data not ready
+ *  0b1..Receive data ready
+ */
+#define LPSPI_SR_RDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
+
+#define LPSPI_SR_WCF_MASK                        (0x100U)
+#define LPSPI_SR_WCF_SHIFT                       (8U)
+/*! WCF - Word Complete Flag
+ *  0b0..No effect
+ *  0b0..Not complete
+ *  0b1..Clear the flag
+ *  0b1..Complete
+ */
+#define LPSPI_SR_WCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
+
+#define LPSPI_SR_FCF_MASK                        (0x200U)
+#define LPSPI_SR_FCF_SHIFT                       (9U)
+/*! FCF - Frame Complete Flag
+ *  0b0..No effect
+ *  0b0..Not complete
+ *  0b1..Clear the flag
+ *  0b1..Complete
+ */
+#define LPSPI_SR_FCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
+
+#define LPSPI_SR_TCF_MASK                        (0x400U)
+#define LPSPI_SR_TCF_SHIFT                       (10U)
+/*! TCF - Transfer Complete Flag
+ *  0b0..No effect
+ *  0b0..Not complete
+ *  0b1..Clear the flag
+ *  0b1..Complete
+ */
+#define LPSPI_SR_TCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
+
+#define LPSPI_SR_TEF_MASK                        (0x800U)
+#define LPSPI_SR_TEF_SHIFT                       (11U)
+/*! TEF - Transmit Error Flag
+ *  0b0..No effect
+ *  0b0..No underrun
+ *  0b1..Clear the flag
+ *  0b1..Underrun
+ */
+#define LPSPI_SR_TEF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
+
+#define LPSPI_SR_REF_MASK                        (0x1000U)
+#define LPSPI_SR_REF_SHIFT                       (12U)
+/*! REF - Receive Error Flag
+ *  0b0..No effect
+ *  0b0..No overflow
+ *  0b1..Clear the flag
+ *  0b1..Overflow
+ */
+#define LPSPI_SR_REF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
+
+#define LPSPI_SR_DMF_MASK                        (0x2000U)
+#define LPSPI_SR_DMF_SHIFT                       (13U)
+/*! DMF - Data Match Flag
+ *  0b0..No effect
+ *  0b0..No match
+ *  0b1..Clear the flag
+ *  0b1..Match
+ */
+#define LPSPI_SR_DMF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
+
+#define LPSPI_SR_MBF_MASK                        (0x1000000U)
+#define LPSPI_SR_MBF_SHIFT                       (24U)
+/*! MBF - Module Busy Flag
+ *  0b0..LPSPI is idle
+ *  0b1..LPSPI is busy
+ */
+#define LPSPI_SR_MBF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
+/*! @} */
+
+/*! @name IER - Interrupt Enable */
+/*! @{ */
+
+#define LPSPI_IER_TDIE_MASK                      (0x1U)
+#define LPSPI_IER_TDIE_SHIFT                     (0U)
+/*! TDIE - Transmit Data Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_IER_TDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
+
+#define LPSPI_IER_RDIE_MASK                      (0x2U)
+#define LPSPI_IER_RDIE_SHIFT                     (1U)
+/*! RDIE - Receive Data Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_IER_RDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
+
+#define LPSPI_IER_WCIE_MASK                      (0x100U)
+#define LPSPI_IER_WCIE_SHIFT                     (8U)
+/*! WCIE - Word Complete Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_IER_WCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
+
+#define LPSPI_IER_FCIE_MASK                      (0x200U)
+#define LPSPI_IER_FCIE_SHIFT                     (9U)
+/*! FCIE - Frame Complete Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_IER_FCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
+
+#define LPSPI_IER_TCIE_MASK                      (0x400U)
+#define LPSPI_IER_TCIE_SHIFT                     (10U)
+/*! TCIE - Transfer Complete Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_IER_TCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
+
+#define LPSPI_IER_TEIE_MASK                      (0x800U)
+#define LPSPI_IER_TEIE_SHIFT                     (11U)
+/*! TEIE - Transmit Error Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_IER_TEIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
+
+#define LPSPI_IER_REIE_MASK                      (0x1000U)
+#define LPSPI_IER_REIE_SHIFT                     (12U)
+/*! REIE - Receive Error Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_IER_REIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
+
+#define LPSPI_IER_DMIE_MASK                      (0x2000U)
+#define LPSPI_IER_DMIE_SHIFT                     (13U)
+/*! DMIE - Data Match Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_IER_DMIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
+/*! @} */
+
+/*! @name DER - DMA Enable */
+/*! @{ */
+
+#define LPSPI_DER_TDDE_MASK                      (0x1U)
+#define LPSPI_DER_TDDE_SHIFT                     (0U)
+/*! TDDE - Transmit Data DMA Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_DER_TDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
+
+#define LPSPI_DER_RDDE_MASK                      (0x2U)
+#define LPSPI_DER_RDDE_SHIFT                     (1U)
+/*! RDDE - Receive Data DMA Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_DER_RDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
+
+#define LPSPI_DER_FCDE_MASK                      (0x200U)
+#define LPSPI_DER_FCDE_SHIFT                     (9U)
+/*! FCDE - Frame Complete DMA Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_DER_FCDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK)
+/*! @} */
+
+/*! @name CFGR0 - Configuration 0 */
+/*! @{ */
+
+#define LPSPI_CFGR0_HREN_MASK                    (0x1U)
+#define LPSPI_CFGR0_HREN_SHIFT                   (0U)
+/*! HREN - Host Request Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_CFGR0_HREN(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
+
+#define LPSPI_CFGR0_HRPOL_MASK                   (0x2U)
+#define LPSPI_CFGR0_HRPOL_SHIFT                  (1U)
+/*! HRPOL - Host Request Polarity
+ *  0b0..Active high
+ *  0b1..Active low
+ */
+#define LPSPI_CFGR0_HRPOL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
+
+#define LPSPI_CFGR0_HRSEL_MASK                   (0x4U)
+#define LPSPI_CFGR0_HRSEL_SHIFT                  (2U)
+/*! HRSEL - Host Request Select
+ *  0b0..HREQ pin
+ *  0b1..Input trigger
+ */
+#define LPSPI_CFGR0_HRSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
+
+#define LPSPI_CFGR0_HRDIR_MASK                   (0x8U)
+#define LPSPI_CFGR0_HRDIR_SHIFT                  (3U)
+/*! HRDIR - Host Request Direction
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define LPSPI_CFGR0_HRDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRDIR_SHIFT)) & LPSPI_CFGR0_HRDIR_MASK)
+
+#define LPSPI_CFGR0_CIRFIFO_MASK                 (0x100U)
+#define LPSPI_CFGR0_CIRFIFO_SHIFT                (8U)
+/*! CIRFIFO - Circular FIFO Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_CFGR0_CIRFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
+
+#define LPSPI_CFGR0_RDMO_MASK                    (0x200U)
+#define LPSPI_CFGR0_RDMO_SHIFT                   (9U)
+/*! RDMO - Receive Data Match Only
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_CFGR0_RDMO(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
+/*! @} */
+
+/*! @name CFGR1 - Configuration 1 */
+/*! @{ */
+
+#define LPSPI_CFGR1_MASTER_MASK                  (0x1U)
+#define LPSPI_CFGR1_MASTER_SHIFT                 (0U)
+/*! MASTER - Controller Mode
+ *  0b0..Peripheral mode
+ *  0b1..Controller mode
+ */
+#define LPSPI_CFGR1_MASTER(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
+
+#define LPSPI_CFGR1_SAMPLE_MASK                  (0x2U)
+#define LPSPI_CFGR1_SAMPLE_SHIFT                 (1U)
+/*! SAMPLE - Sample Point
+ *  0b0..SCK edge
+ *  0b1..Delayed SCK edge
+ */
+#define LPSPI_CFGR1_SAMPLE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
+
+#define LPSPI_CFGR1_AUTOPCS_MASK                 (0x4U)
+#define LPSPI_CFGR1_AUTOPCS_SHIFT                (2U)
+/*! AUTOPCS - Automatic PCS
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_CFGR1_AUTOPCS(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
+
+#define LPSPI_CFGR1_NOSTALL_MASK                 (0x8U)
+#define LPSPI_CFGR1_NOSTALL_SHIFT                (3U)
+/*! NOSTALL - No Stall
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_CFGR1_NOSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
+
+#define LPSPI_CFGR1_PARTIAL_MASK                 (0x10U)
+#define LPSPI_CFGR1_PARTIAL_SHIFT                (4U)
+/*! PARTIAL - Partial Enable
+ *  0b0..Discard
+ *  0b1..Store
+ */
+#define LPSPI_CFGR1_PARTIAL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK)
+
+#define LPSPI_CFGR1_PCSPOL_MASK                  (0xF00U)
+#define LPSPI_CFGR1_PCSPOL_SHIFT                 (8U)
+/*! PCSPOL - Peripheral Chip Select Polarity
+ *  0b0000..Active low
+ *  0b0001..Active high
+ */
+#define LPSPI_CFGR1_PCSPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
+
+#define LPSPI_CFGR1_MATCFG_MASK                  (0x70000U)
+#define LPSPI_CFGR1_MATCFG_SHIFT                 (16U)
+/*! MATCFG - Match Configuration
+ *  0b000..Match is disabled
+ *  0b001..
+ *  0b010..Match first data word with compare word
+ *  0b011..Match any data word with compare word
+ *  0b100..Sequential match, first data word
+ *  0b101..Sequential match, any data word
+ *  0b110..Match first data word (masked) with compare word (masked)
+ *  0b111..Match any data word (masked) with compare word (masked)
+ */
+#define LPSPI_CFGR1_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
+
+#define LPSPI_CFGR1_PINCFG_MASK                  (0x3000000U)
+#define LPSPI_CFGR1_PINCFG_SHIFT                 (24U)
+/*! PINCFG - Pin Configuration
+ *  0b00..SIN is used for input data; SOUT is used for output data
+ *  0b01..SIN is used for both input and output data; only half-duplex serial transfers are supported
+ *  0b10..SOUT is used for both input and output data; only half-duplex serial transfers are supported
+ *  0b11..SOUT is used for input data; SIN is used for output data
+ */
+#define LPSPI_CFGR1_PINCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
+
+#define LPSPI_CFGR1_OUTCFG_MASK                  (0x4000000U)
+#define LPSPI_CFGR1_OUTCFG_SHIFT                 (26U)
+/*! OUTCFG - Output Configuration
+ *  0b0..Retain last value
+ *  0b1..3-stated
+ */
+#define LPSPI_CFGR1_OUTCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
+
+#define LPSPI_CFGR1_PCSCFG_MASK                  (0x8000000U)
+#define LPSPI_CFGR1_PCSCFG_SHIFT                 (27U)
+/*! PCSCFG - Peripheral Chip Select Configuration
+ *  0b0..PCS[3:2] configured for chip select function
+ *  0b1..PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
+ */
+#define LPSPI_CFGR1_PCSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
+/*! @} */
+
+/*! @name DMR0 - Data Match 0 */
+/*! @{ */
+
+#define LPSPI_DMR0_MATCH0_MASK                   (0xFFFFFFFFU)
+#define LPSPI_DMR0_MATCH0_SHIFT                  (0U)
+/*! MATCH0 - Match 0 Value */
+#define LPSPI_DMR0_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
+/*! @} */
+
+/*! @name DMR1 - Data Match 1 */
+/*! @{ */
+
+#define LPSPI_DMR1_MATCH1_MASK                   (0xFFFFFFFFU)
+#define LPSPI_DMR1_MATCH1_SHIFT                  (0U)
+/*! MATCH1 - Match 1 Value */
+#define LPSPI_DMR1_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
+/*! @} */
+
+/*! @name CCR - Clock Configuration */
+/*! @{ */
+
+#define LPSPI_CCR_SCKDIV_MASK                    (0xFFU)
+#define LPSPI_CCR_SCKDIV_SHIFT                   (0U)
+/*! SCKDIV - SCK Divider */
+#define LPSPI_CCR_SCKDIV(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
+
+#define LPSPI_CCR_DBT_MASK                       (0xFF00U)
+#define LPSPI_CCR_DBT_SHIFT                      (8U)
+/*! DBT - Delay Between Transfers */
+#define LPSPI_CCR_DBT(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
+
+#define LPSPI_CCR_PCSSCK_MASK                    (0xFF0000U)
+#define LPSPI_CCR_PCSSCK_SHIFT                   (16U)
+/*! PCSSCK - PCS-to-SCK Delay */
+#define LPSPI_CCR_PCSSCK(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
+
+#define LPSPI_CCR_SCKPCS_MASK                    (0xFF000000U)
+#define LPSPI_CCR_SCKPCS_SHIFT                   (24U)
+/*! SCKPCS - SCK-to-PCS Delay */
+#define LPSPI_CCR_SCKPCS(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
+/*! @} */
+
+/*! @name CCR1 - Clock Configuration 1 */
+/*! @{ */
+
+#define LPSPI_CCR1_SCKSET_MASK                   (0xFFU)
+#define LPSPI_CCR1_SCKSET_SHIFT                  (0U)
+/*! SCKSET - SCK Setup */
+#define LPSPI_CCR1_SCKSET(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK)
+
+#define LPSPI_CCR1_SCKHLD_MASK                   (0xFF00U)
+#define LPSPI_CCR1_SCKHLD_SHIFT                  (8U)
+/*! SCKHLD - SCK Hold */
+#define LPSPI_CCR1_SCKHLD(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK)
+
+#define LPSPI_CCR1_PCSPCS_MASK                   (0xFF0000U)
+#define LPSPI_CCR1_PCSPCS_SHIFT                  (16U)
+/*! PCSPCS - PCS to PCS Delay */
+#define LPSPI_CCR1_PCSPCS(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK)
+
+#define LPSPI_CCR1_SCKSCK_MASK                   (0xFF000000U)
+#define LPSPI_CCR1_SCKSCK_SHIFT                  (24U)
+/*! SCKSCK - SCK Inter-Frame Delay */
+#define LPSPI_CCR1_SCKSCK(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK)
+/*! @} */
+
+/*! @name FCR - FIFO Control */
+/*! @{ */
+
+#define LPSPI_FCR_TXWATER_MASK                   (0x3U)
+#define LPSPI_FCR_TXWATER_SHIFT                  (0U)
+/*! TXWATER - Transmit FIFO Watermark */
+#define LPSPI_FCR_TXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
+
+#define LPSPI_FCR_RXWATER_MASK                   (0x30000U)
+#define LPSPI_FCR_RXWATER_SHIFT                  (16U)
+/*! RXWATER - Receive FIFO Watermark */
+#define LPSPI_FCR_RXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
+/*! @} */
+
+/*! @name FSR - FIFO Status */
+/*! @{ */
+
+#define LPSPI_FSR_TXCOUNT_MASK                   (0x7U)
+#define LPSPI_FSR_TXCOUNT_SHIFT                  (0U)
+/*! TXCOUNT - Transmit FIFO Count */
+#define LPSPI_FSR_TXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
+
+#define LPSPI_FSR_RXCOUNT_MASK                   (0x70000U)
+#define LPSPI_FSR_RXCOUNT_SHIFT                  (16U)
+/*! RXCOUNT - Receive FIFO Count */
+#define LPSPI_FSR_RXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
+/*! @} */
+
+/*! @name TCR - Transmit Command */
+/*! @{ */
+
+#define LPSPI_TCR_FRAMESZ_MASK                   (0xFFFU)
+#define LPSPI_TCR_FRAMESZ_SHIFT                  (0U)
+/*! FRAMESZ - Frame Size */
+#define LPSPI_TCR_FRAMESZ(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
+
+#define LPSPI_TCR_WIDTH_MASK                     (0x30000U)
+#define LPSPI_TCR_WIDTH_SHIFT                    (16U)
+/*! WIDTH - Transfer Width
+ *  0b00..1-bit transfer
+ *  0b01..2-bit transfer
+ *  0b10..4-bit transfer
+ *  0b11..Reserved
+ */
+#define LPSPI_TCR_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
+
+#define LPSPI_TCR_TXMSK_MASK                     (0x40000U)
+#define LPSPI_TCR_TXMSK_SHIFT                    (18U)
+/*! TXMSK - Transmit Data Mask
+ *  0b0..Normal transfer
+ *  0b1..Mask transmit data
+ */
+#define LPSPI_TCR_TXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
+
+#define LPSPI_TCR_RXMSK_MASK                     (0x80000U)
+#define LPSPI_TCR_RXMSK_SHIFT                    (19U)
+/*! RXMSK - Receive Data Mask
+ *  0b0..Normal transfer
+ *  0b1..Mask receive data
+ */
+#define LPSPI_TCR_RXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
+
+#define LPSPI_TCR_CONTC_MASK                     (0x100000U)
+#define LPSPI_TCR_CONTC_SHIFT                    (20U)
+/*! CONTC - Continuing Command
+ *  0b0..Command word for start of new transfer
+ *  0b1..Command word for continuing transfer
+ */
+#define LPSPI_TCR_CONTC(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
+
+#define LPSPI_TCR_CONT_MASK                      (0x200000U)
+#define LPSPI_TCR_CONT_SHIFT                     (21U)
+/*! CONT - Continuous Transfer
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPSPI_TCR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
+
+#define LPSPI_TCR_BYSW_MASK                      (0x400000U)
+#define LPSPI_TCR_BYSW_SHIFT                     (22U)
+/*! BYSW - Byte Swap
+ *  0b0..Disable byte swap
+ *  0b1..Enable byte swap
+ */
+#define LPSPI_TCR_BYSW(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
+
+#define LPSPI_TCR_LSBF_MASK                      (0x800000U)
+#define LPSPI_TCR_LSBF_SHIFT                     (23U)
+/*! LSBF - LSB First
+ *  0b0..MSB first
+ *  0b1..LSB first
+ */
+#define LPSPI_TCR_LSBF(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
+
+#define LPSPI_TCR_PCS_MASK                       (0x3000000U)
+#define LPSPI_TCR_PCS_SHIFT                      (24U)
+/*! PCS - Peripheral Chip Select
+ *  0b00..Transfer using PCS[0]
+ *  0b01..Transfer using PCS[1]
+ *  0b10..Transfer using PCS[2]
+ *  0b11..Transfer using PCS[3]
+ */
+#define LPSPI_TCR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
+
+#define LPSPI_TCR_PRESCALE_MASK                  (0x38000000U)
+#define LPSPI_TCR_PRESCALE_SHIFT                 (27U)
+/*! PRESCALE - Prescaler Value
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 4
+ *  0b011..Divide by 8
+ *  0b100..Divide by 16
+ *  0b101..Divide by 32
+ *  0b110..Divide by 64
+ *  0b111..Divide by 128
+ */
+#define LPSPI_TCR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
+
+#define LPSPI_TCR_CPHA_MASK                      (0x40000000U)
+#define LPSPI_TCR_CPHA_SHIFT                     (30U)
+/*! CPHA - Clock Phase
+ *  0b0..Captured
+ *  0b1..Changed
+ */
+#define LPSPI_TCR_CPHA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
+
+#define LPSPI_TCR_CPOL_MASK                      (0x80000000U)
+#define LPSPI_TCR_CPOL_SHIFT                     (31U)
+/*! CPOL - Clock Polarity
+ *  0b0..Inactive low
+ *  0b1..Inactive high
+ */
+#define LPSPI_TCR_CPOL(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
+/*! @} */
+
+/*! @name TDR - Transmit Data */
+/*! @{ */
+
+#define LPSPI_TDR_DATA_MASK                      (0xFFFFFFFFU)
+#define LPSPI_TDR_DATA_SHIFT                     (0U)
+/*! DATA - Transmit Data */
+#define LPSPI_TDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
+/*! @} */
+
+/*! @name RSR - Receive Status */
+/*! @{ */
+
+#define LPSPI_RSR_SOF_MASK                       (0x1U)
+#define LPSPI_RSR_SOF_SHIFT                      (0U)
+/*! SOF - Start of Frame
+ *  0b0..Subsequent data word or RX FIFO is empty (RXEMPTY=1).
+ *  0b1..First data word
+ */
+#define LPSPI_RSR_SOF(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
+
+#define LPSPI_RSR_RXEMPTY_MASK                   (0x2U)
+#define LPSPI_RSR_RXEMPTY_SHIFT                  (1U)
+/*! RXEMPTY - RX FIFO Empty
+ *  0b0..Not empty
+ *  0b1..Empty
+ */
+#define LPSPI_RSR_RXEMPTY(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
+/*! @} */
+
+/*! @name RDR - Receive Data */
+/*! @{ */
+
+#define LPSPI_RDR_DATA_MASK                      (0xFFFFFFFFU)
+#define LPSPI_RDR_DATA_SHIFT                     (0U)
+/*! DATA - Receive Data */
+#define LPSPI_RDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
+/*! @} */
+
+/*! @name RDROR - Receive Data Read Only */
+/*! @{ */
+
+#define LPSPI_RDROR_DATA_MASK                    (0xFFFFFFFFU)
+#define LPSPI_RDROR_DATA_SHIFT                   (0U)
+/*! DATA - Receive Data */
+#define LPSPI_RDROR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK)
+/*! @} */
+
+/*! @name TCBR - Transmit Command Burst */
+/*! @{ */
+
+#define LPSPI_TCBR_DATA_MASK                     (0xFFFFFFFFU)
+#define LPSPI_TCBR_DATA_SHIFT                    (0U)
+/*! DATA - Command Data */
+#define LPSPI_TCBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK)
+/*! @} */
+
+/*! @name TDBR - Transmit Data Burst */
+/*! @{ */
+
+#define LPSPI_TDBR_DATA_MASK                     (0xFFFFFFFFU)
+#define LPSPI_TDBR_DATA_SHIFT                    (0U)
+/*! DATA - Data */
+#define LPSPI_TDBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK)
+/*! @} */
+
+/*! @name RDBR - Receive Data Burst */
+/*! @{ */
+
+#define LPSPI_RDBR_DATA_MASK                     (0xFFFFFFFFU)
+#define LPSPI_RDBR_DATA_SHIFT                    (0U)
+/*! DATA - Data */
+#define LPSPI_RDBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPSPI_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group LPSPI_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_LPSPI_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPTMR.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPTMR.h
new file mode 100644
index 0000000000..53dd6eed47
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPTMR.h
@@ -0,0 +1,279 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for LPTMR
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_LPTMR.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for LPTMR
+ *
+ * CMSIS Peripheral Access Layer for LPTMR
+ */
+
+#if !defined(PERI_LPTMR_H_)
+#define PERI_LPTMR_H_                            /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /**< Control Status, offset: 0x0 */
+  __IO uint32_t PSR;                               /**< Prescaler and Glitch Filter, offset: 0x4 */
+  __IO uint32_t CMR;                               /**< Compare, offset: 0x8 */
+  __IO uint32_t CNR;                               /**< Counter, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/*! @name CSR - Control Status */
+/*! @{ */
+
+#define LPTMR_CSR_TEN_MASK                       (0x1U)
+#define LPTMR_CSR_TEN_SHIFT                      (0U)
+/*! TEN - Timer Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
+
+#define LPTMR_CSR_TMS_MASK                       (0x2U)
+#define LPTMR_CSR_TMS_SHIFT                      (1U)
+/*! TMS - Timer Mode Select
+ *  0b0..Time Counter
+ *  0b1..Pulse Counter
+ */
+#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
+
+#define LPTMR_CSR_TFC_MASK                       (0x4U)
+#define LPTMR_CSR_TFC_SHIFT                      (2U)
+/*! TFC - Timer Free-Running Counter
+ *  0b0..Reset when TCF asserts
+ *  0b1..Reset on overflow
+ */
+#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
+
+#define LPTMR_CSR_TPP_MASK                       (0x8U)
+#define LPTMR_CSR_TPP_SHIFT                      (3U)
+/*! TPP - Timer Pin Polarity
+ *  0b0..Active-high
+ *  0b1..Active-low
+ */
+#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
+
+#define LPTMR_CSR_TPS_MASK                       (0x30U)
+#define LPTMR_CSR_TPS_SHIFT                      (4U)
+/*! TPS - Timer Pin Select
+ *  0b00..Input 0
+ *  0b01..Input 1
+ *  0b10..Input 2
+ *  0b11..Input 3
+ */
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
+
+#define LPTMR_CSR_TIE_MASK                       (0x40U)
+#define LPTMR_CSR_TIE_SHIFT                      (6U)
+/*! TIE - Timer Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
+
+#define LPTMR_CSR_TCF_MASK                       (0x80U)
+#define LPTMR_CSR_TCF_SHIFT                      (7U)
+/*! TCF - Timer Compare Flag
+ *  0b0..CNR != (CMR + 1)
+ *  0b0..No effect
+ *  0b1..CNR = (CMR + 1)
+ *  0b1..Clear the flag
+ */
+#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
+
+#define LPTMR_CSR_TDRE_MASK                      (0x100U)
+#define LPTMR_CSR_TDRE_SHIFT                     (8U)
+/*! TDRE - Timer DMA Request Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPTMR_CSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK)
+/*! @} */
+
+/*! @name PSR - Prescaler and Glitch Filter */
+/*! @{ */
+
+#define LPTMR_PSR_PCS_MASK                       (0x3U)
+#define LPTMR_PSR_PCS_SHIFT                      (0U)
+/*! PCS - Prescaler and Glitch Filter Clock Select
+ *  0b00..Clock 0
+ *  0b01..Clock 1
+ *  0b10..Clock 2
+ *  0b11..Clock 3
+ */
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
+
+#define LPTMR_PSR_PBYP_MASK                      (0x4U)
+#define LPTMR_PSR_PBYP_SHIFT                     (2U)
+/*! PBYP - Prescaler and Glitch Filter Bypass
+ *  0b0..Prescaler and glitch filter enable
+ *  0b1..Prescaler and glitch filter bypass
+ */
+#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
+
+#define LPTMR_PSR_PRESCALE_MASK                  (0x78U)
+#define LPTMR_PSR_PRESCALE_SHIFT                 (3U)
+/*! PRESCALE - Prescaler and Glitch Filter Value
+ *  0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration
+ *  0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges
+ *  0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges
+ *  0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges
+ *  0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges
+ *  0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges
+ *  0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges
+ *  0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges
+ *  0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges
+ *  0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges
+ *  0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges
+ *  0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges
+ *  0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges
+ *  0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges
+ *  0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges
+ *  0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges
+ */
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
+/*! @} */
+
+/*! @name CMR - Compare */
+/*! @{ */
+
+#define LPTMR_CMR_COMPARE_MASK                   (0xFFFFFFFFU)
+#define LPTMR_CMR_COMPARE_SHIFT                  (0U)
+/*! COMPARE - Compare Value */
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+/*! @} */
+
+/*! @name CNR - Counter */
+/*! @{ */
+
+#define LPTMR_CNR_COUNTER_MASK                   (0xFFFFFFFFU)
+#define LPTMR_CNR_COUNTER_SHIFT                  (0U)
+/*! COUNTER - Counter Value */
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_LPTMR_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPUART.h
new file mode 100644
index 0000000000..59803584a8
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPUART.h
@@ -0,0 +1,1133 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for LPUART
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_LPUART.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for LPUART
+ *
+ * CMSIS Peripheral Access Layer for LPUART
+ */
+
+#if !defined(PERI_LPUART_H_)
+#define PERI_LPUART_H_                           /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- LPUART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
+ * @{
+ */
+
+/** LPUART - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
+  __IO uint32_t GLOBAL;                            /**< Global, offset: 0x8 */
+  __IO uint32_t PINCFG;                            /**< Pin Configuration, offset: 0xC */
+  __IO uint32_t BAUD;                              /**< Baud Rate, offset: 0x10 */
+  __IO uint32_t STAT;                              /**< Status, offset: 0x14 */
+  __IO uint32_t CTRL;                              /**< Control, offset: 0x18 */
+  __IO uint32_t DATA;                              /**< Data, offset: 0x1C */
+  __IO uint32_t MATCH;                             /**< Match Address, offset: 0x20 */
+  __IO uint32_t MODIR;                             /**< MODEM IrDA, offset: 0x24 */
+  __IO uint32_t FIFO;                              /**< FIFO, offset: 0x28 */
+  __IO uint32_t WATER;                             /**< Watermark, offset: 0x2C */
+  __I  uint32_t DATARO;                            /**< Data Read-Only, offset: 0x30 */
+} LPUART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPUART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Masks LPUART Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID */
+/*! @{ */
+
+#define LPUART_VERID_FEATURE_MASK                (0xFFFFU)
+#define LPUART_VERID_FEATURE_SHIFT               (0U)
+/*! FEATURE - Feature Identification Number
+ *  0b0000000000000001..Standard feature set
+ *  0b0000000000000011..Standard feature set with MODEM and IrDA support
+ */
+#define LPUART_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
+
+#define LPUART_VERID_MINOR_MASK                  (0xFF0000U)
+#define LPUART_VERID_MINOR_SHIFT                 (16U)
+/*! MINOR - Minor Version Number */
+#define LPUART_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
+
+#define LPUART_VERID_MAJOR_MASK                  (0xFF000000U)
+#define LPUART_VERID_MAJOR_SHIFT                 (24U)
+/*! MAJOR - Major Version Number */
+#define LPUART_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter */
+/*! @{ */
+
+#define LPUART_PARAM_TXFIFO_MASK                 (0xFFU)
+#define LPUART_PARAM_TXFIFO_SHIFT                (0U)
+/*! TXFIFO - Transmit FIFO Size */
+#define LPUART_PARAM_TXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
+
+#define LPUART_PARAM_RXFIFO_MASK                 (0xFF00U)
+#define LPUART_PARAM_RXFIFO_SHIFT                (8U)
+/*! RXFIFO - Receive FIFO Size */
+#define LPUART_PARAM_RXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
+/*! @} */
+
+/*! @name GLOBAL - Global */
+/*! @{ */
+
+#define LPUART_GLOBAL_RST_MASK                   (0x2U)
+#define LPUART_GLOBAL_RST_SHIFT                  (1U)
+/*! RST - Software Reset
+ *  0b0..Not reset
+ *  0b1..Reset
+ */
+#define LPUART_GLOBAL_RST(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
+/*! @} */
+
+/*! @name PINCFG - Pin Configuration */
+/*! @{ */
+
+#define LPUART_PINCFG_TRGSEL_MASK                (0x3U)
+#define LPUART_PINCFG_TRGSEL_SHIFT               (0U)
+/*! TRGSEL - Trigger Select
+ *  0b00..Input trigger disabled
+ *  0b01..Input trigger used instead of the RXD pin input
+ *  0b10..Input trigger used instead of the CTS_B pin input
+ *  0b11..Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger
+ */
+#define LPUART_PINCFG_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
+/*! @} */
+
+/*! @name BAUD - Baud Rate */
+/*! @{ */
+
+#define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
+#define LPUART_BAUD_SBR_SHIFT                    (0U)
+/*! SBR - Baud Rate Modulo Divisor */
+#define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
+
+#define LPUART_BAUD_SBNS_MASK                    (0x2000U)
+#define LPUART_BAUD_SBNS_SHIFT                   (13U)
+/*! SBNS - Stop Bit Number Select
+ *  0b0..One stop bit
+ *  0b1..Two stop bits
+ */
+#define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
+
+#define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
+#define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
+/*! RXEDGIE - RX Input Active Edge Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
+
+#define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
+#define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
+/*! LBKDIE - LIN Break Detect Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
+
+#define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
+#define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
+/*! RESYNCDIS - Resynchronization Disable
+ *  0b0..Enable
+ *  0b1..Disable
+ */
+#define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
+
+#define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
+#define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
+/*! BOTHEDGE - Both Edge Sampling
+ *  0b0..Rising edge
+ *  0b1..Both rising and falling edges
+ */
+#define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
+
+#define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
+#define LPUART_BAUD_MATCFG_SHIFT                 (18U)
+/*! MATCFG - Match Configuration
+ *  0b00..Address match wake-up
+ *  0b01..Idle match wake-up
+ *  0b10..Match on and match off
+ *  0b11..Enables RWU on data match and match on or off for the transmitter CTS input
+ */
+#define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
+
+#define LPUART_BAUD_RIDMAE_MASK                  (0x100000U)
+#define LPUART_BAUD_RIDMAE_SHIFT                 (20U)
+/*! RIDMAE - Receiver Idle DMA Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_BAUD_RIDMAE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
+
+#define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
+#define LPUART_BAUD_RDMAE_SHIFT                  (21U)
+/*! RDMAE - Receiver Full DMA Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
+
+#define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
+#define LPUART_BAUD_TDMAE_SHIFT                  (23U)
+/*! TDMAE - Transmitter DMA Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
+
+#define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
+#define LPUART_BAUD_OSR_SHIFT                    (24U)
+/*! OSR - Oversampling Ratio
+ *  0b00000..Results in an OSR of 16
+ *  0b00001..Reserved
+ *  0b00010..Reserved
+ *  0b00011..Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1)
+ *  0b00100..Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1)
+ *  0b00101..Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1)
+ *  0b00110..Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1)
+ *  0b00111..Results in an OSR of 8
+ *  0b01000..Results in an OSR of 9
+ *  0b01001..Results in an OSR of 10
+ *  0b01010..Results in an OSR of 11
+ *  0b01011..Results in an OSR of 12
+ *  0b01100..Results in an OSR of 13
+ *  0b01101..Results in an OSR of 14
+ *  0b01110..Results in an OSR of 15
+ *  0b01111..Results in an OSR of 16
+ *  0b10000..Results in an OSR of 17
+ *  0b10001..Results in an OSR of 18
+ *  0b10010..Results in an OSR of 19
+ *  0b10011..Results in an OSR of 20
+ *  0b10100..Results in an OSR of 21
+ *  0b10101..Results in an OSR of 22
+ *  0b10110..Results in an OSR of 23
+ *  0b10111..Results in an OSR of 24
+ *  0b11000..Results in an OSR of 25
+ *  0b11001..Results in an OSR of 26
+ *  0b11010..Results in an OSR of 27
+ *  0b11011..Results in an OSR of 28
+ *  0b11100..Results in an OSR of 29
+ *  0b11101..Results in an OSR of 30
+ *  0b11110..Results in an OSR of 31
+ *  0b11111..Results in an OSR of 32
+ */
+#define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
+
+#define LPUART_BAUD_M10_MASK                     (0x20000000U)
+#define LPUART_BAUD_M10_SHIFT                    (29U)
+/*! M10 - 10-Bit Mode Select
+ *  0b0..Receiver and transmitter use 7-bit to 9-bit data characters
+ *  0b1..Receiver and transmitter use 10-bit data characters
+ */
+#define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
+
+#define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
+#define LPUART_BAUD_MAEN2_SHIFT                  (30U)
+/*! MAEN2 - Match Address Mode Enable 2
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
+
+#define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
+#define LPUART_BAUD_MAEN1_SHIFT                  (31U)
+/*! MAEN1 - Match Address Mode Enable 1
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
+/*! @} */
+
+/*! @name STAT - Status */
+/*! @{ */
+
+#define LPUART_STAT_LBKFE_MASK                   (0x1U)
+#define LPUART_STAT_LBKFE_SHIFT                  (0U)
+/*! LBKFE - LIN Break Flag Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_STAT_LBKFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK)
+
+#define LPUART_STAT_AME_MASK                     (0x2U)
+#define LPUART_STAT_AME_SHIFT                    (1U)
+/*! AME - Address Mark Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_STAT_AME(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK)
+
+#define LPUART_STAT_MA2F_MASK                    (0x4000U)
+#define LPUART_STAT_MA2F_SHIFT                   (14U)
+/*! MA2F - Match 2 Flag
+ *  0b0..No effect
+ *  0b0..Not equal to MA2
+ *  0b1..Clear the flag
+ *  0b1..Equal to MA2
+ */
+#define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
+
+#define LPUART_STAT_MA1F_MASK                    (0x8000U)
+#define LPUART_STAT_MA1F_SHIFT                   (15U)
+/*! MA1F - Match 1 Flag
+ *  0b0..No effect
+ *  0b0..Not equal to MA1
+ *  0b1..Clear the flag
+ *  0b1..Equal to MA1
+ */
+#define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
+
+#define LPUART_STAT_PF_MASK                      (0x10000U)
+#define LPUART_STAT_PF_SHIFT                     (16U)
+/*! PF - Parity Error Flag
+ *  0b0..No effect
+ *  0b0..No parity error detected
+ *  0b1..Clear the flag
+ *  0b1..Parity error detected
+ */
+#define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
+
+#define LPUART_STAT_FE_MASK                      (0x20000U)
+#define LPUART_STAT_FE_SHIFT                     (17U)
+/*! FE - Framing Error Flag
+ *  0b0..No effect
+ *  0b0..No framing error detected (this does not guarantee that the framing is correct)
+ *  0b1..Clear the flag
+ *  0b1..Framing error detected
+ */
+#define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
+
+#define LPUART_STAT_NF_MASK                      (0x40000U)
+#define LPUART_STAT_NF_SHIFT                     (18U)
+/*! NF - Noise Flag
+ *  0b0..No effect
+ *  0b0..No noise detected
+ *  0b1..Clear the flag
+ *  0b1..Noise detected
+ */
+#define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
+
+#define LPUART_STAT_OR_MASK                      (0x80000U)
+#define LPUART_STAT_OR_SHIFT                     (19U)
+/*! OR - Receiver Overrun Flag
+ *  0b0..No effect
+ *  0b0..No overrun
+ *  0b1..Clear the flag
+ *  0b1..Receive overrun (new LPUART data is lost)
+ */
+#define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
+
+#define LPUART_STAT_IDLE_MASK                    (0x100000U)
+#define LPUART_STAT_IDLE_SHIFT                   (20U)
+/*! IDLE - Idle Line Flag
+ *  0b0..Idle line detected
+ *  0b0..No effect
+ *  0b1..Clear the flag
+ *  0b1..Idle line not detected
+ */
+#define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
+
+#define LPUART_STAT_RDRF_MASK                    (0x200000U)
+#define LPUART_STAT_RDRF_SHIFT                   (21U)
+/*! RDRF - Receive Data Register Full Flag
+ *  0b0..Equal to or less than watermark
+ *  0b1..Greater than watermark
+ */
+#define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
+
+#define LPUART_STAT_TC_MASK                      (0x400000U)
+#define LPUART_STAT_TC_SHIFT                     (22U)
+/*! TC - Transmission Complete Flag
+ *  0b0..Transmitter active
+ *  0b1..Transmitter idle
+ */
+#define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
+
+#define LPUART_STAT_TDRE_MASK                    (0x800000U)
+#define LPUART_STAT_TDRE_SHIFT                   (23U)
+/*! TDRE - Transmit Data Register Empty Flag
+ *  0b0..Greater than watermark
+ *  0b1..Equal to or less than watermark
+ */
+#define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
+
+#define LPUART_STAT_RAF_MASK                     (0x1000000U)
+#define LPUART_STAT_RAF_SHIFT                    (24U)
+/*! RAF - Receiver Active Flag
+ *  0b0..Idle, waiting for a start bit
+ *  0b1..Receiver active (RXD pin input not idle)
+ */
+#define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
+
+#define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
+#define LPUART_STAT_LBKDE_SHIFT                  (25U)
+/*! LBKDE - LIN Break Detection Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
+
+#define LPUART_STAT_BRK13_MASK                   (0x4000000U)
+#define LPUART_STAT_BRK13_SHIFT                  (26U)
+/*! BRK13 - Break Character Generation Length
+ *  0b0..9 to 13 bit times
+ *  0b1..12 to 15 bit times
+ */
+#define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
+
+#define LPUART_STAT_RWUID_MASK                   (0x8000000U)
+#define LPUART_STAT_RWUID_SHIFT                  (27U)
+/*! RWUID - Receive Wake Up Idle Detect
+ *  0b0..STAT[IDLE] does not become 1
+ *  0b1..STAT[IDLE] becomes 1
+ */
+#define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
+
+#define LPUART_STAT_RXINV_MASK                   (0x10000000U)
+#define LPUART_STAT_RXINV_SHIFT                  (28U)
+/*! RXINV - Receive Data Inversion
+ *  0b0..Inverted
+ *  0b1..Not inverted
+ */
+#define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
+
+#define LPUART_STAT_MSBF_MASK                    (0x20000000U)
+#define LPUART_STAT_MSBF_SHIFT                   (29U)
+/*! MSBF - MSB First
+ *  0b0..LSB
+ *  0b1..MSB
+ */
+#define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
+
+#define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
+#define LPUART_STAT_RXEDGIF_SHIFT                (30U)
+/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
+ *  0b0..No effect
+ *  0b0..Not occurred
+ *  0b1..Clear the flag
+ *  0b1..Occurred
+ */
+#define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
+
+#define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
+#define LPUART_STAT_LBKDIF_SHIFT                 (31U)
+/*! LBKDIF - LIN Break Detect Interrupt Flag
+ *  0b0..No effect
+ *  0b0..Not detected
+ *  0b1..Clear the flag
+ *  0b1..Detected
+ */
+#define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
+/*! @} */
+
+/*! @name CTRL - Control */
+/*! @{ */
+
+#define LPUART_CTRL_PT_MASK                      (0x1U)
+#define LPUART_CTRL_PT_SHIFT                     (0U)
+/*! PT - Parity Type
+ *  0b0..Even parity
+ *  0b1..Odd parity
+ */
+#define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
+
+#define LPUART_CTRL_PE_MASK                      (0x2U)
+#define LPUART_CTRL_PE_SHIFT                     (1U)
+/*! PE - Parity Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
+
+#define LPUART_CTRL_ILT_MASK                     (0x4U)
+#define LPUART_CTRL_ILT_SHIFT                    (2U)
+/*! ILT - Idle Line Type Select
+ *  0b0..After the start bit
+ *  0b1..After the stop bit
+ */
+#define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
+
+#define LPUART_CTRL_WAKE_MASK                    (0x8U)
+#define LPUART_CTRL_WAKE_SHIFT                   (3U)
+/*! WAKE - Receiver Wake-Up Method Select
+ *  0b0..Idle
+ *  0b1..Mark
+ */
+#define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
+
+#define LPUART_CTRL_M_MASK                       (0x10U)
+#define LPUART_CTRL_M_SHIFT                      (4U)
+/*! M - 9-Bit Or 8-Bit Mode Select
+ *  0b0..8-bit
+ *  0b1..9-bit
+ */
+#define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
+
+#define LPUART_CTRL_RSRC_MASK                    (0x20U)
+#define LPUART_CTRL_RSRC_SHIFT                   (5U)
+/*! RSRC - Receiver Source Select
+ *  0b0..Internal Loopback mode
+ *  0b1..Single-wire mode
+ */
+#define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
+
+#define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
+#define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
+/*! DOZEEN - Doze Mode
+ *  0b0..Enable
+ *  0b1..Disable
+ */
+#define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
+
+#define LPUART_CTRL_LOOPS_MASK                   (0x80U)
+#define LPUART_CTRL_LOOPS_SHIFT                  (7U)
+/*! LOOPS - Loop Mode Select
+ *  0b0..Normal operation: RXD and TXD use separate pins
+ *  0b1..Loop mode or Single-Wire mode
+ */
+#define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
+
+#define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
+#define LPUART_CTRL_IDLECFG_SHIFT                (8U)
+/*! IDLECFG - Idle Configuration
+ *  0b000..1
+ *  0b001..2
+ *  0b010..4
+ *  0b011..8
+ *  0b100..16
+ *  0b101..32
+ *  0b110..64
+ *  0b111..128
+ */
+#define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
+
+#define LPUART_CTRL_M7_MASK                      (0x800U)
+#define LPUART_CTRL_M7_SHIFT                     (11U)
+/*! M7 - 7-Bit Mode Select
+ *  0b0..8-bit to 10-bit
+ *  0b1..7-bit
+ */
+#define LPUART_CTRL_M7(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
+
+#define LPUART_CTRL_SWAP_MASK                    (0x1000U)
+#define LPUART_CTRL_SWAP_SHIFT                   (12U)
+/*! SWAP - TXD and RXD Pin Swap
+ *  0b0..Use the standard way
+ *  0b1..Swap
+ */
+#define LPUART_CTRL_SWAP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SWAP_SHIFT)) & LPUART_CTRL_SWAP_MASK)
+
+#define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
+#define LPUART_CTRL_MA2IE_SHIFT                  (14U)
+/*! MA2IE - Match 2 (MA2F) Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
+
+#define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
+#define LPUART_CTRL_MA1IE_SHIFT                  (15U)
+/*! MA1IE - Match 1 (MA1F) Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
+
+#define LPUART_CTRL_SBK_MASK                     (0x10000U)
+#define LPUART_CTRL_SBK_SHIFT                    (16U)
+/*! SBK - Send Break
+ *  0b0..Normal transmitter operation
+ *  0b1..Queue break character(s) to be sent
+ */
+#define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
+
+#define LPUART_CTRL_RWU_MASK                     (0x20000U)
+#define LPUART_CTRL_RWU_SHIFT                    (17U)
+/*! RWU - Receiver Wake-Up Control
+ *  0b0..Normal receiver operation
+ *  0b1..LPUART receiver in standby, waiting for a wake-up condition
+ */
+#define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
+
+#define LPUART_CTRL_RE_MASK                      (0x40000U)
+#define LPUART_CTRL_RE_SHIFT                     (18U)
+/*! RE - Receiver Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
+
+#define LPUART_CTRL_TE_MASK                      (0x80000U)
+#define LPUART_CTRL_TE_SHIFT                     (19U)
+/*! TE - Transmitter Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
+
+#define LPUART_CTRL_ILIE_MASK                    (0x100000U)
+#define LPUART_CTRL_ILIE_SHIFT                   (20U)
+/*! ILIE - Idle Line Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
+
+#define LPUART_CTRL_RIE_MASK                     (0x200000U)
+#define LPUART_CTRL_RIE_SHIFT                    (21U)
+/*! RIE - Receiver Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
+
+#define LPUART_CTRL_TCIE_MASK                    (0x400000U)
+#define LPUART_CTRL_TCIE_SHIFT                   (22U)
+/*! TCIE - Transmission Complete Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
+
+#define LPUART_CTRL_TIE_MASK                     (0x800000U)
+#define LPUART_CTRL_TIE_SHIFT                    (23U)
+/*! TIE - Transmit Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
+
+#define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
+#define LPUART_CTRL_PEIE_SHIFT                   (24U)
+/*! PEIE - Parity Error Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
+
+#define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
+#define LPUART_CTRL_FEIE_SHIFT                   (25U)
+/*! FEIE - Framing Error Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
+
+#define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
+#define LPUART_CTRL_NEIE_SHIFT                   (26U)
+/*! NEIE - Noise Error Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
+
+#define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
+#define LPUART_CTRL_ORIE_SHIFT                   (27U)
+/*! ORIE - Overrun Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
+
+#define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
+#define LPUART_CTRL_TXINV_SHIFT                  (28U)
+/*! TXINV - Transmit Data Inversion
+ *  0b0..Not inverted
+ *  0b1..Inverted
+ */
+#define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
+
+#define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
+#define LPUART_CTRL_TXDIR_SHIFT                  (29U)
+/*! TXDIR - TXD Pin Direction in Single-Wire Mode
+ *  0b0..Input
+ *  0b1..Output
+ */
+#define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
+
+#define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
+#define LPUART_CTRL_R9T8_SHIFT                   (30U)
+/*! R9T8 - Receive Bit 9 Transmit Bit 8 */
+#define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
+
+#define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
+#define LPUART_CTRL_R8T9_SHIFT                   (31U)
+/*! R8T9 - Receive Bit 8 Transmit Bit 9 */
+#define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
+/*! @} */
+
+/*! @name DATA - Data */
+/*! @{ */
+
+#define LPUART_DATA_R0T0_MASK                    (0x1U)
+#define LPUART_DATA_R0T0_SHIFT                   (0U)
+/*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */
+#define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
+
+#define LPUART_DATA_R1T1_MASK                    (0x2U)
+#define LPUART_DATA_R1T1_SHIFT                   (1U)
+/*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */
+#define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
+
+#define LPUART_DATA_R2T2_MASK                    (0x4U)
+#define LPUART_DATA_R2T2_SHIFT                   (2U)
+/*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */
+#define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
+
+#define LPUART_DATA_R3T3_MASK                    (0x8U)
+#define LPUART_DATA_R3T3_SHIFT                   (3U)
+/*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */
+#define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
+
+#define LPUART_DATA_R4T4_MASK                    (0x10U)
+#define LPUART_DATA_R4T4_SHIFT                   (4U)
+/*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */
+#define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
+
+#define LPUART_DATA_R5T5_MASK                    (0x20U)
+#define LPUART_DATA_R5T5_SHIFT                   (5U)
+/*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */
+#define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
+
+#define LPUART_DATA_R6T6_MASK                    (0x40U)
+#define LPUART_DATA_R6T6_SHIFT                   (6U)
+/*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */
+#define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
+
+#define LPUART_DATA_R7T7_MASK                    (0x80U)
+#define LPUART_DATA_R7T7_SHIFT                   (7U)
+/*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */
+#define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
+
+#define LPUART_DATA_R8T8_MASK                    (0x100U)
+#define LPUART_DATA_R8T8_SHIFT                   (8U)
+/*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */
+#define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
+
+#define LPUART_DATA_R9T9_MASK                    (0x200U)
+#define LPUART_DATA_R9T9_SHIFT                   (9U)
+/*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */
+#define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
+
+#define LPUART_DATA_LINBRK_MASK                  (0x400U)
+#define LPUART_DATA_LINBRK_SHIFT                 (10U)
+/*! LINBRK - LIN Break
+ *  0b0..Not detected
+ *  0b1..Detected
+ */
+#define LPUART_DATA_LINBRK(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK)
+
+#define LPUART_DATA_IDLINE_MASK                  (0x800U)
+#define LPUART_DATA_IDLINE_SHIFT                 (11U)
+/*! IDLINE - Idle Line
+ *  0b0..Not idle
+ *  0b1..Idle
+ */
+#define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
+
+#define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
+#define LPUART_DATA_RXEMPT_SHIFT                 (12U)
+/*! RXEMPT - Receive Buffer Empty
+ *  0b0..Valid data
+ *  0b1..Invalid data and empty
+ */
+#define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
+
+#define LPUART_DATA_FRETSC_MASK                  (0x2000U)
+#define LPUART_DATA_FRETSC_SHIFT                 (13U)
+/*! FRETSC - Frame Error Transmit Special Character
+ *  0b0..Received without a frame error on reads or transmits a normal character on writes
+ *  0b1..Received with a frame error on reads or transmits an idle or break character on writes
+ */
+#define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
+
+#define LPUART_DATA_PARITYE_MASK                 (0x4000U)
+#define LPUART_DATA_PARITYE_SHIFT                (14U)
+/*! PARITYE - Parity Error
+ *  0b0..Received without a parity error
+ *  0b1..Received with a parity error
+ */
+#define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
+
+#define LPUART_DATA_NOISY_MASK                   (0x8000U)
+#define LPUART_DATA_NOISY_SHIFT                  (15U)
+/*! NOISY - Noisy Data Received
+ *  0b0..Received without noise
+ *  0b1..Received with noise
+ */
+#define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
+/*! @} */
+
+/*! @name MATCH - Match Address */
+/*! @{ */
+
+#define LPUART_MATCH_MA1_MASK                    (0x3FFU)
+#define LPUART_MATCH_MA1_SHIFT                   (0U)
+/*! MA1 - Match Address 1 */
+#define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
+
+#define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
+#define LPUART_MATCH_MA2_SHIFT                   (16U)
+/*! MA2 - Match Address 2 */
+#define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
+/*! @} */
+
+/*! @name MODIR - MODEM IrDA */
+/*! @{ */
+
+#define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
+#define LPUART_MODIR_TXCTSE_SHIFT                (0U)
+/*! TXCTSE - Transmitter CTS Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
+
+#define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
+#define LPUART_MODIR_TXRTSE_SHIFT                (1U)
+/*! TXRTSE - Transmitter RTS Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
+
+#define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
+#define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
+/*! TXRTSPOL - Transmitter RTS Polarity
+ *  0b0..Active low
+ *  0b1..Active high
+ */
+#define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
+
+#define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
+#define LPUART_MODIR_RXRTSE_SHIFT                (3U)
+/*! RXRTSE - Receiver RTS Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
+
+#define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
+#define LPUART_MODIR_TXCTSC_SHIFT                (4U)
+/*! TXCTSC - Transmit CTS Configuration
+ *  0b0..Sampled at the start of each character
+ *  0b1..Sampled when the transmitter is idle
+ */
+#define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
+
+#define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
+#define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
+/*! TXCTSSRC - Transmit CTS Source
+ *  0b0..The CTS_B pin
+ *  0b1..An internal connection to the receiver address match result
+ */
+#define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
+
+#define LPUART_MODIR_RTSWATER_MASK               (0x300U)
+#define LPUART_MODIR_RTSWATER_SHIFT              (8U)
+/*! RTSWATER - Receive RTS Configuration */
+#define LPUART_MODIR_RTSWATER(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
+
+#define LPUART_MODIR_TNP_MASK                    (0x30000U)
+#define LPUART_MODIR_TNP_SHIFT                   (16U)
+/*! TNP - Transmitter Narrow Pulse
+ *  0b00..1 / OSR
+ *  0b01..2 / OSR
+ *  0b10..3 / OSR
+ *  0b11..4 / OSR
+ */
+#define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
+
+#define LPUART_MODIR_IREN_MASK                   (0x40000U)
+#define LPUART_MODIR_IREN_SHIFT                  (18U)
+/*! IREN - IR Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
+/*! @} */
+
+/*! @name FIFO - FIFO */
+/*! @{ */
+
+#define LPUART_FIFO_RXFIFOSIZE_MASK              (0x7U)
+#define LPUART_FIFO_RXFIFOSIZE_SHIFT             (0U)
+/*! RXFIFOSIZE - Receive FIFO Buffer Depth
+ *  0b000..1
+ *  0b001..4
+ *  0b010..8
+ *  0b011..16
+ *  0b100..32
+ *  0b101..64
+ *  0b110..128
+ *  0b111..256
+ */
+#define LPUART_FIFO_RXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
+
+#define LPUART_FIFO_RXFE_MASK                    (0x8U)
+#define LPUART_FIFO_RXFE_SHIFT                   (3U)
+/*! RXFE - Receive FIFO Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_FIFO_RXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
+
+#define LPUART_FIFO_TXFIFOSIZE_MASK              (0x70U)
+#define LPUART_FIFO_TXFIFOSIZE_SHIFT             (4U)
+/*! TXFIFOSIZE - Transmit FIFO Buffer Depth
+ *  0b000..1
+ *  0b001..4
+ *  0b010..8
+ *  0b011..16
+ *  0b100..32
+ *  0b101..64
+ *  0b110..128
+ *  0b111..256
+ */
+#define LPUART_FIFO_TXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
+
+#define LPUART_FIFO_TXFE_MASK                    (0x80U)
+#define LPUART_FIFO_TXFE_SHIFT                   (7U)
+/*! TXFE - Transmit FIFO Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_FIFO_TXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
+
+#define LPUART_FIFO_RXUFE_MASK                   (0x100U)
+#define LPUART_FIFO_RXUFE_SHIFT                  (8U)
+/*! RXUFE - Receive FIFO Underflow Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_FIFO_RXUFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
+
+#define LPUART_FIFO_TXOFE_MASK                   (0x200U)
+#define LPUART_FIFO_TXOFE_SHIFT                  (9U)
+/*! TXOFE - Transmit FIFO Overflow Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define LPUART_FIFO_TXOFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
+
+#define LPUART_FIFO_RXIDEN_MASK                  (0x1C00U)
+#define LPUART_FIFO_RXIDEN_SHIFT                 (10U)
+/*! RXIDEN - Receiver Idle Empty Enable
+ *  0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle
+ *  0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character
+ *  0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters
+ *  0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters
+ *  0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters
+ *  0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters
+ *  0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters
+ *  0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters
+ */
+#define LPUART_FIFO_RXIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
+
+#define LPUART_FIFO_RXFLUSH_MASK                 (0x4000U)
+#define LPUART_FIFO_RXFLUSH_SHIFT                (14U)
+/*! RXFLUSH - Receive FIFO Flush
+ *  0b0..No effect
+ *  0b1..All data flushed out
+ */
+#define LPUART_FIFO_RXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
+
+#define LPUART_FIFO_TXFLUSH_MASK                 (0x8000U)
+#define LPUART_FIFO_TXFLUSH_SHIFT                (15U)
+/*! TXFLUSH - Transmit FIFO Flush
+ *  0b0..No effect
+ *  0b1..All data flushed out
+ */
+#define LPUART_FIFO_TXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
+
+#define LPUART_FIFO_RXUF_MASK                    (0x10000U)
+#define LPUART_FIFO_RXUF_SHIFT                   (16U)
+/*! RXUF - Receiver FIFO Underflow Flag
+ *  0b0..No effect
+ *  0b0..No underflow
+ *  0b1..Clear the flag
+ *  0b1..Underflow
+ */
+#define LPUART_FIFO_RXUF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
+
+#define LPUART_FIFO_TXOF_MASK                    (0x20000U)
+#define LPUART_FIFO_TXOF_SHIFT                   (17U)
+/*! TXOF - Transmitter FIFO Overflow Flag
+ *  0b0..No effect
+ *  0b0..No overflow
+ *  0b1..Clear the flag
+ *  0b1..Overflow
+ */
+#define LPUART_FIFO_TXOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
+
+#define LPUART_FIFO_RXEMPT_MASK                  (0x400000U)
+#define LPUART_FIFO_RXEMPT_SHIFT                 (22U)
+/*! RXEMPT - Receive FIFO Or Buffer Empty
+ *  0b0..Not empty
+ *  0b1..Empty
+ */
+#define LPUART_FIFO_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
+
+#define LPUART_FIFO_TXEMPT_MASK                  (0x800000U)
+#define LPUART_FIFO_TXEMPT_SHIFT                 (23U)
+/*! TXEMPT - Transmit FIFO Or Buffer Empty
+ *  0b0..Not empty
+ *  0b1..Empty
+ */
+#define LPUART_FIFO_TXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
+/*! @} */
+
+/*! @name WATER - Watermark */
+/*! @{ */
+
+#define LPUART_WATER_TXWATER_MASK                (0x3U)
+#define LPUART_WATER_TXWATER_SHIFT               (0U)
+/*! TXWATER - Transmit Watermark */
+#define LPUART_WATER_TXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
+
+#define LPUART_WATER_TXCOUNT_MASK                (0x700U)
+#define LPUART_WATER_TXCOUNT_SHIFT               (8U)
+/*! TXCOUNT - Transmit Counter */
+#define LPUART_WATER_TXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
+
+#define LPUART_WATER_RXWATER_MASK                (0x30000U)
+#define LPUART_WATER_RXWATER_SHIFT               (16U)
+/*! RXWATER - Receive Watermark */
+#define LPUART_WATER_RXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
+
+#define LPUART_WATER_RXCOUNT_MASK                (0x7000000U)
+#define LPUART_WATER_RXCOUNT_SHIFT               (24U)
+/*! RXCOUNT - Receive Counter */
+#define LPUART_WATER_RXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
+/*! @} */
+
+/*! @name DATARO - Data Read-Only */
+/*! @{ */
+
+#define LPUART_DATARO_DATA_MASK                  (0xFFFFU)
+#define LPUART_DATARO_DATA_SHIFT                 (0U)
+/*! DATA - Receive Data */
+#define LPUART_DATARO_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group LPUART_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_LPUART_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_MAU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_MAU.h
new file mode 100644
index 0000000000..5856b158fd
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_MAU.h
@@ -0,0 +1,598 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MAU
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_MAU.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for MAU
+ *
+ * CMSIS Peripheral Access Layer for MAU
+ */
+
+#if !defined(PERI_MAU_H_)
+#define PERI_MAU_H_                              /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- MAU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MAU_Peripheral_Access_Layer MAU Peripheral Access Layer
+ * @{
+ */
+
+/** MAU - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[2064];
+  __IO uint32_t SYS_CTLR;                          /**< System Control, offset: 0x810 */
+  __IO uint32_t GEXP_STATUS_IE;                    /**< General Exception Status Interrupt Enable, offset: 0x814 */
+  __IO uint32_t GEXP_STATUS;                       /**< General Exception Status, offset: 0x818 */
+       uint8_t RESERVED_1[20];
+  __IO uint32_t OP_CTRL;                           /**< Operation Control, offset: 0x830 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t RES_STATUS_IE;                     /**< Result Status Interrupt Enable, offset: 0x838 */
+  __IO uint32_t RES_STATUS;                        /**< Result Status, offset: 0x83C */
+  __IO uint32_t RES0;                              /**< Result Register 0, offset: 0x840 */
+  __IO uint32_t RES1;                              /**< Result Register 1, offset: 0x844 */
+  __IO uint32_t RES2;                              /**< Result Register 2, offset: 0x848 */
+  __IO uint32_t RES3;                              /**< Result Register 3, offset: 0x84C */
+} MAU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MAU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MAU_Register_Masks MAU Register Masks
+ * @{
+ */
+
+/*! @name SYS_CTLR - System Control */
+/*! @{ */
+
+#define MAU_SYS_CTLR_ACG_EN_MASK                 (0x1U)
+#define MAU_SYS_CTLR_ACG_EN_SHIFT                (0U)
+/*! ACG_EN - Automatic Clock Gating Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define MAU_SYS_CTLR_ACG_EN(x)                   (((uint32_t)(((uint32_t)(x)) << MAU_SYS_CTLR_ACG_EN_SHIFT)) & MAU_SYS_CTLR_ACG_EN_MASK)
+/*! @} */
+
+/*! @name GEXP_STATUS_IE - General Exception Status Interrupt Enable */
+/*! @{ */
+
+#define MAU_GEXP_STATUS_IE_ERROR_IE_MASK         (0x1U)
+#define MAU_GEXP_STATUS_IE_ERROR_IE_SHIFT        (0U)
+/*! ERROR_IE - Direct operation Error Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define MAU_GEXP_STATUS_IE_ERROR_IE(x)           (((uint32_t)(((uint32_t)(x)) << MAU_GEXP_STATUS_IE_ERROR_IE_SHIFT)) & MAU_GEXP_STATUS_IE_ERROR_IE_MASK)
+/*! @} */
+
+/*! @name GEXP_STATUS - General Exception Status */
+/*! @{ */
+
+#define MAU_GEXP_STATUS_ERROR_MASK               (0x1U)
+#define MAU_GEXP_STATUS_ERROR_SHIFT              (0U)
+/*! ERROR - Direct operation Error
+ *  0b0..No error is generated.
+ *  0b1..An error is generated.
+ */
+#define MAU_GEXP_STATUS_ERROR(x)                 (((uint32_t)(((uint32_t)(x)) << MAU_GEXP_STATUS_ERROR_SHIFT)) & MAU_GEXP_STATUS_ERROR_MASK)
+/*! @} */
+
+/*! @name OP_CTRL - Operation Control */
+/*! @{ */
+
+#define MAU_OP_CTRL_OVDT_EN_RES0_MASK            (0x1U)
+#define MAU_OP_CTRL_OVDT_EN_RES0_SHIFT           (0U)
+/*! OVDT_EN_RES0 - Override RES0 Data Type Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define MAU_OP_CTRL_OVDT_EN_RES0(x)              (((uint32_t)(((uint32_t)(x)) << MAU_OP_CTRL_OVDT_EN_RES0_SHIFT)) & MAU_OP_CTRL_OVDT_EN_RES0_MASK)
+
+#define MAU_OP_CTRL_OVDT_RES0_MASK               (0x6U)
+#define MAU_OP_CTRL_OVDT_RES0_SHIFT              (1U)
+/*! OVDT_RES0 - Override RES0 Data Type
+ *  0b00..UINT
+ *  0b01..INT
+ *  0b10..Q1.X
+ *  0b11..FLOAT
+ */
+#define MAU_OP_CTRL_OVDT_RES0(x)                 (((uint32_t)(((uint32_t)(x)) << MAU_OP_CTRL_OVDT_RES0_SHIFT)) & MAU_OP_CTRL_OVDT_RES0_MASK)
+
+#define MAU_OP_CTRL_OVDT_EN_RES1_MASK            (0x100U)
+#define MAU_OP_CTRL_OVDT_EN_RES1_SHIFT           (8U)
+/*! OVDT_EN_RES1 - Override RES1 Data Type Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define MAU_OP_CTRL_OVDT_EN_RES1(x)              (((uint32_t)(((uint32_t)(x)) << MAU_OP_CTRL_OVDT_EN_RES1_SHIFT)) & MAU_OP_CTRL_OVDT_EN_RES1_MASK)
+
+#define MAU_OP_CTRL_OVDT_RES1_MASK               (0x600U)
+#define MAU_OP_CTRL_OVDT_RES1_SHIFT              (9U)
+/*! OVDT_RES1 - Override RES1 Data Type
+ *  0b00..UINT
+ *  0b01..INT
+ *  0b10..Q1.X
+ *  0b11..FLOAT
+ */
+#define MAU_OP_CTRL_OVDT_RES1(x)                 (((uint32_t)(((uint32_t)(x)) << MAU_OP_CTRL_OVDT_RES1_SHIFT)) & MAU_OP_CTRL_OVDT_RES1_MASK)
+
+#define MAU_OP_CTRL_OVDT_EN_RES2_MASK            (0x10000U)
+#define MAU_OP_CTRL_OVDT_EN_RES2_SHIFT           (16U)
+/*! OVDT_EN_RES2 - Override RES2 Data Type Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define MAU_OP_CTRL_OVDT_EN_RES2(x)              (((uint32_t)(((uint32_t)(x)) << MAU_OP_CTRL_OVDT_EN_RES2_SHIFT)) & MAU_OP_CTRL_OVDT_EN_RES2_MASK)
+
+#define MAU_OP_CTRL_OVDT_RES2_MASK               (0x60000U)
+#define MAU_OP_CTRL_OVDT_RES2_SHIFT              (17U)
+/*! OVDT_RES2 - Override RES2 Data Type
+ *  0b00..UINT
+ *  0b01..INT
+ *  0b10..Q1.X
+ *  0b11..FLOAT
+ */
+#define MAU_OP_CTRL_OVDT_RES2(x)                 (((uint32_t)(((uint32_t)(x)) << MAU_OP_CTRL_OVDT_RES2_SHIFT)) & MAU_OP_CTRL_OVDT_RES2_MASK)
+
+#define MAU_OP_CTRL_OVDT_EN_RES3_MASK            (0x1000000U)
+#define MAU_OP_CTRL_OVDT_EN_RES3_SHIFT           (24U)
+/*! OVDT_EN_RES3 - Override RES3 Data Type Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define MAU_OP_CTRL_OVDT_EN_RES3(x)              (((uint32_t)(((uint32_t)(x)) << MAU_OP_CTRL_OVDT_EN_RES3_SHIFT)) & MAU_OP_CTRL_OVDT_EN_RES3_MASK)
+
+#define MAU_OP_CTRL_OVDT_RES3_MASK               (0x6000000U)
+#define MAU_OP_CTRL_OVDT_RES3_SHIFT              (25U)
+/*! OVDT_RES3 - Override RES3 Data Type
+ *  0b00..UINT
+ *  0b01..INT
+ *  0b10..Q1.X
+ *  0b11..FLOAT
+ */
+#define MAU_OP_CTRL_OVDT_RES3(x)                 (((uint32_t)(((uint32_t)(x)) << MAU_OP_CTRL_OVDT_RES3_SHIFT)) & MAU_OP_CTRL_OVDT_RES3_MASK)
+/*! @} */
+
+/*! @name RES_STATUS_IE - Result Status Interrupt Enable */
+/*! @{ */
+
+#define MAU_RES_STATUS_IE_RES0_IE_MASK           (0x1U)
+#define MAU_RES_STATUS_IE_RES0_IE_SHIFT          (0U)
+/*! RES0_IE - RES0 Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define MAU_RES_STATUS_IE_RES0_IE(x)             (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_IE_RES0_IE_SHIFT)) & MAU_RES_STATUS_IE_RES0_IE_MASK)
+
+#define MAU_RES_STATUS_IE_RES1_IE_MASK           (0x2U)
+#define MAU_RES_STATUS_IE_RES1_IE_SHIFT          (1U)
+/*! RES1_IE - RES1 Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define MAU_RES_STATUS_IE_RES1_IE(x)             (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_IE_RES1_IE_SHIFT)) & MAU_RES_STATUS_IE_RES1_IE_MASK)
+
+#define MAU_RES_STATUS_IE_RES2_IE_MASK           (0x4U)
+#define MAU_RES_STATUS_IE_RES2_IE_SHIFT          (2U)
+/*! RES2_IE - RES2 Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define MAU_RES_STATUS_IE_RES2_IE(x)             (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_IE_RES2_IE_SHIFT)) & MAU_RES_STATUS_IE_RES2_IE_MASK)
+
+#define MAU_RES_STATUS_IE_RES3_IE_MASK           (0x8U)
+#define MAU_RES_STATUS_IE_RES3_IE_SHIFT          (3U)
+/*! RES3_IE - RES3 Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define MAU_RES_STATUS_IE_RES3_IE(x)             (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_IE_RES3_IE_SHIFT)) & MAU_RES_STATUS_IE_RES3_IE_MASK)
+/*! @} */
+
+/*! @name RES_STATUS - Result Status */
+/*! @{ */
+
+#define MAU_RES_STATUS_RES0_NX_MASK              (0x1U)
+#define MAU_RES_STATUS_RES0_NX_SHIFT             (0U)
+/*! RES0_NX - RES0 IEEE Inexact Flag
+ *  0b0..The result is not rounded.
+ *  0b1..The result is rounded, and as a result some digits lost.
+ */
+#define MAU_RES_STATUS_RES0_NX(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES0_NX_SHIFT)) & MAU_RES_STATUS_RES0_NX_MASK)
+
+#define MAU_RES_STATUS_RES0_UF_MASK              (0x2U)
+#define MAU_RES_STATUS_RES0_UF_SHIFT             (1U)
+/*! RES0_UF - RES0 IEEE Underflow Flag
+ *  0b0..No tiny non-zero result is detected.
+ *  0b1..A tiny non-zero result is detected.
+ */
+#define MAU_RES_STATUS_RES0_UF(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES0_UF_SHIFT)) & MAU_RES_STATUS_RES0_UF_MASK)
+
+#define MAU_RES_STATUS_RES0_OF_MASK              (0x4U)
+#define MAU_RES_STATUS_RES0_OF_SHIFT             (2U)
+/*! RES0_OF - RES0 IEEE Overflow Flag
+ *  0b0..The result format's largest finite number is not exceeded.
+ *  0b1..The result format's largest finite number is exceeded.
+ */
+#define MAU_RES_STATUS_RES0_OF(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES0_OF_SHIFT)) & MAU_RES_STATUS_RES0_OF_MASK)
+
+#define MAU_RES_STATUS_RES0_DZ_MASK              (0x8U)
+#define MAU_RES_STATUS_RES0_DZ_SHIFT             (3U)
+/*! RES0_DZ - RES0 IEEE Divide by Zero Flag
+ *  0b0..No exact infinite result is defined for an operation on finite operands.
+ *  0b1..An exact infinite result is defined for an operation on finite operands.
+ */
+#define MAU_RES_STATUS_RES0_DZ(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES0_DZ_SHIFT)) & MAU_RES_STATUS_RES0_DZ_MASK)
+
+#define MAU_RES_STATUS_RES0_NV_MASK              (0x10U)
+#define MAU_RES_STATUS_RES0_NV_SHIFT             (4U)
+/*! RES0_NV - RES0 IEEE Invalid Flag
+ *  0b0..There is usefully definable result.
+ *  0b1..There is no usefully definable result.
+ */
+#define MAU_RES_STATUS_RES0_NV(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES0_NV_SHIFT)) & MAU_RES_STATUS_RES0_NV_MASK)
+
+#define MAU_RES_STATUS_RES0_ERR_MASK             (0x20U)
+#define MAU_RES_STATUS_RES0_ERR_SHIFT            (5U)
+/*! RES0_ERR - RES0 Indirect Operation Error Flag
+ *  0b0..No invalid indirect operation is detected.
+ *  0b1..An invalid indirect operation error is detected.
+ */
+#define MAU_RES_STATUS_RES0_ERR(x)               (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES0_ERR_SHIFT)) & MAU_RES_STATUS_RES0_ERR_MASK)
+
+#define MAU_RES_STATUS_RES0_OVWR_MASK            (0x40U)
+#define MAU_RES_STATUS_RES0_OVWR_SHIFT           (6U)
+/*! RES0_OVWR - RES0 Overwrite Flag
+ *  0b0..The value of RES0 has been read.
+ *  0b1..The value of RES0 has not been read yet and is overwritten by a new MAUWRAP result.
+ */
+#define MAU_RES_STATUS_RES0_OVWR(x)              (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES0_OVWR_SHIFT)) & MAU_RES_STATUS_RES0_OVWR_MASK)
+
+#define MAU_RES_STATUS_RES0_FULL_MASK            (0x80U)
+#define MAU_RES_STATUS_RES0_FULL_SHIFT           (7U)
+/*! RES0_FULL - RES0 Full Flag
+ *  0b0..RES0 has not updated and cannot be read.
+ *  0b1..RES0 has updated and can be read.
+ */
+#define MAU_RES_STATUS_RES0_FULL(x)              (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES0_FULL_SHIFT)) & MAU_RES_STATUS_RES0_FULL_MASK)
+
+#define MAU_RES_STATUS_RES1_NX_MASK              (0x100U)
+#define MAU_RES_STATUS_RES1_NX_SHIFT             (8U)
+/*! RES1_NX - RES1 IEEE Inexact Flag
+ *  0b0..The result is not rounded.
+ *  0b1..The result is rounded, and as a result some digits lost.
+ */
+#define MAU_RES_STATUS_RES1_NX(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES1_NX_SHIFT)) & MAU_RES_STATUS_RES1_NX_MASK)
+
+#define MAU_RES_STATUS_RES1_UF_MASK              (0x200U)
+#define MAU_RES_STATUS_RES1_UF_SHIFT             (9U)
+/*! RES1_UF - RES1 IEEE Underflow Flag
+ *  0b0..No tiny non-zero result is detected.
+ *  0b1..A tiny non-zero result is detected.
+ */
+#define MAU_RES_STATUS_RES1_UF(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES1_UF_SHIFT)) & MAU_RES_STATUS_RES1_UF_MASK)
+
+#define MAU_RES_STATUS_RES1_OF_MASK              (0x400U)
+#define MAU_RES_STATUS_RES1_OF_SHIFT             (10U)
+/*! RES1_OF - RES1 IEEE Overflow Flag
+ *  0b0..The result format's largest finite number is not exceeded.
+ *  0b1..The result format's largest finite number is exceeded.
+ */
+#define MAU_RES_STATUS_RES1_OF(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES1_OF_SHIFT)) & MAU_RES_STATUS_RES1_OF_MASK)
+
+#define MAU_RES_STATUS_RES1_DZ_MASK              (0x800U)
+#define MAU_RES_STATUS_RES1_DZ_SHIFT             (11U)
+/*! RES1_DZ - RES1 IEEE Divide by Zero Flag
+ *  0b0..No exact infinite result is defined for an operation on finite operands.
+ *  0b1..An exact infinite result is defined for an operation on finite operands.
+ */
+#define MAU_RES_STATUS_RES1_DZ(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES1_DZ_SHIFT)) & MAU_RES_STATUS_RES1_DZ_MASK)
+
+#define MAU_RES_STATUS_RES1_NV_MASK              (0x1000U)
+#define MAU_RES_STATUS_RES1_NV_SHIFT             (12U)
+/*! RES1_NV - RES1 IEEE Invalid Flag
+ *  0b0..There is usefully definable result.
+ *  0b1..There is no usefully definable result.
+ */
+#define MAU_RES_STATUS_RES1_NV(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES1_NV_SHIFT)) & MAU_RES_STATUS_RES1_NV_MASK)
+
+#define MAU_RES_STATUS_RES1_ERR_MASK             (0x2000U)
+#define MAU_RES_STATUS_RES1_ERR_SHIFT            (13U)
+/*! RES1_ERR - RES1 Indirect Operation Error Flag
+ *  0b0..No invalid indirect operation is detected.
+ *  0b1..An invalid indirect operation error is detected.
+ */
+#define MAU_RES_STATUS_RES1_ERR(x)               (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES1_ERR_SHIFT)) & MAU_RES_STATUS_RES1_ERR_MASK)
+
+#define MAU_RES_STATUS_RES1_OVWR_MASK            (0x4000U)
+#define MAU_RES_STATUS_RES1_OVWR_SHIFT           (14U)
+/*! RES1_OVWR - RES1 Overwrite Flag
+ *  0b0..The value of RES1 has been read.
+ *  0b1..The value of RES1 has not been read yet and is overwritten by a new MAUWRAP result.
+ */
+#define MAU_RES_STATUS_RES1_OVWR(x)              (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES1_OVWR_SHIFT)) & MAU_RES_STATUS_RES1_OVWR_MASK)
+
+#define MAU_RES_STATUS_RES1_FULL_MASK            (0x8000U)
+#define MAU_RES_STATUS_RES1_FULL_SHIFT           (15U)
+/*! RES1_FULL - RES1 Full Flag
+ *  0b0..RES1 has not updated and cannot be read.
+ *  0b1..RES1 has updated and can be read.
+ */
+#define MAU_RES_STATUS_RES1_FULL(x)              (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES1_FULL_SHIFT)) & MAU_RES_STATUS_RES1_FULL_MASK)
+
+#define MAU_RES_STATUS_RES2_NX_MASK              (0x10000U)
+#define MAU_RES_STATUS_RES2_NX_SHIFT             (16U)
+/*! RES2_NX - RES2 IEEE Inexact Flag
+ *  0b0..The result is not rounded.
+ *  0b1..The result is rounded, and as a result some digits lost.
+ */
+#define MAU_RES_STATUS_RES2_NX(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES2_NX_SHIFT)) & MAU_RES_STATUS_RES2_NX_MASK)
+
+#define MAU_RES_STATUS_RES2_UF_MASK              (0x20000U)
+#define MAU_RES_STATUS_RES2_UF_SHIFT             (17U)
+/*! RES2_UF - RES2 IEEE Underflow Flag
+ *  0b0..No tiny non-zero result is detected.
+ *  0b1..A tiny non-zero result is detected.
+ */
+#define MAU_RES_STATUS_RES2_UF(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES2_UF_SHIFT)) & MAU_RES_STATUS_RES2_UF_MASK)
+
+#define MAU_RES_STATUS_RES2_OF_MASK              (0x40000U)
+#define MAU_RES_STATUS_RES2_OF_SHIFT             (18U)
+/*! RES2_OF - RES2 IEEE Overflow Flag
+ *  0b0..The result format's largest finite number is not exceeded.
+ *  0b1..The result format's largest finite number is exceeded.
+ */
+#define MAU_RES_STATUS_RES2_OF(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES2_OF_SHIFT)) & MAU_RES_STATUS_RES2_OF_MASK)
+
+#define MAU_RES_STATUS_RES2_DZ_MASK              (0x80000U)
+#define MAU_RES_STATUS_RES2_DZ_SHIFT             (19U)
+/*! RES2_DZ - RES2 IEEE Divide by Zero Flag
+ *  0b0..No exact infinite result is defined for an operation on finite operands.
+ *  0b1..An exact infinite result is defined for an operation on finite operands.
+ */
+#define MAU_RES_STATUS_RES2_DZ(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES2_DZ_SHIFT)) & MAU_RES_STATUS_RES2_DZ_MASK)
+
+#define MAU_RES_STATUS_RES2_NV_MASK              (0x100000U)
+#define MAU_RES_STATUS_RES2_NV_SHIFT             (20U)
+/*! RES2_NV - RES2 IEEE Invalid Flag
+ *  0b0..There is usefully definable result.
+ *  0b1..There is no usefully definable result.
+ */
+#define MAU_RES_STATUS_RES2_NV(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES2_NV_SHIFT)) & MAU_RES_STATUS_RES2_NV_MASK)
+
+#define MAU_RES_STATUS_RES2_ERR_MASK             (0x200000U)
+#define MAU_RES_STATUS_RES2_ERR_SHIFT            (21U)
+/*! RES2_ERR - RES2 Indirect Operation Error Flag
+ *  0b0..No invalid indirect operation is detected.
+ *  0b1..An invalid indirect operation error is detected.
+ */
+#define MAU_RES_STATUS_RES2_ERR(x)               (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES2_ERR_SHIFT)) & MAU_RES_STATUS_RES2_ERR_MASK)
+
+#define MAU_RES_STATUS_RES2_OVWR_MASK            (0x400000U)
+#define MAU_RES_STATUS_RES2_OVWR_SHIFT           (22U)
+/*! RES2_OVWR - RES2 Overwrite Flag
+ *  0b0..The value of RES2 has been read.
+ *  0b1..The value of RES2 has not been read yet and is overwritten by a new MAUWRAP result.
+ */
+#define MAU_RES_STATUS_RES2_OVWR(x)              (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES2_OVWR_SHIFT)) & MAU_RES_STATUS_RES2_OVWR_MASK)
+
+#define MAU_RES_STATUS_RES2_FULL_MASK            (0x800000U)
+#define MAU_RES_STATUS_RES2_FULL_SHIFT           (23U)
+/*! RES2_FULL - RES2 Full Flag
+ *  0b0..RES2 has not updated and cannot be read.
+ *  0b1..RES2 has updated and can be read.
+ */
+#define MAU_RES_STATUS_RES2_FULL(x)              (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES2_FULL_SHIFT)) & MAU_RES_STATUS_RES2_FULL_MASK)
+
+#define MAU_RES_STATUS_RES3_NX_MASK              (0x1000000U)
+#define MAU_RES_STATUS_RES3_NX_SHIFT             (24U)
+/*! RES3_NX - RES3 IEEE Inexact Flag
+ *  0b0..The result is not rounded.
+ *  0b1..The result is rounded, and as a result some digits lost.
+ */
+#define MAU_RES_STATUS_RES3_NX(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES3_NX_SHIFT)) & MAU_RES_STATUS_RES3_NX_MASK)
+
+#define MAU_RES_STATUS_RES3_UF_MASK              (0x2000000U)
+#define MAU_RES_STATUS_RES3_UF_SHIFT             (25U)
+/*! RES3_UF - RES3 IEEE Underflow Flag
+ *  0b0..No tiny non-zero result is detected.
+ *  0b1..A tiny non-zero result is detected.
+ */
+#define MAU_RES_STATUS_RES3_UF(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES3_UF_SHIFT)) & MAU_RES_STATUS_RES3_UF_MASK)
+
+#define MAU_RES_STATUS_RES3_OF_MASK              (0x4000000U)
+#define MAU_RES_STATUS_RES3_OF_SHIFT             (26U)
+/*! RES3_OF - RES3 IEEE Overflow Flag
+ *  0b0..The result format's largest finite number is not exceeded.
+ *  0b1..The result format's largest finite number is exceeded.
+ */
+#define MAU_RES_STATUS_RES3_OF(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES3_OF_SHIFT)) & MAU_RES_STATUS_RES3_OF_MASK)
+
+#define MAU_RES_STATUS_RES3_DZ_MASK              (0x8000000U)
+#define MAU_RES_STATUS_RES3_DZ_SHIFT             (27U)
+/*! RES3_DZ - RES3 IEEE Divide by Zero Flag
+ *  0b0..No exact infinite result is defined for an operation on finite operands.
+ *  0b1..An exact infinite result is defined for an operation on finite operands.
+ */
+#define MAU_RES_STATUS_RES3_DZ(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES3_DZ_SHIFT)) & MAU_RES_STATUS_RES3_DZ_MASK)
+
+#define MAU_RES_STATUS_RES3_NV_MASK              (0x10000000U)
+#define MAU_RES_STATUS_RES3_NV_SHIFT             (28U)
+/*! RES3_NV - RES3 IEEE Invalid Flag
+ *  0b0..There is usefully definable result.
+ *  0b1..There is no usefully definable result.
+ */
+#define MAU_RES_STATUS_RES3_NV(x)                (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES3_NV_SHIFT)) & MAU_RES_STATUS_RES3_NV_MASK)
+
+#define MAU_RES_STATUS_RES3_ERR_MASK             (0x20000000U)
+#define MAU_RES_STATUS_RES3_ERR_SHIFT            (29U)
+/*! RES3_ERR - RES3 Indirect Operation Error Flag
+ *  0b0..No invalid indirect operation is detected.
+ *  0b1..An invalid indirect operation error is detected.
+ */
+#define MAU_RES_STATUS_RES3_ERR(x)               (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES3_ERR_SHIFT)) & MAU_RES_STATUS_RES3_ERR_MASK)
+
+#define MAU_RES_STATUS_RES3_OVWR_MASK            (0x40000000U)
+#define MAU_RES_STATUS_RES3_OVWR_SHIFT           (30U)
+/*! RES3_OVWR - RES3 Overwrite Flag
+ *  0b0..The value of RES3 has been read.
+ *  0b1..The value of RES3 has not been read yet and is overwritten by a new MAUWRAP result.
+ */
+#define MAU_RES_STATUS_RES3_OVWR(x)              (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES3_OVWR_SHIFT)) & MAU_RES_STATUS_RES3_OVWR_MASK)
+
+#define MAU_RES_STATUS_RES3_FULL_MASK            (0x80000000U)
+#define MAU_RES_STATUS_RES3_FULL_SHIFT           (31U)
+/*! RES3_FULL - RES3 Full Flag
+ *  0b0..RES3 has not updated and cannot be read.
+ *  0b1..RES3 has updated and can be read.
+ */
+#define MAU_RES_STATUS_RES3_FULL(x)              (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES3_FULL_SHIFT)) & MAU_RES_STATUS_RES3_FULL_MASK)
+/*! @} */
+
+/*! @name RES0 - Result Register 0 */
+/*! @{ */
+
+#define MAU_RES0_MAU_RES0_MASK                   (0xFFFFFFFFU)
+#define MAU_RES0_MAU_RES0_SHIFT                  (0U)
+/*! MAU_RES0 - MAUWRAP Result Register 0 */
+#define MAU_RES0_MAU_RES0(x)                     (((uint32_t)(((uint32_t)(x)) << MAU_RES0_MAU_RES0_SHIFT)) & MAU_RES0_MAU_RES0_MASK)
+/*! @} */
+
+/*! @name RES1 - Result Register 1 */
+/*! @{ */
+
+#define MAU_RES1_MAU_RES1_MASK                   (0xFFFFFFFFU)
+#define MAU_RES1_MAU_RES1_SHIFT                  (0U)
+/*! MAU_RES1 - MAUWRAP Result Register 1 */
+#define MAU_RES1_MAU_RES1(x)                     (((uint32_t)(((uint32_t)(x)) << MAU_RES1_MAU_RES1_SHIFT)) & MAU_RES1_MAU_RES1_MASK)
+/*! @} */
+
+/*! @name RES2 - Result Register 2 */
+/*! @{ */
+
+#define MAU_RES2_MAU_RES2_MASK                   (0xFFFFFFFFU)
+#define MAU_RES2_MAU_RES2_SHIFT                  (0U)
+/*! MAU_RES2 - MAUWRAP Result Register 2 */
+#define MAU_RES2_MAU_RES2(x)                     (((uint32_t)(((uint32_t)(x)) << MAU_RES2_MAU_RES2_SHIFT)) & MAU_RES2_MAU_RES2_MASK)
+/*! @} */
+
+/*! @name RES3 - Result Register 3 */
+/*! @{ */
+
+#define MAU_RES3_MAU_RES3_MASK                   (0xFFFFFFFFU)
+#define MAU_RES3_MAU_RES3_SHIFT                  (0U)
+/*! MAU_RES3 - MAUWRAP Result Register 3 */
+#define MAU_RES3_MAU_RES3(x)                     (((uint32_t)(((uint32_t)(x)) << MAU_RES3_MAU_RES3_SHIFT)) & MAU_RES3_MAU_RES3_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MAU_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group MAU_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_MAU_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_MRCC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_MRCC.h
new file mode 100644
index 0000000000..eb981b941c
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_MRCC.h
@@ -0,0 +1,2600 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MRCC
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_MRCC.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for MRCC
+ *
+ * CMSIS Peripheral Access Layer for MRCC
+ */
+
+#if !defined(PERI_MRCC_H_)
+#define PERI_MRCC_H_                             /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- MRCC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRCC_Peripheral_Access_Layer MRCC Peripheral Access Layer
+ * @{
+ */
+
+/** MRCC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MRCC_GLB_RST0;                     /**< Peripheral Reset Control 0, offset: 0x0 */
+  __O  uint32_t MRCC_GLB_RST0_SET;                 /**< Peripheral Reset Control Set 0, offset: 0x4 */
+  __O  uint32_t MRCC_GLB_RST0_CLR;                 /**< Peripheral Reset Control Clear 0, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t MRCC_GLB_RST1;                     /**< Peripheral Reset Control 1, offset: 0x10 */
+  __O  uint32_t MRCC_GLB_RST1_SET;                 /**< Peripheral Reset Control Set 1, offset: 0x14 */
+  __O  uint32_t MRCC_GLB_RST1_CLR;                 /**< Peripheral Reset Control Clear 1, offset: 0x18 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t MRCC_GLB_RST2;                     /**< Peripheral Reset Control 2, offset: 0x20 */
+  __O  uint32_t MRCC_GLB_RST2_SET;                 /**< Peripheral Reset Control Set 2, offset: 0x24 */
+  __O  uint32_t MRCC_GLB_RST2_CLR;                 /**< Peripheral Reset Control Clear 2, offset: 0x28 */
+       uint8_t RESERVED_2[20];
+  __IO uint32_t MRCC_GLB_CC0;                      /**< AHB Clock Control 0, offset: 0x40 */
+  __O  uint32_t MRCC_GLB_CC0_SET;                  /**< AHB Clock Control Set 0, offset: 0x44 */
+  __O  uint32_t MRCC_GLB_CC0_CLR;                  /**< AHB Clock Control Clear 0, offset: 0x48 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t MRCC_GLB_CC1;                      /**< AHB Clock Control 1, offset: 0x50 */
+  __O  uint32_t MRCC_GLB_CC1_SET;                  /**< AHB Clock Control Set 1, offset: 0x54 */
+  __O  uint32_t MRCC_GLB_CC1_CLR;                  /**< AHB Clock Control Clear 1, offset: 0x58 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t MRCC_GLB_CC2;                      /**< AHB Clock Control 2, offset: 0x60 */
+  __O  uint32_t MRCC_GLB_CC2_SET;                  /**< AHB Clock Control Set 2, offset: 0x64 */
+  __O  uint32_t MRCC_GLB_CC2_CLR;                  /**< AHB Clock Control Clear 2, offset: 0x68 */
+       uint8_t RESERVED_5[20];
+  __IO uint32_t MRCC_GLB_ACC0;                     /**< Control Automatic Clock Gating 0, offset: 0x80 */
+  __IO uint32_t MRCC_GLB_ACC1;                     /**< Control Automatic Clock Gating 1, offset: 0x84 */
+  __IO uint32_t MRCC_GLB_ACC2;                     /**< Control Automatic Clock Gating 2, offset: 0x88 */
+       uint8_t RESERVED_6[20];
+  __IO uint32_t MRCC_CTIMER0_CLKSEL;               /**< CTIMER0 clock selection control, offset: 0xA0 */
+  __IO uint32_t MRCC_CTIMER0_CLKDIV;               /**< CTIMER0 clock divider control, offset: 0xA4 */
+  __IO uint32_t MRCC_CTIMER1_CLKSEL;               /**< CTIMER1 clock selection control, offset: 0xA8 */
+  __IO uint32_t MRCC_CTIMER1_CLKDIV;               /**< CTIMER1 clock divider control, offset: 0xAC */
+  __IO uint32_t MRCC_CTIMER2_CLKSEL;               /**< CTIMER2 clock selection control, offset: 0xB0 */
+  __IO uint32_t MRCC_CTIMER2_CLKDIV;               /**< CTIMER2 clock divider control, offset: 0xB4 */
+       uint8_t RESERVED_7[4];
+  __IO uint32_t MRCC_WWDT0_CLKDIV;                 /**< WWDT0 clock divider control, offset: 0xBC */
+  __IO uint32_t MRCC_LPI2C0_CLKSEL;                /**< LPI2C0 clock selection control, offset: 0xC0 */
+  __IO uint32_t MRCC_LPI2C0_CLKDIV;                /**< LPI2C0 clock divider control, offset: 0xC4 */
+  __IO uint32_t MRCC_LPI2C1_CLKSEL;                /**< LPI2C1 clock selection control, offset: 0xC8 */
+  __IO uint32_t MRCC_LPI2C1_CLKDIV;                /**< LPI2C1 clock divider control, offset: 0xCC */
+  __IO uint32_t MRCC_LPSPI0_CLKSEL;                /**< LPSPI0 clock selection control, offset: 0xD0 */
+  __IO uint32_t MRCC_LPSPI0_CLKDIV;                /**< LPSPI0 clock divider control, offset: 0xD4 */
+  __IO uint32_t MRCC_LPSPI1_CLKSEL;                /**< LPSPI1 clock selection control, offset: 0xD8 */
+  __IO uint32_t MRCC_LPSPI1_CLKDIV;                /**< LPSPI1 clock divider control, offset: 0xDC */
+  __IO uint32_t MRCC_LPUART0_CLKSEL;               /**< LPUART0 clock selection control, offset: 0xE0 */
+  __IO uint32_t MRCC_LPUART0_CLKDIV;               /**< LPUART0 clock divider control, offset: 0xE4 */
+  __IO uint32_t MRCC_LPUART1_CLKSEL;               /**< LPUART1 clock selection control, offset: 0xE8 */
+  __IO uint32_t MRCC_LPUART1_CLKDIV;               /**< LPUART1 clock divider control, offset: 0xEC */
+  __IO uint32_t MRCC_LPUART2_CLKSEL;               /**< LPUART2 clock selection control, offset: 0xF0 */
+  __IO uint32_t MRCC_LPUART2_CLKDIV;               /**< LPUART2 clock divider control, offset: 0xF4 */
+  __IO uint32_t MRCC_LPUART3_CLKSEL;               /**< LPUART3 clock selection control, offset: 0xF8 */
+  __IO uint32_t MRCC_LPUART3_CLKDIV;               /**< LPUART3 clock divider control, offset: 0xFC */
+  __IO uint32_t MRCC_LPTMR0_CLKSEL;                /**< LPTMR0 clock selection control, offset: 0x100 */
+  __IO uint32_t MRCC_LPTMR0_CLKDIV;                /**< LPTMR0 clock divider control, offset: 0x104 */
+  __IO uint32_t MRCC_OSTIMER0_CLKSEL;              /**< OSTIMER0 clock selection control, offset: 0x108 */
+       uint8_t RESERVED_8[4];
+  __IO uint32_t MRCC_ADC_CLKSEL;                   /**< ADCx clock selection control, offset: 0x110 */
+  __IO uint32_t MRCC_ADC_CLKDIV;                   /**< ADCx clock divider control, offset: 0x114 */
+       uint8_t RESERVED_9[4];
+  __IO uint32_t MRCC_CMP0_FUNC_CLKDIV;             /**< CMP0_FUNC clock divider control, offset: 0x11C */
+  __IO uint32_t MRCC_CMP0_RR_CLKSEL;               /**< CMP0_RR clock selection control, offset: 0x120 */
+  __IO uint32_t MRCC_CMP0_RR_CLKDIV;               /**< CMP0_RR clock divider control, offset: 0x124 */
+       uint8_t RESERVED_10[4];
+  __IO uint32_t MRCC_CMP1_FUNC_CLKDIV;             /**< CMP1_FUNC clock divider control, offset: 0x12C */
+  __IO uint32_t MRCC_CMP1_RR_CLKSEL;               /**< CMP1_RR clock selection control, offset: 0x130 */
+  __IO uint32_t MRCC_CMP1_RR_CLKDIV;               /**< CMP1_RR clock divider control, offset: 0x134 */
+       uint8_t RESERVED_11[4];
+  __IO uint32_t MRCC_CMP2_FUNC_CLKDIV;             /**< CMP2_FUNC clock divider control, offset: 0x13C */
+  __IO uint32_t MRCC_CMP2_RR_CLKSEL;               /**< CMP2_RR clock selection control, offset: 0x140 */
+  __IO uint32_t MRCC_CMP2_RR_CLKDIV;               /**< CMP2_RR clock divider control, offset: 0x144 */
+  __IO uint32_t MRCC_FLEXCAN0_CLKSEL;              /**< FLEXCAN0 clock selection control, offset: 0x148 */
+  __IO uint32_t MRCC_FLEXCAN0_CLKDIV;              /**< FLEXCAN0 clock divider control, offset: 0x14C */
+  __IO uint32_t MRCC_DBG_TRACE_CLKSEL;             /**< DBG_TRACE clock selection control, offset: 0x150 */
+  __IO uint32_t MRCC_DBG_TRACE_CLKDIV;             /**< DBG_TRACE clock divider control, offset: 0x154 */
+  __IO uint32_t MRCC_CLKOUT_CLKSEL;                /**< CLKOUT clock selection control, offset: 0x158 */
+  __IO uint32_t MRCC_CLKOUT_CLKDIV;                /**< CLKOUT clock divider control, offset: 0x15C */
+} MRCC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MRCC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRCC_Register_Masks MRCC Register Masks
+ * @{
+ */
+
+/*! @name MRCC_GLB_RST0 - Peripheral Reset Control 0 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_RST0_INPUTMUX0_MASK        (0x1U)
+#define MRCC_MRCC_GLB_RST0_INPUTMUX0_SHIFT       (0U)
+/*! INPUTMUX0 - INPUTMUX0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_INPUTMUX0(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_INPUTMUX0_SHIFT)) & MRCC_MRCC_GLB_RST0_INPUTMUX0_MASK)
+
+#define MRCC_MRCC_GLB_RST0_CTIMER0_MASK          (0x4U)
+#define MRCC_MRCC_GLB_RST0_CTIMER0_SHIFT         (2U)
+/*! CTIMER0 - CTIMER0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_CTIMER0(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER0_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER0_MASK)
+
+#define MRCC_MRCC_GLB_RST0_CTIMER1_MASK          (0x8U)
+#define MRCC_MRCC_GLB_RST0_CTIMER1_SHIFT         (3U)
+/*! CTIMER1 - CTIMER1
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_CTIMER1(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER1_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER1_MASK)
+
+#define MRCC_MRCC_GLB_RST0_CTIMER2_MASK          (0x10U)
+#define MRCC_MRCC_GLB_RST0_CTIMER2_SHIFT         (4U)
+/*! CTIMER2 - CTIMER2
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_CTIMER2(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER2_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER2_MASK)
+
+#define MRCC_MRCC_GLB_RST0_FREQME_MASK           (0x80U)
+#define MRCC_MRCC_GLB_RST0_FREQME_SHIFT          (7U)
+/*! FREQME - FREQME
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_FREQME(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_FREQME_SHIFT)) & MRCC_MRCC_GLB_RST0_FREQME_MASK)
+
+#define MRCC_MRCC_GLB_RST0_UTICK0_MASK           (0x100U)
+#define MRCC_MRCC_GLB_RST0_UTICK0_SHIFT          (8U)
+/*! UTICK0 - UTICK0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_UTICK0(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_UTICK0_SHIFT)) & MRCC_MRCC_GLB_RST0_UTICK0_MASK)
+
+#define MRCC_MRCC_GLB_RST0_SMARTDMA0_MASK        (0x400U)
+#define MRCC_MRCC_GLB_RST0_SMARTDMA0_SHIFT       (10U)
+/*! SMARTDMA0 - SMARTDMA0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_SMARTDMA0(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_SMARTDMA0_SHIFT)) & MRCC_MRCC_GLB_RST0_SMARTDMA0_MASK)
+
+#define MRCC_MRCC_GLB_RST0_DMA0_MASK             (0x800U)
+#define MRCC_MRCC_GLB_RST0_DMA0_SHIFT            (11U)
+/*! DMA0 - DMA0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_DMA0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_DMA0_SHIFT)) & MRCC_MRCC_GLB_RST0_DMA0_MASK)
+
+#define MRCC_MRCC_GLB_RST0_AOI0_MASK             (0x1000U)
+#define MRCC_MRCC_GLB_RST0_AOI0_SHIFT            (12U)
+/*! AOI0 - AOI0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_AOI0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_AOI0_SHIFT)) & MRCC_MRCC_GLB_RST0_AOI0_MASK)
+
+#define MRCC_MRCC_GLB_RST0_CRC0_MASK             (0x2000U)
+#define MRCC_MRCC_GLB_RST0_CRC0_SHIFT            (13U)
+/*! CRC0 - CRC0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_CRC0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CRC0_SHIFT)) & MRCC_MRCC_GLB_RST0_CRC0_MASK)
+
+#define MRCC_MRCC_GLB_RST0_EIM0_MASK             (0x4000U)
+#define MRCC_MRCC_GLB_RST0_EIM0_SHIFT            (14U)
+/*! EIM0 - EIM0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_EIM0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_EIM0_SHIFT)) & MRCC_MRCC_GLB_RST0_EIM0_MASK)
+
+#define MRCC_MRCC_GLB_RST0_ERM0_MASK             (0x8000U)
+#define MRCC_MRCC_GLB_RST0_ERM0_SHIFT            (15U)
+/*! ERM0 - ERM0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_ERM0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_ERM0_SHIFT)) & MRCC_MRCC_GLB_RST0_ERM0_MASK)
+
+#define MRCC_MRCC_GLB_RST0_AOI1_MASK             (0x20000U)
+#define MRCC_MRCC_GLB_RST0_AOI1_SHIFT            (17U)
+/*! AOI1 - AOI1
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_AOI1(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_AOI1_SHIFT)) & MRCC_MRCC_GLB_RST0_AOI1_MASK)
+
+#define MRCC_MRCC_GLB_RST0_LPI2C0_MASK           (0x80000U)
+#define MRCC_MRCC_GLB_RST0_LPI2C0_SHIFT          (19U)
+/*! LPI2C0 - LPI2C0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_LPI2C0(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPI2C0_SHIFT)) & MRCC_MRCC_GLB_RST0_LPI2C0_MASK)
+
+#define MRCC_MRCC_GLB_RST0_LPI2C1_MASK           (0x100000U)
+#define MRCC_MRCC_GLB_RST0_LPI2C1_SHIFT          (20U)
+/*! LPI2C1 - LPI2C1
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_LPI2C1(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPI2C1_SHIFT)) & MRCC_MRCC_GLB_RST0_LPI2C1_MASK)
+
+#define MRCC_MRCC_GLB_RST0_LPSPI0_MASK           (0x200000U)
+#define MRCC_MRCC_GLB_RST0_LPSPI0_SHIFT          (21U)
+/*! LPSPI0 - LPSPI0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_LPSPI0(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPSPI0_SHIFT)) & MRCC_MRCC_GLB_RST0_LPSPI0_MASK)
+
+#define MRCC_MRCC_GLB_RST0_LPSPI1_MASK           (0x400000U)
+#define MRCC_MRCC_GLB_RST0_LPSPI1_SHIFT          (22U)
+/*! LPSPI1 - LPSPI1
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_LPSPI1(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPSPI1_SHIFT)) & MRCC_MRCC_GLB_RST0_LPSPI1_MASK)
+
+#define MRCC_MRCC_GLB_RST0_LPUART0_MASK          (0x800000U)
+#define MRCC_MRCC_GLB_RST0_LPUART0_SHIFT         (23U)
+/*! LPUART0 - LPUART0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_LPUART0(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART0_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART0_MASK)
+
+#define MRCC_MRCC_GLB_RST0_LPUART1_MASK          (0x1000000U)
+#define MRCC_MRCC_GLB_RST0_LPUART1_SHIFT         (24U)
+/*! LPUART1 - LPUART1
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_LPUART1(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART1_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART1_MASK)
+
+#define MRCC_MRCC_GLB_RST0_LPUART2_MASK          (0x2000000U)
+#define MRCC_MRCC_GLB_RST0_LPUART2_SHIFT         (25U)
+/*! LPUART2 - LPUART2
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_LPUART2(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART2_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART2_MASK)
+
+#define MRCC_MRCC_GLB_RST0_LPUART3_MASK          (0x4000000U)
+#define MRCC_MRCC_GLB_RST0_LPUART3_SHIFT         (26U)
+/*! LPUART3 - LPUART3
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_LPUART3(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART3_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART3_MASK)
+
+#define MRCC_MRCC_GLB_RST0_QDC0_MASK             (0x20000000U)
+#define MRCC_MRCC_GLB_RST0_QDC0_SHIFT            (29U)
+/*! QDC0 - QDC0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_QDC0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_QDC0_SHIFT)) & MRCC_MRCC_GLB_RST0_QDC0_MASK)
+
+#define MRCC_MRCC_GLB_RST0_QDC1_MASK             (0x40000000U)
+#define MRCC_MRCC_GLB_RST0_QDC1_SHIFT            (30U)
+/*! QDC1 - QDC1
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_QDC1(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_QDC1_SHIFT)) & MRCC_MRCC_GLB_RST0_QDC1_MASK)
+
+#define MRCC_MRCC_GLB_RST0_FLEXPWM0_MASK         (0x80000000U)
+#define MRCC_MRCC_GLB_RST0_FLEXPWM0_SHIFT        (31U)
+/*! FLEXPWM0 - FLEXPWM0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST0_FLEXPWM0(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_FLEXPWM0_SHIFT)) & MRCC_MRCC_GLB_RST0_FLEXPWM0_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_RST0_SET - Peripheral Reset Control Set 0 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_RST0_SET_DATA_MASK         (0xFFFFFFFFU)
+#define MRCC_MRCC_GLB_RST0_SET_DATA_SHIFT        (0U)
+/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */
+#define MRCC_MRCC_GLB_RST0_SET_DATA(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_RST0_SET_DATA_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_RST0_CLR - Peripheral Reset Control Clear 0 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_RST0_CLR_DATA_MASK         (0xFFFFFFFFU)
+#define MRCC_MRCC_GLB_RST0_CLR_DATA_SHIFT        (0U)
+/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */
+#define MRCC_MRCC_GLB_RST0_CLR_DATA(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_RST0_CLR_DATA_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_RST1 - Peripheral Reset Control 1 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_RST1_FLEXPWM1_MASK         (0x1U)
+#define MRCC_MRCC_GLB_RST1_FLEXPWM1_SHIFT        (0U)
+/*! FLEXPWM1 - FLEXPWM1
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST1_FLEXPWM1(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_FLEXPWM1_SHIFT)) & MRCC_MRCC_GLB_RST1_FLEXPWM1_MASK)
+
+#define MRCC_MRCC_GLB_RST1_OSTIMER0_MASK         (0x2U)
+#define MRCC_MRCC_GLB_RST1_OSTIMER0_SHIFT        (1U)
+/*! OSTIMER0 - OSTIMER0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST1_OSTIMER0(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_OSTIMER0_SHIFT)) & MRCC_MRCC_GLB_RST1_OSTIMER0_MASK)
+
+#define MRCC_MRCC_GLB_RST1_ADC0_MASK             (0x4U)
+#define MRCC_MRCC_GLB_RST1_ADC0_SHIFT            (2U)
+/*! ADC0 - ADC0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST1_ADC0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_ADC0_SHIFT)) & MRCC_MRCC_GLB_RST1_ADC0_MASK)
+
+#define MRCC_MRCC_GLB_RST1_ADC1_MASK             (0x8U)
+#define MRCC_MRCC_GLB_RST1_ADC1_SHIFT            (3U)
+/*! ADC1 - ADC1
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST1_ADC1(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_ADC1_SHIFT)) & MRCC_MRCC_GLB_RST1_ADC1_MASK)
+
+#define MRCC_MRCC_GLB_RST1_CMP1_MASK             (0x20U)
+#define MRCC_MRCC_GLB_RST1_CMP1_SHIFT            (5U)
+/*! CMP1 - CMP1
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST1_CMP1(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_CMP1_SHIFT)) & MRCC_MRCC_GLB_RST1_CMP1_MASK)
+
+#define MRCC_MRCC_GLB_RST1_CMP2_MASK             (0x40U)
+#define MRCC_MRCC_GLB_RST1_CMP2_SHIFT            (6U)
+/*! CMP2 - CMP2
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST1_CMP2(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_CMP2_SHIFT)) & MRCC_MRCC_GLB_RST1_CMP2_MASK)
+
+#define MRCC_MRCC_GLB_RST1_OPAMP0_MASK           (0x100U)
+#define MRCC_MRCC_GLB_RST1_OPAMP0_SHIFT          (8U)
+/*! OPAMP0 - OPAMP0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST1_OPAMP0(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_OPAMP0_SHIFT)) & MRCC_MRCC_GLB_RST1_OPAMP0_MASK)
+
+#define MRCC_MRCC_GLB_RST1_OPAMP1_MASK           (0x200U)
+#define MRCC_MRCC_GLB_RST1_OPAMP1_SHIFT          (9U)
+/*! OPAMP1 - OPAMP1
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST1_OPAMP1(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_OPAMP1_SHIFT)) & MRCC_MRCC_GLB_RST1_OPAMP1_MASK)
+
+#define MRCC_MRCC_GLB_RST1_OPAMP2_MASK           (0x400U)
+#define MRCC_MRCC_GLB_RST1_OPAMP2_SHIFT          (10U)
+/*! OPAMP2 - OPAMP2
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST1_OPAMP2(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_OPAMP2_SHIFT)) & MRCC_MRCC_GLB_RST1_OPAMP2_MASK)
+
+#define MRCC_MRCC_GLB_RST1_PORT0_MASK            (0x1000U)
+#define MRCC_MRCC_GLB_RST1_PORT0_SHIFT           (12U)
+/*! PORT0 - PORT0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST1_PORT0(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT0_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT0_MASK)
+
+#define MRCC_MRCC_GLB_RST1_PORT1_MASK            (0x2000U)
+#define MRCC_MRCC_GLB_RST1_PORT1_SHIFT           (13U)
+/*! PORT1 - PORT1
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST1_PORT1(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT1_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT1_MASK)
+
+#define MRCC_MRCC_GLB_RST1_PORT2_MASK            (0x4000U)
+#define MRCC_MRCC_GLB_RST1_PORT2_SHIFT           (14U)
+/*! PORT2 - PORT2
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST1_PORT2(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT2_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT2_MASK)
+
+#define MRCC_MRCC_GLB_RST1_PORT3_MASK            (0x8000U)
+#define MRCC_MRCC_GLB_RST1_PORT3_SHIFT           (15U)
+/*! PORT3 - PORT3
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST1_PORT3(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT3_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT3_MASK)
+
+#define MRCC_MRCC_GLB_RST1_PORT4_MASK            (0x10000U)
+#define MRCC_MRCC_GLB_RST1_PORT4_SHIFT           (16U)
+/*! PORT4 - PORT4
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST1_PORT4(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT4_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT4_MASK)
+
+#define MRCC_MRCC_GLB_RST1_FLEXCAN0_MASK         (0x40000U)
+#define MRCC_MRCC_GLB_RST1_FLEXCAN0_SHIFT        (18U)
+/*! FLEXCAN0 - FLEXCAN0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST1_FLEXCAN0(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_FLEXCAN0_SHIFT)) & MRCC_MRCC_GLB_RST1_FLEXCAN0_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_RST1_SET - Peripheral Reset Control Set 1 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_RST1_SET_DATA_MASK         (0xFFFFFFFFU)
+#define MRCC_MRCC_GLB_RST1_SET_DATA_SHIFT        (0U)
+/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */
+#define MRCC_MRCC_GLB_RST1_SET_DATA(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_RST1_SET_DATA_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_RST1_CLR - Peripheral Reset Control Clear 1 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_RST1_CLR_DATA_MASK         (0xFFFFFFFFU)
+#define MRCC_MRCC_GLB_RST1_CLR_DATA_SHIFT        (0U)
+/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */
+#define MRCC_MRCC_GLB_RST1_CLR_DATA(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_RST1_CLR_DATA_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_RST2 - Peripheral Reset Control 2 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_RST2_GPIO0_MASK            (0x10U)
+#define MRCC_MRCC_GLB_RST2_GPIO0_SHIFT           (4U)
+/*! GPIO0 - GPIO0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST2_GPIO0(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_GPIO0_SHIFT)) & MRCC_MRCC_GLB_RST2_GPIO0_MASK)
+
+#define MRCC_MRCC_GLB_RST2_GPIO1_MASK            (0x20U)
+#define MRCC_MRCC_GLB_RST2_GPIO1_SHIFT           (5U)
+/*! GPIO1 - GPIO1
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST2_GPIO1(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_GPIO1_SHIFT)) & MRCC_MRCC_GLB_RST2_GPIO1_MASK)
+
+#define MRCC_MRCC_GLB_RST2_GPIO2_MASK            (0x40U)
+#define MRCC_MRCC_GLB_RST2_GPIO2_SHIFT           (6U)
+/*! GPIO2 - GPIO2
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST2_GPIO2(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_GPIO2_SHIFT)) & MRCC_MRCC_GLB_RST2_GPIO2_MASK)
+
+#define MRCC_MRCC_GLB_RST2_GPIO3_MASK            (0x80U)
+#define MRCC_MRCC_GLB_RST2_GPIO3_SHIFT           (7U)
+/*! GPIO3 - GPIO3
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST2_GPIO3(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_GPIO3_SHIFT)) & MRCC_MRCC_GLB_RST2_GPIO3_MASK)
+
+#define MRCC_MRCC_GLB_RST2_GPIO4_MASK            (0x100U)
+#define MRCC_MRCC_GLB_RST2_GPIO4_SHIFT           (8U)
+/*! GPIO4 - GPIO4
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST2_GPIO4(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_GPIO4_SHIFT)) & MRCC_MRCC_GLB_RST2_GPIO4_MASK)
+
+#define MRCC_MRCC_GLB_RST2_MAU0_MASK             (0x200U)
+#define MRCC_MRCC_GLB_RST2_MAU0_SHIFT            (9U)
+/*! MAU0 - MAU0
+ *  0b0..Peripheral is held in reset
+ *  0b1..Peripheral is released from reset
+ */
+#define MRCC_MRCC_GLB_RST2_MAU0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_MAU0_SHIFT)) & MRCC_MRCC_GLB_RST2_MAU0_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_RST2_SET - Peripheral Reset Control Set 2 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_RST2_SET_DATA_MASK         (0xFFFFFFFFU)
+#define MRCC_MRCC_GLB_RST2_SET_DATA_SHIFT        (0U)
+/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */
+#define MRCC_MRCC_GLB_RST2_SET_DATA(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_RST2_SET_DATA_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_RST2_CLR - Peripheral Reset Control Clear 2 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_RST2_CLR_DATA_MASK         (0xFFFFFFFFU)
+#define MRCC_MRCC_GLB_RST2_CLR_DATA_SHIFT        (0U)
+/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */
+#define MRCC_MRCC_GLB_RST2_CLR_DATA(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_RST2_CLR_DATA_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_CC0 - AHB Clock Control 0 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_CC0_INPUTMUX0_MASK         (0x1U)
+#define MRCC_MRCC_GLB_CC0_INPUTMUX0_SHIFT        (0U)
+/*! INPUTMUX0 - INPUTMUX0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_INPUTMUX0(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_INPUTMUX0_SHIFT)) & MRCC_MRCC_GLB_CC0_INPUTMUX0_MASK)
+
+#define MRCC_MRCC_GLB_CC0_CTIMER0_MASK           (0x4U)
+#define MRCC_MRCC_GLB_CC0_CTIMER0_SHIFT          (2U)
+/*! CTIMER0 - CTIMER0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_CTIMER0(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER0_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER0_MASK)
+
+#define MRCC_MRCC_GLB_CC0_CTIMER1_MASK           (0x8U)
+#define MRCC_MRCC_GLB_CC0_CTIMER1_SHIFT          (3U)
+/*! CTIMER1 - CTIMER1
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_CTIMER1(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER1_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER1_MASK)
+
+#define MRCC_MRCC_GLB_CC0_CTIMER2_MASK           (0x10U)
+#define MRCC_MRCC_GLB_CC0_CTIMER2_SHIFT          (4U)
+/*! CTIMER2 - CTIMER2
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_CTIMER2(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER2_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER2_MASK)
+
+#define MRCC_MRCC_GLB_CC0_FREQME_MASK            (0x80U)
+#define MRCC_MRCC_GLB_CC0_FREQME_SHIFT           (7U)
+/*! FREQME - FREQME
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_FREQME(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_FREQME_SHIFT)) & MRCC_MRCC_GLB_CC0_FREQME_MASK)
+
+#define MRCC_MRCC_GLB_CC0_UTICK0_MASK            (0x100U)
+#define MRCC_MRCC_GLB_CC0_UTICK0_SHIFT           (8U)
+/*! UTICK0 - UTICK0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_UTICK0(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_UTICK0_SHIFT)) & MRCC_MRCC_GLB_CC0_UTICK0_MASK)
+
+#define MRCC_MRCC_GLB_CC0_WWDT0_MASK             (0x200U)
+#define MRCC_MRCC_GLB_CC0_WWDT0_SHIFT            (9U)
+/*! WWDT0 - WWDT0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_WWDT0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_WWDT0_SHIFT)) & MRCC_MRCC_GLB_CC0_WWDT0_MASK)
+
+#define MRCC_MRCC_GLB_CC0_SMARTDMA0_MASK         (0x400U)
+#define MRCC_MRCC_GLB_CC0_SMARTDMA0_SHIFT        (10U)
+/*! SMARTDMA0 - SMARTDMA0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_SMARTDMA0(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_SMARTDMA0_SHIFT)) & MRCC_MRCC_GLB_CC0_SMARTDMA0_MASK)
+
+#define MRCC_MRCC_GLB_CC0_DMA0_MASK              (0x800U)
+#define MRCC_MRCC_GLB_CC0_DMA0_SHIFT             (11U)
+/*! DMA0 - DMA0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_DMA0(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_DMA0_SHIFT)) & MRCC_MRCC_GLB_CC0_DMA0_MASK)
+
+#define MRCC_MRCC_GLB_CC0_AOI0_MASK              (0x1000U)
+#define MRCC_MRCC_GLB_CC0_AOI0_SHIFT             (12U)
+/*! AOI0 - AOI0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_AOI0(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_AOI0_SHIFT)) & MRCC_MRCC_GLB_CC0_AOI0_MASK)
+
+#define MRCC_MRCC_GLB_CC0_CRC0_MASK              (0x2000U)
+#define MRCC_MRCC_GLB_CC0_CRC0_SHIFT             (13U)
+/*! CRC0 - CRC0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_CRC0(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CRC0_SHIFT)) & MRCC_MRCC_GLB_CC0_CRC0_MASK)
+
+#define MRCC_MRCC_GLB_CC0_EIM0_MASK              (0x4000U)
+#define MRCC_MRCC_GLB_CC0_EIM0_SHIFT             (14U)
+/*! EIM0 - EIM0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_EIM0(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_EIM0_SHIFT)) & MRCC_MRCC_GLB_CC0_EIM0_MASK)
+
+#define MRCC_MRCC_GLB_CC0_ERM0_MASK              (0x8000U)
+#define MRCC_MRCC_GLB_CC0_ERM0_SHIFT             (15U)
+/*! ERM0 - ERM0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_ERM0(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_ERM0_SHIFT)) & MRCC_MRCC_GLB_CC0_ERM0_MASK)
+
+#define MRCC_MRCC_GLB_CC0_AOI1_MASK              (0x20000U)
+#define MRCC_MRCC_GLB_CC0_AOI1_SHIFT             (17U)
+/*! AOI1 - AOI1
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_AOI1(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_AOI1_SHIFT)) & MRCC_MRCC_GLB_CC0_AOI1_MASK)
+
+#define MRCC_MRCC_GLB_CC0_LPI2C0_MASK            (0x80000U)
+#define MRCC_MRCC_GLB_CC0_LPI2C0_SHIFT           (19U)
+/*! LPI2C0 - LPI2C0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_LPI2C0(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPI2C0_SHIFT)) & MRCC_MRCC_GLB_CC0_LPI2C0_MASK)
+
+#define MRCC_MRCC_GLB_CC0_LPI2C1_MASK            (0x100000U)
+#define MRCC_MRCC_GLB_CC0_LPI2C1_SHIFT           (20U)
+/*! LPI2C1 - LPI2C1
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_LPI2C1(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPI2C1_SHIFT)) & MRCC_MRCC_GLB_CC0_LPI2C1_MASK)
+
+#define MRCC_MRCC_GLB_CC0_LPSPI0_MASK            (0x200000U)
+#define MRCC_MRCC_GLB_CC0_LPSPI0_SHIFT           (21U)
+/*! LPSPI0 - LPSPI0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_LPSPI0(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPSPI0_SHIFT)) & MRCC_MRCC_GLB_CC0_LPSPI0_MASK)
+
+#define MRCC_MRCC_GLB_CC0_LPSPI1_MASK            (0x400000U)
+#define MRCC_MRCC_GLB_CC0_LPSPI1_SHIFT           (22U)
+/*! LPSPI1 - LPSPI1
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_LPSPI1(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPSPI1_SHIFT)) & MRCC_MRCC_GLB_CC0_LPSPI1_MASK)
+
+#define MRCC_MRCC_GLB_CC0_LPUART0_MASK           (0x800000U)
+#define MRCC_MRCC_GLB_CC0_LPUART0_SHIFT          (23U)
+/*! LPUART0 - LPUART0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_LPUART0(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART0_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART0_MASK)
+
+#define MRCC_MRCC_GLB_CC0_LPUART1_MASK           (0x1000000U)
+#define MRCC_MRCC_GLB_CC0_LPUART1_SHIFT          (24U)
+/*! LPUART1 - LPUART1
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_LPUART1(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART1_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART1_MASK)
+
+#define MRCC_MRCC_GLB_CC0_LPUART2_MASK           (0x2000000U)
+#define MRCC_MRCC_GLB_CC0_LPUART2_SHIFT          (25U)
+/*! LPUART2 - LPUART2
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_LPUART2(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART2_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART2_MASK)
+
+#define MRCC_MRCC_GLB_CC0_LPUART3_MASK           (0x4000000U)
+#define MRCC_MRCC_GLB_CC0_LPUART3_SHIFT          (26U)
+/*! LPUART3 - LPUART3
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_LPUART3(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART3_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART3_MASK)
+
+#define MRCC_MRCC_GLB_CC0_QDC0_MASK              (0x20000000U)
+#define MRCC_MRCC_GLB_CC0_QDC0_SHIFT             (29U)
+/*! QDC0 - QDC0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_QDC0(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_QDC0_SHIFT)) & MRCC_MRCC_GLB_CC0_QDC0_MASK)
+
+#define MRCC_MRCC_GLB_CC0_QDC1_MASK              (0x40000000U)
+#define MRCC_MRCC_GLB_CC0_QDC1_SHIFT             (30U)
+/*! QDC1 - QDC1
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_QDC1(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_QDC1_SHIFT)) & MRCC_MRCC_GLB_CC0_QDC1_MASK)
+
+#define MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK          (0x80000000U)
+#define MRCC_MRCC_GLB_CC0_FLEXPWM0_SHIFT         (31U)
+/*! FLEXPWM0 - FLEXPWM0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC0_FLEXPWM0(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_FLEXPWM0_SHIFT)) & MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_CC0_SET - AHB Clock Control Set 0 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_CC0_SET_DATA_MASK          (0xFFFFFFFFU)
+#define MRCC_MRCC_GLB_CC0_SET_DATA_SHIFT         (0U)
+/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */
+#define MRCC_MRCC_GLB_CC0_SET_DATA(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_CC0_SET_DATA_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_CC0_CLR - AHB Clock Control Clear 0 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_CC0_CLR_DATA_MASK          (0xFFFFFFFFU)
+#define MRCC_MRCC_GLB_CC0_CLR_DATA_SHIFT         (0U)
+/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */
+#define MRCC_MRCC_GLB_CC0_CLR_DATA(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_CC0_CLR_DATA_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_CC1 - AHB Clock Control 1 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_CC1_FLEXPWM1_MASK          (0x1U)
+#define MRCC_MRCC_GLB_CC1_FLEXPWM1_SHIFT         (0U)
+/*! FLEXPWM1 - FLEXPWM1
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC1_FLEXPWM1(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_FLEXPWM1_SHIFT)) & MRCC_MRCC_GLB_CC1_FLEXPWM1_MASK)
+
+#define MRCC_MRCC_GLB_CC1_OSTIMER0_MASK          (0x2U)
+#define MRCC_MRCC_GLB_CC1_OSTIMER0_SHIFT         (1U)
+/*! OSTIMER0 - OSTIMER0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC1_OSTIMER0(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_OSTIMER0_SHIFT)) & MRCC_MRCC_GLB_CC1_OSTIMER0_MASK)
+
+#define MRCC_MRCC_GLB_CC1_ADC0_MASK              (0x4U)
+#define MRCC_MRCC_GLB_CC1_ADC0_SHIFT             (2U)
+/*! ADC0 - ADC0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC1_ADC0(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_ADC0_SHIFT)) & MRCC_MRCC_GLB_CC1_ADC0_MASK)
+
+#define MRCC_MRCC_GLB_CC1_ADC1_MASK              (0x8U)
+#define MRCC_MRCC_GLB_CC1_ADC1_SHIFT             (3U)
+/*! ADC1 - ADC1
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC1_ADC1(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_ADC1_SHIFT)) & MRCC_MRCC_GLB_CC1_ADC1_MASK)
+
+#define MRCC_MRCC_GLB_CC1_CMP0_MASK              (0x10U)
+#define MRCC_MRCC_GLB_CC1_CMP0_SHIFT             (4U)
+/*! CMP0 - CMP0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC1_CMP0(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_CMP0_SHIFT)) & MRCC_MRCC_GLB_CC1_CMP0_MASK)
+
+#define MRCC_MRCC_GLB_CC1_CMP1_MASK              (0x20U)
+#define MRCC_MRCC_GLB_CC1_CMP1_SHIFT             (5U)
+/*! CMP1 - CMP1
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC1_CMP1(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_CMP1_SHIFT)) & MRCC_MRCC_GLB_CC1_CMP1_MASK)
+
+#define MRCC_MRCC_GLB_CC1_CMP2_MASK              (0x40U)
+#define MRCC_MRCC_GLB_CC1_CMP2_SHIFT             (6U)
+/*! CMP2 - CMP2
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC1_CMP2(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_CMP2_SHIFT)) & MRCC_MRCC_GLB_CC1_CMP2_MASK)
+
+#define MRCC_MRCC_GLB_CC1_OPAMP0_MASK            (0x100U)
+#define MRCC_MRCC_GLB_CC1_OPAMP0_SHIFT           (8U)
+/*! OPAMP0 - OPAMP0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC1_OPAMP0(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_OPAMP0_SHIFT)) & MRCC_MRCC_GLB_CC1_OPAMP0_MASK)
+
+#define MRCC_MRCC_GLB_CC1_OPAMP1_MASK            (0x200U)
+#define MRCC_MRCC_GLB_CC1_OPAMP1_SHIFT           (9U)
+/*! OPAMP1 - OPAMP1
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC1_OPAMP1(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_OPAMP1_SHIFT)) & MRCC_MRCC_GLB_CC1_OPAMP1_MASK)
+
+#define MRCC_MRCC_GLB_CC1_OPAMP2_MASK            (0x400U)
+#define MRCC_MRCC_GLB_CC1_OPAMP2_SHIFT           (10U)
+/*! OPAMP2 - OPAMP2
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC1_OPAMP2(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_OPAMP2_SHIFT)) & MRCC_MRCC_GLB_CC1_OPAMP2_MASK)
+
+#define MRCC_MRCC_GLB_CC1_PORT0_MASK             (0x1000U)
+#define MRCC_MRCC_GLB_CC1_PORT0_SHIFT            (12U)
+/*! PORT0 - PORT0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC1_PORT0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT0_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT0_MASK)
+
+#define MRCC_MRCC_GLB_CC1_PORT1_MASK             (0x2000U)
+#define MRCC_MRCC_GLB_CC1_PORT1_SHIFT            (13U)
+/*! PORT1 - PORT1
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC1_PORT1(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT1_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT1_MASK)
+
+#define MRCC_MRCC_GLB_CC1_PORT2_MASK             (0x4000U)
+#define MRCC_MRCC_GLB_CC1_PORT2_SHIFT            (14U)
+/*! PORT2 - PORT2
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC1_PORT2(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT2_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT2_MASK)
+
+#define MRCC_MRCC_GLB_CC1_PORT3_MASK             (0x8000U)
+#define MRCC_MRCC_GLB_CC1_PORT3_SHIFT            (15U)
+/*! PORT3 - PORT3
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC1_PORT3(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT3_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT3_MASK)
+
+#define MRCC_MRCC_GLB_CC1_PORT4_MASK             (0x10000U)
+#define MRCC_MRCC_GLB_CC1_PORT4_SHIFT            (16U)
+/*! PORT4 - PORT4
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC1_PORT4(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT4_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT4_MASK)
+
+#define MRCC_MRCC_GLB_CC1_FLEXCAN0_MASK          (0x40000U)
+#define MRCC_MRCC_GLB_CC1_FLEXCAN0_SHIFT         (18U)
+/*! FLEXCAN0 - FLEXCAN0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC1_FLEXCAN0(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_FLEXCAN0_SHIFT)) & MRCC_MRCC_GLB_CC1_FLEXCAN0_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_CC1_SET - AHB Clock Control Set 1 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_CC1_SET_DATA_MASK          (0xFFFFFFFFU)
+#define MRCC_MRCC_GLB_CC1_SET_DATA_SHIFT         (0U)
+/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */
+#define MRCC_MRCC_GLB_CC1_SET_DATA(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_CC1_SET_DATA_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_CC1_CLR - AHB Clock Control Clear 1 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_CC1_CLR_DATA_MASK          (0xFFFFFFFFU)
+#define MRCC_MRCC_GLB_CC1_CLR_DATA_SHIFT         (0U)
+/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */
+#define MRCC_MRCC_GLB_CC1_CLR_DATA(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_CC1_CLR_DATA_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_CC2 - AHB Clock Control 2 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_CC2_RAMA_MASK              (0x2U)
+#define MRCC_MRCC_GLB_CC2_RAMA_SHIFT             (1U)
+/*! RAMA - RAMA
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC2_RAMA(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_RAMA_SHIFT)) & MRCC_MRCC_GLB_CC2_RAMA_MASK)
+
+#define MRCC_MRCC_GLB_CC2_RAMB_MASK              (0x4U)
+#define MRCC_MRCC_GLB_CC2_RAMB_SHIFT             (2U)
+/*! RAMB - RAMB
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC2_RAMB(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_RAMB_SHIFT)) & MRCC_MRCC_GLB_CC2_RAMB_MASK)
+
+#define MRCC_MRCC_GLB_CC2_RAMC_MASK              (0x8U)
+#define MRCC_MRCC_GLB_CC2_RAMC_SHIFT             (3U)
+/*! RAMC - RAMC
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC2_RAMC(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_RAMC_SHIFT)) & MRCC_MRCC_GLB_CC2_RAMC_MASK)
+
+#define MRCC_MRCC_GLB_CC2_GPIO0_MASK             (0x10U)
+#define MRCC_MRCC_GLB_CC2_GPIO0_SHIFT            (4U)
+/*! GPIO0 - GPIO0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC2_GPIO0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_GPIO0_SHIFT)) & MRCC_MRCC_GLB_CC2_GPIO0_MASK)
+
+#define MRCC_MRCC_GLB_CC2_GPIO1_MASK             (0x20U)
+#define MRCC_MRCC_GLB_CC2_GPIO1_SHIFT            (5U)
+/*! GPIO1 - GPIO1
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC2_GPIO1(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_GPIO1_SHIFT)) & MRCC_MRCC_GLB_CC2_GPIO1_MASK)
+
+#define MRCC_MRCC_GLB_CC2_GPIO2_MASK             (0x40U)
+#define MRCC_MRCC_GLB_CC2_GPIO2_SHIFT            (6U)
+/*! GPIO2 - GPIO2
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC2_GPIO2(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_GPIO2_SHIFT)) & MRCC_MRCC_GLB_CC2_GPIO2_MASK)
+
+#define MRCC_MRCC_GLB_CC2_GPIO3_MASK             (0x80U)
+#define MRCC_MRCC_GLB_CC2_GPIO3_SHIFT            (7U)
+/*! GPIO3 - GPIO3
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC2_GPIO3(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_GPIO3_SHIFT)) & MRCC_MRCC_GLB_CC2_GPIO3_MASK)
+
+#define MRCC_MRCC_GLB_CC2_GPIO4_MASK             (0x100U)
+#define MRCC_MRCC_GLB_CC2_GPIO4_SHIFT            (8U)
+/*! GPIO4 - GPIO4
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC2_GPIO4(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_GPIO4_SHIFT)) & MRCC_MRCC_GLB_CC2_GPIO4_MASK)
+
+#define MRCC_MRCC_GLB_CC2_MAU0_MASK              (0x200U)
+#define MRCC_MRCC_GLB_CC2_MAU0_SHIFT             (9U)
+/*! MAU0 - MAU0
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC2_MAU0(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_MAU0_SHIFT)) & MRCC_MRCC_GLB_CC2_MAU0_MASK)
+
+#define MRCC_MRCC_GLB_CC2_ROMC_MASK              (0x400U)
+#define MRCC_MRCC_GLB_CC2_ROMC_SHIFT             (10U)
+/*! ROMC - ROMC
+ *  0b0..Peripheral clock is disabled
+ *  0b1..Peripheral clock is enabled
+ */
+#define MRCC_MRCC_GLB_CC2_ROMC(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_ROMC_SHIFT)) & MRCC_MRCC_GLB_CC2_ROMC_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_CC2_SET - AHB Clock Control Set 2 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_CC2_SET_DATA_MASK          (0xFFFFFFFFU)
+#define MRCC_MRCC_GLB_CC2_SET_DATA_SHIFT         (0U)
+/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */
+#define MRCC_MRCC_GLB_CC2_SET_DATA(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_CC2_SET_DATA_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_CC2_CLR - AHB Clock Control Clear 2 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_CC2_CLR_DATA_MASK          (0xFFFFFFFFU)
+#define MRCC_MRCC_GLB_CC2_CLR_DATA_SHIFT         (0U)
+/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */
+#define MRCC_MRCC_GLB_CC2_CLR_DATA(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_CC2_CLR_DATA_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_ACC0 - Control Automatic Clock Gating 0 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_ACC0_INPUTMUX0_MASK        (0x1U)
+#define MRCC_MRCC_GLB_ACC0_INPUTMUX0_SHIFT       (0U)
+/*! INPUTMUX0 - INPUTMUX0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_INPUTMUX0(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_INPUTMUX0_SHIFT)) & MRCC_MRCC_GLB_ACC0_INPUTMUX0_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_CTIMER0_MASK          (0x4U)
+#define MRCC_MRCC_GLB_ACC0_CTIMER0_SHIFT         (2U)
+/*! CTIMER0 - CTIMER0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_CTIMER0(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER0_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER0_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_CTIMER1_MASK          (0x8U)
+#define MRCC_MRCC_GLB_ACC0_CTIMER1_SHIFT         (3U)
+/*! CTIMER1 - CTIMER1
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_CTIMER1(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER1_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER1_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_CTIMER2_MASK          (0x10U)
+#define MRCC_MRCC_GLB_ACC0_CTIMER2_SHIFT         (4U)
+/*! CTIMER2 - CTIMER2
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_CTIMER2(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER2_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER2_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_FREQME_MASK           (0x80U)
+#define MRCC_MRCC_GLB_ACC0_FREQME_SHIFT          (7U)
+/*! FREQME - FREQME
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_FREQME(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_FREQME_SHIFT)) & MRCC_MRCC_GLB_ACC0_FREQME_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_UTICK0_MASK           (0x100U)
+#define MRCC_MRCC_GLB_ACC0_UTICK0_SHIFT          (8U)
+/*! UTICK0 - UTICK0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_UTICK0(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_UTICK0_SHIFT)) & MRCC_MRCC_GLB_ACC0_UTICK0_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_WWDT0_MASK            (0x200U)
+#define MRCC_MRCC_GLB_ACC0_WWDT0_SHIFT           (9U)
+/*! WWDT0 - WWDT0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_WWDT0(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_WWDT0_SHIFT)) & MRCC_MRCC_GLB_ACC0_WWDT0_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_SMARTDMA0_MASK        (0x400U)
+#define MRCC_MRCC_GLB_ACC0_SMARTDMA0_SHIFT       (10U)
+/*! SMARTDMA0 - SMARTDMA0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_SMARTDMA0(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_SMARTDMA0_SHIFT)) & MRCC_MRCC_GLB_ACC0_SMARTDMA0_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_DMA0_MASK             (0x800U)
+#define MRCC_MRCC_GLB_ACC0_DMA0_SHIFT            (11U)
+/*! DMA0 - DMA0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_DMA0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_DMA0_SHIFT)) & MRCC_MRCC_GLB_ACC0_DMA0_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_AOI0_MASK             (0x1000U)
+#define MRCC_MRCC_GLB_ACC0_AOI0_SHIFT            (12U)
+/*! AOI0 - AOI0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_AOI0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_AOI0_SHIFT)) & MRCC_MRCC_GLB_ACC0_AOI0_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_CRC0_MASK             (0x2000U)
+#define MRCC_MRCC_GLB_ACC0_CRC0_SHIFT            (13U)
+/*! CRC0 - CRC0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_CRC0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CRC0_SHIFT)) & MRCC_MRCC_GLB_ACC0_CRC0_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_EIM0_MASK             (0x4000U)
+#define MRCC_MRCC_GLB_ACC0_EIM0_SHIFT            (14U)
+/*! EIM0 - EIM0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_EIM0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_EIM0_SHIFT)) & MRCC_MRCC_GLB_ACC0_EIM0_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_ERM0_MASK             (0x8000U)
+#define MRCC_MRCC_GLB_ACC0_ERM0_SHIFT            (15U)
+/*! ERM0 - ERM0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_ERM0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_ERM0_SHIFT)) & MRCC_MRCC_GLB_ACC0_ERM0_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_AOI1_MASK             (0x20000U)
+#define MRCC_MRCC_GLB_ACC0_AOI1_SHIFT            (17U)
+/*! AOI1 - AOI1
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_AOI1(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_AOI1_SHIFT)) & MRCC_MRCC_GLB_ACC0_AOI1_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_LPI2C0_MASK           (0x80000U)
+#define MRCC_MRCC_GLB_ACC0_LPI2C0_SHIFT          (19U)
+/*! LPI2C0 - LPI2C0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_LPI2C0(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPI2C0_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPI2C0_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_LPI2C1_MASK           (0x100000U)
+#define MRCC_MRCC_GLB_ACC0_LPI2C1_SHIFT          (20U)
+/*! LPI2C1 - LPI2C1
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_LPI2C1(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPI2C1_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPI2C1_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_LPSPI0_MASK           (0x200000U)
+#define MRCC_MRCC_GLB_ACC0_LPSPI0_SHIFT          (21U)
+/*! LPSPI0 - LPSPI0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_LPSPI0(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPSPI0_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPSPI0_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_LPSPI1_MASK           (0x400000U)
+#define MRCC_MRCC_GLB_ACC0_LPSPI1_SHIFT          (22U)
+/*! LPSPI1 - LPSPI1
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_LPSPI1(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPSPI1_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPSPI1_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_LPUART0_MASK          (0x800000U)
+#define MRCC_MRCC_GLB_ACC0_LPUART0_SHIFT         (23U)
+/*! LPUART0 - LPUART0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_LPUART0(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART0_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART0_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_LPUART1_MASK          (0x1000000U)
+#define MRCC_MRCC_GLB_ACC0_LPUART1_SHIFT         (24U)
+/*! LPUART1 - LPUART1
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_LPUART1(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART1_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART1_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_LPUART2_MASK          (0x2000000U)
+#define MRCC_MRCC_GLB_ACC0_LPUART2_SHIFT         (25U)
+/*! LPUART2 - LPUART2
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_LPUART2(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART2_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART2_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_LPUART3_MASK          (0x4000000U)
+#define MRCC_MRCC_GLB_ACC0_LPUART3_SHIFT         (26U)
+/*! LPUART3 - LPUART3
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_LPUART3(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART3_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART3_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_QDC0_MASK             (0x20000000U)
+#define MRCC_MRCC_GLB_ACC0_QDC0_SHIFT            (29U)
+/*! QDC0 - QDC0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_QDC0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_QDC0_SHIFT)) & MRCC_MRCC_GLB_ACC0_QDC0_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_QDC1_MASK             (0x40000000U)
+#define MRCC_MRCC_GLB_ACC0_QDC1_SHIFT            (30U)
+/*! QDC1 - QDC1
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_QDC1(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_QDC1_SHIFT)) & MRCC_MRCC_GLB_ACC0_QDC1_MASK)
+
+#define MRCC_MRCC_GLB_ACC0_FLEXPWM0_MASK         (0x80000000U)
+#define MRCC_MRCC_GLB_ACC0_FLEXPWM0_SHIFT        (31U)
+/*! FLEXPWM0 - FLEXPWM0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC0_FLEXPWM0(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_FLEXPWM0_SHIFT)) & MRCC_MRCC_GLB_ACC0_FLEXPWM0_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_ACC1 - Control Automatic Clock Gating 1 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_ACC1_FLEXPWM1_MASK         (0x1U)
+#define MRCC_MRCC_GLB_ACC1_FLEXPWM1_SHIFT        (0U)
+/*! FLEXPWM1 - FLEXPWM1
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC1_FLEXPWM1(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_FLEXPWM1_SHIFT)) & MRCC_MRCC_GLB_ACC1_FLEXPWM1_MASK)
+
+#define MRCC_MRCC_GLB_ACC1_OSTIMER0_MASK         (0x2U)
+#define MRCC_MRCC_GLB_ACC1_OSTIMER0_SHIFT        (1U)
+/*! OSTIMER0 - OSTIMER0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC1_OSTIMER0(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_OSTIMER0_SHIFT)) & MRCC_MRCC_GLB_ACC1_OSTIMER0_MASK)
+
+#define MRCC_MRCC_GLB_ACC1_ADC0_MASK             (0x4U)
+#define MRCC_MRCC_GLB_ACC1_ADC0_SHIFT            (2U)
+/*! ADC0 - ADC0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC1_ADC0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_ADC0_SHIFT)) & MRCC_MRCC_GLB_ACC1_ADC0_MASK)
+
+#define MRCC_MRCC_GLB_ACC1_ADC1_MASK             (0x8U)
+#define MRCC_MRCC_GLB_ACC1_ADC1_SHIFT            (3U)
+/*! ADC1 - ADC1
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC1_ADC1(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_ADC1_SHIFT)) & MRCC_MRCC_GLB_ACC1_ADC1_MASK)
+
+#define MRCC_MRCC_GLB_ACC1_CMP0_MASK             (0x10U)
+#define MRCC_MRCC_GLB_ACC1_CMP0_SHIFT            (4U)
+/*! CMP0 - CMP0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC1_CMP0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_CMP0_SHIFT)) & MRCC_MRCC_GLB_ACC1_CMP0_MASK)
+
+#define MRCC_MRCC_GLB_ACC1_CMP1_MASK             (0x20U)
+#define MRCC_MRCC_GLB_ACC1_CMP1_SHIFT            (5U)
+/*! CMP1 - CMP1
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC1_CMP1(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_CMP1_SHIFT)) & MRCC_MRCC_GLB_ACC1_CMP1_MASK)
+
+#define MRCC_MRCC_GLB_ACC1_CMP2_MASK             (0x40U)
+#define MRCC_MRCC_GLB_ACC1_CMP2_SHIFT            (6U)
+/*! CMP2 - CMP2
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC1_CMP2(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_CMP2_SHIFT)) & MRCC_MRCC_GLB_ACC1_CMP2_MASK)
+
+#define MRCC_MRCC_GLB_ACC1_OPAMP0_MASK           (0x100U)
+#define MRCC_MRCC_GLB_ACC1_OPAMP0_SHIFT          (8U)
+/*! OPAMP0 - OPAMP0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC1_OPAMP0(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_OPAMP0_SHIFT)) & MRCC_MRCC_GLB_ACC1_OPAMP0_MASK)
+
+#define MRCC_MRCC_GLB_ACC1_OPAMP1_MASK           (0x200U)
+#define MRCC_MRCC_GLB_ACC1_OPAMP1_SHIFT          (9U)
+/*! OPAMP1 - OPAMP1
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC1_OPAMP1(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_OPAMP1_SHIFT)) & MRCC_MRCC_GLB_ACC1_OPAMP1_MASK)
+
+#define MRCC_MRCC_GLB_ACC1_OPAMP2_MASK           (0x400U)
+#define MRCC_MRCC_GLB_ACC1_OPAMP2_SHIFT          (10U)
+/*! OPAMP2 - OPAMP2
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC1_OPAMP2(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_OPAMP2_SHIFT)) & MRCC_MRCC_GLB_ACC1_OPAMP2_MASK)
+
+#define MRCC_MRCC_GLB_ACC1_PORT0_MASK            (0x1000U)
+#define MRCC_MRCC_GLB_ACC1_PORT0_SHIFT           (12U)
+/*! PORT0 - PORT0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC1_PORT0(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT0_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT0_MASK)
+
+#define MRCC_MRCC_GLB_ACC1_PORT1_MASK            (0x2000U)
+#define MRCC_MRCC_GLB_ACC1_PORT1_SHIFT           (13U)
+/*! PORT1 - PORT1
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC1_PORT1(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT1_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT1_MASK)
+
+#define MRCC_MRCC_GLB_ACC1_PORT2_MASK            (0x4000U)
+#define MRCC_MRCC_GLB_ACC1_PORT2_SHIFT           (14U)
+/*! PORT2 - PORT2
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC1_PORT2(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT2_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT2_MASK)
+
+#define MRCC_MRCC_GLB_ACC1_PORT3_MASK            (0x8000U)
+#define MRCC_MRCC_GLB_ACC1_PORT3_SHIFT           (15U)
+/*! PORT3 - PORT3
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC1_PORT3(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT3_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT3_MASK)
+
+#define MRCC_MRCC_GLB_ACC1_PORT4_MASK            (0x10000U)
+#define MRCC_MRCC_GLB_ACC1_PORT4_SHIFT           (16U)
+/*! PORT4 - PORT4
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC1_PORT4(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT4_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT4_MASK)
+
+#define MRCC_MRCC_GLB_ACC1_FLEXCAN0_MASK         (0x40000U)
+#define MRCC_MRCC_GLB_ACC1_FLEXCAN0_SHIFT        (18U)
+/*! FLEXCAN0 - FLEXCAN0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC1_FLEXCAN0(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_FLEXCAN0_SHIFT)) & MRCC_MRCC_GLB_ACC1_FLEXCAN0_MASK)
+/*! @} */
+
+/*! @name MRCC_GLB_ACC2 - Control Automatic Clock Gating 2 */
+/*! @{ */
+
+#define MRCC_MRCC_GLB_ACC2_RAMA_MASK             (0x2U)
+#define MRCC_MRCC_GLB_ACC2_RAMA_SHIFT            (1U)
+/*! RAMA - RAMA
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC2_RAMA(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_RAMA_SHIFT)) & MRCC_MRCC_GLB_ACC2_RAMA_MASK)
+
+#define MRCC_MRCC_GLB_ACC2_RAMB_MASK             (0x4U)
+#define MRCC_MRCC_GLB_ACC2_RAMB_SHIFT            (2U)
+/*! RAMB - RAMB
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC2_RAMB(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_RAMB_SHIFT)) & MRCC_MRCC_GLB_ACC2_RAMB_MASK)
+
+#define MRCC_MRCC_GLB_ACC2_RAMC_MASK             (0x8U)
+#define MRCC_MRCC_GLB_ACC2_RAMC_SHIFT            (3U)
+/*! RAMC - RAMC
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC2_RAMC(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_RAMC_SHIFT)) & MRCC_MRCC_GLB_ACC2_RAMC_MASK)
+
+#define MRCC_MRCC_GLB_ACC2_GPIO0_MASK            (0x10U)
+#define MRCC_MRCC_GLB_ACC2_GPIO0_SHIFT           (4U)
+/*! GPIO0 - GPIO0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC2_GPIO0(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_GPIO0_SHIFT)) & MRCC_MRCC_GLB_ACC2_GPIO0_MASK)
+
+#define MRCC_MRCC_GLB_ACC2_GPIO1_MASK            (0x20U)
+#define MRCC_MRCC_GLB_ACC2_GPIO1_SHIFT           (5U)
+/*! GPIO1 - GPIO1
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC2_GPIO1(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_GPIO1_SHIFT)) & MRCC_MRCC_GLB_ACC2_GPIO1_MASK)
+
+#define MRCC_MRCC_GLB_ACC2_GPIO2_MASK            (0x40U)
+#define MRCC_MRCC_GLB_ACC2_GPIO2_SHIFT           (6U)
+/*! GPIO2 - GPIO2
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC2_GPIO2(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_GPIO2_SHIFT)) & MRCC_MRCC_GLB_ACC2_GPIO2_MASK)
+
+#define MRCC_MRCC_GLB_ACC2_GPIO3_MASK            (0x80U)
+#define MRCC_MRCC_GLB_ACC2_GPIO3_SHIFT           (7U)
+/*! GPIO3 - GPIO3
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC2_GPIO3(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_GPIO3_SHIFT)) & MRCC_MRCC_GLB_ACC2_GPIO3_MASK)
+
+#define MRCC_MRCC_GLB_ACC2_GPIO4_MASK            (0x100U)
+#define MRCC_MRCC_GLB_ACC2_GPIO4_SHIFT           (8U)
+/*! GPIO4 - GPIO4
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC2_GPIO4(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_GPIO4_SHIFT)) & MRCC_MRCC_GLB_ACC2_GPIO4_MASK)
+
+#define MRCC_MRCC_GLB_ACC2_MAU0_MASK             (0x200U)
+#define MRCC_MRCC_GLB_ACC2_MAU0_SHIFT            (9U)
+/*! MAU0 - MAU0
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC2_MAU0(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_MAU0_SHIFT)) & MRCC_MRCC_GLB_ACC2_MAU0_MASK)
+
+#define MRCC_MRCC_GLB_ACC2_ROMC_MASK             (0x400U)
+#define MRCC_MRCC_GLB_ACC2_ROMC_SHIFT            (10U)
+/*! ROMC - ROMC
+ *  0b0..Automatic clock gating is disabled
+ *  0b1..Automatic clock gating is enabled
+ */
+#define MRCC_MRCC_GLB_ACC2_ROMC(x)               (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_ROMC_SHIFT)) & MRCC_MRCC_GLB_ACC2_ROMC_MASK)
+/*! @} */
+
+/*! @name MRCC_CTIMER0_CLKSEL - CTIMER0 clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_CTIMER0_CLKSEL_MUX_MASK        (0x7U)
+#define MRCC_MRCC_CTIMER0_CLKSEL_MUX_SHIFT       (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_LF_DIV
+ *  0b001..FRO_HF_GATED
+ *  0b011..CLK_IN
+ *  0b100..CLK_16K
+ *  0b101..CLK_1M
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_CTIMER0_CLKSEL_MUX(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER0_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_CTIMER0_CLKDIV - CTIMER0 clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_CTIMER0_CLKDIV_DIV_MASK        (0xFU)
+#define MRCC_MRCC_CTIMER0_CLKDIV_DIV_SHIFT       (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_CTIMER0_CLKDIV_DIV(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_CTIMER0_CLKDIV_RESET_MASK      (0x20000000U)
+#define MRCC_MRCC_CTIMER0_CLKDIV_RESET_SHIFT     (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_CTIMER0_CLKDIV_RESET(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_CTIMER0_CLKDIV_HALT_MASK       (0x40000000U)
+#define MRCC_MRCC_CTIMER0_CLKDIV_HALT_SHIFT      (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_CTIMER0_CLKDIV_HALT(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_MASK     (0x80000000U)
+#define MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_SHIFT    (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB(x)       (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_CTIMER1_CLKSEL - CTIMER1 clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_CTIMER1_CLKSEL_MUX_MASK        (0x7U)
+#define MRCC_MRCC_CTIMER1_CLKSEL_MUX_SHIFT       (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_LF_DIV
+ *  0b001..FRO_HF_GATED
+ *  0b011..CLK_IN
+ *  0b100..CLK_16K
+ *  0b101..CLK_1M
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_CTIMER1_CLKSEL_MUX(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER1_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_CTIMER1_CLKDIV - CTIMER1 clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_CTIMER1_CLKDIV_DIV_MASK        (0xFU)
+#define MRCC_MRCC_CTIMER1_CLKDIV_DIV_SHIFT       (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_CTIMER1_CLKDIV_DIV(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_CTIMER1_CLKDIV_RESET_MASK      (0x20000000U)
+#define MRCC_MRCC_CTIMER1_CLKDIV_RESET_SHIFT     (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_CTIMER1_CLKDIV_RESET(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_CTIMER1_CLKDIV_HALT_MASK       (0x40000000U)
+#define MRCC_MRCC_CTIMER1_CLKDIV_HALT_SHIFT      (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_CTIMER1_CLKDIV_HALT(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_MASK     (0x80000000U)
+#define MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_SHIFT    (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB(x)       (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_CTIMER2_CLKSEL - CTIMER2 clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_CTIMER2_CLKSEL_MUX_MASK        (0x7U)
+#define MRCC_MRCC_CTIMER2_CLKSEL_MUX_SHIFT       (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_LF_DIV
+ *  0b001..FRO_HF_GATED
+ *  0b011..CLK_IN
+ *  0b100..CLK_16K
+ *  0b101..CLK_1M
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_CTIMER2_CLKSEL_MUX(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER2_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_CTIMER2_CLKDIV - CTIMER2 clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_CTIMER2_CLKDIV_DIV_MASK        (0xFU)
+#define MRCC_MRCC_CTIMER2_CLKDIV_DIV_SHIFT       (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_CTIMER2_CLKDIV_DIV(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_CTIMER2_CLKDIV_RESET_MASK      (0x20000000U)
+#define MRCC_MRCC_CTIMER2_CLKDIV_RESET_SHIFT     (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_CTIMER2_CLKDIV_RESET(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_CTIMER2_CLKDIV_HALT_MASK       (0x40000000U)
+#define MRCC_MRCC_CTIMER2_CLKDIV_HALT_SHIFT      (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_CTIMER2_CLKDIV_HALT(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_MASK     (0x80000000U)
+#define MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_SHIFT    (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB(x)       (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_WWDT0_CLKDIV - WWDT0 clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_WWDT0_CLKDIV_DIV_MASK          (0xFU)
+#define MRCC_MRCC_WWDT0_CLKDIV_DIV_SHIFT         (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_WWDT0_CLKDIV_DIV(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_WWDT0_CLKDIV_RESET_MASK        (0x20000000U)
+#define MRCC_MRCC_WWDT0_CLKDIV_RESET_SHIFT       (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_WWDT0_CLKDIV_RESET(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_WWDT0_CLKDIV_HALT_MASK         (0x40000000U)
+#define MRCC_MRCC_WWDT0_CLKDIV_HALT_SHIFT        (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_WWDT0_CLKDIV_HALT(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_MASK       (0x80000000U)
+#define MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_SHIFT      (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_WWDT0_CLKDIV_UNSTAB(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_LPI2C0_CLKSEL - LPI2C0 clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_LPI2C0_CLKSEL_MUX_MASK         (0x7U)
+#define MRCC_MRCC_LPI2C0_CLKSEL_MUX_SHIFT        (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_LF_DIV
+ *  0b010..FRO_HF_DIV
+ *  0b011..CLK_IN
+ *  0b101..CLK_1M
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_LPI2C0_CLKSEL_MUX(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPI2C0_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_LPI2C0_CLKDIV - LPI2C0 clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_LPI2C0_CLKDIV_DIV_MASK         (0xFU)
+#define MRCC_MRCC_LPI2C0_CLKDIV_DIV_SHIFT        (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_LPI2C0_CLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_LPI2C0_CLKDIV_RESET_MASK       (0x20000000U)
+#define MRCC_MRCC_LPI2C0_CLKDIV_RESET_SHIFT      (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_LPI2C0_CLKDIV_RESET(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_LPI2C0_CLKDIV_HALT_MASK        (0x40000000U)
+#define MRCC_MRCC_LPI2C0_CLKDIV_HALT_SHIFT       (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_LPI2C0_CLKDIV_HALT(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_MASK      (0x80000000U)
+#define MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_SHIFT     (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_LPI2C1_CLKSEL - LPI2C1 clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_LPI2C1_CLKSEL_MUX_MASK         (0x7U)
+#define MRCC_MRCC_LPI2C1_CLKSEL_MUX_SHIFT        (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_LF_DIV
+ *  0b010..FRO_HF_DIV
+ *  0b011..CLK_IN
+ *  0b101..CLK_1M
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_LPI2C1_CLKSEL_MUX(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPI2C1_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_LPI2C1_CLKDIV - LPI2C1 clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_LPI2C1_CLKDIV_DIV_MASK         (0xFU)
+#define MRCC_MRCC_LPI2C1_CLKDIV_DIV_SHIFT        (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_LPI2C1_CLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPI2C1_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_LPI2C1_CLKDIV_RESET_MASK       (0x20000000U)
+#define MRCC_MRCC_LPI2C1_CLKDIV_RESET_SHIFT      (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_LPI2C1_CLKDIV_RESET(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPI2C1_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_LPI2C1_CLKDIV_HALT_MASK        (0x40000000U)
+#define MRCC_MRCC_LPI2C1_CLKDIV_HALT_SHIFT       (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_LPI2C1_CLKDIV_HALT(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPI2C1_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB_MASK      (0x80000000U)
+#define MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB_SHIFT     (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_LPSPI0_CLKSEL - LPSPI0 clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_LPSPI0_CLKSEL_MUX_MASK         (0x7U)
+#define MRCC_MRCC_LPSPI0_CLKSEL_MUX_SHIFT        (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_LF_DIV
+ *  0b010..FRO_HF_DIV
+ *  0b011..CLK_IN
+ *  0b101..CLK_1M
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_LPSPI0_CLKSEL_MUX(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPSPI0_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_LPSPI0_CLKDIV - LPSPI0 clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_LPSPI0_CLKDIV_DIV_MASK         (0xFU)
+#define MRCC_MRCC_LPSPI0_CLKDIV_DIV_SHIFT        (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_LPSPI0_CLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_LPSPI0_CLKDIV_RESET_MASK       (0x20000000U)
+#define MRCC_MRCC_LPSPI0_CLKDIV_RESET_SHIFT      (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_LPSPI0_CLKDIV_RESET(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_LPSPI0_CLKDIV_HALT_MASK        (0x40000000U)
+#define MRCC_MRCC_LPSPI0_CLKDIV_HALT_SHIFT       (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_LPSPI0_CLKDIV_HALT(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_MASK      (0x80000000U)
+#define MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_SHIFT     (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_LPSPI1_CLKSEL - LPSPI1 clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_LPSPI1_CLKSEL_MUX_MASK         (0x7U)
+#define MRCC_MRCC_LPSPI1_CLKSEL_MUX_SHIFT        (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_LF_DIV
+ *  0b010..FRO_HF_DIV
+ *  0b011..CLK_IN
+ *  0b101..CLK_1M
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_LPSPI1_CLKSEL_MUX(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPSPI1_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_LPSPI1_CLKDIV - LPSPI1 clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_LPSPI1_CLKDIV_DIV_MASK         (0xFU)
+#define MRCC_MRCC_LPSPI1_CLKDIV_DIV_SHIFT        (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_LPSPI1_CLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_LPSPI1_CLKDIV_RESET_MASK       (0x20000000U)
+#define MRCC_MRCC_LPSPI1_CLKDIV_RESET_SHIFT      (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_LPSPI1_CLKDIV_RESET(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_LPSPI1_CLKDIV_HALT_MASK        (0x40000000U)
+#define MRCC_MRCC_LPSPI1_CLKDIV_HALT_SHIFT       (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_LPSPI1_CLKDIV_HALT(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_MASK      (0x80000000U)
+#define MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_SHIFT     (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_LPUART0_CLKSEL - LPUART0 clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_LPUART0_CLKSEL_MUX_MASK        (0x7U)
+#define MRCC_MRCC_LPUART0_CLKSEL_MUX_SHIFT       (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_LF_DIV
+ *  0b010..FRO_HF_DIV
+ *  0b011..CLK_IN
+ *  0b100..CLK_16K
+ *  0b101..CLK_1M
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_LPUART0_CLKSEL_MUX(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART0_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_LPUART0_CLKDIV - LPUART0 clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_LPUART0_CLKDIV_DIV_MASK        (0xFU)
+#define MRCC_MRCC_LPUART0_CLKDIV_DIV_SHIFT       (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_LPUART0_CLKDIV_DIV(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_LPUART0_CLKDIV_RESET_MASK      (0x20000000U)
+#define MRCC_MRCC_LPUART0_CLKDIV_RESET_SHIFT     (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_LPUART0_CLKDIV_RESET(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_LPUART0_CLKDIV_HALT_MASK       (0x40000000U)
+#define MRCC_MRCC_LPUART0_CLKDIV_HALT_SHIFT      (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_LPUART0_CLKDIV_HALT(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_MASK     (0x80000000U)
+#define MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_SHIFT    (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_LPUART0_CLKDIV_UNSTAB(x)       (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_LPUART1_CLKSEL - LPUART1 clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_LPUART1_CLKSEL_MUX_MASK        (0x7U)
+#define MRCC_MRCC_LPUART1_CLKSEL_MUX_SHIFT       (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_LF_DIV
+ *  0b010..FRO_HF_DIV
+ *  0b011..CLK_IN
+ *  0b100..CLK_16K
+ *  0b101..CLK_1M
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_LPUART1_CLKSEL_MUX(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART1_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_LPUART1_CLKDIV - LPUART1 clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_LPUART1_CLKDIV_DIV_MASK        (0xFU)
+#define MRCC_MRCC_LPUART1_CLKDIV_DIV_SHIFT       (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_LPUART1_CLKDIV_DIV(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_LPUART1_CLKDIV_RESET_MASK      (0x20000000U)
+#define MRCC_MRCC_LPUART1_CLKDIV_RESET_SHIFT     (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_LPUART1_CLKDIV_RESET(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_LPUART1_CLKDIV_HALT_MASK       (0x40000000U)
+#define MRCC_MRCC_LPUART1_CLKDIV_HALT_SHIFT      (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_LPUART1_CLKDIV_HALT(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_MASK     (0x80000000U)
+#define MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_SHIFT    (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_LPUART1_CLKDIV_UNSTAB(x)       (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_LPUART2_CLKSEL - LPUART2 clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_LPUART2_CLKSEL_MUX_MASK        (0x7U)
+#define MRCC_MRCC_LPUART2_CLKSEL_MUX_SHIFT       (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_LF_DIV
+ *  0b010..FRO_HF_DIV
+ *  0b011..CLK_IN
+ *  0b100..CLK_16K
+ *  0b101..CLK_1M
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_LPUART2_CLKSEL_MUX(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART2_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_LPUART2_CLKDIV - LPUART2 clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_LPUART2_CLKDIV_DIV_MASK        (0xFU)
+#define MRCC_MRCC_LPUART2_CLKDIV_DIV_SHIFT       (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_LPUART2_CLKDIV_DIV(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_LPUART2_CLKDIV_RESET_MASK      (0x20000000U)
+#define MRCC_MRCC_LPUART2_CLKDIV_RESET_SHIFT     (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_LPUART2_CLKDIV_RESET(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_LPUART2_CLKDIV_HALT_MASK       (0x40000000U)
+#define MRCC_MRCC_LPUART2_CLKDIV_HALT_SHIFT      (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_LPUART2_CLKDIV_HALT(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_MASK     (0x80000000U)
+#define MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_SHIFT    (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_LPUART2_CLKDIV_UNSTAB(x)       (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_LPUART3_CLKSEL - LPUART3 clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_LPUART3_CLKSEL_MUX_MASK        (0x7U)
+#define MRCC_MRCC_LPUART3_CLKSEL_MUX_SHIFT       (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_LF_DIV
+ *  0b010..FRO_HF_DIV
+ *  0b011..CLK_IN
+ *  0b100..CLK_16K
+ *  0b101..CLK_1M
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_LPUART3_CLKSEL_MUX(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART3_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_LPUART3_CLKDIV - LPUART3 clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_LPUART3_CLKDIV_DIV_MASK        (0xFU)
+#define MRCC_MRCC_LPUART3_CLKDIV_DIV_SHIFT       (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_LPUART3_CLKDIV_DIV(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART3_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_LPUART3_CLKDIV_RESET_MASK      (0x20000000U)
+#define MRCC_MRCC_LPUART3_CLKDIV_RESET_SHIFT     (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_LPUART3_CLKDIV_RESET(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART3_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_LPUART3_CLKDIV_HALT_MASK       (0x40000000U)
+#define MRCC_MRCC_LPUART3_CLKDIV_HALT_SHIFT      (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_LPUART3_CLKDIV_HALT(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART3_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_LPUART3_CLKDIV_UNSTAB_MASK     (0x80000000U)
+#define MRCC_MRCC_LPUART3_CLKDIV_UNSTAB_SHIFT    (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_LPUART3_CLKDIV_UNSTAB(x)       (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART3_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_LPTMR0_CLKSEL - LPTMR0 clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_LPTMR0_CLKSEL_MUX_MASK         (0x7U)
+#define MRCC_MRCC_LPTMR0_CLKSEL_MUX_SHIFT        (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_LF_DIV
+ *  0b010..FRO_HF_DIV
+ *  0b011..CLK_IN
+ *  0b101..CLK_1M
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_LPTMR0_CLKSEL_MUX(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPTMR0_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_LPTMR0_CLKDIV - LPTMR0 clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_LPTMR0_CLKDIV_DIV_MASK         (0xFU)
+#define MRCC_MRCC_LPTMR0_CLKDIV_DIV_SHIFT        (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_LPTMR0_CLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_LPTMR0_CLKDIV_RESET_MASK       (0x20000000U)
+#define MRCC_MRCC_LPTMR0_CLKDIV_RESET_SHIFT      (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_LPTMR0_CLKDIV_RESET(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_LPTMR0_CLKDIV_HALT_MASK        (0x40000000U)
+#define MRCC_MRCC_LPTMR0_CLKDIV_HALT_SHIFT       (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_LPTMR0_CLKDIV_HALT(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_MASK      (0x80000000U)
+#define MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_SHIFT     (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_OSTIMER0_CLKSEL - OSTIMER0 clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_OSTIMER0_CLKSEL_MUX_MASK       (0x3U)
+#define MRCC_MRCC_OSTIMER0_CLKSEL_MUX_SHIFT      (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b00..CLK_16K
+ *  0b10..CLK_1M
+ *  0b11..Reserved2(NO Clock)
+ */
+#define MRCC_MRCC_OSTIMER0_CLKSEL_MUX(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_OSTIMER0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_OSTIMER0_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_ADC_CLKSEL - ADCx clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_ADC_CLKSEL_MUX_MASK            (0x7U)
+#define MRCC_MRCC_ADC_CLKSEL_MUX_SHIFT           (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_LF_DIV
+ *  0b001..FRO_HF_GATED
+ *  0b011..CLK_IN
+ *  0b101..CLK_1M
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_ADC_CLKSEL_MUX(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_ADC_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_ADC_CLKDIV - ADCx clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_ADC_CLKDIV_DIV_MASK            (0xFU)
+#define MRCC_MRCC_ADC_CLKDIV_DIV_SHIFT           (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_ADC_CLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_ADC_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_ADC_CLKDIV_RESET_MASK          (0x20000000U)
+#define MRCC_MRCC_ADC_CLKDIV_RESET_SHIFT         (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_ADC_CLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_ADC_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_ADC_CLKDIV_HALT_MASK           (0x40000000U)
+#define MRCC_MRCC_ADC_CLKDIV_HALT_SHIFT          (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_ADC_CLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_ADC_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_ADC_CLKDIV_UNSTAB_MASK         (0x80000000U)
+#define MRCC_MRCC_ADC_CLKDIV_UNSTAB_SHIFT        (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_ADC_CLKDIV_UNSTAB(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_ADC_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_CMP0_FUNC_CLKDIV - CMP0_FUNC clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_MASK      (0xFU)
+#define MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_SHIFT     (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_MASK    (0x20000000U)
+#define MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_SHIFT   (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET(x)      (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_MASK     (0x40000000U)
+#define MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_SHIFT    (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT(x)       (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_MASK   (0x80000000U)
+#define MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_SHIFT  (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB(x)     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_CMP0_RR_CLKSEL - CMP0_RR clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_CMP0_RR_CLKSEL_MUX_MASK        (0x7U)
+#define MRCC_MRCC_CMP0_RR_CLKSEL_MUX_SHIFT       (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_LF_DIV
+ *  0b010..FRO_HF_DIV
+ *  0b011..CLK_IN
+ *  0b101..CLK_1M
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_CMP0_RR_CLKSEL_MUX(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_CMP0_RR_CLKDIV - CMP0_RR clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_CMP0_RR_CLKDIV_DIV_MASK        (0xFU)
+#define MRCC_MRCC_CMP0_RR_CLKDIV_DIV_SHIFT       (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_CMP0_RR_CLKDIV_DIV(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_CMP0_RR_CLKDIV_RESET_MASK      (0x20000000U)
+#define MRCC_MRCC_CMP0_RR_CLKDIV_RESET_SHIFT     (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_CMP0_RR_CLKDIV_RESET(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_CMP0_RR_CLKDIV_HALT_MASK       (0x40000000U)
+#define MRCC_MRCC_CMP0_RR_CLKDIV_HALT_SHIFT      (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_CMP0_RR_CLKDIV_HALT(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_MASK     (0x80000000U)
+#define MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_SHIFT    (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB(x)       (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_CMP1_FUNC_CLKDIV - CMP1_FUNC clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_MASK      (0xFU)
+#define MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_SHIFT     (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_MASK    (0x20000000U)
+#define MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_SHIFT   (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET(x)      (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_MASK     (0x40000000U)
+#define MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_SHIFT    (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT(x)       (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_MASK   (0x80000000U)
+#define MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_SHIFT  (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB(x)     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_CMP1_RR_CLKSEL - CMP1_RR clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_CMP1_RR_CLKSEL_MUX_MASK        (0x7U)
+#define MRCC_MRCC_CMP1_RR_CLKSEL_MUX_SHIFT       (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_LF_DIV
+ *  0b010..FRO_HF_DIV
+ *  0b011..CLK_IN
+ *  0b101..CLK_1M
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_CMP1_RR_CLKSEL_MUX(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_CMP1_RR_CLKDIV - CMP1_RR clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_CMP1_RR_CLKDIV_DIV_MASK        (0xFU)
+#define MRCC_MRCC_CMP1_RR_CLKDIV_DIV_SHIFT       (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_CMP1_RR_CLKDIV_DIV(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_CMP1_RR_CLKDIV_RESET_MASK      (0x20000000U)
+#define MRCC_MRCC_CMP1_RR_CLKDIV_RESET_SHIFT     (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_CMP1_RR_CLKDIV_RESET(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_CMP1_RR_CLKDIV_HALT_MASK       (0x40000000U)
+#define MRCC_MRCC_CMP1_RR_CLKDIV_HALT_SHIFT      (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_CMP1_RR_CLKDIV_HALT(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_MASK     (0x80000000U)
+#define MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_SHIFT    (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB(x)       (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_CMP2_FUNC_CLKDIV - CMP2_FUNC clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_CMP2_FUNC_CLKDIV_DIV_MASK      (0xFU)
+#define MRCC_MRCC_CMP2_FUNC_CLKDIV_DIV_SHIFT     (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_CMP2_FUNC_CLKDIV_DIV(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_FUNC_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP2_FUNC_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_CMP2_FUNC_CLKDIV_RESET_MASK    (0x20000000U)
+#define MRCC_MRCC_CMP2_FUNC_CLKDIV_RESET_SHIFT   (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_CMP2_FUNC_CLKDIV_RESET(x)      (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_FUNC_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP2_FUNC_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_CMP2_FUNC_CLKDIV_HALT_MASK     (0x40000000U)
+#define MRCC_MRCC_CMP2_FUNC_CLKDIV_HALT_SHIFT    (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_CMP2_FUNC_CLKDIV_HALT(x)       (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_FUNC_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP2_FUNC_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_CMP2_FUNC_CLKDIV_UNSTAB_MASK   (0x80000000U)
+#define MRCC_MRCC_CMP2_FUNC_CLKDIV_UNSTAB_SHIFT  (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_CMP2_FUNC_CLKDIV_UNSTAB(x)     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_FUNC_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP2_FUNC_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_CMP2_RR_CLKSEL - CMP2_RR clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_CMP2_RR_CLKSEL_MUX_MASK        (0x7U)
+#define MRCC_MRCC_CMP2_RR_CLKSEL_MUX_SHIFT       (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_LF_DIV
+ *  0b010..FRO_HF_DIV
+ *  0b011..CLK_IN
+ *  0b101..CLK_1M
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_CMP2_RR_CLKSEL_MUX(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_RR_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CMP2_RR_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_CMP2_RR_CLKDIV - CMP2_RR clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_CMP2_RR_CLKDIV_DIV_MASK        (0xFU)
+#define MRCC_MRCC_CMP2_RR_CLKDIV_DIV_SHIFT       (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_CMP2_RR_CLKDIV_DIV(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_RR_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP2_RR_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_CMP2_RR_CLKDIV_RESET_MASK      (0x20000000U)
+#define MRCC_MRCC_CMP2_RR_CLKDIV_RESET_SHIFT     (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_CMP2_RR_CLKDIV_RESET(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_RR_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP2_RR_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_CMP2_RR_CLKDIV_HALT_MASK       (0x40000000U)
+#define MRCC_MRCC_CMP2_RR_CLKDIV_HALT_SHIFT      (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_CMP2_RR_CLKDIV_HALT(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_RR_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP2_RR_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_CMP2_RR_CLKDIV_UNSTAB_MASK     (0x80000000U)
+#define MRCC_MRCC_CMP2_RR_CLKDIV_UNSTAB_SHIFT    (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_CMP2_RR_CLKDIV_UNSTAB(x)       (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_RR_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP2_RR_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_FLEXCAN0_CLKSEL - FLEXCAN0 clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_FLEXCAN0_CLKSEL_MUX_MASK       (0x7U)
+#define MRCC_MRCC_FLEXCAN0_CLKSEL_MUX_SHIFT      (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b001..FRO_HF_GATED
+ *  0b010..FRO_HF_DIV
+ *  0b011..CLK_IN
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_FLEXCAN0_CLKSEL_MUX(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_FLEXCAN0_CLKDIV - FLEXCAN0 clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_FLEXCAN0_CLKDIV_DIV_MASK       (0xFU)
+#define MRCC_MRCC_FLEXCAN0_CLKDIV_DIV_SHIFT      (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_FLEXCAN0_CLKDIV_DIV(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_FLEXCAN0_CLKDIV_RESET_MASK     (0x20000000U)
+#define MRCC_MRCC_FLEXCAN0_CLKDIV_RESET_SHIFT    (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_FLEXCAN0_CLKDIV_RESET(x)       (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_FLEXCAN0_CLKDIV_HALT_MASK      (0x40000000U)
+#define MRCC_MRCC_FLEXCAN0_CLKDIV_HALT_SHIFT     (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_FLEXCAN0_CLKDIV_HALT(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB_MASK    (0x80000000U)
+#define MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB_SHIFT   (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB(x)      (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_DBG_TRACE_CLKSEL - DBG_TRACE clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_MASK      (0x3U)
+#define MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_SHIFT     (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b00..CPU_CLK
+ *  0b01..CLK_1M
+ *  0b10..CLK_16K
+ *  0b11..Reserved1(NO Clock)
+ */
+#define MRCC_MRCC_DBG_TRACE_CLKSEL_MUX(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_DBG_TRACE_CLKDIV - DBG_TRACE clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_MASK      (0xFU)
+#define MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_SHIFT     (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_DBG_TRACE_CLKDIV_DIV(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_MASK    (0x20000000U)
+#define MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_SHIFT   (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_DBG_TRACE_CLKDIV_RESET(x)      (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_MASK     (0x40000000U)
+#define MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_SHIFT    (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_DBG_TRACE_CLKDIV_HALT(x)       (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_MASK   (0x80000000U)
+#define MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_SHIFT  (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB(x)     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name MRCC_CLKOUT_CLKSEL - CLKOUT clock selection control */
+/*! @{ */
+
+#define MRCC_MRCC_CLKOUT_CLKSEL_MUX_MASK         (0x7U)
+#define MRCC_MRCC_CLKOUT_CLKSEL_MUX_SHIFT        (0U)
+/*! MUX - Functional Clock Mux Select
+ *  0b000..FRO_12M
+ *  0b001..FRO_HF_DIV
+ *  0b010..CLK_IN
+ *  0b011..CLK_16K
+ *  0b110..SLOW_CLK
+ *  0b111..Reserved(NO Clock)
+ */
+#define MRCC_MRCC_CLKOUT_CLKSEL_MUX(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CLKOUT_CLKSEL_MUX_MASK)
+/*! @} */
+
+/*! @name MRCC_CLKOUT_CLKDIV - CLKOUT clock divider control */
+/*! @{ */
+
+#define MRCC_MRCC_CLKOUT_CLKDIV_DIV_MASK         (0xFU)
+#define MRCC_MRCC_CLKOUT_CLKDIV_DIV_SHIFT        (0U)
+/*! DIV - Functional Clock Divider */
+#define MRCC_MRCC_CLKOUT_CLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_DIV_MASK)
+
+#define MRCC_MRCC_CLKOUT_CLKDIV_RESET_MASK       (0x20000000U)
+#define MRCC_MRCC_CLKOUT_CLKDIV_RESET_SHIFT      (29U)
+/*! RESET - Reset divider counter
+ *  0b0..Divider isn't reset
+ *  0b1..Divider is reset
+ */
+#define MRCC_MRCC_CLKOUT_CLKDIV_RESET(x)         (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_RESET_MASK)
+
+#define MRCC_MRCC_CLKOUT_CLKDIV_HALT_MASK        (0x40000000U)
+#define MRCC_MRCC_CLKOUT_CLKDIV_HALT_SHIFT       (30U)
+/*! HALT - Halt divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define MRCC_MRCC_CLKOUT_CLKDIV_HALT(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_HALT_MASK)
+
+#define MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_MASK      (0x80000000U)
+#define MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_SHIFT     (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency isn't stable
+ */
+#define MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MRCC_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group MRCC_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_MRCC_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_OPAMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_OPAMP.h
new file mode 100644
index 0000000000..29dfaecca4
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_OPAMP.h
@@ -0,0 +1,204 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for OPAMP
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_OPAMP.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for OPAMP
+ *
+ * CMSIS Peripheral Access Layer for OPAMP
+ */
+
+#if !defined(PERI_OPAMP_H_)
+#define PERI_OPAMP_H_                            /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- OPAMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OPAMP_Peripheral_Access_Layer OPAMP Peripheral Access Layer
+ * @{
+ */
+
+/** OPAMP - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
+  __IO uint32_t OPAMP_CTRL;                        /**< OPAMP Control, offset: 0x8 */
+} OPAMP_Type;
+
+/* ----------------------------------------------------------------------------
+   -- OPAMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OPAMP_Register_Masks OPAMP Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID */
+/*! @{ */
+
+#define OPAMP_VERID_FEATURE_MASK                 (0xFFFFU)
+#define OPAMP_VERID_FEATURE_SHIFT                (0U)
+/*! FEATURE - Feature Specification Number */
+#define OPAMP_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_FEATURE_SHIFT)) & OPAMP_VERID_FEATURE_MASK)
+
+#define OPAMP_VERID_MINOR_MASK                   (0xFF0000U)
+#define OPAMP_VERID_MINOR_SHIFT                  (16U)
+/*! MINOR - Minor Version Number */
+#define OPAMP_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_MINOR_SHIFT)) & OPAMP_VERID_MINOR_MASK)
+
+#define OPAMP_VERID_MAJOR_MASK                   (0xFF000000U)
+#define OPAMP_VERID_MAJOR_SHIFT                  (24U)
+/*! MAJOR - Major Version Number */
+#define OPAMP_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_MAJOR_SHIFT)) & OPAMP_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter */
+/*! @{ */
+
+#define OPAMP_PARAM_PARAM_MASK                   (0xFFFFFFFFU)
+#define OPAMP_PARAM_PARAM_SHIFT                  (0U)
+/*! PARAM - Parameters */
+#define OPAMP_PARAM_PARAM(x)                     (((uint32_t)(((uint32_t)(x)) << OPAMP_PARAM_PARAM_SHIFT)) & OPAMP_PARAM_PARAM_MASK)
+/*! @} */
+
+/*! @name OPAMP_CTRL - OPAMP Control */
+/*! @{ */
+
+#define OPAMP_OPAMP_CTRL_OPA_EN_MASK             (0x1U)
+#define OPAMP_OPAMP_CTRL_OPA_EN_SHIFT            (0U)
+/*! OPA_EN - OPAMP Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define OPAMP_OPAMP_CTRL_OPA_EN(x)               (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTRL_OPA_EN_SHIFT)) & OPAMP_OPAMP_CTRL_OPA_EN_MASK)
+
+#define OPAMP_OPAMP_CTRL_OPA_CC_SEL_MASK         (0x30U)
+#define OPAMP_OPAMP_CTRL_OPA_CC_SEL_SHIFT        (4U)
+/*! OPA_CC_SEL - Compensation capcitor config selection
+ *  0b00..Fit 2X gains
+ *  0b01..Fit 4X gains
+ *  0b10..Fit 8X gains
+ *  0b11..Fit 16X gains
+ */
+#define OPAMP_OPAMP_CTRL_OPA_CC_SEL(x)           (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTRL_OPA_CC_SEL_SHIFT)) & OPAMP_OPAMP_CTRL_OPA_CC_SEL_MASK)
+
+#define OPAMP_OPAMP_CTRL_OPA_BC_SEL_MASK         (0xC0U)
+#define OPAMP_OPAMP_CTRL_OPA_BC_SEL_SHIFT        (6U)
+/*! OPA_BC_SEL - Bias current config selection
+ *  0b00..Default value. Keep power consumption constant
+ *  0b01..Reduce power consumption to 1/4
+ *  0b10..Reduce power consumption to 1/2
+ *  0b11..Increase power consumption to 3/2
+ */
+#define OPAMP_OPAMP_CTRL_OPA_BC_SEL(x)           (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTRL_OPA_BC_SEL_SHIFT)) & OPAMP_OPAMP_CTRL_OPA_BC_SEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group OPAMP_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group OPAMP_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_OPAMP_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_OSTIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_OSTIMER.h
new file mode 100644
index 0000000000..43d639b490
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_OSTIMER.h
@@ -0,0 +1,233 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for OSTIMER
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_OSTIMER.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for OSTIMER
+ *
+ * CMSIS Peripheral Access Layer for OSTIMER
+ */
+
+#if !defined(PERI_OSTIMER_H_)
+#define PERI_OSTIMER_H_                          /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- OSTIMER Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer
+ * @{
+ */
+
+/** OSTIMER - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t EVTIMERL;                          /**< EVTIMER Low, offset: 0x0 */
+  __I  uint32_t EVTIMERH;                          /**< EVTIMER High, offset: 0x4 */
+  __I  uint32_t CAPTURE_L;                         /**< Local Capture Low for CPU, offset: 0x8 */
+  __I  uint32_t CAPTURE_H;                         /**< Local Capture High for CPU, offset: 0xC */
+  __IO uint32_t MATCH_L;                           /**< Local Match Low for CPU, offset: 0x10 */
+  __IO uint32_t MATCH_H;                           /**< Local Match High for CPU, offset: 0x14 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t OSEVENT_CTRL;                      /**< OSTIMER Control for CPU, offset: 0x1C */
+} OSTIMER_Type;
+
+/* ----------------------------------------------------------------------------
+   -- OSTIMER Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks
+ * @{
+ */
+
+/*! @name EVTIMERL - EVTIMER Low */
+/*! @{ */
+
+#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)
+#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U)
+/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */
+#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK)
+/*! @} */
+
+/*! @name EVTIMERH - EVTIMER High */
+/*! @{ */
+
+#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU)
+#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U)
+/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */
+#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK)
+/*! @} */
+
+/*! @name CAPTURE_L - Local Capture Low for CPU */
+/*! @{ */
+
+#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK     (0xFFFFFFFFU)
+#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT    (0U)
+/*! CAPTURE_VALUE - EVTimer Capture Value */
+#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x)       (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK)
+/*! @} */
+
+/*! @name CAPTURE_H - Local Capture High for CPU */
+/*! @{ */
+
+#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK     (0x3FFU)
+#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT    (0U)
+/*! CAPTURE_VALUE - EVTimer Capture Value */
+#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x)       (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK)
+/*! @} */
+
+/*! @name MATCH_L - Local Match Low for CPU */
+/*! @{ */
+
+#define OSTIMER_MATCH_L_MATCH_VALUE_MASK         (0xFFFFFFFFU)
+#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT        (0U)
+/*! MATCH_VALUE - EVTimer Match Value */
+#define OSTIMER_MATCH_L_MATCH_VALUE(x)           (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK)
+/*! @} */
+
+/*! @name MATCH_H - Local Match High for CPU */
+/*! @{ */
+
+#define OSTIMER_MATCH_H_MATCH_VALUE_MASK         (0x3FFU)
+#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT        (0U)
+/*! MATCH_VALUE - EVTimer Match Value */
+#define OSTIMER_MATCH_H_MATCH_VALUE(x)           (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK)
+/*! @} */
+
+/*! @name OSEVENT_CTRL - OSTIMER Control for CPU */
+/*! @{ */
+
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U)
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U)
+/*! OSTIMER_INTRFLAG - Interrupt Flag */
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK)
+
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U)
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U)
+/*! OSTIMER_INTENA - Interrupt or Wake-Up Request
+ *  0b0..Interrupts blocked
+ *  0b1..Interrupts enabled
+ */
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x)   (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK)
+
+#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK   (0x4U)
+#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT  (2U)
+/*! MATCH_WR_RDY - EVTimer Match Write Ready */
+#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x)     (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)
+
+#define OSTIMER_OSEVENT_CTRL_DEBUG_EN_MASK       (0x8U)
+#define OSTIMER_OSEVENT_CTRL_DEBUG_EN_SHIFT      (3U)
+/*! DEBUG_EN - Debug Enable
+ *  0b0..Disables
+ *  0b1..Enables
+ */
+#define OSTIMER_OSEVENT_CTRL_DEBUG_EN(x)         (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_DEBUG_EN_SHIFT)) & OSTIMER_OSEVENT_CTRL_DEBUG_EN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group OSTIMER_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group OSTIMER_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_OSTIMER_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_PORT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_PORT.h
new file mode 100644
index 0000000000..b35dc4e08d
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_PORT.h
@@ -0,0 +1,602 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for PORT
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_PORT.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for PORT
+ *
+ * CMSIS Peripheral Access Layer for PORT
+ */
+
+#if !defined(PERI_PORT_H_)
+#define PERI_PORT_H_                             /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Size of Registers Arrays */
+#define PORT_PCR_COUNT                            32u
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t GPCLR;                             /**< Global Pin Control Low, offset: 0x10 */
+  __IO uint32_t GPCHR;                             /**< Global Pin Control High, offset: 0x14 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t CONFIG;                            /**< Configuration, offset: 0x20 */
+       uint8_t RESERVED_2[60];
+  __IO uint32_t CALIB0;                            /**< Calibration 0, offset: 0x60, available only on: PORT0, PORT1, PORT3, PORT4 (missing on PORT2) */
+  __IO uint32_t CALIB1;                            /**< Calibration 1, offset: 0x64, available only on: PORT0, PORT1, PORT3, PORT4 (missing on PORT2) */
+       uint8_t RESERVED_3[24];
+  __IO uint32_t PCR[PORT_PCR_COUNT];               /**< Pin Control 0..Pin Control 31, array offset: 0x80, array step: 0x4, irregular array, not all indices are valid */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID */
+/*! @{ */
+
+#define PORT_VERID_FEATURE_MASK                  (0xFFFFU)
+#define PORT_VERID_FEATURE_SHIFT                 (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000000..Basic implementation
+ */
+#define PORT_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << PORT_VERID_FEATURE_SHIFT)) & PORT_VERID_FEATURE_MASK)
+
+#define PORT_VERID_MINOR_MASK                    (0xFF0000U)
+#define PORT_VERID_MINOR_SHIFT                   (16U)
+/*! MINOR - Minor Version Number */
+#define PORT_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MINOR_SHIFT)) & PORT_VERID_MINOR_MASK)
+
+#define PORT_VERID_MAJOR_MASK                    (0xFF000000U)
+#define PORT_VERID_MAJOR_SHIFT                   (24U)
+/*! MAJOR - Major Version Number */
+#define PORT_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MAJOR_SHIFT)) & PORT_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name GPCLR - Global Pin Control Low */
+/*! @{ */
+
+#define PORT_GPCLR_GPWD_MASK                     (0xFFFFU)
+#define PORT_GPCLR_GPWD_SHIFT                    (0U)
+/*! GPWD - Global Pin Write Data */
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+
+#define PORT_GPCLR_GPWE0_MASK                    (0x10000U)
+#define PORT_GPCLR_GPWE0_SHIFT                   (16U)
+/*! GPWE0 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCLR_GPWE0(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE0_SHIFT)) & PORT_GPCLR_GPWE0_MASK)
+
+#define PORT_GPCLR_GPWE1_MASK                    (0x20000U)
+#define PORT_GPCLR_GPWE1_SHIFT                   (17U)
+/*! GPWE1 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCLR_GPWE1(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE1_SHIFT)) & PORT_GPCLR_GPWE1_MASK)
+
+#define PORT_GPCLR_GPWE2_MASK                    (0x40000U)
+#define PORT_GPCLR_GPWE2_SHIFT                   (18U)
+/*! GPWE2 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCLR_GPWE2(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE2_SHIFT)) & PORT_GPCLR_GPWE2_MASK)
+
+#define PORT_GPCLR_GPWE3_MASK                    (0x80000U)
+#define PORT_GPCLR_GPWE3_SHIFT                   (19U)
+/*! GPWE3 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCLR_GPWE3(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE3_SHIFT)) & PORT_GPCLR_GPWE3_MASK)
+
+#define PORT_GPCLR_GPWE4_MASK                    (0x100000U)
+#define PORT_GPCLR_GPWE4_SHIFT                   (20U)
+/*! GPWE4 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCLR_GPWE4(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE4_SHIFT)) & PORT_GPCLR_GPWE4_MASK)
+
+#define PORT_GPCLR_GPWE5_MASK                    (0x200000U)
+#define PORT_GPCLR_GPWE5_SHIFT                   (21U)
+/*! GPWE5 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCLR_GPWE5(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE5_SHIFT)) & PORT_GPCLR_GPWE5_MASK)
+
+#define PORT_GPCLR_GPWE6_MASK                    (0x400000U)
+#define PORT_GPCLR_GPWE6_SHIFT                   (22U)
+/*! GPWE6 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCLR_GPWE6(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE6_SHIFT)) & PORT_GPCLR_GPWE6_MASK)
+
+#define PORT_GPCLR_GPWE7_MASK                    (0x800000U)
+#define PORT_GPCLR_GPWE7_SHIFT                   (23U)
+/*! GPWE7 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCLR_GPWE7(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE7_SHIFT)) & PORT_GPCLR_GPWE7_MASK)
+
+#define PORT_GPCLR_GPWE8_MASK                    (0x1000000U)
+#define PORT_GPCLR_GPWE8_SHIFT                   (24U)
+/*! GPWE8 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCLR_GPWE8(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE8_SHIFT)) & PORT_GPCLR_GPWE8_MASK)
+
+#define PORT_GPCLR_GPWE9_MASK                    (0x2000000U)
+#define PORT_GPCLR_GPWE9_SHIFT                   (25U)
+/*! GPWE9 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCLR_GPWE9(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
+
+#define PORT_GPCLR_GPWE10_MASK                   (0x4000000U)
+#define PORT_GPCLR_GPWE10_SHIFT                  (26U)
+/*! GPWE10 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCLR_GPWE10(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE10_SHIFT)) & PORT_GPCLR_GPWE10_MASK)
+
+#define PORT_GPCLR_GPWE11_MASK                   (0x8000000U)
+#define PORT_GPCLR_GPWE11_SHIFT                  (27U)
+/*! GPWE11 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCLR_GPWE11(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE11_SHIFT)) & PORT_GPCLR_GPWE11_MASK)
+
+#define PORT_GPCLR_GPWE12_MASK                   (0x10000000U)
+#define PORT_GPCLR_GPWE12_SHIFT                  (28U)
+/*! GPWE12 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCLR_GPWE12(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE12_SHIFT)) & PORT_GPCLR_GPWE12_MASK)
+
+#define PORT_GPCLR_GPWE13_MASK                   (0x20000000U)
+#define PORT_GPCLR_GPWE13_SHIFT                  (29U)
+/*! GPWE13 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCLR_GPWE13(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE13_SHIFT)) & PORT_GPCLR_GPWE13_MASK)
+
+#define PORT_GPCLR_GPWE14_MASK                   (0x40000000U)
+#define PORT_GPCLR_GPWE14_SHIFT                  (30U)
+/*! GPWE14 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCLR_GPWE14(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE14_SHIFT)) & PORT_GPCLR_GPWE14_MASK)
+
+#define PORT_GPCLR_GPWE15_MASK                   (0x80000000U)
+#define PORT_GPCLR_GPWE15_SHIFT                  (31U)
+/*! GPWE15 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCLR_GPWE15(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE15_SHIFT)) & PORT_GPCLR_GPWE15_MASK)
+/*! @} */
+
+/*! @name GPCHR - Global Pin Control High */
+/*! @{ */
+
+#define PORT_GPCHR_GPWD_MASK                     (0xFFFFU)
+#define PORT_GPCHR_GPWD_SHIFT                    (0U)
+/*! GPWD - Global Pin Write Data */
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+
+#define PORT_GPCHR_GPWE16_MASK                   (0x10000U)
+#define PORT_GPCHR_GPWE16_SHIFT                  (16U)
+/*! GPWE16 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCHR_GPWE16(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE16_SHIFT)) & PORT_GPCHR_GPWE16_MASK)
+
+#define PORT_GPCHR_GPWE17_MASK                   (0x20000U)
+#define PORT_GPCHR_GPWE17_SHIFT                  (17U)
+/*! GPWE17 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCHR_GPWE17(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE17_SHIFT)) & PORT_GPCHR_GPWE17_MASK)
+
+#define PORT_GPCHR_GPWE18_MASK                   (0x40000U)
+#define PORT_GPCHR_GPWE18_SHIFT                  (18U)
+/*! GPWE18 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCHR_GPWE18(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE18_SHIFT)) & PORT_GPCHR_GPWE18_MASK)
+
+#define PORT_GPCHR_GPWE19_MASK                   (0x80000U)
+#define PORT_GPCHR_GPWE19_SHIFT                  (19U)
+/*! GPWE19 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCHR_GPWE19(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE19_SHIFT)) & PORT_GPCHR_GPWE19_MASK)
+
+#define PORT_GPCHR_GPWE20_MASK                   (0x100000U)
+#define PORT_GPCHR_GPWE20_SHIFT                  (20U)
+/*! GPWE20 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCHR_GPWE20(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE20_SHIFT)) & PORT_GPCHR_GPWE20_MASK)
+
+#define PORT_GPCHR_GPWE21_MASK                   (0x200000U)
+#define PORT_GPCHR_GPWE21_SHIFT                  (21U)
+/*! GPWE21 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCHR_GPWE21(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE21_SHIFT)) & PORT_GPCHR_GPWE21_MASK)
+
+#define PORT_GPCHR_GPWE22_MASK                   (0x400000U)
+#define PORT_GPCHR_GPWE22_SHIFT                  (22U)
+/*! GPWE22 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCHR_GPWE22(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE22_SHIFT)) & PORT_GPCHR_GPWE22_MASK)
+
+#define PORT_GPCHR_GPWE23_MASK                   (0x800000U)
+#define PORT_GPCHR_GPWE23_SHIFT                  (23U)
+/*! GPWE23 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCHR_GPWE23(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE23_SHIFT)) & PORT_GPCHR_GPWE23_MASK)
+
+#define PORT_GPCHR_GPWE24_MASK                   (0x1000000U)
+#define PORT_GPCHR_GPWE24_SHIFT                  (24U)
+/*! GPWE24 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCHR_GPWE24(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE24_SHIFT)) & PORT_GPCHR_GPWE24_MASK)
+
+#define PORT_GPCHR_GPWE25_MASK                   (0x2000000U)
+#define PORT_GPCHR_GPWE25_SHIFT                  (25U)
+/*! GPWE25 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCHR_GPWE25(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE25_SHIFT)) & PORT_GPCHR_GPWE25_MASK)
+
+#define PORT_GPCHR_GPWE26_MASK                   (0x4000000U)
+#define PORT_GPCHR_GPWE26_SHIFT                  (26U)
+/*! GPWE26 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCHR_GPWE26(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE26_SHIFT)) & PORT_GPCHR_GPWE26_MASK)
+
+#define PORT_GPCHR_GPWE27_MASK                   (0x8000000U)
+#define PORT_GPCHR_GPWE27_SHIFT                  (27U)
+/*! GPWE27 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCHR_GPWE27(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE27_SHIFT)) & PORT_GPCHR_GPWE27_MASK)
+
+#define PORT_GPCHR_GPWE28_MASK                   (0x10000000U)
+#define PORT_GPCHR_GPWE28_SHIFT                  (28U)
+/*! GPWE28 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCHR_GPWE28(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE28_SHIFT)) & PORT_GPCHR_GPWE28_MASK)
+
+#define PORT_GPCHR_GPWE29_MASK                   (0x20000000U)
+#define PORT_GPCHR_GPWE29_SHIFT                  (29U)
+/*! GPWE29 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCHR_GPWE29(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE29_SHIFT)) & PORT_GPCHR_GPWE29_MASK)
+
+#define PORT_GPCHR_GPWE30_MASK                   (0x40000000U)
+#define PORT_GPCHR_GPWE30_SHIFT                  (30U)
+/*! GPWE30 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCHR_GPWE30(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE30_SHIFT)) & PORT_GPCHR_GPWE30_MASK)
+
+#define PORT_GPCHR_GPWE31_MASK                   (0x80000000U)
+#define PORT_GPCHR_GPWE31_SHIFT                  (31U)
+/*! GPWE31 - Global Pin Write Enable
+ *  0b0..Not updated
+ *  0b1..Updated
+ */
+#define PORT_GPCHR_GPWE31(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE31_SHIFT)) & PORT_GPCHR_GPWE31_MASK)
+/*! @} */
+
+/*! @name CONFIG - Configuration */
+/*! @{ */
+
+#define PORT_CONFIG_RANGE_MASK                   (0x1U)
+#define PORT_CONFIG_RANGE_SHIFT                  (0U)
+/*! RANGE - Port Voltage Range
+ *  0b0..1.71 V-3.6 V
+ *  0b1..2.70 V-3.6 V
+ */
+#define PORT_CONFIG_RANGE(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_CONFIG_RANGE_SHIFT)) & PORT_CONFIG_RANGE_MASK)
+/*! @} */
+
+/*! @name CALIB0 - Calibration 0 */
+/*! @{ */
+
+#define PORT_CALIB0_NCAL_MASK                    (0x3FU)
+#define PORT_CALIB0_NCAL_SHIFT                   (0U)
+/*! NCAL - Calibration of NMOS Output Driver */
+#define PORT_CALIB0_NCAL(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_NCAL_SHIFT)) & PORT_CALIB0_NCAL_MASK)
+
+#define PORT_CALIB0_PCAL_MASK                    (0x3F0000U)
+#define PORT_CALIB0_PCAL_SHIFT                   (16U)
+/*! PCAL - Calibration of PMOS Output Driver */
+#define PORT_CALIB0_PCAL(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_PCAL_SHIFT)) & PORT_CALIB0_PCAL_MASK)
+/*! @} */
+
+/*! @name CALIB1 - Calibration 1 */
+/*! @{ */
+
+#define PORT_CALIB1_NCAL_MASK                    (0x3FU)
+#define PORT_CALIB1_NCAL_SHIFT                   (0U)
+/*! NCAL - Calibration of NMOS Output Driver */
+#define PORT_CALIB1_NCAL(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_NCAL_SHIFT)) & PORT_CALIB1_NCAL_MASK)
+
+#define PORT_CALIB1_PCAL_MASK                    (0x3F0000U)
+#define PORT_CALIB1_PCAL_SHIFT                   (16U)
+/*! PCAL - Calibration of PMOS Output Driver */
+#define PORT_CALIB1_PCAL(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_PCAL_SHIFT)) & PORT_CALIB1_PCAL_MASK)
+/*! @} */
+
+/*! @name PCR - Pin Control 0..Pin Control 31 */
+/*! @{ */
+
+#define PORT_PCR_PS_MASK                         (0x1U)
+#define PORT_PCR_PS_SHIFT                        (0U)
+/*! PS - Pull Select
+ *  0b0..Enables internal pulldown resistor
+ *  0b1..Enables internal pullup resistor
+ */
+#define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
+
+#define PORT_PCR_PE_MASK                         (0x2U)
+#define PORT_PCR_PE_SHIFT                        (1U)
+/*! PE - Pull Enable
+ *  0b0..Disables
+ *  0b1..Enables
+ */
+#define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
+
+#define PORT_PCR_PV_MASK                         (0x4U)
+#define PORT_PCR_PV_SHIFT                        (2U)
+/*! PV - Pull Value
+ *  0b0..Low
+ *  0b1..High
+ */
+#define PORT_PCR_PV(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PV_SHIFT)) & PORT_PCR_PV_MASK)
+
+#define PORT_PCR_SRE_MASK                        (0x8U)
+#define PORT_PCR_SRE_SHIFT                       (3U)
+/*! SRE - Slew Rate Enable
+ *  0b0..Fast
+ *  0b1..Slow
+ */
+#define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
+
+#define PORT_PCR_PFE_MASK                        (0x10U)
+#define PORT_PCR_PFE_SHIFT                       (4U)
+/*! PFE - Passive Filter Enable
+ *  0b0..Disables
+ *  0b1..Enables
+ */
+#define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
+
+#define PORT_PCR_ODE_MASK                        (0x20U)
+#define PORT_PCR_ODE_SHIFT                       (5U)
+/*! ODE - Open Drain Enable
+ *  0b0..Disables
+ *  0b1..Enables
+ */
+#define PORT_PCR_ODE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
+
+#define PORT_PCR_DSE_MASK                        (0x40U)
+#define PORT_PCR_DSE_SHIFT                       (6U)
+/*! DSE - Drive Strength Enable
+ *  0b0..Low
+ *  0b1..High
+ */
+#define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
+
+#define PORT_PCR_DSE1_MASK                       (0x80U)
+#define PORT_PCR_DSE1_SHIFT                      (7U)
+/*! DSE1 - Drive Strength Enable
+ *  0b0..Normal
+ *  0b1..Double
+ */
+#define PORT_PCR_DSE1(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE1_SHIFT)) & PORT_PCR_DSE1_MASK)
+
+#define PORT_PCR_MUX_MASK                        (0xF00U)  /* Merged from fields with different position or width, of widths (2, 3, 4), largest definition used */
+#define PORT_PCR_MUX_SHIFT                       (8U)
+/*! MUX - Pin Multiplex Control
+ *  0b0000..Alternative 0 (GPIO)
+ *  0b0001..Alternative 1 (chip-specific)
+ *  0b0010..Alternative 2 (chip-specific)
+ *  0b0011..Alternative 3 (chip-specific)
+ *  0b0100..Alternative 4 (chip-specific)
+ *  0b0101..Alternative 5 (chip-specific)
+ *  0b0110..Alternative 6 (chip-specific)
+ *  0b0111..Alternative 7 (chip-specific)
+ *  0b1000..Alternative 8 (chip-specific)
+ *  0b1001..Alternative 9 (chip-specific)
+ *  0b1010..Alternative 10 (chip-specific)
+ *  0b1011..Alternative 11 (chip-specific)
+ *  0b1100..Alternative 12 (chip-specific)
+ *  0b1101..Alternative 13 (chip-specific)
+ */
+#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)  /* Merged from fields with different position or width, of widths (2, 3, 4), largest definition used */
+
+#define PORT_PCR_IBE_MASK                        (0x1000U)
+#define PORT_PCR_IBE_SHIFT                       (12U)
+/*! IBE - Input Buffer Enable
+ *  0b0..Disables
+ *  0b1..Enables
+ */
+#define PORT_PCR_IBE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IBE_SHIFT)) & PORT_PCR_IBE_MASK)
+
+#define PORT_PCR_INV_MASK                        (0x2000U)
+#define PORT_PCR_INV_SHIFT                       (13U)
+/*! INV - Invert Input
+ *  0b0..Does not invert
+ *  0b1..Inverts
+ */
+#define PORT_PCR_INV(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_INV_SHIFT)) & PORT_PCR_INV_MASK)
+
+#define PORT_PCR_LK_MASK                         (0x8000U)
+#define PORT_PCR_LK_SHIFT                        (15U)
+/*! LK - Lock Register
+ *  0b0..Does not lock
+ *  0b1..Locks
+ */
+#define PORT_PCR_LK(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_PORT_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_PWM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_PWM.h
new file mode 100644
index 0000000000..bab5053221
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_PWM.h
@@ -0,0 +1,1355 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for PWM
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_PWM.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for PWM
+ *
+ * CMSIS Peripheral Access Layer for PWM
+ */
+
+#if !defined(PERI_PWM_H_)
+#define PERI_PWM_H_                              /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- PWM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
+ * @{
+ */
+
+/** PWM - Size of Registers Arrays */
+#define PWM_SM_DISMAP_COUNT                       1u
+#define PWM_SM_COUNT                              4u
+
+/** PWM - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x60 */
+    __I  uint16_t CNT;                               /**< Counter Register, array offset: 0x0, array step: 0x60 */
+    __IO uint16_t INIT;                              /**< Initial Count Register, array offset: 0x2, array step: 0x60 */
+    __IO uint16_t CTRL2;                             /**< Control 2 Register, array offset: 0x4, array step: 0x60 */
+    __IO uint16_t CTRL;                              /**< Control Register, array offset: 0x6, array step: 0x60 */
+         uint8_t RESERVED_0[2];
+    __IO uint16_t VAL0;                              /**< Value Register 0, array offset: 0xA, array step: 0x60 */
+         uint8_t RESERVED_1[2];
+    __IO uint16_t VAL1;                              /**< Value Register 1, array offset: 0xE, array step: 0x60 */
+         uint8_t RESERVED_2[2];
+    __IO uint16_t VAL2;                              /**< Value Register 2, array offset: 0x12, array step: 0x60 */
+         uint8_t RESERVED_3[2];
+    __IO uint16_t VAL3;                              /**< Value Register 3, array offset: 0x16, array step: 0x60 */
+         uint8_t RESERVED_4[2];
+    __IO uint16_t VAL4;                              /**< Value Register 4, array offset: 0x1A, array step: 0x60 */
+         uint8_t RESERVED_5[2];
+    __IO uint16_t VAL5;                              /**< Value Register 5, array offset: 0x1E, array step: 0x60 */
+         uint8_t RESERVED_6[2];
+    __IO uint16_t OCTRL;                             /**< Output Control Register, array offset: 0x22, array step: 0x60 */
+    __IO uint16_t STS;                               /**< Status Register, array offset: 0x24, array step: 0x60 */
+    __IO uint16_t INTEN;                             /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */
+    __IO uint16_t DMAEN;                             /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */
+    __IO uint16_t TCTRL;                             /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */
+    __IO uint16_t DISMAP[PWM_SM_DISMAP_COUNT];       /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */
+         uint8_t RESERVED_7[2];
+    __IO uint16_t DTCNT0;                            /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */
+    __IO uint16_t DTCNT1;                            /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */
+         uint8_t RESERVED_8[8];
+    __IO uint16_t CAPTCTRLX;                         /**< Capture Control X Register, array offset: 0x3C, array step: 0x60, irregular array, not all indices are valid */
+    __IO uint16_t CAPTCOMPX;                         /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60, irregular array, not all indices are valid */
+    __I  uint16_t CVAL0;                             /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60, irregular array, not all indices are valid */
+    __I  uint16_t CVAL0CYC;                          /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60, irregular array, not all indices are valid */
+    __I  uint16_t CVAL1;                             /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60, irregular array, not all indices are valid */
+    __I  uint16_t CVAL1CYC;                          /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60, irregular array, not all indices are valid */
+         uint8_t RESERVED_9[16];
+    __IO uint16_t PHASEDLY;                          /**< Phase Delay Register, array offset: 0x58, array step: 0x60, valid indices: [1-3] */
+         uint8_t RESERVED_10[4];
+    __IO uint16_t CAPTFILTX;                         /**< Capture PWM_X Input Filter Register, array offset: 0x5E, array step: 0x60, irregular array, not all indices are valid */
+  } SM[PWM_SM_COUNT];
+  __IO uint16_t OUTEN;                             /**< Output Enable Register, offset: 0x180 */
+  __IO uint16_t MASK;                              /**< Mask Register, offset: 0x182 */
+  __IO uint16_t SWCOUT;                            /**< Software Controlled Output Register, offset: 0x184 */
+  __IO uint16_t DTSRCSEL;                          /**< PWM Source Select Register, offset: 0x186 */
+  __IO uint16_t MCTRL;                             /**< Master Control Register, offset: 0x188 */
+  __IO uint16_t MCTRL2;                            /**< Master Control 2 Register, offset: 0x18A */
+  __IO uint16_t FCTRL;                             /**< Fault Control Register, offset: 0x18C */
+  __IO uint16_t FSTS;                              /**< Fault Status Register, offset: 0x18E */
+  __IO uint16_t FFILT;                             /**< Fault Filter Register, offset: 0x190 */
+  __IO uint16_t FTST;                              /**< Fault Test Register, offset: 0x192 */
+  __IO uint16_t FCTRL2;                            /**< Fault Control 2 Register, offset: 0x194 */
+} PWM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PWM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PWM_Register_Masks PWM Register Masks
+ * @{
+ */
+
+/*! @name CNT - Counter Register */
+/*! @{ */
+
+#define PWM_CNT_CNT_MASK                         (0xFFFFU)
+#define PWM_CNT_CNT_SHIFT                        (0U)
+/*! CNT - Counter Register Bits */
+#define PWM_CNT_CNT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
+/*! @} */
+
+/* The count of PWM_CNT */
+#define PWM_CNT_COUNT                            (4U)
+
+/*! @name INIT - Initial Count Register */
+/*! @{ */
+
+#define PWM_INIT_INIT_MASK                       (0xFFFFU)
+#define PWM_INIT_INIT_SHIFT                      (0U)
+/*! INIT - Initial Count Register Bits */
+#define PWM_INIT_INIT(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
+/*! @} */
+
+/* The count of PWM_INIT */
+#define PWM_INIT_COUNT                           (4U)
+
+/*! @name CTRL2 - Control 2 Register */
+/*! @{ */
+
+#define PWM_CTRL2_CLK_SEL_MASK                   (0x3U)
+#define PWM_CTRL2_CLK_SEL_SHIFT                  (0U)
+/*! CLK_SEL - Clock Source Select
+ *  0b00..The IPBus clock is used as the clock for the local prescaler and counter.
+ *  0b01..EXT_CLK is used as the clock for the local prescaler and counter.
+ *  0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This
+ *        setting should not be used in submodule 0 as it forces the clock to logic 0.
+ *  0b11..Reserved
+ */
+#define PWM_CTRL2_CLK_SEL(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
+
+#define PWM_CTRL2_RELOAD_SEL_MASK                (0x4U)
+#define PWM_CTRL2_RELOAD_SEL_SHIFT               (2U)
+/*! RELOAD_SEL - Reload Source Select
+ *  0b0..The local RELOAD signal is used to reload registers.
+ *  0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used
+ *       in submodule 0 as it forces the RELOAD signal to logic 0.
+ */
+#define PWM_CTRL2_RELOAD_SEL(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
+
+#define PWM_CTRL2_FORCE_SEL_MASK                 (0x38U)
+#define PWM_CTRL2_FORCE_SEL_SHIFT                (3U)
+/*! FORCE_SEL - Force Select
+ *  0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
+ *  0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in
+ *         submodule 0 as it holds the FORCE OUTPUT signal to logic 0.
+ *  0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
+ *  0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should
+ *         not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0.
+ *  0b100..The local sync signal from this submodule is used to force updates.
+ *  0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in
+ *         submodule0 as it holds the FORCE OUTPUT signal to logic 0.
+ *  0b110..The external force signal, EXT_FORCE, from outside the eFlexPWM module causes updates.
+ *  0b111..The external sync signal, EXT_SYNC, from outside the eFlexPWM module causes updates.
+ */
+#define PWM_CTRL2_FORCE_SEL(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
+
+#define PWM_CTRL2_FORCE_MASK                     (0x40U)
+#define PWM_CTRL2_FORCE_SHIFT                    (6U)
+/*! FORCE - Force Initialization */
+#define PWM_CTRL2_FORCE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
+
+#define PWM_CTRL2_FRCEN_MASK                     (0x80U)
+#define PWM_CTRL2_FRCEN_SHIFT                    (7U)
+/*! FRCEN - Force Enable
+ *  0b0..Initialization from a FORCE_OUT is disabled.
+ *  0b1..Initialization from a FORCE_OUT is enabled.
+ */
+#define PWM_CTRL2_FRCEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
+
+#define PWM_CTRL2_INIT_SEL_MASK                  (0x300U)
+#define PWM_CTRL2_INIT_SEL_SHIFT                 (8U)
+/*! INIT_SEL - Initialization Control Select
+ *  0b00..Local sync (PWM_X) causes initialization.
+ *  0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as
+ *        it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload
+ *        occurs.
+ *  0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0.
+ *  0b11..EXT_SYNC causes initialization.
+ */
+#define PWM_CTRL2_INIT_SEL(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
+
+#define PWM_CTRL2_PWMX_INIT_MASK                 (0x400U)
+#define PWM_CTRL2_PWMX_INIT_SHIFT                (10U)
+/*! PWMX_INIT - PWM_X Initial Value */
+#define PWM_CTRL2_PWMX_INIT(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
+
+#define PWM_CTRL2_PWM45_INIT_MASK                (0x800U)
+#define PWM_CTRL2_PWM45_INIT_SHIFT               (11U)
+/*! PWM45_INIT - PWM45 Initial Value */
+#define PWM_CTRL2_PWM45_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
+
+#define PWM_CTRL2_PWM23_INIT_MASK                (0x1000U)
+#define PWM_CTRL2_PWM23_INIT_SHIFT               (12U)
+/*! PWM23_INIT - PWM23 Initial Value */
+#define PWM_CTRL2_PWM23_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
+
+#define PWM_CTRL2_INDEP_MASK                     (0x2000U)
+#define PWM_CTRL2_INDEP_SHIFT                    (13U)
+/*! INDEP - Independent or Complementary Pair Operation
+ *  0b0..PWM_A and PWM_B form a complementary PWM pair.
+ *  0b1..PWM_A and PWM_B outputs are independent PWMs.
+ */
+#define PWM_CTRL2_INDEP(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
+
+#define PWM_CTRL2_DBGEN_MASK                     (0x8000U)
+#define PWM_CTRL2_DBGEN_SHIFT                    (15U)
+/*! DBGEN - Debug Enable */
+#define PWM_CTRL2_DBGEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
+/*! @} */
+
+/* The count of PWM_CTRL2 */
+#define PWM_CTRL2_COUNT                          (4U)
+
+/*! @name CTRL - Control Register */
+/*! @{ */
+
+#define PWM_CTRL_DBLEN_MASK                      (0x1U)
+#define PWM_CTRL_DBLEN_SHIFT                     (0U)
+/*! DBLEN - Double Switching Enable
+ *  0b0..Double switching disabled.
+ *  0b1..Double switching enabled.
+ */
+#define PWM_CTRL_DBLEN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
+
+#define PWM_CTRL_DBLX_MASK                       (0x2U)
+#define PWM_CTRL_DBLX_SHIFT                      (1U)
+/*! DBLX - PWM_X Double Switching Enable
+ *  0b0..PWM_X double pulse disabled.
+ *  0b1..PWM_X double pulse enabled.
+ */
+#define PWM_CTRL_DBLX(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
+
+#define PWM_CTRL_LDMOD_MASK                      (0x4U)
+#define PWM_CTRL_LDMOD_SHIFT                     (2U)
+/*! LDMOD - Load Mode Select
+ *  0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.
+ *  0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set.
+ *       In this case, it is not necessary to set CTRL[FULL] or CTRL[HALF].
+ */
+#define PWM_CTRL_LDMOD(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
+
+#define PWM_CTRL_SPLIT_MASK                      (0x8U)
+#define PWM_CTRL_SPLIT_SHIFT                     (3U)
+/*! SPLIT - Split the DBLPWM signal to PWM_A and PWM_B
+ *  0b0..DBLPWM is not split. PWM_A and PWM_B each have double pulses.
+ *  0b1..DBLPWM is split to PWM_A and PWM_B.
+ */
+#define PWM_CTRL_SPLIT(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
+
+#define PWM_CTRL_PRSC_MASK                       (0x70U)
+#define PWM_CTRL_PRSC_SHIFT                      (4U)
+/*! PRSC - Prescaler
+ *  0b000..Prescaler 1
+ *  0b001..Prescaler 2
+ *  0b010..Prescaler 4
+ *  0b011..Prescaler 8
+ *  0b100..Prescaler 16
+ *  0b101..Prescaler 32
+ *  0b110..Prescaler 64
+ *  0b111..Prescaler 128
+ */
+#define PWM_CTRL_PRSC(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
+
+#define PWM_CTRL_COMPMODE_MASK                   (0x80U)
+#define PWM_CTRL_COMPMODE_SHIFT                  (7U)
+/*! COMPMODE - Compare Mode
+ *  0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges
+ *       are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A
+ *       output that is high at the end of a period maintains this state until a match with VAL3 clears the output
+ *       in the following period.
+ *  0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This
+ *       means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register
+ *       values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the
+ *       next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.
+ */
+#define PWM_CTRL_COMPMODE(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
+
+#define PWM_CTRL_DT_MASK                         (0x300U)
+#define PWM_CTRL_DT_SHIFT                        (8U)
+/*! DT - Deadtime */
+#define PWM_CTRL_DT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
+
+#define PWM_CTRL_FULL_MASK                       (0x400U)
+#define PWM_CTRL_FULL_SHIFT                      (10U)
+/*! FULL - Full Cycle Reload
+ *  0b0..Full-cycle reloads disabled.
+ *  0b1..Full-cycle reloads enabled.
+ */
+#define PWM_CTRL_FULL(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
+
+#define PWM_CTRL_HALF_MASK                       (0x800U)
+#define PWM_CTRL_HALF_SHIFT                      (11U)
+/*! HALF - Half Cycle Reload
+ *  0b0..Half-cycle reloads disabled.
+ *  0b1..Half-cycle reloads enabled.
+ */
+#define PWM_CTRL_HALF(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
+
+#define PWM_CTRL_LDFQ_MASK                       (0xF000U)
+#define PWM_CTRL_LDFQ_SHIFT                      (12U)
+/*! LDFQ - Load Frequency
+ *  0b0000..Every PWM opportunity
+ *  0b0001..Every 2 PWM opportunities
+ *  0b0010..Every 3 PWM opportunities
+ *  0b0011..Every 4 PWM opportunities
+ *  0b0100..Every 5 PWM opportunities
+ *  0b0101..Every 6 PWM opportunities
+ *  0b0110..Every 7 PWM opportunities
+ *  0b0111..Every 8 PWM opportunities
+ *  0b1000..Every 9 PWM opportunities
+ *  0b1001..Every 10 PWM opportunities
+ *  0b1010..Every 11 PWM opportunities
+ *  0b1011..Every 12 PWM opportunities
+ *  0b1100..Every 13 PWM opportunities
+ *  0b1101..Every 14 PWM opportunities
+ *  0b1110..Every 15 PWM opportunities
+ *  0b1111..Every 16 PWM opportunities
+ */
+#define PWM_CTRL_LDFQ(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
+/*! @} */
+
+/* The count of PWM_CTRL */
+#define PWM_CTRL_COUNT                           (4U)
+
+/*! @name VAL0 - Value Register 0 */
+/*! @{ */
+
+#define PWM_VAL0_VAL0_MASK                       (0xFFFFU)
+#define PWM_VAL0_VAL0_SHIFT                      (0U)
+/*! VAL0 - Value 0 */
+#define PWM_VAL0_VAL0(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
+/*! @} */
+
+/* The count of PWM_VAL0 */
+#define PWM_VAL0_COUNT                           (4U)
+
+/*! @name VAL1 - Value Register 1 */
+/*! @{ */
+
+#define PWM_VAL1_VAL1_MASK                       (0xFFFFU)
+#define PWM_VAL1_VAL1_SHIFT                      (0U)
+/*! VAL1 - Value 1 */
+#define PWM_VAL1_VAL1(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
+/*! @} */
+
+/* The count of PWM_VAL1 */
+#define PWM_VAL1_COUNT                           (4U)
+
+/*! @name VAL2 - Value Register 2 */
+/*! @{ */
+
+#define PWM_VAL2_VAL2_MASK                       (0xFFFFU)
+#define PWM_VAL2_VAL2_SHIFT                      (0U)
+/*! VAL2 - Value 2 */
+#define PWM_VAL2_VAL2(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
+/*! @} */
+
+/* The count of PWM_VAL2 */
+#define PWM_VAL2_COUNT                           (4U)
+
+/*! @name VAL3 - Value Register 3 */
+/*! @{ */
+
+#define PWM_VAL3_VAL3_MASK                       (0xFFFFU)
+#define PWM_VAL3_VAL3_SHIFT                      (0U)
+/*! VAL3 - Value 3 */
+#define PWM_VAL3_VAL3(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
+/*! @} */
+
+/* The count of PWM_VAL3 */
+#define PWM_VAL3_COUNT                           (4U)
+
+/*! @name VAL4 - Value Register 4 */
+/*! @{ */
+
+#define PWM_VAL4_VAL4_MASK                       (0xFFFFU)
+#define PWM_VAL4_VAL4_SHIFT                      (0U)
+/*! VAL4 - Value 4 */
+#define PWM_VAL4_VAL4(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
+/*! @} */
+
+/* The count of PWM_VAL4 */
+#define PWM_VAL4_COUNT                           (4U)
+
+/*! @name VAL5 - Value Register 5 */
+/*! @{ */
+
+#define PWM_VAL5_VAL5_MASK                       (0xFFFFU)
+#define PWM_VAL5_VAL5_SHIFT                      (0U)
+/*! VAL5 - Value 5 */
+#define PWM_VAL5_VAL5(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
+/*! @} */
+
+/* The count of PWM_VAL5 */
+#define PWM_VAL5_COUNT                           (4U)
+
+/*! @name OCTRL - Output Control Register */
+/*! @{ */
+
+#define PWM_OCTRL_PWMXFS_MASK                    (0x3U)
+#define PWM_OCTRL_PWMXFS_SHIFT                   (0U)
+/*! PWMXFS - PWM_X Fault State
+ *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
+ *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
+ *  0b10, 0b11..Output is put in a high-impedance state.
+ */
+#define PWM_OCTRL_PWMXFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
+
+#define PWM_OCTRL_PWMBFS_MASK                    (0xCU)
+#define PWM_OCTRL_PWMBFS_SHIFT                   (2U)
+/*! PWMBFS - PWM_B Fault State
+ *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
+ *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
+ *  0b10, 0b11..Output is put in a high-impedance state.
+ */
+#define PWM_OCTRL_PWMBFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
+
+#define PWM_OCTRL_PWMAFS_MASK                    (0x30U)
+#define PWM_OCTRL_PWMAFS_SHIFT                   (4U)
+/*! PWMAFS - PWM_A Fault State
+ *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
+ *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
+ *  0b10, 0b11..Output is put in a high-impedance state.
+ */
+#define PWM_OCTRL_PWMAFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
+
+#define PWM_OCTRL_POLX_MASK                      (0x100U)
+#define PWM_OCTRL_POLX_SHIFT                     (8U)
+/*! POLX - PWM_X Output Polarity
+ *  0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
+ *  0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
+ */
+#define PWM_OCTRL_POLX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
+
+#define PWM_OCTRL_POLB_MASK                      (0x200U)
+#define PWM_OCTRL_POLB_SHIFT                     (9U)
+/*! POLB - PWM_B Output Polarity
+ *  0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
+ *  0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
+ */
+#define PWM_OCTRL_POLB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
+
+#define PWM_OCTRL_POLA_MASK                      (0x400U)
+#define PWM_OCTRL_POLA_SHIFT                     (10U)
+/*! POLA - PWM_A Output Polarity
+ *  0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
+ *  0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
+ */
+#define PWM_OCTRL_POLA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
+
+#define PWM_OCTRL_PWMX_IN_MASK                   (0x2000U)
+#define PWM_OCTRL_PWMX_IN_SHIFT                  (13U)
+/*! PWMX_IN - PWM_X Input */
+#define PWM_OCTRL_PWMX_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
+
+#define PWM_OCTRL_PWMB_IN_MASK                   (0x4000U)
+#define PWM_OCTRL_PWMB_IN_SHIFT                  (14U)
+/*! PWMB_IN - PWM_B Input */
+#define PWM_OCTRL_PWMB_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
+
+#define PWM_OCTRL_PWMA_IN_MASK                   (0x8000U)
+#define PWM_OCTRL_PWMA_IN_SHIFT                  (15U)
+/*! PWMA_IN - PWM_A Input */
+#define PWM_OCTRL_PWMA_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
+/*! @} */
+
+/* The count of PWM_OCTRL */
+#define PWM_OCTRL_COUNT                          (4U)
+
+/*! @name STS - Status Register */
+/*! @{ */
+
+#define PWM_STS_CMPF_MASK                        (0x3FU)
+#define PWM_STS_CMPF_SHIFT                       (0U)
+/*! CMPF - Compare Flags
+ *  0b000000..No compare event has occurred for a particular VALx value.
+ *  0b000001..A compare event has occurred for a particular VALx value.
+ */
+#define PWM_STS_CMPF(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
+
+#define PWM_STS_CFX0_MASK                        (0x40U)
+#define PWM_STS_CFX0_SHIFT                       (6U)
+/*! CFX0 - Capture Flag X0 */
+#define PWM_STS_CFX0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
+
+#define PWM_STS_CFX1_MASK                        (0x80U)
+#define PWM_STS_CFX1_SHIFT                       (7U)
+/*! CFX1 - Capture Flag X1 */
+#define PWM_STS_CFX1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
+
+#define PWM_STS_RF_MASK                          (0x1000U)
+#define PWM_STS_RF_SHIFT                         (12U)
+/*! RF - Reload Flag
+ *  0b0..No new reload cycle since last STS[RF] clearing
+ *  0b1..New reload cycle since last STS[RF] clearing
+ */
+#define PWM_STS_RF(x)                            (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
+
+#define PWM_STS_REF_MASK                         (0x2000U)
+#define PWM_STS_REF_SHIFT                        (13U)
+/*! REF - Reload Error Flag
+ *  0b0..No reload error occurred.
+ *  0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
+ */
+#define PWM_STS_REF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
+
+#define PWM_STS_RUF_MASK                         (0x4000U)
+#define PWM_STS_RUF_SHIFT                        (14U)
+/*! RUF - Registers Updated Flag
+ *  0b0..No register update has occurred since last reload.
+ *  0b1..At least one of the double buffered registers has been updated since the last reload.
+ */
+#define PWM_STS_RUF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
+/*! @} */
+
+/* The count of PWM_STS */
+#define PWM_STS_COUNT                            (4U)
+
+/*! @name INTEN - Interrupt Enable Register */
+/*! @{ */
+
+#define PWM_INTEN_CMPIE_MASK                     (0x3FU)
+#define PWM_INTEN_CMPIE_SHIFT                    (0U)
+/*! CMPIE - Compare Interrupt Enables
+ *  0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request.
+ *  0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.
+ */
+#define PWM_INTEN_CMPIE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
+
+#define PWM_INTEN_CX0IE_MASK                     (0x40U)
+#define PWM_INTEN_CX0IE_SHIFT                    (6U)
+/*! CX0IE - Capture X 0 Interrupt Enable
+ *  0b0..Interrupt request disabled for STS[CFX0].
+ *  0b1..Interrupt request enabled for STS[CFX0].
+ */
+#define PWM_INTEN_CX0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
+
+#define PWM_INTEN_CX1IE_MASK                     (0x80U)
+#define PWM_INTEN_CX1IE_SHIFT                    (7U)
+/*! CX1IE - Capture X 1 Interrupt Enable
+ *  0b0..Interrupt request disabled for STS[CFX1].
+ *  0b1..Interrupt request enabled for STS[CFX1].
+ */
+#define PWM_INTEN_CX1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
+
+#define PWM_INTEN_RIE_MASK                       (0x1000U)
+#define PWM_INTEN_RIE_SHIFT                      (12U)
+/*! RIE - Reload Interrupt Enable
+ *  0b0..STS[RF] CPU interrupt requests disabled
+ *  0b1..STS[RF] CPU interrupt requests enabled
+ */
+#define PWM_INTEN_RIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
+
+#define PWM_INTEN_REIE_MASK                      (0x2000U)
+#define PWM_INTEN_REIE_SHIFT                     (13U)
+/*! REIE - Reload Error Interrupt Enable
+ *  0b0..STS[REF] CPU interrupt requests disabled
+ *  0b1..STS[REF] CPU interrupt requests enabled
+ */
+#define PWM_INTEN_REIE(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
+/*! @} */
+
+/* The count of PWM_INTEN */
+#define PWM_INTEN_COUNT                          (4U)
+
+/*! @name DMAEN - DMA Enable Register */
+/*! @{ */
+
+#define PWM_DMAEN_CX0DE_MASK                     (0x1U)
+#define PWM_DMAEN_CX0DE_SHIFT                    (0U)
+/*! CX0DE - Capture X0 FIFO DMA Enable */
+#define PWM_DMAEN_CX0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
+
+#define PWM_DMAEN_CX1DE_MASK                     (0x2U)
+#define PWM_DMAEN_CX1DE_SHIFT                    (1U)
+/*! CX1DE - Capture X1 FIFO DMA Enable */
+#define PWM_DMAEN_CX1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
+
+#define PWM_DMAEN_CAPTDE_MASK                    (0xC0U)
+#define PWM_DMAEN_CAPTDE_SHIFT                   (6U)
+/*! CAPTDE - Capture DMA Enable Source Select
+ *  0b00..Read DMA requests disabled.
+ *  0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CX1DE], or
+ *        DMAEN[CX0DE] to be set to determine which watermark(s) the DMA request is sensitive.
+ *  0b10..A local synchronization (VAL1 matches counter) sets the read DMA request.
+ *  0b11..A local reload (STS[RF] being set) sets the read DMA request.
+ */
+#define PWM_DMAEN_CAPTDE(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
+
+#define PWM_DMAEN_FAND_MASK                      (0x100U)
+#define PWM_DMAEN_FAND_SHIFT                     (8U)
+/*! FAND - FIFO Watermark AND Control
+ *  0b0..Selected FIFO watermarks are OR'ed together.
+ *  0b1..Selected FIFO watermarks are AND'ed together.
+ */
+#define PWM_DMAEN_FAND(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
+
+#define PWM_DMAEN_VALDE_MASK                     (0x200U)
+#define PWM_DMAEN_VALDE_SHIFT                    (9U)
+/*! VALDE - Value Registers DMA Enable
+ *  0b0..DMA write requests disabled
+ *  0b1..Enabled
+ */
+#define PWM_DMAEN_VALDE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
+/*! @} */
+
+/* The count of PWM_DMAEN */
+#define PWM_DMAEN_COUNT                          (4U)
+
+/*! @name TCTRL - Output Trigger Control Register */
+/*! @{ */
+
+#define PWM_TCTRL_OUT_TRIG_EN_MASK               (0x3FU)
+#define PWM_TCTRL_OUT_TRIG_EN_SHIFT              (0U)
+/*! OUT_TRIG_EN - Output Trigger Enables
+ *  0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value.
+ *  0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value.
+ *  0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value.
+ *  0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value.
+ *  0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value.
+ *  0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.
+ */
+#define PWM_TCTRL_OUT_TRIG_EN(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
+
+#define PWM_TCTRL_TRGFRQ_MASK                    (0x1000U)
+#define PWM_TCTRL_TRGFRQ_SHIFT                   (12U)
+/*! TRGFRQ - Trigger Frequency
+ *  0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
+ *  0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM
+ *       is not reloaded every period due to CTRL[LDFQ] being non-zero.
+ */
+#define PWM_TCTRL_TRGFRQ(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
+
+#define PWM_TCTRL_PWBOT1_MASK                    (0x4000U)
+#define PWM_TCTRL_PWBOT1_SHIFT                   (14U)
+/*! PWBOT1 - Mux Output Trigger 1 Source Select
+ *  0b0..Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port.
+ *  0b1..Route the PWM_B output to the PWM_MUX_TRIG1 port.
+ */
+#define PWM_TCTRL_PWBOT1(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
+
+#define PWM_TCTRL_PWAOT0_MASK                    (0x8000U)
+#define PWM_TCTRL_PWAOT0_SHIFT                   (15U)
+/*! PWAOT0 - Mux Output Trigger 0 Source Select
+ *  0b0..Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port.
+ *  0b1..Route the PWM_A output to the PWM_MUX_TRIG0 port.
+ */
+#define PWM_TCTRL_PWAOT0(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
+/*! @} */
+
+/* The count of PWM_TCTRL */
+#define PWM_TCTRL_COUNT                          (4U)
+
+/*! @name DISMAP - Fault Disable Mapping Register 0 */
+/*! @{ */
+
+#define PWM_DISMAP_DIS0A_MASK                    (0xFU)
+#define PWM_DISMAP_DIS0A_SHIFT                   (0U)
+/*! DIS0A - PWM_A Fault Disable Mask 0 */
+#define PWM_DISMAP_DIS0A(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
+
+#define PWM_DISMAP_DIS0B_MASK                    (0xF0U)
+#define PWM_DISMAP_DIS0B_SHIFT                   (4U)
+/*! DIS0B - PWM_B Fault Disable Mask 0 */
+#define PWM_DISMAP_DIS0B(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
+
+#define PWM_DISMAP_DIS0X_MASK                    (0xF00U)
+#define PWM_DISMAP_DIS0X_SHIFT                   (8U)
+/*! DIS0X - PWM_X Fault Disable Mask 0 */
+#define PWM_DISMAP_DIS0X(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
+/*! @} */
+
+/* The count of PWM_DISMAP */
+#define PWM_DISMAP_COUNT                         (4U)
+
+/* The count of PWM_DISMAP */
+#define PWM_DISMAP_COUNT2                        (1U)
+
+/*! @name DTCNT0 - Deadtime Count Register 0 */
+/*! @{ */
+
+#define PWM_DTCNT0_DTCNT0_MASK                   (0x7FFU)
+#define PWM_DTCNT0_DTCNT0_SHIFT                  (0U)
+/*! DTCNT0 - Deadtime Count Register 0 */
+#define PWM_DTCNT0_DTCNT0(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
+/*! @} */
+
+/* The count of PWM_DTCNT0 */
+#define PWM_DTCNT0_COUNT                         (4U)
+
+/*! @name DTCNT1 - Deadtime Count Register 1 */
+/*! @{ */
+
+#define PWM_DTCNT1_DTCNT1_MASK                   (0x7FFU)
+#define PWM_DTCNT1_DTCNT1_SHIFT                  (0U)
+/*! DTCNT1 - Deadtime Count Register 1 */
+#define PWM_DTCNT1_DTCNT1(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
+/*! @} */
+
+/* The count of PWM_DTCNT1 */
+#define PWM_DTCNT1_COUNT                         (4U)
+
+/*! @name CAPTCTRLX - Capture Control X Register */
+/*! @{ */
+
+#define PWM_CAPTCTRLX_ARMX_MASK                  (0x1U)
+#define PWM_CAPTCTRLX_ARMX_SHIFT                 (0U)
+/*! ARMX - Arm X
+ *  0b0..Input capture operation is disabled.
+ *  0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
+ */
+#define PWM_CAPTCTRLX_ARMX(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
+
+#define PWM_CAPTCTRLX_ONESHOTX_MASK              (0x2U)
+#define PWM_CAPTCTRLX_ONESHOTX_SHIFT             (1U)
+/*! ONESHOTX - One Shot Mode Aux
+ *  0b0..Free Running
+ *  0b1..One Shot
+ */
+#define PWM_CAPTCTRLX_ONESHOTX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
+
+#define PWM_CAPTCTRLX_EDGX0_MASK                 (0xCU)
+#define PWM_CAPTCTRLX_EDGX0_SHIFT                (2U)
+/*! EDGX0 - Edge X 0
+ *  0b00..Disabled
+ *  0b01..Capture falling edges
+ *  0b10..Capture rising edges
+ *  0b11..Capture any edge
+ */
+#define PWM_CAPTCTRLX_EDGX0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
+
+#define PWM_CAPTCTRLX_EDGX1_MASK                 (0x30U)
+#define PWM_CAPTCTRLX_EDGX1_SHIFT                (4U)
+/*! EDGX1 - Edge X 1
+ *  0b00..Disabled
+ *  0b01..Capture falling edges
+ *  0b10..Capture rising edges
+ *  0b11..Capture any edge
+ */
+#define PWM_CAPTCTRLX_EDGX1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
+
+#define PWM_CAPTCTRLX_INP_SELX_MASK              (0x40U)
+#define PWM_CAPTCTRLX_INP_SELX_SHIFT             (6U)
+/*! INP_SELX - Input Select X
+ *  0b0..Raw PWM_X input signal selected as source.
+ *  0b1..Edge Counter
+ */
+#define PWM_CAPTCTRLX_INP_SELX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
+
+#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK            (0x80U)
+#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT           (7U)
+/*! EDGCNTX_EN - Edge Counter X Enable
+ *  0b0..Edge counter disabled and held in reset
+ *  0b1..Edge counter enabled
+ */
+#define PWM_CAPTCTRLX_EDGCNTX_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
+
+#define PWM_CAPTCTRLX_CFXWM_MASK                 (0x300U)
+#define PWM_CAPTCTRLX_CFXWM_SHIFT                (8U)
+/*! CFXWM - Capture X FIFOs Water Mark */
+#define PWM_CAPTCTRLX_CFXWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
+
+#define PWM_CAPTCTRLX_CX0CNT_MASK                (0x1C00U)
+#define PWM_CAPTCTRLX_CX0CNT_SHIFT               (10U)
+/*! CX0CNT - Capture X0 FIFO Word Count */
+#define PWM_CAPTCTRLX_CX0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
+
+#define PWM_CAPTCTRLX_CX1CNT_MASK                (0xE000U)
+#define PWM_CAPTCTRLX_CX1CNT_SHIFT               (13U)
+/*! CX1CNT - Capture X1 FIFO Word Count */
+#define PWM_CAPTCTRLX_CX1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
+/*! @} */
+
+/* The count of PWM_CAPTCTRLX */
+#define PWM_CAPTCTRLX_COUNT                      (4U)
+
+/*! @name CAPTCOMPX - Capture Compare X Register */
+/*! @{ */
+
+#define PWM_CAPTCOMPX_EDGCMPX_MASK               (0xFFU)
+#define PWM_CAPTCOMPX_EDGCMPX_SHIFT              (0U)
+/*! EDGCMPX - Edge Compare X */
+#define PWM_CAPTCOMPX_EDGCMPX(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
+
+#define PWM_CAPTCOMPX_EDGCNTX_MASK               (0xFF00U)
+#define PWM_CAPTCOMPX_EDGCNTX_SHIFT              (8U)
+/*! EDGCNTX - Edge Counter X */
+#define PWM_CAPTCOMPX_EDGCNTX(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
+/*! @} */
+
+/* The count of PWM_CAPTCOMPX */
+#define PWM_CAPTCOMPX_COUNT                      (4U)
+
+/*! @name CVAL0 - Capture Value 0 Register */
+/*! @{ */
+
+#define PWM_CVAL0_CAPTVAL0_MASK                  (0xFFFFU)
+#define PWM_CVAL0_CAPTVAL0_SHIFT                 (0U)
+/*! CAPTVAL0 - Capture Value 0 */
+#define PWM_CVAL0_CAPTVAL0(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
+/*! @} */
+
+/* The count of PWM_CVAL0 */
+#define PWM_CVAL0_COUNT                          (4U)
+
+/*! @name CVAL0CYC - Capture Value 0 Cycle Register */
+/*! @{ */
+
+#define PWM_CVAL0CYC_CVAL0CYC_MASK               (0xFU)
+#define PWM_CVAL0CYC_CVAL0CYC_SHIFT              (0U)
+/*! CVAL0CYC - Capture Value 0 Cycle */
+#define PWM_CVAL0CYC_CVAL0CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
+/*! @} */
+
+/* The count of PWM_CVAL0CYC */
+#define PWM_CVAL0CYC_COUNT                       (4U)
+
+/*! @name CVAL1 - Capture Value 1 Register */
+/*! @{ */
+
+#define PWM_CVAL1_CAPTVAL1_MASK                  (0xFFFFU)
+#define PWM_CVAL1_CAPTVAL1_SHIFT                 (0U)
+/*! CAPTVAL1 - Capture Value 1 */
+#define PWM_CVAL1_CAPTVAL1(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
+/*! @} */
+
+/* The count of PWM_CVAL1 */
+#define PWM_CVAL1_COUNT                          (4U)
+
+/*! @name CVAL1CYC - Capture Value 1 Cycle Register */
+/*! @{ */
+
+#define PWM_CVAL1CYC_CVAL1CYC_MASK               (0xFU)
+#define PWM_CVAL1CYC_CVAL1CYC_SHIFT              (0U)
+/*! CVAL1CYC - Capture Value 1 Cycle */
+#define PWM_CVAL1CYC_CVAL1CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
+/*! @} */
+
+/* The count of PWM_CVAL1CYC */
+#define PWM_CVAL1CYC_COUNT                       (4U)
+
+/*! @name PHASEDLY - Phase Delay Register */
+/*! @{ */
+
+#define PWM_PHASEDLY_PHASEDLY_MASK               (0xFFFFU)
+#define PWM_PHASEDLY_PHASEDLY_SHIFT              (0U)
+/*! PHASEDLY - Initial Count Register Bits */
+#define PWM_PHASEDLY_PHASEDLY(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_PHASEDLY_PHASEDLY_SHIFT)) & PWM_PHASEDLY_PHASEDLY_MASK)
+/*! @} */
+
+/* The count of PWM_PHASEDLY */
+#define PWM_PHASEDLY_COUNT                       (4U)
+
+/*! @name CAPTFILTX - Capture PWM_X Input Filter Register */
+/*! @{ */
+
+#define PWM_CAPTFILTX_CAPTX_FILT_PER_MASK        (0xFFU)
+#define PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT       (0U)
+/*! CAPTX_FILT_PER - Input Capture Filter Period */
+#define PWM_CAPTFILTX_CAPTX_FILT_PER(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_PER_MASK)
+
+#define PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK        (0x700U)
+#define PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT       (8U)
+/*! CAPTX_FILT_CNT - Input Capture Filter Count */
+#define PWM_CAPTFILTX_CAPTX_FILT_CNT(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK)
+/*! @} */
+
+/* The count of PWM_CAPTFILTX */
+#define PWM_CAPTFILTX_COUNT                      (4U)
+
+/*! @name OUTEN - Output Enable Register */
+/*! @{ */
+
+#define PWM_OUTEN_PWMX_EN_MASK                   (0xFU)
+#define PWM_OUTEN_PWMX_EN_SHIFT                  (0U)
+/*! PWMX_EN - PWM_X Output Enables */
+#define PWM_OUTEN_PWMX_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
+
+#define PWM_OUTEN_PWMB_EN_MASK                   (0xF0U)
+#define PWM_OUTEN_PWMB_EN_SHIFT                  (4U)
+/*! PWMB_EN - PWM_B Output Enables */
+#define PWM_OUTEN_PWMB_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
+
+#define PWM_OUTEN_PWMA_EN_MASK                   (0xF00U)
+#define PWM_OUTEN_PWMA_EN_SHIFT                  (8U)
+/*! PWMA_EN - PWM_A Output Enables */
+#define PWM_OUTEN_PWMA_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
+/*! @} */
+
+/*! @name MASK - Mask Register */
+/*! @{ */
+
+#define PWM_MASK_MASKX_MASK                      (0xFU)
+#define PWM_MASK_MASKX_SHIFT                     (0U)
+/*! MASKX - PWM_X Masks */
+#define PWM_MASK_MASKX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
+
+#define PWM_MASK_MASKB_MASK                      (0xF0U)
+#define PWM_MASK_MASKB_SHIFT                     (4U)
+/*! MASKB - PWM_B Masks */
+#define PWM_MASK_MASKB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
+
+#define PWM_MASK_MASKA_MASK                      (0xF00U)
+#define PWM_MASK_MASKA_SHIFT                     (8U)
+/*! MASKA - PWM_A Masks */
+#define PWM_MASK_MASKA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
+
+#define PWM_MASK_UPDATE_MASK_MASK                (0xF000U)
+#define PWM_MASK_UPDATE_MASK_SHIFT               (12U)
+/*! UPDATE_MASK - Update Mask Bits Immediately */
+#define PWM_MASK_UPDATE_MASK(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)
+/*! @} */
+
+/*! @name SWCOUT - Software Controlled Output Register */
+/*! @{ */
+
+#define PWM_SWCOUT_SM0OUT45_MASK                 (0x1U)
+#define PWM_SWCOUT_SM0OUT45_SHIFT                (0U)
+/*! SM0OUT45 - Submodule 0 Software Controlled Output 45
+ *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.
+ *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.
+ */
+#define PWM_SWCOUT_SM0OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
+
+#define PWM_SWCOUT_SM0OUT23_MASK                 (0x2U)
+#define PWM_SWCOUT_SM0OUT23_SHIFT                (1U)
+/*! SM0OUT23 - Submodule 0 Software Controlled Output 23
+ *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.
+ *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.
+ */
+#define PWM_SWCOUT_SM0OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
+
+#define PWM_SWCOUT_SM1OUT45_MASK                 (0x4U)
+#define PWM_SWCOUT_SM1OUT45_SHIFT                (2U)
+/*! SM1OUT45 - Submodule 1 Software Controlled Output 45
+ *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.
+ *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.
+ */
+#define PWM_SWCOUT_SM1OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
+
+#define PWM_SWCOUT_SM1OUT23_MASK                 (0x8U)
+#define PWM_SWCOUT_SM1OUT23_SHIFT                (3U)
+/*! SM1OUT23 - Submodule 1 Software Controlled Output 23
+ *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.
+ *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.
+ */
+#define PWM_SWCOUT_SM1OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
+
+#define PWM_SWCOUT_SM2OUT45_MASK                 (0x10U)
+#define PWM_SWCOUT_SM2OUT45_SHIFT                (4U)
+/*! SM2OUT45 - Submodule 2 Software Controlled Output 45
+ *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.
+ *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.
+ */
+#define PWM_SWCOUT_SM2OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
+
+#define PWM_SWCOUT_SM2OUT23_MASK                 (0x20U)
+#define PWM_SWCOUT_SM2OUT23_SHIFT                (5U)
+/*! SM2OUT23 - Submodule 2 Software Controlled Output 23
+ *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.
+ *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.
+ */
+#define PWM_SWCOUT_SM2OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
+
+#define PWM_SWCOUT_SM3OUT45_MASK                 (0x40U)
+#define PWM_SWCOUT_SM3OUT45_SHIFT                (6U)
+/*! SM3OUT45 - Submodule 3 Software Controlled Output 45
+ *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45.
+ *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45.
+ */
+#define PWM_SWCOUT_SM3OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
+
+#define PWM_SWCOUT_SM3OUT23_MASK                 (0x80U)
+#define PWM_SWCOUT_SM3OUT23_SHIFT                (7U)
+/*! SM3OUT23 - Submodule 3 Software Controlled Output 23
+ *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23.
+ *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23.
+ */
+#define PWM_SWCOUT_SM3OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
+/*! @} */
+
+/*! @name DTSRCSEL - PWM Source Select Register */
+/*! @{ */
+
+#define PWM_DTSRCSEL_SM0SEL45_MASK               (0x3U)
+#define PWM_DTSRCSEL_SM0SEL45_SHIFT              (0U)
+/*! SM0SEL45 - Submodule 0 PWM45 Control Select
+ *  0b00..Generated SM0PWM45 signal used by the deadtime logic.
+ *  0b01..Inverted generated SM0PWM45 signal used by the deadtime logic.
+ *  0b10..SWCOUT[SM0OUT45] used by the deadtime logic.
+ *  0b11..Reserved
+ */
+#define PWM_DTSRCSEL_SM0SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
+
+#define PWM_DTSRCSEL_SM0SEL23_MASK               (0xCU)
+#define PWM_DTSRCSEL_SM0SEL23_SHIFT              (2U)
+/*! SM0SEL23 - Submodule 0 PWM23 Control Select
+ *  0b00..Generated SM0PWM23 signal used by the deadtime logic.
+ *  0b01..Inverted generated SM0PWM23 signal used by the deadtime logic.
+ *  0b10..SWCOUT[SM0OUT23] used by the deadtime logic.
+ *  0b11..PWM0_EXTA signal used by the deadtime logic.
+ */
+#define PWM_DTSRCSEL_SM0SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
+
+#define PWM_DTSRCSEL_SM1SEL45_MASK               (0x30U)
+#define PWM_DTSRCSEL_SM1SEL45_SHIFT              (4U)
+/*! SM1SEL45 - Submodule 1 PWM45 Control Select
+ *  0b00..Generated SM1PWM45 signal used by the deadtime logic.
+ *  0b01..Inverted generated SM1PWM45 signal used by the deadtime logic.
+ *  0b10..SWCOUT[SM1OUT45] used by the deadtime logic.
+ *  0b11..Reserved
+ */
+#define PWM_DTSRCSEL_SM1SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
+
+#define PWM_DTSRCSEL_SM1SEL23_MASK               (0xC0U)
+#define PWM_DTSRCSEL_SM1SEL23_SHIFT              (6U)
+/*! SM1SEL23 - Submodule 1 PWM23 Control Select
+ *  0b00..Generated SM1PWM23 signal used by the deadtime logic.
+ *  0b01..Inverted generated SM1PWM23 signal used by the deadtime logic.
+ *  0b10..SWCOUT[SM1OUT23] used by the deadtime logic.
+ *  0b11..PWM1_EXTA signal used by the deadtime logic.
+ */
+#define PWM_DTSRCSEL_SM1SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
+
+#define PWM_DTSRCSEL_SM2SEL45_MASK               (0x300U)
+#define PWM_DTSRCSEL_SM2SEL45_SHIFT              (8U)
+/*! SM2SEL45 - Submodule 2 PWM45 Control Select
+ *  0b00..Generated SM2PWM45 signal used by the deadtime logic.
+ *  0b01..Inverted generated SM2PWM45 signal used by the deadtime logic.
+ *  0b10..SWCOUT[SM2OUT45] used by the deadtime logic.
+ *  0b11..Reserved
+ */
+#define PWM_DTSRCSEL_SM2SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
+
+#define PWM_DTSRCSEL_SM2SEL23_MASK               (0xC00U)
+#define PWM_DTSRCSEL_SM2SEL23_SHIFT              (10U)
+/*! SM2SEL23 - Submodule 2 PWM23 Control Select
+ *  0b00..Generated SM2PWM23 signal used by the deadtime logic.
+ *  0b01..Inverted generated SM2PWM23 signal used by the deadtime logic.
+ *  0b10..SWCOUT[SM2OUT23] used by the deadtime logic.
+ *  0b11..PWM2_EXTA signal used by the deadtime logic.
+ */
+#define PWM_DTSRCSEL_SM2SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
+
+#define PWM_DTSRCSEL_SM3SEL45_MASK               (0x3000U)
+#define PWM_DTSRCSEL_SM3SEL45_SHIFT              (12U)
+/*! SM3SEL45 - Submodule 3 PWM45 Control Select
+ *  0b00..Generated SM3PWM45 signal used by the deadtime logic.
+ *  0b01..Inverted generated SM3PWM45 signal used by the deadtime logic.
+ *  0b10..SWCOUT[SM3OUT45] used by the deadtime logic.
+ *  0b11..Reserved
+ */
+#define PWM_DTSRCSEL_SM3SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
+
+#define PWM_DTSRCSEL_SM3SEL23_MASK               (0xC000U)
+#define PWM_DTSRCSEL_SM3SEL23_SHIFT              (14U)
+/*! SM3SEL23 - Submodule 3 PWM23 Control Select
+ *  0b00..Generated SM3PWM23 signal used by the deadtime logic.
+ *  0b01..Inverted generated SM3PWM23 signal used by the deadtime logic.
+ *  0b10..SWCOUT[SM3OUT23] used by the deadtime logic.
+ *  0b11..PWM3_EXTA signal used by the deadtime logic.
+ */
+#define PWM_DTSRCSEL_SM3SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
+/*! @} */
+
+/*! @name MCTRL - Master Control Register */
+/*! @{ */
+
+#define PWM_MCTRL_LDOK_MASK                      (0xFU)
+#define PWM_MCTRL_LDOK_SHIFT                     (0U)
+/*! LDOK - Load Okay
+ *  0b0000..Do not load new values.
+ *  0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule.
+ */
+#define PWM_MCTRL_LDOK(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
+
+#define PWM_MCTRL_CLDOK_MASK                     (0xF0U)
+#define PWM_MCTRL_CLDOK_SHIFT                    (4U)
+/*! CLDOK - Clear Load Okay */
+#define PWM_MCTRL_CLDOK(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
+
+#define PWM_MCTRL_RUN_MASK                       (0xF00U)
+#define PWM_MCTRL_RUN_SHIFT                      (8U)
+/*! RUN - Run
+ *  0b0000..PWM counter is stopped, but PWM outputs hold the current state.
+ *  0b0001..PWM counter is started in the corresponding submodule.
+ */
+#define PWM_MCTRL_RUN(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
+
+#define PWM_MCTRL_IPOL_MASK                      (0xF000U)
+#define PWM_MCTRL_IPOL_SHIFT                     (12U)
+/*! IPOL - Current Polarity
+ *  0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule.
+ *  0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule.
+ */
+#define PWM_MCTRL_IPOL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
+/*! @} */
+
+/*! @name MCTRL2 - Master Control 2 Register */
+/*! @{ */
+
+#define PWM_MCTRL2_WRPROT_MASK                   (0xCU)
+#define PWM_MCTRL2_WRPROT_SHIFT                  (2U)
+/*! WRPROT - Write protect
+ *  0b00..Write protection off (default).
+ *  0b01..Write protection on.
+ *  0b10..Write protection off and locked until chip reset.
+ *  0b11..Write protection on and locked until chip reset.
+ */
+#define PWM_MCTRL2_WRPROT(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_WRPROT_SHIFT)) & PWM_MCTRL2_WRPROT_MASK)
+
+#define PWM_MCTRL2_STRETCH_CNT_PRSC_MASK         (0xC0U)
+#define PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT        (6U)
+/*! STRETCH_CNT_PRSC - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig
+ *  0b00..Stretch count is zero, no stretch.
+ *  0b01..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period.
+ *  0b10..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period.
+ *  0b11..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period.
+ */
+#define PWM_MCTRL2_STRETCH_CNT_PRSC(x)           (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT)) & PWM_MCTRL2_STRETCH_CNT_PRSC_MASK)
+/*! @} */
+
+/*! @name FCTRL - Fault Control Register */
+/*! @{ */
+
+#define PWM_FCTRL_FIE_MASK                       (0xFU)
+#define PWM_FCTRL_FIE_SHIFT                      (0U)
+/*! FIE - Fault Interrupt Enables
+ *  0b0000..FAULTx CPU interrupt requests disabled.
+ *  0b0001..FAULTx CPU interrupt requests enabled.
+ */
+#define PWM_FCTRL_FIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
+
+#define PWM_FCTRL_FSAFE_MASK                     (0xF0U)
+#define PWM_FCTRL_FSAFE_SHIFT                    (4U)
+/*! FSAFE - Fault Safety Mode
+ *  0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the
+ *          start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard
+ *          to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set, then the fault condition cannot be
+ *          cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input
+ *          signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in
+ *          DISMAPn).
+ *  0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and
+ *          FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and
+ *          FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared.
+ */
+#define PWM_FCTRL_FSAFE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
+
+#define PWM_FCTRL_FAUTO_MASK                     (0xF00U)
+#define PWM_FCTRL_FAUTO_SHIFT                    (8U)
+/*! FAUTO - Automatic Fault Clearing
+ *  0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear
+ *          at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If
+ *          neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled
+ *          by FCTRL[FSAFE].
+ *  0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at
+ *          the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without
+ *          regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition
+ *          cannot be cleared.
+ */
+#define PWM_FCTRL_FAUTO(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
+
+#define PWM_FCTRL_FLVL_MASK                      (0xF000U)
+#define PWM_FCTRL_FLVL_SHIFT                     (12U)
+/*! FLVL - Fault Level
+ *  0b0000..A logic 0 on the fault input indicates a fault condition.
+ *  0b0001..A logic 1 on the fault input indicates a fault condition.
+ */
+#define PWM_FCTRL_FLVL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
+/*! @} */
+
+/*! @name FSTS - Fault Status Register */
+/*! @{ */
+
+#define PWM_FSTS_FFLAG_MASK                      (0xFU)
+#define PWM_FSTS_FFLAG_SHIFT                     (0U)
+/*! FFLAG - Fault Flags
+ *  0b0000..No fault on the FAULTx pin.
+ *  0b0001..Fault on the FAULTx pin.
+ */
+#define PWM_FSTS_FFLAG(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
+
+#define PWM_FSTS_FFULL_MASK                      (0xF0U)
+#define PWM_FSTS_FFULL_SHIFT                     (4U)
+/*! FFULL - Full Cycle
+ *  0b0000..PWM outputs are not re-enabled at the start of a full cycle
+ *  0b0001..PWM outputs are re-enabled at the start of a full cycle
+ */
+#define PWM_FSTS_FFULL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
+
+#define PWM_FSTS_FFPIN_MASK                      (0xF00U)
+#define PWM_FSTS_FFPIN_SHIFT                     (8U)
+/*! FFPIN - Filtered Fault Pins */
+#define PWM_FSTS_FFPIN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
+
+#define PWM_FSTS_FHALF_MASK                      (0xF000U)
+#define PWM_FSTS_FHALF_SHIFT                     (12U)
+/*! FHALF - Half Cycle Fault Recovery
+ *  0b0000..PWM outputs are not re-enabled at the start of a half cycle.
+ *  0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).
+ */
+#define PWM_FSTS_FHALF(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
+/*! @} */
+
+/*! @name FFILT - Fault Filter Register */
+/*! @{ */
+
+#define PWM_FFILT_FILT_PER_MASK                  (0xFFU)
+#define PWM_FFILT_FILT_PER_SHIFT                 (0U)
+/*! FILT_PER - Fault Filter Period */
+#define PWM_FFILT_FILT_PER(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
+
+#define PWM_FFILT_FILT_CNT_MASK                  (0x700U)
+#define PWM_FFILT_FILT_CNT_SHIFT                 (8U)
+/*! FILT_CNT - Fault Filter Count */
+#define PWM_FFILT_FILT_CNT(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
+
+#define PWM_FFILT_GSTR_MASK                      (0x8000U)
+#define PWM_FFILT_GSTR_SHIFT                     (15U)
+/*! GSTR - Fault Glitch Stretch Enable
+ *  0b0..Fault input glitch stretching is disabled.
+ *  0b1..Input fault signals are stretched to at least 2 IPBus clock cycles.
+ */
+#define PWM_FFILT_GSTR(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
+/*! @} */
+
+/*! @name FTST - Fault Test Register */
+/*! @{ */
+
+#define PWM_FTST_FTEST_MASK                      (0x1U)
+#define PWM_FTST_FTEST_SHIFT                     (0U)
+/*! FTEST - Fault Test
+ *  0b0..No fault
+ *  0b1..Cause a simulated fault
+ */
+#define PWM_FTST_FTEST(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
+/*! @} */
+
+/*! @name FCTRL2 - Fault Control 2 Register */
+/*! @{ */
+
+#define PWM_FCTRL2_NOCOMB_MASK                   (0xFU)
+#define PWM_FCTRL2_NOCOMB_SHIFT                  (0U)
+/*! NOCOMB - No Combinational Path From Fault Input To PWM Output
+ *  0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined
+ *          with the filtered and latched fault signals to disable the PWM outputs.
+ *  0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered
+ *          and latched fault signals are used to disable the PWM outputs.
+ */
+#define PWM_FCTRL2_NOCOMB(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PWM_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group PWM_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_PWM_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_RTC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_RTC.h
new file mode 100644
index 0000000000..862b515735
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_RTC.h
@@ -0,0 +1,358 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for RTC
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_RTC.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for RTC
+ *
+ * CMSIS Peripheral Access Layer for RTC
+ */
+
+#if !defined(PERI_RTC_H_)
+#define PERI_RTC_H_                              /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /**< RTC Time Seconds, offset: 0x0 */
+  __IO uint32_t TPR;                               /**< RTC Time Prescaler, offset: 0x4 */
+  __IO uint32_t TAR;                               /**< RTC Time Alarm, offset: 0x8 */
+  __IO uint32_t TCR;                               /**< RTC Time Compensation, offset: 0xC */
+  __IO uint32_t CR;                                /**< RTC Control, offset: 0x10 */
+  __IO uint32_t SR;                                /**< RTC Status, offset: 0x14 */
+  __IO uint32_t LR;                                /**< RTC Lock, offset: 0x18 */
+  __IO uint32_t IER;                               /**< RTC Interrupt Enable, offset: 0x1C */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name TSR - RTC Time Seconds */
+/*! @{ */
+
+#define RTC_TSR_TSR_MASK                         (0xFFFFFFFFU)
+#define RTC_TSR_TSR_SHIFT                        (0U)
+/*! TSR - Time Seconds Register */
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
+/*! @} */
+
+/*! @name TPR - RTC Time Prescaler */
+/*! @{ */
+
+#define RTC_TPR_TPR_MASK                         (0xFFFFU)
+#define RTC_TPR_TPR_SHIFT                        (0U)
+/*! TPR - Time Prescaler Register */
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+/*! @} */
+
+/*! @name TAR - RTC Time Alarm */
+/*! @{ */
+
+#define RTC_TAR_TAR_MASK                         (0xFFFFFFFFU)
+#define RTC_TAR_TAR_SHIFT                        (0U)
+/*! TAR - Time Alarm Register */
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
+/*! @} */
+
+/*! @name TCR - RTC Time Compensation */
+/*! @{ */
+
+#define RTC_TCR_TCR_MASK                         (0xFFU)
+#define RTC_TCR_TCR_SHIFT                        (0U)
+/*! TCR - Time Compensation Register
+ *  0b00000000..Time Prescaler Register overflows every 32768 clock cycles.
+ *  0b00000001..Time Prescaler Register overflows every 32767 clock cycles.
+ *  0b01111110..Time Prescaler Register overflows every 32642 clock cycles.
+ *  0b01111111..Time Prescaler Register overflows every 32641 clock cycles.
+ *  0b10000000..Time Prescaler Register overflows every 32896 clock cycles.
+ *  0b10000001..Time Prescaler Register overflows every 32895 clock cycles.
+ *  0b11111111..Time Prescaler Register overflows every 32769 clock cycles.
+ */
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+
+#define RTC_TCR_CIR_MASK                         (0xFF00U)
+#define RTC_TCR_CIR_SHIFT                        (8U)
+/*! CIR - Compensation Interval Register */
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+
+#define RTC_TCR_TCV_MASK                         (0xFF0000U)
+#define RTC_TCR_TCV_SHIFT                        (16U)
+/*! TCV - Time Compensation Value */
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+
+#define RTC_TCR_CIC_MASK                         (0xFF000000U)
+#define RTC_TCR_CIC_SHIFT                        (24U)
+/*! CIC - Compensation Interval Counter */
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+/*! @} */
+
+/*! @name CR - RTC Control */
+/*! @{ */
+
+#define RTC_CR_SWR_MASK                          (0x1U)
+#define RTC_CR_SWR_SHIFT                         (0U)
+/*! SWR - Software Reset
+ *  0b0..No effect.
+ *  0b1..Resets all RTC registers except for this bit . This bit is cleared by POR and by software explicitly clearing it.
+ */
+#define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
+
+#define RTC_CR_UM_MASK                           (0x8U)
+#define RTC_CR_UM_SHIFT                          (3U)
+/*! UM - Update Mode
+ *  0b0..Registers cannot be written when locked.
+ *  0b1..Registers can be written when locked under limited conditions.
+ */
+#define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
+
+#define RTC_CR_LPOS_MASK                         (0x80U)
+#define RTC_CR_LPOS_SHIFT                        (7U)
+/*! LPOS - LPO Select
+ *  0b0..RTC prescaler increments using 32.768 kHz clock.
+ *  0b1..RTC prescaler increments using 16.384 kHz LPO. Bit [0] of the prescaler is ignored.
+ */
+#define RTC_CR_LPOS(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_LPOS_SHIFT)) & RTC_CR_LPOS_MASK)
+/*! @} */
+
+/*! @name SR - RTC Status */
+/*! @{ */
+
+#define RTC_SR_TIF_MASK                          (0x1U)
+#define RTC_SR_TIF_SHIFT                         (0U)
+/*! TIF - Time Invalid Flag
+ *  0b0..Time is valid.
+ *  0b1..Time is invalid and time counter is read as zero.
+ */
+#define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
+
+#define RTC_SR_TOF_MASK                          (0x2U)
+#define RTC_SR_TOF_SHIFT                         (1U)
+/*! TOF - Time Overflow Flag
+ *  0b0..Time overflow has not occurred.
+ *  0b1..Time overflow has occurred and time counter reads as zero.
+ */
+#define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
+
+#define RTC_SR_TAF_MASK                          (0x4U)
+#define RTC_SR_TAF_SHIFT                         (2U)
+/*! TAF - Time Alarm Flag
+ *  0b0..Time alarm has not occurred.
+ *  0b1..Time alarm has occurred.
+ */
+#define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
+
+#define RTC_SR_TCE_MASK                          (0x10U)
+#define RTC_SR_TCE_SHIFT                         (4U)
+/*! TCE - Time Counter Enable
+ *  0b0..Disables.
+ *  0b1..Enables.
+ */
+#define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
+/*! @} */
+
+/*! @name LR - RTC Lock */
+/*! @{ */
+
+#define RTC_LR_TCL_MASK                          (0x8U)
+#define RTC_LR_TCL_SHIFT                         (3U)
+/*! TCL - Time Compensation Lock
+ *  0b0..Time Compensation Register is locked and writes are ignored.
+ *  0b1..Time Compensation Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
+
+#define RTC_LR_CRL_MASK                          (0x10U)
+#define RTC_LR_CRL_SHIFT                         (4U)
+/*! CRL - Control Register Lock
+ *  0b0..Control Register is locked and writes are ignored.
+ *  0b1..Control Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
+
+#define RTC_LR_SRL_MASK                          (0x20U)
+#define RTC_LR_SRL_SHIFT                         (5U)
+/*! SRL - Status Register Lock
+ *  0b0..Status Register is locked and writes are ignored.
+ *  0b1..Status Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
+
+#define RTC_LR_LRL_MASK                          (0x40U)
+#define RTC_LR_LRL_SHIFT                         (6U)
+/*! LRL - Lock Register Lock
+ *  0b0..Lock Register is locked and writes are ignored.
+ *  0b1..Lock Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
+/*! @} */
+
+/*! @name IER - RTC Interrupt Enable */
+/*! @{ */
+
+#define RTC_IER_TIIE_MASK                        (0x1U)
+#define RTC_IER_TIIE_SHIFT                       (0U)
+/*! TIIE - Time Invalid Interrupt Enable
+ *  0b0..No interrupt is generated.
+ *  0b1..An interrupt is generated.
+ */
+#define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
+
+#define RTC_IER_TOIE_MASK                        (0x2U)
+#define RTC_IER_TOIE_SHIFT                       (1U)
+/*! TOIE - Time Overflow Interrupt Enable
+ *  0b0..No interrupt is generated.
+ *  0b1..An interrupt is generated.
+ */
+#define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
+
+#define RTC_IER_TAIE_MASK                        (0x4U)
+#define RTC_IER_TAIE_SHIFT                       (2U)
+/*! TAIE - Time Alarm Interrupt Enable
+ *  0b0..No interrupt is generated.
+ *  0b1..An interrupt is generated.
+ */
+#define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
+
+#define RTC_IER_TSIE_MASK                        (0x10U)
+#define RTC_IER_TSIE_SHIFT                       (4U)
+/*! TSIE - Time Seconds Interrupt Enable
+ *  0b0..Disables
+ *  0b1..Enables
+ */
+#define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
+
+#define RTC_IER_TSIC_MASK                        (0x70000U)
+#define RTC_IER_TSIC_SHIFT                       (16U)
+/*! TSIC - Timer Seconds Interrupt Configuration
+ *  0b000..1 Hz.
+ *  0b001..2 Hz.
+ *  0b010..4 Hz.
+ *  0b011..8 Hz.
+ *  0b100..16 Hz.
+ *  0b101..32 Hz.
+ *  0b110..64 Hz.
+ *  0b111..128 Hz.
+ */
+#define RTC_IER_TSIC(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIC_SHIFT)) & RTC_IER_TSIC_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_RTC_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SCG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SCG.h
new file mode 100644
index 0000000000..fb005601fd
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SCG.h
@@ -0,0 +1,720 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for SCG
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_SCG.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for SCG
+ *
+ * CMSIS Peripheral Access Layer for SCG
+ */
+
+#if !defined(PERI_SCG_H_)
+#define PERI_SCG_H_                              /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- SCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer
+ * @{
+ */
+
+/** SCG - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
+  __IO uint32_t TRIM_LOCK;                         /**< Trim Lock, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __I  uint32_t CSR;                               /**< Clock Status, offset: 0x10 */
+  __IO uint32_t RCCR;                              /**< Run Clock Control, offset: 0x14 */
+       uint8_t RESERVED_1[232];
+  __IO uint32_t SOSCCSR;                           /**< SOSC Control Status, offset: 0x100 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t SOSCCFG;                           /**< SOSC Configuration, offset: 0x108 */
+       uint8_t RESERVED_3[244];
+  __IO uint32_t SIRCCSR;                           /**< SIRC Control Status, offset: 0x200 */
+       uint8_t RESERVED_4[8];
+  __IO uint32_t SIRCTCFG;                          /**< SIRC Trim Configuration, offset: 0x20C */
+  __IO uint32_t SIRCTRIM;                          /**< SIRC Trim, offset: 0x210 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t SIRCSTAT;                          /**< SIRC Auto-trimming Status, offset: 0x218 */
+       uint8_t RESERVED_6[228];
+  __IO uint32_t FIRCCSR;                           /**< FIRC Control Status, offset: 0x300 */
+       uint8_t RESERVED_7[4];
+  __IO uint32_t FIRCCFG;                           /**< FIRC Configuration, offset: 0x308 */
+       uint8_t RESERVED_8[4];
+  __IO uint32_t FIRCTRIM;                          /**< FIRC Trim, offset: 0x310 */
+       uint8_t RESERVED_9[236];
+  __IO uint32_t ROSCCSR;                           /**< ROSC Control Status, offset: 0x400 */
+       uint8_t RESERVED_10[1020];
+  __IO uint32_t LDOCSR;                            /**< LDO Control and Status, offset: 0x800 */
+} SCG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCG_Register_Masks SCG Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID */
+/*! @{ */
+
+#define SCG_VERID_VERSION_MASK                   (0xFFFFFFFFU)
+#define SCG_VERID_VERSION_SHIFT                  (0U)
+/*! VERSION - SCG Version Number */
+#define SCG_VERID_VERSION(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter */
+/*! @{ */
+
+#define SCG_PARAM_SOSCCLKPRES_MASK               (0x2U)
+#define SCG_PARAM_SOSCCLKPRES_SHIFT              (1U)
+/*! SOSCCLKPRES - SOSC Clock Present
+ *  0b0..SOSC clock source is not present
+ *  0b1..SOSC clock source is present
+ */
+#define SCG_PARAM_SOSCCLKPRES(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SOSCCLKPRES_SHIFT)) & SCG_PARAM_SOSCCLKPRES_MASK)
+
+#define SCG_PARAM_SIRCCLKPRES_MASK               (0x4U)
+#define SCG_PARAM_SIRCCLKPRES_SHIFT              (2U)
+/*! SIRCCLKPRES - SIRC Clock Present
+ *  0b0..SIRC clock source is not present
+ *  0b1..SIRC clock source is present
+ */
+#define SCG_PARAM_SIRCCLKPRES(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SIRCCLKPRES_SHIFT)) & SCG_PARAM_SIRCCLKPRES_MASK)
+
+#define SCG_PARAM_FIRCCLKPRES_MASK               (0x8U)
+#define SCG_PARAM_FIRCCLKPRES_SHIFT              (3U)
+/*! FIRCCLKPRES - FIRC Clock Present
+ *  0b0..FIRC clock source is not present
+ *  0b1..FIRC clock source is present
+ */
+#define SCG_PARAM_FIRCCLKPRES(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_FIRCCLKPRES_SHIFT)) & SCG_PARAM_FIRCCLKPRES_MASK)
+
+#define SCG_PARAM_ROSCCLKPRES_MASK               (0x10U)
+#define SCG_PARAM_ROSCCLKPRES_SHIFT              (4U)
+/*! ROSCCLKPRES - ROSC Clock Present
+ *  0b0..ROSC clock source is not present
+ *  0b1..ROSC clock source is present
+ */
+#define SCG_PARAM_ROSCCLKPRES(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_ROSCCLKPRES_SHIFT)) & SCG_PARAM_ROSCCLKPRES_MASK)
+/*! @} */
+
+/*! @name TRIM_LOCK - Trim Lock */
+/*! @{ */
+
+#define SCG_TRIM_LOCK_TRIM_UNLOCK_MASK           (0x1U)
+#define SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT          (0U)
+/*! TRIM_UNLOCK - TRIM_UNLOCK
+ *  0b0..SCG Trim Registers locked and not writable.
+ *  0b1..SCG Trim registers unlocked and writable.
+ */
+#define SCG_TRIM_LOCK_TRIM_UNLOCK(x)             (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT)) & SCG_TRIM_LOCK_TRIM_UNLOCK_MASK)
+
+#define SCG_TRIM_LOCK_IFR_DISABLE_MASK           (0x2U)
+#define SCG_TRIM_LOCK_IFR_DISABLE_SHIFT          (1U)
+/*! IFR_DISABLE - IFR_DISABLE
+ *  0b0..IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset.
+ *  0b1..IFR write access to SCG trim registers during system reset is blocked.
+ */
+#define SCG_TRIM_LOCK_IFR_DISABLE(x)             (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_IFR_DISABLE_SHIFT)) & SCG_TRIM_LOCK_IFR_DISABLE_MASK)
+
+#define SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK         (0xFFFF0000U)
+#define SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT        (16U)
+/*! TRIM_LOCK_KEY - TRIM_LOCK_KEY */
+#define SCG_TRIM_LOCK_TRIM_LOCK_KEY(x)           (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT)) & SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK)
+/*! @} */
+
+/*! @name CSR - Clock Status */
+/*! @{ */
+
+#define SCG_CSR_SCS_MASK                         (0x7000000U)
+#define SCG_CSR_SCS_SHIFT                        (24U)
+/*! SCS - System Clock Source
+ *  0b001..SOSC
+ *  0b010..SIRC
+ *  0b011..FIRC
+ *  0b100..ROSC
+ */
+#define SCG_CSR_SCS(x)                           (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK)
+/*! @} */
+
+/*! @name RCCR - Run Clock Control */
+/*! @{ */
+
+#define SCG_RCCR_SCS_MASK                        (0x7000000U)
+#define SCG_RCCR_SCS_SHIFT                       (24U)
+/*! SCS - System Clock Source
+ *  0b001..SOSC
+ *  0b010..SIRC
+ *  0b011..FIRC
+ *  0b100..ROSC
+ */
+#define SCG_RCCR_SCS(x)                          (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK)
+/*! @} */
+
+/*! @name SOSCCSR - SOSC Control Status */
+/*! @{ */
+
+#define SCG_SOSCCSR_SOSCEN_MASK                  (0x1U)
+#define SCG_SOSCCSR_SOSCEN_SHIFT                 (0U)
+/*! SOSCEN - SOSC Enable
+ *  0b0..SOSC is disabled
+ *  0b1..SOSC is enabled
+ */
+#define SCG_SOSCCSR_SOSCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK)
+
+#define SCG_SOSCCSR_SOSCSTEN_MASK                (0x2U)
+#define SCG_SOSCCSR_SOSCSTEN_SHIFT               (1U)
+/*! SOSCSTEN - SOSC Stop Enable
+ *  0b0..SOSC is disabled in Deep Sleep mode
+ *  0b1..SOSC is enabled in Deep Sleep mode only if SOSCEN is set
+ */
+#define SCG_SOSCCSR_SOSCSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK)
+
+#define SCG_SOSCCSR_SOSCCM_MASK                  (0x10000U)
+#define SCG_SOSCCSR_SOSCCM_SHIFT                 (16U)
+/*! SOSCCM - SOSC Clock Monitor Enable
+ *  0b0..SOSC Clock Monitor is disabled
+ *  0b1..SOSC Clock Monitor is enabled
+ */
+#define SCG_SOSCCSR_SOSCCM(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK)
+
+#define SCG_SOSCCSR_SOSCCMRE_MASK                (0x20000U)
+#define SCG_SOSCCSR_SOSCCMRE_SHIFT               (17U)
+/*! SOSCCMRE - SOSC Clock Monitor Reset Enable
+ *  0b0..Clock monitor generates an interrupt when an error is detected
+ *  0b1..Clock monitor generates a reset when an error is detected
+ */
+#define SCG_SOSCCSR_SOSCCMRE(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK)
+
+#define SCG_SOSCCSR_LK_MASK                      (0x800000U)
+#define SCG_SOSCCSR_LK_SHIFT                     (23U)
+/*! LK - Lock
+ *  0b0..This Control Status Register can be written
+ *  0b1..This Control Status Register cannot be written
+ */
+#define SCG_SOSCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK)
+
+#define SCG_SOSCCSR_SOSCVLD_MASK                 (0x1000000U)
+#define SCG_SOSCCSR_SOSCVLD_SHIFT                (24U)
+/*! SOSCVLD - SOSC Valid
+ *  0b0..SOSC is not enabled or clock is not valid
+ *  0b1..SOSC is enabled and output clock is valid
+ */
+#define SCG_SOSCCSR_SOSCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK)
+
+#define SCG_SOSCCSR_SOSCSEL_MASK                 (0x2000000U)
+#define SCG_SOSCCSR_SOSCSEL_SHIFT                (25U)
+/*! SOSCSEL - SOSC Selected
+ *  0b0..SOSC is not the system clock source
+ *  0b1..SOSC is the system clock source
+ */
+#define SCG_SOSCCSR_SOSCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK)
+
+#define SCG_SOSCCSR_SOSCERR_MASK                 (0x4000000U)
+#define SCG_SOSCCSR_SOSCERR_SHIFT                (26U)
+/*! SOSCERR - SOSC Clock Error
+ *  0b0..SOSC Clock Monitor is disabled or has not detected an error
+ *  0b1..SOSC Clock Monitor is enabled and detected an error
+ */
+#define SCG_SOSCCSR_SOSCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK)
+
+#define SCG_SOSCCSR_SOSCVLD_IE_MASK              (0x40000000U)
+#define SCG_SOSCCSR_SOSCVLD_IE_SHIFT             (30U)
+/*! SOSCVLD_IE - SOSC Valid Interrupt Enable
+ *  0b0..SOSCVLD interrupt is not enabled
+ *  0b1..SOSCVLD interrupt is enabled
+ */
+#define SCG_SOSCCSR_SOSCVLD_IE(x)                (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_IE_SHIFT)) & SCG_SOSCCSR_SOSCVLD_IE_MASK)
+/*! @} */
+
+/*! @name SOSCCFG - SOSC Configuration */
+/*! @{ */
+
+#define SCG_SOSCCFG_EREFS_MASK                   (0x4U)
+#define SCG_SOSCCFG_EREFS_SHIFT                  (2U)
+/*! EREFS - External Reference Select
+ *  0b0..External reference clock selected.
+ *  0b1..Internal crystal oscillator of OSC selected.
+ */
+#define SCG_SOSCCFG_EREFS(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK)
+
+#define SCG_SOSCCFG_RANGE_MASK                   (0x30U)
+#define SCG_SOSCCFG_RANGE_SHIFT                  (4U)
+/*! RANGE - SOSC Range Select
+ *  0b00..Frequency range select of 8-16 MHz.
+ *  0b01..Frequency range select of 16-25 MHz.
+ *  0b10..Frequency range select of 25-40 MHz.
+ *  0b11..Frequency range select of 40-50 MHz.
+ */
+#define SCG_SOSCCFG_RANGE(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_RANGE_SHIFT)) & SCG_SOSCCFG_RANGE_MASK)
+/*! @} */
+
+/*! @name SIRCCSR - SIRC Control Status */
+/*! @{ */
+
+#define SCG_SIRCCSR_SIRCSTEN_MASK                (0x2U)
+#define SCG_SIRCCSR_SIRCSTEN_SHIFT               (1U)
+/*! SIRCSTEN - SIRC Stop Enable
+ *  0b0..SIRC is disabled in Deep Sleep mode
+ *  0b1..SIRC is enabled in Deep Sleep mode
+ */
+#define SCG_SIRCCSR_SIRCSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK)
+
+#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK      (0x20U)
+#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT     (5U)
+/*! SIRC_CLK_PERIPH_EN - SIRC Clock to Peripherals Enable
+ *  0b0..SIRC clock to peripherals is disabled
+ *  0b1..SIRC clock to peripherals is enabled
+ */
+#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN(x)        (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT)) & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK)
+
+#define SCG_SIRCCSR_SIRCTREN_MASK                (0x100U)
+#define SCG_SIRCCSR_SIRCTREN_SHIFT               (8U)
+/*! SIRCTREN - SIRC 12 MHz Trim Enable (SIRCCFG[RANGE]=1)
+ *  0b0..Disables trimming SIRC to an external clock source
+ *  0b1..Enables trimming SIRC to an external clock source
+ */
+#define SCG_SIRCCSR_SIRCTREN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTREN_SHIFT)) & SCG_SIRCCSR_SIRCTREN_MASK)
+
+#define SCG_SIRCCSR_SIRCTRUP_MASK                (0x200U)
+#define SCG_SIRCCSR_SIRCTRUP_SHIFT               (9U)
+/*! SIRCTRUP - SIRC Trim Update
+ *  0b0..Disables SIRC trimming updates
+ *  0b1..Enables SIRC trimming updates
+ */
+#define SCG_SIRCCSR_SIRCTRUP(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTRUP_SHIFT)) & SCG_SIRCCSR_SIRCTRUP_MASK)
+
+#define SCG_SIRCCSR_TRIM_LOCK_MASK               (0x400U)
+#define SCG_SIRCCSR_TRIM_LOCK_SHIFT              (10U)
+/*! TRIM_LOCK - SIRC TRIM LOCK
+ *  0b0..SIRC auto trim not locked to target frequency range
+ *  0b1..SIRC auto trim locked to target frequency range
+ */
+#define SCG_SIRCCSR_TRIM_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_TRIM_LOCK_SHIFT)) & SCG_SIRCCSR_TRIM_LOCK_MASK)
+
+#define SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK      (0x800U)
+#define SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT     (11U)
+/*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass
+ *  0b0..SIRC Coarse Auto Trim NOT Bypassed
+ *  0b1..SIRC Coarse Auto Trim Bypassed
+ */
+#define SCG_SIRCCSR_COARSE_TRIM_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK)
+
+#define SCG_SIRCCSR_LK_MASK                      (0x800000U)
+#define SCG_SIRCCSR_LK_SHIFT                     (23U)
+/*! LK - Lock
+ *  0b0..Control Status Register can be written
+ *  0b1..Control Status Register cannot be written
+ */
+#define SCG_SIRCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK)
+
+#define SCG_SIRCCSR_SIRCVLD_MASK                 (0x1000000U)
+#define SCG_SIRCCSR_SIRCVLD_SHIFT                (24U)
+/*! SIRCVLD - SIRC Valid
+ *  0b0..SIRC is not enabled or clock is not valid
+ *  0b1..SIRC is enabled and output clock is valid
+ */
+#define SCG_SIRCCSR_SIRCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK)
+
+#define SCG_SIRCCSR_SIRCSEL_MASK                 (0x2000000U)
+#define SCG_SIRCCSR_SIRCSEL_SHIFT                (25U)
+/*! SIRCSEL - SIRC Selected
+ *  0b0..SIRC is not the system clock source
+ *  0b1..SIRC is the system clock source
+ */
+#define SCG_SIRCCSR_SIRCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK)
+
+#define SCG_SIRCCSR_SIRCERR_MASK                 (0x4000000U)
+#define SCG_SIRCCSR_SIRCERR_SHIFT                (26U)
+/*! SIRCERR - SIRC Clock Error
+ *  0b0..Error not detected with the SIRC trimming
+ *  0b1..Error detected with the SIRC trimming
+ */
+#define SCG_SIRCCSR_SIRCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_SHIFT)) & SCG_SIRCCSR_SIRCERR_MASK)
+
+#define SCG_SIRCCSR_SIRCERR_IE_MASK              (0x8000000U)
+#define SCG_SIRCCSR_SIRCERR_IE_SHIFT             (27U)
+/*! SIRCERR_IE - SIRC Clock Error Interrupt Enable
+ *  0b0..SIRCERR interrupt is not enabled
+ *  0b1..SIRCERR interrupt is enabled
+ */
+#define SCG_SIRCCSR_SIRCERR_IE(x)                (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_IE_SHIFT)) & SCG_SIRCCSR_SIRCERR_IE_MASK)
+/*! @} */
+
+/*! @name SIRCTCFG - SIRC Trim Configuration */
+/*! @{ */
+
+#define SCG_SIRCTCFG_TRIMSRC_MASK                (0x3U)
+#define SCG_SIRCTCFG_TRIMSRC_SHIFT               (0U)
+/*! TRIMSRC - Trim Source
+ *  0b00..Reserved
+ *  0b01..Reserved
+ *  0b10..SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz.
+ *  0b11..Reserved
+ */
+#define SCG_SIRCTCFG_TRIMSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMSRC_SHIFT)) & SCG_SIRCTCFG_TRIMSRC_MASK)
+
+#define SCG_SIRCTCFG_TRIMDIV_MASK                (0x7F0000U)
+#define SCG_SIRCTCFG_TRIMDIV_SHIFT               (16U)
+/*! TRIMDIV - SIRC Trim Pre-divider */
+#define SCG_SIRCTCFG_TRIMDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMDIV_SHIFT)) & SCG_SIRCTCFG_TRIMDIV_MASK)
+/*! @} */
+
+/*! @name SIRCTRIM - SIRC Trim */
+/*! @{ */
+
+#define SCG_SIRCTRIM_CCOTRIM_MASK                (0x3FU)
+#define SCG_SIRCTRIM_CCOTRIM_SHIFT               (0U)
+/*! CCOTRIM - CCO Trim */
+#define SCG_SIRCTRIM_CCOTRIM(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CCOTRIM_SHIFT)) & SCG_SIRCTRIM_CCOTRIM_MASK)
+
+#define SCG_SIRCTRIM_CLTRIM_MASK                 (0x3F00U)
+#define SCG_SIRCTRIM_CLTRIM_SHIFT                (8U)
+/*! CLTRIM - CL Trim */
+#define SCG_SIRCTRIM_CLTRIM(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CLTRIM_SHIFT)) & SCG_SIRCTRIM_CLTRIM_MASK)
+
+#define SCG_SIRCTRIM_TCTRIM_MASK                 (0x1F0000U)
+#define SCG_SIRCTRIM_TCTRIM_SHIFT                (16U)
+/*! TCTRIM - Trim Temp */
+#define SCG_SIRCTRIM_TCTRIM(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_TCTRIM_SHIFT)) & SCG_SIRCTRIM_TCTRIM_MASK)
+
+#define SCG_SIRCTRIM_FVCHTRIM_MASK               (0x1F000000U)
+#define SCG_SIRCTRIM_FVCHTRIM_SHIFT              (24U)
+#define SCG_SIRCTRIM_FVCHTRIM(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_FVCHTRIM_SHIFT)) & SCG_SIRCTRIM_FVCHTRIM_MASK)
+/*! @} */
+
+/*! @name SIRCSTAT - SIRC Auto-trimming Status */
+/*! @{ */
+
+#define SCG_SIRCSTAT_CCOTRIM_MASK                (0x3FU)
+#define SCG_SIRCSTAT_CCOTRIM_SHIFT               (0U)
+/*! CCOTRIM - CCO Trim */
+#define SCG_SIRCSTAT_CCOTRIM(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CCOTRIM_SHIFT)) & SCG_SIRCSTAT_CCOTRIM_MASK)
+
+#define SCG_SIRCSTAT_CLTRIM_MASK                 (0x3F00U)
+#define SCG_SIRCSTAT_CLTRIM_SHIFT                (8U)
+/*! CLTRIM - CL Trim */
+#define SCG_SIRCSTAT_CLTRIM(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CLTRIM_SHIFT)) & SCG_SIRCSTAT_CLTRIM_MASK)
+/*! @} */
+
+/*! @name FIRCCSR - FIRC Control Status */
+/*! @{ */
+
+#define SCG_FIRCCSR_FIRCEN_MASK                  (0x1U)
+#define SCG_FIRCCSR_FIRCEN_SHIFT                 (0U)
+/*! FIRCEN - FIRC Enable
+ *  0b0..FIRC is disabled
+ *  0b1..FIRC is enabled
+ */
+#define SCG_FIRCCSR_FIRCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK)
+
+#define SCG_FIRCCSR_FIRCSTEN_MASK                (0x2U)
+#define SCG_FIRCCSR_FIRCSTEN_SHIFT               (1U)
+/*! FIRCSTEN - FIRC Stop Enable
+ *  0b0..FIRC is disabled in Deep Sleep mode
+ *  0b1..FIRC is enabled in Deep Sleep mode
+ */
+#define SCG_FIRCCSR_FIRCSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK)
+
+#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK     (0x10U)
+#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT    (4U)
+/*! FIRC_SCLK_PERIPH_EN - FIRC 45 MHz Clock to peripherals Enable
+ *  0b0..FIRC 45 MHz to peripherals is disabled
+ *  0b1..FIRC 45 MHz to peripherals is enabled
+ */
+#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN(x)       (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK)
+
+#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK     (0x20U)
+#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT    (5U)
+/*! FIRC_FCLK_PERIPH_EN - FRO_HF Clock to peripherals Enable
+ *  0b0..FRO_HF to peripherals is disabled
+ *  0b1..FRO_HF to peripherals is enabled
+ */
+#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN(x)       (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK)
+
+#define SCG_FIRCCSR_LK_MASK                      (0x800000U)
+#define SCG_FIRCCSR_LK_SHIFT                     (23U)
+/*! LK - Lock
+ *  0b0..Control Status Register can be written
+ *  0b1..Control Status Register cannot be written
+ */
+#define SCG_FIRCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK)
+
+#define SCG_FIRCCSR_FIRCVLD_MASK                 (0x1000000U)
+#define SCG_FIRCCSR_FIRCVLD_SHIFT                (24U)
+/*! FIRCVLD - FIRC Valid status
+ *  0b0..FIRC is not enabled or clock is not valid.
+ *  0b1..FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog.
+ */
+#define SCG_FIRCCSR_FIRCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK)
+
+#define SCG_FIRCCSR_FIRCSEL_MASK                 (0x2000000U)
+#define SCG_FIRCCSR_FIRCSEL_SHIFT                (25U)
+/*! FIRCSEL - FIRC Selected
+ *  0b0..FIRC is not the system clock source
+ *  0b1..FIRC is the system clock source
+ */
+#define SCG_FIRCCSR_FIRCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK)
+
+#define SCG_FIRCCSR_FIRCERR_MASK                 (0x4000000U)
+#define SCG_FIRCCSR_FIRCERR_SHIFT                (26U)
+/*! FIRCERR - FIRC Clock Error
+ *  0b0..Error not detected with the FIRC trimming
+ *  0b1..Error detected with the FIRC trimming
+ */
+#define SCG_FIRCCSR_FIRCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK)
+
+#define SCG_FIRCCSR_FIRCERR_IE_MASK              (0x8000000U)
+#define SCG_FIRCCSR_FIRCERR_IE_SHIFT             (27U)
+/*! FIRCERR_IE - FIRC Clock Error Interrupt Enable
+ *  0b0..FIRCERR interrupt is not enabled
+ *  0b1..FIRCERR interrupt is enabled
+ */
+#define SCG_FIRCCSR_FIRCERR_IE(x)                (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
+
+#define SCG_FIRCCSR_FIRCACC_IE_MASK              (0x40000000U)
+#define SCG_FIRCCSR_FIRCACC_IE_SHIFT             (30U)
+/*! FIRCACC_IE - FIRC Accurate Interrupt Enable
+ *  0b0..FIRCACC interrupt is not enabled
+ *  0b1..FIRCACC interrupt is enabled
+ */
+#define SCG_FIRCCSR_FIRCACC_IE(x)                (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_IE_SHIFT)) & SCG_FIRCCSR_FIRCACC_IE_MASK)
+
+#define SCG_FIRCCSR_FIRCACC_MASK                 (0x80000000U)
+#define SCG_FIRCCSR_FIRCACC_SHIFT                (31U)
+/*! FIRCACC - FIRC Frequency Accurate
+ *  0b0..FIRC is not enabled or clock is not accurate.
+ *  0b1..FIRC is enabled and output clock is accurate after some preparation time which is obtained by counting FRO_HF clock.
+ */
+#define SCG_FIRCCSR_FIRCACC(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_SHIFT)) & SCG_FIRCCSR_FIRCACC_MASK)
+/*! @} */
+
+/*! @name FIRCCFG - FIRC Configuration */
+/*! @{ */
+
+#define SCG_FIRCCFG_FREQ_SEL_MASK                (0xEU)
+#define SCG_FIRCCFG_FREQ_SEL_SHIFT               (1U)
+/*! FREQ_SEL - Frequency select
+ *  0b001..45 MHz FIRC clock selected, divided from 180 MHz
+ *  0b011..60 MHz FIRC clock selected
+ *  0b101..90 MHz FIRC clock selected
+ *  0b111..180 MHz FIRC clock selected
+ */
+#define SCG_FIRCCFG_FREQ_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_FREQ_SEL_SHIFT)) & SCG_FIRCCFG_FREQ_SEL_MASK)
+/*! @} */
+
+/*! @name FIRCTRIM - FIRC Trim */
+/*! @{ */
+
+#define SCG_FIRCTRIM_TRIMFINE_MASK               (0xFFU)
+#define SCG_FIRCTRIM_TRIMFINE_SHIFT              (0U)
+/*! TRIMFINE - Trim Fine */
+#define SCG_FIRCTRIM_TRIMFINE(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMFINE_SHIFT)) & SCG_FIRCTRIM_TRIMFINE_MASK)
+
+#define SCG_FIRCTRIM_TRIMCOAR_MASK               (0x3F00U)
+#define SCG_FIRCTRIM_TRIMCOAR_SHIFT              (8U)
+/*! TRIMCOAR - Trim Coarse */
+#define SCG_FIRCTRIM_TRIMCOAR(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMCOAR_SHIFT)) & SCG_FIRCTRIM_TRIMCOAR_MASK)
+
+#define SCG_FIRCTRIM_TRIMTEMP_MASK               (0xF0000U)
+#define SCG_FIRCTRIM_TRIMTEMP_SHIFT              (16U)
+/*! TRIMTEMP - Trim Temperature */
+#define SCG_FIRCTRIM_TRIMTEMP(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMTEMP_SHIFT)) & SCG_FIRCTRIM_TRIMTEMP_MASK)
+
+#define SCG_FIRCTRIM_TRIMSTART_MASK              (0x3F000000U)
+#define SCG_FIRCTRIM_TRIMSTART_SHIFT             (24U)
+/*! TRIMSTART - Trim Start */
+#define SCG_FIRCTRIM_TRIMSTART(x)                (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMSTART_SHIFT)) & SCG_FIRCTRIM_TRIMSTART_MASK)
+/*! @} */
+
+/*! @name ROSCCSR - ROSC Control Status */
+/*! @{ */
+
+#define SCG_ROSCCSR_LK_MASK                      (0x800000U)
+#define SCG_ROSCCSR_LK_SHIFT                     (23U)
+/*! LK - Lock
+ *  0b0..Control Status Register can be written
+ *  0b1..Control Status Register cannot be written
+ */
+#define SCG_ROSCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_LK_SHIFT)) & SCG_ROSCCSR_LK_MASK)
+
+#define SCG_ROSCCSR_ROSCVLD_MASK                 (0x1000000U)
+#define SCG_ROSCCSR_ROSCVLD_SHIFT                (24U)
+/*! ROSCVLD - ROSC Valid
+ *  0b0..ROSC is not enabled or clock is not valid
+ *  0b1..ROSC is enabled and output clock is valid
+ */
+#define SCG_ROSCCSR_ROSCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK)
+
+#define SCG_ROSCCSR_ROSCSEL_MASK                 (0x2000000U)
+#define SCG_ROSCCSR_ROSCSEL_SHIFT                (25U)
+/*! ROSCSEL - ROSC Selected
+ *  0b0..ROSC is not the system clock source
+ *  0b1..ROSC is the system clock source
+ */
+#define SCG_ROSCCSR_ROSCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCSEL_SHIFT)) & SCG_ROSCCSR_ROSCSEL_MASK)
+
+#define SCG_ROSCCSR_ROSCERR_MASK                 (0x4000000U)
+#define SCG_ROSCCSR_ROSCERR_SHIFT                (26U)
+/*! ROSCERR - ROSC Clock Error
+ *  0b0..ROSC Clock has not detected an error
+ *  0b1..ROSC Clock has detected an error
+ */
+#define SCG_ROSCCSR_ROSCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK)
+/*! @} */
+
+/*! @name LDOCSR - LDO Control and Status */
+/*! @{ */
+
+#define SCG_LDOCSR_LDOEN_MASK                    (0x1U)
+#define SCG_LDOCSR_LDOEN_SHIFT                   (0U)
+/*! LDOEN - LDO Enable
+ *  0b0..LDO is disabled
+ *  0b1..LDO is enabled
+ */
+#define SCG_LDOCSR_LDOEN(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_LDOEN_SHIFT)) & SCG_LDOCSR_LDOEN_MASK)
+
+#define SCG_LDOCSR_VOUT_SEL_MASK                 (0xEU)
+#define SCG_LDOCSR_VOUT_SEL_SHIFT                (1U)
+/*! VOUT_SEL - LDO output voltage select
+ *  0b000..VOUT = 1V
+ *  0b001..VOUT = 1V
+ *  0b010..VOUT = 1V
+ *  0b011..VOUT = 1.05V
+ *  0b100..VOUT = 1.1V
+ *  0b101..VOUT = 1.15V
+ *  0b110..VOUT = 1.2V
+ *  0b111..VOUT = 1.25V
+ */
+#define SCG_LDOCSR_VOUT_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_SEL_SHIFT)) & SCG_LDOCSR_VOUT_SEL_MASK)
+
+#define SCG_LDOCSR_LDOBYPASS_MASK                (0x10U)
+#define SCG_LDOCSR_LDOBYPASS_SHIFT               (4U)
+/*! LDOBYPASS - LDO Bypass
+ *  0b0..LDO is not bypassed
+ *  0b1..LDO is bypassed
+ */
+#define SCG_LDOCSR_LDOBYPASS(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_LDOBYPASS_SHIFT)) & SCG_LDOCSR_LDOBYPASS_MASK)
+
+#define SCG_LDOCSR_VOUT_OK_MASK                  (0x80000000U)
+#define SCG_LDOCSR_VOUT_OK_SHIFT                 (31U)
+/*! VOUT_OK - LDO VOUT OK Inform.
+ *  0b0..LDO output VOUT is not OK
+ *  0b1..LDO output VOUT is OK
+ */
+#define SCG_LDOCSR_VOUT_OK(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_OK_SHIFT)) & SCG_LDOCSR_VOUT_OK_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SCG_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group SCG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_SCG_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SMARTDMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SMARTDMA.h
new file mode 100644
index 0000000000..a4309390bf
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SMARTDMA.h
@@ -0,0 +1,253 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for SMARTDMA
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_SMARTDMA.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for SMARTDMA
+ *
+ * CMSIS Peripheral Access Layer for SMARTDMA
+ */
+
+#if !defined(PERI_SMARTDMA_H_)
+#define PERI_SMARTDMA_H_                         /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- SMARTDMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMARTDMA_Peripheral_Access_Layer SMARTDMA Peripheral Access Layer
+ * @{
+ */
+
+/** SMARTDMA - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[32];
+  __IO uint32_t BOOTADR;                           /**< Boot Address, offset: 0x20 */
+  __IO uint32_t CTRL;                              /**< Control, offset: 0x24 */
+  __I  uint32_t PC;                                /**< Program Counter, offset: 0x28 */
+  __I  uint32_t SP;                                /**< Stack Pointer, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t ARM2EZH;                           /**< ARM to EZH Interrupt Control, offset: 0x40 */
+  __IO uint32_t EZH2ARM;                           /**< EZH to ARM Trigger, offset: 0x44 */
+  __IO uint32_t PENDTRAP;                          /**< Pending Trap Control, offset: 0x48 */
+} SMARTDMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SMARTDMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMARTDMA_Register_Masks SMARTDMA Register Masks
+ * @{
+ */
+
+/*! @name BOOTADR - Boot Address */
+/*! @{ */
+
+#define SMARTDMA_BOOTADR_ADDR_MASK               (0xFFFFFFFCU)
+#define SMARTDMA_BOOTADR_ADDR_SHIFT              (2U)
+/*! ADDR - 32-bit boot address, the boot address should be 4-byte aligned. */
+#define SMARTDMA_BOOTADR_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BOOTADR_ADDR_SHIFT)) & SMARTDMA_BOOTADR_ADDR_MASK)
+/*! @} */
+
+/*! @name CTRL - Control */
+/*! @{ */
+
+#define SMARTDMA_CTRL_START_MASK                 (0x1U)
+#define SMARTDMA_CTRL_START_SHIFT                (0U)
+/*! START - Start Bit Ignition */
+#define SMARTDMA_CTRL_START(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_START_SHIFT)) & SMARTDMA_CTRL_START_MASK)
+
+#define SMARTDMA_CTRL_EXF_MASK                   (0x2U)
+#define SMARTDMA_CTRL_EXF_SHIFT                  (1U)
+/*! EXF - External Flag */
+#define SMARTDMA_CTRL_EXF(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_EXF_SHIFT)) & SMARTDMA_CTRL_EXF_MASK)
+
+#define SMARTDMA_CTRL_ERRDIS_MASK                (0x4U)
+#define SMARTDMA_CTRL_ERRDIS_SHIFT               (2U)
+/*! ERRDIS - Error Disable */
+#define SMARTDMA_CTRL_ERRDIS(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_ERRDIS_SHIFT)) & SMARTDMA_CTRL_ERRDIS_MASK)
+
+#define SMARTDMA_CTRL_BUFEN_MASK                 (0x8U)
+#define SMARTDMA_CTRL_BUFEN_SHIFT                (3U)
+/*! BUFEN - Buffer Enable */
+#define SMARTDMA_CTRL_BUFEN(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_BUFEN_SHIFT)) & SMARTDMA_CTRL_BUFEN_MASK)
+
+#define SMARTDMA_CTRL_SYNCEN_MASK                (0x10U)
+#define SMARTDMA_CTRL_SYNCEN_SHIFT               (4U)
+/*! SYNCEN - Sync Enable */
+#define SMARTDMA_CTRL_SYNCEN(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_SYNCEN_SHIFT)) & SMARTDMA_CTRL_SYNCEN_MASK)
+
+#define SMARTDMA_CTRL_WKEY_MASK                  (0xFFFF0000U)
+#define SMARTDMA_CTRL_WKEY_SHIFT                 (16U)
+/*! WKEY - Write Key */
+#define SMARTDMA_CTRL_WKEY(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_WKEY_SHIFT)) & SMARTDMA_CTRL_WKEY_MASK)
+/*! @} */
+
+/*! @name PC - Program Counter */
+/*! @{ */
+
+#define SMARTDMA_PC_PC_MASK                      (0xFFFFFFFFU)
+#define SMARTDMA_PC_PC_SHIFT                     (0U)
+/*! PC - Program Counter */
+#define SMARTDMA_PC_PC(x)                        (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PC_PC_SHIFT)) & SMARTDMA_PC_PC_MASK)
+/*! @} */
+
+/*! @name SP - Stack Pointer */
+/*! @{ */
+
+#define SMARTDMA_SP_SP_MASK                      (0xFFFFFFFFU)
+#define SMARTDMA_SP_SP_SHIFT                     (0U)
+/*! SP - Stack Pointer */
+#define SMARTDMA_SP_SP(x)                        (((uint32_t)(((uint32_t)(x)) << SMARTDMA_SP_SP_SHIFT)) & SMARTDMA_SP_SP_MASK)
+/*! @} */
+
+/*! @name ARM2EZH - ARM to EZH Interrupt Control */
+/*! @{ */
+
+#define SMARTDMA_ARM2EZH_IE_MASK                 (0x3U)
+#define SMARTDMA_ARM2EZH_IE_SHIFT                (0U)
+/*! IE - Interrupt Enable */
+#define SMARTDMA_ARM2EZH_IE(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTDMA_ARM2EZH_IE_SHIFT)) & SMARTDMA_ARM2EZH_IE_MASK)
+
+#define SMARTDMA_ARM2EZH_GP_MASK                 (0xFFFFFFFCU)
+#define SMARTDMA_ARM2EZH_GP_SHIFT                (2U)
+/*! GP - General purpose register bits */
+#define SMARTDMA_ARM2EZH_GP(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTDMA_ARM2EZH_GP_SHIFT)) & SMARTDMA_ARM2EZH_GP_MASK)
+/*! @} */
+
+/*! @name EZH2ARM - EZH to ARM Trigger */
+/*! @{ */
+
+#define SMARTDMA_EZH2ARM_GP_MASK                 (0xFFFFFFFFU)
+#define SMARTDMA_EZH2ARM_GP_SHIFT                (0U)
+/*! GP - General purpose register bits Writing to EZH2ARM triggers the ARM interrupt when ARM2EZH [1:0] == 2h */
+#define SMARTDMA_EZH2ARM_GP(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EZH2ARM_GP_SHIFT)) & SMARTDMA_EZH2ARM_GP_MASK)
+/*! @} */
+
+/*! @name PENDTRAP - Pending Trap Control */
+/*! @{ */
+
+#define SMARTDMA_PENDTRAP_STATUS_MASK            (0xFFU)
+#define SMARTDMA_PENDTRAP_STATUS_SHIFT           (0U)
+/*! STATUS - Status Flag or Pending Trap Request */
+#define SMARTDMA_PENDTRAP_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_STATUS_SHIFT)) & SMARTDMA_PENDTRAP_STATUS_MASK)
+
+#define SMARTDMA_PENDTRAP_POL_MASK               (0xFF00U)
+#define SMARTDMA_PENDTRAP_POL_SHIFT              (8U)
+/*! POL - Polarity */
+#define SMARTDMA_PENDTRAP_POL(x)                 (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_POL_SHIFT)) & SMARTDMA_PENDTRAP_POL_MASK)
+
+#define SMARTDMA_PENDTRAP_EN_MASK                (0xFF0000U)
+#define SMARTDMA_PENDTRAP_EN_SHIFT               (16U)
+/*! EN - Enable Pending Trap */
+#define SMARTDMA_PENDTRAP_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_EN_SHIFT)) & SMARTDMA_PENDTRAP_EN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SMARTDMA_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group SMARTDMA_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_SMARTDMA_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SPC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SPC.h
new file mode 100644
index 0000000000..274de6a17a
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SPC.h
@@ -0,0 +1,818 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for SPC
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_SPC.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for SPC
+ *
+ * CMSIS Peripheral Access Layer for SPC
+ */
+
+#if !defined(PERI_SPC_H_)
+#define PERI_SPC_H_                              /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- SPC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPC_Peripheral_Access_Layer SPC Peripheral Access Layer
+ * @{
+ */
+
+/** SPC - Size of Registers Arrays */
+#define SPC_PD_STATUS_COUNT                       1u
+
+/** SPC - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t SC;                                /**< Status Control, offset: 0x10 */
+  __IO uint32_t CNTRL;                             /**< SPC Regulator Control, offset: 0x14 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t LPREQ_CFG;                         /**< Low-Power Request Configuration, offset: 0x1C */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t PD_STATUS[SPC_PD_STATUS_COUNT];    /**< SPC Power Domain Mode Status, array offset: 0x30, array step: 0x4 */
+       uint8_t RESERVED_3[12];
+  __IO uint32_t SRAMCTL;                           /**< SRAM Control, offset: 0x40 */
+       uint8_t RESERVED_4[16];
+  __IO uint32_t SRAMRETLDO_REFTRIM;                /**< SRAM Retention Reference Trim, offset: 0x54 */
+  __IO uint32_t SRAMRETLDO_CNTRL;                  /**< SRAM Retention LDO Control, offset: 0x58 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t HP_CNFG_CTRL;                      /**< High Power Config Control, offset: 0x60 */
+       uint8_t RESERVED_6[156];
+  __IO uint32_t ACTIVE_CFG;                        /**< Active Power Mode Configuration, offset: 0x100 */
+  __IO uint32_t ACTIVE_CFG1;                       /**< Active Power Mode Configuration 1, offset: 0x104 */
+  __IO uint32_t LP_CFG;                            /**< Low-Power Mode Configuration, offset: 0x108 */
+  __IO uint32_t LP_CFG1;                           /**< Low Power Mode Configuration 1, offset: 0x10C */
+  __IO uint32_t HP_CFG;                            /**< High Power Mode Configuration, offset: 0x110 */
+       uint8_t RESERVED_7[12];
+  __IO uint32_t LPWKUP_DELAY;                      /**< Low Power Wake-Up Delay, offset: 0x120 */
+  __IO uint32_t ACTIVE_VDELAY;                     /**< Active Voltage Trim Delay, offset: 0x124 */
+       uint8_t RESERVED_8[8];
+  __IO uint32_t VD_STAT;                           /**< Voltage Detect Status, offset: 0x130 */
+  __IO uint32_t VD_CORE_CFG;                       /**< Core Voltage Detect Configuration, offset: 0x134 */
+  __IO uint32_t VD_SYS_CFG;                        /**< System Voltage Detect Configuration, offset: 0x138 */
+       uint8_t RESERVED_9[4];
+  __IO uint32_t EVD_CFG;                           /**< External Voltage Domain Configuration, offset: 0x140 */
+  __IO uint32_t GLITCH_DETECT_SC;                  /**< Glitch Detect Status Control, offset: 0x144 */
+       uint8_t RESERVED_10[440];
+       uint32_t CORELDO_CFG;                       /**< LDO_CORE Configuration, offset: 0x300 */
+} SPC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPC_Register_Masks SPC Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID */
+/*! @{ */
+
+#define SPC_VERID_FEATURE_MASK                   (0xFFFFU)
+#define SPC_VERID_FEATURE_SHIFT                  (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000000..Standard features
+ */
+#define SPC_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << SPC_VERID_FEATURE_SHIFT)) & SPC_VERID_FEATURE_MASK)
+
+#define SPC_VERID_MINOR_MASK                     (0xFF0000U)
+#define SPC_VERID_MINOR_SHIFT                    (16U)
+/*! MINOR - Minor Version Number */
+#define SPC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MINOR_SHIFT)) & SPC_VERID_MINOR_MASK)
+
+#define SPC_VERID_MAJOR_MASK                     (0xFF000000U)
+#define SPC_VERID_MAJOR_SHIFT                    (24U)
+/*! MAJOR - Major Version Number */
+#define SPC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MAJOR_SHIFT)) & SPC_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name SC - Status Control */
+/*! @{ */
+
+#define SPC_SC_BUSY_MASK                         (0x1U)
+#define SPC_SC_BUSY_SHIFT                        (0U)
+/*! BUSY - SPC Busy Status Flag
+ *  0b0..Not busy
+ *  0b1..Busy
+ */
+#define SPC_SC_BUSY(x)                           (((uint32_t)(((uint32_t)(x)) << SPC_SC_BUSY_SHIFT)) & SPC_SC_BUSY_MASK)
+
+#define SPC_SC_SPC_LP_REQ_MASK                   (0x2U)
+#define SPC_SC_SPC_LP_REQ_SHIFT                  (1U)
+/*! SPC_LP_REQ - SPC Power Mode Configuration Status Flag
+ *  0b0..No effect
+ *  0b0..SPC is in Active mode; the ACTIVE_CFG register has control
+ *  0b1..All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register
+ *  0b1..Clear the flag
+ */
+#define SPC_SC_SPC_LP_REQ(x)                     (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_REQ_SHIFT)) & SPC_SC_SPC_LP_REQ_MASK)
+
+#define SPC_SC_HP_ACTIVE_MASK                    (0x8U)
+#define SPC_SC_HP_ACTIVE_SHIFT                   (3U)
+/*! HP_ACTIVE - HP_CFG Select Status Flag
+ *  0b0..ACTIVE_CFG selected
+ *  0b1..HP_CFG selected
+ */
+#define SPC_SC_HP_ACTIVE(x)                      (((uint32_t)(((uint32_t)(x)) << SPC_SC_HP_ACTIVE_SHIFT)) & SPC_SC_HP_ACTIVE_MASK)
+
+#define SPC_SC_SPC_LP_MODE_MASK                  (0xF0U)
+#define SPC_SC_SPC_LP_MODE_SHIFT                 (4U)
+/*! SPC_LP_MODE - Power Domain Low-Power Mode Request
+ *  0b0000..
+ *  0b0001..DSLEEP with system clock off
+ *  0b0010..PDOWN with system clock off
+ *  0b0100..
+ *  0b1000..DPDOWN with system clock off
+ */
+#define SPC_SC_SPC_LP_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_MODE_SHIFT)) & SPC_SC_SPC_LP_MODE_MASK)
+
+#define SPC_SC_ISO_CLR_MASK                      (0x10000U)
+#define SPC_SC_ISO_CLR_SHIFT                     (16U)
+/*! ISO_CLR - Isolation Clear Flags */
+#define SPC_SC_ISO_CLR(x)                        (((uint32_t)(((uint32_t)(x)) << SPC_SC_ISO_CLR_SHIFT)) & SPC_SC_ISO_CLR_MASK)
+/*! @} */
+
+/*! @name CNTRL - SPC Regulator Control */
+/*! @{ */
+
+#define SPC_CNTRL_CORELDO_EN_MASK                (0x1U)
+#define SPC_CNTRL_CORELDO_EN_SHIFT               (0U)
+/*! CORELDO_EN - LDO_CORE Regulator Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_CNTRL_CORELDO_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_CORELDO_EN_SHIFT)) & SPC_CNTRL_CORELDO_EN_MASK)
+/*! @} */
+
+/*! @name LPREQ_CFG - Low-Power Request Configuration */
+/*! @{ */
+
+#define SPC_LPREQ_CFG_LPREQOE_MASK               (0x1U)
+#define SPC_LPREQ_CFG_LPREQOE_SHIFT              (0U)
+/*! LPREQOE - Low-Power Request Output Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_LPREQ_CFG_LPREQOE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOE_SHIFT)) & SPC_LPREQ_CFG_LPREQOE_MASK)
+
+#define SPC_LPREQ_CFG_LPREQPOL_MASK              (0x2U)
+#define SPC_LPREQ_CFG_LPREQPOL_SHIFT             (1U)
+/*! LPREQPOL - Low-Power Request Output Pin Polarity Control
+ *  0b0..High
+ *  0b1..Low
+ */
+#define SPC_LPREQ_CFG_LPREQPOL(x)                (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQPOL_SHIFT)) & SPC_LPREQ_CFG_LPREQPOL_MASK)
+
+#define SPC_LPREQ_CFG_LPREQOV_MASK               (0xCU)
+#define SPC_LPREQ_CFG_LPREQOV_SHIFT              (2U)
+/*! LPREQOV - Low-Power Request Output Override
+ *  0b00..Not forced
+ *  0b01..
+ *  0b10..Forced low (ignore LPREQPOL settings)
+ *  0b11..Forced high (ignore LPREQPOL settings)
+ */
+#define SPC_LPREQ_CFG_LPREQOV(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOV_SHIFT)) & SPC_LPREQ_CFG_LPREQOV_MASK)
+/*! @} */
+
+/*! @name PD_STATUS - SPC Power Domain Mode Status */
+/*! @{ */
+
+#define SPC_PD_STATUS_PD_LP_REQ_MASK             (0x10U)
+#define SPC_PD_STATUS_PD_LP_REQ_SHIFT            (4U)
+/*! PD_LP_REQ - Power Domain Low Power Request Flag
+ *  0b0..Did not request
+ *  0b1..Requested
+ */
+#define SPC_PD_STATUS_PD_LP_REQ(x)               (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PD_LP_REQ_SHIFT)) & SPC_PD_STATUS_PD_LP_REQ_MASK)
+
+#define SPC_PD_STATUS_LP_MODE_MASK               (0xF00U)
+#define SPC_PD_STATUS_LP_MODE_SHIFT              (8U)
+/*! LP_MODE - Power Domain Low Power Mode Request
+ *  0b0000..
+ *  0b0001..DSLEEP with system clock off
+ *  0b0010..PDOWN with system clock off
+ *  0b0100..
+ *  0b1000..DPDOWN with system clock off
+ */
+#define SPC_PD_STATUS_LP_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_LP_MODE_SHIFT)) & SPC_PD_STATUS_LP_MODE_MASK)
+/*! @} */
+
+/*! @name SRAMCTL - SRAM Control */
+/*! @{ */
+
+#define SPC_SRAMCTL_VSM_MASK                     (0x3U)
+#define SPC_SRAMCTL_VSM_SHIFT                    (0U)
+/*! VSM - Voltage Select Margin
+ *  0b00..
+ *  0b01..1.0 V
+ *  0b10..1.1 V
+ *  0b11..
+ */
+#define SPC_SRAMCTL_VSM(x)                       (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_VSM_SHIFT)) & SPC_SRAMCTL_VSM_MASK)
+
+#define SPC_SRAMCTL_REQ_MASK                     (0x40000000U)
+#define SPC_SRAMCTL_REQ_SHIFT                    (30U)
+/*! REQ - SRAM Voltage Update Request
+ *  0b0..Do not request
+ *  0b1..Request
+ */
+#define SPC_SRAMCTL_REQ(x)                       (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_REQ_SHIFT)) & SPC_SRAMCTL_REQ_MASK)
+
+#define SPC_SRAMCTL_ACK_MASK                     (0x80000000U)
+#define SPC_SRAMCTL_ACK_SHIFT                    (31U)
+/*! ACK - SRAM Voltage Update Request Acknowledge
+ *  0b0..Not acknowledged
+ *  0b1..Acknowledged
+ */
+#define SPC_SRAMCTL_ACK(x)                       (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_ACK_SHIFT)) & SPC_SRAMCTL_ACK_MASK)
+/*! @} */
+
+/*! @name SRAMRETLDO_REFTRIM - SRAM Retention Reference Trim */
+/*! @{ */
+
+#define SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK      (0x1FU)
+#define SPC_SRAMRETLDO_REFTRIM_REFTRIM_SHIFT     (0U)
+/*! REFTRIM - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV. */
+#define SPC_SRAMRETLDO_REFTRIM_REFTRIM(x)        (((uint32_t)(((uint32_t)(x)) << SPC_SRAMRETLDO_REFTRIM_REFTRIM_SHIFT)) & SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK)
+/*! @} */
+
+/*! @name SRAMRETLDO_CNTRL - SRAM Retention LDO Control */
+/*! @{ */
+
+#define SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK     (0x1U)
+#define SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_SHIFT    (0U)
+/*! SRAMLDO_ON - SRAM LDO Regulator Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON(x)       (((uint32_t)(((uint32_t)(x)) << SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_SHIFT)) & SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK)
+
+#define SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_MASK    (0xF00U)
+#define SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_SHIFT   (8U)
+/*! SRAM_RET_EN - SRAM Retention */
+#define SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN(x)      (((uint32_t)(((uint32_t)(x)) << SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_SHIFT)) & SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_MASK)
+/*! @} */
+
+/*! @name HP_CNFG_CTRL - High Power Config Control */
+/*! @{ */
+
+#define SPC_HP_CNFG_CTRL_HP_REQ_EN_MASK          (0x1U)
+#define SPC_HP_CNFG_CTRL_HP_REQ_EN_SHIFT         (0U)
+/*! HP_REQ_EN - High Power Request Enable
+ *  0b0..High Power request Disable
+ *  0b1..High power reqeust Enable
+ */
+#define SPC_HP_CNFG_CTRL_HP_REQ_EN(x)            (((uint32_t)(((uint32_t)(x)) << SPC_HP_CNFG_CTRL_HP_REQ_EN_SHIFT)) & SPC_HP_CNFG_CTRL_HP_REQ_EN_MASK)
+
+#define SPC_HP_CNFG_CTRL_OVERRIDE_EN_MASK        (0x2U)
+#define SPC_HP_CNFG_CTRL_OVERRIDE_EN_SHIFT       (1U)
+/*! OVERRIDE_EN - Override Enable
+ *  0b0..Override Disabled
+ *  0b1..Override Enabled
+ */
+#define SPC_HP_CNFG_CTRL_OVERRIDE_EN(x)          (((uint32_t)(((uint32_t)(x)) << SPC_HP_CNFG_CTRL_OVERRIDE_EN_SHIFT)) & SPC_HP_CNFG_CTRL_OVERRIDE_EN_MASK)
+
+#define SPC_HP_CNFG_CTRL_OVERRIDE_SEL_MASK       (0x4U)
+#define SPC_HP_CNFG_CTRL_OVERRIDE_SEL_SHIFT      (2U)
+/*! OVERRIDE_SEL - Override Select
+ *  0b0..Force the HP request to 0
+ *  0b1..Force the HP request to 1
+ */
+#define SPC_HP_CNFG_CTRL_OVERRIDE_SEL(x)         (((uint32_t)(((uint32_t)(x)) << SPC_HP_CNFG_CTRL_OVERRIDE_SEL_SHIFT)) & SPC_HP_CNFG_CTRL_OVERRIDE_SEL_MASK)
+/*! @} */
+
+/*! @name ACTIVE_CFG - Active Power Mode Configuration */
+/*! @{ */
+
+#define SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK       (0x1U)
+#define SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT      (0U)
+/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength
+ *  0b0..Low
+ *  0b1..Normal
+ */
+#define SPC_ACTIVE_CFG_CORELDO_VDD_DS(x)         (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK)
+
+#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK      (0xCU)
+#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT     (2U)
+/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level
+ *  0b00..
+ *  0b01..Regulate to mid voltage (1 V)
+ *  0b10..Regulate to normal voltage (1.1 V)
+ *  0b11..Regulate to overdrive voltage (1.15 V)
+ */
+#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL(x)        (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK)
+
+#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U)
+#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U)
+/*! GLITCH_DETECT_DISABLE - Glitch Detect Disable
+ *  0b0..Low Voltage Glitch Detect enabled
+ *  0b1..Low Voltage Glitch Detect disabled
+ */
+#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE(x)  (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK)
+
+#define SPC_ACTIVE_CFG_BGMODE_MASK               (0x300000U)
+#define SPC_ACTIVE_CFG_BGMODE_SHIFT              (20U)
+/*! BGMODE - Bandgap Mode
+ *  0b00..Bandgap disabled
+ *  0b01..Bandgap enabled, buffer disabled
+ *  0b10..Bandgap enabled, buffer enabled
+ *  0b11..
+ */
+#define SPC_ACTIVE_CFG_BGMODE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_BGMODE_SHIFT)) & SPC_ACTIVE_CFG_BGMODE_MASK)
+
+#define SPC_ACTIVE_CFG_CORE_LVDE_MASK            (0x1000000U)
+#define SPC_ACTIVE_CFG_CORE_LVDE_SHIFT           (24U)
+/*! CORE_LVDE - Core Low-Voltage Detection Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_ACTIVE_CFG_CORE_LVDE(x)              (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_LVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_LVDE_MASK)
+
+#define SPC_ACTIVE_CFG_SYS_LVDE_MASK             (0x2000000U)
+#define SPC_ACTIVE_CFG_SYS_LVDE_SHIFT            (25U)
+/*! SYS_LVDE - System Low-Voltage Detection Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_ACTIVE_CFG_SYS_LVDE(x)               (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_LVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_LVDE_MASK)
+
+#define SPC_ACTIVE_CFG_SYS_HVDE_MASK             (0x10000000U)
+#define SPC_ACTIVE_CFG_SYS_HVDE_SHIFT            (28U)
+/*! SYS_HVDE - System High-Voltage Detection Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_ACTIVE_CFG_SYS_HVDE(x)               (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_HVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_HVDE_MASK)
+/*! @} */
+
+/*! @name ACTIVE_CFG1 - Active Power Mode Configuration 1 */
+/*! @{ */
+
+#define SPC_ACTIVE_CFG1_SOC_CNTRL_MASK           (0xFFFFFFFFU)
+#define SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT          (0U)
+/*! SOC_CNTRL - Active Config Chip Control */
+#define SPC_ACTIVE_CFG1_SOC_CNTRL(x)             (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT)) & SPC_ACTIVE_CFG1_SOC_CNTRL_MASK)
+/*! @} */
+
+/*! @name LP_CFG - Low-Power Mode Configuration */
+/*! @{ */
+
+#define SPC_LP_CFG_CORELDO_VDD_DS_MASK           (0x1U)
+#define SPC_LP_CFG_CORELDO_VDD_DS_SHIFT          (0U)
+/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength
+ *  0b0..Low
+ *  0b1..Normal
+ */
+#define SPC_LP_CFG_CORELDO_VDD_DS(x)             (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_DS_MASK)
+
+#define SPC_LP_CFG_CORELDO_VDD_LVL_MASK          (0xCU)
+#define SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT         (2U)
+/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level
+ *  0b00..Reserved
+ *  0b01..Mid voltage (1 V)
+ *  0b10..Normal voltage (1.1 V)
+ *  0b11..Overdrive voltage (1.15 V)
+ */
+#define SPC_LP_CFG_CORELDO_VDD_LVL(x)            (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_LVL_MASK)
+
+#define SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK    (0x1000U)
+#define SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT   (12U)
+/*! GLITCH_DETECT_DISABLE - Glitch Detect Disable
+ *  0b0..Enable
+ *  0b1..Disable
+ */
+#define SPC_LP_CFG_GLITCH_DETECT_DISABLE(x)      (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK)
+
+#define SPC_LP_CFG_SRAMLDO_DPD_ON_MASK           (0x80000U)
+#define SPC_LP_CFG_SRAMLDO_DPD_ON_SHIFT          (19U)
+/*! SRAMLDO_DPD_ON - SRAM_LDO Deep Power Low Power IREF Enable
+ *  0b0..Low Power IREF is disabled for power saving in Deep Power Down mode
+ *  0b1..Low Power IREF is enabled
+ */
+#define SPC_LP_CFG_SRAMLDO_DPD_ON(x)             (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SRAMLDO_DPD_ON_SHIFT)) & SPC_LP_CFG_SRAMLDO_DPD_ON_MASK)
+
+#define SPC_LP_CFG_BGMODE_MASK                   (0x300000U)
+#define SPC_LP_CFG_BGMODE_SHIFT                  (20U)
+/*! BGMODE - Bandgap Mode
+ *  0b00..Bandgap disabled
+ *  0b01..Bandgap enabled, buffer disabled
+ *  0b10..Bandgap enabled, buffer enabled
+ *  0b11..
+ */
+#define SPC_LP_CFG_BGMODE(x)                     (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_BGMODE_SHIFT)) & SPC_LP_CFG_BGMODE_MASK)
+
+#define SPC_LP_CFG_LP_IREFEN_MASK                (0x800000U)
+#define SPC_LP_CFG_LP_IREFEN_SHIFT               (23U)
+/*! LP_IREFEN - Low-Power IREF Enable
+ *  0b0..Disable for power saving in Deep Power Down mode
+ *  0b1..Enable
+ */
+#define SPC_LP_CFG_LP_IREFEN(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LP_IREFEN_SHIFT)) & SPC_LP_CFG_LP_IREFEN_MASK)
+
+#define SPC_LP_CFG_CORE_LVDE_MASK                (0x1000000U)
+#define SPC_LP_CFG_CORE_LVDE_SHIFT               (24U)
+/*! CORE_LVDE - Core Low Voltage Detect Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_LP_CFG_CORE_LVDE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_LVDE_SHIFT)) & SPC_LP_CFG_CORE_LVDE_MASK)
+
+#define SPC_LP_CFG_SYS_LVDE_MASK                 (0x2000000U)
+#define SPC_LP_CFG_SYS_LVDE_SHIFT                (25U)
+/*! SYS_LVDE - System Low Voltage Detect Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_LP_CFG_SYS_LVDE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_LVDE_SHIFT)) & SPC_LP_CFG_SYS_LVDE_MASK)
+
+#define SPC_LP_CFG_SYS_HVDE_MASK                 (0x10000000U)
+#define SPC_LP_CFG_SYS_HVDE_SHIFT                (28U)
+/*! SYS_HVDE - System High Voltage Detect Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_LP_CFG_SYS_HVDE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_HVDE_SHIFT)) & SPC_LP_CFG_SYS_HVDE_MASK)
+/*! @} */
+
+/*! @name LP_CFG1 - Low Power Mode Configuration 1 */
+/*! @{ */
+
+#define SPC_LP_CFG1_SOC_CNTRL_MASK               (0xFFFFFFFFU)
+#define SPC_LP_CFG1_SOC_CNTRL_SHIFT              (0U)
+/*! SOC_CNTRL - Low-Power Configuration Chip Control */
+#define SPC_LP_CFG1_SOC_CNTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG1_SOC_CNTRL_SHIFT)) & SPC_LP_CFG1_SOC_CNTRL_MASK)
+/*! @} */
+
+/*! @name HP_CFG - High Power Mode Configuration */
+/*! @{ */
+
+#define SPC_HP_CFG_CORELDO_VDD_DS_MASK           (0x1U)
+#define SPC_HP_CFG_CORELDO_VDD_DS_SHIFT          (0U)
+/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength
+ *  0b0..Low
+ *  0b1..Normal
+ */
+#define SPC_HP_CFG_CORELDO_VDD_DS(x)             (((uint32_t)(((uint32_t)(x)) << SPC_HP_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_HP_CFG_CORELDO_VDD_DS_MASK)
+
+#define SPC_HP_CFG_CORELDO_VDD_LVL_MASK          (0xCU)
+#define SPC_HP_CFG_CORELDO_VDD_LVL_SHIFT         (2U)
+/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level
+ *  0b00..
+ *  0b01..Regulate to mid voltage (1 V)
+ *  0b10..Regulate to normal voltage (1.1 V)
+ *  0b11..Regulate to overdrive voltage (1.15 V)
+ */
+#define SPC_HP_CFG_CORELDO_VDD_LVL(x)            (((uint32_t)(((uint32_t)(x)) << SPC_HP_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_HP_CFG_CORELDO_VDD_LVL_MASK)
+
+#define SPC_HP_CFG_GLITCH_DETECT_DISABLE_MASK    (0x1000U)
+#define SPC_HP_CFG_GLITCH_DETECT_DISABLE_SHIFT   (12U)
+/*! GLITCH_DETECT_DISABLE - VDD Core Glitch Detect Disable
+ *  0b0..VDD Core Low Voltage Glitch Detect enabled
+ *  0b1..VDD Core Low Voltage Glitch Detect disabled
+ */
+#define SPC_HP_CFG_GLITCH_DETECT_DISABLE(x)      (((uint32_t)(((uint32_t)(x)) << SPC_HP_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_HP_CFG_GLITCH_DETECT_DISABLE_MASK)
+
+#define SPC_HP_CFG_BGMODE_MASK                   (0x300000U)
+#define SPC_HP_CFG_BGMODE_SHIFT                  (20U)
+/*! BGMODE - Bandgap Mode
+ *  0b00..Bandgap disabled
+ *  0b01..Bandgap enabled, buffer disabled
+ *  0b10..Bandgap enabled, buffer enabled
+ *  0b11..
+ */
+#define SPC_HP_CFG_BGMODE(x)                     (((uint32_t)(((uint32_t)(x)) << SPC_HP_CFG_BGMODE_SHIFT)) & SPC_HP_CFG_BGMODE_MASK)
+
+#define SPC_HP_CFG_CORE_LVDE_MASK                (0x1000000U)
+#define SPC_HP_CFG_CORE_LVDE_SHIFT               (24U)
+/*! CORE_LVDE - Core Low-Voltage Detection Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_HP_CFG_CORE_LVDE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_HP_CFG_CORE_LVDE_SHIFT)) & SPC_HP_CFG_CORE_LVDE_MASK)
+
+#define SPC_HP_CFG_SYS_LVDE_MASK                 (0x2000000U)
+#define SPC_HP_CFG_SYS_LVDE_SHIFT                (25U)
+/*! SYS_LVDE - System Low-Voltage Detection Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_HP_CFG_SYS_LVDE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_HP_CFG_SYS_LVDE_SHIFT)) & SPC_HP_CFG_SYS_LVDE_MASK)
+
+#define SPC_HP_CFG_SYS_HVDE_MASK                 (0x10000000U)
+#define SPC_HP_CFG_SYS_HVDE_SHIFT                (28U)
+/*! SYS_HVDE - System High-Voltage Detection Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_HP_CFG_SYS_HVDE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_HP_CFG_SYS_HVDE_SHIFT)) & SPC_HP_CFG_SYS_HVDE_MASK)
+/*! @} */
+
+/*! @name LPWKUP_DELAY - Low Power Wake-Up Delay */
+/*! @{ */
+
+#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK       (0xFFFFU)
+#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT      (0U)
+/*! LPWKUP_DELAY - Low-Power Wake-Up Delay */
+#define SPC_LPWKUP_DELAY_LPWKUP_DELAY(x)         (((uint32_t)(((uint32_t)(x)) << SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT)) & SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK)
+/*! @} */
+
+/*! @name ACTIVE_VDELAY - Active Voltage Trim Delay */
+/*! @{ */
+
+#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK     (0xFFFFU)
+#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT    (0U)
+/*! ACTIVE_VDELAY - Active Voltage Delay */
+#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(x)       (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT)) & SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK)
+/*! @} */
+
+/*! @name VD_STAT - Voltage Detect Status */
+/*! @{ */
+
+#define SPC_VD_STAT_COREVDD_LVDF_MASK            (0x1U)
+#define SPC_VD_STAT_COREVDD_LVDF_SHIFT           (0U)
+/*! COREVDD_LVDF - Core Low-Voltage Detect Flag
+ *  0b0..Event not detected
+ *  0b0..No effect
+ *  0b1..Clear the flag
+ *  0b1..Event detected
+ */
+#define SPC_VD_STAT_COREVDD_LVDF(x)              (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_LVDF_SHIFT)) & SPC_VD_STAT_COREVDD_LVDF_MASK)
+
+#define SPC_VD_STAT_SYSVDD_LVDF_MASK             (0x2U)
+#define SPC_VD_STAT_SYSVDD_LVDF_SHIFT            (1U)
+/*! SYSVDD_LVDF - System Low-Voltage Detect Flag
+ *  0b0..Event not detected
+ *  0b0..No effect
+ *  0b1..Clear the flag
+ *  0b1..Event detected
+ */
+#define SPC_VD_STAT_SYSVDD_LVDF(x)               (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_LVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_LVDF_MASK)
+
+#define SPC_VD_STAT_SYSVDD_HVDF_MASK             (0x20U)
+#define SPC_VD_STAT_SYSVDD_HVDF_SHIFT            (5U)
+/*! SYSVDD_HVDF - System HVD Flag
+ *  0b0..Event not detected
+ *  0b0..No effect
+ *  0b1..Clear the flag
+ *  0b1..Event detected
+ */
+#define SPC_VD_STAT_SYSVDD_HVDF(x)               (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_HVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_HVDF_MASK)
+/*! @} */
+
+/*! @name VD_CORE_CFG - Core Voltage Detect Configuration */
+/*! @{ */
+
+#define SPC_VD_CORE_CFG_LVDRE_MASK               (0x1U)
+#define SPC_VD_CORE_CFG_LVDRE_SHIFT              (0U)
+/*! LVDRE - Core LVD Reset Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_VD_CORE_CFG_LVDRE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDRE_SHIFT)) & SPC_VD_CORE_CFG_LVDRE_MASK)
+
+#define SPC_VD_CORE_CFG_LVDIE_MASK               (0x2U)
+#define SPC_VD_CORE_CFG_LVDIE_SHIFT              (1U)
+/*! LVDIE - Core LVD Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_VD_CORE_CFG_LVDIE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDIE_SHIFT)) & SPC_VD_CORE_CFG_LVDIE_MASK)
+
+#define SPC_VD_CORE_CFG_LOCK_MASK                (0x10000U)
+#define SPC_VD_CORE_CFG_LOCK_SHIFT               (16U)
+/*! LOCK - Core Voltage Detect Reset Enable Lock
+ *  0b0..Allow
+ *  0b1..Deny
+ */
+#define SPC_VD_CORE_CFG_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LOCK_SHIFT)) & SPC_VD_CORE_CFG_LOCK_MASK)
+/*! @} */
+
+/*! @name VD_SYS_CFG - System Voltage Detect Configuration */
+/*! @{ */
+
+#define SPC_VD_SYS_CFG_LVDRE_MASK                (0x1U)
+#define SPC_VD_SYS_CFG_LVDRE_SHIFT               (0U)
+/*! LVDRE - System LVD Reset Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_VD_SYS_CFG_LVDRE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDRE_SHIFT)) & SPC_VD_SYS_CFG_LVDRE_MASK)
+
+#define SPC_VD_SYS_CFG_LVDIE_MASK                (0x2U)
+#define SPC_VD_SYS_CFG_LVDIE_SHIFT               (1U)
+/*! LVDIE - System LVD Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_VD_SYS_CFG_LVDIE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDIE_SHIFT)) & SPC_VD_SYS_CFG_LVDIE_MASK)
+
+#define SPC_VD_SYS_CFG_HVDRE_MASK                (0x4U)
+#define SPC_VD_SYS_CFG_HVDRE_SHIFT               (2U)
+/*! HVDRE - System HVD Reset Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_VD_SYS_CFG_HVDRE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDRE_SHIFT)) & SPC_VD_SYS_CFG_HVDRE_MASK)
+
+#define SPC_VD_SYS_CFG_HVDIE_MASK                (0x8U)
+#define SPC_VD_SYS_CFG_HVDIE_SHIFT               (3U)
+/*! HVDIE - System HVD Interrupt Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SPC_VD_SYS_CFG_HVDIE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDIE_SHIFT)) & SPC_VD_SYS_CFG_HVDIE_MASK)
+
+#define SPC_VD_SYS_CFG_LVSEL_MASK                (0x100U)
+#define SPC_VD_SYS_CFG_LVSEL_SHIFT               (8U)
+/*! LVSEL - System Low-Voltage Level Select
+ *  0b0..Normal
+ *  0b1..Safe
+ */
+#define SPC_VD_SYS_CFG_LVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVSEL_SHIFT)) & SPC_VD_SYS_CFG_LVSEL_MASK)
+
+#define SPC_VD_SYS_CFG_LOCK_MASK                 (0x10000U)
+#define SPC_VD_SYS_CFG_LOCK_SHIFT                (16U)
+/*! LOCK - System Voltage Detect Reset Enable Lock
+ *  0b0..Allow
+ *  0b1..Deny
+ */
+#define SPC_VD_SYS_CFG_LOCK(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LOCK_SHIFT)) & SPC_VD_SYS_CFG_LOCK_MASK)
+/*! @} */
+
+/*! @name EVD_CFG - External Voltage Domain Configuration */
+/*! @{ */
+
+#define SPC_EVD_CFG_EVDISO_MASK                  (0x7U)
+#define SPC_EVD_CFG_EVDISO_SHIFT                 (0U)
+/*! EVDISO - External Voltage Domain Isolation */
+#define SPC_EVD_CFG_EVDISO(x)                    (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDISO_SHIFT)) & SPC_EVD_CFG_EVDISO_MASK)
+
+#define SPC_EVD_CFG_EVDLPISO_MASK                (0x700U)
+#define SPC_EVD_CFG_EVDLPISO_SHIFT               (8U)
+/*! EVDLPISO - External Voltage Domain Low-Power Isolation */
+#define SPC_EVD_CFG_EVDLPISO(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDLPISO_SHIFT)) & SPC_EVD_CFG_EVDLPISO_MASK)
+
+#define SPC_EVD_CFG_EVDSTAT_MASK                 (0x70000U)
+#define SPC_EVD_CFG_EVDSTAT_SHIFT                (16U)
+/*! EVDSTAT - External Voltage Domain Status */
+#define SPC_EVD_CFG_EVDSTAT(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDSTAT_SHIFT)) & SPC_EVD_CFG_EVDSTAT_MASK)
+/*! @} */
+
+/*! @name GLITCH_DETECT_SC - Glitch Detect Status Control */
+/*! @{ */
+
+#define SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK     (0x3U)
+#define SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT    (0U)
+/*! CNT_SELECT - Counter Select
+ *  0b00..0
+ *  0b01..1
+ *  0b10..2
+ *  0b11..3
+ */
+#define SPC_GLITCH_DETECT_SC_CNT_SELECT(x)       (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT)) & SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK)
+
+#define SPC_GLITCH_DETECT_SC_TIMEOUT_MASK        (0x3CU)
+#define SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT       (2U)
+/*! TIMEOUT - Timeout */
+#define SPC_GLITCH_DETECT_SC_TIMEOUT(x)          (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT)) & SPC_GLITCH_DETECT_SC_TIMEOUT_MASK)
+
+#define SPC_GLITCH_DETECT_SC_RE_MASK             (0x40U)
+#define SPC_GLITCH_DETECT_SC_RE_SHIFT            (6U)
+/*! RE - Glitch Detect Reset Enable
+ *  0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate POR/LVD reset
+ *  0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate POR/LVD reset
+ */
+#define SPC_GLITCH_DETECT_SC_RE(x)               (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_RE_SHIFT)) & SPC_GLITCH_DETECT_SC_RE_MASK)
+
+#define SPC_GLITCH_DETECT_SC_IE_MASK             (0x80U)
+#define SPC_GLITCH_DETECT_SC_IE_SHIFT            (7U)
+/*! IE - Glitch Detect Interrupt Enable
+ *  0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate hardware interrupt (user polling)
+ *  0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate hardware interrupt
+ */
+#define SPC_GLITCH_DETECT_SC_IE(x)               (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_IE_SHIFT)) & SPC_GLITCH_DETECT_SC_IE_MASK)
+
+#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK (0xF00U)
+#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT (8U)
+/*! GLITCH_DETECT_FLAG - GLITCH_DETECT_FLAG */
+#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT)) & SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK)
+
+#define SPC_GLITCH_DETECT_SC_LOCK_MASK           (0x10000U)
+#define SPC_GLITCH_DETECT_SC_LOCK_SHIFT          (16U)
+/*! LOCK - Glitch Detect Reset Enable Lock Bit
+ *  0b0..Writes to RE are allowed.
+ *  0b1..Writes to RE are ignored.
+ */
+#define SPC_GLITCH_DETECT_SC_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_LOCK_SHIFT)) & SPC_GLITCH_DETECT_SC_LOCK_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SPC_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group SPC_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_SPC_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SYSCON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SYSCON.h
new file mode 100644
index 0000000000..a8fb762b76
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SYSCON.h
@@ -0,0 +1,1337 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for SYSCON
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_SYSCON.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for SYSCON
+ *
+ * CMSIS Peripheral Access Layer for SYSCON
+ */
+
+#if !defined(PERI_SYSCON_H_)
+#define PERI_SYSCON_H_                           /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- SYSCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** SYSCON - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[512];
+  __IO uint32_t REMAP;                             /**< AHB Matrix Remap Control, offset: 0x200 */
+       uint8_t RESERVED_1[12];
+  __IO uint32_t AHBMATPRIO;                        /**< AHB Matrix Priority Control, offset: 0x210 */
+       uint8_t RESERVED_2[40];
+  __IO uint32_t CPU0NSTCKCAL;                      /**< Non-Secure CPU0 System Tick Calibration, offset: 0x23C */
+       uint8_t RESERVED_3[8];
+  __IO uint32_t NMISRC;                            /**< NMI Source Select, offset: 0x248 */
+  __IO uint32_t PROTLVL;                           /**< Protect Level Control, offset: 0x24C */
+       uint8_t RESERVED_4[296];
+  __IO uint32_t SLOWCLKDIV;                        /**< SLOW_CLK Clock Divider, offset: 0x378 */
+  __IO uint32_t BUSCLKDIV;                         /**< BUS_CLK Clock Divider, offset: 0x37C */
+  __IO uint32_t AHBCLKDIV;                         /**< System Clock Divider, offset: 0x380 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t FROHFDIV;                          /**< FRO_HF_DIV Clock Divider, offset: 0x388 */
+  __IO uint32_t FROLFDIV;                          /**< FRO_LF_DIV Clock Divider, offset: 0x38C */
+       uint8_t RESERVED_6[108];
+  __IO uint32_t CLKUNLOCK;                         /**< Clock Configuration Unlock, offset: 0x3FC */
+  __IO uint32_t NVM_CTRL;                          /**< NVM Control, offset: 0x400 */
+       uint8_t RESERVED_7[16];
+  __IO uint32_t SMARTDMAINT;                       /**< SmartDMA Interrupt Hijack, offset: 0x414 */
+       uint8_t RESERVED_8[1012];
+  __I  uint32_t CPUSTAT;                           /**< CPU Status, offset: 0x80C */
+       uint8_t RESERVED_9[20];
+  __IO uint32_t LPCAC_CTRL;                        /**< LPCAC Control, offset: 0x824 */
+       uint8_t RESERVED_10[272];
+  __IO uint32_t PWM0SUBCTL;                        /**< PWM0 Submodule Control, offset: 0x938 */
+  __IO uint32_t PWM1SUBCTL;                        /**< PWM1 Submodule Control, offset: 0x93C */
+  __IO uint32_t CTIMERGLOBALSTARTEN;               /**< CTIMER Global Start Enable, offset: 0x940 */
+  __IO uint32_t RAM_CTRL;                          /**< RAM Control, offset: 0x944 */
+       uint8_t RESERVED_11[536];
+  __IO uint32_t GRAY_CODE_LSB;                     /**< Gray to Binary Converter Gray Code [31:0], offset: 0xB60 */
+  __IO uint32_t GRAY_CODE_MSB;                     /**< Gray to Binary Converter Gray Code [41:32], offset: 0xB64 */
+  __I  uint32_t BINARY_CODE_LSB;                   /**< Gray to Binary Converter Binary Code [31:0], offset: 0xB68 */
+  __I  uint32_t BINARY_CODE_MSB;                   /**< Gray to Binary Converter Binary Code [41:32], offset: 0xB6C */
+       uint8_t RESERVED_12[684];
+  __IO uint32_t MSFCFG;                            /**< MSF Configuration, offset: 0xE1C */
+       uint8_t RESERVED_13[28];
+  __I  uint32_t ROP_STATE;                         /**< ROP State Register, offset: 0xE3C */
+       uint8_t RESERVED_14[24];
+  __IO uint32_t SRAM_XEN;                          /**< RAM XEN Control, offset: 0xE58 */
+  __IO uint32_t SRAM_XEN_DP;                       /**< RAM XEN Control (Duplicate), offset: 0xE5C */
+       uint8_t RESERVED_15[32];
+  __I  uint32_t ELS_OTP_LC_STATE;                  /**< Life Cycle State Register, offset: 0xE80 */
+  __I  uint32_t ELS_OTP_LC_STATE_DP;               /**< Life Cycle State Register (Duplicate), offset: 0xE84 */
+       uint8_t RESERVED_16[280];
+  __IO uint32_t DEBUG_LOCK_EN;                     /**< Control Write Access to Security, offset: 0xFA0 */
+  __IO uint32_t DEBUG_FEATURES;                    /**< Cortex Debug Features Control, offset: 0xFA4 */
+  __IO uint32_t DEBUG_FEATURES_DP;                 /**< Cortex Debug Features Control (Duplicate), offset: 0xFA8 */
+       uint8_t RESERVED_17[8];
+  __IO uint32_t SWD_ACCESS_CPU0;                   /**< CPU0 Software Debug Access, offset: 0xFB4 */
+       uint8_t RESERVED_18[8];
+  __IO uint32_t DEBUG_AUTH_BEACON;                 /**< Debug Authentication BEACON, offset: 0xFC0 */
+       uint8_t RESERVED_19[44];
+  __I  uint32_t JTAG_ID;                           /**< JTAG Chip ID, offset: 0xFF0 */
+  __I  uint32_t DEVICE_TYPE;                       /**< Device Type, offset: 0xFF4 */
+  __I  uint32_t DEVICE_ID0;                        /**< Device ID, offset: 0xFF8 */
+} SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SYSCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
+ * @{
+ */
+
+/*! @name REMAP - AHB Matrix Remap Control */
+/*! @{ */
+
+#define SYSCON_REMAP_CPU0_SBUS_MASK              (0xCU)
+#define SYSCON_REMAP_CPU0_SBUS_SHIFT             (2U)
+/*! CPU0_SBUS - RAMX0 address remap for CPU System bus
+ *  0b00..RAMX0: alias space is disabled.
+ *  0b01..RAMX0: alias space is enabled. It's linear address space from bottom of system ram. The start address is
+ *        0x20000000 + (system ram size - RAMX size)*1024.
+ */
+#define SYSCON_REMAP_CPU0_SBUS(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_CPU0_SBUS_SHIFT)) & SYSCON_REMAP_CPU0_SBUS_MASK)
+
+#define SYSCON_REMAP_SMARTDMA_I_MASK             (0x30U)
+#define SYSCON_REMAP_SMARTDMA_I_SHIFT            (4U)
+/*! SmartDMA_I - RAMX0 address remap for SmartDMA I-BUS
+ *  0b00..RAMX0: alias space is disabled.
+ *  0b01..RAMX0: same alias space as CPU0_SBUS
+ */
+#define SYSCON_REMAP_SMARTDMA_I(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_SMARTDMA_I_SHIFT)) & SYSCON_REMAP_SMARTDMA_I_MASK)
+
+#define SYSCON_REMAP_SMARTDMA_D_MASK             (0xC0U)
+#define SYSCON_REMAP_SMARTDMA_D_SHIFT            (6U)
+/*! SmartDMA_D - RAMX0 address remap for SmartDMA D-BUS
+ *  0b00..RAMX0: alias space is disabled.
+ *  0b01..RAMX0: same alias space as CPU0_SBUS
+ */
+#define SYSCON_REMAP_SMARTDMA_D(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_SMARTDMA_D_SHIFT)) & SYSCON_REMAP_SMARTDMA_D_MASK)
+
+#define SYSCON_REMAP_DMA0_MASK                   (0x300U)
+#define SYSCON_REMAP_DMA0_SHIFT                  (8U)
+/*! DMA0 - RAMX0 address remap for DMA0
+ *  0b00..RAMX0: alias space is disabled.
+ *  0b01..RAMX0: same alias space as CPU0_SBUS
+ */
+#define SYSCON_REMAP_DMA0(x)                     (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_DMA0_SHIFT)) & SYSCON_REMAP_DMA0_MASK)
+
+#define SYSCON_REMAP_LOCK_MASK                   (0x80000000U)
+#define SYSCON_REMAP_LOCK_SHIFT                  (31U)
+/*! LOCK - This 1-bit field provides a mechanism to limit writes to this register to protect its
+ *    contents. Once set, this bit remains asserted until a system reset.
+ *  0b0..This register is not locked and can be altered.
+ *  0b1..This register is locked and cannot be altered until a system reset.
+ */
+#define SYSCON_REMAP_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_LOCK_SHIFT)) & SYSCON_REMAP_LOCK_MASK)
+/*! @} */
+
+/*! @name AHBMATPRIO - AHB Matrix Priority Control */
+/*! @{ */
+
+#define SYSCON_AHBMATPRIO_CPU0_CBUS_MASK         (0x3U)
+#define SYSCON_AHBMATPRIO_CPU0_CBUS_SHIFT        (0U)
+/*! CPU0_CBUS - CPU0 C-AHB bus master priority level
+ *  0b00..level 0
+ *  0b01..level 1
+ *  0b10..level 2
+ *  0b11..level 3
+ */
+#define SYSCON_AHBMATPRIO_CPU0_CBUS(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_CPU0_CBUS_MASK)
+
+#define SYSCON_AHBMATPRIO_CPU0_SBUS_MASK         (0xCU)
+#define SYSCON_AHBMATPRIO_CPU0_SBUS_SHIFT        (2U)
+/*! CPU0_SBUS - CPU0 S-AHB bus master priority level
+ *  0b00..level 0
+ *  0b01..level 1
+ *  0b10..level 2
+ *  0b11..level 3
+ */
+#define SYSCON_AHBMATPRIO_CPU0_SBUS(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_CPU0_SBUS_MASK)
+
+#define SYSCON_AHBMATPRIO_CPU1_CBUS_SMARTDMA_I_MASK (0x30U)
+#define SYSCON_AHBMATPRIO_CPU1_CBUS_SMARTDMA_I_SHIFT (4U)
+/*! CPU1_CBUS_SmartDMA_I - SmartDMA-I bus master priority level
+ *  0b00..level 0
+ *  0b01..level 1
+ *  0b10..level 2
+ *  0b11..level 3
+ */
+#define SYSCON_AHBMATPRIO_CPU1_CBUS_SMARTDMA_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_CPU1_CBUS_SMARTDMA_I_SHIFT)) & SYSCON_AHBMATPRIO_CPU1_CBUS_SMARTDMA_I_MASK)
+
+#define SYSCON_AHBMATPRIO_CPU1_SBUS_SMARTDMA_D_MASK (0xC0U)
+#define SYSCON_AHBMATPRIO_CPU1_SBUS_SMARTDMA_D_SHIFT (6U)
+/*! CPU1_SBUS_SmartDMA_D - SmartDMA-D bus master priority level
+ *  0b00..level 0
+ *  0b01..level 1
+ *  0b10..level 2
+ *  0b11..level 3
+ */
+#define SYSCON_AHBMATPRIO_CPU1_SBUS_SMARTDMA_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_CPU1_SBUS_SMARTDMA_D_SHIFT)) & SYSCON_AHBMATPRIO_CPU1_SBUS_SMARTDMA_D_MASK)
+
+#define SYSCON_AHBMATPRIO_DMA0_MASK              (0x300U)
+#define SYSCON_AHBMATPRIO_DMA0_SHIFT             (8U)
+/*! DMA0 - DMA0 controller bus master priority level
+ *  0b00..level 0
+ *  0b01..level 1
+ *  0b10..level 2
+ *  0b11..level 3
+ */
+#define SYSCON_AHBMATPRIO_DMA0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_DMA0_SHIFT)) & SYSCON_AHBMATPRIO_DMA0_MASK)
+/*! @} */
+
+/*! @name CPU0NSTCKCAL - Non-Secure CPU0 System Tick Calibration */
+/*! @{ */
+
+#define SYSCON_CPU0NSTCKCAL_TENMS_MASK           (0xFFFFFFU)
+#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT          (0U)
+/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the
+ *    value reads as zero, the calibration value is not known.
+ */
+#define SYSCON_CPU0NSTCKCAL_TENMS(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK)
+
+#define SYSCON_CPU0NSTCKCAL_SKEW_MASK            (0x1000000U)
+#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT           (24U)
+/*! SKEW - Indicates whether the TENMS value is exact.
+ *  0b0..TENMS value is exact
+ *  0b1..TENMS value is not exact or not given
+ */
+#define SYSCON_CPU0NSTCKCAL_SKEW(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK)
+
+#define SYSCON_CPU0NSTCKCAL_NOREF_MASK           (0x2000000U)
+#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT          (25U)
+/*! NOREF - Indicates whether the device provides a reference clock to the processor.
+ *  0b0..Reference clock is provided
+ *  0b1..No reference clock is provided
+ */
+#define SYSCON_CPU0NSTCKCAL_NOREF(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK)
+/*! @} */
+
+/*! @name NMISRC - NMI Source Select */
+/*! @{ */
+
+#define SYSCON_NMISRC_IRQCPU0_MASK               (0xFFU)
+#define SYSCON_NMISRC_IRQCPU0_SHIFT              (0U)
+/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0. */
+#define SYSCON_NMISRC_IRQCPU0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK)
+
+#define SYSCON_NMISRC_NMIENCPU0_MASK             (0x80000000U)
+#define SYSCON_NMISRC_NMIENCPU0_SHIFT            (31U)
+/*! NMIENCPU0 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0.
+ *  0b0..Disable.
+ *  0b1..Enable.
+ */
+#define SYSCON_NMISRC_NMIENCPU0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK)
+/*! @} */
+
+/*! @name PROTLVL - Protect Level Control */
+/*! @{ */
+
+#define SYSCON_PROTLVL_PRIV_MASK                 (0x1U)
+#define SYSCON_PROTLVL_PRIV_SHIFT                (0U)
+/*! PRIV - Control privileged access of EIM, ERM, Flexcan, MBC, SCG.
+ *  0b0..privileged access is disabled. the peripherals could be access in user mode.
+ *  0b1..privileged access is enabled. the peripherals could be access in privilege mode.
+ */
+#define SYSCON_PROTLVL_PRIV(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_PROTLVL_PRIV_SHIFT)) & SYSCON_PROTLVL_PRIV_MASK)
+
+#define SYSCON_PROTLVL_LOCKNSMPU_MASK            (0x10000U)
+#define SYSCON_PROTLVL_LOCKNSMPU_SHIFT           (16U)
+/*! LOCKNSMPU - Control write access to Nonsecure MPU memory regions.
+ *  0b0..Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed.
+ *  0b1..Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and
+ *       MPU_RLAR_A_NSn. All writes to the registers are ignored.
+ */
+#define SYSCON_PROTLVL_LOCKNSMPU(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PROTLVL_LOCKNSMPU_SHIFT)) & SYSCON_PROTLVL_LOCKNSMPU_MASK)
+
+#define SYSCON_PROTLVL_LOCK_MASK                 (0x80000000U)
+#define SYSCON_PROTLVL_LOCK_SHIFT                (31U)
+/*! LOCK - This 1-bit field provides a mechanism to limit writes to this register to protect its
+ *    contents. Once set, this bit remains asserted until a system reset.
+ *  0b0..This register is not locked and can be altered.
+ *  0b1..This register is locked and cannot be altered until a system reset.
+ */
+#define SYSCON_PROTLVL_LOCK(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_PROTLVL_LOCK_SHIFT)) & SYSCON_PROTLVL_LOCK_MASK)
+/*! @} */
+
+/*! @name SLOWCLKDIV - SLOW_CLK Clock Divider */
+/*! @{ */
+
+#define SYSCON_SLOWCLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_SLOWCLKDIV_DIV_SHIFT              (0U)
+/*! DIV - Clock divider value */
+#define SYSCON_SLOWCLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_DIV_SHIFT)) & SYSCON_SLOWCLKDIV_DIV_MASK)
+
+#define SYSCON_SLOWCLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_SLOWCLKDIV_RESET_SHIFT            (29U)
+/*! RESET - Resets the divider counter
+ *  0b0..Divider is not reset
+ *  0b1..Divider is reset
+ */
+#define SYSCON_SLOWCLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_RESET_SHIFT)) & SYSCON_SLOWCLKDIV_RESET_MASK)
+
+#define SYSCON_SLOWCLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_SLOWCLKDIV_HALT_SHIFT             (30U)
+/*! HALT - Halts the divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define SYSCON_SLOWCLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_HALT_SHIFT)) & SYSCON_SLOWCLKDIV_HALT_MASK)
+
+#define SYSCON_SLOWCLKDIV_UNSTAB_MASK            (0x80000000U)
+#define SYSCON_SLOWCLKDIV_UNSTAB_SHIFT           (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency is not stable
+ */
+#define SYSCON_SLOWCLKDIV_UNSTAB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_UNSTAB_SHIFT)) & SYSCON_SLOWCLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name BUSCLKDIV - BUS_CLK Clock Divider */
+/*! @{ */
+
+#define SYSCON_BUSCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_BUSCLKDIV_DIV_SHIFT               (0U)
+/*! DIV - Clock divider value */
+#define SYSCON_BUSCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_BUSCLKDIV_DIV_SHIFT)) & SYSCON_BUSCLKDIV_DIV_MASK)
+
+#define SYSCON_BUSCLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_BUSCLKDIV_RESET_SHIFT             (29U)
+/*! RESET - Resets the divider counter
+ *  0b0..Divider is not reset
+ *  0b1..Divider is reset
+ */
+#define SYSCON_BUSCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_BUSCLKDIV_RESET_SHIFT)) & SYSCON_BUSCLKDIV_RESET_MASK)
+
+#define SYSCON_BUSCLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_BUSCLKDIV_HALT_SHIFT              (30U)
+/*! HALT - Halts the divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define SYSCON_BUSCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_BUSCLKDIV_HALT_SHIFT)) & SYSCON_BUSCLKDIV_HALT_MASK)
+
+#define SYSCON_BUSCLKDIV_UNSTAB_MASK             (0x80000000U)
+#define SYSCON_BUSCLKDIV_UNSTAB_SHIFT            (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency is not stable
+ */
+#define SYSCON_BUSCLKDIV_UNSTAB(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_BUSCLKDIV_UNSTAB_SHIFT)) & SYSCON_BUSCLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name AHBCLKDIV - System Clock Divider */
+/*! @{ */
+
+#define SYSCON_AHBCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_AHBCLKDIV_DIV_SHIFT               (0U)
+/*! DIV - Clock divider value */
+#define SYSCON_AHBCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
+
+#define SYSCON_AHBCLKDIV_UNSTAB_MASK             (0x80000000U)
+#define SYSCON_AHBCLKDIV_UNSTAB_SHIFT            (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency is not stable
+ */
+#define SYSCON_AHBCLKDIV_UNSTAB(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_UNSTAB_SHIFT)) & SYSCON_AHBCLKDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name FROHFDIV - FRO_HF_DIV Clock Divider */
+/*! @{ */
+
+#define SYSCON_FROHFDIV_DIV_MASK                 (0xFFU)
+#define SYSCON_FROHFDIV_DIV_SHIFT                (0U)
+/*! DIV - Clock divider value */
+#define SYSCON_FROHFDIV_DIV(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK)
+
+#define SYSCON_FROHFDIV_RESET_MASK               (0x20000000U)
+#define SYSCON_FROHFDIV_RESET_SHIFT              (29U)
+/*! RESET - Resets the divider counter
+ *  0b0..Divider is not reset
+ *  0b1..Divider is reset
+ */
+#define SYSCON_FROHFDIV_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK)
+
+#define SYSCON_FROHFDIV_HALT_MASK                (0x40000000U)
+#define SYSCON_FROHFDIV_HALT_SHIFT               (30U)
+/*! HALT - Halts the divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define SYSCON_FROHFDIV_HALT(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK)
+
+#define SYSCON_FROHFDIV_UNSTAB_MASK              (0x80000000U)
+#define SYSCON_FROHFDIV_UNSTAB_SHIFT             (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency is not stable
+ */
+#define SYSCON_FROHFDIV_UNSTAB(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_UNSTAB_SHIFT)) & SYSCON_FROHFDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name FROLFDIV - FRO_LF_DIV Clock Divider */
+/*! @{ */
+
+#define SYSCON_FROLFDIV_DIV_MASK                 (0xFFU)
+#define SYSCON_FROLFDIV_DIV_SHIFT                (0U)
+/*! DIV - Clock divider value */
+#define SYSCON_FROLFDIV_DIV(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FROLFDIV_DIV_SHIFT)) & SYSCON_FROLFDIV_DIV_MASK)
+
+#define SYSCON_FROLFDIV_RESET_MASK               (0x20000000U)
+#define SYSCON_FROLFDIV_RESET_SHIFT              (29U)
+/*! RESET - Resets the divider counter
+ *  0b0..Divider is not reset
+ *  0b1..Divider is reset
+ */
+#define SYSCON_FROLFDIV_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FROLFDIV_RESET_SHIFT)) & SYSCON_FROLFDIV_RESET_MASK)
+
+#define SYSCON_FROLFDIV_HALT_MASK                (0x40000000U)
+#define SYSCON_FROLFDIV_HALT_SHIFT               (30U)
+/*! HALT - Halts the divider counter
+ *  0b0..Divider clock is running
+ *  0b1..Divider clock is stopped
+ */
+#define SYSCON_FROLFDIV_HALT(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FROLFDIV_HALT_SHIFT)) & SYSCON_FROLFDIV_HALT_MASK)
+
+#define SYSCON_FROLFDIV_UNSTAB_MASK              (0x80000000U)
+#define SYSCON_FROLFDIV_UNSTAB_SHIFT             (31U)
+/*! UNSTAB - Divider status flag
+ *  0b0..Divider clock is stable
+ *  0b1..Clock frequency is not stable
+ */
+#define SYSCON_FROLFDIV_UNSTAB(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FROLFDIV_UNSTAB_SHIFT)) & SYSCON_FROLFDIV_UNSTAB_MASK)
+/*! @} */
+
+/*! @name CLKUNLOCK - Clock Configuration Unlock */
+/*! @{ */
+
+#define SYSCON_CLKUNLOCK_UNLOCK_MASK             (0x1U)
+#define SYSCON_CLKUNLOCK_UNLOCK_SHIFT            (0U)
+/*! UNLOCK - Controls clock configuration registers access (for example, SLOWCLKDIV, BUSCLKDIV,
+ *    AHBCLKDIV, FROHFDIV, FROLFDIV, PLLxCLKDIV, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx)
+ *  0b0..Updates are allowed to all clock configuration registers
+ *  0b1..Freezes all clock configuration registers update.
+ */
+#define SYSCON_CLKUNLOCK_UNLOCK(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKUNLOCK_UNLOCK_SHIFT)) & SYSCON_CLKUNLOCK_UNLOCK_MASK)
+/*! @} */
+
+/*! @name NVM_CTRL - NVM Control */
+/*! @{ */
+
+#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK      (0x1U)
+#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT     (0U)
+/*! DIS_FLASH_SPEC - Flash speculation control
+ *  0b0..Enables flash speculation
+ *  0b1..Disables flash speculation
+ */
+#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK)
+
+#define SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK       (0x2U)
+#define SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT      (1U)
+/*! DIS_DATA_SPEC - Flash data speculation control
+ *  0b0..Enables data speculation
+ *  0b1..Disables data speculation
+ */
+#define SYSCON_NVM_CTRL_DIS_DATA_SPEC(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK)
+
+#define SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK      (0x400U)
+#define SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT     (10U)
+/*! FLASH_STALL_EN - FLASH stall on busy control
+ *  0b0..No stall on FLASH busy
+ *  0b1..Stall on FLASH busy
+ */
+#define SYSCON_NVM_CTRL_FLASH_STALL_EN(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT)) & SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK)
+
+#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK  (0x10000U)
+#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT (16U)
+/*! DIS_MBECC_ERR_INST
+ *  0b0..Enables bus error on multi-bit ECC error for instruction
+ *  0b1..Disables bus error on multi-bit ECC error for instruction
+ */
+#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK)
+
+#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK  (0x20000U)
+#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT (17U)
+/*! DIS_MBECC_ERR_DATA
+ *  0b0..Enables bus error on multi-bit ECC error for data
+ *  0b1..Disables bus error on multi-bit ECC error for data
+ */
+#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK)
+/*! @} */
+
+/*! @name SMARTDMAINT - SmartDMA Interrupt Hijack */
+/*! @{ */
+
+#define SYSCON_SMARTDMAINT_INT0_MASK             (0x1U)
+#define SYSCON_SMARTDMAINT_INT0_SHIFT            (0U)
+/*! INT0 - SmartDMA hijack NVIC IRQ2
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT0_SHIFT)) & SYSCON_SMARTDMAINT_INT0_MASK)
+
+#define SYSCON_SMARTDMAINT_INT2_MASK             (0x4U)
+#define SYSCON_SMARTDMAINT_INT2_SHIFT            (2U)
+/*! INT2 - SmartDMA hijack NVIC IRQ26
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT2_SHIFT)) & SYSCON_SMARTDMAINT_INT2_MASK)
+
+#define SYSCON_SMARTDMAINT_INT3_MASK             (0x8U)
+#define SYSCON_SMARTDMAINT_INT3_SHIFT            (3U)
+/*! INT3 - SmartDMA hijack NVIC IRQ27
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT3_SHIFT)) & SYSCON_SMARTDMAINT_INT3_MASK)
+
+#define SYSCON_SMARTDMAINT_INT4_MASK             (0x10U)
+#define SYSCON_SMARTDMAINT_INT4_SHIFT            (4U)
+/*! INT4 - SmartDMA hijack NVIC IRQ28
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT4(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT4_SHIFT)) & SYSCON_SMARTDMAINT_INT4_MASK)
+
+#define SYSCON_SMARTDMAINT_INT5_MASK             (0x20U)
+#define SYSCON_SMARTDMAINT_INT5_SHIFT            (5U)
+/*! INT5 - SmartDMA hijack NVIC IRQ29
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT5(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT5_SHIFT)) & SYSCON_SMARTDMAINT_INT5_MASK)
+
+#define SYSCON_SMARTDMAINT_INT6_MASK             (0x40U)
+#define SYSCON_SMARTDMAINT_INT6_SHIFT            (6U)
+/*! INT6 - SmartDMA hijack NVIC IRQ31
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT6(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT6_SHIFT)) & SYSCON_SMARTDMAINT_INT6_MASK)
+
+#define SYSCON_SMARTDMAINT_INT7_MASK             (0x80U)
+#define SYSCON_SMARTDMAINT_INT7_SHIFT            (7U)
+/*! INT7 - SmartDMA hijack NVIC IRQ32
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT7(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT7_SHIFT)) & SYSCON_SMARTDMAINT_INT7_MASK)
+
+#define SYSCON_SMARTDMAINT_INT8_MASK             (0x100U)
+#define SYSCON_SMARTDMAINT_INT8_SHIFT            (8U)
+/*! INT8 - SmartDMA hijack NVIC IRQ33
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT8(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT8_SHIFT)) & SYSCON_SMARTDMAINT_INT8_MASK)
+
+#define SYSCON_SMARTDMAINT_INT9_MASK             (0x200U)
+#define SYSCON_SMARTDMAINT_INT9_SHIFT            (9U)
+/*! INT9 - SmartDMA hijack NVIC IRQ34
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT9(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT9_SHIFT)) & SYSCON_SMARTDMAINT_INT9_MASK)
+
+#define SYSCON_SMARTDMAINT_INT11_MASK            (0x800U)
+#define SYSCON_SMARTDMAINT_INT11_SHIFT           (11U)
+/*! INT11 - SmartDMA hijack NVIC IRQ39
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT11(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT11_SHIFT)) & SYSCON_SMARTDMAINT_INT11_MASK)
+
+#define SYSCON_SMARTDMAINT_INT12_MASK            (0x1000U)
+#define SYSCON_SMARTDMAINT_INT12_SHIFT           (12U)
+/*! INT12 - SmartDMA hijack NVIC IRQ40
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT12(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT12_SHIFT)) & SYSCON_SMARTDMAINT_INT12_MASK)
+
+#define SYSCON_SMARTDMAINT_INT13_MASK            (0x2000U)
+#define SYSCON_SMARTDMAINT_INT13_SHIFT           (13U)
+/*! INT13 - SmartDMA hijack NVIC IRQ41
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT13(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT13_SHIFT)) & SYSCON_SMARTDMAINT_INT13_MASK)
+
+#define SYSCON_SMARTDMAINT_INT14_MASK            (0x4000U)
+#define SYSCON_SMARTDMAINT_INT14_SHIFT           (14U)
+/*! INT14 - SmartDMA hijack NVIC IRQ59
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT14(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT14_SHIFT)) & SYSCON_SMARTDMAINT_INT14_MASK)
+
+#define SYSCON_SMARTDMAINT_INT15_MASK            (0x8000U)
+#define SYSCON_SMARTDMAINT_INT15_SHIFT           (15U)
+/*! INT15 - SmartDMA hijack NVIC IRQ62
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT15(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT15_SHIFT)) & SYSCON_SMARTDMAINT_INT15_MASK)
+
+#define SYSCON_SMARTDMAINT_INT16_MASK            (0x10000U)
+#define SYSCON_SMARTDMAINT_INT16_SHIFT           (16U)
+/*! INT16 - SmartDMA hijack NVIC IRQ64
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT16(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT16_SHIFT)) & SYSCON_SMARTDMAINT_INT16_MASK)
+
+#define SYSCON_SMARTDMAINT_INT17_MASK            (0x20000U)
+#define SYSCON_SMARTDMAINT_INT17_SHIFT           (17U)
+/*! INT17 - SmartDMA hijack NVIC IRQ71
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT17(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT17_SHIFT)) & SYSCON_SMARTDMAINT_INT17_MASK)
+
+#define SYSCON_SMARTDMAINT_INT18_MASK            (0x40000U)
+#define SYSCON_SMARTDMAINT_INT18_SHIFT           (18U)
+/*! INT18 - SmartDMA hijack NVIC IRQ72
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT18(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT18_SHIFT)) & SYSCON_SMARTDMAINT_INT18_MASK)
+
+#define SYSCON_SMARTDMAINT_INT19_MASK            (0x80000U)
+#define SYSCON_SMARTDMAINT_INT19_SHIFT           (19U)
+/*! INT19 - SmartDMA hijack NVIC IRQ73
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT19(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT19_SHIFT)) & SYSCON_SMARTDMAINT_INT19_MASK)
+
+#define SYSCON_SMARTDMAINT_INT20_MASK            (0x100000U)
+#define SYSCON_SMARTDMAINT_INT20_SHIFT           (20U)
+/*! INT20 - SmartDMA hijack NVIC IRQ74
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT20(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT20_SHIFT)) & SYSCON_SMARTDMAINT_INT20_MASK)
+
+#define SYSCON_SMARTDMAINT_INT21_MASK            (0x200000U)
+#define SYSCON_SMARTDMAINT_INT21_SHIFT           (21U)
+/*! INT21 - SmartDMA hijack NVIC IRQ75
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_SMARTDMAINT_INT21(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT21_SHIFT)) & SYSCON_SMARTDMAINT_INT21_MASK)
+/*! @} */
+
+/*! @name CPUSTAT - CPU Status */
+/*! @{ */
+
+#define SYSCON_CPUSTAT_CPU0SLEEPING_MASK         (0x1U)
+#define SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT        (0U)
+/*! CPU0SLEEPING - CPU0 sleeping state
+ *  0b0..CPU is not sleeping
+ *  0b1..CPU is sleeping
+ */
+#define SYSCON_CPUSTAT_CPU0SLEEPING(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPUSTAT_CPU0SLEEPING_MASK)
+
+#define SYSCON_CPUSTAT_CPU0LOCKUP_MASK           (0x4U)
+#define SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT          (2U)
+/*! CPU0LOCKUP - CPU0 lockup state
+ *  0b0..CPU is not in lockup
+ *  0b1..CPU is in lockup
+ */
+#define SYSCON_CPUSTAT_CPU0LOCKUP(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPUSTAT_CPU0LOCKUP_MASK)
+/*! @} */
+
+/*! @name LPCAC_CTRL - LPCAC Control */
+/*! @{ */
+
+#define SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK         (0x1U)
+#define SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT        (0U)
+/*! DIS_LPCAC - Disables/enables the cache function.
+ *  0b0..Enabled
+ *  0b1..Disabled
+ */
+#define SYSCON_LPCAC_CTRL_DIS_LPCAC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK)
+
+#define SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK         (0x2U)
+#define SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT        (1U)
+/*! CLR_LPCAC - Clears the cache function.
+ *  0b0..Unclears the cache
+ *  0b1..Clears the cache
+ */
+#define SYSCON_LPCAC_CTRL_CLR_LPCAC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK)
+
+#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK      (0x4U)
+#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT     (2U)
+/*! FRC_NO_ALLOC - Forces no allocation.
+ *  0b0..Forces allocation
+ *  0b1..Forces no allocation
+ */
+#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT)) & SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK)
+
+#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK    (0x10U)
+#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT   (4U)
+/*! DIS_LPCAC_WTBF - Disable LPCAC Write Through Buffer.
+ *  0b0..Enables write through buffer
+ *  0b1..Disables write through buffer
+ */
+#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK)
+
+#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK    (0x20U)
+#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT   (5U)
+/*! LIM_LPCAC_WTBF - Limit LPCAC Write Through Buffer.
+ *  0b0..Write buffer enabled when transaction is bufferable.
+ *  0b1..Write buffer enabled when transaction is cacheable and bufferable
+ */
+#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK)
+
+#define SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK         (0x80U)
+#define SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT        (7U)
+/*! LPCAC_XOM - LPCAC XOM(eXecute-Only-Memory) attribute control
+ *  0b0..Disabled.
+ *  0b1..Enabled.
+ */
+#define SYSCON_LPCAC_CTRL_LPCAC_XOM(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT)) & SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK)
+
+#define SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK     (0x100U)
+#define SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_SHIFT    (8U)
+/*! LPCAC_MEM_REQ - Request LPCAC memories.
+ *  0b0..Configure shared memories RAMX1 as general memories.
+ *  0b1..Configure shared memories RAMX1 as LPCAC memories, write one lock until a system reset.
+ */
+#define SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_SHIFT)) & SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK)
+/*! @} */
+
+/*! @name PWM0SUBCTL - PWM0 Submodule Control */
+/*! @{ */
+
+#define SYSCON_PWM0SUBCTL_CLK0_EN_MASK           (0x1U)
+#define SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT          (0U)
+/*! CLK0_EN - Enables PWM0 SUB Clock0
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_PWM0SUBCTL_CLK0_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK0_EN_MASK)
+
+#define SYSCON_PWM0SUBCTL_CLK1_EN_MASK           (0x2U)
+#define SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT          (1U)
+/*! CLK1_EN - Enables PWM0 SUB Clock1
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_PWM0SUBCTL_CLK1_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK1_EN_MASK)
+
+#define SYSCON_PWM0SUBCTL_CLK2_EN_MASK           (0x4U)
+#define SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT          (2U)
+/*! CLK2_EN - Enables PWM0 SUB Clock2
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_PWM0SUBCTL_CLK2_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK2_EN_MASK)
+
+#define SYSCON_PWM0SUBCTL_CLK3_EN_MASK           (0x8U)
+#define SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT          (3U)
+/*! CLK3_EN - Enables PWM0 SUB Clock3
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_PWM0SUBCTL_CLK3_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK3_EN_MASK)
+/*! @} */
+
+/*! @name PWM1SUBCTL - PWM1 Submodule Control */
+/*! @{ */
+
+#define SYSCON_PWM1SUBCTL_CLK0_EN_MASK           (0x1U)
+#define SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT          (0U)
+/*! CLK0_EN - Enables PWM1 SUB Clock0
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_PWM1SUBCTL_CLK0_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK0_EN_MASK)
+
+#define SYSCON_PWM1SUBCTL_CLK1_EN_MASK           (0x2U)
+#define SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT          (1U)
+/*! CLK1_EN - Enables PWM1 SUB Clock1
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_PWM1SUBCTL_CLK1_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK1_EN_MASK)
+
+#define SYSCON_PWM1SUBCTL_CLK2_EN_MASK           (0x4U)
+#define SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT          (2U)
+/*! CLK2_EN - Enables PWM1 SUB Clock2
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_PWM1SUBCTL_CLK2_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK2_EN_MASK)
+
+#define SYSCON_PWM1SUBCTL_CLK3_EN_MASK           (0x8U)
+#define SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT          (3U)
+/*! CLK3_EN - Enables PWM1 SUB Clock3
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_PWM1SUBCTL_CLK3_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK3_EN_MASK)
+/*! @} */
+
+/*! @name CTIMERGLOBALSTARTEN - CTIMER Global Start Enable */
+/*! @{ */
+
+#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK (0x1U)
+#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT (0U)
+/*! CTIMER0_CLK_EN - Enables the CTIMER0 function clock
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK)
+
+#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK (0x2U)
+#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT (1U)
+/*! CTIMER1_CLK_EN - Enables the CTIMER1 function clock
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK)
+
+#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK (0x4U)
+#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT (2U)
+/*! CTIMER2_CLK_EN - Enables the CTIMER2 function clock
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK)
+/*! @} */
+
+/*! @name RAM_CTRL - RAM Control */
+/*! @{ */
+
+#define SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_MASK     (0x1U)
+#define SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_SHIFT    (0U)
+/*! RAMA_ECC_ENABLE - RAMA ECC enable
+ *  0b0..ECC is disabled
+ *  0b1..ECC is enabled
+ */
+#define SYSCON_RAM_CTRL_RAMA_ECC_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_SHIFT)) & SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_MASK)
+
+#define SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_MASK    (0x10000U)
+#define SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_SHIFT   (16U)
+/*! RAMA_CG_OVERRIDE - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0.
+ *  0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles
+ *  0b1..Auto clock gating feature is disabled
+ */
+#define SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_MASK)
+
+#define SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_MASK    (0x20000U)
+#define SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_SHIFT   (17U)
+/*! RAMX_CG_OVERRIDE - RAMX bank clock gating control
+ *  0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles
+ *  0b1..Auto clock gating feature is disabled
+ */
+#define SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_MASK)
+
+#define SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE_MASK    (0x40000U)
+#define SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE_SHIFT   (18U)
+/*! RAMB_CG_OVERRIDE - RAMB bank clock gating control
+ *  0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles
+ *  0b1..Auto clock gating feature is disabled
+ */
+#define SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE_MASK)
+
+#define SYSCON_RAM_CTRL_RAMC_CG_OVERRIDE_MASK    (0x80000U)
+#define SYSCON_RAM_CTRL_RAMC_CG_OVERRIDE_SHIFT   (19U)
+/*! RAMC_CG_OVERRIDE - RAMC bank clock gating control
+ *  0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles
+ *  0b1..Auto clock gating feature is disabled
+ */
+#define SYSCON_RAM_CTRL_RAMC_CG_OVERRIDE(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMC_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMC_CG_OVERRIDE_MASK)
+/*! @} */
+
+/*! @name GRAY_CODE_LSB - Gray to Binary Converter Gray Code [31:0] */
+/*! @{ */
+
+#define SYSCON_GRAY_CODE_LSB_CODE_GRAY_31_0_MASK (0xFFFFFFFFU)
+#define SYSCON_GRAY_CODE_LSB_CODE_GRAY_31_0_SHIFT (0U)
+/*! code_gray_31_0 - Gray code [31:0] */
+#define SYSCON_GRAY_CODE_LSB_CODE_GRAY_31_0(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_LSB_CODE_GRAY_31_0_SHIFT)) & SYSCON_GRAY_CODE_LSB_CODE_GRAY_31_0_MASK)
+/*! @} */
+
+/*! @name GRAY_CODE_MSB - Gray to Binary Converter Gray Code [41:32] */
+/*! @{ */
+
+#define SYSCON_GRAY_CODE_MSB_CODE_GRAY_41_32_MASK (0x3FFU)
+#define SYSCON_GRAY_CODE_MSB_CODE_GRAY_41_32_SHIFT (0U)
+/*! code_gray_41_32 - Gray code [41:32] */
+#define SYSCON_GRAY_CODE_MSB_CODE_GRAY_41_32(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_MSB_CODE_GRAY_41_32_SHIFT)) & SYSCON_GRAY_CODE_MSB_CODE_GRAY_41_32_MASK)
+/*! @} */
+
+/*! @name BINARY_CODE_LSB - Gray to Binary Converter Binary Code [31:0] */
+/*! @{ */
+
+#define SYSCON_BINARY_CODE_LSB_CODE_BIN_31_0_MASK (0xFFFFFFFFU)
+#define SYSCON_BINARY_CODE_LSB_CODE_BIN_31_0_SHIFT (0U)
+/*! code_bin_31_0 - Binary code [31:0] */
+#define SYSCON_BINARY_CODE_LSB_CODE_BIN_31_0(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_LSB_CODE_BIN_31_0_SHIFT)) & SYSCON_BINARY_CODE_LSB_CODE_BIN_31_0_MASK)
+/*! @} */
+
+/*! @name BINARY_CODE_MSB - Gray to Binary Converter Binary Code [41:32] */
+/*! @{ */
+
+#define SYSCON_BINARY_CODE_MSB_CODE_BIN_41_32_MASK (0x3FFU)
+#define SYSCON_BINARY_CODE_MSB_CODE_BIN_41_32_SHIFT (0U)
+/*! code_bin_41_32 - Binary code [41:32] */
+#define SYSCON_BINARY_CODE_MSB_CODE_BIN_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_MSB_CODE_BIN_41_32_SHIFT)) & SYSCON_BINARY_CODE_MSB_CODE_BIN_41_32_MASK)
+/*! @} */
+
+/*! @name MSFCFG - MSF Configuration */
+/*! @{ */
+
+#define SYSCON_MSFCFG_IFR_ERASE_DIS0_MASK        (0x1U)
+#define SYSCON_MSFCFG_IFR_ERASE_DIS0_SHIFT       (0U)
+/*! IFR_ERASE_DIS0 - user IFR sector 0 erase control
+ *  0b0..Enable IFR sector erase.
+ *  0b1..Disable IFR sector erase, write one lock until a system reset.
+ */
+#define SYSCON_MSFCFG_IFR_ERASE_DIS0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_MSFCFG_IFR_ERASE_DIS0_SHIFT)) & SYSCON_MSFCFG_IFR_ERASE_DIS0_MASK)
+
+#define SYSCON_MSFCFG_IFR_ERASE_DIS1_MASK        (0x2U)
+#define SYSCON_MSFCFG_IFR_ERASE_DIS1_SHIFT       (1U)
+/*! IFR_ERASE_DIS1 - user IFR sector 1 erase control
+ *  0b0..Enable IFR sector erase.
+ *  0b1..Disable IFR sector erase, write one lock until a system reset.
+ */
+#define SYSCON_MSFCFG_IFR_ERASE_DIS1(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_MSFCFG_IFR_ERASE_DIS1_SHIFT)) & SYSCON_MSFCFG_IFR_ERASE_DIS1_MASK)
+
+#define SYSCON_MSFCFG_IFR_ERASE_DIS2_MASK        (0x4U)
+#define SYSCON_MSFCFG_IFR_ERASE_DIS2_SHIFT       (2U)
+/*! IFR_ERASE_DIS2 - user IFR sector 2 erase control
+ *  0b0..Enable IFR sector erase.
+ *  0b1..Disable IFR sector erase, write one lock until a system reset.
+ */
+#define SYSCON_MSFCFG_IFR_ERASE_DIS2(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_MSFCFG_IFR_ERASE_DIS2_SHIFT)) & SYSCON_MSFCFG_IFR_ERASE_DIS2_MASK)
+
+#define SYSCON_MSFCFG_IFR_ERASE_DIS3_MASK        (0x8U)
+#define SYSCON_MSFCFG_IFR_ERASE_DIS3_SHIFT       (3U)
+/*! IFR_ERASE_DIS3 - user IFR sector 3 erase control
+ *  0b0..Enable IFR sector erase.
+ *  0b1..Disable IFR sector erase, write one lock until a system reset.
+ */
+#define SYSCON_MSFCFG_IFR_ERASE_DIS3(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_MSFCFG_IFR_ERASE_DIS3_SHIFT)) & SYSCON_MSFCFG_IFR_ERASE_DIS3_MASK)
+
+#define SYSCON_MSFCFG_MASS_ERASE_DIS_MASK        (0x100U)
+#define SYSCON_MSFCFG_MASS_ERASE_DIS_SHIFT       (8U)
+/*! MASS_ERASE_DIS - Mass erase control
+ *  0b0..Enables mass erase
+ *  0b1..Disables mass erase, write one lock until a system reset.
+ */
+#define SYSCON_MSFCFG_MASS_ERASE_DIS(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_MSFCFG_MASS_ERASE_DIS_SHIFT)) & SYSCON_MSFCFG_MASS_ERASE_DIS_MASK)
+/*! @} */
+
+/*! @name ROP_STATE - ROP State Register */
+/*! @{ */
+
+#define SYSCON_ROP_STATE_ROP_STATE_MASK          (0xFFFFFFFFU)
+#define SYSCON_ROP_STATE_ROP_STATE_SHIFT         (0U)
+/*! ROP_STATE - ROP state */
+#define SYSCON_ROP_STATE_ROP_STATE(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_ROP_STATE_ROP_STATE_SHIFT)) & SYSCON_ROP_STATE_ROP_STATE_MASK)
+/*! @} */
+
+/*! @name SRAM_XEN - RAM XEN Control */
+/*! @{ */
+
+#define SYSCON_SRAM_XEN_RAMX0_XEN_MASK           (0x1U)
+#define SYSCON_SRAM_XEN_RAMX0_XEN_SHIFT          (0U)
+/*! RAMX0_XEN - RAMX0 Execute permission control.
+ *  0b0..Execute permission is disabled, R/W are enabled.
+ *  0b1..Execute permission is enabled, R/W/X are enabled.
+ */
+#define SYSCON_SRAM_XEN_RAMX0_XEN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMX0_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMX0_XEN_MASK)
+
+#define SYSCON_SRAM_XEN_RAMX1_XEN_MASK           (0x2U)
+#define SYSCON_SRAM_XEN_RAMX1_XEN_SHIFT          (1U)
+/*! RAMX1_XEN - RAMX1 Execute permission control.
+ *  0b0..Execute permission is disabled, R/W are enabled.
+ *  0b1..Execute permission is enabled, R/W/X are enabled.
+ */
+#define SYSCON_SRAM_XEN_RAMX1_XEN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMX1_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMX1_XEN_MASK)
+
+#define SYSCON_SRAM_XEN_RAMA0_XEN_MASK           (0x4U)
+#define SYSCON_SRAM_XEN_RAMA0_XEN_SHIFT          (2U)
+/*! RAMA0_XEN - RAMA0 Execute permission control.
+ *  0b0..Execute permission is disabled, R/W are enabled.
+ *  0b1..Execute permission is enabled, R/W/X are enabled.
+ */
+#define SYSCON_SRAM_XEN_RAMA0_XEN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMA0_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMA0_XEN_MASK)
+
+#define SYSCON_SRAM_XEN_RAMA1_XEN_MASK           (0x8U)
+#define SYSCON_SRAM_XEN_RAMA1_XEN_SHIFT          (3U)
+/*! RAMA1_XEN - RAMAx (excepts RAMA0) Execute permission control.
+ *  0b0..Execute permission is disabled, R/W are enabled.
+ *  0b1..Execute permission is enabled, R/W/X are enabled.
+ */
+#define SYSCON_SRAM_XEN_RAMA1_XEN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMA1_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMA1_XEN_MASK)
+
+#define SYSCON_SRAM_XEN_RAMB_XEN_MASK            (0x10U)
+#define SYSCON_SRAM_XEN_RAMB_XEN_SHIFT           (4U)
+/*! RAMB_XEN - RAMBx Execute permission control.
+ *  0b0..Execute permission is disabled, R/W are enabled.
+ *  0b1..Execute permission is enabled, R/W/X are enabled.
+ */
+#define SYSCON_SRAM_XEN_RAMB_XEN(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMB_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMB_XEN_MASK)
+
+#define SYSCON_SRAM_XEN_RAMC_XEN_MASK            (0x20U)
+#define SYSCON_SRAM_XEN_RAMC_XEN_SHIFT           (5U)
+/*! RAMC_XEN - RAMCx Execute permission control.
+ *  0b0..Execute permission is disabled, R/W are enabled.
+ *  0b1..Execute permission is enabled, R/W/X are enabled.
+ */
+#define SYSCON_SRAM_XEN_RAMC_XEN(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMC_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMC_XEN_MASK)
+
+#define SYSCON_SRAM_XEN_LOCK_MASK                (0x80000000U)
+#define SYSCON_SRAM_XEN_LOCK_SHIFT               (31U)
+/*! LOCK - This 1-bit field provides a mechanism to limit writes to this register (and SRAM_XEN_DP)
+ *    to protect its contents. Once set, this bit remains asserted until a system reset.
+ *  0b0..This register is not locked and can be altered.
+ *  0b1..This register is locked and cannot be altered.
+ */
+#define SYSCON_SRAM_XEN_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_LOCK_SHIFT)) & SYSCON_SRAM_XEN_LOCK_MASK)
+/*! @} */
+
+/*! @name SRAM_XEN_DP - RAM XEN Control (Duplicate) */
+/*! @{ */
+
+#define SYSCON_SRAM_XEN_DP_RAMX0_XEN_MASK        (0x1U)
+#define SYSCON_SRAM_XEN_DP_RAMX0_XEN_SHIFT       (0U)
+/*! RAMX0_XEN - Refer to SRAM_XEN for more details. */
+#define SYSCON_SRAM_XEN_DP_RAMX0_XEN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMX0_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMX0_XEN_MASK)
+
+#define SYSCON_SRAM_XEN_DP_RAMX1_XEN_MASK        (0x2U)
+#define SYSCON_SRAM_XEN_DP_RAMX1_XEN_SHIFT       (1U)
+/*! RAMX1_XEN - Refer to SRAM_XEN for more details. */
+#define SYSCON_SRAM_XEN_DP_RAMX1_XEN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMX1_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMX1_XEN_MASK)
+
+#define SYSCON_SRAM_XEN_DP_RAMA0_XEN_MASK        (0x4U)
+#define SYSCON_SRAM_XEN_DP_RAMA0_XEN_SHIFT       (2U)
+/*! RAMA0_XEN - Refer to SRAM_XEN for more details. */
+#define SYSCON_SRAM_XEN_DP_RAMA0_XEN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMA0_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMA0_XEN_MASK)
+
+#define SYSCON_SRAM_XEN_DP_RAMA1_XEN_MASK        (0x8U)
+#define SYSCON_SRAM_XEN_DP_RAMA1_XEN_SHIFT       (3U)
+/*! RAMA1_XEN - Refer to SRAM_XEN for more details. */
+#define SYSCON_SRAM_XEN_DP_RAMA1_XEN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMA1_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMA1_XEN_MASK)
+
+#define SYSCON_SRAM_XEN_DP_RAMB_XEN_MASK         (0x10U)
+#define SYSCON_SRAM_XEN_DP_RAMB_XEN_SHIFT        (4U)
+/*! RAMB_XEN - Refer to SRAM_XEN for more details. */
+#define SYSCON_SRAM_XEN_DP_RAMB_XEN(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMB_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMB_XEN_MASK)
+
+#define SYSCON_SRAM_XEN_DP_RAMC_XEN_MASK         (0x20U)
+#define SYSCON_SRAM_XEN_DP_RAMC_XEN_SHIFT        (5U)
+/*! RAMC_XEN - Refer to SRAM_XEN for more details. */
+#define SYSCON_SRAM_XEN_DP_RAMC_XEN(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMC_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMC_XEN_MASK)
+/*! @} */
+
+/*! @name ELS_OTP_LC_STATE - Life Cycle State Register */
+/*! @{ */
+
+#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK (0xFFU)
+#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT (0U)
+/*! OTP_LC_STATE - OTP life cycle state */
+#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK)
+/*! @} */
+
+/*! @name ELS_OTP_LC_STATE_DP - Life Cycle State Register (Duplicate) */
+/*! @{ */
+
+#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK (0xFFU)
+#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT (0U)
+/*! OTP_LC_STATE_DP - OTP life cycle state */
+#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK)
+/*! @} */
+
+/*! @name DEBUG_LOCK_EN - Control Write Access to Security */
+/*! @{ */
+
+#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK       (0xFU)
+#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT      (0U)
+/*! LOCK_ALL - Controls write access to the security registers
+ *  0b0000..Any other value than b1010: disables write access to all registers
+ *  0b1010..Enables write access to all registers
+ */
+#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK)
+/*! @} */
+
+/*! @name DEBUG_FEATURES - Cortex Debug Features Control */
+/*! @{ */
+
+#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK    (0x3U)
+#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT   (0U)
+/*! CPU0_DBGEN - CPU0 invasive debug control
+ *  0b01..Disables debug
+ *  0b10..Enables debug
+ */
+#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK)
+
+#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK    (0xCU)
+#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT   (2U)
+/*! CPU0_NIDEN - CPU0 non-invasive debug control
+ *  0b01..Disables debug
+ *  0b10..Enables debug
+ */
+#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK)
+/*! @} */
+
+/*! @name DEBUG_FEATURES_DP - Cortex Debug Features Control (Duplicate) */
+/*! @{ */
+
+#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U)
+#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U)
+/*! CPU0_DBGEN - CPU0 invasive debug control
+ *  0b01..Disables debug
+ *  0b10..Enables debug
+ */
+#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK)
+
+#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU)
+#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U)
+/*! CPU0_NIDEN - CPU0 non-invasive debug control
+ *  0b01..Disables debug
+ *  0b10..Enables debug
+ */
+#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK)
+/*! @} */
+
+/*! @name SWD_ACCESS_CPU0 - CPU0 Software Debug Access */
+/*! @{ */
+
+#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE_MASK     (0xFFFFFFFFU)
+#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE_SHIFT    (0U)
+/*! SEC_CODE - CPU0 SWD-AP: 0x12345678
+ *  0b00000000000000000000000000000000..CPU0 DAP is not allowed. Reading back register is read as 0x5.
+ *  0b00010010001101000101011001111000..Value to write to enable CPU0 SWD access. Reading back register is read as 0xA.
+ */
+#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU0_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU0_SEC_CODE_MASK)
+/*! @} */
+
+/*! @name DEBUG_AUTH_BEACON - Debug Authentication BEACON */
+/*! @{ */
+
+#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK     (0xFFFFFFFFU)
+#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT    (0U)
+/*! BEACON - Sets by the debug authentication code in ROM to pass the debug beacons (Credential
+ *    Beacon and Authentication Beacon) to the application code.
+ */
+#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK)
+/*! @} */
+
+/*! @name JTAG_ID - JTAG Chip ID */
+/*! @{ */
+
+#define SYSCON_JTAG_ID_JTAG_ID_MASK              (0xFFFFFFFFU)
+#define SYSCON_JTAG_ID_JTAG_ID_SHIFT             (0U)
+/*! JTAG_ID - Indicates the device ID */
+#define SYSCON_JTAG_ID_JTAG_ID(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAG_ID_JTAG_ID_SHIFT)) & SYSCON_JTAG_ID_JTAG_ID_MASK)
+/*! @} */
+
+/*! @name DEVICE_TYPE - Device Type */
+/*! @{ */
+
+#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_NUM_MASK  (0xFFFFU)
+#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_NUM_SHIFT (0U)
+/*! DEVICE_TYPE_NUM - Indicates the device part number */
+#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_NUM(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_NUM_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_NUM_MASK)
+
+#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_SEC_MASK  (0x10000U)
+#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_SEC_SHIFT (16U)
+/*! DEVICE_TYPE_SEC - Indicates the device type
+ *  0b0..Non Secure
+ *  0b1..Secure
+ */
+#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_SEC(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_SEC_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_SEC_MASK)
+
+#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PKG_MASK  (0xF00000U)
+#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PKG_SHIFT (20U)
+/*! DEVICE_TYPE_PKG - Indicates the device's package type
+ *  0b0000..HLQFP
+ *  0b0001..HTQFP
+ *  0b0010..BGA
+ *  0b0011..HDQFP
+ *  0b0100..QFN
+ *  0b0101..CSP
+ *  0b0110..LQFP
+ */
+#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PKG(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_PKG_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_PKG_MASK)
+
+#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PIN_MASK  (0xFF000000U)
+#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PIN_SHIFT (24U)
+/*! DEVICE_TYPE_PIN - Indicates the device's pin number */
+#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PIN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_PIN_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_PIN_MASK)
+/*! @} */
+
+/*! @name DEVICE_ID0 - Device ID */
+/*! @{ */
+
+#define SYSCON_DEVICE_ID0_RAM_SIZE_MASK          (0xFU)
+#define SYSCON_DEVICE_ID0_RAM_SIZE_SHIFT         (0U)
+/*! RAM_SIZE - Indicates the device's ram size
+ *  0b0000..8KB.
+ *  0b0001..16KB.
+ *  0b0010..32KB.
+ *  0b0011..64KB.
+ *  0b0100..96KB.
+ *  0b0101..128KB.
+ *  0b0110..160KB.
+ *  0b0111..192KB.
+ *  0b1000..256KB.
+ *  0b1001..288KB.
+ *  0b1010..352KB.
+ *  0b1011..512KB.
+ */
+#define SYSCON_DEVICE_ID0_RAM_SIZE(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_RAM_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_RAM_SIZE_MASK)
+
+#define SYSCON_DEVICE_ID0_FLASH_SIZE_MASK        (0xF0U)
+#define SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT       (4U)
+/*! FLASH_SIZE - Indicates the device's flash size
+ *  0b0000..32KB.
+ *  0b0001..64KB.
+ *  0b0010..128KB.
+ *  0b0011..256KB.
+ *  0b0100..512KB.
+ *  0b0101..768KB.
+ *  0b0110..1MB.
+ *  0b0111..1.5MB.
+ *  0b1000..2MB.
+ */
+#define SYSCON_DEVICE_ID0_FLASH_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_FLASH_SIZE_MASK)
+
+#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK     (0xF00000U)
+#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT    (20U)
+/*! ROM_REV_MINOR - Indicates the device's ROM revision */
+#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK)
+
+#define SYSCON_DEVICE_ID0_SECURITY_MASK          (0xF000000U)
+#define SYSCON_DEVICE_ID0_SECURITY_SHIFT         (24U)
+/*! SECURITY
+ *  0b0101..Secure version. (All values other than 1010b represent the secure version.)
+ *  0b1010..Non secure version.
+ */
+#define SYSCON_DEVICE_ID0_SECURITY(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_SECURITY_SHIFT)) & SYSCON_DEVICE_ID0_SECURITY_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SYSCON_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group SYSCON_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_SYSCON_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_TRDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_TRDC.h
new file mode 100644
index 0000000000..eabacda7fd
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_TRDC.h
@@ -0,0 +1,904 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for TRDC
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_TRDC.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for TRDC
+ *
+ * CMSIS Peripheral Access Layer for TRDC
+ */
+
+#if !defined(PERI_TRDC_H_)
+#define PERI_TRDC_H_                             /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- TRDC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TRDC_Peripheral_Access_Layer TRDC Peripheral Access Layer
+ * @{
+ */
+
+/** TRDC - Size of Registers Arrays */
+#define MBC_MEM_GLBCFG_COUNT                      4u
+#define MBC_MEMN_GLBAC_COUNT                      8u
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_COUNT 4u
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_COUNT 2u
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_COUNT 1u
+#define TRDC_MBC_INDEX_COUNT                      1u
+
+/** TRDC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x1AC */
+    __IO uint32_t MBC_MEM_GLBCFG[MBC_MEM_GLBCFG_COUNT];   /**< MBC Global Configuration Register, array offset: 0x0, array step: index*0x1AC, index2*0x4 */
+         uint8_t RESERVED_0[16];
+    __IO uint32_t MBC_MEMN_GLBAC[MBC_MEMN_GLBAC_COUNT];   /**< MBC Global Access Control, array offset: 0x20, array step: index*0x1AC, index2*0x4 */
+    __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_COUNT];   /**< MBC Memory Block Configuration Word, array offset: 0x40, array step: index*0x1AC, index2*0x4 */
+         uint8_t RESERVED_1[304];
+    __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_COUNT];   /**< MBC Memory Block Configuration Word, array offset: 0x180, array step: index*0x1AC, index2*0x4 */
+         uint8_t RESERVED_2[32];
+    __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_COUNT];   /**< MBC Memory Block Configuration Word, array offset: 0x1A8, array step: index*0x1AC, index2*0x4 */
+  } MBC_INDEX[TRDC_MBC_INDEX_COUNT];
+} TRDC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TRDC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TRDC_Register_Masks TRDC Register Masks
+ * @{
+ */
+
+/*! @name MBC_INDEX_MBC_MEM_GLBCFG - MBC Global Configuration Register */
+/*! @{ */
+
+#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK (0x3FFU)
+#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT (0U)
+/*! NBLKS - Number of blocks in this memory */
+#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK)
+
+#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U)
+#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U)
+/*! SIZE_LOG2 - Log2 size per block */
+#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK)
+
+#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK  (0xC0000000U)
+#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT (30U)
+/*! CLRE - Clear Error */
+#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK)
+/*! @} */
+
+/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */
+#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT      (1U)
+
+/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */
+#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT2     (4U)
+
+/*! @name MBC_INDEX_MBC_MEMN_GLBAC - MBC Global Access Control */
+/*! @{ */
+
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK   (0x1U)
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT  (0U)
+/*! NUX - NonsecureUser Execute
+ *  0b0..Execute access is not allowed in Nonsecure User mode.
+ *  0b1..Execute access is allowed in Nonsecure User mode.
+ */
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK)
+
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK   (0x2U)
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT  (1U)
+/*! NUW - NonsecureUser Write
+ *  0b0..Write access is not allowed in Nonsecure User mode.
+ *  0b1..Write access is allowed in Nonsecure User mode.
+ */
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK)
+
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK   (0x4U)
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT  (2U)
+/*! NUR - NonsecureUser Read
+ *  0b0..Read access is not allowed in Nonsecure User mode.
+ *  0b1..Read access is allowed in Nonsecure User mode.
+ */
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK)
+
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK   (0x10U)
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT  (4U)
+/*! NPX - NonsecurePriv Execute
+ *  0b0..Execute access is not allowed in Nonsecure Privilege mode.
+ *  0b1..Execute access is allowed in Nonsecure Privilege mode.
+ */
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK)
+
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK   (0x20U)
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT  (5U)
+/*! NPW - NonsecurePriv Write
+ *  0b0..Write access is not allowed in Nonsecure Privilege mode.
+ *  0b1..Write access is allowed in Nonsecure Privilege mode.
+ */
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK)
+
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK   (0x40U)
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT  (6U)
+/*! NPR - NonsecurePriv Read
+ *  0b0..Read access is not allowed in Nonsecure Privilege mode.
+ *  0b1..Read access is allowed in Nonsecure Privilege mode.
+ */
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK)
+
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK   (0x100U)
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT  (8U)
+/*! SUX - SecureUser Execute
+ *  0b0..Execute access is not allowed in Secure User mode.
+ *  0b1..Execute access is allowed in Secure User mode.
+ */
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK)
+
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK   (0x200U)
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT  (9U)
+/*! SUW - SecureUser Write
+ *  0b0..Write access is not allowed in Secure User mode.
+ *  0b1..Write access is allowed in Secure User mode.
+ */
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK)
+
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK   (0x400U)
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT  (10U)
+/*! SUR - SecureUser Read
+ *  0b0..Read access is not allowed in Secure User mode.
+ *  0b1..Read access is allowed in Secure User mode.
+ */
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK)
+
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK   (0x1000U)
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT  (12U)
+/*! SPX - SecurePriv Execute
+ *  0b0..Execute access is not allowed in Secure Privilege mode.
+ *  0b1..Execute access is allowed in Secure Privilege mode.
+ */
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK)
+
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK   (0x2000U)
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT  (13U)
+/*! SPW - SecurePriv Write
+ *  0b0..Write access is not allowed in Secure Privilege mode.
+ *  0b1..Write access is allowed in Secure Privilege mode.
+ */
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK)
+
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK   (0x4000U)
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT  (14U)
+/*! SPR - SecurePriv Read
+ *  0b0..Read access is not allowed in Secure Privilege mode.
+ *  0b1..Read access is allowed in Secure Privilege mode.
+ */
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK)
+
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK    (0x80000000U)
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT   (31U)
+/*! LK - LOCK
+ *  0b0..This register is not locked and can be altered.
+ *  0b1..This register is locked and cannot be altered.
+ */
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK(x)      (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK)
+/*! @} */
+
+/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT      (1U)
+
+/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */
+#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT2     (8U)
+
+/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
+/*! @{ */
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
+/*! MBACSEL0 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK (0x8U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT (3U)
+/*! NSE0 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
+/*! MBACSEL1 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK (0x80U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT (7U)
+/*! NSE1 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
+/*! MBACSEL2 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK (0x800U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT (11U)
+/*! NSE2 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
+/*! MBACSEL3 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT (15U)
+/*! NSE3 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
+/*! MBACSEL4 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT (19U)
+/*! NSE4 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
+/*! MBACSEL5 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT (23U)
+/*! NSE5 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
+/*! MBACSEL6 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT (27U)
+/*! NSE6 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
+/*! MBACSEL7 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT (31U)
+/*! NSE7 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK)
+/*! @} */
+
+/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT (1U)
+
+/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2 (4U)
+
+/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
+/*! @{ */
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
+/*! MBACSEL0 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK (0x8U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT (3U)
+/*! NSE0 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
+/*! MBACSEL1 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK (0x80U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT (7U)
+/*! NSE1 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
+/*! MBACSEL2 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK (0x800U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT (11U)
+/*! NSE2 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
+/*! MBACSEL3 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT (15U)
+/*! NSE3 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
+/*! MBACSEL4 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT (19U)
+/*! NSE4 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
+/*! MBACSEL5 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT (23U)
+/*! NSE5 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
+/*! MBACSEL6 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT (27U)
+/*! NSE6 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
+/*! MBACSEL7 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT (31U)
+/*! NSE7 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK)
+/*! @} */
+
+/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT (1U)
+
+/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2 (2U)
+
+/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
+/*! @{ */
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
+/*! MBACSEL0 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK (0x8U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT (3U)
+/*! NSE0 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
+/*! MBACSEL1 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK (0x80U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT (7U)
+/*! NSE1 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
+/*! MBACSEL2 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK (0x800U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT (11U)
+/*! NSE2 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
+/*! MBACSEL3 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT (15U)
+/*! NSE3 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
+/*! MBACSEL4 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT (19U)
+/*! NSE4 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
+/*! MBACSEL5 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT (23U)
+/*! NSE5 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
+/*! MBACSEL6 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT (27U)
+/*! NSE6 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
+/*! MBACSEL7 - Memory Block Access Control Select for block B
+ *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
+ *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
+ *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
+ *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
+ *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
+ *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
+ *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
+ *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK)
+
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U)
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT (31U)
+/*! NSE7 - NonSecure Enable for block B
+ *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
+ *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
+ *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
+ *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
+ */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK)
+/*! @} */
+
+/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT (1U)
+
+/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */
+#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2 (1U)
+
+
+/*!
+ * @}
+ */ /* end of group TRDC_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group TRDC_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_TRDC_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_UTICK.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_UTICK.h
new file mode 100644
index 0000000000..15524a5b46
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_UTICK.h
@@ -0,0 +1,310 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for UTICK
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_UTICK.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for UTICK
+ *
+ * CMSIS Peripheral Access Layer for UTICK
+ */
+
+#if !defined(PERI_UTICK_H_)
+#define PERI_UTICK_H_                            /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- UTICK Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
+ * @{
+ */
+
+/** UTICK - Size of Registers Arrays */
+#define UTICK_CAP_COUNT                           4u
+
+/** UTICK - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< Control, offset: 0x0 */
+  __IO uint32_t STAT;                              /**< Status, offset: 0x4 */
+  __IO uint32_t CFG;                               /**< Capture Configuration, offset: 0x8 */
+  __O  uint32_t CAPCLR;                            /**< Capture Clear, offset: 0xC */
+  __I  uint32_t CAP[UTICK_CAP_COUNT];              /**< Capture, array offset: 0x10, array step: 0x4 */
+} UTICK_Type;
+
+/* ----------------------------------------------------------------------------
+   -- UTICK Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Register_Masks UTICK Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control */
+/*! @{ */
+
+#define UTICK_CTRL_DELAYVAL_MASK                 (0x7FFFFFFFU)
+#define UTICK_CTRL_DELAYVAL_SHIFT                (0U)
+/*! DELAYVAL - Tick Interval
+ *  0b0000000000000000000000000000000..
+ *  *..Clock cycles as defined in the description
+ */
+#define UTICK_CTRL_DELAYVAL(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
+
+#define UTICK_CTRL_REPEAT_MASK                   (0x80000000U)
+#define UTICK_CTRL_REPEAT_SHIFT                  (31U)
+/*! REPEAT - Repeat Delay
+ *  0b0..One-time delay
+ *  0b1..Delay repeats continuously
+ */
+#define UTICK_CTRL_REPEAT(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
+/*! @} */
+
+/*! @name STAT - Status */
+/*! @{ */
+
+#define UTICK_STAT_INTR_MASK                     (0x1U)
+#define UTICK_STAT_INTR_SHIFT                    (0U)
+/*! INTR - Interrupt Flag
+ *  0b0..Not pending
+ *  0b1..Pending
+ */
+#define UTICK_STAT_INTR(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
+
+#define UTICK_STAT_ACTIVE_MASK                   (0x2U)
+#define UTICK_STAT_ACTIVE_SHIFT                  (1U)
+/*! ACTIVE - Timer Active Flag
+ *  0b0..Inactive (stopped)
+ *  0b1..Active
+ */
+#define UTICK_STAT_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
+/*! @} */
+
+/*! @name CFG - Capture Configuration */
+/*! @{ */
+
+#define UTICK_CFG_CAPEN0_MASK                    (0x1U)
+#define UTICK_CFG_CAPEN0_SHIFT                   (0U)
+/*! CAPEN0 - Enable Capture 0
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define UTICK_CFG_CAPEN0(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
+
+#define UTICK_CFG_CAPEN1_MASK                    (0x2U)
+#define UTICK_CFG_CAPEN1_SHIFT                   (1U)
+/*! CAPEN1 - Enable Capture 1
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define UTICK_CFG_CAPEN1(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
+
+#define UTICK_CFG_CAPEN2_MASK                    (0x4U)
+#define UTICK_CFG_CAPEN2_SHIFT                   (2U)
+/*! CAPEN2 - Enable Capture 2
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define UTICK_CFG_CAPEN2(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
+
+#define UTICK_CFG_CAPEN3_MASK                    (0x8U)
+#define UTICK_CFG_CAPEN3_SHIFT                   (3U)
+/*! CAPEN3 - Enable Capture 3
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define UTICK_CFG_CAPEN3(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
+
+#define UTICK_CFG_CAPPOL0_MASK                   (0x100U)
+#define UTICK_CFG_CAPPOL0_SHIFT                  (8U)
+/*! CAPPOL0 - Capture Polarity 0
+ *  0b0..Positive
+ *  0b1..Negative
+ */
+#define UTICK_CFG_CAPPOL0(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
+
+#define UTICK_CFG_CAPPOL1_MASK                   (0x200U)
+#define UTICK_CFG_CAPPOL1_SHIFT                  (9U)
+/*! CAPPOL1 - Capture-Polarity 1
+ *  0b0..Positive
+ *  0b1..Negative
+ */
+#define UTICK_CFG_CAPPOL1(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
+
+#define UTICK_CFG_CAPPOL2_MASK                   (0x400U)
+#define UTICK_CFG_CAPPOL2_SHIFT                  (10U)
+/*! CAPPOL2 - Capture Polarity 2
+ *  0b0..Positive
+ *  0b1..Negative
+ */
+#define UTICK_CFG_CAPPOL2(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
+
+#define UTICK_CFG_CAPPOL3_MASK                   (0x800U)
+#define UTICK_CFG_CAPPOL3_SHIFT                  (11U)
+/*! CAPPOL3 - Capture Polarity 3
+ *  0b0..Positive
+ *  0b1..Negative
+ */
+#define UTICK_CFG_CAPPOL3(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
+/*! @} */
+
+/*! @name CAPCLR - Capture Clear */
+/*! @{ */
+
+#define UTICK_CAPCLR_CAPCLR0_MASK                (0x1U)
+#define UTICK_CAPCLR_CAPCLR0_SHIFT               (0U)
+/*! CAPCLR0 - Clear Capture 0
+ *  0b0..Does nothing
+ *  0b1..Clears the CAP0 register value
+ */
+#define UTICK_CAPCLR_CAPCLR0(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
+
+#define UTICK_CAPCLR_CAPCLR1_MASK                (0x2U)
+#define UTICK_CAPCLR_CAPCLR1_SHIFT               (1U)
+/*! CAPCLR1 - Clear Capture 1
+ *  0b0..Does nothing
+ *  0b1..Clears the CAP1 register value
+ */
+#define UTICK_CAPCLR_CAPCLR1(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
+
+#define UTICK_CAPCLR_CAPCLR2_MASK                (0x4U)
+#define UTICK_CAPCLR_CAPCLR2_SHIFT               (2U)
+/*! CAPCLR2 - Clear Capture 2
+ *  0b0..Does nothing
+ *  0b1..Clears the CAP2 register value
+ */
+#define UTICK_CAPCLR_CAPCLR2(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
+
+#define UTICK_CAPCLR_CAPCLR3_MASK                (0x8U)
+#define UTICK_CAPCLR_CAPCLR3_SHIFT               (3U)
+/*! CAPCLR3 - Clear Capture 3
+ *  0b0..Does nothing
+ *  0b1..Clears the CAP3 register value
+ */
+#define UTICK_CAPCLR_CAPCLR3(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
+/*! @} */
+
+/*! @name CAP - Capture */
+/*! @{ */
+
+#define UTICK_CAP_CAP_VALUE_MASK                 (0x7FFFFFFFU)
+#define UTICK_CAP_CAP_VALUE_SHIFT                (0U)
+/*! CAP_VALUE - Captured Value for the Related Capture Event */
+#define UTICK_CAP_CAP_VALUE(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
+
+#define UTICK_CAP_VALID_MASK                     (0x80000000U)
+#define UTICK_CAP_VALID_SHIFT                    (31U)
+/*! VALID - Captured Value Valid Flag
+ *  0b0..Valid value not captured
+ *  0b1..Valid value captured
+ */
+#define UTICK_CAP_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group UTICK_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group UTICK_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_UTICK_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_VBAT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_VBAT.h
new file mode 100644
index 0000000000..3c910f08b8
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_VBAT.h
@@ -0,0 +1,234 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for VBAT
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_VBAT.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for VBAT
+ *
+ * CMSIS Peripheral Access Layer for VBAT
+ */
+
+#if !defined(PERI_VBAT_H_)
+#define PERI_VBAT_H_                             /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- VBAT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VBAT_Peripheral_Access_Layer VBAT Peripheral Access Layer
+ * @{
+ */
+
+/** VBAT - Size of Registers Arrays */
+#define VBAT_WAKEUP_COUNT                         2u
+
+/** VBAT - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
+       uint8_t RESERVED_0[508];
+  __IO uint32_t FROCTLA;                           /**< FRO16K Control A, offset: 0x200 */
+       uint8_t RESERVED_1[20];
+  __IO uint32_t FROLCKA;                           /**< FRO16K Lock A, offset: 0x218 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t FROCLKE;                           /**< FRO16K Clock Enable, offset: 0x220 */
+       uint8_t RESERVED_3[1244];
+  struct {                                         /* offset: 0x700, array step: 0x8 */
+    __IO uint32_t WAKEUPA;                           /**< Wakeup 0 Register A, array offset: 0x700, array step: 0x8 */
+         uint8_t RESERVED_0[4];
+  } WAKEUP[VBAT_WAKEUP_COUNT];
+       uint8_t RESERVED_4[232];
+  __IO uint32_t WAKLCKA;                           /**< Wakeup Lock A, offset: 0x7F8 */
+} VBAT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- VBAT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VBAT_Register_Masks VBAT Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID */
+/*! @{ */
+
+#define VBAT_VERID_FEATURE_MASK                  (0xFFFFU)
+#define VBAT_VERID_FEATURE_SHIFT                 (0U)
+/*! FEATURE - Feature Specification Number */
+#define VBAT_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_FEATURE_SHIFT)) & VBAT_VERID_FEATURE_MASK)
+
+#define VBAT_VERID_MINOR_MASK                    (0xFF0000U)
+#define VBAT_VERID_MINOR_SHIFT                   (16U)
+/*! MINOR - Minor Version Number */
+#define VBAT_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MINOR_SHIFT)) & VBAT_VERID_MINOR_MASK)
+
+#define VBAT_VERID_MAJOR_MASK                    (0xFF000000U)
+#define VBAT_VERID_MAJOR_SHIFT                   (24U)
+/*! MAJOR - Major Version Number */
+#define VBAT_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MAJOR_SHIFT)) & VBAT_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name FROCTLA - FRO16K Control A */
+/*! @{ */
+
+#define VBAT_FROCTLA_FRO_EN_MASK                 (0x1U)
+#define VBAT_FROCTLA_FRO_EN_SHIFT                (0U)
+/*! FRO_EN - FRO16K Enable
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define VBAT_FROCTLA_FRO_EN(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_FROCTLA_FRO_EN_SHIFT)) & VBAT_FROCTLA_FRO_EN_MASK)
+/*! @} */
+
+/*! @name FROLCKA - FRO16K Lock A */
+/*! @{ */
+
+#define VBAT_FROLCKA_LOCK_MASK                   (0x1U)
+#define VBAT_FROLCKA_LOCK_SHIFT                  (0U)
+/*! LOCK - Lock
+ *  0b0..Do not block
+ *  0b1..Block
+ */
+#define VBAT_FROLCKA_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_FROLCKA_LOCK_SHIFT)) & VBAT_FROLCKA_LOCK_MASK)
+/*! @} */
+
+/*! @name FROCLKE - FRO16K Clock Enable */
+/*! @{ */
+
+#define VBAT_FROCLKE_CLKE_MASK                   (0x3U)
+#define VBAT_FROCLKE_CLKE_SHIFT                  (0U)
+/*! CLKE - Clock Enable */
+#define VBAT_FROCLKE_CLKE(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_FROCLKE_CLKE_SHIFT)) & VBAT_FROCLKE_CLKE_MASK)
+/*! @} */
+
+/*! @name WAKEUP_WAKEUPA - Wakeup 0 Register A */
+/*! @{ */
+
+#define VBAT_WAKEUP_WAKEUPA_REG_MASK             (0xFFFFFFFFU)
+#define VBAT_WAKEUP_WAKEUPA_REG_SHIFT            (0U)
+/*! REG - Register */
+#define VBAT_WAKEUP_WAKEUPA_REG(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_WAKEUP_WAKEUPA_REG_SHIFT)) & VBAT_WAKEUP_WAKEUPA_REG_MASK)
+/*! @} */
+
+/* The count of VBAT_WAKEUP_WAKEUPA */
+#define VBAT_WAKEUP_WAKEUPA_COUNT                (2U)
+
+/*! @name WAKLCKA - Wakeup Lock A */
+/*! @{ */
+
+#define VBAT_WAKLCKA_LOCK_MASK                   (0x1U)
+#define VBAT_WAKLCKA_LOCK_SHIFT                  (0U)
+/*! LOCK - Lock
+ *  0b0..Lock is disabled
+ *  0b1..Lock is enabled
+ */
+#define VBAT_WAKLCKA_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_WAKLCKA_LOCK_SHIFT)) & VBAT_WAKLCKA_LOCK_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group VBAT_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group VBAT_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_VBAT_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WAKETIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WAKETIMER.h
new file mode 100644
index 0000000000..eeb911a90d
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WAKETIMER.h
@@ -0,0 +1,189 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for WAKETIMER
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_WAKETIMER.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for WAKETIMER
+ *
+ * CMSIS Peripheral Access Layer for WAKETIMER
+ */
+
+#if !defined(PERI_WAKETIMER_H_)
+#define PERI_WAKETIMER_H_                        /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- WAKETIMER Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WAKETIMER_Peripheral_Access_Layer WAKETIMER Peripheral Access Layer
+ * @{
+ */
+
+/** WAKETIMER - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t WAKE_TIMER_CTRL;                   /**< Wake Timer Control, offset: 0x0 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t WAKE_TIMER_CNT;                    /**< Wake Timer Counter, offset: 0xC */
+} WAKETIMER_Type;
+
+/* ----------------------------------------------------------------------------
+   -- WAKETIMER Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WAKETIMER_Register_Masks WAKETIMER Register Masks
+ * @{
+ */
+
+/*! @name WAKE_TIMER_CTRL - Wake Timer Control */
+/*! @{ */
+
+#define WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_MASK (0x2U)
+#define WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT (1U)
+/*! WAKE_FLAG - Wake Timer Status Flag
+ *  0b0..Wake timer has not timed out.
+ *  0b1..Wake timer has timed out.
+ */
+#define WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG(x)   (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_MASK)
+
+#define WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK (0x4U)
+#define WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT (2U)
+/*! CLR_WAKE_TIMER - Clear Wake Timer
+ *  0b0..No effect.
+ *  0b1..Clears the wake timer counter and halts operation until a new count value is loaded.
+ */
+#define WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK)
+
+#define WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK (0x10U)
+#define WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT (4U)
+/*! OSC_DIV_ENA - OSC Divide Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK)
+
+#define WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_MASK   (0x20U)
+#define WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_SHIFT  (5U)
+/*! INTR_EN - Enable Interrupt
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define WAKETIMER_WAKE_TIMER_CTRL_INTR_EN(x)     (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_MASK)
+/*! @} */
+
+/*! @name WAKE_TIMER_CNT - Wake Timer Counter */
+/*! @{ */
+
+#define WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_MASK   (0xFFFFFFFFU)
+#define WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_SHIFT  (0U)
+/*! WAKE_CNT - Wake Counter */
+#define WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT(x)     (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_SHIFT)) & WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group WAKETIMER_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group WAKETIMER_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_WAKETIMER_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WUU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WUU.h
new file mode 100644
index 0000000000..2faeaa0ab1
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WUU.h
@@ -0,0 +1,1573 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for WUU
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_WUU.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for WUU
+ *
+ * CMSIS Peripheral Access Layer for WUU
+ */
+
+#if !defined(PERI_WUU_H_)
+#define PERI_WUU_H_                              /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- WUU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WUU_Peripheral_Access_Layer WUU Peripheral Access Layer
+ * @{
+ */
+
+/** WUU - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
+  __IO uint32_t PE1;                               /**< Pin Enable 1, offset: 0x8 */
+  __IO uint32_t PE2;                               /**< Pin Enable 2, offset: 0xC */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t ME;                                /**< Module Interrupt Enable, offset: 0x18 */
+  __IO uint32_t DE;                                /**< Module DMA/Trigger Enable, offset: 0x1C */
+  __IO uint32_t PF;                                /**< Pin Flag, offset: 0x20 */
+       uint8_t RESERVED_1[12];
+  __IO uint32_t FILT;                              /**< Pin Filter, offset: 0x30 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t PDC1;                              /**< Pin DMA/Trigger Configuration 1, offset: 0x38 */
+  __IO uint32_t PDC2;                              /**< Pin DMA/Trigger Configuration 2, offset: 0x3C */
+       uint8_t RESERVED_3[8];
+  __IO uint32_t FDC;                               /**< Pin Filter DMA/Trigger Configuration, offset: 0x48 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t PMC;                               /**< Pin Mode Configuration, offset: 0x50 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t FMC;                               /**< Pin Filter Mode Configuration, offset: 0x58 */
+} WUU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- WUU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WUU_Register_Masks WUU Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID */
+/*! @{ */
+
+#define WUU_VERID_FEATURE_MASK                   (0xFFFFU)
+#define WUU_VERID_FEATURE_SHIFT                  (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000000..Standard features implemented
+ *  0b0000000000000001..Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for
+ *                      external pin/filter detection during all power modes enabled.
+ */
+#define WUU_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_VERID_FEATURE_SHIFT)) & WUU_VERID_FEATURE_MASK)
+
+#define WUU_VERID_MINOR_MASK                     (0xFF0000U)
+#define WUU_VERID_MINOR_SHIFT                    (16U)
+/*! MINOR - Minor Version Number */
+#define WUU_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MINOR_SHIFT)) & WUU_VERID_MINOR_MASK)
+
+#define WUU_VERID_MAJOR_MASK                     (0xFF000000U)
+#define WUU_VERID_MAJOR_SHIFT                    (24U)
+/*! MAJOR - Major Version Number */
+#define WUU_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MAJOR_SHIFT)) & WUU_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter */
+/*! @{ */
+
+#define WUU_PARAM_FILTERS_MASK                   (0xFFU)
+#define WUU_PARAM_FILTERS_SHIFT                  (0U)
+/*! FILTERS - Filter Number */
+#define WUU_PARAM_FILTERS(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_FILTERS_SHIFT)) & WUU_PARAM_FILTERS_MASK)
+
+#define WUU_PARAM_DMAS_MASK                      (0xFF00U)
+#define WUU_PARAM_DMAS_SHIFT                     (8U)
+/*! DMAS - DMA Number */
+#define WUU_PARAM_DMAS(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_DMAS_SHIFT)) & WUU_PARAM_DMAS_MASK)
+
+#define WUU_PARAM_MODULES_MASK                   (0xFF0000U)
+#define WUU_PARAM_MODULES_SHIFT                  (16U)
+/*! MODULES - Module Number */
+#define WUU_PARAM_MODULES(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_MODULES_SHIFT)) & WUU_PARAM_MODULES_MASK)
+
+#define WUU_PARAM_PINS_MASK                      (0xFF000000U)
+#define WUU_PARAM_PINS_SHIFT                     (24U)
+/*! PINS - Pin Number */
+#define WUU_PARAM_PINS(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_PINS_SHIFT)) & WUU_PARAM_PINS_MASK)
+/*! @} */
+
+/*! @name PE1 - Pin Enable 1 */
+/*! @{ */
+
+#define WUU_PE1_Reserved0_MASK                   (0x3U)
+#define WUU_PE1_Reserved0_SHIFT                  (0U)
+/*! Reserved0 - Reserved
+ *  0b00..Not supported
+ *  0b01..Not supported
+ *  0b10..Not supported
+ *  0b11..Not supported
+ */
+#define WUU_PE1_Reserved0(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved0_SHIFT)) & WUU_PE1_Reserved0_MASK)
+
+#define WUU_PE1_Reserved1_MASK                   (0xCU)
+#define WUU_PE1_Reserved1_SHIFT                  (2U)
+/*! Reserved1 - Reserved
+ *  0b00..Not supported
+ *  0b01..Not supported
+ *  0b10..Not supported
+ *  0b11..Not supported
+ */
+#define WUU_PE1_Reserved1(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved1_SHIFT)) & WUU_PE1_Reserved1_MASK)
+
+#define WUU_PE1_WUPE2_MASK                       (0x30U)
+#define WUU_PE1_WUPE2_SHIFT                      (4U)
+/*! WUPE2 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE1_WUPE2(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE2_SHIFT)) & WUU_PE1_WUPE2_MASK)
+
+#define WUU_PE1_WUPE3_MASK                       (0xC0U)
+#define WUU_PE1_WUPE3_SHIFT                      (6U)
+/*! WUPE3 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE1_WUPE3(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE3_SHIFT)) & WUU_PE1_WUPE3_MASK)
+
+#define WUU_PE1_WUPE4_MASK                       (0x300U)
+#define WUU_PE1_WUPE4_SHIFT                      (8U)
+/*! WUPE4 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE1_WUPE4(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE4_SHIFT)) & WUU_PE1_WUPE4_MASK)
+
+#define WUU_PE1_WUPE5_MASK                       (0xC00U)
+#define WUU_PE1_WUPE5_SHIFT                      (10U)
+/*! WUPE5 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE1_WUPE5(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE5_SHIFT)) & WUU_PE1_WUPE5_MASK)
+
+#define WUU_PE1_WUPE6_MASK                       (0x3000U)
+#define WUU_PE1_WUPE6_SHIFT                      (12U)
+/*! WUPE6 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE1_WUPE6(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE6_SHIFT)) & WUU_PE1_WUPE6_MASK)
+
+#define WUU_PE1_WUPE7_MASK                       (0xC000U)
+#define WUU_PE1_WUPE7_SHIFT                      (14U)
+/*! WUPE7 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE1_WUPE7(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE7_SHIFT)) & WUU_PE1_WUPE7_MASK)
+
+#define WUU_PE1_WUPE8_MASK                       (0x30000U)
+#define WUU_PE1_WUPE8_SHIFT                      (16U)
+/*! WUPE8 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE1_WUPE8(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE8_SHIFT)) & WUU_PE1_WUPE8_MASK)
+
+#define WUU_PE1_WUPE9_MASK                       (0xC0000U)
+#define WUU_PE1_WUPE9_SHIFT                      (18U)
+/*! WUPE9 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE1_WUPE9(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE9_SHIFT)) & WUU_PE1_WUPE9_MASK)
+
+#define WUU_PE1_WUPE10_MASK                      (0x300000U)
+#define WUU_PE1_WUPE10_SHIFT                     (20U)
+/*! WUPE10 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE1_WUPE10(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE10_SHIFT)) & WUU_PE1_WUPE10_MASK)
+
+#define WUU_PE1_WUPE11_MASK                      (0xC00000U)
+#define WUU_PE1_WUPE11_SHIFT                     (22U)
+/*! WUPE11 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE1_WUPE11(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE11_SHIFT)) & WUU_PE1_WUPE11_MASK)
+
+#define WUU_PE1_WUPE12_MASK                      (0x3000000U)
+#define WUU_PE1_WUPE12_SHIFT                     (24U)
+/*! WUPE12 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE1_WUPE12(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE12_SHIFT)) & WUU_PE1_WUPE12_MASK)
+
+#define WUU_PE1_WUPE13_MASK                      (0xC000000U)
+#define WUU_PE1_WUPE13_SHIFT                     (26U)
+/*! WUPE13 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE1_WUPE13(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE13_SHIFT)) & WUU_PE1_WUPE13_MASK)
+
+#define WUU_PE1_Reserved14_MASK                  (0x30000000U)
+#define WUU_PE1_Reserved14_SHIFT                 (28U)
+/*! Reserved14 - Reserved
+ *  0b00..Not supported
+ *  0b01..Not supported
+ *  0b10..Not supported
+ *  0b11..Not supported
+ */
+#define WUU_PE1_Reserved14(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved14_SHIFT)) & WUU_PE1_Reserved14_MASK)
+
+#define WUU_PE1_Reserved15_MASK                  (0xC0000000U)
+#define WUU_PE1_Reserved15_SHIFT                 (30U)
+/*! Reserved15 - Reserved
+ *  0b00..Not supported
+ *  0b01..Not supported
+ *  0b10..Not supported
+ *  0b11..Not supported
+ */
+#define WUU_PE1_Reserved15(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved15_SHIFT)) & WUU_PE1_Reserved15_MASK)
+/*! @} */
+
+/*! @name PE2 - Pin Enable 2 */
+/*! @{ */
+
+#define WUU_PE2_WUPE16_MASK                      (0x3U)
+#define WUU_PE2_WUPE16_SHIFT                     (0U)
+/*! WUPE16 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE2_WUPE16(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE16_SHIFT)) & WUU_PE2_WUPE16_MASK)
+
+#define WUU_PE2_WUPE17_MASK                      (0xCU)
+#define WUU_PE2_WUPE17_SHIFT                     (2U)
+/*! WUPE17 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE2_WUPE17(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE17_SHIFT)) & WUU_PE2_WUPE17_MASK)
+
+#define WUU_PE2_WUPE18_MASK                      (0x30U)
+#define WUU_PE2_WUPE18_SHIFT                     (4U)
+/*! WUPE18 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE2_WUPE18(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE18_SHIFT)) & WUU_PE2_WUPE18_MASK)
+
+#define WUU_PE2_WUPE19_MASK                      (0xC0U)
+#define WUU_PE2_WUPE19_SHIFT                     (6U)
+/*! WUPE19 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE2_WUPE19(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE19_SHIFT)) & WUU_PE2_WUPE19_MASK)
+
+#define WUU_PE2_WUPE20_MASK                      (0x300U)
+#define WUU_PE2_WUPE20_SHIFT                     (8U)
+/*! WUPE20 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE2_WUPE20(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE20_SHIFT)) & WUU_PE2_WUPE20_MASK)
+
+#define WUU_PE2_WUPE21_MASK                      (0xC00U)
+#define WUU_PE2_WUPE21_SHIFT                     (10U)
+/*! WUPE21 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE2_WUPE21(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE21_SHIFT)) & WUU_PE2_WUPE21_MASK)
+
+#define WUU_PE2_WUPE22_MASK                      (0x3000U)
+#define WUU_PE2_WUPE22_SHIFT                     (12U)
+/*! WUPE22 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE2_WUPE22(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE22_SHIFT)) & WUU_PE2_WUPE22_MASK)
+
+#define WUU_PE2_WUPE23_MASK                      (0xC000U)
+#define WUU_PE2_WUPE23_SHIFT                     (14U)
+/*! WUPE23 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE2_WUPE23(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE23_SHIFT)) & WUU_PE2_WUPE23_MASK)
+
+#define WUU_PE2_WUPE24_MASK                      (0x30000U)
+#define WUU_PE2_WUPE24_SHIFT                     (16U)
+/*! WUPE24 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE2_WUPE24(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE24_SHIFT)) & WUU_PE2_WUPE24_MASK)
+
+#define WUU_PE2_WUPE25_MASK                      (0xC0000U)
+#define WUU_PE2_WUPE25_SHIFT                     (18U)
+/*! WUPE25 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE2_WUPE25(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE25_SHIFT)) & WUU_PE2_WUPE25_MASK)
+
+#define WUU_PE2_WUPE26_MASK                      (0x300000U)
+#define WUU_PE2_WUPE26_SHIFT                     (20U)
+/*! WUPE26 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE2_WUPE26(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE26_SHIFT)) & WUU_PE2_WUPE26_MASK)
+
+#define WUU_PE2_WUPE27_MASK                      (0xC00000U)
+#define WUU_PE2_WUPE27_SHIFT                     (22U)
+/*! WUPE27 - Wake-up Pin Enable for WUU_Pn
+ *  0b00..Disable
+ *  0b01..Enable (detect on rising edge or high level)
+ *  0b10..Enable (detect on falling edge or low level)
+ *  0b11..Enable (detect on any edge)
+ */
+#define WUU_PE2_WUPE27(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE27_SHIFT)) & WUU_PE2_WUPE27_MASK)
+
+#define WUU_PE2_Reserved28_MASK                  (0x3000000U)
+#define WUU_PE2_Reserved28_SHIFT                 (24U)
+/*! Reserved28 - Reserved
+ *  0b00..Not supported
+ *  0b01..Not supported
+ *  0b10..Not supported
+ *  0b11..Not supported
+ */
+#define WUU_PE2_Reserved28(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved28_SHIFT)) & WUU_PE2_Reserved28_MASK)
+
+#define WUU_PE2_Reserved29_MASK                  (0xC000000U)
+#define WUU_PE2_Reserved29_SHIFT                 (26U)
+/*! Reserved29 - Reserved
+ *  0b00..Not supported
+ *  0b01..Not supported
+ *  0b10..Not supported
+ *  0b11..Not supported
+ */
+#define WUU_PE2_Reserved29(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved29_SHIFT)) & WUU_PE2_Reserved29_MASK)
+
+#define WUU_PE2_WUPE30_MASK                      (0x30000000U)
+#define WUU_PE2_WUPE30_SHIFT                     (28U)
+/*! WUPE30 - Reserved
+ *  0b00..Not supported
+ *  0b01..Not supported
+ *  0b10..Not supported
+ *  0b11..Not supported
+ */
+#define WUU_PE2_WUPE30(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE30_SHIFT)) & WUU_PE2_WUPE30_MASK)
+
+#define WUU_PE2_WUPE31_MASK                      (0xC0000000U)
+#define WUU_PE2_WUPE31_SHIFT                     (30U)
+/*! WUPE31 - Reserved
+ *  0b00..Not supported
+ *  0b01..Not supported
+ *  0b10..Not supported
+ *  0b11..Not supported
+ */
+#define WUU_PE2_WUPE31(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE31_SHIFT)) & WUU_PE2_WUPE31_MASK)
+/*! @} */
+
+/*! @name ME - Module Interrupt Enable */
+/*! @{ */
+
+#define WUU_ME_WUME0_MASK                        (0x1U)
+#define WUU_ME_WUME0_SHIFT                       (0U)
+/*! WUME0 - Module Interrupt Wake-up Enable for Module 0
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define WUU_ME_WUME0(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME0_SHIFT)) & WUU_ME_WUME0_MASK)
+
+#define WUU_ME_WUME1_MASK                        (0x2U)
+#define WUU_ME_WUME1_SHIFT                       (1U)
+/*! WUME1 - Module Interrupt Wake-up Enable for Module 1
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define WUU_ME_WUME1(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME1_SHIFT)) & WUU_ME_WUME1_MASK)
+
+#define WUU_ME_WUME2_MASK                        (0x4U)
+#define WUU_ME_WUME2_SHIFT                       (2U)
+/*! WUME2 - Module Interrupt Wake-up Enable for Module 2
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define WUU_ME_WUME2(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME2_SHIFT)) & WUU_ME_WUME2_MASK)
+
+#define WUU_ME_WUME6_MASK                        (0x40U)
+#define WUU_ME_WUME6_SHIFT                       (6U)
+/*! WUME6 - Module Interrupt Wake-up Enable for Module 6
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define WUU_ME_WUME6(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME6_SHIFT)) & WUU_ME_WUME6_MASK)
+
+#define WUU_ME_WUME8_MASK                        (0x100U)
+#define WUU_ME_WUME8_SHIFT                       (8U)
+/*! WUME8 - Module Interrupt Wake-up Enable for Module 8
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define WUU_ME_WUME8(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME8_SHIFT)) & WUU_ME_WUME8_MASK)
+/*! @} */
+
+/*! @name DE - Module DMA/Trigger Enable */
+/*! @{ */
+
+#define WUU_DE_WUDE4_MASK                        (0x10U)
+#define WUU_DE_WUDE4_SHIFT                       (4U)
+/*! WUDE4 - DMA/Trigger Wake-up Enable for Module 4
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define WUU_DE_WUDE4(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE4_SHIFT)) & WUU_DE_WUDE4_MASK)
+
+#define WUU_DE_WUDE6_MASK                        (0x40U)
+#define WUU_DE_WUDE6_SHIFT                       (6U)
+/*! WUDE6 - DMA/Trigger Wake-up Enable for Module 6
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define WUU_DE_WUDE6(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE6_SHIFT)) & WUU_DE_WUDE6_MASK)
+
+#define WUU_DE_WUDE8_MASK                        (0x100U)
+#define WUU_DE_WUDE8_SHIFT                       (8U)
+/*! WUDE8 - DMA/Trigger Wake-up Enable for Module 8
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define WUU_DE_WUDE8(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE8_SHIFT)) & WUU_DE_WUDE8_MASK)
+/*! @} */
+
+/*! @name PF - Pin Flag */
+/*! @{ */
+
+#define WUU_PF_Reserved0_MASK                    (0x1U)
+#define WUU_PF_Reserved0_SHIFT                   (0U)
+/*! Reserved0 - Reserved
+ *  0b0..Not supported
+ *  0b1..Not supported
+ */
+#define WUU_PF_Reserved0(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved0_SHIFT)) & WUU_PF_Reserved0_MASK)
+
+#define WUU_PF_Reserved1_MASK                    (0x2U)
+#define WUU_PF_Reserved1_SHIFT                   (1U)
+/*! Reserved1 - Reserved
+ *  0b0..Not supported
+ *  0b1..Not supported
+ */
+#define WUU_PF_Reserved1(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved1_SHIFT)) & WUU_PF_Reserved1_MASK)
+
+#define WUU_PF_WUF2_MASK                         (0x4U)
+#define WUU_PF_WUF2_SHIFT                        (2U)
+/*! WUF2 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF2(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF2_SHIFT)) & WUU_PF_WUF2_MASK)
+
+#define WUU_PF_WUF3_MASK                         (0x8U)
+#define WUU_PF_WUF3_SHIFT                        (3U)
+/*! WUF3 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF3(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF3_SHIFT)) & WUU_PF_WUF3_MASK)
+
+#define WUU_PF_WUF4_MASK                         (0x10U)
+#define WUU_PF_WUF4_SHIFT                        (4U)
+/*! WUF4 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF4(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF4_SHIFT)) & WUU_PF_WUF4_MASK)
+
+#define WUU_PF_WUF5_MASK                         (0x20U)
+#define WUU_PF_WUF5_SHIFT                        (5U)
+/*! WUF5 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF5(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF5_SHIFT)) & WUU_PF_WUF5_MASK)
+
+#define WUU_PF_WUF6_MASK                         (0x40U)
+#define WUU_PF_WUF6_SHIFT                        (6U)
+/*! WUF6 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF6(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF6_SHIFT)) & WUU_PF_WUF6_MASK)
+
+#define WUU_PF_WUF7_MASK                         (0x80U)
+#define WUU_PF_WUF7_SHIFT                        (7U)
+/*! WUF7 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF7(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF7_SHIFT)) & WUU_PF_WUF7_MASK)
+
+#define WUU_PF_WUF8_MASK                         (0x100U)
+#define WUU_PF_WUF8_SHIFT                        (8U)
+/*! WUF8 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF8(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF8_SHIFT)) & WUU_PF_WUF8_MASK)
+
+#define WUU_PF_WUF9_MASK                         (0x200U)
+#define WUU_PF_WUF9_SHIFT                        (9U)
+/*! WUF9 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF9(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF9_SHIFT)) & WUU_PF_WUF9_MASK)
+
+#define WUU_PF_WUF10_MASK                        (0x400U)
+#define WUU_PF_WUF10_SHIFT                       (10U)
+/*! WUF10 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF10(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF10_SHIFT)) & WUU_PF_WUF10_MASK)
+
+#define WUU_PF_WUF11_MASK                        (0x800U)
+#define WUU_PF_WUF11_SHIFT                       (11U)
+/*! WUF11 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF11(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF11_SHIFT)) & WUU_PF_WUF11_MASK)
+
+#define WUU_PF_WUF12_MASK                        (0x1000U)
+#define WUU_PF_WUF12_SHIFT                       (12U)
+/*! WUF12 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF12(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF12_SHIFT)) & WUU_PF_WUF12_MASK)
+
+#define WUU_PF_WUF13_MASK                        (0x2000U)
+#define WUU_PF_WUF13_SHIFT                       (13U)
+/*! WUF13 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF13(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF13_SHIFT)) & WUU_PF_WUF13_MASK)
+
+#define WUU_PF_Reserved14_MASK                   (0x4000U)
+#define WUU_PF_Reserved14_SHIFT                  (14U)
+/*! Reserved14 - Reserved
+ *  0b0..Not supported
+ *  0b1..Not supported
+ */
+#define WUU_PF_Reserved14(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved14_SHIFT)) & WUU_PF_Reserved14_MASK)
+
+#define WUU_PF_Reserved15_MASK                   (0x8000U)
+#define WUU_PF_Reserved15_SHIFT                  (15U)
+/*! Reserved15 - Reserved
+ *  0b0..Not supported
+ *  0b1..Not supported
+ */
+#define WUU_PF_Reserved15(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved15_SHIFT)) & WUU_PF_Reserved15_MASK)
+
+#define WUU_PF_WUF16_MASK                        (0x10000U)
+#define WUU_PF_WUF16_SHIFT                       (16U)
+/*! WUF16 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF16(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF16_SHIFT)) & WUU_PF_WUF16_MASK)
+
+#define WUU_PF_WUF17_MASK                        (0x20000U)
+#define WUU_PF_WUF17_SHIFT                       (17U)
+/*! WUF17 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF17(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF17_SHIFT)) & WUU_PF_WUF17_MASK)
+
+#define WUU_PF_WUF18_MASK                        (0x40000U)
+#define WUU_PF_WUF18_SHIFT                       (18U)
+/*! WUF18 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF18(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF18_SHIFT)) & WUU_PF_WUF18_MASK)
+
+#define WUU_PF_WUF19_MASK                        (0x80000U)
+#define WUU_PF_WUF19_SHIFT                       (19U)
+/*! WUF19 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF19(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF19_SHIFT)) & WUU_PF_WUF19_MASK)
+
+#define WUU_PF_WUF20_MASK                        (0x100000U)
+#define WUU_PF_WUF20_SHIFT                       (20U)
+/*! WUF20 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF20(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF20_SHIFT)) & WUU_PF_WUF20_MASK)
+
+#define WUU_PF_WUF21_MASK                        (0x200000U)
+#define WUU_PF_WUF21_SHIFT                       (21U)
+/*! WUF21 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF21(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF21_SHIFT)) & WUU_PF_WUF21_MASK)
+
+#define WUU_PF_WUF22_MASK                        (0x400000U)
+#define WUU_PF_WUF22_SHIFT                       (22U)
+/*! WUF22 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF22(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF22_SHIFT)) & WUU_PF_WUF22_MASK)
+
+#define WUU_PF_WUF23_MASK                        (0x800000U)
+#define WUU_PF_WUF23_SHIFT                       (23U)
+/*! WUF23 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF23(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF23_SHIFT)) & WUU_PF_WUF23_MASK)
+
+#define WUU_PF_WUF24_MASK                        (0x1000000U)
+#define WUU_PF_WUF24_SHIFT                       (24U)
+/*! WUF24 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF24(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF24_SHIFT)) & WUU_PF_WUF24_MASK)
+
+#define WUU_PF_WUF25_MASK                        (0x2000000U)
+#define WUU_PF_WUF25_SHIFT                       (25U)
+/*! WUF25 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF25(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF25_SHIFT)) & WUU_PF_WUF25_MASK)
+
+#define WUU_PF_WUF26_MASK                        (0x4000000U)
+#define WUU_PF_WUF26_SHIFT                       (26U)
+/*! WUF26 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF26(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF26_SHIFT)) & WUU_PF_WUF26_MASK)
+
+#define WUU_PF_WUF27_MASK                        (0x8000000U)
+#define WUU_PF_WUF27_SHIFT                       (27U)
+/*! WUF27 - Wake-up Flag for WUU_Pn
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_PF_WUF27(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF27_SHIFT)) & WUU_PF_WUF27_MASK)
+
+#define WUU_PF_Reserved28_MASK                   (0x10000000U)
+#define WUU_PF_Reserved28_SHIFT                  (28U)
+/*! Reserved28 - Reserved
+ *  0b0..Not supported
+ *  0b1..Not supported
+ */
+#define WUU_PF_Reserved28(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved28_SHIFT)) & WUU_PF_Reserved28_MASK)
+
+#define WUU_PF_Reserved29_MASK                   (0x20000000U)
+#define WUU_PF_Reserved29_SHIFT                  (29U)
+/*! Reserved29 - Reserved
+ *  0b0..Not supported
+ *  0b1..Not supported
+ */
+#define WUU_PF_Reserved29(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved29_SHIFT)) & WUU_PF_Reserved29_MASK)
+
+#define WUU_PF_WUF30_MASK                        (0x40000000U)
+#define WUU_PF_WUF30_SHIFT                       (30U)
+/*! WUF30 - Reserved
+ *  0b0..Not supported
+ *  0b1..Not supported
+ */
+#define WUU_PF_WUF30(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF30_SHIFT)) & WUU_PF_WUF30_MASK)
+
+#define WUU_PF_WUF31_MASK                        (0x80000000U)
+#define WUU_PF_WUF31_SHIFT                       (31U)
+/*! WUF31 - Reserved
+ *  0b0..Not supported
+ *  0b1..Not supported
+ */
+#define WUU_PF_WUF31(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF31_SHIFT)) & WUU_PF_WUF31_MASK)
+/*! @} */
+
+/*! @name FILT - Pin Filter */
+/*! @{ */
+
+#define WUU_FILT_FILTSEL1_MASK                   (0x1FU)
+#define WUU_FILT_FILTSEL1_SHIFT                  (0U)
+/*! FILTSEL1 - Filter 1 Pin Select */
+#define WUU_FILT_FILTSEL1(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL1_SHIFT)) & WUU_FILT_FILTSEL1_MASK)
+
+#define WUU_FILT_FILTE1_MASK                     (0x60U)
+#define WUU_FILT_FILTE1_SHIFT                    (5U)
+/*! FILTE1 - Filter 1 Enable
+ *  0b00..Disable
+ *  0b01..Enable (Detect on rising edge or high level)
+ *  0b10..Enable (Detect on falling edge or low level)
+ *  0b11..Enable (Detect on any edge)
+ */
+#define WUU_FILT_FILTE1(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE1_SHIFT)) & WUU_FILT_FILTE1_MASK)
+
+#define WUU_FILT_FILTF1_MASK                     (0x80U)
+#define WUU_FILT_FILTF1_SHIFT                    (7U)
+/*! FILTF1 - Filter 1 Flag
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_FILT_FILTF1(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF1_SHIFT)) & WUU_FILT_FILTF1_MASK)
+
+#define WUU_FILT_FILTSEL2_MASK                   (0x1F00U)
+#define WUU_FILT_FILTSEL2_SHIFT                  (8U)
+/*! FILTSEL2 - Filter 2 Pin Select */
+#define WUU_FILT_FILTSEL2(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL2_SHIFT)) & WUU_FILT_FILTSEL2_MASK)
+
+#define WUU_FILT_FILTE2_MASK                     (0x6000U)
+#define WUU_FILT_FILTE2_SHIFT                    (13U)
+/*! FILTE2 - Filter 2 Enable
+ *  0b00..Disable
+ *  0b01..Enable (Detect on rising edge or high level)
+ *  0b10..Enable (Detect on falling edge or low level)
+ *  0b11..Enable (Detect on any edge)
+ */
+#define WUU_FILT_FILTE2(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE2_SHIFT)) & WUU_FILT_FILTE2_MASK)
+
+#define WUU_FILT_FILTF2_MASK                     (0x8000U)
+#define WUU_FILT_FILTF2_SHIFT                    (15U)
+/*! FILTF2 - Filter 2 Flag
+ *  0b0..No
+ *  0b1..Yes
+ */
+#define WUU_FILT_FILTF2(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF2_SHIFT)) & WUU_FILT_FILTF2_MASK)
+/*! @} */
+
+/*! @name PDC1 - Pin DMA/Trigger Configuration 1 */
+/*! @{ */
+
+#define WUU_PDC1_Reserved0_MASK                  (0x3U)
+#define WUU_PDC1_Reserved0_SHIFT                 (0U)
+/*! Reserved0 - Reserved
+ *  0b00..Not supported
+ *  0b01..Not supported
+ *  0b10..Not supported
+ *  0b11..Not supported
+ */
+#define WUU_PDC1_Reserved0(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved0_SHIFT)) & WUU_PDC1_Reserved0_MASK)
+
+#define WUU_PDC1_Reserved1_MASK                  (0xCU)
+#define WUU_PDC1_Reserved1_SHIFT                 (2U)
+/*! Reserved1 - Reserved
+ *  0b00..Not supported
+ *  0b01..Not supported
+ *  0b10..Not supported
+ *  0b11..Not supported
+ */
+#define WUU_PDC1_Reserved1(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved1_SHIFT)) & WUU_PDC1_Reserved1_MASK)
+
+#define WUU_PDC1_WUPDC2_MASK                     (0x30U)
+#define WUU_PDC1_WUPDC2_SHIFT                    (4U)
+/*! WUPDC2 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC1_WUPDC2(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC2_SHIFT)) & WUU_PDC1_WUPDC2_MASK)
+
+#define WUU_PDC1_WUPDC3_MASK                     (0xC0U)
+#define WUU_PDC1_WUPDC3_SHIFT                    (6U)
+/*! WUPDC3 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC1_WUPDC3(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC3_SHIFT)) & WUU_PDC1_WUPDC3_MASK)
+
+#define WUU_PDC1_WUPDC4_MASK                     (0x300U)
+#define WUU_PDC1_WUPDC4_SHIFT                    (8U)
+/*! WUPDC4 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC1_WUPDC4(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC4_SHIFT)) & WUU_PDC1_WUPDC4_MASK)
+
+#define WUU_PDC1_WUPDC5_MASK                     (0xC00U)
+#define WUU_PDC1_WUPDC5_SHIFT                    (10U)
+/*! WUPDC5 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC1_WUPDC5(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC5_SHIFT)) & WUU_PDC1_WUPDC5_MASK)
+
+#define WUU_PDC1_WUPDC6_MASK                     (0x3000U)
+#define WUU_PDC1_WUPDC6_SHIFT                    (12U)
+/*! WUPDC6 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC1_WUPDC6(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC6_SHIFT)) & WUU_PDC1_WUPDC6_MASK)
+
+#define WUU_PDC1_WUPDC7_MASK                     (0xC000U)
+#define WUU_PDC1_WUPDC7_SHIFT                    (14U)
+/*! WUPDC7 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC1_WUPDC7(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC7_SHIFT)) & WUU_PDC1_WUPDC7_MASK)
+
+#define WUU_PDC1_WUPDC8_MASK                     (0x30000U)
+#define WUU_PDC1_WUPDC8_SHIFT                    (16U)
+/*! WUPDC8 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC1_WUPDC8(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC8_SHIFT)) & WUU_PDC1_WUPDC8_MASK)
+
+#define WUU_PDC1_WUPDC9_MASK                     (0xC0000U)
+#define WUU_PDC1_WUPDC9_SHIFT                    (18U)
+/*! WUPDC9 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC1_WUPDC9(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC9_SHIFT)) & WUU_PDC1_WUPDC9_MASK)
+
+#define WUU_PDC1_WUPDC10_MASK                    (0x300000U)
+#define WUU_PDC1_WUPDC10_SHIFT                   (20U)
+/*! WUPDC10 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC1_WUPDC10(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC10_SHIFT)) & WUU_PDC1_WUPDC10_MASK)
+
+#define WUU_PDC1_WUPDC11_MASK                    (0xC00000U)
+#define WUU_PDC1_WUPDC11_SHIFT                   (22U)
+/*! WUPDC11 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC1_WUPDC11(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC11_SHIFT)) & WUU_PDC1_WUPDC11_MASK)
+
+#define WUU_PDC1_WUPDC12_MASK                    (0x3000000U)
+#define WUU_PDC1_WUPDC12_SHIFT                   (24U)
+/*! WUPDC12 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC1_WUPDC12(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC12_SHIFT)) & WUU_PDC1_WUPDC12_MASK)
+
+#define WUU_PDC1_WUPDC13_MASK                    (0xC000000U)
+#define WUU_PDC1_WUPDC13_SHIFT                   (26U)
+/*! WUPDC13 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC1_WUPDC13(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC13_SHIFT)) & WUU_PDC1_WUPDC13_MASK)
+
+#define WUU_PDC1_Reserved14_MASK                 (0x30000000U)
+#define WUU_PDC1_Reserved14_SHIFT                (28U)
+/*! Reserved14 - Reserved
+ *  0b00..Not supported
+ *  0b01..Not supported
+ *  0b10..Not supported
+ *  0b11..Not supported
+ */
+#define WUU_PDC1_Reserved14(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved14_SHIFT)) & WUU_PDC1_Reserved14_MASK)
+
+#define WUU_PDC1_Reserved15_MASK                 (0xC0000000U)
+#define WUU_PDC1_Reserved15_SHIFT                (30U)
+/*! Reserved15 - Reserved
+ *  0b00..Not supported
+ *  0b01..Not supported
+ *  0b10..Not supported
+ *  0b11..Not supported
+ */
+#define WUU_PDC1_Reserved15(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved15_SHIFT)) & WUU_PDC1_Reserved15_MASK)
+/*! @} */
+
+/*! @name PDC2 - Pin DMA/Trigger Configuration 2 */
+/*! @{ */
+
+#define WUU_PDC2_WUPDC16_MASK                    (0x3U)
+#define WUU_PDC2_WUPDC16_SHIFT                   (0U)
+/*! WUPDC16 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC2_WUPDC16(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC16_SHIFT)) & WUU_PDC2_WUPDC16_MASK)
+
+#define WUU_PDC2_WUPDC17_MASK                    (0xCU)
+#define WUU_PDC2_WUPDC17_SHIFT                   (2U)
+/*! WUPDC17 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC2_WUPDC17(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC17_SHIFT)) & WUU_PDC2_WUPDC17_MASK)
+
+#define WUU_PDC2_WUPDC18_MASK                    (0x30U)
+#define WUU_PDC2_WUPDC18_SHIFT                   (4U)
+/*! WUPDC18 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC2_WUPDC18(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC18_SHIFT)) & WUU_PDC2_WUPDC18_MASK)
+
+#define WUU_PDC2_WUPDC19_MASK                    (0xC0U)
+#define WUU_PDC2_WUPDC19_SHIFT                   (6U)
+/*! WUPDC19 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC2_WUPDC19(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC19_SHIFT)) & WUU_PDC2_WUPDC19_MASK)
+
+#define WUU_PDC2_WUPDC20_MASK                    (0x300U)
+#define WUU_PDC2_WUPDC20_SHIFT                   (8U)
+/*! WUPDC20 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC2_WUPDC20(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC20_SHIFT)) & WUU_PDC2_WUPDC20_MASK)
+
+#define WUU_PDC2_WUPDC21_MASK                    (0xC00U)
+#define WUU_PDC2_WUPDC21_SHIFT                   (10U)
+/*! WUPDC21 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC2_WUPDC21(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC21_SHIFT)) & WUU_PDC2_WUPDC21_MASK)
+
+#define WUU_PDC2_WUPDC22_MASK                    (0x3000U)
+#define WUU_PDC2_WUPDC22_SHIFT                   (12U)
+/*! WUPDC22 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC2_WUPDC22(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC22_SHIFT)) & WUU_PDC2_WUPDC22_MASK)
+
+#define WUU_PDC2_WUPDC23_MASK                    (0xC000U)
+#define WUU_PDC2_WUPDC23_SHIFT                   (14U)
+/*! WUPDC23 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC2_WUPDC23(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC23_SHIFT)) & WUU_PDC2_WUPDC23_MASK)
+
+#define WUU_PDC2_WUPDC24_MASK                    (0x30000U)
+#define WUU_PDC2_WUPDC24_SHIFT                   (16U)
+/*! WUPDC24 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC2_WUPDC24(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC24_SHIFT)) & WUU_PDC2_WUPDC24_MASK)
+
+#define WUU_PDC2_WUPDC25_MASK                    (0xC0000U)
+#define WUU_PDC2_WUPDC25_SHIFT                   (18U)
+/*! WUPDC25 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC2_WUPDC25(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC25_SHIFT)) & WUU_PDC2_WUPDC25_MASK)
+
+#define WUU_PDC2_WUPDC26_MASK                    (0x300000U)
+#define WUU_PDC2_WUPDC26_SHIFT                   (20U)
+/*! WUPDC26 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC2_WUPDC26(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC26_SHIFT)) & WUU_PDC2_WUPDC26_MASK)
+
+#define WUU_PDC2_WUPDC27_MASK                    (0xC00000U)
+#define WUU_PDC2_WUPDC27_SHIFT                   (22U)
+/*! WUPDC27 - Wake-up Pin Configuration for WUU_Pn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_PDC2_WUPDC27(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC27_SHIFT)) & WUU_PDC2_WUPDC27_MASK)
+
+#define WUU_PDC2_Reserved28_MASK                 (0x3000000U)
+#define WUU_PDC2_Reserved28_SHIFT                (24U)
+/*! Reserved28 - Reserved
+ *  0b00..Not supported
+ *  0b01..Not supported
+ *  0b10..Not supported
+ *  0b11..Not supported
+ */
+#define WUU_PDC2_Reserved28(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved28_SHIFT)) & WUU_PDC2_Reserved28_MASK)
+
+#define WUU_PDC2_Reserved29_MASK                 (0xC000000U)
+#define WUU_PDC2_Reserved29_SHIFT                (26U)
+/*! Reserved29 - Reserved
+ *  0b00..Not supported
+ *  0b01..Not supported
+ *  0b10..Not supported
+ *  0b11..Not supported
+ */
+#define WUU_PDC2_Reserved29(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved29_SHIFT)) & WUU_PDC2_Reserved29_MASK)
+
+#define WUU_PDC2_WUPDC30_MASK                    (0x30000000U)
+#define WUU_PDC2_WUPDC30_SHIFT                   (28U)
+/*! WUPDC30 - Reserved
+ *  0b00..Not supported
+ *  0b01..Not supported
+ *  0b10..Not supported
+ *  0b11..Reserved
+ */
+#define WUU_PDC2_WUPDC30(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC30_SHIFT)) & WUU_PDC2_WUPDC30_MASK)
+
+#define WUU_PDC2_WUPDC31_MASK                    (0xC0000000U)
+#define WUU_PDC2_WUPDC31_SHIFT                   (30U)
+/*! WUPDC31 - Reserved
+ *  0b00..Not supported
+ *  0b01..Not supported
+ *  0b10..Not supported
+ *  0b11..Reserved
+ */
+#define WUU_PDC2_WUPDC31(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC31_SHIFT)) & WUU_PDC2_WUPDC31_MASK)
+/*! @} */
+
+/*! @name FDC - Pin Filter DMA/Trigger Configuration */
+/*! @{ */
+
+#define WUU_FDC_FILTC1_MASK                      (0x3U)
+#define WUU_FDC_FILTC1_SHIFT                     (0U)
+/*! FILTC1 - Filter Configuration for FILTn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_FDC_FILTC1(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC1_SHIFT)) & WUU_FDC_FILTC1_MASK)
+
+#define WUU_FDC_FILTC2_MASK                      (0xCU)
+#define WUU_FDC_FILTC2_SHIFT                     (2U)
+/*! FILTC2 - Filter Configuration for FILTn
+ *  0b00..Interrupt
+ *  0b01..DMA request
+ *  0b10..Trigger event
+ *  0b11..Reserved
+ */
+#define WUU_FDC_FILTC2(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC2_SHIFT)) & WUU_FDC_FILTC2_MASK)
+/*! @} */
+
+/*! @name PMC - Pin Mode Configuration */
+/*! @{ */
+
+#define WUU_PMC_Reserved0_MASK                   (0x1U)
+#define WUU_PMC_Reserved0_SHIFT                  (0U)
+/*! Reserved0 - Reserved
+ *  0b0..Not supported
+ *  0b1..Not supported
+ */
+#define WUU_PMC_Reserved0(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved0_SHIFT)) & WUU_PMC_Reserved0_MASK)
+
+#define WUU_PMC_Reserved1_MASK                   (0x2U)
+#define WUU_PMC_Reserved1_SHIFT                  (1U)
+/*! Reserved1 - Reserved
+ *  0b0..Not supported
+ *  0b1..Not supported
+ */
+#define WUU_PMC_Reserved1(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved1_SHIFT)) & WUU_PMC_Reserved1_MASK)
+
+#define WUU_PMC_WUPMC2_MASK                      (0x4U)
+#define WUU_PMC_WUPMC2_SHIFT                     (2U)
+/*! WUPMC2 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC2(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC2_SHIFT)) & WUU_PMC_WUPMC2_MASK)
+
+#define WUU_PMC_WUPMC3_MASK                      (0x8U)
+#define WUU_PMC_WUPMC3_SHIFT                     (3U)
+/*! WUPMC3 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC3(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC3_SHIFT)) & WUU_PMC_WUPMC3_MASK)
+
+#define WUU_PMC_WUPMC4_MASK                      (0x10U)
+#define WUU_PMC_WUPMC4_SHIFT                     (4U)
+/*! WUPMC4 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC4(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC4_SHIFT)) & WUU_PMC_WUPMC4_MASK)
+
+#define WUU_PMC_WUPMC5_MASK                      (0x20U)
+#define WUU_PMC_WUPMC5_SHIFT                     (5U)
+/*! WUPMC5 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC5(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC5_SHIFT)) & WUU_PMC_WUPMC5_MASK)
+
+#define WUU_PMC_WUPMC6_MASK                      (0x40U)
+#define WUU_PMC_WUPMC6_SHIFT                     (6U)
+/*! WUPMC6 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC6(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC6_SHIFT)) & WUU_PMC_WUPMC6_MASK)
+
+#define WUU_PMC_WUPMC7_MASK                      (0x80U)
+#define WUU_PMC_WUPMC7_SHIFT                     (7U)
+/*! WUPMC7 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC7(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC7_SHIFT)) & WUU_PMC_WUPMC7_MASK)
+
+#define WUU_PMC_WUPMC8_MASK                      (0x100U)
+#define WUU_PMC_WUPMC8_SHIFT                     (8U)
+/*! WUPMC8 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC8(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC8_SHIFT)) & WUU_PMC_WUPMC8_MASK)
+
+#define WUU_PMC_WUPMC9_MASK                      (0x200U)
+#define WUU_PMC_WUPMC9_SHIFT                     (9U)
+/*! WUPMC9 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC9(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC9_SHIFT)) & WUU_PMC_WUPMC9_MASK)
+
+#define WUU_PMC_WUPMC10_MASK                     (0x400U)
+#define WUU_PMC_WUPMC10_SHIFT                    (10U)
+/*! WUPMC10 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC10(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC10_SHIFT)) & WUU_PMC_WUPMC10_MASK)
+
+#define WUU_PMC_WUPMC11_MASK                     (0x800U)
+#define WUU_PMC_WUPMC11_SHIFT                    (11U)
+/*! WUPMC11 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC11(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC11_SHIFT)) & WUU_PMC_WUPMC11_MASK)
+
+#define WUU_PMC_WUPMC12_MASK                     (0x1000U)
+#define WUU_PMC_WUPMC12_SHIFT                    (12U)
+/*! WUPMC12 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC12(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC12_SHIFT)) & WUU_PMC_WUPMC12_MASK)
+
+#define WUU_PMC_WUPMC13_MASK                     (0x2000U)
+#define WUU_PMC_WUPMC13_SHIFT                    (13U)
+/*! WUPMC13 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC13(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC13_SHIFT)) & WUU_PMC_WUPMC13_MASK)
+
+#define WUU_PMC_Reserved14_MASK                  (0x4000U)
+#define WUU_PMC_Reserved14_SHIFT                 (14U)
+/*! Reserved14 - Reserved
+ *  0b0..Not supported
+ *  0b1..Not supported
+ */
+#define WUU_PMC_Reserved14(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved14_SHIFT)) & WUU_PMC_Reserved14_MASK)
+
+#define WUU_PMC_Reserved15_MASK                  (0x8000U)
+#define WUU_PMC_Reserved15_SHIFT                 (15U)
+/*! Reserved15 - Reserved
+ *  0b0..Not supported
+ *  0b1..Not supported
+ */
+#define WUU_PMC_Reserved15(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved15_SHIFT)) & WUU_PMC_Reserved15_MASK)
+
+#define WUU_PMC_WUPMC16_MASK                     (0x10000U)
+#define WUU_PMC_WUPMC16_SHIFT                    (16U)
+/*! WUPMC16 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC16(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC16_SHIFT)) & WUU_PMC_WUPMC16_MASK)
+
+#define WUU_PMC_WUPMC17_MASK                     (0x20000U)
+#define WUU_PMC_WUPMC17_SHIFT                    (17U)
+/*! WUPMC17 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC17(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC17_SHIFT)) & WUU_PMC_WUPMC17_MASK)
+
+#define WUU_PMC_WUPMC18_MASK                     (0x40000U)
+#define WUU_PMC_WUPMC18_SHIFT                    (18U)
+/*! WUPMC18 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC18(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC18_SHIFT)) & WUU_PMC_WUPMC18_MASK)
+
+#define WUU_PMC_WUPMC19_MASK                     (0x80000U)
+#define WUU_PMC_WUPMC19_SHIFT                    (19U)
+/*! WUPMC19 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC19(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC19_SHIFT)) & WUU_PMC_WUPMC19_MASK)
+
+#define WUU_PMC_WUPMC20_MASK                     (0x100000U)
+#define WUU_PMC_WUPMC20_SHIFT                    (20U)
+/*! WUPMC20 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC20(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC20_SHIFT)) & WUU_PMC_WUPMC20_MASK)
+
+#define WUU_PMC_WUPMC21_MASK                     (0x200000U)
+#define WUU_PMC_WUPMC21_SHIFT                    (21U)
+/*! WUPMC21 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC21(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC21_SHIFT)) & WUU_PMC_WUPMC21_MASK)
+
+#define WUU_PMC_WUPMC22_MASK                     (0x400000U)
+#define WUU_PMC_WUPMC22_SHIFT                    (22U)
+/*! WUPMC22 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC22(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC22_SHIFT)) & WUU_PMC_WUPMC22_MASK)
+
+#define WUU_PMC_WUPMC23_MASK                     (0x800000U)
+#define WUU_PMC_WUPMC23_SHIFT                    (23U)
+/*! WUPMC23 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC23(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC23_SHIFT)) & WUU_PMC_WUPMC23_MASK)
+
+#define WUU_PMC_WUPMC24_MASK                     (0x1000000U)
+#define WUU_PMC_WUPMC24_SHIFT                    (24U)
+/*! WUPMC24 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC24(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC24_SHIFT)) & WUU_PMC_WUPMC24_MASK)
+
+#define WUU_PMC_WUPMC25_MASK                     (0x2000000U)
+#define WUU_PMC_WUPMC25_SHIFT                    (25U)
+/*! WUPMC25 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC25(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC25_SHIFT)) & WUU_PMC_WUPMC25_MASK)
+
+#define WUU_PMC_WUPMC26_MASK                     (0x4000000U)
+#define WUU_PMC_WUPMC26_SHIFT                    (26U)
+/*! WUPMC26 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC26(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC26_SHIFT)) & WUU_PMC_WUPMC26_MASK)
+
+#define WUU_PMC_WUPMC27_MASK                     (0x8000000U)
+#define WUU_PMC_WUPMC27_SHIFT                    (27U)
+/*! WUPMC27 - Wake-up Pin Mode Configuration for WUU_Pn
+ *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
+ *       Pin DMA/Trigger Configuration (PDCn).
+ *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
+ */
+#define WUU_PMC_WUPMC27(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC27_SHIFT)) & WUU_PMC_WUPMC27_MASK)
+
+#define WUU_PMC_Reserved28_MASK                  (0x10000000U)
+#define WUU_PMC_Reserved28_SHIFT                 (28U)
+/*! Reserved28 - Reserved
+ *  0b0..Not supported
+ *  0b1..Not supported
+ */
+#define WUU_PMC_Reserved28(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved28_SHIFT)) & WUU_PMC_Reserved28_MASK)
+
+#define WUU_PMC_Reserved29_MASK                  (0x20000000U)
+#define WUU_PMC_Reserved29_SHIFT                 (29U)
+/*! Reserved29 - Reserved
+ *  0b0..Not supported
+ *  0b1..Not supported
+ */
+#define WUU_PMC_Reserved29(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved29_SHIFT)) & WUU_PMC_Reserved29_MASK)
+
+#define WUU_PMC_WUPMC30_MASK                     (0x40000000U)
+#define WUU_PMC_WUPMC30_SHIFT                    (30U)
+/*! WUPMC30 - Reserved
+ *  0b0..Not supported
+ *  0b1..Not supported
+ */
+#define WUU_PMC_WUPMC30(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC30_SHIFT)) & WUU_PMC_WUPMC30_MASK)
+
+#define WUU_PMC_WUPMC31_MASK                     (0x80000000U)
+#define WUU_PMC_WUPMC31_SHIFT                    (31U)
+/*! WUPMC31 - Reserved
+ *  0b0..Not supported
+ *  0b1..Not supported
+ */
+#define WUU_PMC_WUPMC31(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC31_SHIFT)) & WUU_PMC_WUPMC31_MASK)
+/*! @} */
+
+/*! @name FMC - Pin Filter Mode Configuration */
+/*! @{ */
+
+#define WUU_FMC_FILTM1_MASK                      (0x1U)
+#define WUU_FMC_FILTM1_SHIFT                     (0U)
+/*! FILTM1 - Filter Mode for FILTn
+ *  0b0..Active only during Deep Sleep 1/Deep Power Down mode
+ *  0b1..Active during all power modes
+ */
+#define WUU_FMC_FILTM1(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM1_SHIFT)) & WUU_FMC_FILTM1_MASK)
+
+#define WUU_FMC_FILTM2_MASK                      (0x2U)
+#define WUU_FMC_FILTM2_SHIFT                     (1U)
+/*! FILTM2 - Filter Mode for FILTn
+ *  0b0..Active only during Deep Sleep 1/Deep Power Down mode
+ *  0b1..Active during all power modes
+ */
+#define WUU_FMC_FILTM2(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM2_SHIFT)) & WUU_FMC_FILTM2_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group WUU_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group WUU_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_WUU_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WWDT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WWDT.h
new file mode 100644
index 0000000000..211644874e
--- /dev/null
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WWDT.h
@@ -0,0 +1,245 @@
+/*
+** ###################################################################
+**     Processors:          MCXA343VFM
+**                          MCXA343VLF
+**                          MCXA343VLH
+**                          MCXA343VLL
+**                          MCXA344VFM
+**                          MCXA344VLF
+**                          MCXA344VLH
+**                          MCXA344VLL
+**
+**     Version:             rev. 2.0, 2024-10-29
+**     Build:               b250806
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for WWDT
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-26)
+**         Initial version based on Rev1 DraftC RM
+**     - rev. 2.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file PERI_WWDT.h
+ * @version 2.0
+ * @date 2024-10-29
+ * @brief CMSIS Peripheral Access Layer for WWDT
+ *
+ * CMSIS Peripheral Access Layer for WWDT
+ */
+
+#if !defined(PERI_WWDT_H_)
+#define PERI_WWDT_H_                             /**< Symbol preventing repeated inclusion */
+
+#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL))
+#include "MCXA343_COMMON.h"
+#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL))
+#include "MCXA344_COMMON.h"
+#else
+  #error "No valid CPU defined!"
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- WWDT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
+ * @{
+ */
+
+/** WWDT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MOD;                               /**< Mode, offset: 0x0 */
+  __IO uint32_t TC;                                /**< Timer Constant, offset: 0x4 */
+  __O  uint32_t FEED;                              /**< Feed Sequence, offset: 0x8 */
+  __I  uint32_t TV;                                /**< Timer Value, offset: 0xC */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t WARNINT;                           /**< Warning Interrupt Compare Value, offset: 0x14 */
+  __IO uint32_t WINDOW;                            /**< Window Compare Value, offset: 0x18 */
+} WWDT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- WWDT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Register_Masks WWDT Register Masks
+ * @{
+ */
+
+/*! @name MOD - Mode */
+/*! @{ */
+
+#define WWDT_MOD_WDEN_MASK                       (0x1U)
+#define WWDT_MOD_WDEN_SHIFT                      (0U)
+/*! WDEN - Watchdog Enable
+ *  0b0..Timer stopped
+ *  0b1..Timer running
+ */
+#define WWDT_MOD_WDEN(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
+
+#define WWDT_MOD_WDRESET_MASK                    (0x2U)
+#define WWDT_MOD_WDRESET_SHIFT                   (1U)
+/*! WDRESET - Watchdog Reset Enable
+ *  0b0..Interrupt
+ *  0b1..Reset
+ */
+#define WWDT_MOD_WDRESET(x)                      (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
+
+#define WWDT_MOD_WDTOF_MASK                      (0x4U)
+#define WWDT_MOD_WDTOF_SHIFT                     (2U)
+/*! WDTOF - Watchdog Timeout Flag
+ *  0b0..Watchdog event has not occurred.
+ *  0b1..Watchdog event has occurred (causes a chip reset if WDRESET = 1).
+ */
+#define WWDT_MOD_WDTOF(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
+
+#define WWDT_MOD_WDINT_MASK                      (0x8U)
+#define WWDT_MOD_WDINT_SHIFT                     (3U)
+/*! WDINT - Warning Interrupt Flag
+ *  0b0..No flag
+ *  0b1..Flag
+ */
+#define WWDT_MOD_WDINT(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
+
+#define WWDT_MOD_WDPROTECT_MASK                  (0x10U)
+#define WWDT_MOD_WDPROTECT_SHIFT                 (4U)
+/*! WDPROTECT - Watchdog Update Mode
+ *  0b0..Flexible
+ *  0b1..Threshold
+ */
+#define WWDT_MOD_WDPROTECT(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
+
+#define WWDT_MOD_LOCK_MASK                       (0x20U)
+#define WWDT_MOD_LOCK_SHIFT                      (5U)
+/*! LOCK - Lock
+ *  0b0..No Lock
+ *  0b1..Lock
+ */
+#define WWDT_MOD_LOCK(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
+/*! @} */
+
+/*! @name TC - Timer Constant */
+/*! @{ */
+
+#define WWDT_TC_COUNT_MASK                       (0xFFFFFFU)
+#define WWDT_TC_COUNT_SHIFT                      (0U)
+/*! COUNT - Watchdog Timeout Value */
+#define WWDT_TC_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
+/*! @} */
+
+/*! @name FEED - Feed Sequence */
+/*! @{ */
+
+#define WWDT_FEED_FEED_MASK                      (0xFFU)
+#define WWDT_FEED_FEED_SHIFT                     (0U)
+/*! FEED - Feed Value */
+#define WWDT_FEED_FEED(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
+/*! @} */
+
+/*! @name TV - Timer Value */
+/*! @{ */
+
+#define WWDT_TV_COUNT_MASK                       (0xFFFFFFU)
+#define WWDT_TV_COUNT_SHIFT                      (0U)
+/*! COUNT - Counter Timer Value */
+#define WWDT_TV_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
+/*! @} */
+
+/*! @name WARNINT - Warning Interrupt Compare Value */
+/*! @{ */
+
+#define WWDT_WARNINT_WARNINT_MASK                (0x3FFU)
+#define WWDT_WARNINT_WARNINT_SHIFT               (0U)
+/*! WARNINT - Watchdog Warning Interrupt Compare Value */
+#define WWDT_WARNINT_WARNINT(x)                  (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
+/*! @} */
+
+/*! @name WINDOW - Window Compare Value */
+/*! @{ */
+
+#define WWDT_WINDOW_WINDOW_MASK                  (0xFFFFFFU)
+#define WWDT_WINDOW_WINDOW_SHIFT                 (0U)
+/*! WINDOW - Watchdog Window Value */
+#define WWDT_WINDOW_WINDOW(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group WWDT_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group WWDT_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* PERI_WWDT_H_ */
+
diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph_mapping.md b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph_mapping.md
index cd3e33a688..076cac3ddd 100644
--- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph_mapping.md
+++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph_mapping.md
@@ -2,3 +2,4 @@
 * periph:MCXA132,MCXA133,MCXA142,MCXA143,MCXA152,MCXA153
 * periph1:MCXA144,MCXA145,MCXA146,MCXA154,MCXA155,MCXA156
 * periph2:MCXA266,MCXA345,MCXA346,MCXA366
+* periph3:MCXA343,MCXA344