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nhutnguyenkcKhiemNguyenT
nhutnguyenkc
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KhiemNguyenT
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hal: renesas: rzt: Add clock control support for RZ/T2M
Add clock control support for RZ/T2M. Clock frequency and clock settings are taken from dts. Signed-off-by: Nhut Nguyen <[email protected]> Signed-off-by: Quang Le <[email protected]>
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‎zephyr/rz/rz_cfg/fsp_cfg/bsp/rzt2m/bsp_clock_cfg.h‎

Lines changed: 85 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -4,45 +4,93 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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7+
#include <zephyr/drivers/clock_control/renesas_rz_cgc.h>
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#ifndef BSP_CLOCK_CFG_H_
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#define BSP_CLOCK_CFG_H_
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#define BSP_CFG_CLOCKS_SECURE (0)
1012
#define BSP_CFG_CLOCKS_OVERRIDE (0)
11-
#define BSP_CFG_MAIN_CLOCK_HZ (25000000) /* Main Clock: 25MHz */
12-
#define BSP_CFG_LOCO_ENABLE (BSP_CLOCKS_LOCO_ENABLE) /* LOCO Enabled */
13-
#define BSP_CFG_PLL1 (BSP_CLOCKS_PLL1_INITIAL) /* PLL1 is initial state */
14-
#define BSP_CFG_PHYSEL (BSP_CLOCKS_PHYSEL_PLL1_DIV) /* Ethernet Clock src: PLL1 divider clock */
15-
#define BSP_CFG_CLMA0_ENABLE (BSP_CLOCKS_CLMA0_ENABLE) /* CLMA0 Enabled */
16-
#define BSP_CFG_CLMA0MASK (BSP_CLOCKS_CLMA0_ERROR_NOT_MASK) /* CLMA0 error not mask */
17-
#define BSP_CFG_CLMA3MASK (BSP_CLOCKS_CLMA3_ERROR_NOT_MASK) /* CLMA3 error not mask */
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#define BSP_CFG_CLMA1MASK (BSP_CLOCKS_CLMA1_ERROR_MASK) /* CLMA1 error mask */
19-
#define BSP_CFG_CLMA3_ENABLE (BSP_CLOCKS_CLMA3_ENABLE) /* CLMA3 Enabled */
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#define BSP_CFG_CLMA1_ENABLE (BSP_CLOCKS_CLMA1_ENABLE) /* CLMA1 Enabled */
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#define BSP_CFG_CLMA2_ENABLE (BSP_CLOCKS_CLMA2_ENABLE) /* CLMA2 Enabled */
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#define BSP_CFG_CLMA0_CMPL (1) /* CLMA0 CMPL 1 */
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#define BSP_CFG_CLMA1_CMPL (1) /* CLMA1 CMPL 1 */
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#define BSP_CFG_CLMA2_CMPL (1) /* CLMA2 CMPL 1 */
25-
#define BSP_CFG_CLMA3_CMPL (1) /* CLMA3 CMPL 1 */
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#define BSP_CFG_CLMASEL (BSP_CLOCKS_CLMASEL_LOCO) /* Alternative clock: LOCO */
27-
#define BSP_CFG_CLMA0_CMPH (1023) /* CLMA0 CMPH 1023 */
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#define BSP_CFG_CLMA1_CMPH (1023) /* CLMA1 CMPH 1023 */
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#define BSP_CFG_CLMA2_CMPH (1023) /* CLMA2 CMPH 1023 */
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#define BSP_CFG_CLMA3_CMPH (1023) /* CLMA3 CMPH 1023 */
31-
#define BSP_CFG_DIVSELSUB (BSP_CLOCKS_DIVSELSUB_0) /* ICLK 200MHz */
32-
#define BSP_CFG_SCI0ASYNCCLK (BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI0ASYNCCLK: 96MHz */
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#define BSP_CFG_SCI1ASYNCCLK (BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI1ASYNCCLK: 96MHz */
34-
#define BSP_CFG_SCI2ASYNCCLK (BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI2ASYNCCLK: 96MHz */
35-
#define BSP_CFG_SCI3ASYNCCLK (BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI3ASYNCCLK: 96MHz */
36-
#define BSP_CFG_SCI4ASYNCCLK (BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI4ASYNCCLK: 96MHz */
37-
#define BSP_CFG_SCI5ASYNCCLK (BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI5ASYNCCLK: 96MHz */
38-
#define BSP_CFG_SPI0ASYNCCLK (BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI0ASYNCCLK: 96MHz */
39-
#define BSP_CFG_SPI1ASYNCCLK (BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI1ASYNCCLK: 96MHz */
40-
#define BSP_CFG_SPI2ASYNCCLK (BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI2ASYNCCLK: 96MHz */
41-
#define BSP_CFG_SPI3ASYNCCLK (BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI3ASYNCCLK: 96MHz */
42-
#define BSP_CFG_FSELCPU0 (BSP_CLOCKS_FSELCPU0_ICLK_MUL1) /* CPU0CLK Mul x1 */
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#define BSP_CFG_FSELCPU1 (BSP_CLOCKS_FSELCPU1_ICLK_MUL1) /* CPU1CLK Mul x1 */
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#define BSP_CFG_CKIO (BSP_CLOCKS_CKIO_ICLK_DIV4) /* CKIO Div /4 */
45-
#define BSP_CFG_FSELCANFD (BSP_CLOCKS_CANFD_CLOCK_40_MHZ) /* CANFDCLK Src: PCLKCAN 40MHz */
46-
#define BSP_CFG_FSELXSPI0_DIVSELXSPI0 (BSP_CLOCKS_XSPI0_CLOCK_DIV0_12_5_MHZ) /* XSPI_CLK0 12.5MHz */
47-
#define BSP_CFG_FSELXSPI1_DIVSELXSPI1 (BSP_CLOCKS_XSPI1_CLOCK_DIV0_12_5_MHZ) /* XSPI_CLK1 12.5MHz */
13+
#define BSP_CFG_MAIN_CLOCK_HZ (DT_PROP(DT_NODELABEL(osc), clock_frequency)) /* Main Clock: 25MHz */
14+
BUILD_ASSERT(BSP_CFG_MAIN_CLOCK_HZ == 25000000, "The main clock must be 25MHz!");
15+
16+
/* LOCO Enable/Disable */
17+
#define BSP_CFG_LOCO_ENABLE \
18+
((DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(loco)) == 1) ? BSP_CLOCKS_LOCO_ENABLE \
19+
: BSP_CLOCKS_LOCO_DISABLE)
20+
21+
/* PLL1 initial state */
22+
#define BSP_CFG_PLL1 \
23+
((DT_ENUM_IDX(DT_NODELABEL(pll1), state) == 0) ? BSP_CLOCKS_PLL1_INITIAL \
24+
: (DT_ENUM_IDX(DT_NODELABEL(pll1), state) == 1) ? BSP_CLOCKS_PLL1_STANDBY \
25+
: BSP_CLOCKS_PLL1_NORMAL)
26+
27+
/* Ethernet Clock src */
28+
#define BSP_CFG_PHYSEL DT_ENUM_IDX(DT_NODELABEL(eth_refclk), eth_phy_source)
29+
30+
#define BSP_CFG_CLMA0_ENABLE (BSP_CLOCKS_CLMA0_ENABLE) /* CLMA0 Enabled */
31+
#define BSP_CFG_CLMA0MASK (BSP_CLOCKS_CLMA0_ERROR_NOT_MASK) /* CLMA0 error not mask */
32+
#define BSP_CFG_CLMA3MASK (BSP_CLOCKS_CLMA3_ERROR_NOT_MASK) /* CLMA3 error not mask */
33+
#define BSP_CFG_CLMA1MASK (BSP_CLOCKS_CLMA1_ERROR_MASK) /* CLMA1 error mask */
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#define BSP_CFG_CLMA3_ENABLE (BSP_CLOCKS_CLMA3_ENABLE) /* CLMA3 Enabled */
35+
#define BSP_CFG_CLMA1_ENABLE (BSP_CLOCKS_CLMA1_ENABLE) /* CLMA1 Enabled */
36+
#define BSP_CFG_CLMA2_ENABLE (BSP_CLOCKS_CLMA2_ENABLE) /* CLMA2 Enabled */
37+
#define BSP_CFG_CLMA0_CMPL (1) /* CLMA0 CMPL 1 */
38+
#define BSP_CFG_CLMA1_CMPL (1) /* CLMA1 CMPL 1 */
39+
#define BSP_CFG_CLMA2_CMPL (1) /* CLMA2 CMPL 1 */
40+
#define BSP_CFG_CLMA3_CMPL (1) /* CLMA3 CMPL 1 */
41+
#define BSP_CFG_CLMASEL (BSP_CLOCKS_CLMASEL_LOCO) /* Alternative clock: LOCO */
42+
#define BSP_CFG_CLMA0_CMPH (1023) /* CLMA0 CMPH 1023 */
43+
#define BSP_CFG_CLMA1_CMPH (1023) /* CLMA1 CMPH 1023 */
44+
#define BSP_CFG_CLMA2_CMPH (1023) /* CLMA2 CMPH 1023 */
45+
#define BSP_CFG_CLMA3_CMPH (1023) /* CLMA3 CMPH 1023 */
46+
47+
#define BSP_CFG_DIVSELSUB DT_ENUM_IDX(DT_NODELABEL(iclk), clock_frequency) /* ICLK */
48+
#define BSP_CFG_SCI0ASYNCCLK DT_ENUM_IDX(DT_NODELABEL(sci0asyncclk), clock_frequency) /* SCI0ASYNCCLK */
49+
#define BSP_CFG_SCI1ASYNCCLK DT_ENUM_IDX(DT_NODELABEL(sci1asyncclk), clock_frequency) /* SCI1ASYNCCLK */
50+
#define BSP_CFG_SCI2ASYNCCLK DT_ENUM_IDX(DT_NODELABEL(sci2asyncclk), clock_frequency) /* SCI2ASYNCCLK */
51+
#define BSP_CFG_SCI3ASYNCCLK DT_ENUM_IDX(DT_NODELABEL(sci3asyncclk), clock_frequency) /* SCI3ASYNCCLK */
52+
#define BSP_CFG_SCI4ASYNCCLK DT_ENUM_IDX(DT_NODELABEL(sci4asyncclk), clock_frequency) /* SCI4ASYNCCLK */
53+
#define BSP_CFG_SCI5ASYNCCLK DT_ENUM_IDX(DT_NODELABEL(sci5asyncclk), clock_frequency) /* SCI5ASYNCCLK */
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#define BSP_CFG_SPI0ASYNCCLK DT_ENUM_IDX(DT_NODELABEL(spi0asyncclk), clock_frequency) /* SPI0ASYNCCLK */
55+
#define BSP_CFG_SPI1ASYNCCLK DT_ENUM_IDX(DT_NODELABEL(spi1asyncclk), clock_frequency) /* SPI1ASYNCCLK */
56+
#define BSP_CFG_SPI2ASYNCCLK DT_ENUM_IDX(DT_NODELABEL(spi2asyncclk), clock_frequency) /* SPI2ASYNCCLK */
57+
#define BSP_CFG_SPI3ASYNCCLK DT_ENUM_IDX(DT_NODELABEL(spi3asyncclk), clock_frequency) /* SPI3ASYNCCLK */
58+
#define BSP_CFG_FSELCPU0 RZ_CGC_SUBCLK_MUL(DT_NODELABEL(cpu0clk)) /* CPU0CLK Mul */
59+
#define BSP_CFG_FSELCPU1 RZ_CGC_SUBCLK_MUL(DT_NODELABEL(cpu1clk)) /* CPU1CLK Mul */
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#define BSP_CFG_CKIO RZ_CGC_SUBCLK_DIV(DT_NODELABEL(ckio)) /* CKIO Div */
61+
62+
/* Validate the CPU0 multiplier */
63+
BUILD_ASSERT(IN_RANGE(LOG2(DT_PROP(DT_NODELABEL(cpu0clk), mul)), 0, 2) == 1,
64+
"The CPU0 multiplier must be 1, 2, or 4!");
65+
66+
/* Validate the CPU1 multiplier */
67+
BUILD_ASSERT(IN_RANGE(LOG2(DT_PROP(DT_NODELABEL(cpu1clk), mul)), 0, 2) == 1,
68+
"The CPU1 multiplier must be 1, 2, or 4!");
69+
70+
/* CANFDCLK Src */
71+
#define BSP_CFG_FSELCANFD \
72+
((DT_ENUM_IDX(DT_NODELABEL(canfdclk), canfd_source) == 0) ? BSP_CLOCKS_CANFD_CLOCK_80_MHZ \
73+
: (DT_ENUM_IDX(DT_NODELABEL(canfdclk), canfd_source) == 1) ? BSP_CLOCKS_CANFD_CLOCK_40_MHZ \
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: BSP_CLOCKS_CANFD_CLOCK_PCLKM)
75+
76+
/* XSPI_CLK0 */
77+
#define BSP_CFG_FSELXSPI0_DIVSELXSPI0 \
78+
((DT_PROP(DT_NODELABEL(xspi_clk0), xspi_clk_frequency) == 133333333) ? BSP_CLOCKS_XSPI0_CLOCK_DIV0_133_3_MHZ \
79+
: (DT_PROP(DT_NODELABEL(xspi_clk0), xspi_clk_frequency) == 100000000) ? BSP_CLOCKS_XSPI0_CLOCK_DIV0_100_0_MHZ \
80+
: (DT_PROP(DT_NODELABEL(xspi_clk0), xspi_clk_frequency) == 50000000) ? BSP_CLOCKS_XSPI0_CLOCK_DIV0_50_0_MHZ \
81+
: (DT_PROP(DT_NODELABEL(xspi_clk0), xspi_clk_frequency) == 25000000) ? BSP_CLOCKS_XSPI0_CLOCK_DIV0_25_0_MHZ \
82+
: (DT_PROP(DT_NODELABEL(xspi_clk0), xspi_clk_frequency) == 12500000) ? BSP_CLOCKS_XSPI0_CLOCK_DIV0_12_5_MHZ \
83+
: (DT_PROP(DT_NODELABEL(xspi_clk0), xspi_clk_frequency) == 75000000) ? BSP_CLOCKS_XSPI0_CLOCK_DIV1_75_0_MHZ \
84+
: BSP_CLOCKS_XSPI0_CLOCK_DIV1_37_5_MHZ)
85+
86+
/* XSPI_CLK1 */
87+
#define BSP_CFG_FSELXSPI1_DIVSELXSPI1 \
88+
((DT_PROP(DT_NODELABEL(xspi_clk1), xspi_clk_frequency) == 133333333) ? BSP_CLOCKS_XSPI1_CLOCK_DIV0_133_3_MHZ \
89+
: (DT_PROP(DT_NODELABEL(xspi_clk1), xspi_clk_frequency) == 100000000) ? BSP_CLOCKS_XSPI1_CLOCK_DIV0_100_0_MHZ \
90+
: (DT_PROP(DT_NODELABEL(xspi_clk1), xspi_clk_frequency) == 50000000) ? BSP_CLOCKS_XSPI1_CLOCK_DIV0_50_0_MHZ \
91+
: (DT_PROP(DT_NODELABEL(xspi_clk1), xspi_clk_frequency) == 25000000) ? BSP_CLOCKS_XSPI1_CLOCK_DIV0_25_0_MHZ \
92+
: (DT_PROP(DT_NODELABEL(xspi_clk1), xspi_clk_frequency) == 12500000) ? BSP_CLOCKS_XSPI1_CLOCK_DIV0_12_5_MHZ \
93+
: (DT_PROP(DT_NODELABEL(xspi_clk1), xspi_clk_frequency) == 75000000) ? BSP_CLOCKS_XSPI1_CLOCK_DIV1_75_0_MHZ \
94+
: BSP_CLOCKS_XSPI1_CLOCK_DIV1_37_5_MHZ)
95+
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#endif /* BSP_CLOCK_CFG_H_ */

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