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Danh DoanKhiemNguyenT
Danh Doan
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KhiemNguyenT
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hal: renesas: ra: initial support for sdram controller
Initial support SDRAM on Renesas RA SoC Signed-off-by: Danh Doan <[email protected]>
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‎drivers/ra/CMakeLists.txt

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@@ -57,6 +57,8 @@ zephyr_library_sources_ifdef(CONFIG_USE_RA_FSP_SDHI
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fsp/src/r_sdhi/r_sdhi.c)
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zephyr_library_sources_ifdef(CONFIG_USE_RA_FSP_OSPI_B_NOR_FLASH
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fsp/src/r_ospi_b/r_ospi_b.c)
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zephyr_library_sources_ifdef(CONFIG_USE_RA_FSP_SDRAM
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fsp/src/bsp/mcu/all/bsp_sdram.c)
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if(CONFIG_USE_RA_FSP_SCE)
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zephyr_include_directories(

‎drivers/ra/README

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@@ -77,3 +77,8 @@ Patch List:
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drivers/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c
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drivers/ra/fsp/inc/instances/r_ether_phy.h
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drivers/ra/fsp/inc/instances/r_ether.h
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* Add support for SDRAM controllers taken from FSP v5.6.0
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Impacted files:
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drivers/ra/fsp/src/bsp/mcu/all/bsp_sdram.h
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drivers/ra/fsp/src/bsp/mcu/all/bsp_sdram.c

‎drivers/ra/fsp/src/bsp/mcu/all/bsp_sdram.c

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*******************************************************************************************************************//**
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* @defgroup BSP_SDRAM BSP SDRAM support
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* @ingroup RENESAS_COMMON
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* @brief Code that initializes the SDRAMC and SDR SDRAM device memory.
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*
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* @{
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Includes
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**********************************************************************************************************************/
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#include "bsp_api.h"
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/* Due to hardware limitations of the SDRAM peripheral,
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* it is not expected any of these need to be changable by end user.
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* Only sequential, single access at a time is supported. */
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#define BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC (1U) /* MR.M9 : Single Location Access */
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#define BSP_PRV_SDRAM_MR_OP_MODE (0U) /* MR.M8:M7 : Standard Operation */
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#define BSP_PRV_SDRAM_MR_BT_SEQUENTIAL (0U) /* MR.M3 Burst Type : Sequential */
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#define BSP_PRV_SDRAM_MR_BURST_LENGTH (0U) /* MR.M2:M0 Burst Length: 0(1 burst) */
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/***********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Private function prototypes
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Private global variables
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Functions
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**********************************************************************************************************************/
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#if 0 != BSP_FEATURE_SDRAM_START_ADDRESS
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/*******************************************************************************************************************//**
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* @brief Initializes SDRAM.
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* @param init_memory If true, this function will execute the initialization of the external modules.
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* Otherwise, it will only initialize the SDRAMC and leave the memory in self-refresh mode.
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*
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* This function initializes SDRAMC and SDR SDRAM device.
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*
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* @note This function must only be called once after reset.
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**********************************************************************************************************************/
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void R_BSP_SdramInit (bool init_memory)
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{
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/** Setting for SDRAM initialization sequence */
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while (R_BUS->SDRAM.SDSR)
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{
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/* According to h/w manual, need to confirm that all the status bits in SDSR are 0 before SDICR modification. */
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}
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/* Must only write to SDIR once after reset. */
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R_BUS->SDRAM.SDIR = ((BSP_CFG_SDRAM_INIT_ARFI - 3U) << R_BUS_SDRAM_SDIR_ARFI_Pos) |
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(BSP_CFG_SDRAM_INIT_ARFC << R_BUS_SDRAM_SDIR_ARFC_Pos) |
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((BSP_CFG_SDRAM_INIT_PRC - 3U) << R_BUS_SDRAM_SDIR_PRC_Pos);
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R_BUS->SDRAM.SDCCR = (BSP_CFG_SDRAM_BUS_WIDTH << R_BUS_SDRAM_SDCCR_BSIZE_Pos); /* set SDRAM bus width */
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if (init_memory)
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{
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/* Enable the SDCLK output. */
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R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC);
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R_SYSTEM->SDCKOCR = 1;
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R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC);
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/** If requested, start SDRAM initialization sequence. */
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R_BUS->SDRAM.SDICR = 1U;
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while (R_BUS->SDRAM.SDSR_b.INIST)
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{
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/* Wait the end of initialization sequence. */
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}
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}
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/** Setting for SDRAM controller */
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R_BUS->SDRAM.SDAMOD = BSP_CFG_SDRAM_ACCESS_MODE; /* enable continuous access */
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R_BUS->SDRAM.SDCMOD = BSP_CFG_SDRAM_ENDIAN_MODE; /* set endian mode for SDRAM address space */
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while (R_BUS->SDRAM.SDSR)
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{
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/* According to h/w manual, need to confirm that all the status bits in SDSR are 0 before SDMOD modification. */
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}
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if (init_memory)
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{
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/** Using LMR command, program the mode register */
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R_BUS->SDRAM.SDMOD = (BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC << 9) |
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(BSP_PRV_SDRAM_MR_OP_MODE << 7) |
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(BSP_CFG_SDRAM_TCL << 4) |
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(BSP_PRV_SDRAM_MR_BT_SEQUENTIAL << 3) |
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(BSP_PRV_SDRAM_MR_BURST_LENGTH << 0);
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/** wait at least tMRD time */
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while (R_BUS->SDRAM.SDSR_b.MRSST)
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{
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/* Wait until Mode Register setting done. */
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}
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}
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/** Set timing parameters for SDRAM. Must do in single write. */
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R_BUS->SDRAM.SDTR = ((BSP_CFG_SDRAM_TRAS - 1U) << R_BUS_SDRAM_SDTR_RAS_Pos) |
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((BSP_CFG_SDRAM_TRCD - 1U) << R_BUS_SDRAM_SDTR_RCD_Pos) |
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((BSP_CFG_SDRAM_TRP - 1U) << R_BUS_SDRAM_SDTR_RP_Pos) |
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((BSP_CFG_SDRAM_TWR - 1U) << R_BUS_SDRAM_SDTR_WR_Pos) |
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(BSP_CFG_SDRAM_TCL << R_BUS_SDRAM_SDTR_CL_Pos);
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/** Set row address offset for target SDRAM */
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R_BUS->SDRAM.SDADR = BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT;
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/* Set Auto-Refresh timings. */
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R_BUS->SDRAM.SDRFCR = ((BSP_CFG_SDRAM_TREFW - 1U) << R_BUS_SDRAM_SDRFCR_REFW_Pos) |
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((BSP_CFG_SDRAM_TRFC - 1U) << R_BUS_SDRAM_SDRFCR_RFC_Pos);
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/** Start Auto-refresh */
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R_BUS->SDRAM.SDRFEN = 1U;
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if (init_memory)
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{
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/** Enable SDRAM access */
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R_BUS->SDRAM.SDCCR = R_BUS_SDRAM_SDCCR_EXENB_Msk | (BSP_CFG_SDRAM_BUS_WIDTH << R_BUS_SDRAM_SDCCR_BSIZE_Pos);
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}
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else
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{
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/* If not initializing memory modules, start in self-refresh mode. */
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while (R_BUS->SDRAM.SDCCR_b.EXENB || (0U != R_BUS->SDRAM.SDSR))
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{
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/* Wait for access to be disabled and no status bits set. */
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}
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/* Enable the self-refresh mode. */
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R_BUS->SDRAM.SDSELF = 1U;
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}
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}
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/*******************************************************************************************************************//**
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* @brief Changes SDRAM from Auto-refresh to Self-refresh
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*
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* This function allows Software Standby and Deep Software Standby modes to be entered without data loss.
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*
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* @note SDRAM cannot be accessed after calling this function. Use @ref R_BSP_SdramSelfRefreshDisable to resume normal
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* SDRAM operation.
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**********************************************************************************************************************/
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void R_BSP_SdramSelfRefreshEnable (void)
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{
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R_BUS->SDRAM.SDCCR = (BSP_CFG_SDRAM_BUS_WIDTH << R_BUS_SDRAM_SDCCR_BSIZE_Pos);
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while (R_BUS->SDRAM.SDCCR_b.EXENB || (0U != R_BUS->SDRAM.SDSR))
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{
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/* Wait for access to be disabled and no status bits set. */
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}
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/* Enable the self-refresh mode. */
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R_BUS->SDRAM.SDSELF = 1U;
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}
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/*******************************************************************************************************************//**
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* @brief Changes SDRAM from Self-refresh to Auto-refresh
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*
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* This function changes back to Auto-refresh and allows normal SDRAM operation to resume.
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*
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**********************************************************************************************************************/
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void R_BSP_SdramSelfRefreshDisable (void)
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{
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if (0 == R_SYSTEM->SDCKOCR)
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{
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/* Enable the SDCLK output. It may not already be enabled here if recovering from Deep Software Standby. */
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R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC);
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R_SYSTEM->SDCKOCR = 1;
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R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC);
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}
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while (0U != R_BUS->SDRAM.SDSR)
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{
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/* Wait for all status bits to be cleared. */
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}
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/* Disable the self-refresh mode. */
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R_BUS->SDRAM.SDSELF = 0U;
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/* Reenable SDRAM bus access. */
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R_BUS->SDRAM.SDCCR = R_BUS_SDRAM_SDCCR_EXENB_Msk | (BSP_CFG_SDRAM_BUS_WIDTH << R_BUS_SDRAM_SDCCR_BSIZE_Pos);
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}
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#endif
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/** @} (end addtogroup BSP_SDRAM) */

‎drivers/ra/fsp/src/bsp/mcu/all/bsp_sdram.h

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BSP_SDRAM_H
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#define BSP_SDRAM_H
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#if 0 != BSP_FEATURE_SDRAM_START_ADDRESS
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/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
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FSP_HEADER
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Exported global variables
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Exported global functions (to be accessed by other files)
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**********************************************************************************************************************/
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void R_BSP_SdramInit(bool init_memory);
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void R_BSP_SdramSelfRefreshEnable(void);
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void R_BSP_SdramSelfRefreshDisable(void);
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/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
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FSP_FOOTER
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#endif
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#endif

‎zephyr/ra/portable/bsp_common.h

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/* BSP TFU Includes. */
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#include "bsp_tfu.h"
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#include "bsp_sdram.h"
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2830
#include "bsp_cfg.h"
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3032
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m2/bsp_mcu_family_cfg.h

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#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
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#endif
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/* SDRAM controller configuration */
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#if DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram))
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#define BSP_CFG_SDRAM_TRAS \
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DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 0)
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#define BSP_CFG_SDRAM_TRCD \
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DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 1)
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#define BSP_CFG_SDRAM_TRP \
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DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 2)
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#define BSP_CFG_SDRAM_TWR \
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DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 3)
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#define BSP_CFG_SDRAM_TCL \
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DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 4)
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#define BSP_CFG_SDRAM_TRFC \
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DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 5)
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#define BSP_CFG_SDRAM_TREFW \
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DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 6)
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#define BSP_CFG_SDRAM_INIT_ARFI DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_interval)
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#define BSP_CFG_SDRAM_INIT_ARFC DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_count)
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#define BSP_CFG_SDRAM_INIT_PRC DT_PROP(DT_INST(0, renesas_ra_sdram), precharge_cycle_count)
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#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), multiplex_addr_shift)
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#define BSP_CFG_SDRAM_ENDIAN_MODE DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), edian_mode)
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#define BSP_CFG_SDRAM_ACCESS_MODE DT_PROP(DT_INST(0, renesas_ra_sdram), continuous_access)
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#define BSP_CFG_SDRAM_BUS_WIDTH DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), bus_width)
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#else
108+
#define BSP_CFG_SDRAM_TRAS (0)
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#define BSP_CFG_SDRAM_TRCD (0)
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#define BSP_CFG_SDRAM_TRP (0)
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#define BSP_CFG_SDRAM_TWR (0)
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#define BSP_CFG_SDRAM_TCL (0)
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#define BSP_CFG_SDRAM_TRFC (0)
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#define BSP_CFG_SDRAM_TREFW (0)
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#define BSP_CFG_SDRAM_INIT_ARFI (0)
116+
#define BSP_CFG_SDRAM_INIT_ARFC (0)
117+
#define BSP_CFG_SDRAM_INIT_PRC (0)
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#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (0)
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#define BSP_CFG_SDRAM_ENDIAN_MODE (0)
120+
#define BSP_CFG_SDRAM_ACCESS_MODE (0)
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#define BSP_CFG_SDRAM_BUS_WIDTH (0)
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#endif /* DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram)) */
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#endif /* BSP_MCU_FAMILY_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m3/bsp_mcu_family_cfg.h

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#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
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#endif
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/* SDRAM controller configuration */
86+
#if DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram))
87+
#define BSP_CFG_SDRAM_TRAS \
88+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 0)
89+
#define BSP_CFG_SDRAM_TRCD \
90+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 1)
91+
#define BSP_CFG_SDRAM_TRP \
92+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 2)
93+
#define BSP_CFG_SDRAM_TWR \
94+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 3)
95+
#define BSP_CFG_SDRAM_TCL \
96+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 4)
97+
#define BSP_CFG_SDRAM_TRFC \
98+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 5)
99+
#define BSP_CFG_SDRAM_TREFW \
100+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 6)
101+
#define BSP_CFG_SDRAM_INIT_ARFI DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_interval)
102+
#define BSP_CFG_SDRAM_INIT_ARFC DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_count)
103+
#define BSP_CFG_SDRAM_INIT_PRC DT_PROP(DT_INST(0, renesas_ra_sdram), precharge_cycle_count)
104+
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), multiplex_addr_shift)
105+
#define BSP_CFG_SDRAM_ENDIAN_MODE DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), edian_mode)
106+
#define BSP_CFG_SDRAM_ACCESS_MODE DT_PROP(DT_INST(0, renesas_ra_sdram), continuous_access)
107+
#define BSP_CFG_SDRAM_BUS_WIDTH DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), bus_width)
108+
#else
109+
#define BSP_CFG_SDRAM_TRAS (0)
110+
#define BSP_CFG_SDRAM_TRCD (0)
111+
#define BSP_CFG_SDRAM_TRP (0)
112+
#define BSP_CFG_SDRAM_TWR (0)
113+
#define BSP_CFG_SDRAM_TCL (0)
114+
#define BSP_CFG_SDRAM_TRFC (0)
115+
#define BSP_CFG_SDRAM_TREFW (0)
116+
#define BSP_CFG_SDRAM_INIT_ARFI (0)
117+
#define BSP_CFG_SDRAM_INIT_ARFC (0)
118+
#define BSP_CFG_SDRAM_INIT_PRC (0)
119+
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (0)
120+
#define BSP_CFG_SDRAM_ENDIAN_MODE (0)
121+
#define BSP_CFG_SDRAM_ACCESS_MODE (0)
122+
#define BSP_CFG_SDRAM_BUS_WIDTH (0)
123+
#endif /* DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram)) */
124+
85125
#endif /* BSP_MCU_FAMILY_CFG_H_ */

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