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Hieu Nguyennhutnguyenkc
Hieu Nguyen
authored and
nhutnguyenkc
committed
hal: renesas: rza: Add DMA support for RZ/A series
- Add HAL FSP DMAC files to support DMA for RZ/A series - Change the cast type from uint32_t to uintptr_t when assigning an address to a register in the DMAC FSP driver of the RZ/A3UL to avoid build warnings - Disable the BSP_FEATURE_BSP_HAS_MMU_SUPPORT configuration of the RZ/A3UL to avoid using FSP MMU functions Signed-off-by: Hieu Nguyen <[email protected]> Signed-off-by: Nhut Nguyen <[email protected]>
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‎drivers/rz/README‎

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@@ -92,3 +92,13 @@ Patch List:
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* Use r_transfer_api.h of rzv-fsp to support the callbackSet member of the transfer_api_t struct
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Impacted files:
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drivers/rz/fsp/inc/api/r_transfer_api.h
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* Change the cast type from uint32_t to uintptr_t when assigning an address to a register in the
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DMAC FSP driver of the RZ/A3UL to avoid build warnings
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Impacted files:
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drivers/rz/fsp/src/rza/r_dmac/r_dmac.c
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* Disable the BSP_FEATURE_BSP_HAS_MMU_SUPPORT configuration of the RZ/A3UL to avoid using
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FSP MMU functions
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Impacted files:
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drivers/rz/fsp/src/rza/bsp/mcu/rza3ul/bsp_feature.h

‎drivers/rz/fsp/inc/instances/rza/r_dmac.h‎

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*******************************************************************************************************************//**
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* @addtogroup DMAC
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* @{
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**********************************************************************************************************************/
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#ifndef R_DMAC_H
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#define R_DMAC_H
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/***********************************************************************************************************************
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* Includes
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**********************************************************************************************************************/
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#include "bsp_api.h"
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#include "r_transfer_api.h"
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#include "r_dmac_cfg.h"
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/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
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FSP_HEADER
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/** Max configurable number of transfers in TRANSFER_MODE_NORMAL. */
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#define DMAC_MAX_NORMAL_TRANSFER_LENGTH (0xFFFFFFFF)
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/** Max number of transfers per block in TRANSFER_MODE_BLOCK */
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#define DMAC_MAX_BLOCK_TRANSFER_LENGTH (0xFFFFFFFF)
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/***********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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typedef transfer_callback_args_t dmac_callback_args_t;
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/** Events that can trigger a callback function. */
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typedef enum e_dmac_event
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{
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DMAC_EVENT_TRANSFER_END = 0, ///< DMA transfer has completed.
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DMAC_EVENT_TRANSFER_ERROR = 1, ///< A bus error occurred during DMA transfer.
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} dmac_event_t;
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/** Transfer size specifies the size of each individual transfer. */
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typedef enum e_dmac_transfer_size
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{
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DMAC_TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value.
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DMAC_TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value.
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DMAC_TRANSFER_SIZE_4_BYTE = 2, ///< Each transfer transfers a 32-bit value.
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DMAC_TRANSFER_SIZE_8_BYTE = 3, ///< Each transfer transfers a 64-bit value.
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DMAC_TRANSFER_SIZE_16_BYTE = 4, ///< Each transfer transfers a 128-bit value.
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DMAC_TRANSFER_SIZE_32_BYTE = 5, ///< Each transfer transfers a 256-bit value.
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DMAC_TRANSFER_SIZE_64_BYTE = 6, ///< Each transfer transfers a 512-bit value.
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DMAC_TRANSFER_SIZE_128_BYTE = 7, ///< Each transfer transfers a 1024-bit value.
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} dmac_transfer_size_t;
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/** DACK output mode. See RZ/T2M hardware manual Table 14.19 DMA Transfer Request Detection Operation Setting Table. */
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typedef enum e_dmac_ack_mode
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{
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DMAC_ACK_MODE_LEVEL_MODE = 1, ///< Level mode.
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DMAC_ACK_MODE_BUS_CYCLE_MODE = 2, ///< Bus cycle mode.
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DMAC_ACK_MODE_MASK_DACK_OUTPUT = 4, ///< Output is masked.
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} dmac_ack_mode_t;
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/** Detection method of the DMA request signal. See RZ/T2M hardware manual Table 14.19 DMA Transfer Request Detection Operation Setting Table. */
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typedef enum e_dmac_detection
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{
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DMAC_DETECTION_FALLING_EDGE = 1, ///< Falling edge detection.
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DMAC_DETECTION_RISING_EDGE = 2, ///< Rising edge detection.
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DMAC_DETECTION_LOW_LEVEL = 5, ///< Low level detection.
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DMAC_DETECTION_HIGH_LEVEL = 6, ///< High level detection.
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} dmac_detection_t;
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/** DMA activation request source select. See RZ/T2M hardware manual Table 14.19 DMA Transfer Request Detection Operation Setting Table. */
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typedef enum e_dmac_request_direction
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{
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DMAC_REQUEST_DIRECTION_SOURCE_MODULE = 0, ///< Requested by a transfer source module.
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DMAC_REQUEST_DIRECTION_DESTINATION_MODULE = 1, ///< Requested by a transfer destination module.
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} dmac_request_direction_t;
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/** Select the Next register set to be executed next. */
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typedef enum e_dmac_continuous_setting
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{
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DMAC_CONTINUOUS_SETTING_TRANSFER_NEXT0_ONCE = 0x0, ///< Transfer only once using the Next0 register set.
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DMAC_CONTINUOUS_SETTING_TRANSFER_NEXT0_NEXT1_ALTERNATELY = 0x3, ///< Transfers are performed alternately with the Next0 register set and the Next1 register set.
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} dmac_continuous_setting_t;
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/** Register set settings. */
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typedef struct st_dmac_next1_register_setting
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{
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void const * p_src; ///< Source pointer.
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void * p_dest; ///< Destination pointer.
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uint32_t length; ///< Transfer Byte.
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} dmac_next1_register_setting_t;
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/** DMAC channel scheduling. */
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typedef enum e_dmac_channel_scheduling
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{
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DMAC_CHANNEL_SCHEDULING_FIXED = 0, ///< Fixed priority mode.
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DMAC_CHANNEL_SCHEDULING_ROUND_ROBIN = 1, ///< Round-robin mode.
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} dmac_channel_scheduling_t;
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/** DMAC mode setting. */
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typedef enum e_dmac_mode_select
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{
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DMAC_MODE_SELECT_REGISTER = 0, ///< Register mode.
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DMAC_MODE_SELECT_LINK = 1, ///< Link mode.
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} dmac_mode_select_t;
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/** Indicates the descriptor is enabled or disabled. */
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typedef enum e_dmac_link_valid
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{
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DMAC_LINK_VALID_DESCRIPTOR_DISABLE = 0, ///< The Descriptor is disabled.
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DMAC_LINK_VALID_DESCRIPTOR_ENABLE = 1, ///< The Descriptor is enabled.
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} dmac_link_valid_t;
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/** Indicates that the link ends during DMA transfer of this descriptor. */
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typedef enum e_dmac_link_end
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{
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DMAC_LINK_END_DISABLE = 0, ///< The link continues.
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DMAC_LINK_END_ENABLE = 1, ///< The link ends.
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} dmac_link_end_t;
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/** Masks write back execution of the dmac_link_cfg_t::link_valid. When disable, DMAC does not perform write-back operation. */
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typedef enum e_dmac_link_write_back
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{
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DMAC_LINK_WRITE_BACK_ENABLE = 0, ///< Set dmac_link_cfg_t::link_valid to disable after the DMA transfer ends.
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DMAC_LINK_WRITE_BACK_DISABLE = 1, ///< Remain dmac_link_cfg_t::link_valid after DMA transfer ends.
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} dmac_link_write_back_t;
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/** When dmac_link_cfg_t::link_valid is DMAC_LINK_VALID_DESCRIPTOR_DISABLE at loading of header, specifies whether DMA transfer completion interrupt mask or not. */
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typedef enum e_dmac_link_interrupt_mask
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{
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DMAC_LINK_INTERRUPT_MASK_DISABLE = 0, ///< DMA transfer completion interrupt is asserted.
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DMAC_LINK_INTERRUPT_MASK_ENABLE = 1, ///< DMA transfer completion interrupt is masked.
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} dmac_link_interrupt_mask_t;
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/** Descriptor structure used in DMAC link mode, and variables of dmac_link_cfg_t must be allocated in the memory area. */
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#if (BSP_FEATURE_DMAC_64BIT_SYSTEM == 1)
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typedef struct st_dmac_link_cfg
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{
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union
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{
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uint32_t header_u32; ///< Descriptor header
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struct
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{
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dmac_link_valid_t link_valid : 1; ///< The descriptor is valid or not.
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dmac_link_end_t link_end : 1; ///< The descriptor is end or not.
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dmac_link_write_back_t write_back_disable : 1; ///< Write back enable or not.
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dmac_link_interrupt_mask_t interrupt_mask : 1; ///< Interrupt mask is enable or not.
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uint32_t : 28;
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} header;
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};
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volatile uint32_t src_addr; ///< Source address.
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volatile uint32_t dest_addr; ///< Destination address.
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volatile uint32_t transaction_byte; ///< Transaction byte.
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volatile uint32_t channel_cfg; ///< Channel configuration (Set value for CHCFG_n register).
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volatile uint32_t channel_interval; ///< Channel interval (Set value for CHITVL register).
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volatile uint32_t channel_extension_cfg; ///< Channel extension configuration (Set value for CHEXT_n register).
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volatile uint32_t next_link_addr; ///< Next link address.
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} dmac_link_cfg_t;
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#else
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typedef struct st_dmac_link_cfg
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{
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union
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{
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uint32_t header_u32; ///< Descriptor header
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struct
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{
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dmac_link_valid_t link_valid : 1; ///< The descriptor is valid or not.
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dmac_link_end_t link_end : 1; ///< The descriptor is end or not.
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dmac_link_write_back_t write_back_disable : 1; ///< Write back enable or not.
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dmac_link_interrupt_mask_t interrupt_mask : 1; ///< Interrupt mask is enable or not.
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uint32_t : 28;
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} header;
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};
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void const * volatile p_src; ///< Source address.
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void * volatile p_dest; ///< Destination address.
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volatile uint32_t transaction_byte; ///< Transaction byte.
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volatile uint32_t channel_cfg; ///< Channel configuration (Set value for CHCFG_n register).
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volatile uint32_t channel_interval; ///< Channel interval (Set value for CHITVL register).
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volatile uint32_t channel_extension_cfg; ///< Channel extension configuration (Set value for CHEXT_n register).
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void * volatile p_next_link_addr; ///< Next link address.
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} dmac_link_cfg_t;
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#endif
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/** Control block used by driver. DO NOT INITIALIZE - this structure will be initialized in @ref transfer_api_t::open. */
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typedef struct st_dmac_instance_ctrl
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{
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uint32_t open; // Driver ID
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transfer_cfg_t const * p_cfg;
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dmac_link_cfg_t const * p_descriptor;
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/* Pointer to base register. */
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R_DMA0_Type * p_reg;
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void (* p_callback)(dmac_callback_args_t *); // Pointer to callback
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dmac_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory
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void const * p_context;
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} dmac_instance_ctrl_t;
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/** DMAC transfer configuration extension. This extension is required. */
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typedef struct st_dmac_extended_cfg
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{
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uint8_t channel; ///< Channel number
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IRQn_Type dmac_int_irq; ///< DMAC interrupt number
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uint8_t dmac_int_ipl; ///< DMAC interrupt priority
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uint32_t dmac_int_irq_detect_type; ///< DMAC interrupt detection type
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/** Select which event will trigger the transfer. */
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dmac_trigger_event_t activation_source;
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/** The interrupt ID number that corresponds to the Activation Source. */
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IRQn_Type activation_irq_number;
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dmac_ack_mode_t ack_mode; ///< DACK output mode
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dmac_detection_t detection_mode; ///< DMAC request detection method
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dmac_request_direction_t activation_request_source_select; ///< DMAC activation request source
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dmac_mode_select_t dmac_mode; ///< DMAC Mode
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dmac_link_cfg_t const * p_descriptor; ///< The address of the descriptor (DMA Link Mode only)
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dmac_continuous_setting_t continuous_setting; ///< Next register operation settings
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uint16_t transfer_interval; ///< DMA transfer interval
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dmac_channel_scheduling_t channel_scheduling; ///< DMA channel scheduling
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/** Callback for transfer end interrupt. */
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void (* p_callback)(dmac_callback_args_t * cb_data);
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dmac_callback_args_t * p_callback_memory;
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/** Placeholder for user data. Passed to the user p_callback in ::transfer_callback_args_t. */
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void const * p_context;
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} dmac_extended_cfg_t;
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/** DMAC transfer configuration extension. This extension is required. */
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typedef struct st_dmac_extended_info
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{
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/** Select number of source bytes to transfer at once. */
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dmac_transfer_size_t src_size;
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/** Select number of destnination bytes to transfer at once. */
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dmac_transfer_size_t dest_size;
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/** Next1 Register set settings */
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dmac_next1_register_setting_t * p_next1_register_setting;
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} dmac_extended_info_t;
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/**********************************************************************************************************************
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* Exported global variables
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**********************************************************************************************************************/
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/** @cond INC_HEADER_DEFS_SEC */
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/** Filled in Interface API structure for this Instance. */
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extern const transfer_api_t g_transfer_on_dmac;
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/** @endcond */
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/***********************************************************************************************************************
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* Public Function Prototypes
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**********************************************************************************************************************/
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fsp_err_t R_DMAC_Open(transfer_ctrl_t * const p_api_ctrl, transfer_cfg_t const * const p_cfg);
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fsp_err_t R_DMAC_Reconfigure(transfer_ctrl_t * const p_api_ctrl, transfer_info_t * p_info);
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fsp_err_t R_DMAC_Reset(transfer_ctrl_t * const p_api_ctrl,
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void const * volatile p_src,
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void * volatile p_dest,
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uint16_t const num_transfers);
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fsp_err_t R_DMAC_SoftwareStart(transfer_ctrl_t * const p_api_ctrl, transfer_start_mode_t mode);
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fsp_err_t R_DMAC_SoftwareStop(transfer_ctrl_t * const p_api_ctrl);
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fsp_err_t R_DMAC_Enable(transfer_ctrl_t * const p_api_ctrl);
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fsp_err_t R_DMAC_Disable(transfer_ctrl_t * const p_api_ctrl);
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fsp_err_t R_DMAC_InfoGet(transfer_ctrl_t * const p_api_ctrl, transfer_properties_t * const p_info);
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fsp_err_t R_DMAC_Close(transfer_ctrl_t * const p_api_ctrl);
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fsp_err_t R_DMAC_Reload(transfer_ctrl_t * const p_api_ctrl,
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void const * p_src,
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void * p_dest,
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uint32_t const num_transfers);
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fsp_err_t R_DMAC_CallbackSet(transfer_ctrl_t * const p_api_ctrl,
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void ( * p_callback)(dmac_callback_args_t *),
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void const * const p_context,
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dmac_callback_args_t * const p_callback_memory);
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fsp_err_t R_DMAC_LinkDescriptorSet(transfer_ctrl_t * const p_api_ctrl, dmac_link_cfg_t * p_descriptor);
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/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
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FSP_FOOTER
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#endif
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/*******************************************************************************************************************//**
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* @} (end defgroup DMAC)
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**********************************************************************************************************************/

‎drivers/rz/fsp/src/rza/bsp/mcu/rza3ul/bsp_feature.h‎

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@@ -35,7 +35,7 @@
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/* BSP Capabilities Definitions */
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#define BSP_FEATURE_BSP_SUPPORT_PLL5_CONFIG (0U)
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#define BSP_FEATURE_BSP_SUPPORT_OCTAL_MEMORY (1U)
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#define BSP_FEATURE_BSP_HAS_MMU_SUPPORT (1)
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#define BSP_FEATURE_BSP_HAS_MMU_SUPPORT (0U)
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#define BSP_FEATURE_BSP_HAS_ELC (0U)
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#define BSP_FEATURE_BSP_SUPPORT_SD_VOLT (1U)
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#define BSP_FEATURE_BSP_SUPPORT_ETHER_VOLT (1U)

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