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hal: renesas: Add support for Renesas RA8P1
Add support for Renesas RA8P1 Signed-off-by: Khoa Nguyen <[email protected]>
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‎drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7KA8P1KF_core0.h

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‎drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7KA8P1KF_core1.h

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‎drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h

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#include "R7FA8M1AH.h"
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#elif BSP_MCU_GROUP_RA8D1
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#include "R7FA8D1BH.h"
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#elif BSP_MCU_GROUP_RA8P1
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#if 0U == BSP_CFG_CPU_CORE
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#include "R7KA8P1KF_core0.h"
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#elif 1U == BSP_CFG_CPU_CORE
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#include "R7KA8P1KF_core1.h"
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#else
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#warning "Unsupported CPU number"
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#endif
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#elif BSP_MCU_GROUP_RA8T1
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#include "R7FA8T1AH.h"
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#elif BSP_MCU_GROUP_RA8E1

‎drivers/ra/fsp/src/bsp/mcu/ra8p1/bsp_elc.h

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‎drivers/ra/fsp/src/bsp/mcu/ra8p1/bsp_feature.h

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‎drivers/ra/fsp/src/bsp/mcu/ra8p1/bsp_mcu_info.h

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/*
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* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*******************************************************************************************************************//**
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* @ingroup BSP_MCU
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* @defgroup BSP_MCU_RA8P1 RA8P1
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* @{
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**********************************************************************************************************************/
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// RA8P1_TODO: includedoc config_bsp_ra8p1_fsp.html
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/** @} (end defgroup BSP_MCU_RA8P1) */
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#ifndef BSP_MCU_INFO_H
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#define BSP_MCU_INFO_H
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/***********************************************************************************************************************
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* Includes <System Includes> , "Project Includes"
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**********************************************************************************************************************/
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/* BSP MCU Specific Includes. */
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#include "bsp_elc.h"
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#include "bsp_feature.h"
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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typedef elc_event_t bsp_interrupt_event_t;
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/***********************************************************************************************************************
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* Exported global variables
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Exported global functions (to be accessed by other files)
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**********************************************************************************************************************/
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#endif

‎drivers/ra/fsp/src/bsp/mcu/ra8p1/bsp_override.h

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/*
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* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*******************************************************************************************************************//**
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* @addtogroup BSP_MCU_RA8P1
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* @{
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**********************************************************************************************************************/
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/** @} (end addtogroup BSP_MCU_RA8P1) */
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#ifndef BSP_OVERRIDE_H
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#define BSP_OVERRIDE_H
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/***********************************************************************************************************************
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* Includes <System Includes> , "Project Includes"
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**********************************************************************************************************************/
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#if __has_include("r_lpm_device_types.h")
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#include "r_lpm_device_types.h"
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#endif
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/* Define overrides required for this MCU. */
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#define BSP_OVERRIDE_CGC_DIVIDER_CFG_T
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#define BSP_OVERRIDE_CGC_SYS_CLOCK_DIV_T
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#define BSP_OVERRIDE_GROUP_IRQ_T
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#define BSP_OVERRIDE_IOPORT_PERIPHERAL_T
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#define BSP_OVERRIDE_LVD_PERIPHERAL_T
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/* Override definitions. */
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/* Private definition to set enumeration values. */
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#define IOPORT_PRV_PFS_PSEL_OFFSET (24)
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/***********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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/** System clock divider values - The individually selectable divider of each of the system clocks, ICLK, BCLK, FCLK,
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* PCLKS A-D. */
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typedef enum e_cgc_sys_clock_div
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{
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CGC_SYS_CLOCK_DIV_1 = 0, ///< System clock divided by 1
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CGC_SYS_CLOCK_DIV_2 = 1, ///< System clock divided by 2
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CGC_SYS_CLOCK_DIV_4 = 2, ///< System clock divided by 4
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CGC_SYS_CLOCK_DIV_8 = 3, ///< System clock divided by 8
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CGC_SYS_CLOCK_DIV_16 = 4, ///< System clock divided by 16
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CGC_SYS_CLOCK_DIV_32 = 5, ///< System clock divided by 32
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CGC_SYS_CLOCK_DIV_64 = 6, ///< System clock divided by 64
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CGC_SYS_CLOCK_DIV_3 = 8, ///< System clock divided by 3
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CGC_SYS_CLOCK_DIV_6 = 9, ///< System clock divided by 6
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CGC_SYS_CLOCK_DIV_12 = 10, ///< System clock divided by 12
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CGC_SYS_CLOCK_DIV_24 = 11, ///< System clock divided by 24
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} cgc_sys_clock_div_t;
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/** Clock configuration structure - Used as an input parameter to the @ref cgc_api_t::systemClockSet and @ref cgc_api_t::systemClockGet
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* functions. */
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typedef struct st_cgc_divider_cfg
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{
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union
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{
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uint32_t sckdivcr_w; ///< System clock Division control register
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struct
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{
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cgc_sys_clock_div_t pclkd_div : 4; ///< Divider value for PCLKD
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cgc_sys_clock_div_t pclkc_div : 4; ///< Divider value for PCLKC
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cgc_sys_clock_div_t pclkb_div : 4; ///< Divider value for PCLKB
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cgc_sys_clock_div_t pclka_div : 4; ///< Divider value for PCLKA
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cgc_sys_clock_div_t bclk_div : 4; ///< Divider value for BCLK
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cgc_sys_clock_div_t pclke_div : 4; ///< Divider value for PCLKE
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cgc_sys_clock_div_t iclk_div : 4; ///< Divider value for ICLK
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cgc_sys_clock_div_t fclk_div : 4; ///< Divider value for FCLK
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} sckdivcr_b;
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};
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union
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{
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uint16_t sckdivcr2; ///< System clock Division control register 2
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struct
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{
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cgc_sys_clock_div_t cpuclk_div : 4; ///< Divider value for CPUCLK0
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cgc_sys_clock_div_t cpuclk1_div : 4; ///< Divider value for CPUCLK1
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cgc_sys_clock_div_t npuclk_div : 4; ///< Divider value for NPUCLK
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cgc_sys_clock_div_t mriclk_div : 4; ///< Divider value for MRICLK
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} sckdivcr2_b;
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};
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} cgc_divider_cfg_t;
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/* Which interrupts can have callbacks registered. */
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typedef enum e_bsp_grp_irq
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{
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BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred
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BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred
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BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt
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BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt
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BSP_GRP_IRQ_SOSC_STOP_DETECT = 5, ///< Sub Oscillation stop is detected
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BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected
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BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt
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BSP_GRP_IRQ_MPU_BUS_TZF = 12, ///< MPU Bus or TrustZone Filter Error
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BSP_GRP_IRQ_COMMON_MEMORY = 13, ///< SRAM ECC or SRAM Parity Error
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BSP_GRP_IRQ_LOCAL_MEMORY = 14, ///< Local Memory Error
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BSP_GRP_IRQ_LOCKUP = 15, ///< LockUp Error
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BSP_GRP_IRQ_FPU = 16, ///< FPU Exception
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BSP_GRP_IRQ_MRC = 17, ///< MRAM Code read error
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BSP_GRP_IRQ_MRE = 18, ///< MRAM Extra read error
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BSP_GRP_IRQ_IPC = 20, ///< IPC Interrupt
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} bsp_grp_irq_t;
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/** Superset of all peripheral functions. */
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typedef enum e_ioport_peripheral
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{
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/** Pin will functions as an IO pin */
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IOPORT_PERIPHERAL_IO = 0x00,
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/** Pin will function as a DEBUG pin */
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IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as an AGT peripheral pin */
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IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as an AGT peripheral pin */
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IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as an AGT peripheral pin */
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IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a GPT peripheral pin */
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IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a GPT peripheral pin */
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IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as an SCI peripheral pin */
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IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as an SCI peripheral pin */
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IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a SPI peripheral pin */
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IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a IIC peripheral pin */
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IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a KEY peripheral pin */
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IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a clock/comparator/RTC peripheral pin */
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IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a CAC/ADC peripheral pin */
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IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a BUS peripheral pin */
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IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a CTSU peripheral pin */
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IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a CMPHS peripheral pin */
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IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a segment LCD peripheral pin */
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IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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#if BSP_FEATURE_SCI_UART_DE_IS_INVERTED
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/** Pin will function as an SCI peripheral DEn pin */
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IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as an SCI DEn peripheral pin */
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IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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#else
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/** Pin will function as an SCI peripheral DEn pin */
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IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as an SCI DEn peripheral pin */
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IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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#endif
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/** Pin will function as a DALI peripheral pin */
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IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a CEU peripheral pin */
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IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a CAN peripheral pin */
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IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a QSPI peripheral pin */
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IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as an SSI peripheral pin */
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IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a USB full speed peripheral pin */
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IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a USB high speed peripheral pin */
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IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a GPT peripheral pin */
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IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as an SD/MMC peripheral pin */
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IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a GPT peripheral pin */
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IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as an Ethernet MMI peripheral pin */
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IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a GPT peripheral pin */
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IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as an Ethernet RMMI peripheral pin */
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IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a PDC peripheral pin */
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IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a graphics LCD peripheral pin */
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IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a CAC peripheral pin */
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IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a debug trace peripheral pin */
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IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a OSPI peripheral pin */
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IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a CEC peripheral pin */
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IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a PGAOUT peripheral pin */
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IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a PGAOUT peripheral pin */
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IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a ULPT peripheral pin */
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IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a MIPI DSI peripheral pin */
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IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a RGMII peripheral pin */
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IOPORT_PERIPHERAL_ETHER_RGMII = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a ETHERNET slave controller peripheral pin */
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IOPORT_PERIPHERAL_ESC = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a PDM peripheral pin */
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IOPORT_PERIPHERAL_PDM = (0x1BUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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} ioport_peripheral_t;
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/** The thresholds supported by each MCU are in the MCU User's Manual as well as
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* in the r_lvd module description on the stack tab of the RA project. */
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typedef enum
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{
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LVD_THRESHOLD_MONITOR_LEVEL_3_86V = 0x03UL, ///< 3.86V
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LVD_THRESHOLD_MONITOR_LEVEL_3_14V = 0x04UL, ///< 3.14V
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LVD_THRESHOLD_MONITOR_LEVEL_3_10V = 0x05UL, ///< 3.10V
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LVD_THRESHOLD_MONITOR_LEVEL_3_08V = 0x06UL, ///< 3.08V
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LVD_THRESHOLD_MONITOR_LEVEL_2_85V = 0x07UL, ///< 2.85V
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LVD_THRESHOLD_MONITOR_LEVEL_2_83V = 0x08UL, ///< 2.83V
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LVD_THRESHOLD_MONITOR_LEVEL_2_80V = 0x09UL, ///< 2.80V
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LVD_THRESHOLD_MONITOR_LEVEL_2_62V = 0x0AUL, ///< 2.62V
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LVD_THRESHOLD_MONITOR_LEVEL_2_33V = 0x0BUL, ///< 2.33V
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LVD_THRESHOLD_MONITOR_LEVEL_1_90V = 0x0CUL, ///< 1.90V
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LVD_THRESHOLD_MONITOR_LEVEL_1_86V = 0x0DUL, ///< 1.86V
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LVD_THRESHOLD_MONITOR_LEVEL_1_74V = 0x0EUL, ///< 1.74V
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LVD_THRESHOLD_MONITOR_LEVEL_1_71V = 0x0FUL, ///< 1.71V
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LVD_THRESHOLD_NOT_AVAILABLE = 0xFFUL, ///< Not Used
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} lvd_threshold_t;
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/***********************************************************************************************************************
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* Exported global variables
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Exported global functions (to be accessed by other files)
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**********************************************************************************************************************/
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#endif

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