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Hieu NguyenKhiemNguyenT
Hieu Nguyen
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KhiemNguyenT
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hal: renesas: rz: Add initial support for RZ/T
This is the initial HAL support for RZ/T series. The HAL support for RZ/T is based on RZ/T FSP Signed-off-by: Hieu Nguyen <[email protected]> Signed-off-by: Nhut Nguyen <[email protected]>
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‎drivers/rz/fsp/src/rzt/bsp/cmsis/Device/RENESAS/Include/R9A07G075.h

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‎drivers/rz/fsp/src/rzt/bsp/mcu/rzt2m/bsp_elc.h

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‎drivers/rz/fsp/src/rzt/bsp/mcu/rzt2m/bsp_feature.h

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‎drivers/rz/fsp/src/rzt/bsp/mcu/rzt2m/bsp_mcu_info.h

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*******************************************************************************************************************//**
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* @ingroup BSP_MCU
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* @defgroup BSP_MCU_RZT2M RZT2M
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* @includedoc config_bsp_rzt2m_fsp.html
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* @{
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**********************************************************************************************************************/
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/** @} (end defgroup BSP_MCU_RZT2M) */
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#ifndef BSP_MCU_INFO_H
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#define BSP_MCU_INFO_H
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/***********************************************************************************************************************
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* Includes <System Includes> , "Project Includes"
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**********************************************************************************************************************/
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/* BSP MCU Specific Includes. */
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#include "bsp_elc.h"
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#include "bsp_feature.h"
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/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
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FSP_HEADER
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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typedef elc_event_t bsp_interrupt_event_t;
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/***********************************************************************************************************************
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* Exported global variables
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Exported global functions (to be accessed by other files)
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**********************************************************************************************************************/
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/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
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FSP_FOOTER
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#endif

‎zephyr/rz/rz_cfg/fsp_cfg/bsp/rzt2m/bsp_cfg.h

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BSP_CFG_H_
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#define BSP_CFG_H_
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_family_cfg.h"
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#ifndef BSP_CFG_RTOS
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#define BSP_CFG_RTOS (0)
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#endif
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#define BSP_CFG_MCU_VCC_MV (3300)
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#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
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#define BSP_CFG_ASSERT (0)
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#define BSP_CFG_ERROR_LOG (0)
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#define BSP_CFG_PORT_PROTECT (1)
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#define BSP_CFG_SOFT_RESET_SUPPORTED (0)
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#define BSP_CFG_EARLY_INIT (0)
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#define BSP_CFG_MULTIPLEX_INTERRUPT_SUPPORTED (0)
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#if BSP_CFG_MULTIPLEX_INTERRUPT_SUPPORTED
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#define BSP_CFG_MULTIPLEX_INTERRUPT_ENABLE BSP_INTERRUPT_ENABLE
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#define BSP_CFG_MULTIPLEX_INTERRUPT_DISABLE BSP_INTERRUPT_DISABLE
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#else
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#define BSP_CFG_MULTIPLEX_INTERRUPT_ENABLE
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#define BSP_CFG_MULTIPLEX_INTERRUPT_DISABLE
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#endif
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#endif /* BSP_CFG_H_ */

‎zephyr/rz/rz_cfg/fsp_cfg/bsp/rzt2m/bsp_clock_cfg.h

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BSP_CLOCK_CFG_H_
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#define BSP_CLOCK_CFG_H_
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#define BSP_CFG_CLOCKS_SECURE (0)
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#define BSP_CFG_CLOCKS_OVERRIDE (0)
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#define BSP_CFG_MAIN_CLOCK_HZ (25000000) /* Main Clock: 25MHz */
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#define BSP_CFG_LOCO_ENABLE (BSP_CLOCKS_LOCO_ENABLE) /* LOCO Enabled */
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#define BSP_CFG_PLL1 (BSP_CLOCKS_PLL1_INITIAL) /* PLL1 is initial state */
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#define BSP_CFG_PHYSEL (BSP_CLOCKS_PHYSEL_PLL1_DIV) /* Ethernet Clock src: PLL1 divider clock */
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#define BSP_CFG_CLMA0_ENABLE (BSP_CLOCKS_CLMA0_ENABLE) /* CLMA0 Enabled */
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#define BSP_CFG_CLMA0MASK (BSP_CLOCKS_CLMA0_ERROR_NOT_MASK) /* CLMA0 error not mask */
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#define BSP_CFG_CLMA3MASK (BSP_CLOCKS_CLMA3_ERROR_NOT_MASK) /* CLMA3 error not mask */
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#define BSP_CFG_CLMA1MASK (BSP_CLOCKS_CLMA1_ERROR_MASK) /* CLMA1 error mask */
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#define BSP_CFG_CLMA3_ENABLE (BSP_CLOCKS_CLMA3_ENABLE) /* CLMA3 Enabled */
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#define BSP_CFG_CLMA1_ENABLE (BSP_CLOCKS_CLMA1_ENABLE) /* CLMA1 Enabled */
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#define BSP_CFG_CLMA2_ENABLE (BSP_CLOCKS_CLMA2_ENABLE) /* CLMA2 Enabled */
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#define BSP_CFG_CLMA0_CMPL (1) /* CLMA0 CMPL 1 */
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#define BSP_CFG_CLMA1_CMPL (1) /* CLMA1 CMPL 1 */
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#define BSP_CFG_CLMA2_CMPL (1) /* CLMA2 CMPL 1 */
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#define BSP_CFG_CLMA3_CMPL (1) /* CLMA3 CMPL 1 */
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#define BSP_CFG_CLMASEL (BSP_CLOCKS_CLMASEL_LOCO) /* Alternative clock: LOCO */
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#define BSP_CFG_CLMA0_CMPH (1023) /* CLMA0 CMPH 1023 */
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#define BSP_CFG_CLMA1_CMPH (1023) /* CLMA1 CMPH 1023 */
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#define BSP_CFG_CLMA2_CMPH (1023) /* CLMA2 CMPH 1023 */
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#define BSP_CFG_CLMA3_CMPH (1023) /* CLMA3 CMPH 1023 */
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#define BSP_CFG_DIVSELSUB (BSP_CLOCKS_DIVSELSUB_0) /* ICLK 200MHz */
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#define BSP_CFG_SCI0ASYNCCLK (BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI0ASYNCCLK: 96MHz */
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#define BSP_CFG_SCI1ASYNCCLK (BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI1ASYNCCLK: 96MHz */
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#define BSP_CFG_SCI2ASYNCCLK (BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI2ASYNCCLK: 96MHz */
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#define BSP_CFG_SCI3ASYNCCLK (BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI3ASYNCCLK: 96MHz */
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#define BSP_CFG_SCI4ASYNCCLK (BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI4ASYNCCLK: 96MHz */
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#define BSP_CFG_SCI5ASYNCCLK (BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI5ASYNCCLK: 96MHz */
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#define BSP_CFG_SPI0ASYNCCLK (BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI0ASYNCCLK: 96MHz */
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#define BSP_CFG_SPI1ASYNCCLK (BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI1ASYNCCLK: 96MHz */
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#define BSP_CFG_SPI2ASYNCCLK (BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI2ASYNCCLK: 96MHz */
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#define BSP_CFG_SPI3ASYNCCLK (BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI3ASYNCCLK: 96MHz */
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#define BSP_CFG_FSELCPU0 (BSP_CLOCKS_FSELCPU0_ICLK_MUL1) /* CPU0CLK Mul x1 */
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#define BSP_CFG_FSELCPU1 (BSP_CLOCKS_FSELCPU1_ICLK_MUL1) /* CPU1CLK Mul x1 */
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#define BSP_CFG_CKIO (BSP_CLOCKS_CKIO_ICLK_DIV4) /* CKIO Div /4 */
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#define BSP_CFG_FSELCANFD (BSP_CLOCKS_CANFD_CLOCK_40_MHZ) /* CANFDCLK Src: PCLKCAN 40MHz */
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#define BSP_CFG_FSELXSPI0_DIVSELXSPI0 (BSP_CLOCKS_XSPI0_CLOCK_DIV0_12_5_MHZ) /* XSPI_CLK0 12.5MHz */
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#define BSP_CFG_FSELXSPI1_DIVSELXSPI1 (BSP_CLOCKS_XSPI1_CLOCK_DIV0_12_5_MHZ) /* XSPI_CLK1 12.5MHz */
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#endif /* BSP_CLOCK_CFG_H_ */

‎zephyr/rz/rz_cfg/fsp_cfg/bsp/rzt2m/bsp_mcu_device_cfg.h

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BSP_MCU_DEVICE_CFG_H_
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#define BSP_MCU_DEVICE_CFG_H_
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#define BSP_CFG_STACK_FIQ_BYTES (0x1000)
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#define BSP_CFG_STACK_IRQ_BYTES (0x1000)
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#define BSP_CFG_STACK_ABT_BYTES (0x1000)
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#define BSP_CFG_STACK_UND_BYTES (0x1000)
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#define BSP_CFG_STACK_SYS_BYTES (0x1000)
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#define BSP_CFG_STACK_SVC_BYTES (0x1000)
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#define BSP_CFG_HEAP_BYTES (0x8000)
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#define BSP_CFG_C_RUNTIME_INIT (1)
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#define BSP_CFG_USE_TFU_MATHLIB ((1))
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#endif /* BSP_MCU_DEVICE_CFG_H_ */

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