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soburisoburi
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hal: renesas: Replace the BSP clock settings with new macros.
To simplify the DeviceTree notation, we have introduced macros that derive BSP macro definitions from DeviceTree values. The clock settings were rewritten by it.
1 parent 7872e93 commit 33ff5b7

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17 files changed

+433
-680
lines changed

17 files changed

+433
-680
lines changed

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2a1/bsp_clock_cfg.h‎

Lines changed: 14 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
/*
2-
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3-
* Copyright (c) 2024 TOKITA Hiroshi
4-
*
5-
* SPDX-License-Identifier: BSD-3-Clause
6-
*/
2+
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3+
* Copyright (c) 2024 TOKITA Hiroshi
4+
*
5+
* SPDX-License-Identifier: BSD-3-Clause
6+
*/
77

88
#include <zephyr/devicetree.h>
99
#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
@@ -14,7 +14,7 @@
1414
#define BSP_CFG_CLOCKS_SECURE (0)
1515
#define BSP_CFG_CLOCKS_OVERRIDE (0)
1616

17-
#define BSP_CFG_XTAL_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0)
17+
#define BSP_CFG_XTAL_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0))
1818

1919
#if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 24000000
2020
#define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 24MHz */
@@ -27,19 +27,13 @@
2727
#else
2828
#error "Invalid HOCO frequency, only can be set to 24MHz, 32MHz, 48MHz, 64MHz"
2929
#endif
30-
#define BSP_CFG_CLOCK_SOURCE \
31-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \
32-
RA_PLL_SOURCE_DISABLE)
33-
#define BSP_CFG_ICLK_DIV \
34-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), clk_div, RA_SYS_CLOCK_DIV_1)
35-
#define BSP_CFG_PCLKB_DIV \
36-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), clk_div, RA_SYS_CLOCK_DIV_2)
37-
#define BSP_CFG_PCLKD_DIV \
38-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), clk_div, RA_SYS_CLOCK_DIV_1)
39-
#define BSP_CFG_FCLK_DIV \
40-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(fclk), clk_div, RA_SYS_CLOCK_DIV_2)
41-
#define BSP_CFG_CLKOUT_SOURCE \
42-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_src, RA_CLOCK_SOURCE_DISABLE)
43-
#define BSP_CFG_CLKOUT_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_div, 0)
30+
31+
#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))
32+
#define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 1)
33+
#define BSP_CFG_PCLKB_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkb), div, 2)
34+
#define BSP_CFG_PCLKD_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkd), div, 1)
35+
#define BSP_CFG_FCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(fclk), div, 2)
36+
#define BSP_CFG_CLKOUT_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(clkout)))
37+
#define BSP_CFG_CLKOUT_DIV RA_CGC_CLK_DIV(DT_NODELABEL(clkout), div, 1)
4438

4539
#endif /* BSP_CLOCK_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2l1/bsp_clock_cfg.h‎

Lines changed: 11 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/*
2-
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3-
*
4-
* SPDX-License-Identifier: BSD-3-Clause
5-
*/
2+
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3+
*
4+
* SPDX-License-Identifier: BSD-3-Clause
5+
*/
66

77
#include <zephyr/devicetree.h>
88
#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
@@ -13,7 +13,7 @@
1313
#define BSP_CFG_CLOCKS_SECURE (0)
1414
#define BSP_CFG_CLOCKS_OVERRIDE (0)
1515

16-
#define BSP_CFG_XTAL_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0)
16+
#define BSP_CFG_XTAL_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0))
1717

1818
#if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 24000000
1919
#define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 24MHz */
@@ -27,19 +27,13 @@
2727
#error "Invalid HOCO frequency, only can be set to 24MHz, 32MHz, 48MHz, 64MHz"
2828
#endif
2929

30-
#define BSP_CFG_CLOCK_SOURCE \
31-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \
32-
RA_CLOCK_SOURCE_DISABLE)
30+
#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))
3331

34-
#define BSP_CFG_ICLK_DIV \
35-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), clk_div, RA_SYS_CLOCK_DIV_2)
36-
#define BSP_CFG_PCLKB_DIV \
37-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), clk_div, RA_SYS_CLOCK_DIV_2)
38-
#define BSP_CFG_PCLKD_DIV \
39-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), clk_div, RA_SYS_CLOCK_DIV_1)
32+
#define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
33+
#define BSP_CFG_PCLKB_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkb), div, 2)
34+
#define BSP_CFG_PCLKD_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkd), div, 1)
4035

41-
#define BSP_CFG_CLKOUT_SOURCE \
42-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_src, RA_CLOCK_SOURCE_DISABLE)
43-
#define BSP_CFG_CLKOUT_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_div, 0)
36+
#define BSP_CFG_CLKOUT_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(clkout)))
37+
#define BSP_CFG_CLKOUT_DIV RA_CGC_CLK_DIV(DT_NODELABEL(clkout), div, 1)
4438

4539
#endif /* BSP_CLOCK_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e2/bsp_clock_cfg.h‎

Lines changed: 24 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
#define BSP_CFG_CLOCKS_SECURE (0)
1414
#define BSP_CFG_CLOCKS_OVERRIDE (0)
1515

16-
#define BSP_CFG_XTAL_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0)
16+
#define BSP_CFG_XTAL_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0))
1717

1818
#if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 16000000
1919
#define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 16MHz */
@@ -25,49 +25,34 @@
2525
#error "Invalid HOCO frequency, only can be set to 16MHz, 18MHz, and 20MHz"
2626
#endif
2727

28-
29-
#define BSP_CFG_PLL_SOURCE \
30-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
31-
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_1)
28+
#define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll)))
29+
#define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 1)
3230
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
3331
#define BSP_CFG_PLL_MUL \
34-
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
35-
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
32+
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
33+
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
3634
#else
3735
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
3836
#endif
3937

40-
#define BSP_CFG_CLOCK_SOURCE \
41-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \
42-
RA_PLL_SOURCE_DISABLE)
43-
44-
#define BSP_CFG_ICLK_DIV \
45-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), clk_div, RA_SYS_CLOCK_DIV_2)
46-
#define BSP_CFG_PCLKA_DIV \
47-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclka), clk_div, RA_SYS_CLOCK_DIV_2)
48-
#define BSP_CFG_PCLKB_DIV \
49-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), clk_div, RA_SYS_CLOCK_DIV_4)
50-
#define BSP_CFG_PCLKC_DIV \
51-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkc), clk_div, RA_SYS_CLOCK_DIV_4)
52-
#define BSP_CFG_PCLKD_DIV \
53-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), clk_div, RA_SYS_CLOCK_DIV_2)
54-
#define BSP_CFG_FCLK_DIV \
55-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(fclk), clk_div, RA_SYS_CLOCK_DIV_4)
56-
57-
#define BSP_CFG_UCK_SOURCE \
58-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
59-
#define BSP_CFG_UCK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_div, 0)
60-
#define BSP_CFG_CLKOUT_SOURCE \
61-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_src, RA_CLOCK_SOURCE_DISABLE)
62-
#define BSP_CFG_CLKOUT_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_div, 0)
63-
#define BSP_CFG_I3CCLK_SOURCE \
64-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(i3cclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
65-
#define BSP_CFG_I3CCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(i3cclk), clk_div, 0)
66-
#define BSP_CFG_CECCLK_SOURCE \
67-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(cecclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
68-
#define BSP_CFG_CECCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(cecclk), clk_div, 0)
69-
#define BSP_CFG_CANFDCLK_SOURCE \
70-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(canfdclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
71-
#define BSP_CFG_CANFDCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(canfdclk), clk_div, 0)
38+
#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))
39+
40+
#define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
41+
#define BSP_CFG_PCLKA_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclka), div, 2)
42+
#define BSP_CFG_PCLKB_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkb), div, 4)
43+
#define BSP_CFG_PCLKC_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkc), div, 4)
44+
#define BSP_CFG_PCLKD_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkd), div, 2)
45+
#define BSP_CFG_FCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(fclk), div, 4)
46+
47+
#define BSP_CFG_UCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(uclk)))
48+
#define BSP_CFG_UCK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(uclk), div, 1)
49+
#define BSP_CFG_CLKOUT_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(clkout)))
50+
#define BSP_CFG_CLKOUT_DIV RA_CGC_CLK_DIV(DT_NODELABEL(clkout), div, 1)
51+
#define BSP_CFG_I3CCLK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(i3cclk)))
52+
#define BSP_CFG_I3CCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(i3cclk), div, 1)
53+
#define BSP_CFG_CECCLK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(cecclk)))
54+
#define BSP_CFG_CECCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(cecclk), div, 1)
55+
#define BSP_CFG_CANFDCLK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(canfdclk)))
56+
#define BSP_CFG_CANFDCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(canfdclk), div, 1)
7257

7358
#endif /* BSP_CLOCK_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/bsp_clock_cfg.h‎

Lines changed: 17 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -10,11 +10,10 @@
1010
#ifndef BSP_CLOCK_CFG_H_
1111
#define BSP_CLOCK_CFG_H_
1212

13-
#define BSP_CFG_CLOCKS_SECURE (0)
13+
#define BSP_CFG_CLOCKS_SECURE (0)
1414
#define BSP_CFG_CLOCKS_OVERRIDE (0)
1515

16-
17-
#define BSP_CFG_XTAL_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0)
16+
#define BSP_CFG_XTAL_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0))
1817

1918
#if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 24000000
2019
#define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 24MHz */
@@ -28,39 +27,28 @@
2827
#error "Invalid HOCO frequency, only can be set to 24MHz, 32MHz, 48MHz and 64MHz"
2928
#endif
3029

31-
#define BSP_CFG_PLL_SOURCE \
32-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
33-
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_2)
30+
#define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll)))
31+
#define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 2)
3432
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
3533
#define BSP_CFG_PLL_MUL \
36-
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
37-
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
34+
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
35+
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
3836
#else
3937
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
4038
#endif
4139

42-
#define BSP_CFG_CLOCK_SOURCE \
43-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \
44-
RA_PLL_SOURCE_DISABLE)
40+
#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))
4541

46-
#define BSP_CFG_ICLK_DIV \
47-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), clk_div, RA_SYS_CLOCK_DIV_1)
48-
#define BSP_CFG_PCLKA_DIV \
49-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclka), clk_div, RA_SYS_CLOCK_DIV_1)
50-
#define BSP_CFG_PCLKB_DIV \
51-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), clk_div, RA_SYS_CLOCK_DIV_2)
52-
#define BSP_CFG_PCLKC_DIV \
53-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkc), clk_div, RA_SYS_CLOCK_DIV_1)
54-
#define BSP_CFG_PCLKD_DIV \
55-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), clk_div, RA_SYS_CLOCK_DIV_1)
56-
#define BSP_CFG_FCLK_DIV \
57-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(fclk), clk_div, RA_SYS_CLOCK_DIV_2)
42+
#define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 1)
43+
#define BSP_CFG_PCLKA_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclka), div, 1)
44+
#define BSP_CFG_PCLKB_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkb), div, 2)
45+
#define BSP_CFG_PCLKC_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkc), div, 1)
46+
#define BSP_CFG_PCLKD_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkd), div, 1)
47+
#define BSP_CFG_FCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(fclk), div, 2)
5848

59-
#define BSP_CFG_UCK_SOURCE \
60-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
61-
#define BSP_CFG_UCK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_div, 0)
62-
#define BSP_CFG_CLKOUT_SOURCE \
63-
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_src, RA_CLOCK_SOURCE_DISABLE)
64-
#define BSP_CFG_CLKOUT_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_div, 0)
49+
#define BSP_CFG_UCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(uclk)))
50+
#define BSP_CFG_UCK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(uclk), div, 1)
51+
#define BSP_CFG_CLKOUT_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(clkout)))
52+
#define BSP_CFG_CLKOUT_DIV RA_CGC_CLK_DIV(DT_NODELABEL(clkout), div, 1)
6553

6654
#endif /* BSP_CLOCK_CFG_H_ */

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